1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max); 144 145 return ret; 146 } 147 148 int smu_get_dpm_freq_range(struct smu_context *smu, 149 enum smu_clk_type clk_type, 150 uint32_t *min, 151 uint32_t *max) 152 { 153 int ret = -ENOTSUPP; 154 155 if (!min && !max) 156 return -EINVAL; 157 158 if (smu->ppt_funcs->get_dpm_ultimate_freq) 159 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 160 clk_type, 161 min, 162 max); 163 164 return ret; 165 } 166 167 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 168 { 169 int ret = 0; 170 struct amdgpu_device *adev = smu->adev; 171 172 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 173 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 174 if (ret) 175 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 176 } 177 return ret; 178 } 179 180 static u32 smu_get_mclk(void *handle, bool low) 181 { 182 struct smu_context *smu = handle; 183 uint32_t clk_freq; 184 int ret = 0; 185 186 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 187 low ? &clk_freq : NULL, 188 !low ? &clk_freq : NULL); 189 if (ret) 190 return 0; 191 return clk_freq * 100; 192 } 193 194 static u32 smu_get_sclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static int smu_set_gfx_imu_enable(struct smu_context *smu) 209 { 210 struct amdgpu_device *adev = smu->adev; 211 212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 213 return 0; 214 215 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 216 return 0; 217 218 return smu_set_gfx_power_up_by_imu(smu); 219 } 220 221 static bool is_vcn_enabled(struct amdgpu_device *adev) 222 { 223 int i; 224 225 for (i = 0; i < adev->num_ip_blocks; i++) { 226 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 227 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 228 !adev->ip_blocks[i].status.valid) 229 return false; 230 } 231 232 return true; 233 } 234 235 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 236 bool enable) 237 { 238 struct smu_power_context *smu_power = &smu->smu_power; 239 struct smu_power_gate *power_gate = &smu_power->power_gate; 240 int ret = 0; 241 242 /* 243 * don't poweron vcn/jpeg when they are skipped. 244 */ 245 if (!is_vcn_enabled(smu->adev)) 246 return 0; 247 248 if (!smu->ppt_funcs->dpm_set_vcn_enable) 249 return 0; 250 251 if (atomic_read(&power_gate->vcn_gated) ^ enable) 252 return 0; 253 254 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 255 if (!ret) 256 atomic_set(&power_gate->vcn_gated, !enable); 257 258 return ret; 259 } 260 261 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 262 bool enable) 263 { 264 struct smu_power_context *smu_power = &smu->smu_power; 265 struct smu_power_gate *power_gate = &smu_power->power_gate; 266 int ret = 0; 267 268 if (!is_vcn_enabled(smu->adev)) 269 return 0; 270 271 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 272 return 0; 273 274 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 275 return 0; 276 277 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 278 if (!ret) 279 atomic_set(&power_gate->jpeg_gated, !enable); 280 281 return ret; 282 } 283 284 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 285 bool enable) 286 { 287 struct smu_power_context *smu_power = &smu->smu_power; 288 struct smu_power_gate *power_gate = &smu_power->power_gate; 289 int ret = 0; 290 291 if (!smu->ppt_funcs->dpm_set_vpe_enable) 292 return 0; 293 294 if (atomic_read(&power_gate->vpe_gated) ^ enable) 295 return 0; 296 297 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 298 if (!ret) 299 atomic_set(&power_gate->vpe_gated, !enable); 300 301 return ret; 302 } 303 304 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 305 bool enable) 306 { 307 struct smu_power_context *smu_power = &smu->smu_power; 308 struct smu_power_gate *power_gate = &smu_power->power_gate; 309 int ret = 0; 310 311 if (!smu->adev->enable_umsch_mm) 312 return 0; 313 314 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 315 return 0; 316 317 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 318 return 0; 319 320 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 321 if (!ret) 322 atomic_set(&power_gate->umsch_mm_gated, !enable); 323 324 return ret; 325 } 326 327 static int smu_set_mall_enable(struct smu_context *smu) 328 { 329 int ret = 0; 330 331 if (!smu->ppt_funcs->set_mall_enable) 332 return 0; 333 334 ret = smu->ppt_funcs->set_mall_enable(smu); 335 336 return ret; 337 } 338 339 /** 340 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 341 * 342 * @handle: smu_context pointer 343 * @block_type: the IP block to power gate/ungate 344 * @gate: to power gate if true, ungate otherwise 345 * 346 * This API uses no smu->mutex lock protection due to: 347 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 348 * This is guarded to be race condition free by the caller. 349 * 2. Or get called on user setting request of power_dpm_force_performance_level. 350 * Under this case, the smu->mutex lock protection is already enforced on 351 * the parent API smu_force_performance_level of the call path. 352 */ 353 static int smu_dpm_set_power_gate(void *handle, 354 uint32_t block_type, 355 bool gate) 356 { 357 struct smu_context *smu = handle; 358 int ret = 0; 359 360 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 361 dev_WARN(smu->adev->dev, 362 "SMU uninitialized but power %s requested for %u!\n", 363 gate ? "gate" : "ungate", block_type); 364 return -EOPNOTSUPP; 365 } 366 367 switch (block_type) { 368 /* 369 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 370 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 371 */ 372 case AMD_IP_BLOCK_TYPE_UVD: 373 case AMD_IP_BLOCK_TYPE_VCN: 374 ret = smu_dpm_set_vcn_enable(smu, !gate); 375 if (ret) 376 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 377 gate ? "gate" : "ungate"); 378 break; 379 case AMD_IP_BLOCK_TYPE_GFX: 380 ret = smu_gfx_off_control(smu, gate); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 383 gate ? "enable" : "disable"); 384 break; 385 case AMD_IP_BLOCK_TYPE_SDMA: 386 ret = smu_powergate_sdma(smu, gate); 387 if (ret) 388 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 389 gate ? "gate" : "ungate"); 390 break; 391 case AMD_IP_BLOCK_TYPE_JPEG: 392 ret = smu_dpm_set_jpeg_enable(smu, !gate); 393 if (ret) 394 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 395 gate ? "gate" : "ungate"); 396 break; 397 case AMD_IP_BLOCK_TYPE_VPE: 398 ret = smu_dpm_set_vpe_enable(smu, !gate); 399 if (ret) 400 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 401 gate ? "gate" : "ungate"); 402 break; 403 default: 404 dev_err(smu->adev->dev, "Unsupported block type!\n"); 405 return -EINVAL; 406 } 407 408 return ret; 409 } 410 411 /** 412 * smu_set_user_clk_dependencies - set user profile clock dependencies 413 * 414 * @smu: smu_context pointer 415 * @clk: enum smu_clk_type type 416 * 417 * Enable/Disable the clock dependency for the @clk type. 418 */ 419 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 420 { 421 if (smu->adev->in_suspend) 422 return; 423 424 if (clk == SMU_MCLK) { 425 smu->user_dpm_profile.clk_dependency = 0; 426 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 427 } else if (clk == SMU_FCLK) { 428 /* MCLK takes precedence over FCLK */ 429 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 430 return; 431 432 smu->user_dpm_profile.clk_dependency = 0; 433 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 434 } else if (clk == SMU_SOCCLK) { 435 /* MCLK takes precedence over SOCCLK */ 436 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 437 return; 438 439 smu->user_dpm_profile.clk_dependency = 0; 440 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 441 } else 442 /* Add clk dependencies here, if any */ 443 return; 444 } 445 446 /** 447 * smu_restore_dpm_user_profile - reinstate user dpm profile 448 * 449 * @smu: smu_context pointer 450 * 451 * Restore the saved user power configurations include power limit, 452 * clock frequencies, fan control mode and fan speed. 453 */ 454 static void smu_restore_dpm_user_profile(struct smu_context *smu) 455 { 456 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 457 int ret = 0; 458 459 if (!smu->adev->in_suspend) 460 return; 461 462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 463 return; 464 465 /* Enable restore flag */ 466 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 467 468 /* set the user dpm power limit */ 469 if (smu->user_dpm_profile.power_limit) { 470 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 471 if (ret) 472 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 473 } 474 475 /* set the user dpm clock configurations */ 476 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 477 enum smu_clk_type clk_type; 478 479 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 480 /* 481 * Iterate over smu clk type and force the saved user clk 482 * configs, skip if clock dependency is enabled 483 */ 484 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 485 smu->user_dpm_profile.clk_mask[clk_type]) { 486 ret = smu_force_smuclk_levels(smu, clk_type, 487 smu->user_dpm_profile.clk_mask[clk_type]); 488 if (ret) 489 dev_err(smu->adev->dev, 490 "Failed to set clock type = %d\n", clk_type); 491 } 492 } 493 } 494 495 /* set the user dpm fan configurations */ 496 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 497 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 498 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 499 if (ret != -EOPNOTSUPP) { 500 smu->user_dpm_profile.fan_speed_pwm = 0; 501 smu->user_dpm_profile.fan_speed_rpm = 0; 502 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 503 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 504 } 505 506 if (smu->user_dpm_profile.fan_speed_pwm) { 507 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 508 if (ret != -EOPNOTSUPP) 509 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 510 } 511 512 if (smu->user_dpm_profile.fan_speed_rpm) { 513 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 514 if (ret != -EOPNOTSUPP) 515 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 516 } 517 } 518 519 /* Restore user customized OD settings */ 520 if (smu->user_dpm_profile.user_od) { 521 if (smu->ppt_funcs->restore_user_od_settings) { 522 ret = smu->ppt_funcs->restore_user_od_settings(smu); 523 if (ret) 524 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 525 } 526 } 527 528 /* Disable restore flag */ 529 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 530 } 531 532 static int smu_get_power_num_states(void *handle, 533 struct pp_states_info *state_info) 534 { 535 if (!state_info) 536 return -EINVAL; 537 538 /* not support power state */ 539 memset(state_info, 0, sizeof(struct pp_states_info)); 540 state_info->nums = 1; 541 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 542 543 return 0; 544 } 545 546 bool is_support_sw_smu(struct amdgpu_device *adev) 547 { 548 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 549 if (adev->asic_type == CHIP_VEGA20) 550 return false; 551 552 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 553 return true; 554 555 return false; 556 } 557 558 bool is_support_cclk_dpm(struct amdgpu_device *adev) 559 { 560 struct smu_context *smu = adev->powerplay.pp_handle; 561 562 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 563 return false; 564 565 return true; 566 } 567 568 569 static int smu_sys_get_pp_table(void *handle, 570 char **table) 571 { 572 struct smu_context *smu = handle; 573 struct smu_table_context *smu_table = &smu->smu_table; 574 575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 576 return -EOPNOTSUPP; 577 578 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 579 return -EINVAL; 580 581 if (smu_table->hardcode_pptable) 582 *table = smu_table->hardcode_pptable; 583 else 584 *table = smu_table->power_play_table; 585 586 return smu_table->power_play_table_size; 587 } 588 589 static int smu_sys_set_pp_table(void *handle, 590 const char *buf, 591 size_t size) 592 { 593 struct smu_context *smu = handle; 594 struct smu_table_context *smu_table = &smu->smu_table; 595 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 596 int ret = 0; 597 598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 599 return -EOPNOTSUPP; 600 601 if (header->usStructureSize != size) { 602 dev_err(smu->adev->dev, "pp table size not matched !\n"); 603 return -EIO; 604 } 605 606 if (!smu_table->hardcode_pptable) { 607 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 608 if (!smu_table->hardcode_pptable) 609 return -ENOMEM; 610 } 611 612 memcpy(smu_table->hardcode_pptable, buf, size); 613 smu_table->power_play_table = smu_table->hardcode_pptable; 614 smu_table->power_play_table_size = size; 615 616 /* 617 * Special hw_fini action(for Navi1x, the DPMs disablement will be 618 * skipped) may be needed for custom pptable uploading. 619 */ 620 smu->uploading_custom_pp_table = true; 621 622 ret = smu_reset(smu); 623 if (ret) 624 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 625 626 smu->uploading_custom_pp_table = false; 627 628 return ret; 629 } 630 631 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 632 { 633 struct smu_feature *feature = &smu->smu_feature; 634 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 635 int ret = 0; 636 637 /* 638 * With SCPM enabled, the allowed featuremasks setting(via 639 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 640 * That means there is no way to let PMFW knows the settings below. 641 * Thus, we just assume all the features are allowed under 642 * such scenario. 643 */ 644 if (smu->adev->scpm_enabled) { 645 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 646 return 0; 647 } 648 649 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 650 651 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 652 SMU_FEATURE_MAX/32); 653 if (ret) 654 return ret; 655 656 bitmap_or(feature->allowed, feature->allowed, 657 (unsigned long *)allowed_feature_mask, 658 feature->feature_num); 659 660 return ret; 661 } 662 663 static int smu_set_funcs(struct amdgpu_device *adev) 664 { 665 struct smu_context *smu = adev->powerplay.pp_handle; 666 667 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 668 smu->od_enabled = true; 669 670 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 671 case IP_VERSION(11, 0, 0): 672 case IP_VERSION(11, 0, 5): 673 case IP_VERSION(11, 0, 9): 674 navi10_set_ppt_funcs(smu); 675 break; 676 case IP_VERSION(11, 0, 7): 677 case IP_VERSION(11, 0, 11): 678 case IP_VERSION(11, 0, 12): 679 case IP_VERSION(11, 0, 13): 680 sienna_cichlid_set_ppt_funcs(smu); 681 break; 682 case IP_VERSION(12, 0, 0): 683 case IP_VERSION(12, 0, 1): 684 renoir_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 5, 0): 687 vangogh_set_ppt_funcs(smu); 688 break; 689 case IP_VERSION(13, 0, 1): 690 case IP_VERSION(13, 0, 3): 691 case IP_VERSION(13, 0, 8): 692 yellow_carp_set_ppt_funcs(smu); 693 break; 694 case IP_VERSION(13, 0, 4): 695 case IP_VERSION(13, 0, 11): 696 smu_v13_0_4_set_ppt_funcs(smu); 697 break; 698 case IP_VERSION(13, 0, 5): 699 smu_v13_0_5_set_ppt_funcs(smu); 700 break; 701 case IP_VERSION(11, 0, 8): 702 cyan_skillfish_set_ppt_funcs(smu); 703 break; 704 case IP_VERSION(11, 0, 2): 705 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 706 arcturus_set_ppt_funcs(smu); 707 /* OD is not supported on Arcturus */ 708 smu->od_enabled = false; 709 break; 710 case IP_VERSION(13, 0, 2): 711 aldebaran_set_ppt_funcs(smu); 712 /* Enable pp_od_clk_voltage node */ 713 smu->od_enabled = true; 714 break; 715 case IP_VERSION(13, 0, 0): 716 case IP_VERSION(13, 0, 10): 717 smu_v13_0_0_set_ppt_funcs(smu); 718 break; 719 case IP_VERSION(13, 0, 6): 720 case IP_VERSION(13, 0, 14): 721 smu_v13_0_6_set_ppt_funcs(smu); 722 /* Enable pp_od_clk_voltage node */ 723 smu->od_enabled = true; 724 break; 725 case IP_VERSION(13, 0, 7): 726 smu_v13_0_7_set_ppt_funcs(smu); 727 break; 728 case IP_VERSION(14, 0, 0): 729 case IP_VERSION(14, 0, 1): 730 smu_v14_0_0_set_ppt_funcs(smu); 731 break; 732 case IP_VERSION(14, 0, 2): 733 case IP_VERSION(14, 0, 3): 734 smu_v14_0_2_set_ppt_funcs(smu); 735 break; 736 default: 737 return -EINVAL; 738 } 739 740 return 0; 741 } 742 743 static int smu_early_init(void *handle) 744 { 745 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 746 struct smu_context *smu; 747 int r; 748 749 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 750 if (!smu) 751 return -ENOMEM; 752 753 smu->adev = adev; 754 smu->pm_enabled = !!amdgpu_dpm; 755 smu->is_apu = false; 756 smu->smu_baco.state = SMU_BACO_STATE_NONE; 757 smu->smu_baco.platform_support = false; 758 smu->smu_baco.maco_support = false; 759 smu->user_dpm_profile.fan_mode = -1; 760 761 mutex_init(&smu->message_lock); 762 763 adev->powerplay.pp_handle = smu; 764 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 765 766 r = smu_set_funcs(adev); 767 if (r) 768 return r; 769 return smu_init_microcode(smu); 770 } 771 772 static int smu_set_default_dpm_table(struct smu_context *smu) 773 { 774 struct amdgpu_device *adev = smu->adev; 775 struct smu_power_context *smu_power = &smu->smu_power; 776 struct smu_power_gate *power_gate = &smu_power->power_gate; 777 int vcn_gate, jpeg_gate; 778 int ret = 0; 779 780 if (!smu->ppt_funcs->set_default_dpm_table) 781 return 0; 782 783 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 784 vcn_gate = atomic_read(&power_gate->vcn_gated); 785 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 786 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 787 788 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 789 ret = smu_dpm_set_vcn_enable(smu, true); 790 if (ret) 791 return ret; 792 } 793 794 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 795 ret = smu_dpm_set_jpeg_enable(smu, true); 796 if (ret) 797 goto err_out; 798 } 799 800 ret = smu->ppt_funcs->set_default_dpm_table(smu); 801 if (ret) 802 dev_err(smu->adev->dev, 803 "Failed to setup default dpm clock tables!\n"); 804 805 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 806 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 807 err_out: 808 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 809 smu_dpm_set_vcn_enable(smu, !vcn_gate); 810 811 return ret; 812 } 813 814 static int smu_apply_default_config_table_settings(struct smu_context *smu) 815 { 816 struct amdgpu_device *adev = smu->adev; 817 int ret = 0; 818 819 ret = smu_get_default_config_table_settings(smu, 820 &adev->pm.config_table); 821 if (ret) 822 return ret; 823 824 return smu_set_config_table(smu, &adev->pm.config_table); 825 } 826 827 static int smu_late_init(void *handle) 828 { 829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 830 struct smu_context *smu = adev->powerplay.pp_handle; 831 int ret = 0; 832 833 smu_set_fine_grain_gfx_freq_parameters(smu); 834 835 if (!smu->pm_enabled) 836 return 0; 837 838 ret = smu_post_init(smu); 839 if (ret) { 840 dev_err(adev->dev, "Failed to post smu init!\n"); 841 return ret; 842 } 843 844 /* 845 * Explicitly notify PMFW the power mode the system in. Since 846 * the PMFW may boot the ASIC with a different mode. 847 * For those supporting ACDC switch via gpio, PMFW will 848 * handle the switch automatically. Driver involvement 849 * is unnecessary. 850 */ 851 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 852 smu_set_ac_dc(smu); 853 854 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 855 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 856 return 0; 857 858 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 859 ret = smu_set_default_od_settings(smu); 860 if (ret) { 861 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 862 return ret; 863 } 864 } 865 866 ret = smu_populate_umd_state_clk(smu); 867 if (ret) { 868 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 869 return ret; 870 } 871 872 ret = smu_get_asic_power_limits(smu, 873 &smu->current_power_limit, 874 &smu->default_power_limit, 875 &smu->max_power_limit, 876 &smu->min_power_limit); 877 if (ret) { 878 dev_err(adev->dev, "Failed to get asic power limits!\n"); 879 return ret; 880 } 881 882 if (!amdgpu_sriov_vf(adev)) 883 smu_get_unique_id(smu); 884 885 smu_get_fan_parameters(smu); 886 887 smu_handle_task(smu, 888 smu->smu_dpm.dpm_level, 889 AMD_PP_TASK_COMPLETE_INIT); 890 891 ret = smu_apply_default_config_table_settings(smu); 892 if (ret && (ret != -EOPNOTSUPP)) { 893 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 894 return ret; 895 } 896 897 smu_restore_dpm_user_profile(smu); 898 899 return 0; 900 } 901 902 static int smu_init_fb_allocations(struct smu_context *smu) 903 { 904 struct amdgpu_device *adev = smu->adev; 905 struct smu_table_context *smu_table = &smu->smu_table; 906 struct smu_table *tables = smu_table->tables; 907 struct smu_table *driver_table = &(smu_table->driver_table); 908 uint32_t max_table_size = 0; 909 int ret, i; 910 911 /* VRAM allocation for tool table */ 912 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 913 ret = amdgpu_bo_create_kernel(adev, 914 tables[SMU_TABLE_PMSTATUSLOG].size, 915 tables[SMU_TABLE_PMSTATUSLOG].align, 916 tables[SMU_TABLE_PMSTATUSLOG].domain, 917 &tables[SMU_TABLE_PMSTATUSLOG].bo, 918 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 919 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 920 if (ret) { 921 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 922 return ret; 923 } 924 } 925 926 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 927 /* VRAM allocation for driver table */ 928 for (i = 0; i < SMU_TABLE_COUNT; i++) { 929 if (tables[i].size == 0) 930 continue; 931 932 /* If one of the tables has VRAM domain restriction, keep it in 933 * VRAM 934 */ 935 if ((tables[i].domain & 936 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 937 AMDGPU_GEM_DOMAIN_VRAM) 938 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 939 940 if (i == SMU_TABLE_PMSTATUSLOG) 941 continue; 942 943 if (max_table_size < tables[i].size) 944 max_table_size = tables[i].size; 945 } 946 947 driver_table->size = max_table_size; 948 driver_table->align = PAGE_SIZE; 949 950 ret = amdgpu_bo_create_kernel(adev, 951 driver_table->size, 952 driver_table->align, 953 driver_table->domain, 954 &driver_table->bo, 955 &driver_table->mc_address, 956 &driver_table->cpu_addr); 957 if (ret) { 958 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 959 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 960 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 961 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 962 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 963 } 964 965 return ret; 966 } 967 968 static int smu_fini_fb_allocations(struct smu_context *smu) 969 { 970 struct smu_table_context *smu_table = &smu->smu_table; 971 struct smu_table *tables = smu_table->tables; 972 struct smu_table *driver_table = &(smu_table->driver_table); 973 974 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 975 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 976 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 977 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 978 979 amdgpu_bo_free_kernel(&driver_table->bo, 980 &driver_table->mc_address, 981 &driver_table->cpu_addr); 982 983 return 0; 984 } 985 986 /** 987 * smu_alloc_memory_pool - allocate memory pool in the system memory 988 * 989 * @smu: amdgpu_device pointer 990 * 991 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 992 * and DramLogSetDramAddr can notify it changed. 993 * 994 * Returns 0 on success, error on failure. 995 */ 996 static int smu_alloc_memory_pool(struct smu_context *smu) 997 { 998 struct amdgpu_device *adev = smu->adev; 999 struct smu_table_context *smu_table = &smu->smu_table; 1000 struct smu_table *memory_pool = &smu_table->memory_pool; 1001 uint64_t pool_size = smu->pool_size; 1002 int ret = 0; 1003 1004 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1005 return ret; 1006 1007 memory_pool->size = pool_size; 1008 memory_pool->align = PAGE_SIZE; 1009 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1010 1011 switch (pool_size) { 1012 case SMU_MEMORY_POOL_SIZE_256_MB: 1013 case SMU_MEMORY_POOL_SIZE_512_MB: 1014 case SMU_MEMORY_POOL_SIZE_1_GB: 1015 case SMU_MEMORY_POOL_SIZE_2_GB: 1016 ret = amdgpu_bo_create_kernel(adev, 1017 memory_pool->size, 1018 memory_pool->align, 1019 memory_pool->domain, 1020 &memory_pool->bo, 1021 &memory_pool->mc_address, 1022 &memory_pool->cpu_addr); 1023 if (ret) 1024 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1025 break; 1026 default: 1027 break; 1028 } 1029 1030 return ret; 1031 } 1032 1033 static int smu_free_memory_pool(struct smu_context *smu) 1034 { 1035 struct smu_table_context *smu_table = &smu->smu_table; 1036 struct smu_table *memory_pool = &smu_table->memory_pool; 1037 1038 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1039 return 0; 1040 1041 amdgpu_bo_free_kernel(&memory_pool->bo, 1042 &memory_pool->mc_address, 1043 &memory_pool->cpu_addr); 1044 1045 memset(memory_pool, 0, sizeof(struct smu_table)); 1046 1047 return 0; 1048 } 1049 1050 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1051 { 1052 struct smu_table_context *smu_table = &smu->smu_table; 1053 struct smu_table *dummy_read_1_table = 1054 &smu_table->dummy_read_1_table; 1055 struct amdgpu_device *adev = smu->adev; 1056 int ret = 0; 1057 1058 if (!dummy_read_1_table->size) 1059 return 0; 1060 1061 ret = amdgpu_bo_create_kernel(adev, 1062 dummy_read_1_table->size, 1063 dummy_read_1_table->align, 1064 dummy_read_1_table->domain, 1065 &dummy_read_1_table->bo, 1066 &dummy_read_1_table->mc_address, 1067 &dummy_read_1_table->cpu_addr); 1068 if (ret) 1069 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1070 1071 return ret; 1072 } 1073 1074 static void smu_free_dummy_read_table(struct smu_context *smu) 1075 { 1076 struct smu_table_context *smu_table = &smu->smu_table; 1077 struct smu_table *dummy_read_1_table = 1078 &smu_table->dummy_read_1_table; 1079 1080 1081 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1082 &dummy_read_1_table->mc_address, 1083 &dummy_read_1_table->cpu_addr); 1084 1085 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1086 } 1087 1088 static int smu_smc_table_sw_init(struct smu_context *smu) 1089 { 1090 int ret; 1091 1092 /** 1093 * Create smu_table structure, and init smc tables such as 1094 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1095 */ 1096 ret = smu_init_smc_tables(smu); 1097 if (ret) { 1098 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1099 return ret; 1100 } 1101 1102 /** 1103 * Create smu_power_context structure, and allocate smu_dpm_context and 1104 * context size to fill the smu_power_context data. 1105 */ 1106 ret = smu_init_power(smu); 1107 if (ret) { 1108 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1109 return ret; 1110 } 1111 1112 /* 1113 * allocate vram bos to store smc table contents. 1114 */ 1115 ret = smu_init_fb_allocations(smu); 1116 if (ret) 1117 return ret; 1118 1119 ret = smu_alloc_memory_pool(smu); 1120 if (ret) 1121 return ret; 1122 1123 ret = smu_alloc_dummy_read_table(smu); 1124 if (ret) 1125 return ret; 1126 1127 ret = smu_i2c_init(smu); 1128 if (ret) 1129 return ret; 1130 1131 return 0; 1132 } 1133 1134 static int smu_smc_table_sw_fini(struct smu_context *smu) 1135 { 1136 int ret; 1137 1138 smu_i2c_fini(smu); 1139 1140 smu_free_dummy_read_table(smu); 1141 1142 ret = smu_free_memory_pool(smu); 1143 if (ret) 1144 return ret; 1145 1146 ret = smu_fini_fb_allocations(smu); 1147 if (ret) 1148 return ret; 1149 1150 ret = smu_fini_power(smu); 1151 if (ret) { 1152 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1153 return ret; 1154 } 1155 1156 ret = smu_fini_smc_tables(smu); 1157 if (ret) { 1158 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1159 return ret; 1160 } 1161 1162 return 0; 1163 } 1164 1165 static void smu_throttling_logging_work_fn(struct work_struct *work) 1166 { 1167 struct smu_context *smu = container_of(work, struct smu_context, 1168 throttling_logging_work); 1169 1170 smu_log_thermal_throttling(smu); 1171 } 1172 1173 static void smu_interrupt_work_fn(struct work_struct *work) 1174 { 1175 struct smu_context *smu = container_of(work, struct smu_context, 1176 interrupt_work); 1177 1178 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1179 smu->ppt_funcs->interrupt_work(smu); 1180 } 1181 1182 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1183 { 1184 struct smu_context *smu = 1185 container_of(work, struct smu_context, swctf_delayed_work.work); 1186 struct smu_temperature_range *range = 1187 &smu->thermal_range; 1188 struct amdgpu_device *adev = smu->adev; 1189 uint32_t hotspot_tmp, size; 1190 1191 /* 1192 * If the hotspot temperature is confirmed as below SW CTF setting point 1193 * after the delay enforced, nothing will be done. 1194 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1195 */ 1196 if (range->software_shutdown_temp && 1197 smu->ppt_funcs->read_sensor && 1198 !smu->ppt_funcs->read_sensor(smu, 1199 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1200 &hotspot_tmp, 1201 &size) && 1202 hotspot_tmp / 1000 < range->software_shutdown_temp) 1203 return; 1204 1205 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1206 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1207 orderly_poweroff(true); 1208 } 1209 1210 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1211 { 1212 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1213 struct smu_dpm_policy_ctxt *policy_ctxt; 1214 struct smu_dpm_policy *policy; 1215 1216 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1217 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1218 if (policy) 1219 policy->current_level = XGMI_PLPD_DEFAULT; 1220 return; 1221 } 1222 1223 /* PMFW put PLPD into default policy after enabling the feature */ 1224 if (smu_feature_is_enabled(smu, 1225 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1226 if (policy) 1227 policy->current_level = XGMI_PLPD_DEFAULT; 1228 } else { 1229 policy_ctxt = dpm_ctxt->dpm_policies; 1230 if (policy_ctxt) 1231 policy_ctxt->policy_mask &= 1232 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1233 } 1234 } 1235 1236 static int smu_sw_init(void *handle) 1237 { 1238 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1239 struct smu_context *smu = adev->powerplay.pp_handle; 1240 int ret; 1241 1242 smu->pool_size = adev->pm.smu_prv_buffer_size; 1243 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1244 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1245 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1246 1247 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1248 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1249 atomic64_set(&smu->throttle_int_counter, 0); 1250 smu->watermarks_bitmap = 0; 1251 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1252 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1253 1254 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1255 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1256 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1257 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1258 1259 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1260 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1261 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1262 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1263 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1264 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1265 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1266 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1267 1268 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1269 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1270 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1271 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1272 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1273 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1274 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1275 smu->display_config = &adev->pm.pm_display_cfg; 1276 1277 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1278 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1279 1280 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1281 smu_swctf_delayed_work_handler); 1282 1283 ret = smu_smc_table_sw_init(smu); 1284 if (ret) { 1285 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1286 return ret; 1287 } 1288 1289 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1290 ret = smu_get_vbios_bootup_values(smu); 1291 if (ret) { 1292 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1293 return ret; 1294 } 1295 1296 ret = smu_init_pptable_microcode(smu); 1297 if (ret) { 1298 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1299 return ret; 1300 } 1301 1302 ret = smu_register_irq_handler(smu); 1303 if (ret) { 1304 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1305 return ret; 1306 } 1307 1308 /* If there is no way to query fan control mode, fan control is not supported */ 1309 if (!smu->ppt_funcs->get_fan_control_mode) 1310 smu->adev->pm.no_fan = true; 1311 1312 return 0; 1313 } 1314 1315 static int smu_sw_fini(void *handle) 1316 { 1317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1318 struct smu_context *smu = adev->powerplay.pp_handle; 1319 int ret; 1320 1321 ret = smu_smc_table_sw_fini(smu); 1322 if (ret) { 1323 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1324 return ret; 1325 } 1326 1327 smu_fini_microcode(smu); 1328 1329 return 0; 1330 } 1331 1332 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1333 { 1334 struct amdgpu_device *adev = smu->adev; 1335 struct smu_temperature_range *range = 1336 &smu->thermal_range; 1337 int ret = 0; 1338 1339 if (!smu->ppt_funcs->get_thermal_temperature_range) 1340 return 0; 1341 1342 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1343 if (ret) 1344 return ret; 1345 1346 adev->pm.dpm.thermal.min_temp = range->min; 1347 adev->pm.dpm.thermal.max_temp = range->max; 1348 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1349 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1350 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1351 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1352 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1353 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1354 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1355 1356 return ret; 1357 } 1358 1359 /** 1360 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1361 * 1362 * @smu: smu_context pointer 1363 * 1364 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1365 * Returns 0 on success, error on failure. 1366 */ 1367 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1368 { 1369 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1370 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1371 struct amdgpu_device *adev = smu->adev; 1372 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1373 uint64_t start, end; 1374 int ret, i, j; 1375 1376 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1377 if (ret) { 1378 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1379 return ret; 1380 } 1381 1382 /* 1383 * The exclusion ranges array we got might be filled with holes and duplicate 1384 * entries. For example: 1385 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1386 * We need to do some sortups to eliminate those holes and duplicate entries. 1387 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1388 */ 1389 for (i = 0; i < num_of_wbrf_ranges; i++) { 1390 start = wifi_bands[i].start; 1391 end = wifi_bands[i].end; 1392 1393 /* get the last valid entry to fill the intermediate hole */ 1394 if (!start && !end) { 1395 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1396 if (wifi_bands[j].start && wifi_bands[j].end) 1397 break; 1398 1399 /* no valid entry left */ 1400 if (j <= i) 1401 break; 1402 1403 start = wifi_bands[i].start = wifi_bands[j].start; 1404 end = wifi_bands[i].end = wifi_bands[j].end; 1405 wifi_bands[j].start = 0; 1406 wifi_bands[j].end = 0; 1407 num_of_wbrf_ranges = j; 1408 } 1409 1410 /* eliminate duplicate entries */ 1411 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1412 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1413 wifi_bands[j].start = 0; 1414 wifi_bands[j].end = 0; 1415 } 1416 } 1417 } 1418 1419 /* Send the sorted wifi_bands to PMFW */ 1420 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1421 /* Try to set the wifi_bands again */ 1422 if (unlikely(ret == -EBUSY)) { 1423 mdelay(5); 1424 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1425 } 1426 1427 return ret; 1428 } 1429 1430 /** 1431 * smu_wbrf_event_handler - handle notify events 1432 * 1433 * @nb: notifier block 1434 * @action: event type 1435 * @_arg: event data 1436 * 1437 * Calls relevant amdgpu function in response to wbrf event 1438 * notification from kernel. 1439 */ 1440 static int smu_wbrf_event_handler(struct notifier_block *nb, 1441 unsigned long action, void *_arg) 1442 { 1443 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1444 1445 switch (action) { 1446 case WBRF_CHANGED: 1447 schedule_delayed_work(&smu->wbrf_delayed_work, 1448 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1449 break; 1450 default: 1451 return NOTIFY_DONE; 1452 } 1453 1454 return NOTIFY_OK; 1455 } 1456 1457 /** 1458 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1459 * 1460 * @work: struct work_struct pointer 1461 * 1462 * Flood is over and driver will consume the latest exclusion ranges. 1463 */ 1464 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1465 { 1466 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1467 1468 smu_wbrf_handle_exclusion_ranges(smu); 1469 } 1470 1471 /** 1472 * smu_wbrf_support_check - check wbrf support 1473 * 1474 * @smu: smu_context pointer 1475 * 1476 * Verifies the ACPI interface whether wbrf is supported. 1477 */ 1478 static void smu_wbrf_support_check(struct smu_context *smu) 1479 { 1480 struct amdgpu_device *adev = smu->adev; 1481 1482 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1483 acpi_amd_wbrf_supported_consumer(adev->dev); 1484 1485 if (smu->wbrf_supported) 1486 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1487 } 1488 1489 /** 1490 * smu_wbrf_init - init driver wbrf support 1491 * 1492 * @smu: smu_context pointer 1493 * 1494 * Verifies the AMD ACPI interfaces and registers with the wbrf 1495 * notifier chain if wbrf feature is supported. 1496 * Returns 0 on success, error on failure. 1497 */ 1498 static int smu_wbrf_init(struct smu_context *smu) 1499 { 1500 int ret; 1501 1502 if (!smu->wbrf_supported) 1503 return 0; 1504 1505 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1506 1507 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1508 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1509 if (ret) 1510 return ret; 1511 1512 /* 1513 * Some wifiband exclusion ranges may be already there 1514 * before our driver loaded. To make sure our driver 1515 * is awared of those exclusion ranges. 1516 */ 1517 schedule_delayed_work(&smu->wbrf_delayed_work, 1518 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1519 1520 return 0; 1521 } 1522 1523 /** 1524 * smu_wbrf_fini - tear down driver wbrf support 1525 * 1526 * @smu: smu_context pointer 1527 * 1528 * Unregisters with the wbrf notifier chain. 1529 */ 1530 static void smu_wbrf_fini(struct smu_context *smu) 1531 { 1532 if (!smu->wbrf_supported) 1533 return; 1534 1535 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1536 1537 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1538 } 1539 1540 static int smu_smc_hw_setup(struct smu_context *smu) 1541 { 1542 struct smu_feature *feature = &smu->smu_feature; 1543 struct amdgpu_device *adev = smu->adev; 1544 uint8_t pcie_gen = 0, pcie_width = 0; 1545 uint64_t features_supported; 1546 int ret = 0; 1547 1548 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1549 case IP_VERSION(11, 0, 7): 1550 case IP_VERSION(11, 0, 11): 1551 case IP_VERSION(11, 5, 0): 1552 case IP_VERSION(11, 0, 12): 1553 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1554 dev_info(adev->dev, "dpm has been enabled\n"); 1555 ret = smu_system_features_control(smu, true); 1556 if (ret) 1557 dev_err(adev->dev, "Failed system features control!\n"); 1558 return ret; 1559 } 1560 break; 1561 default: 1562 break; 1563 } 1564 1565 ret = smu_init_display_count(smu, 0); 1566 if (ret) { 1567 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1568 return ret; 1569 } 1570 1571 ret = smu_set_driver_table_location(smu); 1572 if (ret) { 1573 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1574 return ret; 1575 } 1576 1577 /* 1578 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1579 */ 1580 ret = smu_set_tool_table_location(smu); 1581 if (ret) { 1582 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1583 return ret; 1584 } 1585 1586 /* 1587 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1588 * pool location. 1589 */ 1590 ret = smu_notify_memory_pool_location(smu); 1591 if (ret) { 1592 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1593 return ret; 1594 } 1595 1596 /* 1597 * It is assumed the pptable used before runpm is same as 1598 * the one used afterwards. Thus, we can reuse the stored 1599 * copy and do not need to resetup the pptable again. 1600 */ 1601 if (!adev->in_runpm) { 1602 ret = smu_setup_pptable(smu); 1603 if (ret) { 1604 dev_err(adev->dev, "Failed to setup pptable!\n"); 1605 return ret; 1606 } 1607 } 1608 1609 /* smu_dump_pptable(smu); */ 1610 1611 /* 1612 * With SCPM enabled, PSP is responsible for the PPTable transferring 1613 * (to SMU). Driver involvement is not needed and permitted. 1614 */ 1615 if (!adev->scpm_enabled) { 1616 /* 1617 * Copy pptable bo in the vram to smc with SMU MSGs such as 1618 * SetDriverDramAddr and TransferTableDram2Smu. 1619 */ 1620 ret = smu_write_pptable(smu); 1621 if (ret) { 1622 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1623 return ret; 1624 } 1625 } 1626 1627 /* issue Run*Btc msg */ 1628 ret = smu_run_btc(smu); 1629 if (ret) 1630 return ret; 1631 1632 /* Enable UclkShadow on wbrf supported */ 1633 if (smu->wbrf_supported) { 1634 ret = smu_enable_uclk_shadow(smu, true); 1635 if (ret) { 1636 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1637 return ret; 1638 } 1639 } 1640 1641 /* 1642 * With SCPM enabled, these actions(and relevant messages) are 1643 * not needed and permitted. 1644 */ 1645 if (!adev->scpm_enabled) { 1646 ret = smu_feature_set_allowed_mask(smu); 1647 if (ret) { 1648 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1649 return ret; 1650 } 1651 } 1652 1653 ret = smu_system_features_control(smu, true); 1654 if (ret) { 1655 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1656 return ret; 1657 } 1658 1659 smu_init_xgmi_plpd_mode(smu); 1660 1661 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1662 if (ret) { 1663 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1664 return ret; 1665 } 1666 bitmap_copy(feature->supported, 1667 (unsigned long *)&features_supported, 1668 feature->feature_num); 1669 1670 if (!smu_is_dpm_running(smu)) 1671 dev_info(adev->dev, "dpm has been disabled\n"); 1672 1673 /* 1674 * Set initialized values (get from vbios) to dpm tables context such as 1675 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1676 * type of clks. 1677 */ 1678 ret = smu_set_default_dpm_table(smu); 1679 if (ret) { 1680 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1681 return ret; 1682 } 1683 1684 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1685 pcie_gen = 3; 1686 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1687 pcie_gen = 2; 1688 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1689 pcie_gen = 1; 1690 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1691 pcie_gen = 0; 1692 1693 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1694 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1695 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1696 */ 1697 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1698 pcie_width = 6; 1699 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1700 pcie_width = 5; 1701 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1702 pcie_width = 4; 1703 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1704 pcie_width = 3; 1705 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1706 pcie_width = 2; 1707 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1708 pcie_width = 1; 1709 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1710 if (ret) { 1711 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1712 return ret; 1713 } 1714 1715 ret = smu_get_thermal_temperature_range(smu); 1716 if (ret) { 1717 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1718 return ret; 1719 } 1720 1721 ret = smu_enable_thermal_alert(smu); 1722 if (ret) { 1723 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1724 return ret; 1725 } 1726 1727 ret = smu_notify_display_change(smu); 1728 if (ret) { 1729 dev_err(adev->dev, "Failed to notify display change!\n"); 1730 return ret; 1731 } 1732 1733 /* 1734 * Set min deep sleep dce fclk with bootup value from vbios via 1735 * SetMinDeepSleepDcefclk MSG. 1736 */ 1737 ret = smu_set_min_dcef_deep_sleep(smu, 1738 smu->smu_table.boot_values.dcefclk / 100); 1739 if (ret) { 1740 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1741 return ret; 1742 } 1743 1744 /* Init wbrf support. Properly setup the notifier */ 1745 ret = smu_wbrf_init(smu); 1746 if (ret) 1747 dev_err(adev->dev, "Error during wbrf init call\n"); 1748 1749 return ret; 1750 } 1751 1752 static int smu_start_smc_engine(struct smu_context *smu) 1753 { 1754 struct amdgpu_device *adev = smu->adev; 1755 int ret = 0; 1756 1757 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1758 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1759 if (smu->ppt_funcs->load_microcode) { 1760 ret = smu->ppt_funcs->load_microcode(smu); 1761 if (ret) 1762 return ret; 1763 } 1764 } 1765 } 1766 1767 if (smu->ppt_funcs->check_fw_status) { 1768 ret = smu->ppt_funcs->check_fw_status(smu); 1769 if (ret) { 1770 dev_err(adev->dev, "SMC is not ready\n"); 1771 return ret; 1772 } 1773 } 1774 1775 /* 1776 * Send msg GetDriverIfVersion to check if the return value is equal 1777 * with DRIVER_IF_VERSION of smc header. 1778 */ 1779 ret = smu_check_fw_version(smu); 1780 if (ret) 1781 return ret; 1782 1783 return ret; 1784 } 1785 1786 static int smu_hw_init(void *handle) 1787 { 1788 int ret; 1789 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1790 struct smu_context *smu = adev->powerplay.pp_handle; 1791 1792 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1793 smu->pm_enabled = false; 1794 return 0; 1795 } 1796 1797 ret = smu_start_smc_engine(smu); 1798 if (ret) { 1799 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1800 return ret; 1801 } 1802 1803 /* 1804 * Check whether wbrf is supported. This needs to be done 1805 * before SMU setup starts since part of SMU configuration 1806 * relies on this. 1807 */ 1808 smu_wbrf_support_check(smu); 1809 1810 if (smu->is_apu) { 1811 ret = smu_set_gfx_imu_enable(smu); 1812 if (ret) 1813 return ret; 1814 smu_dpm_set_vcn_enable(smu, true); 1815 smu_dpm_set_jpeg_enable(smu, true); 1816 smu_dpm_set_vpe_enable(smu, true); 1817 smu_dpm_set_umsch_mm_enable(smu, true); 1818 smu_set_mall_enable(smu); 1819 smu_set_gfx_cgpg(smu, true); 1820 } 1821 1822 if (!smu->pm_enabled) 1823 return 0; 1824 1825 ret = smu_get_driver_allowed_feature_mask(smu); 1826 if (ret) 1827 return ret; 1828 1829 ret = smu_smc_hw_setup(smu); 1830 if (ret) { 1831 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1832 return ret; 1833 } 1834 1835 /* 1836 * Move maximum sustainable clock retrieving here considering 1837 * 1. It is not needed on resume(from S3). 1838 * 2. DAL settings come between .hw_init and .late_init of SMU. 1839 * And DAL needs to know the maximum sustainable clocks. Thus 1840 * it cannot be put in .late_init(). 1841 */ 1842 ret = smu_init_max_sustainable_clocks(smu); 1843 if (ret) { 1844 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1845 return ret; 1846 } 1847 1848 adev->pm.dpm_enabled = true; 1849 1850 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1851 1852 return 0; 1853 } 1854 1855 static int smu_disable_dpms(struct smu_context *smu) 1856 { 1857 struct amdgpu_device *adev = smu->adev; 1858 int ret = 0; 1859 bool use_baco = !smu->is_apu && 1860 ((amdgpu_in_reset(adev) && 1861 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1862 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1863 1864 /* 1865 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1866 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1867 */ 1868 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1869 case IP_VERSION(13, 0, 0): 1870 case IP_VERSION(13, 0, 7): 1871 case IP_VERSION(13, 0, 10): 1872 case IP_VERSION(14, 0, 2): 1873 case IP_VERSION(14, 0, 3): 1874 return 0; 1875 default: 1876 break; 1877 } 1878 1879 /* 1880 * For custom pptable uploading, skip the DPM features 1881 * disable process on Navi1x ASICs. 1882 * - As the gfx related features are under control of 1883 * RLC on those ASICs. RLC reinitialization will be 1884 * needed to reenable them. That will cost much more 1885 * efforts. 1886 * 1887 * - SMU firmware can handle the DPM reenablement 1888 * properly. 1889 */ 1890 if (smu->uploading_custom_pp_table) { 1891 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1892 case IP_VERSION(11, 0, 0): 1893 case IP_VERSION(11, 0, 5): 1894 case IP_VERSION(11, 0, 9): 1895 case IP_VERSION(11, 0, 7): 1896 case IP_VERSION(11, 0, 11): 1897 case IP_VERSION(11, 5, 0): 1898 case IP_VERSION(11, 0, 12): 1899 case IP_VERSION(11, 0, 13): 1900 return 0; 1901 default: 1902 break; 1903 } 1904 } 1905 1906 /* 1907 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1908 * on BACO in. Driver involvement is unnecessary. 1909 */ 1910 if (use_baco) { 1911 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1912 case IP_VERSION(11, 0, 7): 1913 case IP_VERSION(11, 0, 0): 1914 case IP_VERSION(11, 0, 5): 1915 case IP_VERSION(11, 0, 9): 1916 case IP_VERSION(13, 0, 7): 1917 return 0; 1918 default: 1919 break; 1920 } 1921 } 1922 1923 /* 1924 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1925 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1926 */ 1927 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1928 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1929 case IP_VERSION(13, 0, 4): 1930 case IP_VERSION(13, 0, 11): 1931 case IP_VERSION(14, 0, 0): 1932 case IP_VERSION(14, 0, 1): 1933 return 0; 1934 default: 1935 break; 1936 } 1937 } 1938 1939 /* 1940 * For gpu reset, runpm and hibernation through BACO, 1941 * BACO feature has to be kept enabled. 1942 */ 1943 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1944 ret = smu_disable_all_features_with_exception(smu, 1945 SMU_FEATURE_BACO_BIT); 1946 if (ret) 1947 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1948 } else { 1949 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1950 if (!adev->scpm_enabled) { 1951 ret = smu_system_features_control(smu, false); 1952 if (ret) 1953 dev_err(adev->dev, "Failed to disable smu features.\n"); 1954 } 1955 } 1956 1957 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1958 * otherwise SMU will hang while interacting with RLC if RLC is halted 1959 * this is a WA for Vangogh asic which fix the SMU hang issue. 1960 */ 1961 ret = smu_notify_rlc_state(smu, false); 1962 if (ret) { 1963 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1964 return ret; 1965 } 1966 1967 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1968 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1969 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1970 adev->gfx.rlc.funcs->stop(adev); 1971 1972 return ret; 1973 } 1974 1975 static int smu_smc_hw_cleanup(struct smu_context *smu) 1976 { 1977 struct amdgpu_device *adev = smu->adev; 1978 int ret = 0; 1979 1980 smu_wbrf_fini(smu); 1981 1982 cancel_work_sync(&smu->throttling_logging_work); 1983 cancel_work_sync(&smu->interrupt_work); 1984 1985 ret = smu_disable_thermal_alert(smu); 1986 if (ret) { 1987 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1988 return ret; 1989 } 1990 1991 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1992 1993 ret = smu_disable_dpms(smu); 1994 if (ret) { 1995 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1996 return ret; 1997 } 1998 1999 return 0; 2000 } 2001 2002 static int smu_reset_mp1_state(struct smu_context *smu) 2003 { 2004 struct amdgpu_device *adev = smu->adev; 2005 int ret = 0; 2006 2007 if ((!adev->in_runpm) && (!adev->in_suspend) && 2008 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2009 IP_VERSION(13, 0, 10) && 2010 !amdgpu_device_has_display_hardware(adev)) 2011 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2012 2013 return ret; 2014 } 2015 2016 static int smu_hw_fini(void *handle) 2017 { 2018 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2019 struct smu_context *smu = adev->powerplay.pp_handle; 2020 int ret; 2021 2022 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2023 return 0; 2024 2025 smu_dpm_set_vcn_enable(smu, false); 2026 smu_dpm_set_jpeg_enable(smu, false); 2027 smu_dpm_set_vpe_enable(smu, false); 2028 smu_dpm_set_umsch_mm_enable(smu, false); 2029 2030 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2031 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2032 2033 if (!smu->pm_enabled) 2034 return 0; 2035 2036 adev->pm.dpm_enabled = false; 2037 2038 ret = smu_smc_hw_cleanup(smu); 2039 if (ret) 2040 return ret; 2041 2042 ret = smu_reset_mp1_state(smu); 2043 if (ret) 2044 return ret; 2045 2046 return 0; 2047 } 2048 2049 static void smu_late_fini(void *handle) 2050 { 2051 struct amdgpu_device *adev = handle; 2052 struct smu_context *smu = adev->powerplay.pp_handle; 2053 2054 kfree(smu); 2055 } 2056 2057 static int smu_reset(struct smu_context *smu) 2058 { 2059 struct amdgpu_device *adev = smu->adev; 2060 int ret; 2061 2062 ret = smu_hw_fini(adev); 2063 if (ret) 2064 return ret; 2065 2066 ret = smu_hw_init(adev); 2067 if (ret) 2068 return ret; 2069 2070 ret = smu_late_init(adev); 2071 if (ret) 2072 return ret; 2073 2074 return 0; 2075 } 2076 2077 static int smu_suspend(void *handle) 2078 { 2079 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2080 struct smu_context *smu = adev->powerplay.pp_handle; 2081 int ret; 2082 uint64_t count; 2083 2084 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2085 return 0; 2086 2087 if (!smu->pm_enabled) 2088 return 0; 2089 2090 adev->pm.dpm_enabled = false; 2091 2092 ret = smu_smc_hw_cleanup(smu); 2093 if (ret) 2094 return ret; 2095 2096 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2097 2098 smu_set_gfx_cgpg(smu, false); 2099 2100 /* 2101 * pwfw resets entrycount when device is suspended, so we save the 2102 * last value to be used when we resume to keep it consistent 2103 */ 2104 ret = smu_get_entrycount_gfxoff(smu, &count); 2105 if (!ret) 2106 adev->gfx.gfx_off_entrycount = count; 2107 2108 return 0; 2109 } 2110 2111 static int smu_resume(void *handle) 2112 { 2113 int ret; 2114 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2115 struct smu_context *smu = adev->powerplay.pp_handle; 2116 2117 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2118 return 0; 2119 2120 if (!smu->pm_enabled) 2121 return 0; 2122 2123 dev_info(adev->dev, "SMU is resuming...\n"); 2124 2125 ret = smu_start_smc_engine(smu); 2126 if (ret) { 2127 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2128 return ret; 2129 } 2130 2131 ret = smu_smc_hw_setup(smu); 2132 if (ret) { 2133 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2134 return ret; 2135 } 2136 2137 ret = smu_set_gfx_imu_enable(smu); 2138 if (ret) 2139 return ret; 2140 2141 smu_set_gfx_cgpg(smu, true); 2142 2143 smu->disable_uclk_switch = 0; 2144 2145 adev->pm.dpm_enabled = true; 2146 2147 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2148 2149 return 0; 2150 } 2151 2152 static int smu_display_configuration_change(void *handle, 2153 const struct amd_pp_display_configuration *display_config) 2154 { 2155 struct smu_context *smu = handle; 2156 2157 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2158 return -EOPNOTSUPP; 2159 2160 if (!display_config) 2161 return -EINVAL; 2162 2163 smu_set_min_dcef_deep_sleep(smu, 2164 display_config->min_dcef_deep_sleep_set_clk / 100); 2165 2166 return 0; 2167 } 2168 2169 static int smu_set_clockgating_state(void *handle, 2170 enum amd_clockgating_state state) 2171 { 2172 return 0; 2173 } 2174 2175 static int smu_set_powergating_state(void *handle, 2176 enum amd_powergating_state state) 2177 { 2178 return 0; 2179 } 2180 2181 static int smu_enable_umd_pstate(void *handle, 2182 enum amd_dpm_forced_level *level) 2183 { 2184 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2185 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2186 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2187 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2188 2189 struct smu_context *smu = (struct smu_context*)(handle); 2190 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2191 2192 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2193 return -EINVAL; 2194 2195 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2196 /* enter umd pstate, save current level, disable gfx cg*/ 2197 if (*level & profile_mode_mask) { 2198 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2199 smu_gpo_control(smu, false); 2200 smu_gfx_ulv_control(smu, false); 2201 smu_deep_sleep_control(smu, false); 2202 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2203 } 2204 } else { 2205 /* exit umd pstate, restore level, enable gfx cg*/ 2206 if (!(*level & profile_mode_mask)) { 2207 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2208 *level = smu_dpm_ctx->saved_dpm_level; 2209 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2210 smu_deep_sleep_control(smu, true); 2211 smu_gfx_ulv_control(smu, true); 2212 smu_gpo_control(smu, true); 2213 } 2214 } 2215 2216 return 0; 2217 } 2218 2219 static int smu_bump_power_profile_mode(struct smu_context *smu, 2220 long *param, 2221 uint32_t param_size) 2222 { 2223 int ret = 0; 2224 2225 if (smu->ppt_funcs->set_power_profile_mode) 2226 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2227 2228 return ret; 2229 } 2230 2231 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2232 enum amd_dpm_forced_level level, 2233 bool skip_display_settings) 2234 { 2235 int ret = 0; 2236 int index = 0; 2237 long workload[1]; 2238 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2239 2240 if (!skip_display_settings) { 2241 ret = smu_display_config_changed(smu); 2242 if (ret) { 2243 dev_err(smu->adev->dev, "Failed to change display config!"); 2244 return ret; 2245 } 2246 } 2247 2248 ret = smu_apply_clocks_adjust_rules(smu); 2249 if (ret) { 2250 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2251 return ret; 2252 } 2253 2254 if (!skip_display_settings) { 2255 ret = smu_notify_smc_display_config(smu); 2256 if (ret) { 2257 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2258 return ret; 2259 } 2260 } 2261 2262 if (smu_dpm_ctx->dpm_level != level) { 2263 ret = smu_asic_set_performance_level(smu, level); 2264 if (ret) { 2265 dev_err(smu->adev->dev, "Failed to set performance level!"); 2266 return ret; 2267 } 2268 2269 /* update the saved copy */ 2270 smu_dpm_ctx->dpm_level = level; 2271 } 2272 2273 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2274 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2275 index = fls(smu->workload_mask); 2276 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2277 workload[0] = smu->workload_setting[index]; 2278 2279 if (smu->power_profile_mode != workload[0]) 2280 smu_bump_power_profile_mode(smu, workload, 0); 2281 } 2282 2283 return ret; 2284 } 2285 2286 static int smu_handle_task(struct smu_context *smu, 2287 enum amd_dpm_forced_level level, 2288 enum amd_pp_task task_id) 2289 { 2290 int ret = 0; 2291 2292 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2293 return -EOPNOTSUPP; 2294 2295 switch (task_id) { 2296 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2297 ret = smu_pre_display_config_changed(smu); 2298 if (ret) 2299 return ret; 2300 ret = smu_adjust_power_state_dynamic(smu, level, false); 2301 break; 2302 case AMD_PP_TASK_COMPLETE_INIT: 2303 case AMD_PP_TASK_READJUST_POWER_STATE: 2304 ret = smu_adjust_power_state_dynamic(smu, level, true); 2305 break; 2306 default: 2307 break; 2308 } 2309 2310 return ret; 2311 } 2312 2313 static int smu_handle_dpm_task(void *handle, 2314 enum amd_pp_task task_id, 2315 enum amd_pm_state_type *user_state) 2316 { 2317 struct smu_context *smu = handle; 2318 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2319 2320 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2321 2322 } 2323 2324 static int smu_switch_power_profile(void *handle, 2325 enum PP_SMC_POWER_PROFILE type, 2326 bool en) 2327 { 2328 struct smu_context *smu = handle; 2329 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2330 long workload[1]; 2331 uint32_t index; 2332 2333 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2334 return -EOPNOTSUPP; 2335 2336 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2337 return -EINVAL; 2338 2339 if (!en) { 2340 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2341 index = fls(smu->workload_mask); 2342 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2343 workload[0] = smu->workload_setting[index]; 2344 } else { 2345 smu->workload_mask |= (1 << smu->workload_prority[type]); 2346 index = fls(smu->workload_mask); 2347 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2348 workload[0] = smu->workload_setting[index]; 2349 } 2350 2351 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2352 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2353 smu_bump_power_profile_mode(smu, workload, 0); 2354 2355 return 0; 2356 } 2357 2358 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2359 { 2360 struct smu_context *smu = handle; 2361 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2362 2363 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2364 return -EOPNOTSUPP; 2365 2366 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2367 return -EINVAL; 2368 2369 return smu_dpm_ctx->dpm_level; 2370 } 2371 2372 static int smu_force_performance_level(void *handle, 2373 enum amd_dpm_forced_level level) 2374 { 2375 struct smu_context *smu = handle; 2376 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2377 int ret = 0; 2378 2379 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2380 return -EOPNOTSUPP; 2381 2382 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2383 return -EINVAL; 2384 2385 ret = smu_enable_umd_pstate(smu, &level); 2386 if (ret) 2387 return ret; 2388 2389 ret = smu_handle_task(smu, level, 2390 AMD_PP_TASK_READJUST_POWER_STATE); 2391 2392 /* reset user dpm clock state */ 2393 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2394 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2395 smu->user_dpm_profile.clk_dependency = 0; 2396 } 2397 2398 return ret; 2399 } 2400 2401 static int smu_set_display_count(void *handle, uint32_t count) 2402 { 2403 struct smu_context *smu = handle; 2404 2405 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2406 return -EOPNOTSUPP; 2407 2408 return smu_init_display_count(smu, count); 2409 } 2410 2411 static int smu_force_smuclk_levels(struct smu_context *smu, 2412 enum smu_clk_type clk_type, 2413 uint32_t mask) 2414 { 2415 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2416 int ret = 0; 2417 2418 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2419 return -EOPNOTSUPP; 2420 2421 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2422 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2423 return -EINVAL; 2424 } 2425 2426 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2427 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2428 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2429 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2430 smu_set_user_clk_dependencies(smu, clk_type); 2431 } 2432 } 2433 2434 return ret; 2435 } 2436 2437 static int smu_force_ppclk_levels(void *handle, 2438 enum pp_clock_type type, 2439 uint32_t mask) 2440 { 2441 struct smu_context *smu = handle; 2442 enum smu_clk_type clk_type; 2443 2444 switch (type) { 2445 case PP_SCLK: 2446 clk_type = SMU_SCLK; break; 2447 case PP_MCLK: 2448 clk_type = SMU_MCLK; break; 2449 case PP_PCIE: 2450 clk_type = SMU_PCIE; break; 2451 case PP_SOCCLK: 2452 clk_type = SMU_SOCCLK; break; 2453 case PP_FCLK: 2454 clk_type = SMU_FCLK; break; 2455 case PP_DCEFCLK: 2456 clk_type = SMU_DCEFCLK; break; 2457 case PP_VCLK: 2458 clk_type = SMU_VCLK; break; 2459 case PP_VCLK1: 2460 clk_type = SMU_VCLK1; break; 2461 case PP_DCLK: 2462 clk_type = SMU_DCLK; break; 2463 case PP_DCLK1: 2464 clk_type = SMU_DCLK1; break; 2465 case OD_SCLK: 2466 clk_type = SMU_OD_SCLK; break; 2467 case OD_MCLK: 2468 clk_type = SMU_OD_MCLK; break; 2469 case OD_VDDC_CURVE: 2470 clk_type = SMU_OD_VDDC_CURVE; break; 2471 case OD_RANGE: 2472 clk_type = SMU_OD_RANGE; break; 2473 default: 2474 return -EINVAL; 2475 } 2476 2477 return smu_force_smuclk_levels(smu, clk_type, mask); 2478 } 2479 2480 /* 2481 * On system suspending or resetting, the dpm_enabled 2482 * flag will be cleared. So that those SMU services which 2483 * are not supported will be gated. 2484 * However, the mp1 state setting should still be granted 2485 * even if the dpm_enabled cleared. 2486 */ 2487 static int smu_set_mp1_state(void *handle, 2488 enum pp_mp1_state mp1_state) 2489 { 2490 struct smu_context *smu = handle; 2491 int ret = 0; 2492 2493 if (!smu->pm_enabled) 2494 return -EOPNOTSUPP; 2495 2496 if (smu->ppt_funcs && 2497 smu->ppt_funcs->set_mp1_state) 2498 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2499 2500 return ret; 2501 } 2502 2503 static int smu_set_df_cstate(void *handle, 2504 enum pp_df_cstate state) 2505 { 2506 struct smu_context *smu = handle; 2507 int ret = 0; 2508 2509 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2510 return -EOPNOTSUPP; 2511 2512 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2513 return 0; 2514 2515 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2516 if (ret) 2517 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2518 2519 return ret; 2520 } 2521 2522 int smu_write_watermarks_table(struct smu_context *smu) 2523 { 2524 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2525 return -EOPNOTSUPP; 2526 2527 return smu_set_watermarks_table(smu, NULL); 2528 } 2529 2530 static int smu_set_watermarks_for_clock_ranges(void *handle, 2531 struct pp_smu_wm_range_sets *clock_ranges) 2532 { 2533 struct smu_context *smu = handle; 2534 2535 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2536 return -EOPNOTSUPP; 2537 2538 if (smu->disable_watermark) 2539 return 0; 2540 2541 return smu_set_watermarks_table(smu, clock_ranges); 2542 } 2543 2544 int smu_set_ac_dc(struct smu_context *smu) 2545 { 2546 int ret = 0; 2547 2548 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2549 return -EOPNOTSUPP; 2550 2551 /* controlled by firmware */ 2552 if (smu->dc_controlled_by_gpio) 2553 return 0; 2554 2555 ret = smu_set_power_source(smu, 2556 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2557 SMU_POWER_SOURCE_DC); 2558 if (ret) 2559 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2560 smu->adev->pm.ac_power ? "AC" : "DC"); 2561 2562 return ret; 2563 } 2564 2565 const struct amd_ip_funcs smu_ip_funcs = { 2566 .name = "smu", 2567 .early_init = smu_early_init, 2568 .late_init = smu_late_init, 2569 .sw_init = smu_sw_init, 2570 .sw_fini = smu_sw_fini, 2571 .hw_init = smu_hw_init, 2572 .hw_fini = smu_hw_fini, 2573 .late_fini = smu_late_fini, 2574 .suspend = smu_suspend, 2575 .resume = smu_resume, 2576 .is_idle = NULL, 2577 .check_soft_reset = NULL, 2578 .wait_for_idle = NULL, 2579 .soft_reset = NULL, 2580 .set_clockgating_state = smu_set_clockgating_state, 2581 .set_powergating_state = smu_set_powergating_state, 2582 }; 2583 2584 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2585 .type = AMD_IP_BLOCK_TYPE_SMC, 2586 .major = 11, 2587 .minor = 0, 2588 .rev = 0, 2589 .funcs = &smu_ip_funcs, 2590 }; 2591 2592 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2593 .type = AMD_IP_BLOCK_TYPE_SMC, 2594 .major = 12, 2595 .minor = 0, 2596 .rev = 0, 2597 .funcs = &smu_ip_funcs, 2598 }; 2599 2600 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2601 .type = AMD_IP_BLOCK_TYPE_SMC, 2602 .major = 13, 2603 .minor = 0, 2604 .rev = 0, 2605 .funcs = &smu_ip_funcs, 2606 }; 2607 2608 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2609 .type = AMD_IP_BLOCK_TYPE_SMC, 2610 .major = 14, 2611 .minor = 0, 2612 .rev = 0, 2613 .funcs = &smu_ip_funcs, 2614 }; 2615 2616 static int smu_load_microcode(void *handle) 2617 { 2618 struct smu_context *smu = handle; 2619 struct amdgpu_device *adev = smu->adev; 2620 int ret = 0; 2621 2622 if (!smu->pm_enabled) 2623 return -EOPNOTSUPP; 2624 2625 /* This should be used for non PSP loading */ 2626 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2627 return 0; 2628 2629 if (smu->ppt_funcs->load_microcode) { 2630 ret = smu->ppt_funcs->load_microcode(smu); 2631 if (ret) { 2632 dev_err(adev->dev, "Load microcode failed\n"); 2633 return ret; 2634 } 2635 } 2636 2637 if (smu->ppt_funcs->check_fw_status) { 2638 ret = smu->ppt_funcs->check_fw_status(smu); 2639 if (ret) { 2640 dev_err(adev->dev, "SMC is not ready\n"); 2641 return ret; 2642 } 2643 } 2644 2645 return ret; 2646 } 2647 2648 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2649 { 2650 int ret = 0; 2651 2652 if (smu->ppt_funcs->set_gfx_cgpg) 2653 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2654 2655 return ret; 2656 } 2657 2658 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2659 { 2660 struct smu_context *smu = handle; 2661 int ret = 0; 2662 2663 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2664 return -EOPNOTSUPP; 2665 2666 if (!smu->ppt_funcs->set_fan_speed_rpm) 2667 return -EOPNOTSUPP; 2668 2669 if (speed == U32_MAX) 2670 return -EINVAL; 2671 2672 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2673 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2674 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2675 smu->user_dpm_profile.fan_speed_rpm = speed; 2676 2677 /* Override custom PWM setting as they cannot co-exist */ 2678 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2679 smu->user_dpm_profile.fan_speed_pwm = 0; 2680 } 2681 2682 return ret; 2683 } 2684 2685 /** 2686 * smu_get_power_limit - Request one of the SMU Power Limits 2687 * 2688 * @handle: pointer to smu context 2689 * @limit: requested limit is written back to this variable 2690 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2691 * @pp_power_type: &pp_power_type type of power 2692 * Return: 0 on success, <0 on error 2693 * 2694 */ 2695 int smu_get_power_limit(void *handle, 2696 uint32_t *limit, 2697 enum pp_power_limit_level pp_limit_level, 2698 enum pp_power_type pp_power_type) 2699 { 2700 struct smu_context *smu = handle; 2701 struct amdgpu_device *adev = smu->adev; 2702 enum smu_ppt_limit_level limit_level; 2703 uint32_t limit_type; 2704 int ret = 0; 2705 2706 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2707 return -EOPNOTSUPP; 2708 2709 switch (pp_power_type) { 2710 case PP_PWR_TYPE_SUSTAINED: 2711 limit_type = SMU_DEFAULT_PPT_LIMIT; 2712 break; 2713 case PP_PWR_TYPE_FAST: 2714 limit_type = SMU_FAST_PPT_LIMIT; 2715 break; 2716 default: 2717 return -EOPNOTSUPP; 2718 } 2719 2720 switch (pp_limit_level) { 2721 case PP_PWR_LIMIT_CURRENT: 2722 limit_level = SMU_PPT_LIMIT_CURRENT; 2723 break; 2724 case PP_PWR_LIMIT_DEFAULT: 2725 limit_level = SMU_PPT_LIMIT_DEFAULT; 2726 break; 2727 case PP_PWR_LIMIT_MAX: 2728 limit_level = SMU_PPT_LIMIT_MAX; 2729 break; 2730 case PP_PWR_LIMIT_MIN: 2731 limit_level = SMU_PPT_LIMIT_MIN; 2732 break; 2733 default: 2734 return -EOPNOTSUPP; 2735 } 2736 2737 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2738 if (smu->ppt_funcs->get_ppt_limit) 2739 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2740 } else { 2741 switch (limit_level) { 2742 case SMU_PPT_LIMIT_CURRENT: 2743 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2744 case IP_VERSION(13, 0, 2): 2745 case IP_VERSION(13, 0, 6): 2746 case IP_VERSION(13, 0, 14): 2747 case IP_VERSION(11, 0, 7): 2748 case IP_VERSION(11, 0, 11): 2749 case IP_VERSION(11, 0, 12): 2750 case IP_VERSION(11, 0, 13): 2751 ret = smu_get_asic_power_limits(smu, 2752 &smu->current_power_limit, 2753 NULL, NULL, NULL); 2754 break; 2755 default: 2756 break; 2757 } 2758 *limit = smu->current_power_limit; 2759 break; 2760 case SMU_PPT_LIMIT_DEFAULT: 2761 *limit = smu->default_power_limit; 2762 break; 2763 case SMU_PPT_LIMIT_MAX: 2764 *limit = smu->max_power_limit; 2765 break; 2766 case SMU_PPT_LIMIT_MIN: 2767 *limit = smu->min_power_limit; 2768 break; 2769 default: 2770 return -EINVAL; 2771 } 2772 } 2773 2774 return ret; 2775 } 2776 2777 static int smu_set_power_limit(void *handle, uint32_t limit) 2778 { 2779 struct smu_context *smu = handle; 2780 uint32_t limit_type = limit >> 24; 2781 int ret = 0; 2782 2783 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2784 return -EOPNOTSUPP; 2785 2786 limit &= (1<<24)-1; 2787 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2788 if (smu->ppt_funcs->set_power_limit) 2789 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2790 2791 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2792 dev_err(smu->adev->dev, 2793 "New power limit (%d) is out of range [%d,%d]\n", 2794 limit, smu->min_power_limit, smu->max_power_limit); 2795 return -EINVAL; 2796 } 2797 2798 if (!limit) 2799 limit = smu->current_power_limit; 2800 2801 if (smu->ppt_funcs->set_power_limit) { 2802 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2803 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2804 smu->user_dpm_profile.power_limit = limit; 2805 } 2806 2807 return ret; 2808 } 2809 2810 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2811 { 2812 int ret = 0; 2813 2814 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2815 return -EOPNOTSUPP; 2816 2817 if (smu->ppt_funcs->print_clk_levels) 2818 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2819 2820 return ret; 2821 } 2822 2823 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2824 { 2825 enum smu_clk_type clk_type; 2826 2827 switch (type) { 2828 case PP_SCLK: 2829 clk_type = SMU_SCLK; break; 2830 case PP_MCLK: 2831 clk_type = SMU_MCLK; break; 2832 case PP_PCIE: 2833 clk_type = SMU_PCIE; break; 2834 case PP_SOCCLK: 2835 clk_type = SMU_SOCCLK; break; 2836 case PP_FCLK: 2837 clk_type = SMU_FCLK; break; 2838 case PP_DCEFCLK: 2839 clk_type = SMU_DCEFCLK; break; 2840 case PP_VCLK: 2841 clk_type = SMU_VCLK; break; 2842 case PP_VCLK1: 2843 clk_type = SMU_VCLK1; break; 2844 case PP_DCLK: 2845 clk_type = SMU_DCLK; break; 2846 case PP_DCLK1: 2847 clk_type = SMU_DCLK1; break; 2848 case OD_SCLK: 2849 clk_type = SMU_OD_SCLK; break; 2850 case OD_MCLK: 2851 clk_type = SMU_OD_MCLK; break; 2852 case OD_VDDC_CURVE: 2853 clk_type = SMU_OD_VDDC_CURVE; break; 2854 case OD_RANGE: 2855 clk_type = SMU_OD_RANGE; break; 2856 case OD_VDDGFX_OFFSET: 2857 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2858 case OD_CCLK: 2859 clk_type = SMU_OD_CCLK; break; 2860 case OD_FAN_CURVE: 2861 clk_type = SMU_OD_FAN_CURVE; break; 2862 case OD_ACOUSTIC_LIMIT: 2863 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2864 case OD_ACOUSTIC_TARGET: 2865 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2866 case OD_FAN_TARGET_TEMPERATURE: 2867 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2868 case OD_FAN_MINIMUM_PWM: 2869 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2870 default: 2871 clk_type = SMU_CLK_COUNT; break; 2872 } 2873 2874 return clk_type; 2875 } 2876 2877 static int smu_print_ppclk_levels(void *handle, 2878 enum pp_clock_type type, 2879 char *buf) 2880 { 2881 struct smu_context *smu = handle; 2882 enum smu_clk_type clk_type; 2883 2884 clk_type = smu_convert_to_smuclk(type); 2885 if (clk_type == SMU_CLK_COUNT) 2886 return -EINVAL; 2887 2888 return smu_print_smuclk_levels(smu, clk_type, buf); 2889 } 2890 2891 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2892 { 2893 struct smu_context *smu = handle; 2894 enum smu_clk_type clk_type; 2895 2896 clk_type = smu_convert_to_smuclk(type); 2897 if (clk_type == SMU_CLK_COUNT) 2898 return -EINVAL; 2899 2900 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2901 return -EOPNOTSUPP; 2902 2903 if (!smu->ppt_funcs->emit_clk_levels) 2904 return -ENOENT; 2905 2906 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2907 2908 } 2909 2910 static int smu_od_edit_dpm_table(void *handle, 2911 enum PP_OD_DPM_TABLE_COMMAND type, 2912 long *input, uint32_t size) 2913 { 2914 struct smu_context *smu = handle; 2915 int ret = 0; 2916 2917 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2918 return -EOPNOTSUPP; 2919 2920 if (smu->ppt_funcs->od_edit_dpm_table) { 2921 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2922 } 2923 2924 return ret; 2925 } 2926 2927 static int smu_read_sensor(void *handle, 2928 int sensor, 2929 void *data, 2930 int *size_arg) 2931 { 2932 struct smu_context *smu = handle; 2933 struct smu_umd_pstate_table *pstate_table = 2934 &smu->pstate_table; 2935 int ret = 0; 2936 uint32_t *size, size_val; 2937 2938 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2939 return -EOPNOTSUPP; 2940 2941 if (!data || !size_arg) 2942 return -EINVAL; 2943 2944 size_val = *size_arg; 2945 size = &size_val; 2946 2947 if (smu->ppt_funcs->read_sensor) 2948 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2949 goto unlock; 2950 2951 switch (sensor) { 2952 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2953 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2954 *size = 4; 2955 break; 2956 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2957 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2958 *size = 4; 2959 break; 2960 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2961 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2962 *size = 4; 2963 break; 2964 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2965 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2966 *size = 4; 2967 break; 2968 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2969 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2970 *size = 8; 2971 break; 2972 case AMDGPU_PP_SENSOR_UVD_POWER: 2973 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2974 *size = 4; 2975 break; 2976 case AMDGPU_PP_SENSOR_VCE_POWER: 2977 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2978 *size = 4; 2979 break; 2980 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2981 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2982 *size = 4; 2983 break; 2984 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2985 *(uint32_t *)data = 0; 2986 *size = 4; 2987 break; 2988 default: 2989 *size = 0; 2990 ret = -EOPNOTSUPP; 2991 break; 2992 } 2993 2994 unlock: 2995 // assign uint32_t to int 2996 *size_arg = size_val; 2997 2998 return ret; 2999 } 3000 3001 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3002 { 3003 int ret = -EOPNOTSUPP; 3004 struct smu_context *smu = handle; 3005 3006 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3007 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3008 3009 return ret; 3010 } 3011 3012 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3013 { 3014 int ret = -EOPNOTSUPP; 3015 struct smu_context *smu = handle; 3016 3017 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3018 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3019 3020 return ret; 3021 } 3022 3023 static int smu_get_power_profile_mode(void *handle, char *buf) 3024 { 3025 struct smu_context *smu = handle; 3026 3027 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3028 !smu->ppt_funcs->get_power_profile_mode) 3029 return -EOPNOTSUPP; 3030 if (!buf) 3031 return -EINVAL; 3032 3033 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3034 } 3035 3036 static int smu_set_power_profile_mode(void *handle, 3037 long *param, 3038 uint32_t param_size) 3039 { 3040 struct smu_context *smu = handle; 3041 3042 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3043 !smu->ppt_funcs->set_power_profile_mode) 3044 return -EOPNOTSUPP; 3045 3046 return smu_bump_power_profile_mode(smu, param, param_size); 3047 } 3048 3049 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3050 { 3051 struct smu_context *smu = handle; 3052 3053 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3054 return -EOPNOTSUPP; 3055 3056 if (!smu->ppt_funcs->get_fan_control_mode) 3057 return -EOPNOTSUPP; 3058 3059 if (!fan_mode) 3060 return -EINVAL; 3061 3062 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3063 3064 return 0; 3065 } 3066 3067 static int smu_set_fan_control_mode(void *handle, u32 value) 3068 { 3069 struct smu_context *smu = handle; 3070 int ret = 0; 3071 3072 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3073 return -EOPNOTSUPP; 3074 3075 if (!smu->ppt_funcs->set_fan_control_mode) 3076 return -EOPNOTSUPP; 3077 3078 if (value == U32_MAX) 3079 return -EINVAL; 3080 3081 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3082 if (ret) 3083 goto out; 3084 3085 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3086 smu->user_dpm_profile.fan_mode = value; 3087 3088 /* reset user dpm fan speed */ 3089 if (value != AMD_FAN_CTRL_MANUAL) { 3090 smu->user_dpm_profile.fan_speed_pwm = 0; 3091 smu->user_dpm_profile.fan_speed_rpm = 0; 3092 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3093 } 3094 } 3095 3096 out: 3097 return ret; 3098 } 3099 3100 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3101 { 3102 struct smu_context *smu = handle; 3103 int ret = 0; 3104 3105 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3106 return -EOPNOTSUPP; 3107 3108 if (!smu->ppt_funcs->get_fan_speed_pwm) 3109 return -EOPNOTSUPP; 3110 3111 if (!speed) 3112 return -EINVAL; 3113 3114 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3115 3116 return ret; 3117 } 3118 3119 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3120 { 3121 struct smu_context *smu = handle; 3122 int ret = 0; 3123 3124 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3125 return -EOPNOTSUPP; 3126 3127 if (!smu->ppt_funcs->set_fan_speed_pwm) 3128 return -EOPNOTSUPP; 3129 3130 if (speed == U32_MAX) 3131 return -EINVAL; 3132 3133 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3134 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3135 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3136 smu->user_dpm_profile.fan_speed_pwm = speed; 3137 3138 /* Override custom RPM setting as they cannot co-exist */ 3139 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3140 smu->user_dpm_profile.fan_speed_rpm = 0; 3141 } 3142 3143 return ret; 3144 } 3145 3146 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3147 { 3148 struct smu_context *smu = handle; 3149 int ret = 0; 3150 3151 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3152 return -EOPNOTSUPP; 3153 3154 if (!smu->ppt_funcs->get_fan_speed_rpm) 3155 return -EOPNOTSUPP; 3156 3157 if (!speed) 3158 return -EINVAL; 3159 3160 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3161 3162 return ret; 3163 } 3164 3165 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3166 { 3167 struct smu_context *smu = handle; 3168 3169 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3170 return -EOPNOTSUPP; 3171 3172 return smu_set_min_dcef_deep_sleep(smu, clk); 3173 } 3174 3175 static int smu_get_clock_by_type_with_latency(void *handle, 3176 enum amd_pp_clock_type type, 3177 struct pp_clock_levels_with_latency *clocks) 3178 { 3179 struct smu_context *smu = handle; 3180 enum smu_clk_type clk_type; 3181 int ret = 0; 3182 3183 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3184 return -EOPNOTSUPP; 3185 3186 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3187 switch (type) { 3188 case amd_pp_sys_clock: 3189 clk_type = SMU_GFXCLK; 3190 break; 3191 case amd_pp_mem_clock: 3192 clk_type = SMU_MCLK; 3193 break; 3194 case amd_pp_dcef_clock: 3195 clk_type = SMU_DCEFCLK; 3196 break; 3197 case amd_pp_disp_clock: 3198 clk_type = SMU_DISPCLK; 3199 break; 3200 default: 3201 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3202 return -EINVAL; 3203 } 3204 3205 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3206 } 3207 3208 return ret; 3209 } 3210 3211 static int smu_display_clock_voltage_request(void *handle, 3212 struct pp_display_clock_request *clock_req) 3213 { 3214 struct smu_context *smu = handle; 3215 int ret = 0; 3216 3217 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3218 return -EOPNOTSUPP; 3219 3220 if (smu->ppt_funcs->display_clock_voltage_request) 3221 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3222 3223 return ret; 3224 } 3225 3226 3227 static int smu_display_disable_memory_clock_switch(void *handle, 3228 bool disable_memory_clock_switch) 3229 { 3230 struct smu_context *smu = handle; 3231 int ret = -EINVAL; 3232 3233 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3234 return -EOPNOTSUPP; 3235 3236 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3237 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3238 3239 return ret; 3240 } 3241 3242 static int smu_set_xgmi_pstate(void *handle, 3243 uint32_t pstate) 3244 { 3245 struct smu_context *smu = handle; 3246 int ret = 0; 3247 3248 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3249 return -EOPNOTSUPP; 3250 3251 if (smu->ppt_funcs->set_xgmi_pstate) 3252 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3253 3254 if (ret) 3255 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3256 3257 return ret; 3258 } 3259 3260 static int smu_get_baco_capability(void *handle) 3261 { 3262 struct smu_context *smu = handle; 3263 3264 if (!smu->pm_enabled) 3265 return false; 3266 3267 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3268 return false; 3269 3270 return smu->ppt_funcs->get_bamaco_support(smu); 3271 } 3272 3273 static int smu_baco_set_state(void *handle, int state) 3274 { 3275 struct smu_context *smu = handle; 3276 int ret = 0; 3277 3278 if (!smu->pm_enabled) 3279 return -EOPNOTSUPP; 3280 3281 if (state == 0) { 3282 if (smu->ppt_funcs->baco_exit) 3283 ret = smu->ppt_funcs->baco_exit(smu); 3284 } else if (state == 1) { 3285 if (smu->ppt_funcs->baco_enter) 3286 ret = smu->ppt_funcs->baco_enter(smu); 3287 } else { 3288 return -EINVAL; 3289 } 3290 3291 if (ret) 3292 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3293 (state)?"enter":"exit"); 3294 3295 return ret; 3296 } 3297 3298 bool smu_mode1_reset_is_support(struct smu_context *smu) 3299 { 3300 bool ret = false; 3301 3302 if (!smu->pm_enabled) 3303 return false; 3304 3305 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3306 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3307 3308 return ret; 3309 } 3310 3311 bool smu_mode2_reset_is_support(struct smu_context *smu) 3312 { 3313 bool ret = false; 3314 3315 if (!smu->pm_enabled) 3316 return false; 3317 3318 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3319 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3320 3321 return ret; 3322 } 3323 3324 int smu_mode1_reset(struct smu_context *smu) 3325 { 3326 int ret = 0; 3327 3328 if (!smu->pm_enabled) 3329 return -EOPNOTSUPP; 3330 3331 if (smu->ppt_funcs->mode1_reset) 3332 ret = smu->ppt_funcs->mode1_reset(smu); 3333 3334 return ret; 3335 } 3336 3337 static int smu_mode2_reset(void *handle) 3338 { 3339 struct smu_context *smu = handle; 3340 int ret = 0; 3341 3342 if (!smu->pm_enabled) 3343 return -EOPNOTSUPP; 3344 3345 if (smu->ppt_funcs->mode2_reset) 3346 ret = smu->ppt_funcs->mode2_reset(smu); 3347 3348 if (ret) 3349 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3350 3351 return ret; 3352 } 3353 3354 static int smu_enable_gfx_features(void *handle) 3355 { 3356 struct smu_context *smu = handle; 3357 int ret = 0; 3358 3359 if (!smu->pm_enabled) 3360 return -EOPNOTSUPP; 3361 3362 if (smu->ppt_funcs->enable_gfx_features) 3363 ret = smu->ppt_funcs->enable_gfx_features(smu); 3364 3365 if (ret) 3366 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3367 3368 return ret; 3369 } 3370 3371 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3372 struct pp_smu_nv_clock_table *max_clocks) 3373 { 3374 struct smu_context *smu = handle; 3375 int ret = 0; 3376 3377 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3378 return -EOPNOTSUPP; 3379 3380 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3381 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3382 3383 return ret; 3384 } 3385 3386 static int smu_get_uclk_dpm_states(void *handle, 3387 unsigned int *clock_values_in_khz, 3388 unsigned int *num_states) 3389 { 3390 struct smu_context *smu = handle; 3391 int ret = 0; 3392 3393 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3394 return -EOPNOTSUPP; 3395 3396 if (smu->ppt_funcs->get_uclk_dpm_states) 3397 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3398 3399 return ret; 3400 } 3401 3402 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3403 { 3404 struct smu_context *smu = handle; 3405 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3406 3407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3408 return -EOPNOTSUPP; 3409 3410 if (smu->ppt_funcs->get_current_power_state) 3411 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3412 3413 return pm_state; 3414 } 3415 3416 static int smu_get_dpm_clock_table(void *handle, 3417 struct dpm_clocks *clock_table) 3418 { 3419 struct smu_context *smu = handle; 3420 int ret = 0; 3421 3422 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3423 return -EOPNOTSUPP; 3424 3425 if (smu->ppt_funcs->get_dpm_clock_table) 3426 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3427 3428 return ret; 3429 } 3430 3431 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3432 { 3433 struct smu_context *smu = handle; 3434 3435 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3436 return -EOPNOTSUPP; 3437 3438 if (!smu->ppt_funcs->get_gpu_metrics) 3439 return -EOPNOTSUPP; 3440 3441 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3442 } 3443 3444 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3445 size_t size) 3446 { 3447 struct smu_context *smu = handle; 3448 3449 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3450 return -EOPNOTSUPP; 3451 3452 if (!smu->ppt_funcs->get_pm_metrics) 3453 return -EOPNOTSUPP; 3454 3455 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3456 } 3457 3458 static int smu_enable_mgpu_fan_boost(void *handle) 3459 { 3460 struct smu_context *smu = handle; 3461 int ret = 0; 3462 3463 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3464 return -EOPNOTSUPP; 3465 3466 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3467 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3468 3469 return ret; 3470 } 3471 3472 static int smu_gfx_state_change_set(void *handle, 3473 uint32_t state) 3474 { 3475 struct smu_context *smu = handle; 3476 int ret = 0; 3477 3478 if (smu->ppt_funcs->gfx_state_change_set) 3479 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3480 3481 return ret; 3482 } 3483 3484 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3485 { 3486 int ret = 0; 3487 3488 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3489 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3490 3491 return ret; 3492 } 3493 3494 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3495 { 3496 int ret = -EOPNOTSUPP; 3497 3498 if (smu->ppt_funcs && 3499 smu->ppt_funcs->get_ecc_info) 3500 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3501 3502 return ret; 3503 3504 } 3505 3506 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3507 { 3508 struct smu_context *smu = handle; 3509 struct smu_table_context *smu_table = &smu->smu_table; 3510 struct smu_table *memory_pool = &smu_table->memory_pool; 3511 3512 if (!addr || !size) 3513 return -EINVAL; 3514 3515 *addr = NULL; 3516 *size = 0; 3517 if (memory_pool->bo) { 3518 *addr = memory_pool->cpu_addr; 3519 *size = memory_pool->size; 3520 } 3521 3522 return 0; 3523 } 3524 3525 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3526 size_t *size) 3527 { 3528 size_t offset = *size; 3529 int level; 3530 3531 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3532 if (level == policy->current_level) 3533 offset += sysfs_emit_at(sysbuf, offset, 3534 "%d : %s*\n", level, 3535 policy->desc->get_desc(policy, level)); 3536 else 3537 offset += sysfs_emit_at(sysbuf, offset, 3538 "%d : %s\n", level, 3539 policy->desc->get_desc(policy, level)); 3540 } 3541 3542 *size = offset; 3543 } 3544 3545 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3546 enum pp_pm_policy p_type, char *sysbuf) 3547 { 3548 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3549 struct smu_dpm_policy_ctxt *policy_ctxt; 3550 struct smu_dpm_policy *dpm_policy; 3551 size_t offset = 0; 3552 3553 policy_ctxt = dpm_ctxt->dpm_policies; 3554 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3555 !policy_ctxt->policy_mask) 3556 return -EOPNOTSUPP; 3557 3558 if (p_type == PP_PM_POLICY_NONE) 3559 return -EINVAL; 3560 3561 dpm_policy = smu_get_pm_policy(smu, p_type); 3562 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3563 return -ENOENT; 3564 3565 if (!sysbuf) 3566 return -EINVAL; 3567 3568 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3569 3570 return offset; 3571 } 3572 3573 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3574 enum pp_pm_policy p_type) 3575 { 3576 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3577 struct smu_dpm_policy_ctxt *policy_ctxt; 3578 int i; 3579 3580 policy_ctxt = dpm_ctxt->dpm_policies; 3581 if (!policy_ctxt) 3582 return NULL; 3583 3584 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3585 if (policy_ctxt->policies[i].policy_type == p_type) 3586 return &policy_ctxt->policies[i]; 3587 } 3588 3589 return NULL; 3590 } 3591 3592 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3593 int level) 3594 { 3595 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3596 struct smu_dpm_policy *dpm_policy = NULL; 3597 struct smu_dpm_policy_ctxt *policy_ctxt; 3598 int ret = -EOPNOTSUPP; 3599 3600 policy_ctxt = dpm_ctxt->dpm_policies; 3601 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3602 !policy_ctxt->policy_mask) 3603 return ret; 3604 3605 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3606 return -EINVAL; 3607 3608 dpm_policy = smu_get_pm_policy(smu, p_type); 3609 3610 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3611 return ret; 3612 3613 if (dpm_policy->current_level == level) 3614 return 0; 3615 3616 ret = dpm_policy->set_policy(smu, level); 3617 3618 if (!ret) 3619 dpm_policy->current_level = level; 3620 3621 return ret; 3622 } 3623 3624 static const struct amd_pm_funcs swsmu_pm_funcs = { 3625 /* export for sysfs */ 3626 .set_fan_control_mode = smu_set_fan_control_mode, 3627 .get_fan_control_mode = smu_get_fan_control_mode, 3628 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3629 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3630 .force_clock_level = smu_force_ppclk_levels, 3631 .print_clock_levels = smu_print_ppclk_levels, 3632 .emit_clock_levels = smu_emit_ppclk_levels, 3633 .force_performance_level = smu_force_performance_level, 3634 .read_sensor = smu_read_sensor, 3635 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3636 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3637 .get_performance_level = smu_get_performance_level, 3638 .get_current_power_state = smu_get_current_power_state, 3639 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3640 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3641 .get_pp_num_states = smu_get_power_num_states, 3642 .get_pp_table = smu_sys_get_pp_table, 3643 .set_pp_table = smu_sys_set_pp_table, 3644 .switch_power_profile = smu_switch_power_profile, 3645 /* export to amdgpu */ 3646 .dispatch_tasks = smu_handle_dpm_task, 3647 .load_firmware = smu_load_microcode, 3648 .set_powergating_by_smu = smu_dpm_set_power_gate, 3649 .set_power_limit = smu_set_power_limit, 3650 .get_power_limit = smu_get_power_limit, 3651 .get_power_profile_mode = smu_get_power_profile_mode, 3652 .set_power_profile_mode = smu_set_power_profile_mode, 3653 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3654 .set_mp1_state = smu_set_mp1_state, 3655 .gfx_state_change_set = smu_gfx_state_change_set, 3656 /* export to DC */ 3657 .get_sclk = smu_get_sclk, 3658 .get_mclk = smu_get_mclk, 3659 .display_configuration_change = smu_display_configuration_change, 3660 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3661 .display_clock_voltage_request = smu_display_clock_voltage_request, 3662 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3663 .set_active_display_count = smu_set_display_count, 3664 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3665 .get_asic_baco_capability = smu_get_baco_capability, 3666 .set_asic_baco_state = smu_baco_set_state, 3667 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3668 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3669 .asic_reset_mode_2 = smu_mode2_reset, 3670 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3671 .set_df_cstate = smu_set_df_cstate, 3672 .set_xgmi_pstate = smu_set_xgmi_pstate, 3673 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3674 .get_pm_metrics = smu_sys_get_pm_metrics, 3675 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3676 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3677 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3678 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3679 .get_dpm_clock_table = smu_get_dpm_clock_table, 3680 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3681 }; 3682 3683 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3684 uint64_t event_arg) 3685 { 3686 int ret = -EINVAL; 3687 3688 if (smu->ppt_funcs->wait_for_event) 3689 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3690 3691 return ret; 3692 } 3693 3694 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3695 { 3696 3697 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3698 return -EOPNOTSUPP; 3699 3700 /* Confirm the buffer allocated is of correct size */ 3701 if (size != smu->stb_context.stb_buf_size) 3702 return -EINVAL; 3703 3704 /* 3705 * No need to lock smu mutex as we access STB directly through MMIO 3706 * and not going through SMU messaging route (for now at least). 3707 * For registers access rely on implementation internal locking. 3708 */ 3709 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3710 } 3711 3712 #if defined(CONFIG_DEBUG_FS) 3713 3714 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3715 { 3716 struct amdgpu_device *adev = filp->f_inode->i_private; 3717 struct smu_context *smu = adev->powerplay.pp_handle; 3718 unsigned char *buf; 3719 int r; 3720 3721 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3722 if (!buf) 3723 return -ENOMEM; 3724 3725 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3726 if (r) 3727 goto out; 3728 3729 filp->private_data = buf; 3730 3731 return 0; 3732 3733 out: 3734 kvfree(buf); 3735 return r; 3736 } 3737 3738 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3739 loff_t *pos) 3740 { 3741 struct amdgpu_device *adev = filp->f_inode->i_private; 3742 struct smu_context *smu = adev->powerplay.pp_handle; 3743 3744 3745 if (!filp->private_data) 3746 return -EINVAL; 3747 3748 return simple_read_from_buffer(buf, 3749 size, 3750 pos, filp->private_data, 3751 smu->stb_context.stb_buf_size); 3752 } 3753 3754 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3755 { 3756 kvfree(filp->private_data); 3757 filp->private_data = NULL; 3758 3759 return 0; 3760 } 3761 3762 /* 3763 * We have to define not only read method but also 3764 * open and release because .read takes up to PAGE_SIZE 3765 * data each time so and so is invoked multiple times. 3766 * We allocate the STB buffer in .open and release it 3767 * in .release 3768 */ 3769 static const struct file_operations smu_stb_debugfs_fops = { 3770 .owner = THIS_MODULE, 3771 .open = smu_stb_debugfs_open, 3772 .read = smu_stb_debugfs_read, 3773 .release = smu_stb_debugfs_release, 3774 .llseek = default_llseek, 3775 }; 3776 3777 #endif 3778 3779 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3780 { 3781 #if defined(CONFIG_DEBUG_FS) 3782 3783 struct smu_context *smu = adev->powerplay.pp_handle; 3784 3785 if (!smu || (!smu->stb_context.stb_buf_size)) 3786 return; 3787 3788 debugfs_create_file_size("amdgpu_smu_stb_dump", 3789 S_IRUSR, 3790 adev_to_drm(adev)->primary->debugfs_root, 3791 adev, 3792 &smu_stb_debugfs_fops, 3793 smu->stb_context.stb_buf_size); 3794 #endif 3795 } 3796 3797 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3798 { 3799 int ret = 0; 3800 3801 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3802 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3803 3804 return ret; 3805 } 3806 3807 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3808 { 3809 int ret = 0; 3810 3811 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3812 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3813 3814 return ret; 3815 } 3816 3817 int smu_send_rma_reason(struct smu_context *smu) 3818 { 3819 int ret = 0; 3820 3821 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3822 ret = smu->ppt_funcs->send_rma_reason(smu); 3823 3824 return ret; 3825 } 3826