1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "smu_v15_0_0_ppt.h" 50 #include "smu_v15_0_8_ppt.h" 51 #include "amd_pcie.h" 52 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 static const struct amd_pm_funcs swsmu_pm_funcs; 64 static int smu_force_smuclk_levels(struct smu_context *smu, 65 enum smu_clk_type clk_type, 66 uint32_t mask); 67 static int smu_handle_task(struct smu_context *smu, 68 enum amd_dpm_forced_level level, 69 enum amd_pp_task task_id); 70 static int smu_reset(struct smu_context *smu); 71 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 72 static int smu_set_fan_control_mode(void *handle, u32 value); 73 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit); 74 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 75 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 76 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 77 static void smu_power_profile_mode_get(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 static void smu_power_profile_mode_put(struct smu_context *smu, 80 enum PP_SMC_POWER_PROFILE profile_mode); 81 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); 82 static int smu_od_edit_dpm_table(void *handle, 83 enum PP_OD_DPM_TABLE_COMMAND type, 84 long *input, uint32_t size); 85 86 static int smu_sys_get_pp_feature_mask(void *handle, 87 char *buf) 88 { 89 struct smu_context *smu = handle; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 return smu_get_pp_feature_mask(smu, buf); 95 } 96 97 static int smu_sys_set_pp_feature_mask(void *handle, 98 uint64_t new_mask) 99 { 100 struct smu_context *smu = handle; 101 102 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 103 return -EOPNOTSUPP; 104 105 return smu_set_pp_feature_mask(smu, new_mask); 106 } 107 108 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 109 { 110 if (!smu->ppt_funcs->set_gfx_off_residency) 111 return -EINVAL; 112 113 return smu_set_gfx_off_residency(smu, value); 114 } 115 116 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 117 { 118 if (!smu->ppt_funcs->get_gfx_off_residency) 119 return -EINVAL; 120 121 return smu_get_gfx_off_residency(smu, value); 122 } 123 124 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 125 { 126 if (!smu->ppt_funcs->get_gfx_off_entrycount) 127 return -EINVAL; 128 129 return smu_get_gfx_off_entrycount(smu, value); 130 } 131 132 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 133 { 134 if (!smu->ppt_funcs->get_gfx_off_status) 135 return -EINVAL; 136 137 *value = smu_get_gfx_off_status(smu); 138 139 return 0; 140 } 141 142 int smu_set_soft_freq_range(struct smu_context *smu, 143 enum pp_clock_type type, 144 uint32_t min, 145 uint32_t max) 146 { 147 enum smu_clk_type clk_type; 148 int ret = 0; 149 150 clk_type = smu_convert_to_smuclk(type); 151 if (clk_type == SMU_CLK_COUNT) 152 return -EINVAL; 153 154 if (smu->ppt_funcs->set_soft_freq_limited_range) 155 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 156 clk_type, 157 min, 158 max, 159 false); 160 161 return ret; 162 } 163 164 int smu_get_dpm_freq_range(struct smu_context *smu, 165 enum smu_clk_type clk_type, 166 uint32_t *min, 167 uint32_t *max) 168 { 169 int ret = -ENOTSUPP; 170 171 if (!min && !max) 172 return -EINVAL; 173 174 if (smu->ppt_funcs->get_dpm_ultimate_freq) 175 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 176 clk_type, 177 min, 178 max); 179 180 return ret; 181 } 182 183 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 184 { 185 int ret = 0; 186 struct amdgpu_device *adev = smu->adev; 187 188 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 189 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 190 if (ret) 191 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 192 } 193 return ret; 194 } 195 196 static u32 smu_get_mclk(void *handle, bool low) 197 { 198 struct smu_context *smu = handle; 199 uint32_t clk_freq; 200 int ret = 0; 201 202 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 203 low ? &clk_freq : NULL, 204 !low ? &clk_freq : NULL); 205 if (ret) 206 return 0; 207 return clk_freq * 100; 208 } 209 210 static u32 smu_get_sclk(void *handle, bool low) 211 { 212 struct smu_context *smu = handle; 213 uint32_t clk_freq; 214 int ret = 0; 215 216 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 217 low ? &clk_freq : NULL, 218 !low ? &clk_freq : NULL); 219 if (ret) 220 return 0; 221 return clk_freq * 100; 222 } 223 224 static int smu_set_gfx_imu_enable(struct smu_context *smu) 225 { 226 struct amdgpu_device *adev = smu->adev; 227 228 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 229 return 0; 230 231 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 232 return 0; 233 234 return smu_set_gfx_power_up_by_imu(smu); 235 } 236 237 static bool is_vcn_enabled(struct amdgpu_device *adev) 238 { 239 int i; 240 241 for (i = 0; i < adev->num_ip_blocks; i++) { 242 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 243 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 244 !adev->ip_blocks[i].status.valid) 245 return false; 246 } 247 248 return true; 249 } 250 251 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 252 bool enable, 253 int inst) 254 { 255 struct smu_power_context *smu_power = &smu->smu_power; 256 struct smu_power_gate *power_gate = &smu_power->power_gate; 257 int ret = 0; 258 259 /* 260 * don't poweron vcn/jpeg when they are skipped. 261 */ 262 if (!is_vcn_enabled(smu->adev)) 263 return 0; 264 265 if (!smu->ppt_funcs->dpm_set_vcn_enable) 266 return 0; 267 268 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 269 return 0; 270 271 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 272 if (!ret) 273 atomic_set(&power_gate->vcn_gated[inst], !enable); 274 275 return ret; 276 } 277 278 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 279 bool enable) 280 { 281 struct smu_power_context *smu_power = &smu->smu_power; 282 struct smu_power_gate *power_gate = &smu_power->power_gate; 283 int ret = 0; 284 285 if (!is_vcn_enabled(smu->adev)) 286 return 0; 287 288 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 289 return 0; 290 291 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 292 return 0; 293 294 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 295 if (!ret) 296 atomic_set(&power_gate->jpeg_gated, !enable); 297 298 return ret; 299 } 300 301 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 302 bool enable) 303 { 304 struct smu_power_context *smu_power = &smu->smu_power; 305 struct smu_power_gate *power_gate = &smu_power->power_gate; 306 int ret = 0; 307 308 if (!smu->ppt_funcs->dpm_set_vpe_enable) 309 return 0; 310 311 if (atomic_read(&power_gate->vpe_gated) ^ enable) 312 return 0; 313 314 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 315 if (!ret) 316 atomic_set(&power_gate->vpe_gated, !enable); 317 318 return ret; 319 } 320 321 static int smu_dpm_set_isp_enable(struct smu_context *smu, 322 bool enable) 323 { 324 struct smu_power_context *smu_power = &smu->smu_power; 325 struct smu_power_gate *power_gate = &smu_power->power_gate; 326 int ret; 327 328 if (!smu->ppt_funcs->dpm_set_isp_enable) 329 return 0; 330 331 if (atomic_read(&power_gate->isp_gated) ^ enable) 332 return 0; 333 334 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable); 335 if (!ret) 336 atomic_set(&power_gate->isp_gated, !enable); 337 338 return ret; 339 } 340 341 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 342 bool enable) 343 { 344 struct smu_power_context *smu_power = &smu->smu_power; 345 struct smu_power_gate *power_gate = &smu_power->power_gate; 346 int ret = 0; 347 348 if (!smu->adev->enable_umsch_mm) 349 return 0; 350 351 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 352 return 0; 353 354 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 355 return 0; 356 357 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 358 if (!ret) 359 atomic_set(&power_gate->umsch_mm_gated, !enable); 360 361 return ret; 362 } 363 364 static int smu_set_mall_enable(struct smu_context *smu) 365 { 366 int ret = 0; 367 368 if (!smu->ppt_funcs->set_mall_enable) 369 return 0; 370 371 ret = smu->ppt_funcs->set_mall_enable(smu); 372 373 return ret; 374 } 375 376 /** 377 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 378 * 379 * @handle: smu_context pointer 380 * @block_type: the IP block to power gate/ungate 381 * @gate: to power gate if true, ungate otherwise 382 * @inst: the instance of the IP block to power gate/ungate 383 * 384 * This API uses no smu->mutex lock protection due to: 385 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 386 * This is guarded to be race condition free by the caller. 387 * 2. Or get called on user setting request of power_dpm_force_performance_level. 388 * Under this case, the smu->mutex lock protection is already enforced on 389 * the parent API smu_force_performance_level of the call path. 390 */ 391 static int smu_dpm_set_power_gate(void *handle, 392 uint32_t block_type, 393 bool gate, 394 int inst) 395 { 396 struct smu_context *smu = handle; 397 int ret = 0; 398 399 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 400 dev_WARN(smu->adev->dev, 401 "SMU uninitialized but power %s requested for %u!\n", 402 gate ? "gate" : "ungate", block_type); 403 return -EOPNOTSUPP; 404 } 405 406 switch (block_type) { 407 /* 408 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 409 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 410 */ 411 case AMD_IP_BLOCK_TYPE_UVD: 412 case AMD_IP_BLOCK_TYPE_VCN: 413 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 414 if (ret) 415 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 416 gate ? "gate" : "ungate", inst); 417 break; 418 case AMD_IP_BLOCK_TYPE_GFX: 419 ret = smu_gfx_off_control(smu, gate); 420 if (ret) 421 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 422 gate ? "enable" : "disable"); 423 break; 424 case AMD_IP_BLOCK_TYPE_SDMA: 425 ret = smu_powergate_sdma(smu, gate); 426 if (ret) 427 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 428 gate ? "gate" : "ungate"); 429 break; 430 case AMD_IP_BLOCK_TYPE_JPEG: 431 ret = smu_dpm_set_jpeg_enable(smu, !gate); 432 if (ret) 433 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 434 gate ? "gate" : "ungate"); 435 break; 436 case AMD_IP_BLOCK_TYPE_VPE: 437 ret = smu_dpm_set_vpe_enable(smu, !gate); 438 if (ret) 439 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 440 gate ? "gate" : "ungate"); 441 break; 442 case AMD_IP_BLOCK_TYPE_ISP: 443 ret = smu_dpm_set_isp_enable(smu, !gate); 444 if (ret) 445 dev_err(smu->adev->dev, "Failed to power %s ISP!\n", 446 gate ? "gate" : "ungate"); 447 break; 448 default: 449 dev_err(smu->adev->dev, "Unsupported block type!\n"); 450 return -EINVAL; 451 } 452 453 return ret; 454 } 455 456 /** 457 * smu_set_user_clk_dependencies - set user profile clock dependencies 458 * 459 * @smu: smu_context pointer 460 * @clk: enum smu_clk_type type 461 * 462 * Enable/Disable the clock dependency for the @clk type. 463 */ 464 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 465 { 466 if (smu->adev->in_suspend) 467 return; 468 469 if (clk == SMU_MCLK) { 470 smu->user_dpm_profile.clk_dependency = 0; 471 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 472 } else if (clk == SMU_FCLK) { 473 /* MCLK takes precedence over FCLK */ 474 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 475 return; 476 477 smu->user_dpm_profile.clk_dependency = 0; 478 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 479 } else if (clk == SMU_SOCCLK) { 480 /* MCLK takes precedence over SOCCLK */ 481 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 482 return; 483 484 smu->user_dpm_profile.clk_dependency = 0; 485 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 486 } else 487 /* Add clk dependencies here, if any */ 488 return; 489 } 490 491 /** 492 * smu_restore_dpm_user_profile - reinstate user dpm profile 493 * 494 * @smu: smu_context pointer 495 * 496 * Restore the saved user power configurations include power limit, 497 * clock frequencies, fan control mode and fan speed. 498 */ 499 static void smu_restore_dpm_user_profile(struct smu_context *smu) 500 { 501 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 502 int ret = 0; 503 504 if (!smu->adev->in_suspend) 505 return; 506 507 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 508 return; 509 510 /* Enable restore flag */ 511 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 512 513 /* set the user dpm power limits */ 514 for (int i = SMU_DEFAULT_PPT_LIMIT; i < SMU_LIMIT_TYPE_COUNT; i++) { 515 if (!smu->user_dpm_profile.power_limits[i]) 516 continue; 517 ret = smu_set_power_limit(smu, i, 518 smu->user_dpm_profile.power_limits[i]); 519 if (ret) 520 dev_err(smu->adev->dev, "Failed to set %d power limit value\n", i); 521 } 522 523 /* set the user dpm clock configurations */ 524 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 525 enum smu_clk_type clk_type; 526 527 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 528 /* 529 * Iterate over smu clk type and force the saved user clk 530 * configs, skip if clock dependency is enabled 531 */ 532 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 533 smu->user_dpm_profile.clk_mask[clk_type]) { 534 ret = smu_force_smuclk_levels(smu, clk_type, 535 smu->user_dpm_profile.clk_mask[clk_type]); 536 if (ret) 537 dev_err(smu->adev->dev, 538 "Failed to set clock type = %d\n", clk_type); 539 } 540 } 541 } 542 543 /* set the user dpm fan configurations */ 544 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 545 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 546 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 547 if (ret != -EOPNOTSUPP) { 548 smu->user_dpm_profile.fan_speed_pwm = 0; 549 smu->user_dpm_profile.fan_speed_rpm = 0; 550 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 551 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 552 } 553 554 if (smu->user_dpm_profile.fan_speed_pwm) { 555 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 556 if (ret != -EOPNOTSUPP) 557 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 558 } 559 560 if (smu->user_dpm_profile.fan_speed_rpm) { 561 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 562 if (ret != -EOPNOTSUPP) 563 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 564 } 565 } 566 567 /* Restore user customized OD settings */ 568 if (smu->user_dpm_profile.user_od) { 569 if (smu->ppt_funcs->restore_user_od_settings) { 570 ret = smu->ppt_funcs->restore_user_od_settings(smu); 571 if (ret) 572 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 573 } 574 } 575 576 /* Disable restore flag */ 577 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 578 } 579 580 static int smu_get_power_num_states(void *handle, 581 struct pp_states_info *state_info) 582 { 583 if (!state_info) 584 return -EINVAL; 585 586 /* not support power state */ 587 memset(state_info, 0, sizeof(struct pp_states_info)); 588 state_info->nums = 1; 589 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 590 591 return 0; 592 } 593 594 bool is_support_sw_smu(struct amdgpu_device *adev) 595 { 596 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 597 if (adev->asic_type == CHIP_VEGA20) 598 return false; 599 600 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 601 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 602 return true; 603 604 return false; 605 } 606 607 bool is_support_cclk_dpm(struct amdgpu_device *adev) 608 { 609 struct smu_context *smu = adev->powerplay.pp_handle; 610 611 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 612 return false; 613 614 return true; 615 } 616 617 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 618 uint32_t param, uint32_t *read_arg) 619 { 620 struct smu_context *smu = adev->powerplay.pp_handle; 621 int ret = -EOPNOTSUPP; 622 623 if (!smu) 624 return ret; 625 626 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 627 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 628 629 return ret; 630 } 631 632 int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, 633 enum smu_feature_mask mask) 634 { 635 struct smu_context *smu = adev->powerplay.pp_handle; 636 int ret = 0; 637 638 if (smu->ppt_funcs && smu->ppt_funcs->feature_is_enabled) 639 ret = smu->ppt_funcs->feature_is_enabled(smu, mask); 640 641 return ret; 642 } 643 644 static int smu_sys_get_pp_table(void *handle, 645 char **table) 646 { 647 struct smu_context *smu = handle; 648 struct smu_table_context *smu_table = &smu->smu_table; 649 650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 651 return -EOPNOTSUPP; 652 653 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 654 return -EOPNOTSUPP; 655 656 if (smu_table->hardcode_pptable) 657 *table = smu_table->hardcode_pptable; 658 else 659 *table = smu_table->power_play_table; 660 661 return smu_table->power_play_table_size; 662 } 663 664 static int smu_sys_set_pp_table(void *handle, 665 const char *buf, 666 size_t size) 667 { 668 struct smu_context *smu = handle; 669 struct smu_table_context *smu_table = &smu->smu_table; 670 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 671 int ret = 0; 672 673 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 674 return -EOPNOTSUPP; 675 676 if (header->usStructureSize != size) { 677 dev_err(smu->adev->dev, "pp table size not matched !\n"); 678 return -EIO; 679 } 680 681 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 682 kfree(smu_table->hardcode_pptable); 683 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 684 if (!smu_table->hardcode_pptable) 685 return -ENOMEM; 686 } 687 688 memcpy(smu_table->hardcode_pptable, buf, size); 689 smu_table->power_play_table = smu_table->hardcode_pptable; 690 smu_table->power_play_table_size = size; 691 692 /* 693 * Special hw_fini action(for Navi1x, the DPMs disablement will be 694 * skipped) may be needed for custom pptable uploading. 695 */ 696 smu->uploading_custom_pp_table = true; 697 698 ret = smu_reset(smu); 699 if (ret) 700 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 701 702 smu->uploading_custom_pp_table = false; 703 704 return ret; 705 } 706 707 static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) 708 { 709 /* 710 * With SCPM enabled, the allowed featuremasks setting(via 711 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 712 * That means there is no way to let PMFW knows the settings below. 713 * Thus, we just assume all the features are allowed under 714 * such scenario. 715 */ 716 if (smu->adev->scpm_enabled) { 717 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 718 return 0; 719 } 720 721 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 722 723 return smu_init_allowed_features(smu); 724 } 725 726 static int smu_set_funcs(struct amdgpu_device *adev) 727 { 728 struct smu_context *smu = adev->powerplay.pp_handle; 729 730 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 731 smu->od_enabled = true; 732 733 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 734 case IP_VERSION(11, 0, 0): 735 case IP_VERSION(11, 0, 5): 736 case IP_VERSION(11, 0, 9): 737 navi10_set_ppt_funcs(smu); 738 break; 739 case IP_VERSION(11, 0, 7): 740 case IP_VERSION(11, 0, 11): 741 case IP_VERSION(11, 0, 12): 742 case IP_VERSION(11, 0, 13): 743 sienna_cichlid_set_ppt_funcs(smu); 744 break; 745 case IP_VERSION(12, 0, 0): 746 case IP_VERSION(12, 0, 1): 747 renoir_set_ppt_funcs(smu); 748 break; 749 case IP_VERSION(11, 5, 0): 750 case IP_VERSION(11, 5, 2): 751 vangogh_set_ppt_funcs(smu); 752 break; 753 case IP_VERSION(13, 0, 1): 754 case IP_VERSION(13, 0, 3): 755 case IP_VERSION(13, 0, 8): 756 yellow_carp_set_ppt_funcs(smu); 757 break; 758 case IP_VERSION(13, 0, 4): 759 case IP_VERSION(13, 0, 11): 760 smu_v13_0_4_set_ppt_funcs(smu); 761 break; 762 case IP_VERSION(13, 0, 5): 763 smu_v13_0_5_set_ppt_funcs(smu); 764 break; 765 case IP_VERSION(11, 0, 8): 766 cyan_skillfish_set_ppt_funcs(smu); 767 break; 768 case IP_VERSION(11, 0, 2): 769 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 770 arcturus_set_ppt_funcs(smu); 771 /* OD is not supported on Arcturus */ 772 smu->od_enabled = false; 773 break; 774 case IP_VERSION(13, 0, 2): 775 aldebaran_set_ppt_funcs(smu); 776 /* Enable pp_od_clk_voltage node */ 777 smu->od_enabled = true; 778 break; 779 case IP_VERSION(13, 0, 0): 780 case IP_VERSION(13, 0, 10): 781 smu_v13_0_0_set_ppt_funcs(smu); 782 break; 783 case IP_VERSION(13, 0, 6): 784 case IP_VERSION(13, 0, 14): 785 case IP_VERSION(13, 0, 12): 786 smu_v13_0_6_set_ppt_funcs(smu); 787 /* Enable pp_od_clk_voltage node */ 788 smu->od_enabled = true; 789 break; 790 case IP_VERSION(13, 0, 7): 791 smu_v13_0_7_set_ppt_funcs(smu); 792 break; 793 case IP_VERSION(14, 0, 0): 794 case IP_VERSION(14, 0, 1): 795 case IP_VERSION(14, 0, 4): 796 case IP_VERSION(14, 0, 5): 797 smu_v14_0_0_set_ppt_funcs(smu); 798 break; 799 case IP_VERSION(14, 0, 2): 800 case IP_VERSION(14, 0, 3): 801 smu_v14_0_2_set_ppt_funcs(smu); 802 break; 803 case IP_VERSION(15, 0, 0): 804 case IP_VERSION(15, 0, 5): 805 case IP_VERSION(15, 0, 9): 806 smu_v15_0_0_set_ppt_funcs(smu); 807 break; 808 case IP_VERSION(15, 0, 8): 809 smu_v15_0_8_set_ppt_funcs(smu); 810 smu->od_enabled = true; 811 break; 812 default: 813 return -EINVAL; 814 } 815 816 return 0; 817 } 818 819 static int smu_early_init(struct amdgpu_ip_block *ip_block) 820 { 821 struct amdgpu_device *adev = ip_block->adev; 822 struct smu_context *smu; 823 int r; 824 825 smu = kzalloc_obj(struct smu_context); 826 if (!smu) 827 return -ENOMEM; 828 829 smu->adev = adev; 830 smu->pm_enabled = !!amdgpu_dpm; 831 smu->is_apu = false; 832 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 833 smu->smu_baco.platform_support = false; 834 smu->smu_baco.maco_support = false; 835 smu->user_dpm_profile.fan_mode = -1; 836 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 837 838 adev->powerplay.pp_handle = smu; 839 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 840 841 r = smu_set_funcs(adev); 842 if (r) 843 return r; 844 return smu_init_microcode(smu); 845 } 846 847 static int smu_set_default_dpm_table(struct smu_context *smu) 848 { 849 struct amdgpu_device *adev = smu->adev; 850 struct smu_power_context *smu_power = &smu->smu_power; 851 struct smu_power_gate *power_gate = &smu_power->power_gate; 852 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 853 int ret = 0; 854 855 if (!smu->ppt_funcs->set_default_dpm_table) 856 return 0; 857 858 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 859 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 860 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 861 } 862 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 863 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 864 865 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 866 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 867 ret = smu_dpm_set_vcn_enable(smu, true, i); 868 if (ret) 869 return ret; 870 } 871 } 872 873 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 874 ret = smu_dpm_set_jpeg_enable(smu, true); 875 if (ret) 876 goto err_out; 877 } 878 879 ret = smu->ppt_funcs->set_default_dpm_table(smu); 880 if (ret) 881 dev_err(smu->adev->dev, 882 "Failed to setup default dpm clock tables!\n"); 883 884 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 885 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 886 err_out: 887 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 888 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 889 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 890 } 891 892 return ret; 893 } 894 895 static int smu_apply_default_config_table_settings(struct smu_context *smu) 896 { 897 struct amdgpu_device *adev = smu->adev; 898 int ret = 0; 899 900 ret = smu_get_default_config_table_settings(smu, 901 &adev->pm.config_table); 902 if (ret) 903 return ret; 904 905 return smu_set_config_table(smu, &adev->pm.config_table); 906 } 907 908 static int smu_late_init(struct amdgpu_ip_block *ip_block) 909 { 910 struct amdgpu_device *adev = ip_block->adev; 911 struct smu_context *smu = adev->powerplay.pp_handle; 912 int ret = 0; 913 914 smu_set_fine_grain_gfx_freq_parameters(smu); 915 916 if (!smu->pm_enabled) 917 return 0; 918 919 ret = smu_post_init(smu); 920 if (ret) { 921 dev_err(adev->dev, "Failed to post smu init!\n"); 922 return ret; 923 } 924 925 /* 926 * Explicitly notify PMFW the power mode the system in. Since 927 * the PMFW may boot the ASIC with a different mode. 928 * For those supporting ACDC switch via gpio, PMFW will 929 * handle the switch automatically. Driver involvement 930 * is unnecessary. 931 */ 932 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 933 smu_set_ac_dc(smu); 934 935 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 936 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 937 return 0; 938 939 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 940 ret = smu_set_default_od_settings(smu); 941 if (ret) { 942 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 943 return ret; 944 } 945 } 946 947 ret = smu_populate_umd_state_clk(smu); 948 if (ret) { 949 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 950 return ret; 951 } 952 953 ret = smu_get_asic_power_limits(smu, 954 &smu->current_power_limit, 955 &smu->default_power_limit, 956 &smu->max_power_limit, 957 &smu->min_power_limit); 958 if (ret) { 959 dev_err(adev->dev, "Failed to get asic power limits!\n"); 960 return ret; 961 } 962 963 if (!amdgpu_sriov_vf(adev)) 964 smu_get_unique_id(smu); 965 966 smu_get_fan_parameters(smu); 967 968 smu_handle_task(smu, 969 smu->smu_dpm.dpm_level, 970 AMD_PP_TASK_COMPLETE_INIT); 971 972 ret = smu_apply_default_config_table_settings(smu); 973 if (ret && (ret != -EOPNOTSUPP)) { 974 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 975 return ret; 976 } 977 978 smu_restore_dpm_user_profile(smu); 979 980 return 0; 981 } 982 983 static int smu_init_fb_allocations(struct smu_context *smu) 984 { 985 struct amdgpu_device *adev = smu->adev; 986 struct smu_table_context *smu_table = &smu->smu_table; 987 struct smu_table *tables = smu_table->tables; 988 struct smu_table *driver_table = &(smu_table->driver_table); 989 uint32_t max_table_size = 0; 990 int ret, i; 991 992 /* VRAM allocation for tool table */ 993 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 994 ret = amdgpu_bo_create_kernel(adev, 995 tables[SMU_TABLE_PMSTATUSLOG].size, 996 tables[SMU_TABLE_PMSTATUSLOG].align, 997 tables[SMU_TABLE_PMSTATUSLOG].domain, 998 &tables[SMU_TABLE_PMSTATUSLOG].bo, 999 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1000 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1001 if (ret) { 1002 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 1003 return ret; 1004 } 1005 } 1006 1007 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 1008 /* VRAM allocation for driver table */ 1009 for (i = 0; i < SMU_TABLE_COUNT; i++) { 1010 if (tables[i].size == 0) 1011 continue; 1012 1013 /* If one of the tables has VRAM domain restriction, keep it in 1014 * VRAM 1015 */ 1016 if ((tables[i].domain & 1017 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 1018 AMDGPU_GEM_DOMAIN_VRAM) 1019 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 1020 1021 if (i == SMU_TABLE_PMSTATUSLOG) 1022 continue; 1023 1024 if (max_table_size < tables[i].size) 1025 max_table_size = tables[i].size; 1026 } 1027 1028 driver_table->size = max_table_size; 1029 driver_table->align = PAGE_SIZE; 1030 1031 ret = amdgpu_bo_create_kernel(adev, 1032 driver_table->size, 1033 driver_table->align, 1034 driver_table->domain, 1035 &driver_table->bo, 1036 &driver_table->mc_address, 1037 &driver_table->cpu_addr); 1038 if (ret) { 1039 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 1040 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1041 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1042 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1043 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1044 } 1045 1046 return ret; 1047 } 1048 1049 static int smu_fini_fb_allocations(struct smu_context *smu) 1050 { 1051 struct smu_table_context *smu_table = &smu->smu_table; 1052 struct smu_table *tables = smu_table->tables; 1053 struct smu_table *driver_table = &(smu_table->driver_table); 1054 1055 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1056 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1057 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1058 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1059 1060 amdgpu_bo_free_kernel(&driver_table->bo, 1061 &driver_table->mc_address, 1062 &driver_table->cpu_addr); 1063 1064 return 0; 1065 } 1066 1067 static void smu_update_gpu_addresses(struct smu_context *smu) 1068 { 1069 struct smu_table_context *smu_table = &smu->smu_table; 1070 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1071 struct smu_table *driver_table = &(smu_table->driver_table); 1072 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1073 1074 if (pm_status_table->bo) 1075 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1076 if (driver_table->bo) 1077 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1078 if (dummy_read_1_table->bo) 1079 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1080 } 1081 1082 /** 1083 * smu_alloc_memory_pool - allocate memory pool in the system memory 1084 * 1085 * @smu: amdgpu_device pointer 1086 * 1087 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1088 * and DramLogSetDramAddr can notify it changed. 1089 * 1090 * Returns 0 on success, error on failure. 1091 */ 1092 static int smu_alloc_memory_pool(struct smu_context *smu) 1093 { 1094 struct amdgpu_device *adev = smu->adev; 1095 struct smu_table_context *smu_table = &smu->smu_table; 1096 struct smu_table *memory_pool = &smu_table->memory_pool; 1097 uint64_t pool_size = smu->pool_size; 1098 int ret = 0; 1099 1100 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1101 return ret; 1102 1103 memory_pool->size = pool_size; 1104 memory_pool->align = PAGE_SIZE; 1105 memory_pool->domain = 1106 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1107 AMDGPU_GEM_DOMAIN_VRAM : 1108 AMDGPU_GEM_DOMAIN_GTT; 1109 1110 switch (pool_size) { 1111 case SMU_MEMORY_POOL_SIZE_256_MB: 1112 case SMU_MEMORY_POOL_SIZE_512_MB: 1113 case SMU_MEMORY_POOL_SIZE_1_GB: 1114 case SMU_MEMORY_POOL_SIZE_2_GB: 1115 ret = amdgpu_bo_create_kernel(adev, 1116 memory_pool->size, 1117 memory_pool->align, 1118 memory_pool->domain, 1119 &memory_pool->bo, 1120 &memory_pool->mc_address, 1121 &memory_pool->cpu_addr); 1122 if (ret) 1123 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1124 break; 1125 default: 1126 break; 1127 } 1128 1129 return ret; 1130 } 1131 1132 static int smu_free_memory_pool(struct smu_context *smu) 1133 { 1134 struct smu_table_context *smu_table = &smu->smu_table; 1135 struct smu_table *memory_pool = &smu_table->memory_pool; 1136 1137 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1138 return 0; 1139 1140 amdgpu_bo_free_kernel(&memory_pool->bo, 1141 &memory_pool->mc_address, 1142 &memory_pool->cpu_addr); 1143 1144 memset(memory_pool, 0, sizeof(struct smu_table)); 1145 1146 return 0; 1147 } 1148 1149 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1150 { 1151 struct smu_table_context *smu_table = &smu->smu_table; 1152 struct smu_table *dummy_read_1_table = 1153 &smu_table->dummy_read_1_table; 1154 struct amdgpu_device *adev = smu->adev; 1155 int ret = 0; 1156 1157 if (!dummy_read_1_table->size) 1158 return 0; 1159 1160 ret = amdgpu_bo_create_kernel(adev, 1161 dummy_read_1_table->size, 1162 dummy_read_1_table->align, 1163 dummy_read_1_table->domain, 1164 &dummy_read_1_table->bo, 1165 &dummy_read_1_table->mc_address, 1166 &dummy_read_1_table->cpu_addr); 1167 if (ret) 1168 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1169 1170 return ret; 1171 } 1172 1173 static void smu_free_dummy_read_table(struct smu_context *smu) 1174 { 1175 struct smu_table_context *smu_table = &smu->smu_table; 1176 struct smu_table *dummy_read_1_table = 1177 &smu_table->dummy_read_1_table; 1178 1179 1180 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1181 &dummy_read_1_table->mc_address, 1182 &dummy_read_1_table->cpu_addr); 1183 1184 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1185 } 1186 1187 static int smu_smc_table_sw_init(struct smu_context *smu) 1188 { 1189 int ret; 1190 1191 /** 1192 * Create smu_table structure, and init smc tables such as 1193 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1194 */ 1195 ret = smu_init_smc_tables(smu); 1196 if (ret) { 1197 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1198 return ret; 1199 } 1200 1201 /** 1202 * Create smu_power_context structure, and allocate smu_dpm_context and 1203 * context size to fill the smu_power_context data. 1204 */ 1205 ret = smu_init_power(smu); 1206 if (ret) { 1207 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1208 return ret; 1209 } 1210 1211 /* 1212 * allocate vram bos to store smc table contents. 1213 */ 1214 ret = smu_init_fb_allocations(smu); 1215 if (ret) 1216 return ret; 1217 1218 ret = smu_alloc_memory_pool(smu); 1219 if (ret) 1220 return ret; 1221 1222 ret = smu_alloc_dummy_read_table(smu); 1223 if (ret) 1224 return ret; 1225 1226 ret = smu_i2c_init(smu); 1227 if (ret) 1228 return ret; 1229 1230 return 0; 1231 } 1232 1233 static int smu_smc_table_sw_fini(struct smu_context *smu) 1234 { 1235 int ret; 1236 1237 smu_i2c_fini(smu); 1238 1239 smu_free_dummy_read_table(smu); 1240 1241 ret = smu_free_memory_pool(smu); 1242 if (ret) 1243 return ret; 1244 1245 ret = smu_fini_fb_allocations(smu); 1246 if (ret) 1247 return ret; 1248 1249 ret = smu_fini_power(smu); 1250 if (ret) { 1251 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1252 return ret; 1253 } 1254 1255 ret = smu_fini_smc_tables(smu); 1256 if (ret) { 1257 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1258 return ret; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static void smu_throttling_logging_work_fn(struct work_struct *work) 1265 { 1266 struct smu_context *smu = container_of(work, struct smu_context, 1267 throttling_logging_work); 1268 1269 smu_log_thermal_throttling(smu); 1270 } 1271 1272 static void smu_interrupt_work_fn(struct work_struct *work) 1273 { 1274 struct smu_context *smu = container_of(work, struct smu_context, 1275 interrupt_work); 1276 1277 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1278 smu->ppt_funcs->interrupt_work(smu); 1279 } 1280 1281 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1282 { 1283 struct smu_context *smu = 1284 container_of(work, struct smu_context, swctf_delayed_work.work); 1285 struct smu_temperature_range *range = 1286 &smu->thermal_range; 1287 struct amdgpu_device *adev = smu->adev; 1288 uint32_t hotspot_tmp, size; 1289 1290 /* 1291 * If the hotspot temperature is confirmed as below SW CTF setting point 1292 * after the delay enforced, nothing will be done. 1293 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1294 */ 1295 if (range->software_shutdown_temp && 1296 smu->ppt_funcs->read_sensor && 1297 !smu->ppt_funcs->read_sensor(smu, 1298 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1299 &hotspot_tmp, 1300 &size) && 1301 hotspot_tmp / 1000 < range->software_shutdown_temp) 1302 return; 1303 1304 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1305 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1306 orderly_poweroff(true); 1307 } 1308 1309 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1310 { 1311 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1312 struct smu_dpm_policy_ctxt *policy_ctxt; 1313 struct smu_dpm_policy *policy; 1314 1315 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1316 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1317 if (policy) 1318 policy->current_level = XGMI_PLPD_DEFAULT; 1319 return; 1320 } 1321 1322 /* PMFW put PLPD into default policy after enabling the feature */ 1323 if (smu_feature_is_enabled(smu, 1324 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1325 if (policy) 1326 policy->current_level = XGMI_PLPD_DEFAULT; 1327 } else { 1328 policy_ctxt = dpm_ctxt->dpm_policies; 1329 if (policy_ctxt) 1330 policy_ctxt->policy_mask &= 1331 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1332 } 1333 } 1334 1335 static void smu_init_power_profile(struct smu_context *smu) 1336 { 1337 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1338 smu->power_profile_mode = 1339 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1340 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1341 } 1342 1343 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1344 { 1345 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1346 1347 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1348 return; 1349 1350 set_bit(fea_id, fea_cap->cap_map); 1351 } 1352 1353 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1354 { 1355 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1356 1357 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1358 return false; 1359 1360 return test_bit(fea_id, fea_cap->cap_map); 1361 } 1362 1363 static void smu_feature_cap_init(struct smu_context *smu) 1364 { 1365 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1366 1367 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT); 1368 } 1369 1370 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1371 { 1372 struct amdgpu_device *adev = ip_block->adev; 1373 struct smu_context *smu = adev->powerplay.pp_handle; 1374 int i, ret; 1375 1376 smu->pool_size = adev->pm.smu_prv_buffer_size; 1377 smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT); 1378 1379 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1380 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1381 atomic64_set(&smu->throttle_int_counter, 0); 1382 smu->watermarks_bitmap = 0; 1383 1384 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1385 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1386 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1387 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1388 atomic_set(&smu->smu_power.power_gate.isp_gated, 1); 1389 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1390 1391 smu_init_power_profile(smu); 1392 smu->display_config = &adev->pm.pm_display_cfg; 1393 1394 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1395 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1396 1397 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1398 smu_swctf_delayed_work_handler); 1399 1400 smu_feature_cap_init(smu); 1401 1402 ret = smu_smc_table_sw_init(smu); 1403 if (ret) { 1404 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1405 return ret; 1406 } 1407 1408 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1409 ret = smu_get_vbios_bootup_values(smu); 1410 if (ret) { 1411 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1412 return ret; 1413 } 1414 1415 ret = smu_init_pptable_microcode(smu); 1416 if (ret) { 1417 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1418 return ret; 1419 } 1420 1421 ret = smu_register_irq_handler(smu); 1422 if (ret) { 1423 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1424 return ret; 1425 } 1426 1427 /* If there is no way to query fan control mode, fan control is not supported */ 1428 if (!smu->ppt_funcs->get_fan_control_mode) 1429 smu->adev->pm.no_fan = true; 1430 1431 return 0; 1432 } 1433 1434 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1435 { 1436 struct amdgpu_device *adev = ip_block->adev; 1437 struct smu_context *smu = adev->powerplay.pp_handle; 1438 int ret; 1439 1440 ret = smu_smc_table_sw_fini(smu); 1441 if (ret) { 1442 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1443 return ret; 1444 } 1445 1446 if (smu->custom_profile_params) { 1447 kfree(smu->custom_profile_params); 1448 smu->custom_profile_params = NULL; 1449 } 1450 1451 smu_fini_microcode(smu); 1452 1453 return 0; 1454 } 1455 1456 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1457 { 1458 struct amdgpu_device *adev = smu->adev; 1459 struct smu_temperature_range *range = 1460 &smu->thermal_range; 1461 int ret = 0; 1462 1463 if (!smu->ppt_funcs->get_thermal_temperature_range) 1464 return 0; 1465 1466 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1467 if (ret) 1468 return ret; 1469 1470 adev->pm.dpm.thermal.min_temp = range->min; 1471 adev->pm.dpm.thermal.max_temp = range->max; 1472 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1473 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1474 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1475 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1476 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1477 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1478 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1479 1480 return ret; 1481 } 1482 1483 /** 1484 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1485 * 1486 * @smu: smu_context pointer 1487 * 1488 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1489 * Returns 0 on success, error on failure. 1490 */ 1491 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1492 { 1493 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1494 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1495 struct amdgpu_device *adev = smu->adev; 1496 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1497 uint64_t start, end; 1498 int ret, i, j; 1499 1500 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1501 if (ret) { 1502 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1503 return ret; 1504 } 1505 1506 /* 1507 * The exclusion ranges array we got might be filled with holes and duplicate 1508 * entries. For example: 1509 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1510 * We need to do some sortups to eliminate those holes and duplicate entries. 1511 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1512 */ 1513 for (i = 0; i < num_of_wbrf_ranges; i++) { 1514 start = wifi_bands[i].start; 1515 end = wifi_bands[i].end; 1516 1517 /* get the last valid entry to fill the intermediate hole */ 1518 if (!start && !end) { 1519 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1520 if (wifi_bands[j].start && wifi_bands[j].end) 1521 break; 1522 1523 /* no valid entry left */ 1524 if (j <= i) 1525 break; 1526 1527 start = wifi_bands[i].start = wifi_bands[j].start; 1528 end = wifi_bands[i].end = wifi_bands[j].end; 1529 wifi_bands[j].start = 0; 1530 wifi_bands[j].end = 0; 1531 num_of_wbrf_ranges = j; 1532 } 1533 1534 /* eliminate duplicate entries */ 1535 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1536 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1537 wifi_bands[j].start = 0; 1538 wifi_bands[j].end = 0; 1539 } 1540 } 1541 } 1542 1543 /* Send the sorted wifi_bands to PMFW */ 1544 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1545 /* Try to set the wifi_bands again */ 1546 if (unlikely(ret == -EBUSY)) { 1547 mdelay(5); 1548 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1549 } 1550 1551 return ret; 1552 } 1553 1554 /** 1555 * smu_wbrf_event_handler - handle notify events 1556 * 1557 * @nb: notifier block 1558 * @action: event type 1559 * @_arg: event data 1560 * 1561 * Calls relevant amdgpu function in response to wbrf event 1562 * notification from kernel. 1563 */ 1564 static int smu_wbrf_event_handler(struct notifier_block *nb, 1565 unsigned long action, void *_arg) 1566 { 1567 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1568 1569 switch (action) { 1570 case WBRF_CHANGED: 1571 schedule_delayed_work(&smu->wbrf_delayed_work, 1572 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1573 break; 1574 default: 1575 return NOTIFY_DONE; 1576 } 1577 1578 return NOTIFY_OK; 1579 } 1580 1581 /** 1582 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1583 * 1584 * @work: struct work_struct pointer 1585 * 1586 * Flood is over and driver will consume the latest exclusion ranges. 1587 */ 1588 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1589 { 1590 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1591 1592 smu_wbrf_handle_exclusion_ranges(smu); 1593 } 1594 1595 /** 1596 * smu_wbrf_support_check - check wbrf support 1597 * 1598 * @smu: smu_context pointer 1599 * 1600 * Verifies the ACPI interface whether wbrf is supported. 1601 */ 1602 static void smu_wbrf_support_check(struct smu_context *smu) 1603 { 1604 struct amdgpu_device *adev = smu->adev; 1605 1606 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1607 acpi_amd_wbrf_supported_consumer(adev->dev); 1608 1609 if (smu->wbrf_supported) 1610 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1611 } 1612 1613 /** 1614 * smu_wbrf_init - init driver wbrf support 1615 * 1616 * @smu: smu_context pointer 1617 * 1618 * Verifies the AMD ACPI interfaces and registers with the wbrf 1619 * notifier chain if wbrf feature is supported. 1620 * Returns 0 on success, error on failure. 1621 */ 1622 static int smu_wbrf_init(struct smu_context *smu) 1623 { 1624 int ret; 1625 1626 if (!smu->wbrf_supported) 1627 return 0; 1628 1629 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1630 1631 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1632 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1633 if (ret) 1634 return ret; 1635 1636 /* 1637 * Some wifiband exclusion ranges may be already there 1638 * before our driver loaded. To make sure our driver 1639 * is awared of those exclusion ranges. 1640 */ 1641 schedule_delayed_work(&smu->wbrf_delayed_work, 1642 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1643 1644 return 0; 1645 } 1646 1647 /** 1648 * smu_wbrf_fini - tear down driver wbrf support 1649 * 1650 * @smu: smu_context pointer 1651 * 1652 * Unregisters with the wbrf notifier chain. 1653 */ 1654 static void smu_wbrf_fini(struct smu_context *smu) 1655 { 1656 if (!smu->wbrf_supported) 1657 return; 1658 1659 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1660 1661 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1662 } 1663 1664 static int smu_smc_hw_setup(struct smu_context *smu) 1665 { 1666 struct amdgpu_device *adev = smu->adev; 1667 uint8_t pcie_gen = 0, pcie_width = 0; 1668 struct smu_feature_bits features_supported; 1669 int ret = 0; 1670 1671 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1672 case IP_VERSION(11, 0, 7): 1673 case IP_VERSION(11, 0, 11): 1674 case IP_VERSION(11, 5, 0): 1675 case IP_VERSION(11, 5, 2): 1676 case IP_VERSION(11, 0, 12): 1677 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1678 dev_info(adev->dev, "dpm has been enabled\n"); 1679 ret = smu_system_features_control(smu, true); 1680 if (ret) { 1681 dev_err(adev->dev, "Failed system features control!\n"); 1682 return ret; 1683 } 1684 1685 return smu_enable_thermal_alert(smu); 1686 } 1687 break; 1688 default: 1689 break; 1690 } 1691 1692 ret = smu_init_display_count(smu, 0); 1693 if (ret) { 1694 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1695 return ret; 1696 } 1697 1698 ret = smu_set_driver_table_location(smu); 1699 if (ret) { 1700 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1701 return ret; 1702 } 1703 1704 /* 1705 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1706 */ 1707 ret = smu_set_tool_table_location(smu); 1708 if (ret) { 1709 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1710 return ret; 1711 } 1712 1713 /* 1714 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1715 * pool location. 1716 */ 1717 ret = smu_notify_memory_pool_location(smu); 1718 if (ret) { 1719 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1720 return ret; 1721 } 1722 1723 /* 1724 * It is assumed the pptable used before runpm is same as 1725 * the one used afterwards. Thus, we can reuse the stored 1726 * copy and do not need to resetup the pptable again. 1727 */ 1728 if (!adev->in_runpm) { 1729 ret = smu_setup_pptable(smu); 1730 if (ret) { 1731 dev_err(adev->dev, "Failed to setup pptable!\n"); 1732 return ret; 1733 } 1734 } 1735 1736 /* smu_dump_pptable(smu); */ 1737 1738 /* 1739 * With SCPM enabled, PSP is responsible for the PPTable transferring 1740 * (to SMU). Driver involvement is not needed and permitted. 1741 */ 1742 if (!adev->scpm_enabled) { 1743 /* 1744 * Copy pptable bo in the vram to smc with SMU MSGs such as 1745 * SetDriverDramAddr and TransferTableDram2Smu. 1746 */ 1747 ret = smu_write_pptable(smu); 1748 if (ret) { 1749 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1750 return ret; 1751 } 1752 } 1753 1754 /* issue Run*Btc msg */ 1755 ret = smu_run_btc(smu); 1756 if (ret) 1757 return ret; 1758 1759 /* Enable UclkShadow on wbrf supported */ 1760 if (smu->wbrf_supported) { 1761 ret = smu_enable_uclk_shadow(smu, true); 1762 if (ret) { 1763 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1764 return ret; 1765 } 1766 } 1767 1768 /* 1769 * With SCPM enabled, these actions(and relevant messages) are 1770 * not needed and permitted. 1771 */ 1772 if (!adev->scpm_enabled) { 1773 ret = smu_feature_set_allowed_mask(smu); 1774 if (ret) { 1775 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1776 return ret; 1777 } 1778 } 1779 1780 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1781 pcie_gen = 4; 1782 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1783 pcie_gen = 3; 1784 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1785 pcie_gen = 2; 1786 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1787 pcie_gen = 1; 1788 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1789 pcie_gen = 0; 1790 1791 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1792 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1793 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1794 */ 1795 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1796 pcie_width = 7; 1797 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1798 pcie_width = 6; 1799 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1800 pcie_width = 5; 1801 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1802 pcie_width = 4; 1803 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1804 pcie_width = 3; 1805 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1806 pcie_width = 2; 1807 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1808 pcie_width = 1; 1809 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1810 if (ret) { 1811 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1812 return ret; 1813 } 1814 1815 ret = smu_system_features_control(smu, true); 1816 if (ret) { 1817 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1818 return ret; 1819 } 1820 1821 smu_init_xgmi_plpd_mode(smu); 1822 1823 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1824 if (ret) { 1825 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1826 return ret; 1827 } 1828 smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, 1829 features_supported.bits); 1830 1831 if (!smu_is_dpm_running(smu)) 1832 dev_info(adev->dev, "dpm has been disabled\n"); 1833 1834 /* 1835 * Set initialized values (get from vbios) to dpm tables context such as 1836 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1837 * type of clks. 1838 */ 1839 ret = smu_set_default_dpm_table(smu); 1840 if (ret) { 1841 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1842 return ret; 1843 } 1844 1845 ret = smu_get_thermal_temperature_range(smu); 1846 if (ret) { 1847 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1848 return ret; 1849 } 1850 1851 ret = smu_enable_thermal_alert(smu); 1852 if (ret) { 1853 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1854 return ret; 1855 } 1856 1857 ret = smu_notify_display_change(smu); 1858 if (ret) { 1859 dev_err(adev->dev, "Failed to notify display change!\n"); 1860 return ret; 1861 } 1862 1863 /* 1864 * Set min deep sleep dce fclk with bootup value from vbios via 1865 * SetMinDeepSleepDcefclk MSG. 1866 */ 1867 ret = smu_set_min_dcef_deep_sleep(smu, 1868 smu->smu_table.boot_values.dcefclk / 100); 1869 if (ret) { 1870 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1871 return ret; 1872 } 1873 1874 /* Init wbrf support. Properly setup the notifier */ 1875 ret = smu_wbrf_init(smu); 1876 if (ret) 1877 dev_err(adev->dev, "Error during wbrf init call\n"); 1878 1879 return ret; 1880 } 1881 1882 static int smu_start_smc_engine(struct smu_context *smu) 1883 { 1884 struct amdgpu_device *adev = smu->adev; 1885 int ret = 0; 1886 1887 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1888 smu_update_gpu_addresses(smu); 1889 1890 smu->smc_fw_state = SMU_FW_INIT; 1891 1892 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1893 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1894 if (smu->ppt_funcs->load_microcode) { 1895 ret = smu->ppt_funcs->load_microcode(smu); 1896 if (ret) 1897 return ret; 1898 } 1899 } 1900 } 1901 1902 if (smu->ppt_funcs->check_fw_status) { 1903 ret = smu->ppt_funcs->check_fw_status(smu); 1904 if (ret) { 1905 dev_err(adev->dev, "SMC is not ready\n"); 1906 return ret; 1907 } 1908 } 1909 1910 /* 1911 * Send msg GetDriverIfVersion to check if the return value is equal 1912 * with DRIVER_IF_VERSION of smc header. 1913 */ 1914 ret = smu_check_fw_version(smu); 1915 if (ret) 1916 return ret; 1917 1918 return ret; 1919 } 1920 1921 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1922 { 1923 int i, ret; 1924 struct amdgpu_device *adev = ip_block->adev; 1925 struct smu_context *smu = adev->powerplay.pp_handle; 1926 1927 if (amdgpu_sriov_multi_vf_mode(adev)) { 1928 smu->pm_enabled = false; 1929 return 0; 1930 } 1931 1932 ret = smu_start_smc_engine(smu); 1933 if (ret) { 1934 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1935 return ret; 1936 } 1937 1938 /* 1939 * Check whether wbrf is supported. This needs to be done 1940 * before SMU setup starts since part of SMU configuration 1941 * relies on this. 1942 */ 1943 smu_wbrf_support_check(smu); 1944 1945 if (smu->is_apu) { 1946 ret = smu_set_gfx_imu_enable(smu); 1947 if (ret) 1948 return ret; 1949 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1950 smu_dpm_set_vcn_enable(smu, true, i); 1951 smu_dpm_set_jpeg_enable(smu, true); 1952 smu_dpm_set_umsch_mm_enable(smu, true); 1953 smu_set_mall_enable(smu); 1954 smu_set_gfx_cgpg(smu, true); 1955 } 1956 1957 if (!smu->pm_enabled) 1958 return 0; 1959 1960 ret = smu_init_driver_allowed_feature_mask(smu); 1961 if (ret) 1962 return ret; 1963 1964 ret = smu_smc_hw_setup(smu); 1965 if (ret) { 1966 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1967 return ret; 1968 } 1969 1970 /* 1971 * Move maximum sustainable clock retrieving here considering 1972 * 1. It is not needed on resume(from S3). 1973 * 2. DAL settings come between .hw_init and .late_init of SMU. 1974 * And DAL needs to know the maximum sustainable clocks. Thus 1975 * it cannot be put in .late_init(). 1976 */ 1977 ret = smu_init_max_sustainable_clocks(smu); 1978 if (ret) { 1979 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1980 return ret; 1981 } 1982 1983 adev->pm.dpm_enabled = true; 1984 1985 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1986 1987 return 0; 1988 } 1989 1990 static int smu_disable_dpms(struct smu_context *smu) 1991 { 1992 struct amdgpu_device *adev = smu->adev; 1993 int ret = 0; 1994 bool use_baco = !smu->is_apu && 1995 ((amdgpu_in_reset(adev) && 1996 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1997 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1998 1999 /* 2000 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 2001 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 2002 */ 2003 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2004 case IP_VERSION(13, 0, 0): 2005 case IP_VERSION(13, 0, 7): 2006 case IP_VERSION(13, 0, 10): 2007 case IP_VERSION(14, 0, 2): 2008 case IP_VERSION(14, 0, 3): 2009 return 0; 2010 default: 2011 break; 2012 } 2013 2014 /* 2015 * For custom pptable uploading, skip the DPM features 2016 * disable process on Navi1x ASICs. 2017 * - As the gfx related features are under control of 2018 * RLC on those ASICs. RLC reinitialization will be 2019 * needed to reenable them. That will cost much more 2020 * efforts. 2021 * 2022 * - SMU firmware can handle the DPM reenablement 2023 * properly. 2024 */ 2025 if (smu->uploading_custom_pp_table) { 2026 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2027 case IP_VERSION(11, 0, 0): 2028 case IP_VERSION(11, 0, 5): 2029 case IP_VERSION(11, 0, 9): 2030 case IP_VERSION(11, 0, 7): 2031 case IP_VERSION(11, 0, 11): 2032 case IP_VERSION(11, 5, 0): 2033 case IP_VERSION(11, 5, 2): 2034 case IP_VERSION(11, 0, 12): 2035 case IP_VERSION(11, 0, 13): 2036 return 0; 2037 default: 2038 break; 2039 } 2040 } 2041 2042 /* 2043 * For Sienna_Cichlid, PMFW will handle the features disablement properly 2044 * on BACO in. Driver involvement is unnecessary. 2045 */ 2046 if (use_baco) { 2047 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2048 case IP_VERSION(11, 0, 7): 2049 case IP_VERSION(11, 0, 0): 2050 case IP_VERSION(11, 0, 5): 2051 case IP_VERSION(11, 0, 9): 2052 case IP_VERSION(13, 0, 7): 2053 return 0; 2054 default: 2055 break; 2056 } 2057 } 2058 2059 /* 2060 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 2061 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 2062 */ 2063 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 2064 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2065 return 0; 2066 2067 /* vangogh s0ix */ 2068 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2069 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2070 adev->in_s0ix) 2071 return 0; 2072 2073 /* 2074 * For gpu reset, runpm and hibernation through BACO, 2075 * BACO feature has to be kept enabled. 2076 */ 2077 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 2078 ret = smu_disable_all_features_with_exception(smu, 2079 SMU_FEATURE_BACO_BIT); 2080 if (ret) 2081 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 2082 } else { 2083 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 2084 if (!adev->scpm_enabled) { 2085 ret = smu_system_features_control(smu, false); 2086 if (ret) 2087 dev_err(adev->dev, "Failed to disable smu features.\n"); 2088 } 2089 } 2090 2091 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 2092 * otherwise SMU will hang while interacting with RLC if RLC is halted 2093 * this is a WA for Vangogh asic which fix the SMU hang issue. 2094 */ 2095 ret = smu_notify_rlc_state(smu, false); 2096 if (ret) { 2097 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2098 return ret; 2099 } 2100 2101 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2102 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2103 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2104 adev->gfx.rlc.funcs->stop(adev); 2105 2106 return ret; 2107 } 2108 2109 static int smu_smc_hw_cleanup(struct smu_context *smu) 2110 { 2111 struct amdgpu_device *adev = smu->adev; 2112 int ret = 0; 2113 2114 smu_wbrf_fini(smu); 2115 2116 cancel_work_sync(&smu->throttling_logging_work); 2117 cancel_work_sync(&smu->interrupt_work); 2118 2119 ret = smu_disable_thermal_alert(smu); 2120 if (ret) { 2121 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2122 return ret; 2123 } 2124 2125 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2126 2127 ret = smu_disable_dpms(smu); 2128 if (ret) { 2129 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2130 return ret; 2131 } 2132 2133 return 0; 2134 } 2135 2136 static int smu_reset_mp1_state(struct smu_context *smu) 2137 { 2138 struct amdgpu_device *adev = smu->adev; 2139 int ret = 0; 2140 2141 if ((!adev->in_runpm) && (!adev->in_suspend) && 2142 (!amdgpu_in_reset(adev)) && !smu->is_apu && 2143 amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0)) 2144 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2145 2146 return ret; 2147 } 2148 2149 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2150 { 2151 struct amdgpu_device *adev = ip_block->adev; 2152 struct smu_context *smu = adev->powerplay.pp_handle; 2153 int i, ret; 2154 2155 if (amdgpu_sriov_multi_vf_mode(adev)) 2156 return 0; 2157 2158 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2159 smu_dpm_set_vcn_enable(smu, false, i); 2160 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2161 } 2162 smu_dpm_set_jpeg_enable(smu, false); 2163 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2164 smu_dpm_set_umsch_mm_enable(smu, false); 2165 2166 if (!smu->pm_enabled) 2167 return 0; 2168 2169 adev->pm.dpm_enabled = false; 2170 2171 ret = smu_smc_hw_cleanup(smu); 2172 if (ret) 2173 return ret; 2174 2175 ret = smu_reset_mp1_state(smu); 2176 if (ret) 2177 return ret; 2178 2179 return 0; 2180 } 2181 2182 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2183 { 2184 struct amdgpu_device *adev = ip_block->adev; 2185 struct smu_context *smu = adev->powerplay.pp_handle; 2186 2187 kfree(smu); 2188 } 2189 2190 static int smu_reset(struct smu_context *smu) 2191 { 2192 struct amdgpu_device *adev = smu->adev; 2193 struct amdgpu_ip_block *ip_block; 2194 int ret; 2195 2196 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2197 if (!ip_block) 2198 return -EINVAL; 2199 2200 ret = smu_hw_fini(ip_block); 2201 if (ret) 2202 return ret; 2203 2204 ret = smu_hw_init(ip_block); 2205 if (ret) 2206 return ret; 2207 2208 ret = smu_late_init(ip_block); 2209 if (ret) 2210 return ret; 2211 2212 return 0; 2213 } 2214 2215 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2216 { 2217 struct amdgpu_device *adev = ip_block->adev; 2218 struct smu_context *smu = adev->powerplay.pp_handle; 2219 int ret; 2220 uint64_t count; 2221 2222 if (amdgpu_sriov_multi_vf_mode(adev)) 2223 return 0; 2224 2225 if (!smu->pm_enabled) 2226 return 0; 2227 2228 adev->pm.dpm_enabled = false; 2229 2230 ret = smu_smc_hw_cleanup(smu); 2231 if (ret) 2232 return ret; 2233 2234 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2235 2236 smu_set_gfx_cgpg(smu, false); 2237 2238 /* 2239 * pwfw resets entrycount when device is suspended, so we save the 2240 * last value to be used when we resume to keep it consistent 2241 */ 2242 ret = smu_get_entrycount_gfxoff(smu, &count); 2243 if (!ret) 2244 adev->gfx.gfx_off_entrycount = count; 2245 2246 /* clear this on suspend so it will get reprogrammed on resume */ 2247 smu->workload_mask = 0; 2248 2249 return 0; 2250 } 2251 2252 static int smu_resume(struct amdgpu_ip_block *ip_block) 2253 { 2254 int ret; 2255 struct amdgpu_device *adev = ip_block->adev; 2256 struct smu_context *smu = adev->powerplay.pp_handle; 2257 2258 if (amdgpu_sriov_multi_vf_mode(adev)) 2259 return 0; 2260 2261 if (!smu->pm_enabled) 2262 return 0; 2263 2264 dev_info(adev->dev, "SMU is resuming...\n"); 2265 2266 ret = smu_start_smc_engine(smu); 2267 if (ret) { 2268 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2269 return ret; 2270 } 2271 2272 ret = smu_smc_hw_setup(smu); 2273 if (ret) { 2274 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2275 return ret; 2276 } 2277 2278 ret = smu_set_gfx_imu_enable(smu); 2279 if (ret) 2280 return ret; 2281 2282 smu_set_gfx_cgpg(smu, true); 2283 2284 smu->disable_uclk_switch = 0; 2285 2286 adev->pm.dpm_enabled = true; 2287 2288 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2289 2290 return 0; 2291 } 2292 2293 static int smu_display_configuration_change(void *handle, 2294 const struct amd_pp_display_configuration *display_config) 2295 { 2296 struct smu_context *smu = handle; 2297 2298 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2299 return -EOPNOTSUPP; 2300 2301 if (!display_config) 2302 return -EINVAL; 2303 2304 smu_set_min_dcef_deep_sleep(smu, 2305 display_config->min_dcef_deep_sleep_set_clk / 100); 2306 2307 return 0; 2308 } 2309 2310 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2311 enum amd_clockgating_state state) 2312 { 2313 return 0; 2314 } 2315 2316 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2317 enum amd_powergating_state state) 2318 { 2319 return 0; 2320 } 2321 2322 static int smu_enable_umd_pstate(void *handle, 2323 enum amd_dpm_forced_level *level) 2324 { 2325 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2326 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2327 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2328 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2329 2330 struct smu_context *smu = (struct smu_context*)(handle); 2331 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2332 2333 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2334 return -EINVAL; 2335 2336 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2337 /* enter umd pstate, save current level, disable gfx cg*/ 2338 if (*level & profile_mode_mask) { 2339 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2340 smu_gpo_control(smu, false); 2341 smu_gfx_ulv_control(smu, false); 2342 smu_deep_sleep_control(smu, false); 2343 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2344 } 2345 } else { 2346 /* exit umd pstate, restore level, enable gfx cg*/ 2347 if (!(*level & profile_mode_mask)) { 2348 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2349 *level = smu_dpm_ctx->saved_dpm_level; 2350 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2351 smu_deep_sleep_control(smu, true); 2352 smu_gfx_ulv_control(smu, true); 2353 smu_gpo_control(smu, true); 2354 } 2355 } 2356 2357 return 0; 2358 } 2359 2360 static int smu_bump_power_profile_mode(struct smu_context *smu, 2361 long *custom_params, 2362 u32 custom_params_max_idx) 2363 { 2364 u32 workload_mask = 0; 2365 int i, ret = 0; 2366 2367 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2368 if (smu->workload_refcount[i]) 2369 workload_mask |= 1 << i; 2370 } 2371 2372 if (smu->workload_mask == workload_mask) 2373 return 0; 2374 2375 if (smu->ppt_funcs->set_power_profile_mode) 2376 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2377 custom_params, 2378 custom_params_max_idx); 2379 2380 if (!ret) 2381 smu->workload_mask = workload_mask; 2382 2383 return ret; 2384 } 2385 2386 static void smu_power_profile_mode_get(struct smu_context *smu, 2387 enum PP_SMC_POWER_PROFILE profile_mode) 2388 { 2389 smu->workload_refcount[profile_mode]++; 2390 } 2391 2392 static void smu_power_profile_mode_put(struct smu_context *smu, 2393 enum PP_SMC_POWER_PROFILE profile_mode) 2394 { 2395 if (smu->workload_refcount[profile_mode]) 2396 smu->workload_refcount[profile_mode]--; 2397 } 2398 2399 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2400 enum amd_dpm_forced_level level, 2401 bool skip_display_settings) 2402 { 2403 int ret = 0; 2404 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2405 2406 if (!skip_display_settings) { 2407 ret = smu_display_config_changed(smu); 2408 if (ret) { 2409 dev_err(smu->adev->dev, "Failed to change display config!"); 2410 return ret; 2411 } 2412 } 2413 2414 ret = smu_apply_clocks_adjust_rules(smu); 2415 if (ret) { 2416 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2417 return ret; 2418 } 2419 2420 if (!skip_display_settings) { 2421 ret = smu_notify_smc_display_config(smu); 2422 if (ret) { 2423 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2424 return ret; 2425 } 2426 } 2427 2428 if (smu_dpm_ctx->dpm_level != level) { 2429 ret = smu_asic_set_performance_level(smu, level); 2430 if (ret) { 2431 if (ret == -EOPNOTSUPP) 2432 dev_info(smu->adev->dev, "set performance level %d not supported", 2433 level); 2434 else 2435 dev_err(smu->adev->dev, "Failed to set performance level %d", 2436 level); 2437 return ret; 2438 } 2439 2440 /* update the saved copy */ 2441 smu_dpm_ctx->dpm_level = level; 2442 } 2443 2444 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2445 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2446 smu_bump_power_profile_mode(smu, NULL, 0); 2447 2448 return ret; 2449 } 2450 2451 static int smu_handle_task(struct smu_context *smu, 2452 enum amd_dpm_forced_level level, 2453 enum amd_pp_task task_id) 2454 { 2455 int ret = 0; 2456 2457 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2458 return -EOPNOTSUPP; 2459 2460 switch (task_id) { 2461 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2462 ret = smu_pre_display_config_changed(smu); 2463 if (ret) 2464 return ret; 2465 ret = smu_adjust_power_state_dynamic(smu, level, false); 2466 break; 2467 case AMD_PP_TASK_COMPLETE_INIT: 2468 ret = smu_adjust_power_state_dynamic(smu, level, true); 2469 break; 2470 case AMD_PP_TASK_READJUST_POWER_STATE: 2471 ret = smu_adjust_power_state_dynamic(smu, level, true); 2472 break; 2473 default: 2474 break; 2475 } 2476 2477 return ret; 2478 } 2479 2480 static int smu_handle_dpm_task(void *handle, 2481 enum amd_pp_task task_id, 2482 enum amd_pm_state_type *user_state) 2483 { 2484 struct smu_context *smu = handle; 2485 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2486 2487 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2488 2489 } 2490 2491 static int smu_switch_power_profile(void *handle, 2492 enum PP_SMC_POWER_PROFILE type, 2493 bool enable) 2494 { 2495 struct smu_context *smu = handle; 2496 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2497 int ret; 2498 2499 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2500 return -EOPNOTSUPP; 2501 2502 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2503 return -EINVAL; 2504 2505 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2506 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2507 if (enable) 2508 smu_power_profile_mode_get(smu, type); 2509 else 2510 smu_power_profile_mode_put(smu, type); 2511 /* don't switch the active workload when paused */ 2512 if (smu->pause_workload) 2513 ret = 0; 2514 else 2515 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2516 if (ret) { 2517 if (enable) 2518 smu_power_profile_mode_put(smu, type); 2519 else 2520 smu_power_profile_mode_get(smu, type); 2521 return ret; 2522 } 2523 } 2524 2525 return 0; 2526 } 2527 2528 static int smu_pause_power_profile(void *handle, 2529 bool pause) 2530 { 2531 struct smu_context *smu = handle; 2532 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2533 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2534 int ret; 2535 2536 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2537 return -EOPNOTSUPP; 2538 2539 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2540 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2541 smu->pause_workload = pause; 2542 2543 /* force to bootup default profile */ 2544 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2545 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2546 workload_mask, 2547 NULL, 2548 0); 2549 else 2550 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2551 return ret; 2552 } 2553 2554 return 0; 2555 } 2556 2557 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2558 { 2559 struct smu_context *smu = handle; 2560 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2561 2562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2563 return -EOPNOTSUPP; 2564 2565 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2566 return -EINVAL; 2567 2568 return smu_dpm_ctx->dpm_level; 2569 } 2570 2571 static int smu_force_performance_level(void *handle, 2572 enum amd_dpm_forced_level level) 2573 { 2574 struct smu_context *smu = handle; 2575 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2576 int ret = 0; 2577 2578 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2579 return -EOPNOTSUPP; 2580 2581 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2582 return -EINVAL; 2583 2584 ret = smu_enable_umd_pstate(smu, &level); 2585 if (ret) 2586 return ret; 2587 2588 ret = smu_handle_task(smu, level, 2589 AMD_PP_TASK_READJUST_POWER_STATE); 2590 2591 /* reset user dpm clock state */ 2592 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2593 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2594 smu->user_dpm_profile.clk_dependency = 0; 2595 } 2596 2597 return ret; 2598 } 2599 2600 static int smu_set_display_count(void *handle, uint32_t count) 2601 { 2602 struct smu_context *smu = handle; 2603 2604 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2605 return -EOPNOTSUPP; 2606 2607 return smu_init_display_count(smu, count); 2608 } 2609 2610 static int smu_force_smuclk_levels(struct smu_context *smu, 2611 enum smu_clk_type clk_type, 2612 uint32_t mask) 2613 { 2614 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2615 int ret = 0; 2616 2617 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2618 return -EOPNOTSUPP; 2619 2620 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2621 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2622 return -EINVAL; 2623 } 2624 2625 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2626 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2627 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2628 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2629 smu_set_user_clk_dependencies(smu, clk_type); 2630 } 2631 } 2632 2633 return ret; 2634 } 2635 2636 static int smu_force_ppclk_levels(void *handle, 2637 enum pp_clock_type type, 2638 uint32_t mask) 2639 { 2640 struct smu_context *smu = handle; 2641 enum smu_clk_type clk_type; 2642 2643 switch (type) { 2644 case PP_SCLK: 2645 clk_type = SMU_SCLK; break; 2646 case PP_MCLK: 2647 clk_type = SMU_MCLK; break; 2648 case PP_PCIE: 2649 clk_type = SMU_PCIE; break; 2650 case PP_SOCCLK: 2651 clk_type = SMU_SOCCLK; break; 2652 case PP_FCLK: 2653 clk_type = SMU_FCLK; break; 2654 case PP_DCEFCLK: 2655 clk_type = SMU_DCEFCLK; break; 2656 case PP_VCLK: 2657 clk_type = SMU_VCLK; break; 2658 case PP_VCLK1: 2659 clk_type = SMU_VCLK1; break; 2660 case PP_DCLK: 2661 clk_type = SMU_DCLK; break; 2662 case PP_DCLK1: 2663 clk_type = SMU_DCLK1; break; 2664 case OD_SCLK: 2665 clk_type = SMU_OD_SCLK; break; 2666 case OD_MCLK: 2667 clk_type = SMU_OD_MCLK; break; 2668 case OD_VDDC_CURVE: 2669 clk_type = SMU_OD_VDDC_CURVE; break; 2670 case OD_RANGE: 2671 clk_type = SMU_OD_RANGE; break; 2672 default: 2673 return -EINVAL; 2674 } 2675 2676 return smu_force_smuclk_levels(smu, clk_type, mask); 2677 } 2678 2679 /* 2680 * On system suspending or resetting, the dpm_enabled 2681 * flag will be cleared. So that those SMU services which 2682 * are not supported will be gated. 2683 * However, the mp1 state setting should still be granted 2684 * even if the dpm_enabled cleared. 2685 */ 2686 static int smu_set_mp1_state(void *handle, 2687 enum pp_mp1_state mp1_state) 2688 { 2689 struct smu_context *smu = handle; 2690 int ret = 0; 2691 2692 if (!smu->pm_enabled) 2693 return -EOPNOTSUPP; 2694 2695 if (smu->ppt_funcs && 2696 smu->ppt_funcs->set_mp1_state) 2697 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2698 2699 return ret; 2700 } 2701 2702 static int smu_set_df_cstate(void *handle, 2703 enum pp_df_cstate state) 2704 { 2705 struct smu_context *smu = handle; 2706 int ret = 0; 2707 2708 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2709 return -EOPNOTSUPP; 2710 2711 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2712 return 0; 2713 2714 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2715 if (ret) 2716 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2717 2718 return ret; 2719 } 2720 2721 int smu_write_watermarks_table(struct smu_context *smu) 2722 { 2723 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2724 return -EOPNOTSUPP; 2725 2726 return smu_set_watermarks_table(smu, NULL); 2727 } 2728 2729 static int smu_set_watermarks_for_clock_ranges(void *handle, 2730 struct pp_smu_wm_range_sets *clock_ranges) 2731 { 2732 struct smu_context *smu = handle; 2733 2734 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2735 return -EOPNOTSUPP; 2736 2737 if (smu->disable_watermark) 2738 return 0; 2739 2740 return smu_set_watermarks_table(smu, clock_ranges); 2741 } 2742 2743 int smu_set_ac_dc(struct smu_context *smu) 2744 { 2745 int ret = 0; 2746 2747 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2748 return -EOPNOTSUPP; 2749 2750 /* controlled by firmware */ 2751 if (smu->dc_controlled_by_gpio) 2752 return 0; 2753 2754 ret = smu_set_power_source(smu, 2755 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2756 SMU_POWER_SOURCE_DC); 2757 if (ret) 2758 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2759 smu->adev->pm.ac_power ? "AC" : "DC"); 2760 2761 return ret; 2762 } 2763 2764 const struct amd_ip_funcs smu_ip_funcs = { 2765 .name = "smu", 2766 .early_init = smu_early_init, 2767 .late_init = smu_late_init, 2768 .sw_init = smu_sw_init, 2769 .sw_fini = smu_sw_fini, 2770 .hw_init = smu_hw_init, 2771 .hw_fini = smu_hw_fini, 2772 .late_fini = smu_late_fini, 2773 .suspend = smu_suspend, 2774 .resume = smu_resume, 2775 .is_idle = NULL, 2776 .check_soft_reset = NULL, 2777 .wait_for_idle = NULL, 2778 .soft_reset = NULL, 2779 .set_clockgating_state = smu_set_clockgating_state, 2780 .set_powergating_state = smu_set_powergating_state, 2781 }; 2782 2783 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2784 .type = AMD_IP_BLOCK_TYPE_SMC, 2785 .major = 11, 2786 .minor = 0, 2787 .rev = 0, 2788 .funcs = &smu_ip_funcs, 2789 }; 2790 2791 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2792 .type = AMD_IP_BLOCK_TYPE_SMC, 2793 .major = 12, 2794 .minor = 0, 2795 .rev = 0, 2796 .funcs = &smu_ip_funcs, 2797 }; 2798 2799 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2800 .type = AMD_IP_BLOCK_TYPE_SMC, 2801 .major = 13, 2802 .minor = 0, 2803 .rev = 0, 2804 .funcs = &smu_ip_funcs, 2805 }; 2806 2807 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2808 .type = AMD_IP_BLOCK_TYPE_SMC, 2809 .major = 14, 2810 .minor = 0, 2811 .rev = 0, 2812 .funcs = &smu_ip_funcs, 2813 }; 2814 2815 const struct amdgpu_ip_block_version smu_v15_0_ip_block = { 2816 .type = AMD_IP_BLOCK_TYPE_SMC, 2817 .major = 15, 2818 .minor = 0, 2819 .rev = 0, 2820 .funcs = &smu_ip_funcs, 2821 }; 2822 2823 const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) 2824 { 2825 struct smu_context *smu = (struct smu_context *)handle; 2826 const struct ras_smu_drv *tmp = NULL; 2827 int ret; 2828 2829 ret = smu_get_ras_smu_drv(smu, &tmp); 2830 2831 return ret ? NULL : tmp; 2832 } 2833 2834 static int smu_load_microcode(void *handle) 2835 { 2836 struct smu_context *smu = handle; 2837 struct amdgpu_device *adev = smu->adev; 2838 int ret = 0; 2839 2840 if (!smu->pm_enabled) 2841 return -EOPNOTSUPP; 2842 2843 /* This should be used for non PSP loading */ 2844 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2845 return 0; 2846 2847 if (smu->ppt_funcs->load_microcode) { 2848 ret = smu->ppt_funcs->load_microcode(smu); 2849 if (ret) { 2850 dev_err(adev->dev, "Load microcode failed\n"); 2851 return ret; 2852 } 2853 } 2854 2855 if (smu->ppt_funcs->check_fw_status) { 2856 ret = smu->ppt_funcs->check_fw_status(smu); 2857 if (ret) { 2858 dev_err(adev->dev, "SMC is not ready\n"); 2859 return ret; 2860 } 2861 } 2862 2863 return ret; 2864 } 2865 2866 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2867 { 2868 int ret = 0; 2869 2870 if (smu->ppt_funcs->set_gfx_cgpg) 2871 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2872 2873 return ret; 2874 } 2875 2876 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2877 { 2878 struct smu_context *smu = handle; 2879 int ret = 0; 2880 2881 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2882 return -EOPNOTSUPP; 2883 2884 if (!smu->ppt_funcs->set_fan_speed_rpm) 2885 return -EOPNOTSUPP; 2886 2887 if (speed == U32_MAX) 2888 return -EINVAL; 2889 2890 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2891 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2892 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2893 smu->user_dpm_profile.fan_speed_rpm = speed; 2894 2895 /* Override custom PWM setting as they cannot co-exist */ 2896 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2897 smu->user_dpm_profile.fan_speed_pwm = 0; 2898 } 2899 2900 return ret; 2901 } 2902 2903 /** 2904 * smu_get_power_limit - Request one of the SMU Power Limits 2905 * 2906 * @handle: pointer to smu context 2907 * @limit: requested limit is written back to this variable 2908 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2909 * @pp_power_type: &pp_power_type type of power 2910 * Return: 0 on success, <0 on error 2911 * 2912 */ 2913 int smu_get_power_limit(void *handle, 2914 uint32_t *limit, 2915 enum pp_power_limit_level pp_limit_level, 2916 enum pp_power_type pp_power_type) 2917 { 2918 struct smu_context *smu = handle; 2919 struct amdgpu_device *adev = smu->adev; 2920 enum smu_ppt_limit_level limit_level; 2921 uint32_t limit_type; 2922 int ret = 0; 2923 2924 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2925 return -EOPNOTSUPP; 2926 2927 if (!limit) 2928 return -EINVAL; 2929 2930 switch (pp_power_type) { 2931 case PP_PWR_TYPE_SUSTAINED: 2932 limit_type = SMU_DEFAULT_PPT_LIMIT; 2933 break; 2934 case PP_PWR_TYPE_FAST: 2935 limit_type = SMU_FAST_PPT_LIMIT; 2936 break; 2937 default: 2938 return -EOPNOTSUPP; 2939 } 2940 2941 switch (pp_limit_level) { 2942 case PP_PWR_LIMIT_CURRENT: 2943 limit_level = SMU_PPT_LIMIT_CURRENT; 2944 break; 2945 case PP_PWR_LIMIT_DEFAULT: 2946 limit_level = SMU_PPT_LIMIT_DEFAULT; 2947 break; 2948 case PP_PWR_LIMIT_MAX: 2949 limit_level = SMU_PPT_LIMIT_MAX; 2950 break; 2951 case PP_PWR_LIMIT_MIN: 2952 limit_level = SMU_PPT_LIMIT_MIN; 2953 break; 2954 default: 2955 return -EOPNOTSUPP; 2956 } 2957 2958 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2959 if (smu->ppt_funcs->get_ppt_limit) 2960 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2961 else 2962 return -EOPNOTSUPP; 2963 } else { 2964 switch (limit_level) { 2965 case SMU_PPT_LIMIT_CURRENT: 2966 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2967 case IP_VERSION(13, 0, 2): 2968 case IP_VERSION(13, 0, 6): 2969 case IP_VERSION(13, 0, 12): 2970 case IP_VERSION(13, 0, 14): 2971 case IP_VERSION(11, 0, 7): 2972 case IP_VERSION(11, 0, 11): 2973 case IP_VERSION(11, 0, 12): 2974 case IP_VERSION(11, 0, 13): 2975 case IP_VERSION(15, 0, 8): 2976 ret = smu_get_asic_power_limits(smu, 2977 &smu->current_power_limit, 2978 NULL, NULL, NULL); 2979 break; 2980 default: 2981 break; 2982 } 2983 *limit = smu->current_power_limit; 2984 break; 2985 case SMU_PPT_LIMIT_DEFAULT: 2986 *limit = smu->default_power_limit; 2987 break; 2988 case SMU_PPT_LIMIT_MAX: 2989 *limit = smu->max_power_limit; 2990 break; 2991 case SMU_PPT_LIMIT_MIN: 2992 *limit = smu->min_power_limit; 2993 break; 2994 default: 2995 return -EINVAL; 2996 } 2997 } 2998 2999 return ret; 3000 } 3001 3002 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 3003 { 3004 struct smu_context *smu = handle; 3005 int ret = 0; 3006 3007 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3008 return -EOPNOTSUPP; 3009 3010 if (limit_type == SMU_DEFAULT_PPT_LIMIT) { 3011 if (!limit) 3012 limit = smu->current_power_limit; 3013 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 3014 dev_err(smu->adev->dev, 3015 "New power limit (%d) is out of range [%d,%d]\n", 3016 limit, smu->min_power_limit, smu->max_power_limit); 3017 return -EINVAL; 3018 } 3019 } 3020 3021 if (smu->ppt_funcs->set_power_limit) { 3022 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 3023 if (ret) 3024 return ret; 3025 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 3026 smu->user_dpm_profile.power_limits[limit_type] = limit; 3027 } 3028 3029 return 0; 3030 } 3031 3032 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 3033 { 3034 enum smu_clk_type clk_type; 3035 3036 switch (type) { 3037 case PP_SCLK: 3038 clk_type = SMU_SCLK; break; 3039 case PP_MCLK: 3040 clk_type = SMU_MCLK; break; 3041 case PP_PCIE: 3042 clk_type = SMU_PCIE; break; 3043 case PP_SOCCLK: 3044 clk_type = SMU_SOCCLK; break; 3045 case PP_FCLK: 3046 clk_type = SMU_FCLK; break; 3047 case PP_DCEFCLK: 3048 clk_type = SMU_DCEFCLK; break; 3049 case PP_VCLK: 3050 clk_type = SMU_VCLK; break; 3051 case PP_VCLK1: 3052 clk_type = SMU_VCLK1; break; 3053 case PP_DCLK: 3054 clk_type = SMU_DCLK; break; 3055 case PP_DCLK1: 3056 clk_type = SMU_DCLK1; break; 3057 case PP_ISPICLK: 3058 clk_type = SMU_ISPICLK; 3059 break; 3060 case PP_ISPXCLK: 3061 clk_type = SMU_ISPXCLK; 3062 break; 3063 case OD_SCLK: 3064 clk_type = SMU_OD_SCLK; break; 3065 case OD_MCLK: 3066 clk_type = SMU_OD_MCLK; break; 3067 case OD_FCLK: 3068 clk_type = SMU_OD_FCLK; break; 3069 case OD_VDDC_CURVE: 3070 clk_type = SMU_OD_VDDC_CURVE; break; 3071 case OD_RANGE: 3072 clk_type = SMU_OD_RANGE; break; 3073 case OD_VDDGFX_OFFSET: 3074 clk_type = SMU_OD_VDDGFX_OFFSET; break; 3075 case OD_CCLK: 3076 clk_type = SMU_OD_CCLK; break; 3077 case OD_FAN_CURVE: 3078 clk_type = SMU_OD_FAN_CURVE; break; 3079 case OD_ACOUSTIC_LIMIT: 3080 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 3081 case OD_ACOUSTIC_TARGET: 3082 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 3083 case OD_FAN_TARGET_TEMPERATURE: 3084 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 3085 case OD_FAN_MINIMUM_PWM: 3086 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 3087 case OD_FAN_ZERO_RPM_ENABLE: 3088 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 3089 case OD_FAN_ZERO_RPM_STOP_TEMP: 3090 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 3091 default: 3092 clk_type = SMU_CLK_COUNT; break; 3093 } 3094 3095 return clk_type; 3096 } 3097 3098 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3099 { 3100 struct smu_context *smu = handle; 3101 enum smu_clk_type clk_type; 3102 3103 clk_type = smu_convert_to_smuclk(type); 3104 if (clk_type == SMU_CLK_COUNT) 3105 return -EINVAL; 3106 3107 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3108 return -EOPNOTSUPP; 3109 3110 if (!smu->ppt_funcs->emit_clk_levels) 3111 return -ENOENT; 3112 3113 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3114 3115 } 3116 3117 static int smu_od_edit_dpm_table(void *handle, 3118 enum PP_OD_DPM_TABLE_COMMAND type, 3119 long *input, uint32_t size) 3120 { 3121 struct smu_context *smu = handle; 3122 int ret = 0; 3123 3124 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3125 return -EOPNOTSUPP; 3126 3127 if (smu->ppt_funcs->od_edit_dpm_table) { 3128 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3129 } 3130 3131 return ret; 3132 } 3133 3134 static int smu_read_sensor(void *handle, 3135 int sensor, 3136 void *data, 3137 int *size_arg) 3138 { 3139 struct smu_context *smu = handle; 3140 struct amdgpu_device *adev = smu->adev; 3141 struct smu_umd_pstate_table *pstate_table = 3142 &smu->pstate_table; 3143 int i, ret = 0; 3144 uint32_t *size, size_val; 3145 3146 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3147 return -EOPNOTSUPP; 3148 3149 if (!data || !size_arg) 3150 return -EINVAL; 3151 3152 size_val = *size_arg; 3153 size = &size_val; 3154 3155 if (smu->ppt_funcs->read_sensor) 3156 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3157 goto unlock; 3158 3159 switch (sensor) { 3160 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3161 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3162 *size = 4; 3163 break; 3164 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3165 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3166 *size = 4; 3167 break; 3168 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3169 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3170 *size = 4; 3171 break; 3172 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3173 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3174 *size = 4; 3175 break; 3176 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: { 3177 struct smu_feature_bits feature_mask; 3178 uint32_t features[2]; 3179 3180 /* TBD: need to handle for > 64 bits */ 3181 ret = smu_feature_get_enabled_mask(smu, &feature_mask); 3182 if (!ret) { 3183 smu_feature_bits_to_arr32(&feature_mask, features, 64); 3184 *(uint64_t *)data = *(uint64_t *)features; 3185 } 3186 *size = 8; 3187 break; 3188 } 3189 case AMDGPU_PP_SENSOR_UVD_POWER: 3190 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3191 *size = 4; 3192 break; 3193 case AMDGPU_PP_SENSOR_VCE_POWER: 3194 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3195 *size = 4; 3196 break; 3197 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3198 *(uint32_t *)data = 0; 3199 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3200 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3201 *(uint32_t *)data = 1; 3202 break; 3203 } 3204 } 3205 *size = 4; 3206 break; 3207 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3208 *(uint32_t *)data = 0; 3209 *size = 4; 3210 break; 3211 default: 3212 *size = 0; 3213 ret = -EOPNOTSUPP; 3214 break; 3215 } 3216 3217 unlock: 3218 // assign uint32_t to int 3219 *size_arg = size_val; 3220 3221 return ret; 3222 } 3223 3224 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3225 { 3226 int ret = -EOPNOTSUPP; 3227 struct smu_context *smu = handle; 3228 3229 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3230 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3231 3232 return ret; 3233 } 3234 3235 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3236 { 3237 int ret = -EOPNOTSUPP; 3238 struct smu_context *smu = handle; 3239 3240 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3241 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3242 3243 return ret; 3244 } 3245 3246 static int smu_get_power_profile_mode(void *handle, char *buf) 3247 { 3248 struct smu_context *smu = handle; 3249 3250 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3251 !smu->ppt_funcs->get_power_profile_mode) 3252 return -EOPNOTSUPP; 3253 if (!buf) 3254 return -EINVAL; 3255 3256 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3257 } 3258 3259 static int smu_set_power_profile_mode(void *handle, 3260 long *param, 3261 uint32_t param_size) 3262 { 3263 struct smu_context *smu = handle; 3264 bool custom = false; 3265 int ret = 0; 3266 3267 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3268 !smu->ppt_funcs->set_power_profile_mode) 3269 return -EOPNOTSUPP; 3270 3271 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3272 custom = true; 3273 /* clear frontend mask so custom changes propogate */ 3274 smu->workload_mask = 0; 3275 } 3276 3277 if ((param[param_size] != smu->power_profile_mode) || custom) { 3278 /* clear the old user preference */ 3279 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3280 /* set the new user preference */ 3281 smu_power_profile_mode_get(smu, param[param_size]); 3282 ret = smu_bump_power_profile_mode(smu, 3283 custom ? param : NULL, 3284 custom ? param_size : 0); 3285 if (ret) 3286 smu_power_profile_mode_put(smu, param[param_size]); 3287 else 3288 /* store the user's preference */ 3289 smu->power_profile_mode = param[param_size]; 3290 } 3291 3292 return ret; 3293 } 3294 3295 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3296 { 3297 struct smu_context *smu = handle; 3298 3299 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3300 return -EOPNOTSUPP; 3301 3302 if (!smu->ppt_funcs->get_fan_control_mode) 3303 return -EOPNOTSUPP; 3304 3305 if (!fan_mode) 3306 return -EINVAL; 3307 3308 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3309 3310 return 0; 3311 } 3312 3313 static int smu_set_fan_control_mode(void *handle, u32 value) 3314 { 3315 struct smu_context *smu = handle; 3316 int ret = 0; 3317 3318 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3319 return -EOPNOTSUPP; 3320 3321 if (!smu->ppt_funcs->set_fan_control_mode) 3322 return -EOPNOTSUPP; 3323 3324 if (value == U32_MAX) 3325 return -EINVAL; 3326 3327 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3328 if (ret) 3329 goto out; 3330 3331 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3332 smu->user_dpm_profile.fan_mode = value; 3333 3334 /* reset user dpm fan speed */ 3335 if (value != AMD_FAN_CTRL_MANUAL) { 3336 smu->user_dpm_profile.fan_speed_pwm = 0; 3337 smu->user_dpm_profile.fan_speed_rpm = 0; 3338 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3339 } 3340 } 3341 3342 out: 3343 return ret; 3344 } 3345 3346 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3347 { 3348 struct smu_context *smu = handle; 3349 int ret = 0; 3350 3351 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3352 return -EOPNOTSUPP; 3353 3354 if (!smu->ppt_funcs->get_fan_speed_pwm) 3355 return -EOPNOTSUPP; 3356 3357 if (!speed) 3358 return -EINVAL; 3359 3360 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3361 3362 return ret; 3363 } 3364 3365 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3366 { 3367 struct smu_context *smu = handle; 3368 int ret = 0; 3369 3370 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3371 return -EOPNOTSUPP; 3372 3373 if (!smu->ppt_funcs->set_fan_speed_pwm) 3374 return -EOPNOTSUPP; 3375 3376 if (speed == U32_MAX) 3377 return -EINVAL; 3378 3379 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3380 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3381 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3382 smu->user_dpm_profile.fan_speed_pwm = speed; 3383 3384 /* Override custom RPM setting as they cannot co-exist */ 3385 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3386 smu->user_dpm_profile.fan_speed_rpm = 0; 3387 } 3388 3389 return ret; 3390 } 3391 3392 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3393 { 3394 struct smu_context *smu = handle; 3395 int ret = 0; 3396 3397 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3398 return -EOPNOTSUPP; 3399 3400 if (!smu->ppt_funcs->get_fan_speed_rpm) 3401 return -EOPNOTSUPP; 3402 3403 if (!speed) 3404 return -EINVAL; 3405 3406 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3407 3408 return ret; 3409 } 3410 3411 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3412 { 3413 struct smu_context *smu = handle; 3414 3415 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3416 return -EOPNOTSUPP; 3417 3418 return smu_set_min_dcef_deep_sleep(smu, clk); 3419 } 3420 3421 static int smu_get_clock_by_type_with_latency(void *handle, 3422 enum amd_pp_clock_type type, 3423 struct pp_clock_levels_with_latency *clocks) 3424 { 3425 struct smu_context *smu = handle; 3426 enum smu_clk_type clk_type; 3427 int ret = 0; 3428 3429 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3430 return -EOPNOTSUPP; 3431 3432 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3433 switch (type) { 3434 case amd_pp_sys_clock: 3435 clk_type = SMU_GFXCLK; 3436 break; 3437 case amd_pp_mem_clock: 3438 clk_type = SMU_MCLK; 3439 break; 3440 case amd_pp_dcef_clock: 3441 clk_type = SMU_DCEFCLK; 3442 break; 3443 case amd_pp_disp_clock: 3444 clk_type = SMU_DISPCLK; 3445 break; 3446 default: 3447 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3448 return -EINVAL; 3449 } 3450 3451 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3452 } 3453 3454 return ret; 3455 } 3456 3457 static int smu_display_clock_voltage_request(void *handle, 3458 struct pp_display_clock_request *clock_req) 3459 { 3460 struct smu_context *smu = handle; 3461 int ret = 0; 3462 3463 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3464 return -EOPNOTSUPP; 3465 3466 if (smu->ppt_funcs->display_clock_voltage_request) 3467 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3468 3469 return ret; 3470 } 3471 3472 3473 static int smu_display_disable_memory_clock_switch(void *handle, 3474 bool disable_memory_clock_switch) 3475 { 3476 struct smu_context *smu = handle; 3477 int ret = -EINVAL; 3478 3479 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3480 return -EOPNOTSUPP; 3481 3482 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3483 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3484 3485 return ret; 3486 } 3487 3488 static int smu_set_xgmi_pstate(void *handle, 3489 uint32_t pstate) 3490 { 3491 struct smu_context *smu = handle; 3492 int ret = 0; 3493 3494 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3495 return -EOPNOTSUPP; 3496 3497 if (smu->ppt_funcs->set_xgmi_pstate) 3498 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3499 3500 if (ret) 3501 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3502 3503 return ret; 3504 } 3505 3506 static int smu_get_baco_capability(void *handle) 3507 { 3508 struct smu_context *smu = handle; 3509 3510 if (!smu->pm_enabled) 3511 return false; 3512 3513 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3514 return false; 3515 3516 return smu->ppt_funcs->get_bamaco_support(smu); 3517 } 3518 3519 static int smu_baco_set_state(void *handle, int state) 3520 { 3521 struct smu_context *smu = handle; 3522 int ret = 0; 3523 3524 if (!smu->pm_enabled) 3525 return -EOPNOTSUPP; 3526 3527 if (state == 0) { 3528 if (smu->ppt_funcs->baco_exit) 3529 ret = smu->ppt_funcs->baco_exit(smu); 3530 } else if (state == 1) { 3531 if (smu->ppt_funcs->baco_enter) 3532 ret = smu->ppt_funcs->baco_enter(smu); 3533 } else { 3534 return -EINVAL; 3535 } 3536 3537 if (ret) 3538 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3539 (state)?"enter":"exit"); 3540 3541 return ret; 3542 } 3543 3544 bool smu_mode1_reset_is_support(struct smu_context *smu) 3545 { 3546 bool ret = false; 3547 3548 if (!smu->pm_enabled) 3549 return false; 3550 3551 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3552 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3553 3554 return ret; 3555 } 3556 3557 bool smu_link_reset_is_support(struct smu_context *smu) 3558 { 3559 if (!smu->pm_enabled) 3560 return false; 3561 3562 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET); 3563 } 3564 3565 int smu_mode1_reset(struct smu_context *smu) 3566 { 3567 int ret = 0; 3568 3569 if (!smu->pm_enabled) 3570 return -EOPNOTSUPP; 3571 3572 if (smu->ppt_funcs->mode1_reset) 3573 ret = smu->ppt_funcs->mode1_reset(smu); 3574 3575 return ret; 3576 } 3577 3578 static int smu_mode2_reset(void *handle) 3579 { 3580 struct smu_context *smu = handle; 3581 int ret = 0; 3582 3583 if (!smu->pm_enabled) 3584 return -EOPNOTSUPP; 3585 3586 if (smu->ppt_funcs->mode2_reset) 3587 ret = smu->ppt_funcs->mode2_reset(smu); 3588 3589 if (ret) 3590 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3591 3592 return ret; 3593 } 3594 3595 int smu_link_reset(struct smu_context *smu) 3596 { 3597 int ret = 0; 3598 3599 if (!smu->pm_enabled) 3600 return -EOPNOTSUPP; 3601 3602 if (smu->ppt_funcs->link_reset) 3603 ret = smu->ppt_funcs->link_reset(smu); 3604 3605 return ret; 3606 } 3607 3608 static int smu_enable_gfx_features(void *handle) 3609 { 3610 struct smu_context *smu = handle; 3611 int ret = 0; 3612 3613 if (!smu->pm_enabled) 3614 return -EOPNOTSUPP; 3615 3616 if (smu->ppt_funcs->enable_gfx_features) 3617 ret = smu->ppt_funcs->enable_gfx_features(smu); 3618 3619 if (ret) 3620 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3621 3622 return ret; 3623 } 3624 3625 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3626 struct pp_smu_nv_clock_table *max_clocks) 3627 { 3628 struct smu_context *smu = handle; 3629 int ret = 0; 3630 3631 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3632 return -EOPNOTSUPP; 3633 3634 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3635 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3636 3637 return ret; 3638 } 3639 3640 static int smu_get_uclk_dpm_states(void *handle, 3641 unsigned int *clock_values_in_khz, 3642 unsigned int *num_states) 3643 { 3644 struct smu_context *smu = handle; 3645 int ret = 0; 3646 3647 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3648 return -EOPNOTSUPP; 3649 3650 if (smu->ppt_funcs->get_uclk_dpm_states) 3651 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3652 3653 return ret; 3654 } 3655 3656 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3657 { 3658 struct smu_context *smu = handle; 3659 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3660 3661 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3662 return -EOPNOTSUPP; 3663 3664 if (smu->ppt_funcs->get_current_power_state) 3665 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3666 3667 return pm_state; 3668 } 3669 3670 static int smu_get_dpm_clock_table(void *handle, 3671 struct dpm_clocks *clock_table) 3672 { 3673 struct smu_context *smu = handle; 3674 int ret = 0; 3675 3676 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3677 return -EOPNOTSUPP; 3678 3679 if (smu->ppt_funcs->get_dpm_clock_table) 3680 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3681 3682 return ret; 3683 } 3684 3685 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3686 { 3687 struct smu_context *smu = handle; 3688 struct smu_table_context *smu_table = &smu->smu_table; 3689 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3690 struct smu_driver_table *gpu_metrics_table; 3691 3692 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3693 return -EOPNOTSUPP; 3694 3695 if (!smu->ppt_funcs->get_gpu_metrics) 3696 return -EOPNOTSUPP; 3697 3698 gpu_metrics_table = &driver_tables[SMU_DRIVER_TABLE_GPU_METRICS]; 3699 3700 /* If cached table is valid, return it */ 3701 if (smu_driver_table_is_valid(gpu_metrics_table)) { 3702 *table = gpu_metrics_table->cache.buffer; 3703 return gpu_metrics_table->cache.size; 3704 } 3705 3706 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3707 } 3708 3709 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3710 size_t size) 3711 { 3712 struct smu_context *smu = handle; 3713 3714 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3715 return -EOPNOTSUPP; 3716 3717 if (!smu->ppt_funcs->get_pm_metrics) 3718 return -EOPNOTSUPP; 3719 3720 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3721 } 3722 3723 static int smu_enable_mgpu_fan_boost(void *handle) 3724 { 3725 struct smu_context *smu = handle; 3726 int ret = 0; 3727 3728 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3729 return -EOPNOTSUPP; 3730 3731 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3732 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3733 3734 return ret; 3735 } 3736 3737 static int smu_gfx_state_change_set(void *handle, 3738 uint32_t state) 3739 { 3740 struct smu_context *smu = handle; 3741 int ret = 0; 3742 3743 if (smu->ppt_funcs->gfx_state_change_set) 3744 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3745 3746 return ret; 3747 } 3748 3749 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3750 { 3751 int ret = 0; 3752 3753 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3754 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3755 3756 return ret; 3757 } 3758 3759 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3760 { 3761 int ret = -EOPNOTSUPP; 3762 3763 if (smu->ppt_funcs && 3764 smu->ppt_funcs->get_ecc_info) 3765 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3766 3767 return ret; 3768 3769 } 3770 3771 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3772 { 3773 struct smu_context *smu = handle; 3774 struct smu_table_context *smu_table = &smu->smu_table; 3775 struct smu_table *memory_pool = &smu_table->memory_pool; 3776 3777 if (!addr || !size) 3778 return -EINVAL; 3779 3780 *addr = NULL; 3781 *size = 0; 3782 if (memory_pool->bo) { 3783 *addr = memory_pool->cpu_addr; 3784 *size = memory_pool->size; 3785 } 3786 3787 return 0; 3788 } 3789 3790 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3791 size_t *size) 3792 { 3793 size_t offset = *size; 3794 int level; 3795 3796 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3797 if (level == policy->current_level) 3798 offset += sysfs_emit_at(sysbuf, offset, 3799 "%d : %s*\n", level, 3800 policy->desc->get_desc(policy, level)); 3801 else 3802 offset += sysfs_emit_at(sysbuf, offset, 3803 "%d : %s\n", level, 3804 policy->desc->get_desc(policy, level)); 3805 } 3806 3807 *size = offset; 3808 } 3809 3810 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3811 enum pp_pm_policy p_type, char *sysbuf) 3812 { 3813 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3814 struct smu_dpm_policy_ctxt *policy_ctxt; 3815 struct smu_dpm_policy *dpm_policy; 3816 size_t offset = 0; 3817 3818 policy_ctxt = dpm_ctxt->dpm_policies; 3819 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3820 !policy_ctxt->policy_mask) 3821 return -EOPNOTSUPP; 3822 3823 if (p_type == PP_PM_POLICY_NONE) 3824 return -EINVAL; 3825 3826 dpm_policy = smu_get_pm_policy(smu, p_type); 3827 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3828 return -ENOENT; 3829 3830 if (!sysbuf) 3831 return -EINVAL; 3832 3833 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3834 3835 return offset; 3836 } 3837 3838 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3839 enum pp_pm_policy p_type) 3840 { 3841 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3842 struct smu_dpm_policy_ctxt *policy_ctxt; 3843 int i; 3844 3845 policy_ctxt = dpm_ctxt->dpm_policies; 3846 if (!policy_ctxt) 3847 return NULL; 3848 3849 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3850 if (policy_ctxt->policies[i].policy_type == p_type) 3851 return &policy_ctxt->policies[i]; 3852 } 3853 3854 return NULL; 3855 } 3856 3857 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3858 int level) 3859 { 3860 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3861 struct smu_dpm_policy *dpm_policy = NULL; 3862 struct smu_dpm_policy_ctxt *policy_ctxt; 3863 int ret = -EOPNOTSUPP; 3864 3865 policy_ctxt = dpm_ctxt->dpm_policies; 3866 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3867 !policy_ctxt->policy_mask) 3868 return ret; 3869 3870 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3871 return -EINVAL; 3872 3873 dpm_policy = smu_get_pm_policy(smu, p_type); 3874 3875 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3876 return ret; 3877 3878 if (dpm_policy->current_level == level) 3879 return 0; 3880 3881 ret = dpm_policy->set_policy(smu, level); 3882 3883 if (!ret) 3884 dpm_policy->current_level = level; 3885 3886 return ret; 3887 } 3888 3889 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) 3890 { 3891 struct smu_context *smu = handle; 3892 struct smu_table_context *smu_table = &smu->smu_table; 3893 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3894 enum smu_driver_table_id table_id; 3895 struct smu_driver_table *temp_table; 3896 3897 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3898 return -EOPNOTSUPP; 3899 3900 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) 3901 return -EOPNOTSUPP; 3902 3903 table_id = smu_metrics_get_temp_table_id(type); 3904 3905 if (table_id == SMU_DRIVER_TABLE_COUNT) 3906 return -EINVAL; 3907 3908 temp_table = &driver_tables[table_id]; 3909 3910 /* If the request is to get size alone, return the cached table size */ 3911 if (!table && temp_table->cache.size) 3912 return temp_table->cache.size; 3913 3914 if (smu_driver_table_is_valid(temp_table)) { 3915 memcpy(table, temp_table->cache.buffer, temp_table->cache.size); 3916 return temp_table->cache.size; 3917 } 3918 3919 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); 3920 } 3921 3922 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) 3923 { 3924 struct smu_context *smu = handle; 3925 bool ret = false; 3926 3927 if (!smu->pm_enabled) 3928 return false; 3929 3930 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) 3931 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); 3932 3933 return ret; 3934 } 3935 3936 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3937 { 3938 struct smu_context *smu = handle; 3939 3940 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3941 return -EOPNOTSUPP; 3942 3943 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3944 return -EOPNOTSUPP; 3945 3946 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3947 } 3948 3949 static const struct amd_pm_funcs swsmu_pm_funcs = { 3950 /* export for sysfs */ 3951 .set_fan_control_mode = smu_set_fan_control_mode, 3952 .get_fan_control_mode = smu_get_fan_control_mode, 3953 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3954 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3955 .force_clock_level = smu_force_ppclk_levels, 3956 .emit_clock_levels = smu_emit_ppclk_levels, 3957 .force_performance_level = smu_force_performance_level, 3958 .read_sensor = smu_read_sensor, 3959 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3960 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3961 .get_performance_level = smu_get_performance_level, 3962 .get_current_power_state = smu_get_current_power_state, 3963 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3964 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3965 .get_pp_num_states = smu_get_power_num_states, 3966 .get_pp_table = smu_sys_get_pp_table, 3967 .set_pp_table = smu_sys_set_pp_table, 3968 .switch_power_profile = smu_switch_power_profile, 3969 .pause_power_profile = smu_pause_power_profile, 3970 /* export to amdgpu */ 3971 .dispatch_tasks = smu_handle_dpm_task, 3972 .load_firmware = smu_load_microcode, 3973 .set_powergating_by_smu = smu_dpm_set_power_gate, 3974 .set_power_limit = smu_set_power_limit, 3975 .get_power_limit = smu_get_power_limit, 3976 .get_power_profile_mode = smu_get_power_profile_mode, 3977 .set_power_profile_mode = smu_set_power_profile_mode, 3978 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3979 .set_mp1_state = smu_set_mp1_state, 3980 .gfx_state_change_set = smu_gfx_state_change_set, 3981 /* export to DC */ 3982 .get_sclk = smu_get_sclk, 3983 .get_mclk = smu_get_mclk, 3984 .display_configuration_change = smu_display_configuration_change, 3985 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3986 .display_clock_voltage_request = smu_display_clock_voltage_request, 3987 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3988 .set_active_display_count = smu_set_display_count, 3989 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3990 .get_asic_baco_capability = smu_get_baco_capability, 3991 .set_asic_baco_state = smu_baco_set_state, 3992 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3993 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3994 .asic_reset_mode_2 = smu_mode2_reset, 3995 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3996 .set_df_cstate = smu_set_df_cstate, 3997 .set_xgmi_pstate = smu_set_xgmi_pstate, 3998 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3999 .get_pm_metrics = smu_sys_get_pm_metrics, 4000 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 4001 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 4002 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 4003 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 4004 .get_dpm_clock_table = smu_get_dpm_clock_table, 4005 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 4006 .get_xcp_metrics = smu_sys_get_xcp_metrics, 4007 .get_temp_metrics = smu_sys_get_temp_metrics, 4008 .temp_metrics_is_supported = smu_temp_metrics_is_supported, 4009 }; 4010 4011 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 4012 uint64_t event_arg) 4013 { 4014 int ret = -EINVAL; 4015 4016 if (smu->ppt_funcs->wait_for_event) 4017 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 4018 4019 return ret; 4020 } 4021 4022 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 4023 { 4024 4025 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 4026 return -EOPNOTSUPP; 4027 4028 /* Confirm the buffer allocated is of correct size */ 4029 if (size != smu->stb_context.stb_buf_size) 4030 return -EINVAL; 4031 4032 /* 4033 * No need to lock smu mutex as we access STB directly through MMIO 4034 * and not going through SMU messaging route (for now at least). 4035 * For registers access rely on implementation internal locking. 4036 */ 4037 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 4038 } 4039 4040 #if defined(CONFIG_DEBUG_FS) 4041 4042 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 4043 { 4044 struct amdgpu_device *adev = filp->f_inode->i_private; 4045 struct smu_context *smu = adev->powerplay.pp_handle; 4046 unsigned char *buf; 4047 int r; 4048 4049 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 4050 if (!buf) 4051 return -ENOMEM; 4052 4053 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 4054 if (r) 4055 goto out; 4056 4057 filp->private_data = buf; 4058 4059 return 0; 4060 4061 out: 4062 kvfree(buf); 4063 return r; 4064 } 4065 4066 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 4067 loff_t *pos) 4068 { 4069 struct amdgpu_device *adev = filp->f_inode->i_private; 4070 struct smu_context *smu = adev->powerplay.pp_handle; 4071 4072 4073 if (!filp->private_data) 4074 return -EINVAL; 4075 4076 return simple_read_from_buffer(buf, 4077 size, 4078 pos, filp->private_data, 4079 smu->stb_context.stb_buf_size); 4080 } 4081 4082 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 4083 { 4084 kvfree(filp->private_data); 4085 filp->private_data = NULL; 4086 4087 return 0; 4088 } 4089 4090 /* 4091 * We have to define not only read method but also 4092 * open and release because .read takes up to PAGE_SIZE 4093 * data each time so and so is invoked multiple times. 4094 * We allocate the STB buffer in .open and release it 4095 * in .release 4096 */ 4097 static const struct file_operations smu_stb_debugfs_fops = { 4098 .owner = THIS_MODULE, 4099 .open = smu_stb_debugfs_open, 4100 .read = smu_stb_debugfs_read, 4101 .release = smu_stb_debugfs_release, 4102 .llseek = default_llseek, 4103 }; 4104 4105 #endif 4106 4107 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 4108 { 4109 #if defined(CONFIG_DEBUG_FS) 4110 4111 struct smu_context *smu = adev->powerplay.pp_handle; 4112 4113 if (!smu || (!smu->stb_context.stb_buf_size)) 4114 return; 4115 4116 debugfs_create_file_size("amdgpu_smu_stb_dump", 4117 S_IRUSR, 4118 adev_to_drm(adev)->primary->debugfs_root, 4119 adev, 4120 &smu_stb_debugfs_fops, 4121 smu->stb_context.stb_buf_size); 4122 #endif 4123 } 4124 4125 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 4126 { 4127 int ret = 0; 4128 4129 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 4130 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 4131 4132 return ret; 4133 } 4134 4135 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 4136 { 4137 int ret = 0; 4138 4139 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 4140 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 4141 4142 return ret; 4143 } 4144 4145 int smu_send_rma_reason(struct smu_context *smu) 4146 { 4147 int ret = 0; 4148 4149 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 4150 ret = smu->ppt_funcs->send_rma_reason(smu); 4151 4152 return ret; 4153 } 4154 4155 /** 4156 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 4157 * @smu: smu_context pointer 4158 * 4159 * This function checks if the SMU supports resetting the SDMA engine. 4160 * It returns true if supported, false otherwise. 4161 */ 4162 bool smu_reset_sdma_is_supported(struct smu_context *smu) 4163 { 4164 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); 4165 } 4166 4167 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4168 { 4169 int ret = 0; 4170 4171 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4172 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4173 4174 return ret; 4175 } 4176 4177 bool smu_reset_vcn_is_supported(struct smu_context *smu) 4178 { 4179 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET); 4180 } 4181 4182 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4183 { 4184 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4185 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4186 4187 return 0; 4188 } 4189