1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "amd_pcie.h" 41 42 /* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47 #undef pr_err 48 #undef pr_warn 49 #undef pr_info 50 #undef pr_debug 51 52 static const struct amd_pm_funcs swsmu_pm_funcs; 53 static int smu_force_smuclk_levels(struct smu_context *smu, 54 enum smu_clk_type clk_type, 55 uint32_t mask); 56 static int smu_handle_task(struct smu_context *smu, 57 enum amd_dpm_forced_level level, 58 enum amd_pp_task task_id, 59 bool lock_needed); 60 static int smu_reset(struct smu_context *smu); 61 static int smu_set_fan_speed_percent(void *handle, u32 speed); 62 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 63 static int smu_set_power_limit(void *handle, uint32_t limit); 64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 66 67 static int smu_sys_get_pp_feature_mask(void *handle, 68 char *buf) 69 { 70 struct smu_context *smu = handle; 71 int size = 0; 72 73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 74 return -EOPNOTSUPP; 75 76 mutex_lock(&smu->mutex); 77 78 size = smu_get_pp_feature_mask(smu, buf); 79 80 mutex_unlock(&smu->mutex); 81 82 return size; 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 int ret = 0; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 mutex_lock(&smu->mutex); 95 96 ret = smu_set_pp_feature_mask(smu, new_mask); 97 98 mutex_unlock(&smu->mutex); 99 100 return ret; 101 } 102 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 104 { 105 int ret = 0; 106 struct smu_context *smu = &adev->smu; 107 108 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 109 *value = smu_get_gfx_off_status(smu); 110 else 111 ret = -EINVAL; 112 113 return ret; 114 } 115 116 int smu_set_soft_freq_range(struct smu_context *smu, 117 enum smu_clk_type clk_type, 118 uint32_t min, 119 uint32_t max) 120 { 121 int ret = 0; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->set_soft_freq_limited_range) 126 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 int smu_get_dpm_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t *min, 139 uint32_t *max) 140 { 141 int ret = 0; 142 143 if (!min && !max) 144 return -EINVAL; 145 146 mutex_lock(&smu->mutex); 147 148 if (smu->ppt_funcs->get_dpm_ultimate_freq) 149 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 150 clk_type, 151 min, 152 max); 153 154 mutex_unlock(&smu->mutex); 155 156 return ret; 157 } 158 159 static u32 smu_get_mclk(void *handle, bool low) 160 { 161 struct smu_context *smu = handle; 162 uint32_t clk_freq; 163 int ret = 0; 164 165 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 166 low ? &clk_freq : NULL, 167 !low ? &clk_freq : NULL); 168 if (ret) 169 return 0; 170 return clk_freq * 100; 171 } 172 173 static u32 smu_get_sclk(void *handle, bool low) 174 { 175 struct smu_context *smu = handle; 176 uint32_t clk_freq; 177 int ret = 0; 178 179 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 180 low ? &clk_freq : NULL, 181 !low ? &clk_freq : NULL); 182 if (ret) 183 return 0; 184 return clk_freq * 100; 185 } 186 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 188 bool enable) 189 { 190 struct smu_power_context *smu_power = &smu->smu_power; 191 struct smu_power_gate *power_gate = &smu_power->power_gate; 192 int ret = 0; 193 194 if (!smu->ppt_funcs->dpm_set_vcn_enable) 195 return 0; 196 197 if (atomic_read(&power_gate->vcn_gated) ^ enable) 198 return 0; 199 200 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 201 if (!ret) 202 atomic_set(&power_gate->vcn_gated, !enable); 203 204 return ret; 205 } 206 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 208 bool enable) 209 { 210 struct smu_power_context *smu_power = &smu->smu_power; 211 struct smu_power_gate *power_gate = &smu_power->power_gate; 212 int ret = 0; 213 214 mutex_lock(&power_gate->vcn_gate_lock); 215 216 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 217 218 mutex_unlock(&power_gate->vcn_gate_lock); 219 220 return ret; 221 } 222 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 224 bool enable) 225 { 226 struct smu_power_context *smu_power = &smu->smu_power; 227 struct smu_power_gate *power_gate = &smu_power->power_gate; 228 int ret = 0; 229 230 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 231 return 0; 232 233 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 234 return 0; 235 236 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 237 if (!ret) 238 atomic_set(&power_gate->jpeg_gated, !enable); 239 240 return ret; 241 } 242 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 244 bool enable) 245 { 246 struct smu_power_context *smu_power = &smu->smu_power; 247 struct smu_power_gate *power_gate = &smu_power->power_gate; 248 int ret = 0; 249 250 mutex_lock(&power_gate->jpeg_gate_lock); 251 252 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 253 254 mutex_unlock(&power_gate->jpeg_gate_lock); 255 256 return ret; 257 } 258 259 /** 260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 261 * 262 * @handle: smu_context pointer 263 * @block_type: the IP block to power gate/ungate 264 * @gate: to power gate if true, ungate otherwise 265 * 266 * This API uses no smu->mutex lock protection due to: 267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 268 * This is guarded to be race condition free by the caller. 269 * 2. Or get called on user setting request of power_dpm_force_performance_level. 270 * Under this case, the smu->mutex lock protection is already enforced on 271 * the parent API smu_force_performance_level of the call path. 272 */ 273 static int smu_dpm_set_power_gate(void *handle, 274 uint32_t block_type, 275 bool gate) 276 { 277 struct smu_context *smu = handle; 278 int ret = 0; 279 280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 281 return -EOPNOTSUPP; 282 283 switch (block_type) { 284 /* 285 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 286 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 287 */ 288 case AMD_IP_BLOCK_TYPE_UVD: 289 case AMD_IP_BLOCK_TYPE_VCN: 290 ret = smu_dpm_set_vcn_enable(smu, !gate); 291 if (ret) 292 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 293 gate ? "gate" : "ungate"); 294 break; 295 case AMD_IP_BLOCK_TYPE_GFX: 296 ret = smu_gfx_off_control(smu, gate); 297 if (ret) 298 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 299 gate ? "enable" : "disable"); 300 break; 301 case AMD_IP_BLOCK_TYPE_SDMA: 302 ret = smu_powergate_sdma(smu, gate); 303 if (ret) 304 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 305 gate ? "gate" : "ungate"); 306 break; 307 case AMD_IP_BLOCK_TYPE_JPEG: 308 ret = smu_dpm_set_jpeg_enable(smu, !gate); 309 if (ret) 310 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 311 gate ? "gate" : "ungate"); 312 break; 313 default: 314 dev_err(smu->adev->dev, "Unsupported block type!\n"); 315 return -EINVAL; 316 } 317 318 return ret; 319 } 320 321 /** 322 * smu_set_user_clk_dependencies - set user profile clock dependencies 323 * 324 * @smu: smu_context pointer 325 * @clk: enum smu_clk_type type 326 * 327 * Enable/Disable the clock dependency for the @clk type. 328 */ 329 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 330 { 331 if (smu->adev->in_suspend) 332 return; 333 334 if (clk == SMU_MCLK) { 335 smu->user_dpm_profile.clk_dependency = 0; 336 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 337 } else if (clk == SMU_FCLK) { 338 /* MCLK takes precedence over FCLK */ 339 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 340 return; 341 342 smu->user_dpm_profile.clk_dependency = 0; 343 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 344 } else if (clk == SMU_SOCCLK) { 345 /* MCLK takes precedence over SOCCLK */ 346 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 347 return; 348 349 smu->user_dpm_profile.clk_dependency = 0; 350 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 351 } else 352 /* Add clk dependencies here, if any */ 353 return; 354 } 355 356 /** 357 * smu_restore_dpm_user_profile - reinstate user dpm profile 358 * 359 * @smu: smu_context pointer 360 * 361 * Restore the saved user power configurations include power limit, 362 * clock frequencies, fan control mode and fan speed. 363 */ 364 static void smu_restore_dpm_user_profile(struct smu_context *smu) 365 { 366 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 367 int ret = 0; 368 369 if (!smu->adev->in_suspend) 370 return; 371 372 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 373 return; 374 375 /* Enable restore flag */ 376 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 377 378 /* set the user dpm power limit */ 379 if (smu->user_dpm_profile.power_limit) { 380 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 383 } 384 385 /* set the user dpm clock configurations */ 386 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 387 enum smu_clk_type clk_type; 388 389 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 390 /* 391 * Iterate over smu clk type and force the saved user clk 392 * configs, skip if clock dependency is enabled 393 */ 394 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 395 smu->user_dpm_profile.clk_mask[clk_type]) { 396 ret = smu_force_smuclk_levels(smu, clk_type, 397 smu->user_dpm_profile.clk_mask[clk_type]); 398 if (ret) 399 dev_err(smu->adev->dev, 400 "Failed to set clock type = %d\n", clk_type); 401 } 402 } 403 } 404 405 /* set the user dpm fan configurations */ 406 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL) { 407 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 408 if (ret) { 409 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 410 return; 411 } 412 413 if (!ret && smu->user_dpm_profile.fan_speed_percent) { 414 ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent); 415 if (ret) 416 dev_err(smu->adev->dev, "Failed to set manual fan speed\n"); 417 } 418 } 419 420 /* Disable restore flag */ 421 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 422 } 423 424 static int smu_get_power_num_states(void *handle, 425 struct pp_states_info *state_info) 426 { 427 if (!state_info) 428 return -EINVAL; 429 430 /* not support power state */ 431 memset(state_info, 0, sizeof(struct pp_states_info)); 432 state_info->nums = 1; 433 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 434 435 return 0; 436 } 437 438 bool is_support_sw_smu(struct amdgpu_device *adev) 439 { 440 if (adev->asic_type >= CHIP_ARCTURUS) 441 return true; 442 443 return false; 444 } 445 446 bool is_support_cclk_dpm(struct amdgpu_device *adev) 447 { 448 struct smu_context *smu = &adev->smu; 449 450 if (!is_support_sw_smu(adev)) 451 return false; 452 453 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 454 return false; 455 456 return true; 457 } 458 459 460 static int smu_sys_get_pp_table(void *handle, 461 char **table) 462 { 463 struct smu_context *smu = handle; 464 struct smu_table_context *smu_table = &smu->smu_table; 465 uint32_t powerplay_table_size; 466 467 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 468 return -EOPNOTSUPP; 469 470 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 471 return -EINVAL; 472 473 mutex_lock(&smu->mutex); 474 475 if (smu_table->hardcode_pptable) 476 *table = smu_table->hardcode_pptable; 477 else 478 *table = smu_table->power_play_table; 479 480 powerplay_table_size = smu_table->power_play_table_size; 481 482 mutex_unlock(&smu->mutex); 483 484 return powerplay_table_size; 485 } 486 487 static int smu_sys_set_pp_table(void *handle, 488 const char *buf, 489 size_t size) 490 { 491 struct smu_context *smu = handle; 492 struct smu_table_context *smu_table = &smu->smu_table; 493 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 494 int ret = 0; 495 496 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 497 return -EOPNOTSUPP; 498 499 if (header->usStructureSize != size) { 500 dev_err(smu->adev->dev, "pp table size not matched !\n"); 501 return -EIO; 502 } 503 504 mutex_lock(&smu->mutex); 505 if (!smu_table->hardcode_pptable) 506 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 507 if (!smu_table->hardcode_pptable) { 508 ret = -ENOMEM; 509 goto failed; 510 } 511 512 memcpy(smu_table->hardcode_pptable, buf, size); 513 smu_table->power_play_table = smu_table->hardcode_pptable; 514 smu_table->power_play_table_size = size; 515 516 /* 517 * Special hw_fini action(for Navi1x, the DPMs disablement will be 518 * skipped) may be needed for custom pptable uploading. 519 */ 520 smu->uploading_custom_pp_table = true; 521 522 ret = smu_reset(smu); 523 if (ret) 524 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 525 526 smu->uploading_custom_pp_table = false; 527 528 failed: 529 mutex_unlock(&smu->mutex); 530 return ret; 531 } 532 533 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 534 { 535 struct smu_feature *feature = &smu->smu_feature; 536 int ret = 0; 537 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 538 539 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 540 541 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 542 SMU_FEATURE_MAX/32); 543 if (ret) 544 return ret; 545 546 bitmap_or(feature->allowed, feature->allowed, 547 (unsigned long *)allowed_feature_mask, 548 feature->feature_num); 549 550 return ret; 551 } 552 553 static int smu_set_funcs(struct amdgpu_device *adev) 554 { 555 struct smu_context *smu = &adev->smu; 556 557 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 558 smu->od_enabled = true; 559 560 switch (adev->asic_type) { 561 case CHIP_NAVI10: 562 case CHIP_NAVI14: 563 case CHIP_NAVI12: 564 navi10_set_ppt_funcs(smu); 565 break; 566 case CHIP_ARCTURUS: 567 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 568 arcturus_set_ppt_funcs(smu); 569 /* OD is not supported on Arcturus */ 570 smu->od_enabled =false; 571 break; 572 case CHIP_SIENNA_CICHLID: 573 case CHIP_NAVY_FLOUNDER: 574 case CHIP_DIMGREY_CAVEFISH: 575 case CHIP_BEIGE_GOBY: 576 sienna_cichlid_set_ppt_funcs(smu); 577 break; 578 case CHIP_ALDEBARAN: 579 aldebaran_set_ppt_funcs(smu); 580 /* Enable pp_od_clk_voltage node */ 581 smu->od_enabled = true; 582 break; 583 case CHIP_RENOIR: 584 renoir_set_ppt_funcs(smu); 585 break; 586 case CHIP_VANGOGH: 587 vangogh_set_ppt_funcs(smu); 588 break; 589 case CHIP_YELLOW_CARP: 590 yellow_carp_set_ppt_funcs(smu); 591 break; 592 case CHIP_CYAN_SKILLFISH: 593 cyan_skillfish_set_ppt_funcs(smu); 594 break; 595 default: 596 return -EINVAL; 597 } 598 599 return 0; 600 } 601 602 static int smu_early_init(void *handle) 603 { 604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 605 struct smu_context *smu = &adev->smu; 606 607 smu->adev = adev; 608 smu->pm_enabled = !!amdgpu_dpm; 609 smu->is_apu = false; 610 mutex_init(&smu->mutex); 611 mutex_init(&smu->smu_baco.mutex); 612 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 613 smu->smu_baco.platform_support = false; 614 615 adev->powerplay.pp_handle = smu; 616 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 617 618 return smu_set_funcs(adev); 619 } 620 621 static int smu_set_default_dpm_table(struct smu_context *smu) 622 { 623 struct smu_power_context *smu_power = &smu->smu_power; 624 struct smu_power_gate *power_gate = &smu_power->power_gate; 625 int vcn_gate, jpeg_gate; 626 int ret = 0; 627 628 if (!smu->ppt_funcs->set_default_dpm_table) 629 return 0; 630 631 mutex_lock(&power_gate->vcn_gate_lock); 632 mutex_lock(&power_gate->jpeg_gate_lock); 633 634 vcn_gate = atomic_read(&power_gate->vcn_gated); 635 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 636 637 ret = smu_dpm_set_vcn_enable_locked(smu, true); 638 if (ret) 639 goto err0_out; 640 641 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 642 if (ret) 643 goto err1_out; 644 645 ret = smu->ppt_funcs->set_default_dpm_table(smu); 646 if (ret) 647 dev_err(smu->adev->dev, 648 "Failed to setup default dpm clock tables!\n"); 649 650 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 651 err1_out: 652 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 653 err0_out: 654 mutex_unlock(&power_gate->jpeg_gate_lock); 655 mutex_unlock(&power_gate->vcn_gate_lock); 656 657 return ret; 658 } 659 660 661 static int smu_late_init(void *handle) 662 { 663 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 664 struct smu_context *smu = &adev->smu; 665 int ret = 0; 666 667 smu_set_fine_grain_gfx_freq_parameters(smu); 668 669 if (!smu->pm_enabled) 670 return 0; 671 672 ret = smu_post_init(smu); 673 if (ret) { 674 dev_err(adev->dev, "Failed to post smu init!\n"); 675 return ret; 676 } 677 678 if (adev->asic_type == CHIP_YELLOW_CARP) 679 return 0; 680 681 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 682 ret = smu_set_default_od_settings(smu); 683 if (ret) { 684 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 685 return ret; 686 } 687 } 688 689 ret = smu_populate_umd_state_clk(smu); 690 if (ret) { 691 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 692 return ret; 693 } 694 695 ret = smu_get_asic_power_limits(smu, 696 &smu->current_power_limit, 697 &smu->default_power_limit, 698 &smu->max_power_limit); 699 if (ret) { 700 dev_err(adev->dev, "Failed to get asic power limits!\n"); 701 return ret; 702 } 703 704 if (!amdgpu_sriov_vf(adev)) 705 smu_get_unique_id(smu); 706 707 smu_get_fan_parameters(smu); 708 709 smu_handle_task(&adev->smu, 710 smu->smu_dpm.dpm_level, 711 AMD_PP_TASK_COMPLETE_INIT, 712 false); 713 714 smu_restore_dpm_user_profile(smu); 715 716 return 0; 717 } 718 719 static int smu_init_fb_allocations(struct smu_context *smu) 720 { 721 struct amdgpu_device *adev = smu->adev; 722 struct smu_table_context *smu_table = &smu->smu_table; 723 struct smu_table *tables = smu_table->tables; 724 struct smu_table *driver_table = &(smu_table->driver_table); 725 uint32_t max_table_size = 0; 726 int ret, i; 727 728 /* VRAM allocation for tool table */ 729 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 730 ret = amdgpu_bo_create_kernel(adev, 731 tables[SMU_TABLE_PMSTATUSLOG].size, 732 tables[SMU_TABLE_PMSTATUSLOG].align, 733 tables[SMU_TABLE_PMSTATUSLOG].domain, 734 &tables[SMU_TABLE_PMSTATUSLOG].bo, 735 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 736 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 737 if (ret) { 738 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 739 return ret; 740 } 741 } 742 743 /* VRAM allocation for driver table */ 744 for (i = 0; i < SMU_TABLE_COUNT; i++) { 745 if (tables[i].size == 0) 746 continue; 747 748 if (i == SMU_TABLE_PMSTATUSLOG) 749 continue; 750 751 if (max_table_size < tables[i].size) 752 max_table_size = tables[i].size; 753 } 754 755 driver_table->size = max_table_size; 756 driver_table->align = PAGE_SIZE; 757 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 758 759 ret = amdgpu_bo_create_kernel(adev, 760 driver_table->size, 761 driver_table->align, 762 driver_table->domain, 763 &driver_table->bo, 764 &driver_table->mc_address, 765 &driver_table->cpu_addr); 766 if (ret) { 767 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 768 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 769 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 770 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 771 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 772 } 773 774 return ret; 775 } 776 777 static int smu_fini_fb_allocations(struct smu_context *smu) 778 { 779 struct smu_table_context *smu_table = &smu->smu_table; 780 struct smu_table *tables = smu_table->tables; 781 struct smu_table *driver_table = &(smu_table->driver_table); 782 783 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 784 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 785 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 786 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 787 788 amdgpu_bo_free_kernel(&driver_table->bo, 789 &driver_table->mc_address, 790 &driver_table->cpu_addr); 791 792 return 0; 793 } 794 795 /** 796 * smu_alloc_memory_pool - allocate memory pool in the system memory 797 * 798 * @smu: amdgpu_device pointer 799 * 800 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 801 * and DramLogSetDramAddr can notify it changed. 802 * 803 * Returns 0 on success, error on failure. 804 */ 805 static int smu_alloc_memory_pool(struct smu_context *smu) 806 { 807 struct amdgpu_device *adev = smu->adev; 808 struct smu_table_context *smu_table = &smu->smu_table; 809 struct smu_table *memory_pool = &smu_table->memory_pool; 810 uint64_t pool_size = smu->pool_size; 811 int ret = 0; 812 813 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 814 return ret; 815 816 memory_pool->size = pool_size; 817 memory_pool->align = PAGE_SIZE; 818 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 819 820 switch (pool_size) { 821 case SMU_MEMORY_POOL_SIZE_256_MB: 822 case SMU_MEMORY_POOL_SIZE_512_MB: 823 case SMU_MEMORY_POOL_SIZE_1_GB: 824 case SMU_MEMORY_POOL_SIZE_2_GB: 825 ret = amdgpu_bo_create_kernel(adev, 826 memory_pool->size, 827 memory_pool->align, 828 memory_pool->domain, 829 &memory_pool->bo, 830 &memory_pool->mc_address, 831 &memory_pool->cpu_addr); 832 if (ret) 833 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 834 break; 835 default: 836 break; 837 } 838 839 return ret; 840 } 841 842 static int smu_free_memory_pool(struct smu_context *smu) 843 { 844 struct smu_table_context *smu_table = &smu->smu_table; 845 struct smu_table *memory_pool = &smu_table->memory_pool; 846 847 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 848 return 0; 849 850 amdgpu_bo_free_kernel(&memory_pool->bo, 851 &memory_pool->mc_address, 852 &memory_pool->cpu_addr); 853 854 memset(memory_pool, 0, sizeof(struct smu_table)); 855 856 return 0; 857 } 858 859 static int smu_alloc_dummy_read_table(struct smu_context *smu) 860 { 861 struct smu_table_context *smu_table = &smu->smu_table; 862 struct smu_table *dummy_read_1_table = 863 &smu_table->dummy_read_1_table; 864 struct amdgpu_device *adev = smu->adev; 865 int ret = 0; 866 867 dummy_read_1_table->size = 0x40000; 868 dummy_read_1_table->align = PAGE_SIZE; 869 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 870 871 ret = amdgpu_bo_create_kernel(adev, 872 dummy_read_1_table->size, 873 dummy_read_1_table->align, 874 dummy_read_1_table->domain, 875 &dummy_read_1_table->bo, 876 &dummy_read_1_table->mc_address, 877 &dummy_read_1_table->cpu_addr); 878 if (ret) 879 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 880 881 return ret; 882 } 883 884 static void smu_free_dummy_read_table(struct smu_context *smu) 885 { 886 struct smu_table_context *smu_table = &smu->smu_table; 887 struct smu_table *dummy_read_1_table = 888 &smu_table->dummy_read_1_table; 889 890 891 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 892 &dummy_read_1_table->mc_address, 893 &dummy_read_1_table->cpu_addr); 894 895 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 896 } 897 898 static int smu_smc_table_sw_init(struct smu_context *smu) 899 { 900 int ret; 901 902 /** 903 * Create smu_table structure, and init smc tables such as 904 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 905 */ 906 ret = smu_init_smc_tables(smu); 907 if (ret) { 908 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 909 return ret; 910 } 911 912 /** 913 * Create smu_power_context structure, and allocate smu_dpm_context and 914 * context size to fill the smu_power_context data. 915 */ 916 ret = smu_init_power(smu); 917 if (ret) { 918 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 919 return ret; 920 } 921 922 /* 923 * allocate vram bos to store smc table contents. 924 */ 925 ret = smu_init_fb_allocations(smu); 926 if (ret) 927 return ret; 928 929 ret = smu_alloc_memory_pool(smu); 930 if (ret) 931 return ret; 932 933 ret = smu_alloc_dummy_read_table(smu); 934 if (ret) 935 return ret; 936 937 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 938 if (ret) 939 return ret; 940 941 return 0; 942 } 943 944 static int smu_smc_table_sw_fini(struct smu_context *smu) 945 { 946 int ret; 947 948 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 949 950 smu_free_dummy_read_table(smu); 951 952 ret = smu_free_memory_pool(smu); 953 if (ret) 954 return ret; 955 956 ret = smu_fini_fb_allocations(smu); 957 if (ret) 958 return ret; 959 960 ret = smu_fini_power(smu); 961 if (ret) { 962 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 963 return ret; 964 } 965 966 ret = smu_fini_smc_tables(smu); 967 if (ret) { 968 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 969 return ret; 970 } 971 972 return 0; 973 } 974 975 static void smu_throttling_logging_work_fn(struct work_struct *work) 976 { 977 struct smu_context *smu = container_of(work, struct smu_context, 978 throttling_logging_work); 979 980 smu_log_thermal_throttling(smu); 981 } 982 983 static void smu_interrupt_work_fn(struct work_struct *work) 984 { 985 struct smu_context *smu = container_of(work, struct smu_context, 986 interrupt_work); 987 988 mutex_lock(&smu->mutex); 989 990 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 991 smu->ppt_funcs->interrupt_work(smu); 992 993 mutex_unlock(&smu->mutex); 994 } 995 996 static int smu_sw_init(void *handle) 997 { 998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 999 struct smu_context *smu = &adev->smu; 1000 int ret; 1001 1002 smu->pool_size = adev->pm.smu_prv_buffer_size; 1003 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1004 mutex_init(&smu->smu_feature.mutex); 1005 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1006 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1007 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1008 1009 mutex_init(&smu->sensor_lock); 1010 mutex_init(&smu->metrics_lock); 1011 mutex_init(&smu->message_lock); 1012 1013 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1014 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1015 atomic64_set(&smu->throttle_int_counter, 0); 1016 smu->watermarks_bitmap = 0; 1017 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1018 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1019 1020 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1021 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1022 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1023 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1024 1025 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1026 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1027 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1028 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1029 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1030 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1031 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1032 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1033 1034 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1035 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1036 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1037 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1038 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1039 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1040 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1041 smu->display_config = &adev->pm.pm_display_cfg; 1042 1043 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1044 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1045 1046 ret = smu_init_microcode(smu); 1047 if (ret) { 1048 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1049 return ret; 1050 } 1051 1052 ret = smu_smc_table_sw_init(smu); 1053 if (ret) { 1054 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1055 return ret; 1056 } 1057 1058 ret = smu_register_irq_handler(smu); 1059 if (ret) { 1060 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1061 return ret; 1062 } 1063 1064 /* If there is no way to query fan control mode, fan control is not supported */ 1065 if (!smu->ppt_funcs->get_fan_control_mode) 1066 smu->adev->pm.no_fan = true; 1067 1068 return 0; 1069 } 1070 1071 static int smu_sw_fini(void *handle) 1072 { 1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1074 struct smu_context *smu = &adev->smu; 1075 int ret; 1076 1077 ret = smu_smc_table_sw_fini(smu); 1078 if (ret) { 1079 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1080 return ret; 1081 } 1082 1083 smu_fini_microcode(smu); 1084 1085 return 0; 1086 } 1087 1088 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1089 { 1090 struct amdgpu_device *adev = smu->adev; 1091 struct smu_temperature_range *range = 1092 &smu->thermal_range; 1093 int ret = 0; 1094 1095 if (!smu->ppt_funcs->get_thermal_temperature_range) 1096 return 0; 1097 1098 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1099 if (ret) 1100 return ret; 1101 1102 adev->pm.dpm.thermal.min_temp = range->min; 1103 adev->pm.dpm.thermal.max_temp = range->max; 1104 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1105 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1106 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1107 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1108 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1109 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1110 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1111 1112 return ret; 1113 } 1114 1115 static int smu_smc_hw_setup(struct smu_context *smu) 1116 { 1117 struct amdgpu_device *adev = smu->adev; 1118 uint32_t pcie_gen = 0, pcie_width = 0; 1119 int ret = 0; 1120 1121 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1122 dev_info(adev->dev, "dpm has been enabled\n"); 1123 /* this is needed specifically */ 1124 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 1125 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1126 ret = smu_system_features_control(smu, true); 1127 return ret; 1128 } 1129 1130 ret = smu_init_display_count(smu, 0); 1131 if (ret) { 1132 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1133 return ret; 1134 } 1135 1136 ret = smu_set_driver_table_location(smu); 1137 if (ret) { 1138 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1139 return ret; 1140 } 1141 1142 /* 1143 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1144 */ 1145 ret = smu_set_tool_table_location(smu); 1146 if (ret) { 1147 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1148 return ret; 1149 } 1150 1151 /* 1152 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1153 * pool location. 1154 */ 1155 ret = smu_notify_memory_pool_location(smu); 1156 if (ret) { 1157 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1158 return ret; 1159 } 1160 1161 /* smu_dump_pptable(smu); */ 1162 /* 1163 * Copy pptable bo in the vram to smc with SMU MSGs such as 1164 * SetDriverDramAddr and TransferTableDram2Smu. 1165 */ 1166 ret = smu_write_pptable(smu); 1167 if (ret) { 1168 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1169 return ret; 1170 } 1171 1172 /* issue Run*Btc msg */ 1173 ret = smu_run_btc(smu); 1174 if (ret) 1175 return ret; 1176 1177 ret = smu_feature_set_allowed_mask(smu); 1178 if (ret) { 1179 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1180 return ret; 1181 } 1182 1183 ret = smu_system_features_control(smu, true); 1184 if (ret) { 1185 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1186 return ret; 1187 } 1188 1189 if (!smu_is_dpm_running(smu)) 1190 dev_info(adev->dev, "dpm has been disabled\n"); 1191 1192 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1193 pcie_gen = 3; 1194 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1195 pcie_gen = 2; 1196 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1197 pcie_gen = 1; 1198 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1199 pcie_gen = 0; 1200 1201 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1202 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1203 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1204 */ 1205 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1206 pcie_width = 6; 1207 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1208 pcie_width = 5; 1209 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1210 pcie_width = 4; 1211 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1212 pcie_width = 3; 1213 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1214 pcie_width = 2; 1215 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1216 pcie_width = 1; 1217 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1218 if (ret) { 1219 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1220 return ret; 1221 } 1222 1223 ret = smu_get_thermal_temperature_range(smu); 1224 if (ret) { 1225 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1226 return ret; 1227 } 1228 1229 ret = smu_enable_thermal_alert(smu); 1230 if (ret) { 1231 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1232 return ret; 1233 } 1234 1235 /* 1236 * Set initialized values (get from vbios) to dpm tables context such as 1237 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1238 * type of clks. 1239 */ 1240 ret = smu_set_default_dpm_table(smu); 1241 if (ret) { 1242 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1243 return ret; 1244 } 1245 1246 ret = smu_notify_display_change(smu); 1247 if (ret) 1248 return ret; 1249 1250 /* 1251 * Set min deep sleep dce fclk with bootup value from vbios via 1252 * SetMinDeepSleepDcefclk MSG. 1253 */ 1254 ret = smu_set_min_dcef_deep_sleep(smu, 1255 smu->smu_table.boot_values.dcefclk / 100); 1256 if (ret) 1257 return ret; 1258 1259 return ret; 1260 } 1261 1262 static int smu_start_smc_engine(struct smu_context *smu) 1263 { 1264 struct amdgpu_device *adev = smu->adev; 1265 int ret = 0; 1266 1267 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1268 if (adev->asic_type < CHIP_NAVI10) { 1269 if (smu->ppt_funcs->load_microcode) { 1270 ret = smu->ppt_funcs->load_microcode(smu); 1271 if (ret) 1272 return ret; 1273 } 1274 } 1275 } 1276 1277 if (smu->ppt_funcs->check_fw_status) { 1278 ret = smu->ppt_funcs->check_fw_status(smu); 1279 if (ret) { 1280 dev_err(adev->dev, "SMC is not ready\n"); 1281 return ret; 1282 } 1283 } 1284 1285 /* 1286 * Send msg GetDriverIfVersion to check if the return value is equal 1287 * with DRIVER_IF_VERSION of smc header. 1288 */ 1289 ret = smu_check_fw_version(smu); 1290 if (ret) 1291 return ret; 1292 1293 return ret; 1294 } 1295 1296 static int smu_hw_init(void *handle) 1297 { 1298 int ret; 1299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1300 struct smu_context *smu = &adev->smu; 1301 1302 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1303 smu->pm_enabled = false; 1304 return 0; 1305 } 1306 1307 ret = smu_start_smc_engine(smu); 1308 if (ret) { 1309 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1310 return ret; 1311 } 1312 1313 if (smu->is_apu) { 1314 smu_powergate_sdma(&adev->smu, false); 1315 smu_dpm_set_vcn_enable(smu, true); 1316 smu_dpm_set_jpeg_enable(smu, true); 1317 smu_set_gfx_cgpg(&adev->smu, true); 1318 } 1319 1320 if (!smu->pm_enabled) 1321 return 0; 1322 1323 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1324 ret = smu_get_vbios_bootup_values(smu); 1325 if (ret) { 1326 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1327 return ret; 1328 } 1329 1330 ret = smu_setup_pptable(smu); 1331 if (ret) { 1332 dev_err(adev->dev, "Failed to setup pptable!\n"); 1333 return ret; 1334 } 1335 1336 ret = smu_get_driver_allowed_feature_mask(smu); 1337 if (ret) 1338 return ret; 1339 1340 ret = smu_smc_hw_setup(smu); 1341 if (ret) { 1342 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1343 return ret; 1344 } 1345 1346 /* 1347 * Move maximum sustainable clock retrieving here considering 1348 * 1. It is not needed on resume(from S3). 1349 * 2. DAL settings come between .hw_init and .late_init of SMU. 1350 * And DAL needs to know the maximum sustainable clocks. Thus 1351 * it cannot be put in .late_init(). 1352 */ 1353 ret = smu_init_max_sustainable_clocks(smu); 1354 if (ret) { 1355 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1356 return ret; 1357 } 1358 1359 adev->pm.dpm_enabled = true; 1360 1361 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1362 1363 return 0; 1364 } 1365 1366 static int smu_disable_dpms(struct smu_context *smu) 1367 { 1368 struct amdgpu_device *adev = smu->adev; 1369 int ret = 0; 1370 bool use_baco = !smu->is_apu && 1371 ((amdgpu_in_reset(adev) && 1372 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1373 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1374 1375 /* 1376 * For custom pptable uploading, skip the DPM features 1377 * disable process on Navi1x ASICs. 1378 * - As the gfx related features are under control of 1379 * RLC on those ASICs. RLC reinitialization will be 1380 * needed to reenable them. That will cost much more 1381 * efforts. 1382 * 1383 * - SMU firmware can handle the DPM reenablement 1384 * properly. 1385 */ 1386 if (smu->uploading_custom_pp_table && 1387 (adev->asic_type >= CHIP_NAVI10) && 1388 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1389 return smu_disable_all_features_with_exception(smu, 1390 true, 1391 SMU_FEATURE_COUNT); 1392 1393 /* 1394 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1395 * on BACO in. Driver involvement is unnecessary. 1396 */ 1397 if (((adev->asic_type == CHIP_SIENNA_CICHLID) || 1398 ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) && 1399 use_baco) 1400 return smu_disable_all_features_with_exception(smu, 1401 true, 1402 SMU_FEATURE_BACO_BIT); 1403 1404 /* 1405 * For gpu reset, runpm and hibernation through BACO, 1406 * BACO feature has to be kept enabled. 1407 */ 1408 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1409 ret = smu_disable_all_features_with_exception(smu, 1410 false, 1411 SMU_FEATURE_BACO_BIT); 1412 if (ret) 1413 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1414 } else { 1415 ret = smu_system_features_control(smu, false); 1416 if (ret) 1417 dev_err(adev->dev, "Failed to disable smu features.\n"); 1418 } 1419 1420 if (adev->asic_type >= CHIP_NAVI10 && 1421 adev->gfx.rlc.funcs->stop) 1422 adev->gfx.rlc.funcs->stop(adev); 1423 1424 return ret; 1425 } 1426 1427 static int smu_smc_hw_cleanup(struct smu_context *smu) 1428 { 1429 struct amdgpu_device *adev = smu->adev; 1430 int ret = 0; 1431 1432 cancel_work_sync(&smu->throttling_logging_work); 1433 cancel_work_sync(&smu->interrupt_work); 1434 1435 ret = smu_disable_thermal_alert(smu); 1436 if (ret) { 1437 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1438 return ret; 1439 } 1440 1441 ret = smu_disable_dpms(smu); 1442 if (ret) { 1443 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1444 return ret; 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int smu_hw_fini(void *handle) 1451 { 1452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1453 struct smu_context *smu = &adev->smu; 1454 1455 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1456 return 0; 1457 1458 if (smu->is_apu) { 1459 smu_powergate_sdma(&adev->smu, true); 1460 } 1461 1462 smu_dpm_set_vcn_enable(smu, false); 1463 smu_dpm_set_jpeg_enable(smu, false); 1464 1465 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1466 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1467 1468 if (!smu->pm_enabled) 1469 return 0; 1470 1471 adev->pm.dpm_enabled = false; 1472 1473 return smu_smc_hw_cleanup(smu); 1474 } 1475 1476 static int smu_reset(struct smu_context *smu) 1477 { 1478 struct amdgpu_device *adev = smu->adev; 1479 int ret; 1480 1481 amdgpu_gfx_off_ctrl(smu->adev, false); 1482 1483 ret = smu_hw_fini(adev); 1484 if (ret) 1485 return ret; 1486 1487 ret = smu_hw_init(adev); 1488 if (ret) 1489 return ret; 1490 1491 ret = smu_late_init(adev); 1492 if (ret) 1493 return ret; 1494 1495 amdgpu_gfx_off_ctrl(smu->adev, true); 1496 1497 return 0; 1498 } 1499 1500 static int smu_suspend(void *handle) 1501 { 1502 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1503 struct smu_context *smu = &adev->smu; 1504 int ret; 1505 1506 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1507 return 0; 1508 1509 if (!smu->pm_enabled) 1510 return 0; 1511 1512 adev->pm.dpm_enabled = false; 1513 1514 ret = smu_smc_hw_cleanup(smu); 1515 if (ret) 1516 return ret; 1517 1518 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1519 1520 /* skip CGPG when in S0ix */ 1521 if (smu->is_apu && !adev->in_s0ix) 1522 smu_set_gfx_cgpg(&adev->smu, false); 1523 1524 return 0; 1525 } 1526 1527 static int smu_resume(void *handle) 1528 { 1529 int ret; 1530 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1531 struct smu_context *smu = &adev->smu; 1532 1533 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1534 return 0; 1535 1536 if (!smu->pm_enabled) 1537 return 0; 1538 1539 dev_info(adev->dev, "SMU is resuming...\n"); 1540 1541 ret = smu_start_smc_engine(smu); 1542 if (ret) { 1543 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1544 return ret; 1545 } 1546 1547 ret = smu_smc_hw_setup(smu); 1548 if (ret) { 1549 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1550 return ret; 1551 } 1552 1553 if (smu->is_apu) 1554 smu_set_gfx_cgpg(&adev->smu, true); 1555 1556 smu->disable_uclk_switch = 0; 1557 1558 adev->pm.dpm_enabled = true; 1559 1560 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1561 1562 return 0; 1563 } 1564 1565 static int smu_display_configuration_change(void *handle, 1566 const struct amd_pp_display_configuration *display_config) 1567 { 1568 struct smu_context *smu = handle; 1569 int index = 0; 1570 int num_of_active_display = 0; 1571 1572 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1573 return -EOPNOTSUPP; 1574 1575 if (!display_config) 1576 return -EINVAL; 1577 1578 mutex_lock(&smu->mutex); 1579 1580 smu_set_min_dcef_deep_sleep(smu, 1581 display_config->min_dcef_deep_sleep_set_clk / 100); 1582 1583 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1584 if (display_config->displays[index].controller_id != 0) 1585 num_of_active_display++; 1586 } 1587 1588 mutex_unlock(&smu->mutex); 1589 1590 return 0; 1591 } 1592 1593 static int smu_set_clockgating_state(void *handle, 1594 enum amd_clockgating_state state) 1595 { 1596 return 0; 1597 } 1598 1599 static int smu_set_powergating_state(void *handle, 1600 enum amd_powergating_state state) 1601 { 1602 return 0; 1603 } 1604 1605 static int smu_enable_umd_pstate(void *handle, 1606 enum amd_dpm_forced_level *level) 1607 { 1608 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1609 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1610 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1611 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1612 1613 struct smu_context *smu = (struct smu_context*)(handle); 1614 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1615 1616 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1617 return -EINVAL; 1618 1619 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1620 /* enter umd pstate, save current level, disable gfx cg*/ 1621 if (*level & profile_mode_mask) { 1622 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1623 smu_dpm_ctx->enable_umd_pstate = true; 1624 smu_gpo_control(smu, false); 1625 amdgpu_device_ip_set_powergating_state(smu->adev, 1626 AMD_IP_BLOCK_TYPE_GFX, 1627 AMD_PG_STATE_UNGATE); 1628 amdgpu_device_ip_set_clockgating_state(smu->adev, 1629 AMD_IP_BLOCK_TYPE_GFX, 1630 AMD_CG_STATE_UNGATE); 1631 smu_gfx_ulv_control(smu, false); 1632 smu_deep_sleep_control(smu, false); 1633 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1634 } 1635 } else { 1636 /* exit umd pstate, restore level, enable gfx cg*/ 1637 if (!(*level & profile_mode_mask)) { 1638 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1639 *level = smu_dpm_ctx->saved_dpm_level; 1640 smu_dpm_ctx->enable_umd_pstate = false; 1641 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1642 smu_deep_sleep_control(smu, true); 1643 smu_gfx_ulv_control(smu, true); 1644 amdgpu_device_ip_set_clockgating_state(smu->adev, 1645 AMD_IP_BLOCK_TYPE_GFX, 1646 AMD_CG_STATE_GATE); 1647 amdgpu_device_ip_set_powergating_state(smu->adev, 1648 AMD_IP_BLOCK_TYPE_GFX, 1649 AMD_PG_STATE_GATE); 1650 smu_gpo_control(smu, true); 1651 } 1652 } 1653 1654 return 0; 1655 } 1656 1657 static int smu_bump_power_profile_mode(struct smu_context *smu, 1658 long *param, 1659 uint32_t param_size) 1660 { 1661 int ret = 0; 1662 1663 if (smu->ppt_funcs->set_power_profile_mode) 1664 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1665 1666 return ret; 1667 } 1668 1669 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1670 enum amd_dpm_forced_level level, 1671 bool skip_display_settings) 1672 { 1673 int ret = 0; 1674 int index = 0; 1675 long workload; 1676 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1677 1678 if (!skip_display_settings) { 1679 ret = smu_display_config_changed(smu); 1680 if (ret) { 1681 dev_err(smu->adev->dev, "Failed to change display config!"); 1682 return ret; 1683 } 1684 } 1685 1686 ret = smu_apply_clocks_adjust_rules(smu); 1687 if (ret) { 1688 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1689 return ret; 1690 } 1691 1692 if (!skip_display_settings) { 1693 ret = smu_notify_smc_display_config(smu); 1694 if (ret) { 1695 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1696 return ret; 1697 } 1698 } 1699 1700 if (smu_dpm_ctx->dpm_level != level) { 1701 ret = smu_asic_set_performance_level(smu, level); 1702 if (ret) { 1703 dev_err(smu->adev->dev, "Failed to set performance level!"); 1704 return ret; 1705 } 1706 1707 /* update the saved copy */ 1708 smu_dpm_ctx->dpm_level = level; 1709 } 1710 1711 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1712 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1713 index = fls(smu->workload_mask); 1714 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1715 workload = smu->workload_setting[index]; 1716 1717 if (smu->power_profile_mode != workload) 1718 smu_bump_power_profile_mode(smu, &workload, 0); 1719 } 1720 1721 return ret; 1722 } 1723 1724 static int smu_handle_task(struct smu_context *smu, 1725 enum amd_dpm_forced_level level, 1726 enum amd_pp_task task_id, 1727 bool lock_needed) 1728 { 1729 int ret = 0; 1730 1731 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1732 return -EOPNOTSUPP; 1733 1734 if (lock_needed) 1735 mutex_lock(&smu->mutex); 1736 1737 switch (task_id) { 1738 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1739 ret = smu_pre_display_config_changed(smu); 1740 if (ret) 1741 goto out; 1742 ret = smu_adjust_power_state_dynamic(smu, level, false); 1743 break; 1744 case AMD_PP_TASK_COMPLETE_INIT: 1745 case AMD_PP_TASK_READJUST_POWER_STATE: 1746 ret = smu_adjust_power_state_dynamic(smu, level, true); 1747 break; 1748 default: 1749 break; 1750 } 1751 1752 out: 1753 if (lock_needed) 1754 mutex_unlock(&smu->mutex); 1755 1756 return ret; 1757 } 1758 1759 static int smu_handle_dpm_task(void *handle, 1760 enum amd_pp_task task_id, 1761 enum amd_pm_state_type *user_state) 1762 { 1763 struct smu_context *smu = handle; 1764 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1765 1766 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1767 1768 } 1769 1770 static int smu_switch_power_profile(void *handle, 1771 enum PP_SMC_POWER_PROFILE type, 1772 bool en) 1773 { 1774 struct smu_context *smu = handle; 1775 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1776 long workload; 1777 uint32_t index; 1778 1779 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1780 return -EOPNOTSUPP; 1781 1782 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1783 return -EINVAL; 1784 1785 mutex_lock(&smu->mutex); 1786 1787 if (!en) { 1788 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1789 index = fls(smu->workload_mask); 1790 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1791 workload = smu->workload_setting[index]; 1792 } else { 1793 smu->workload_mask |= (1 << smu->workload_prority[type]); 1794 index = fls(smu->workload_mask); 1795 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1796 workload = smu->workload_setting[index]; 1797 } 1798 1799 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1800 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1801 smu_bump_power_profile_mode(smu, &workload, 0); 1802 1803 mutex_unlock(&smu->mutex); 1804 1805 return 0; 1806 } 1807 1808 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1809 { 1810 struct smu_context *smu = handle; 1811 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1812 enum amd_dpm_forced_level level; 1813 1814 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1815 return -EOPNOTSUPP; 1816 1817 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1818 return -EINVAL; 1819 1820 mutex_lock(&(smu->mutex)); 1821 level = smu_dpm_ctx->dpm_level; 1822 mutex_unlock(&(smu->mutex)); 1823 1824 return level; 1825 } 1826 1827 static int smu_force_performance_level(void *handle, 1828 enum amd_dpm_forced_level level) 1829 { 1830 struct smu_context *smu = handle; 1831 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1832 int ret = 0; 1833 1834 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1835 return -EOPNOTSUPP; 1836 1837 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1838 return -EINVAL; 1839 1840 mutex_lock(&smu->mutex); 1841 1842 ret = smu_enable_umd_pstate(smu, &level); 1843 if (ret) { 1844 mutex_unlock(&smu->mutex); 1845 return ret; 1846 } 1847 1848 ret = smu_handle_task(smu, level, 1849 AMD_PP_TASK_READJUST_POWER_STATE, 1850 false); 1851 1852 mutex_unlock(&smu->mutex); 1853 1854 /* reset user dpm clock state */ 1855 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1856 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1857 smu->user_dpm_profile.clk_dependency = 0; 1858 } 1859 1860 return ret; 1861 } 1862 1863 static int smu_set_display_count(void *handle, uint32_t count) 1864 { 1865 struct smu_context *smu = handle; 1866 int ret = 0; 1867 1868 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1869 return -EOPNOTSUPP; 1870 1871 mutex_lock(&smu->mutex); 1872 ret = smu_init_display_count(smu, count); 1873 mutex_unlock(&smu->mutex); 1874 1875 return ret; 1876 } 1877 1878 static int smu_force_smuclk_levels(struct smu_context *smu, 1879 enum smu_clk_type clk_type, 1880 uint32_t mask) 1881 { 1882 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1883 int ret = 0; 1884 1885 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1886 return -EOPNOTSUPP; 1887 1888 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1889 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1890 return -EINVAL; 1891 } 1892 1893 mutex_lock(&smu->mutex); 1894 1895 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1896 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1897 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1898 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1899 smu_set_user_clk_dependencies(smu, clk_type); 1900 } 1901 } 1902 1903 mutex_unlock(&smu->mutex); 1904 1905 return ret; 1906 } 1907 1908 static int smu_force_ppclk_levels(void *handle, 1909 enum pp_clock_type type, 1910 uint32_t mask) 1911 { 1912 struct smu_context *smu = handle; 1913 enum smu_clk_type clk_type; 1914 1915 switch (type) { 1916 case PP_SCLK: 1917 clk_type = SMU_SCLK; break; 1918 case PP_MCLK: 1919 clk_type = SMU_MCLK; break; 1920 case PP_PCIE: 1921 clk_type = SMU_PCIE; break; 1922 case PP_SOCCLK: 1923 clk_type = SMU_SOCCLK; break; 1924 case PP_FCLK: 1925 clk_type = SMU_FCLK; break; 1926 case PP_DCEFCLK: 1927 clk_type = SMU_DCEFCLK; break; 1928 case PP_VCLK: 1929 clk_type = SMU_VCLK; break; 1930 case PP_DCLK: 1931 clk_type = SMU_DCLK; break; 1932 case OD_SCLK: 1933 clk_type = SMU_OD_SCLK; break; 1934 case OD_MCLK: 1935 clk_type = SMU_OD_MCLK; break; 1936 case OD_VDDC_CURVE: 1937 clk_type = SMU_OD_VDDC_CURVE; break; 1938 case OD_RANGE: 1939 clk_type = SMU_OD_RANGE; break; 1940 default: 1941 return -EINVAL; 1942 } 1943 1944 return smu_force_smuclk_levels(smu, clk_type, mask); 1945 } 1946 1947 /* 1948 * On system suspending or resetting, the dpm_enabled 1949 * flag will be cleared. So that those SMU services which 1950 * are not supported will be gated. 1951 * However, the mp1 state setting should still be granted 1952 * even if the dpm_enabled cleared. 1953 */ 1954 static int smu_set_mp1_state(void *handle, 1955 enum pp_mp1_state mp1_state) 1956 { 1957 struct smu_context *smu = handle; 1958 int ret = 0; 1959 1960 if (!smu->pm_enabled) 1961 return -EOPNOTSUPP; 1962 1963 mutex_lock(&smu->mutex); 1964 1965 if (smu->ppt_funcs && 1966 smu->ppt_funcs->set_mp1_state) 1967 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1968 1969 mutex_unlock(&smu->mutex); 1970 1971 return ret; 1972 } 1973 1974 static int smu_set_df_cstate(void *handle, 1975 enum pp_df_cstate state) 1976 { 1977 struct smu_context *smu = handle; 1978 int ret = 0; 1979 1980 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1981 return -EOPNOTSUPP; 1982 1983 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1984 return 0; 1985 1986 mutex_lock(&smu->mutex); 1987 1988 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1989 if (ret) 1990 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1991 1992 mutex_unlock(&smu->mutex); 1993 1994 return ret; 1995 } 1996 1997 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1998 { 1999 int ret = 0; 2000 2001 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2002 return -EOPNOTSUPP; 2003 2004 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2005 return 0; 2006 2007 mutex_lock(&smu->mutex); 2008 2009 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2010 if (ret) 2011 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2012 2013 mutex_unlock(&smu->mutex); 2014 2015 return ret; 2016 } 2017 2018 int smu_write_watermarks_table(struct smu_context *smu) 2019 { 2020 int ret = 0; 2021 2022 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2023 return -EOPNOTSUPP; 2024 2025 mutex_lock(&smu->mutex); 2026 2027 ret = smu_set_watermarks_table(smu, NULL); 2028 2029 mutex_unlock(&smu->mutex); 2030 2031 return ret; 2032 } 2033 2034 static int smu_set_watermarks_for_clock_ranges(void *handle, 2035 struct pp_smu_wm_range_sets *clock_ranges) 2036 { 2037 struct smu_context *smu = handle; 2038 int ret = 0; 2039 2040 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2041 return -EOPNOTSUPP; 2042 2043 if (smu->disable_watermark) 2044 return 0; 2045 2046 mutex_lock(&smu->mutex); 2047 2048 ret = smu_set_watermarks_table(smu, clock_ranges); 2049 2050 mutex_unlock(&smu->mutex); 2051 2052 return ret; 2053 } 2054 2055 int smu_set_ac_dc(struct smu_context *smu) 2056 { 2057 int ret = 0; 2058 2059 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2060 return -EOPNOTSUPP; 2061 2062 /* controlled by firmware */ 2063 if (smu->dc_controlled_by_gpio) 2064 return 0; 2065 2066 mutex_lock(&smu->mutex); 2067 ret = smu_set_power_source(smu, 2068 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2069 SMU_POWER_SOURCE_DC); 2070 if (ret) 2071 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2072 smu->adev->pm.ac_power ? "AC" : "DC"); 2073 mutex_unlock(&smu->mutex); 2074 2075 return ret; 2076 } 2077 2078 const struct amd_ip_funcs smu_ip_funcs = { 2079 .name = "smu", 2080 .early_init = smu_early_init, 2081 .late_init = smu_late_init, 2082 .sw_init = smu_sw_init, 2083 .sw_fini = smu_sw_fini, 2084 .hw_init = smu_hw_init, 2085 .hw_fini = smu_hw_fini, 2086 .suspend = smu_suspend, 2087 .resume = smu_resume, 2088 .is_idle = NULL, 2089 .check_soft_reset = NULL, 2090 .wait_for_idle = NULL, 2091 .soft_reset = NULL, 2092 .set_clockgating_state = smu_set_clockgating_state, 2093 .set_powergating_state = smu_set_powergating_state, 2094 .enable_umd_pstate = smu_enable_umd_pstate, 2095 }; 2096 2097 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2098 { 2099 .type = AMD_IP_BLOCK_TYPE_SMC, 2100 .major = 11, 2101 .minor = 0, 2102 .rev = 0, 2103 .funcs = &smu_ip_funcs, 2104 }; 2105 2106 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2107 { 2108 .type = AMD_IP_BLOCK_TYPE_SMC, 2109 .major = 12, 2110 .minor = 0, 2111 .rev = 0, 2112 .funcs = &smu_ip_funcs, 2113 }; 2114 2115 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2116 { 2117 .type = AMD_IP_BLOCK_TYPE_SMC, 2118 .major = 13, 2119 .minor = 0, 2120 .rev = 0, 2121 .funcs = &smu_ip_funcs, 2122 }; 2123 2124 static int smu_load_microcode(void *handle) 2125 { 2126 struct smu_context *smu = handle; 2127 struct amdgpu_device *adev = smu->adev; 2128 int ret = 0; 2129 2130 if (!smu->pm_enabled) 2131 return -EOPNOTSUPP; 2132 2133 /* This should be used for non PSP loading */ 2134 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2135 return 0; 2136 2137 if (smu->ppt_funcs->load_microcode) { 2138 ret = smu->ppt_funcs->load_microcode(smu); 2139 if (ret) { 2140 dev_err(adev->dev, "Load microcode failed\n"); 2141 return ret; 2142 } 2143 } 2144 2145 if (smu->ppt_funcs->check_fw_status) { 2146 ret = smu->ppt_funcs->check_fw_status(smu); 2147 if (ret) { 2148 dev_err(adev->dev, "SMC is not ready\n"); 2149 return ret; 2150 } 2151 } 2152 2153 return ret; 2154 } 2155 2156 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2157 { 2158 int ret = 0; 2159 2160 mutex_lock(&smu->mutex); 2161 2162 if (smu->ppt_funcs->set_gfx_cgpg) 2163 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2164 2165 mutex_unlock(&smu->mutex); 2166 2167 return ret; 2168 } 2169 2170 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2171 { 2172 struct smu_context *smu = handle; 2173 u32 percent; 2174 int ret = 0; 2175 2176 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2177 return -EOPNOTSUPP; 2178 2179 mutex_lock(&smu->mutex); 2180 2181 if (smu->ppt_funcs->set_fan_speed_percent) { 2182 percent = speed * 100 / smu->fan_max_rpm; 2183 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent); 2184 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2185 smu->user_dpm_profile.fan_speed_percent = percent; 2186 } 2187 2188 mutex_unlock(&smu->mutex); 2189 2190 return ret; 2191 } 2192 2193 /** 2194 * smu_get_power_limit - Request one of the SMU Power Limits 2195 * 2196 * @handle: pointer to smu context 2197 * @limit: requested limit is written back to this variable 2198 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2199 * @pp_power_type: &pp_power_type type of power 2200 * Return: 0 on success, <0 on error 2201 * 2202 */ 2203 int smu_get_power_limit(void *handle, 2204 uint32_t *limit, 2205 enum pp_power_limit_level pp_limit_level, 2206 enum pp_power_type pp_power_type) 2207 { 2208 struct smu_context *smu = handle; 2209 enum smu_ppt_limit_level limit_level; 2210 uint32_t limit_type; 2211 int ret = 0; 2212 2213 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2214 return -EOPNOTSUPP; 2215 2216 switch(pp_power_type) { 2217 case PP_PWR_TYPE_SUSTAINED: 2218 limit_type = SMU_DEFAULT_PPT_LIMIT; 2219 break; 2220 case PP_PWR_TYPE_FAST: 2221 limit_type = SMU_FAST_PPT_LIMIT; 2222 break; 2223 default: 2224 return -EOPNOTSUPP; 2225 break; 2226 } 2227 2228 switch(pp_limit_level){ 2229 case PP_PWR_LIMIT_CURRENT: 2230 limit_level = SMU_PPT_LIMIT_CURRENT; 2231 break; 2232 case PP_PWR_LIMIT_DEFAULT: 2233 limit_level = SMU_PPT_LIMIT_DEFAULT; 2234 break; 2235 case PP_PWR_LIMIT_MAX: 2236 limit_level = SMU_PPT_LIMIT_MAX; 2237 break; 2238 case PP_PWR_LIMIT_MIN: 2239 default: 2240 return -EOPNOTSUPP; 2241 break; 2242 } 2243 2244 mutex_lock(&smu->mutex); 2245 2246 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2247 if (smu->ppt_funcs->get_ppt_limit) 2248 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2249 } else { 2250 switch (limit_level) { 2251 case SMU_PPT_LIMIT_CURRENT: 2252 if ((smu->adev->asic_type == CHIP_ALDEBARAN) || 2253 (smu->adev->asic_type == CHIP_SIENNA_CICHLID) || 2254 (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) || 2255 (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) || 2256 (smu->adev->asic_type == CHIP_BEIGE_GOBY)) 2257 ret = smu_get_asic_power_limits(smu, 2258 &smu->current_power_limit, 2259 NULL, 2260 NULL); 2261 *limit = smu->current_power_limit; 2262 break; 2263 case SMU_PPT_LIMIT_DEFAULT: 2264 *limit = smu->default_power_limit; 2265 break; 2266 case SMU_PPT_LIMIT_MAX: 2267 *limit = smu->max_power_limit; 2268 break; 2269 default: 2270 break; 2271 } 2272 } 2273 2274 mutex_unlock(&smu->mutex); 2275 2276 return ret; 2277 } 2278 2279 static int smu_set_power_limit(void *handle, uint32_t limit) 2280 { 2281 struct smu_context *smu = handle; 2282 uint32_t limit_type = limit >> 24; 2283 int ret = 0; 2284 2285 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2286 return -EOPNOTSUPP; 2287 2288 mutex_lock(&smu->mutex); 2289 2290 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2291 if (smu->ppt_funcs->set_power_limit) { 2292 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2293 goto out; 2294 } 2295 2296 if (limit > smu->max_power_limit) { 2297 dev_err(smu->adev->dev, 2298 "New power limit (%d) is over the max allowed %d\n", 2299 limit, smu->max_power_limit); 2300 ret = -EINVAL; 2301 goto out; 2302 } 2303 2304 if (!limit) 2305 limit = smu->current_power_limit; 2306 2307 if (smu->ppt_funcs->set_power_limit) { 2308 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2309 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2310 smu->user_dpm_profile.power_limit = limit; 2311 } 2312 2313 out: 2314 mutex_unlock(&smu->mutex); 2315 2316 return ret; 2317 } 2318 2319 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2320 { 2321 int ret = 0; 2322 2323 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2324 return -EOPNOTSUPP; 2325 2326 mutex_lock(&smu->mutex); 2327 2328 if (smu->ppt_funcs->print_clk_levels) 2329 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2330 2331 mutex_unlock(&smu->mutex); 2332 2333 return ret; 2334 } 2335 2336 static int smu_print_ppclk_levels(void *handle, 2337 enum pp_clock_type type, 2338 char *buf) 2339 { 2340 struct smu_context *smu = handle; 2341 enum smu_clk_type clk_type; 2342 2343 switch (type) { 2344 case PP_SCLK: 2345 clk_type = SMU_SCLK; break; 2346 case PP_MCLK: 2347 clk_type = SMU_MCLK; break; 2348 case PP_PCIE: 2349 clk_type = SMU_PCIE; break; 2350 case PP_SOCCLK: 2351 clk_type = SMU_SOCCLK; break; 2352 case PP_FCLK: 2353 clk_type = SMU_FCLK; break; 2354 case PP_DCEFCLK: 2355 clk_type = SMU_DCEFCLK; break; 2356 case PP_VCLK: 2357 clk_type = SMU_VCLK; break; 2358 case PP_DCLK: 2359 clk_type = SMU_DCLK; break; 2360 case OD_SCLK: 2361 clk_type = SMU_OD_SCLK; break; 2362 case OD_MCLK: 2363 clk_type = SMU_OD_MCLK; break; 2364 case OD_VDDC_CURVE: 2365 clk_type = SMU_OD_VDDC_CURVE; break; 2366 case OD_RANGE: 2367 clk_type = SMU_OD_RANGE; break; 2368 case OD_VDDGFX_OFFSET: 2369 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2370 case OD_CCLK: 2371 clk_type = SMU_OD_CCLK; break; 2372 default: 2373 return -EINVAL; 2374 } 2375 2376 return smu_print_smuclk_levels(smu, clk_type, buf); 2377 } 2378 2379 static int smu_od_edit_dpm_table(void *handle, 2380 enum PP_OD_DPM_TABLE_COMMAND type, 2381 long *input, uint32_t size) 2382 { 2383 struct smu_context *smu = handle; 2384 int ret = 0; 2385 2386 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2387 return -EOPNOTSUPP; 2388 2389 mutex_lock(&smu->mutex); 2390 2391 if (smu->ppt_funcs->od_edit_dpm_table) { 2392 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2393 } 2394 2395 mutex_unlock(&smu->mutex); 2396 2397 return ret; 2398 } 2399 2400 static int smu_read_sensor(void *handle, 2401 int sensor, 2402 void *data, 2403 int *size_arg) 2404 { 2405 struct smu_context *smu = handle; 2406 struct smu_umd_pstate_table *pstate_table = 2407 &smu->pstate_table; 2408 int ret = 0; 2409 uint32_t *size, size_val; 2410 2411 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2412 return -EOPNOTSUPP; 2413 2414 if (!data || !size_arg) 2415 return -EINVAL; 2416 2417 size_val = *size_arg; 2418 size = &size_val; 2419 2420 mutex_lock(&smu->mutex); 2421 2422 if (smu->ppt_funcs->read_sensor) 2423 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2424 goto unlock; 2425 2426 switch (sensor) { 2427 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2428 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2429 *size = 4; 2430 break; 2431 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2432 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2433 *size = 4; 2434 break; 2435 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2436 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2437 *size = 8; 2438 break; 2439 case AMDGPU_PP_SENSOR_UVD_POWER: 2440 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2441 *size = 4; 2442 break; 2443 case AMDGPU_PP_SENSOR_VCE_POWER: 2444 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2445 *size = 4; 2446 break; 2447 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2448 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2449 *size = 4; 2450 break; 2451 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2452 *(uint32_t *)data = 0; 2453 *size = 4; 2454 break; 2455 default: 2456 *size = 0; 2457 ret = -EOPNOTSUPP; 2458 break; 2459 } 2460 2461 unlock: 2462 mutex_unlock(&smu->mutex); 2463 2464 // assign uint32_t to int 2465 *size_arg = size_val; 2466 2467 return ret; 2468 } 2469 2470 static int smu_get_power_profile_mode(void *handle, char *buf) 2471 { 2472 struct smu_context *smu = handle; 2473 int ret = 0; 2474 2475 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2476 return -EOPNOTSUPP; 2477 2478 mutex_lock(&smu->mutex); 2479 2480 if (smu->ppt_funcs->get_power_profile_mode) 2481 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2482 2483 mutex_unlock(&smu->mutex); 2484 2485 return ret; 2486 } 2487 2488 static int smu_set_power_profile_mode(void *handle, 2489 long *param, 2490 uint32_t param_size) 2491 { 2492 struct smu_context *smu = handle; 2493 int ret = 0; 2494 2495 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2496 return -EOPNOTSUPP; 2497 2498 mutex_lock(&smu->mutex); 2499 2500 smu_bump_power_profile_mode(smu, param, param_size); 2501 2502 mutex_unlock(&smu->mutex); 2503 2504 return ret; 2505 } 2506 2507 2508 static u32 smu_get_fan_control_mode(void *handle) 2509 { 2510 struct smu_context *smu = handle; 2511 u32 ret = 0; 2512 2513 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2514 return AMD_FAN_CTRL_NONE; 2515 2516 mutex_lock(&smu->mutex); 2517 2518 if (smu->ppt_funcs->get_fan_control_mode) 2519 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2520 2521 mutex_unlock(&smu->mutex); 2522 2523 return ret; 2524 } 2525 2526 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2527 { 2528 int ret = 0; 2529 2530 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2531 return -EOPNOTSUPP; 2532 2533 mutex_lock(&smu->mutex); 2534 2535 if (smu->ppt_funcs->set_fan_control_mode) { 2536 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2537 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2538 smu->user_dpm_profile.fan_mode = value; 2539 } 2540 2541 mutex_unlock(&smu->mutex); 2542 2543 /* reset user dpm fan speed */ 2544 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2545 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2546 smu->user_dpm_profile.fan_speed_percent = 0; 2547 2548 return ret; 2549 } 2550 2551 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2552 { 2553 struct smu_context *smu = handle; 2554 2555 smu_set_fan_control_mode(smu, value); 2556 } 2557 2558 2559 static int smu_get_fan_speed_percent(void *handle, u32 *speed) 2560 { 2561 struct smu_context *smu = handle; 2562 int ret = 0; 2563 uint32_t percent; 2564 2565 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2566 return -EOPNOTSUPP; 2567 2568 mutex_lock(&smu->mutex); 2569 2570 if (smu->ppt_funcs->get_fan_speed_percent) { 2571 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2572 if (!ret) { 2573 *speed = percent > 100 ? 100 : percent; 2574 } 2575 } 2576 2577 mutex_unlock(&smu->mutex); 2578 2579 2580 return ret; 2581 } 2582 2583 static int smu_set_fan_speed_percent(void *handle, u32 speed) 2584 { 2585 struct smu_context *smu = handle; 2586 int ret = 0; 2587 2588 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2589 return -EOPNOTSUPP; 2590 2591 mutex_lock(&smu->mutex); 2592 2593 if (smu->ppt_funcs->set_fan_speed_percent) { 2594 if (speed > 100) 2595 speed = 100; 2596 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed); 2597 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2598 smu->user_dpm_profile.fan_speed_percent = speed; 2599 } 2600 2601 mutex_unlock(&smu->mutex); 2602 2603 return ret; 2604 } 2605 2606 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2607 { 2608 struct smu_context *smu = handle; 2609 int ret = 0; 2610 u32 percent; 2611 2612 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2613 return -EOPNOTSUPP; 2614 2615 mutex_lock(&smu->mutex); 2616 2617 if (smu->ppt_funcs->get_fan_speed_percent) { 2618 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2619 *speed = percent * smu->fan_max_rpm / 100; 2620 } 2621 2622 mutex_unlock(&smu->mutex); 2623 2624 return ret; 2625 } 2626 2627 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2628 { 2629 struct smu_context *smu = handle; 2630 int ret = 0; 2631 2632 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2633 return -EOPNOTSUPP; 2634 2635 mutex_lock(&smu->mutex); 2636 2637 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2638 2639 mutex_unlock(&smu->mutex); 2640 2641 return ret; 2642 } 2643 2644 static int smu_get_clock_by_type_with_latency(void *handle, 2645 enum amd_pp_clock_type type, 2646 struct pp_clock_levels_with_latency *clocks) 2647 { 2648 struct smu_context *smu = handle; 2649 enum smu_clk_type clk_type; 2650 int ret = 0; 2651 2652 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2653 return -EOPNOTSUPP; 2654 2655 mutex_lock(&smu->mutex); 2656 2657 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2658 switch (type) { 2659 case amd_pp_sys_clock: 2660 clk_type = SMU_GFXCLK; 2661 break; 2662 case amd_pp_mem_clock: 2663 clk_type = SMU_MCLK; 2664 break; 2665 case amd_pp_dcef_clock: 2666 clk_type = SMU_DCEFCLK; 2667 break; 2668 case amd_pp_disp_clock: 2669 clk_type = SMU_DISPCLK; 2670 break; 2671 default: 2672 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2673 mutex_unlock(&smu->mutex); 2674 return -EINVAL; 2675 } 2676 2677 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2678 } 2679 2680 mutex_unlock(&smu->mutex); 2681 2682 return ret; 2683 } 2684 2685 static int smu_display_clock_voltage_request(void *handle, 2686 struct pp_display_clock_request *clock_req) 2687 { 2688 struct smu_context *smu = handle; 2689 int ret = 0; 2690 2691 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2692 return -EOPNOTSUPP; 2693 2694 mutex_lock(&smu->mutex); 2695 2696 if (smu->ppt_funcs->display_clock_voltage_request) 2697 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2698 2699 mutex_unlock(&smu->mutex); 2700 2701 return ret; 2702 } 2703 2704 2705 static int smu_display_disable_memory_clock_switch(void *handle, 2706 bool disable_memory_clock_switch) 2707 { 2708 struct smu_context *smu = handle; 2709 int ret = -EINVAL; 2710 2711 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2712 return -EOPNOTSUPP; 2713 2714 mutex_lock(&smu->mutex); 2715 2716 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2717 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2718 2719 mutex_unlock(&smu->mutex); 2720 2721 return ret; 2722 } 2723 2724 static int smu_set_xgmi_pstate(void *handle, 2725 uint32_t pstate) 2726 { 2727 struct smu_context *smu = handle; 2728 int ret = 0; 2729 2730 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2731 return -EOPNOTSUPP; 2732 2733 mutex_lock(&smu->mutex); 2734 2735 if (smu->ppt_funcs->set_xgmi_pstate) 2736 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2737 2738 mutex_unlock(&smu->mutex); 2739 2740 if(ret) 2741 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2742 2743 return ret; 2744 } 2745 2746 static int smu_get_baco_capability(void *handle, bool *cap) 2747 { 2748 struct smu_context *smu = handle; 2749 int ret = 0; 2750 2751 *cap = false; 2752 2753 if (!smu->pm_enabled) 2754 return 0; 2755 2756 mutex_lock(&smu->mutex); 2757 2758 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2759 *cap = smu->ppt_funcs->baco_is_support(smu); 2760 2761 mutex_unlock(&smu->mutex); 2762 2763 return ret; 2764 } 2765 2766 static int smu_baco_set_state(void *handle, int state) 2767 { 2768 struct smu_context *smu = handle; 2769 int ret = 0; 2770 2771 if (!smu->pm_enabled) 2772 return -EOPNOTSUPP; 2773 2774 if (state == 0) { 2775 mutex_lock(&smu->mutex); 2776 2777 if (smu->ppt_funcs->baco_exit) 2778 ret = smu->ppt_funcs->baco_exit(smu); 2779 2780 mutex_unlock(&smu->mutex); 2781 } else if (state == 1) { 2782 mutex_lock(&smu->mutex); 2783 2784 if (smu->ppt_funcs->baco_enter) 2785 ret = smu->ppt_funcs->baco_enter(smu); 2786 2787 mutex_unlock(&smu->mutex); 2788 2789 } else { 2790 return -EINVAL; 2791 } 2792 2793 if (ret) 2794 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2795 (state)?"enter":"exit"); 2796 2797 return ret; 2798 } 2799 2800 bool smu_mode1_reset_is_support(struct smu_context *smu) 2801 { 2802 bool ret = false; 2803 2804 if (!smu->pm_enabled) 2805 return false; 2806 2807 mutex_lock(&smu->mutex); 2808 2809 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2810 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2811 2812 mutex_unlock(&smu->mutex); 2813 2814 return ret; 2815 } 2816 2817 bool smu_mode2_reset_is_support(struct smu_context *smu) 2818 { 2819 bool ret = false; 2820 2821 if (!smu->pm_enabled) 2822 return false; 2823 2824 mutex_lock(&smu->mutex); 2825 2826 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2827 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2828 2829 mutex_unlock(&smu->mutex); 2830 2831 return ret; 2832 } 2833 2834 int smu_mode1_reset(struct smu_context *smu) 2835 { 2836 int ret = 0; 2837 2838 if (!smu->pm_enabled) 2839 return -EOPNOTSUPP; 2840 2841 mutex_lock(&smu->mutex); 2842 2843 if (smu->ppt_funcs->mode1_reset) 2844 ret = smu->ppt_funcs->mode1_reset(smu); 2845 2846 mutex_unlock(&smu->mutex); 2847 2848 return ret; 2849 } 2850 2851 static int smu_mode2_reset(void *handle) 2852 { 2853 struct smu_context *smu = handle; 2854 int ret = 0; 2855 2856 if (!smu->pm_enabled) 2857 return -EOPNOTSUPP; 2858 2859 mutex_lock(&smu->mutex); 2860 2861 if (smu->ppt_funcs->mode2_reset) 2862 ret = smu->ppt_funcs->mode2_reset(smu); 2863 2864 mutex_unlock(&smu->mutex); 2865 2866 if (ret) 2867 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2868 2869 return ret; 2870 } 2871 2872 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2873 struct pp_smu_nv_clock_table *max_clocks) 2874 { 2875 struct smu_context *smu = handle; 2876 int ret = 0; 2877 2878 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2879 return -EOPNOTSUPP; 2880 2881 mutex_lock(&smu->mutex); 2882 2883 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2884 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2885 2886 mutex_unlock(&smu->mutex); 2887 2888 return ret; 2889 } 2890 2891 static int smu_get_uclk_dpm_states(void *handle, 2892 unsigned int *clock_values_in_khz, 2893 unsigned int *num_states) 2894 { 2895 struct smu_context *smu = handle; 2896 int ret = 0; 2897 2898 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2899 return -EOPNOTSUPP; 2900 2901 mutex_lock(&smu->mutex); 2902 2903 if (smu->ppt_funcs->get_uclk_dpm_states) 2904 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2905 2906 mutex_unlock(&smu->mutex); 2907 2908 return ret; 2909 } 2910 2911 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2912 { 2913 struct smu_context *smu = handle; 2914 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2915 2916 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2917 return -EOPNOTSUPP; 2918 2919 mutex_lock(&smu->mutex); 2920 2921 if (smu->ppt_funcs->get_current_power_state) 2922 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2923 2924 mutex_unlock(&smu->mutex); 2925 2926 return pm_state; 2927 } 2928 2929 static int smu_get_dpm_clock_table(void *handle, 2930 struct dpm_clocks *clock_table) 2931 { 2932 struct smu_context *smu = handle; 2933 int ret = 0; 2934 2935 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2936 return -EOPNOTSUPP; 2937 2938 mutex_lock(&smu->mutex); 2939 2940 if (smu->ppt_funcs->get_dpm_clock_table) 2941 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2942 2943 mutex_unlock(&smu->mutex); 2944 2945 return ret; 2946 } 2947 2948 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2949 { 2950 struct smu_context *smu = handle; 2951 ssize_t size; 2952 2953 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2954 return -EOPNOTSUPP; 2955 2956 if (!smu->ppt_funcs->get_gpu_metrics) 2957 return -EOPNOTSUPP; 2958 2959 mutex_lock(&smu->mutex); 2960 2961 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2962 2963 mutex_unlock(&smu->mutex); 2964 2965 return size; 2966 } 2967 2968 static int smu_enable_mgpu_fan_boost(void *handle) 2969 { 2970 struct smu_context *smu = handle; 2971 int ret = 0; 2972 2973 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2974 return -EOPNOTSUPP; 2975 2976 mutex_lock(&smu->mutex); 2977 2978 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2979 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2980 2981 mutex_unlock(&smu->mutex); 2982 2983 return ret; 2984 } 2985 2986 static int smu_gfx_state_change_set(void *handle, 2987 uint32_t state) 2988 { 2989 struct smu_context *smu = handle; 2990 int ret = 0; 2991 2992 mutex_lock(&smu->mutex); 2993 if (smu->ppt_funcs->gfx_state_change_set) 2994 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2995 mutex_unlock(&smu->mutex); 2996 2997 return ret; 2998 } 2999 3000 int smu_set_light_sbr(struct smu_context *smu, bool enable) 3001 { 3002 int ret = 0; 3003 3004 mutex_lock(&smu->mutex); 3005 if (smu->ppt_funcs->set_light_sbr) 3006 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 3007 mutex_unlock(&smu->mutex); 3008 3009 return ret; 3010 } 3011 3012 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3013 { 3014 struct smu_context *smu = handle; 3015 struct smu_table_context *smu_table = &smu->smu_table; 3016 struct smu_table *memory_pool = &smu_table->memory_pool; 3017 3018 if (!addr || !size) 3019 return -EINVAL; 3020 3021 *addr = NULL; 3022 *size = 0; 3023 mutex_lock(&smu->mutex); 3024 if (memory_pool->bo) { 3025 *addr = memory_pool->cpu_addr; 3026 *size = memory_pool->size; 3027 } 3028 mutex_unlock(&smu->mutex); 3029 3030 return 0; 3031 } 3032 3033 static const struct amd_pm_funcs swsmu_pm_funcs = { 3034 /* export for sysfs */ 3035 .set_fan_control_mode = smu_pp_set_fan_control_mode, 3036 .get_fan_control_mode = smu_get_fan_control_mode, 3037 .set_fan_speed_percent = smu_set_fan_speed_percent, 3038 .get_fan_speed_percent = smu_get_fan_speed_percent, 3039 .force_clock_level = smu_force_ppclk_levels, 3040 .print_clock_levels = smu_print_ppclk_levels, 3041 .force_performance_level = smu_force_performance_level, 3042 .read_sensor = smu_read_sensor, 3043 .get_performance_level = smu_get_performance_level, 3044 .get_current_power_state = smu_get_current_power_state, 3045 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3046 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3047 .get_pp_num_states = smu_get_power_num_states, 3048 .get_pp_table = smu_sys_get_pp_table, 3049 .set_pp_table = smu_sys_set_pp_table, 3050 .switch_power_profile = smu_switch_power_profile, 3051 /* export to amdgpu */ 3052 .dispatch_tasks = smu_handle_dpm_task, 3053 .load_firmware = smu_load_microcode, 3054 .set_powergating_by_smu = smu_dpm_set_power_gate, 3055 .set_power_limit = smu_set_power_limit, 3056 .get_power_limit = smu_get_power_limit, 3057 .get_power_profile_mode = smu_get_power_profile_mode, 3058 .set_power_profile_mode = smu_set_power_profile_mode, 3059 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3060 .set_mp1_state = smu_set_mp1_state, 3061 .gfx_state_change_set = smu_gfx_state_change_set, 3062 /* export to DC */ 3063 .get_sclk = smu_get_sclk, 3064 .get_mclk = smu_get_mclk, 3065 .display_configuration_change = smu_display_configuration_change, 3066 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3067 .display_clock_voltage_request = smu_display_clock_voltage_request, 3068 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3069 .set_active_display_count = smu_set_display_count, 3070 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3071 .get_asic_baco_capability = smu_get_baco_capability, 3072 .set_asic_baco_state = smu_baco_set_state, 3073 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3074 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3075 .asic_reset_mode_2 = smu_mode2_reset, 3076 .set_df_cstate = smu_set_df_cstate, 3077 .set_xgmi_pstate = smu_set_xgmi_pstate, 3078 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3079 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3080 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3081 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3082 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3083 .get_dpm_clock_table = smu_get_dpm_clock_table, 3084 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3085 }; 3086 3087 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3088 uint64_t event_arg) 3089 { 3090 int ret = -EINVAL; 3091 struct smu_context *smu = &adev->smu; 3092 3093 if (smu->ppt_funcs->wait_for_event) { 3094 mutex_lock(&smu->mutex); 3095 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3096 mutex_unlock(&smu->mutex); 3097 } 3098 3099 return ret; 3100 } 3101