1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77 static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 80 static int smu_sys_get_pp_feature_mask(void *handle, 81 char *buf) 82 { 83 struct smu_context *smu = handle; 84 85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 86 return -EOPNOTSUPP; 87 88 return smu_get_pp_feature_mask(smu, buf); 89 } 90 91 static int smu_sys_set_pp_feature_mask(void *handle, 92 uint64_t new_mask) 93 { 94 struct smu_context *smu = handle; 95 96 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 97 return -EOPNOTSUPP; 98 99 return smu_set_pp_feature_mask(smu, new_mask); 100 } 101 102 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 103 { 104 if (!smu->ppt_funcs->set_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_set_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_residency) 113 return -EINVAL; 114 115 return smu_get_gfx_off_residency(smu, value); 116 } 117 118 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_entrycount) 121 return -EINVAL; 122 123 return smu_get_gfx_off_entrycount(smu, value); 124 } 125 126 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 127 { 128 if (!smu->ppt_funcs->get_gfx_off_status) 129 return -EINVAL; 130 131 *value = smu_get_gfx_off_status(smu); 132 133 return 0; 134 } 135 136 int smu_set_soft_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t min, 139 uint32_t max) 140 { 141 int ret = 0; 142 143 if (smu->ppt_funcs->set_soft_freq_limited_range) 144 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 145 clk_type, 146 min, 147 max, 148 false); 149 150 return ret; 151 } 152 153 int smu_get_dpm_freq_range(struct smu_context *smu, 154 enum smu_clk_type clk_type, 155 uint32_t *min, 156 uint32_t *max) 157 { 158 int ret = -ENOTSUPP; 159 160 if (!min && !max) 161 return -EINVAL; 162 163 if (smu->ppt_funcs->get_dpm_ultimate_freq) 164 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 165 clk_type, 166 min, 167 max); 168 169 return ret; 170 } 171 172 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 173 { 174 int ret = 0; 175 struct amdgpu_device *adev = smu->adev; 176 177 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 178 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 179 if (ret) 180 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 181 } 182 return ret; 183 } 184 185 static u32 smu_get_mclk(void *handle, bool low) 186 { 187 struct smu_context *smu = handle; 188 uint32_t clk_freq; 189 int ret = 0; 190 191 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 192 low ? &clk_freq : NULL, 193 !low ? &clk_freq : NULL); 194 if (ret) 195 return 0; 196 return clk_freq * 100; 197 } 198 199 static u32 smu_get_sclk(void *handle, bool low) 200 { 201 struct smu_context *smu = handle; 202 uint32_t clk_freq; 203 int ret = 0; 204 205 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 206 low ? &clk_freq : NULL, 207 !low ? &clk_freq : NULL); 208 if (ret) 209 return 0; 210 return clk_freq * 100; 211 } 212 213 static int smu_set_gfx_imu_enable(struct smu_context *smu) 214 { 215 struct amdgpu_device *adev = smu->adev; 216 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 return 0; 219 220 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 221 return 0; 222 223 return smu_set_gfx_power_up_by_imu(smu); 224 } 225 226 static bool is_vcn_enabled(struct amdgpu_device *adev) 227 { 228 int i; 229 230 for (i = 0; i < adev->num_ip_blocks; i++) { 231 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 233 !adev->ip_blocks[i].status.valid) 234 return false; 235 } 236 237 return true; 238 } 239 240 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 241 bool enable, 242 int inst) 243 { 244 struct smu_power_context *smu_power = &smu->smu_power; 245 struct smu_power_gate *power_gate = &smu_power->power_gate; 246 int ret = 0; 247 248 /* 249 * don't poweron vcn/jpeg when they are skipped. 250 */ 251 if (!is_vcn_enabled(smu->adev)) 252 return 0; 253 254 if (!smu->ppt_funcs->dpm_set_vcn_enable) 255 return 0; 256 257 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 258 return 0; 259 260 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 261 if (!ret) 262 atomic_set(&power_gate->vcn_gated[inst], !enable); 263 264 return ret; 265 } 266 267 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 268 bool enable) 269 { 270 struct smu_power_context *smu_power = &smu->smu_power; 271 struct smu_power_gate *power_gate = &smu_power->power_gate; 272 int ret = 0; 273 274 if (!is_vcn_enabled(smu->adev)) 275 return 0; 276 277 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 278 return 0; 279 280 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 281 return 0; 282 283 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 284 if (!ret) 285 atomic_set(&power_gate->jpeg_gated, !enable); 286 287 return ret; 288 } 289 290 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 291 bool enable) 292 { 293 struct smu_power_context *smu_power = &smu->smu_power; 294 struct smu_power_gate *power_gate = &smu_power->power_gate; 295 int ret = 0; 296 297 if (!smu->ppt_funcs->dpm_set_vpe_enable) 298 return 0; 299 300 if (atomic_read(&power_gate->vpe_gated) ^ enable) 301 return 0; 302 303 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 304 if (!ret) 305 atomic_set(&power_gate->vpe_gated, !enable); 306 307 return ret; 308 } 309 310 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 311 bool enable) 312 { 313 struct smu_power_context *smu_power = &smu->smu_power; 314 struct smu_power_gate *power_gate = &smu_power->power_gate; 315 int ret = 0; 316 317 if (!smu->adev->enable_umsch_mm) 318 return 0; 319 320 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 321 return 0; 322 323 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 324 return 0; 325 326 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 327 if (!ret) 328 atomic_set(&power_gate->umsch_mm_gated, !enable); 329 330 return ret; 331 } 332 333 static int smu_set_mall_enable(struct smu_context *smu) 334 { 335 int ret = 0; 336 337 if (!smu->ppt_funcs->set_mall_enable) 338 return 0; 339 340 ret = smu->ppt_funcs->set_mall_enable(smu); 341 342 return ret; 343 } 344 345 /** 346 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 347 * 348 * @handle: smu_context pointer 349 * @block_type: the IP block to power gate/ungate 350 * @gate: to power gate if true, ungate otherwise 351 * @inst: the instance of the IP block to power gate/ungate 352 * 353 * This API uses no smu->mutex lock protection due to: 354 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 355 * This is guarded to be race condition free by the caller. 356 * 2. Or get called on user setting request of power_dpm_force_performance_level. 357 * Under this case, the smu->mutex lock protection is already enforced on 358 * the parent API smu_force_performance_level of the call path. 359 */ 360 static int smu_dpm_set_power_gate(void *handle, 361 uint32_t block_type, 362 bool gate, 363 int inst) 364 { 365 struct smu_context *smu = handle; 366 int ret = 0; 367 368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 369 dev_WARN(smu->adev->dev, 370 "SMU uninitialized but power %s requested for %u!\n", 371 gate ? "gate" : "ungate", block_type); 372 return -EOPNOTSUPP; 373 } 374 375 switch (block_type) { 376 /* 377 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 378 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 379 */ 380 case AMD_IP_BLOCK_TYPE_UVD: 381 case AMD_IP_BLOCK_TYPE_VCN: 382 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 385 gate ? "gate" : "ungate", inst); 386 break; 387 case AMD_IP_BLOCK_TYPE_GFX: 388 ret = smu_gfx_off_control(smu, gate); 389 if (ret) 390 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 391 gate ? "enable" : "disable"); 392 break; 393 case AMD_IP_BLOCK_TYPE_SDMA: 394 ret = smu_powergate_sdma(smu, gate); 395 if (ret) 396 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 397 gate ? "gate" : "ungate"); 398 break; 399 case AMD_IP_BLOCK_TYPE_JPEG: 400 ret = smu_dpm_set_jpeg_enable(smu, !gate); 401 if (ret) 402 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 403 gate ? "gate" : "ungate"); 404 break; 405 case AMD_IP_BLOCK_TYPE_VPE: 406 ret = smu_dpm_set_vpe_enable(smu, !gate); 407 if (ret) 408 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 409 gate ? "gate" : "ungate"); 410 break; 411 default: 412 dev_err(smu->adev->dev, "Unsupported block type!\n"); 413 return -EINVAL; 414 } 415 416 return ret; 417 } 418 419 /** 420 * smu_set_user_clk_dependencies - set user profile clock dependencies 421 * 422 * @smu: smu_context pointer 423 * @clk: enum smu_clk_type type 424 * 425 * Enable/Disable the clock dependency for the @clk type. 426 */ 427 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 428 { 429 if (smu->adev->in_suspend) 430 return; 431 432 if (clk == SMU_MCLK) { 433 smu->user_dpm_profile.clk_dependency = 0; 434 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 435 } else if (clk == SMU_FCLK) { 436 /* MCLK takes precedence over FCLK */ 437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 438 return; 439 440 smu->user_dpm_profile.clk_dependency = 0; 441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 442 } else if (clk == SMU_SOCCLK) { 443 /* MCLK takes precedence over SOCCLK */ 444 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 445 return; 446 447 smu->user_dpm_profile.clk_dependency = 0; 448 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 449 } else 450 /* Add clk dependencies here, if any */ 451 return; 452 } 453 454 /** 455 * smu_restore_dpm_user_profile - reinstate user dpm profile 456 * 457 * @smu: smu_context pointer 458 * 459 * Restore the saved user power configurations include power limit, 460 * clock frequencies, fan control mode and fan speed. 461 */ 462 static void smu_restore_dpm_user_profile(struct smu_context *smu) 463 { 464 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 465 int ret = 0; 466 467 if (!smu->adev->in_suspend) 468 return; 469 470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 471 return; 472 473 /* Enable restore flag */ 474 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 475 476 /* set the user dpm power limit */ 477 if (smu->user_dpm_profile.power_limit) { 478 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 479 if (ret) 480 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 481 } 482 483 /* set the user dpm clock configurations */ 484 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 485 enum smu_clk_type clk_type; 486 487 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 488 /* 489 * Iterate over smu clk type and force the saved user clk 490 * configs, skip if clock dependency is enabled 491 */ 492 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 493 smu->user_dpm_profile.clk_mask[clk_type]) { 494 ret = smu_force_smuclk_levels(smu, clk_type, 495 smu->user_dpm_profile.clk_mask[clk_type]); 496 if (ret) 497 dev_err(smu->adev->dev, 498 "Failed to set clock type = %d\n", clk_type); 499 } 500 } 501 } 502 503 /* set the user dpm fan configurations */ 504 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 505 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 506 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 507 if (ret != -EOPNOTSUPP) { 508 smu->user_dpm_profile.fan_speed_pwm = 0; 509 smu->user_dpm_profile.fan_speed_rpm = 0; 510 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 511 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 512 } 513 514 if (smu->user_dpm_profile.fan_speed_pwm) { 515 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 516 if (ret != -EOPNOTSUPP) 517 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 518 } 519 520 if (smu->user_dpm_profile.fan_speed_rpm) { 521 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 522 if (ret != -EOPNOTSUPP) 523 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 524 } 525 } 526 527 /* Restore user customized OD settings */ 528 if (smu->user_dpm_profile.user_od) { 529 if (smu->ppt_funcs->restore_user_od_settings) { 530 ret = smu->ppt_funcs->restore_user_od_settings(smu); 531 if (ret) 532 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 533 } 534 } 535 536 /* Disable restore flag */ 537 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 538 } 539 540 static int smu_get_power_num_states(void *handle, 541 struct pp_states_info *state_info) 542 { 543 if (!state_info) 544 return -EINVAL; 545 546 /* not support power state */ 547 memset(state_info, 0, sizeof(struct pp_states_info)); 548 state_info->nums = 1; 549 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 550 551 return 0; 552 } 553 554 bool is_support_sw_smu(struct amdgpu_device *adev) 555 { 556 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 557 if (adev->asic_type == CHIP_VEGA20) 558 return false; 559 560 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 561 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 562 return true; 563 564 return false; 565 } 566 567 bool is_support_cclk_dpm(struct amdgpu_device *adev) 568 { 569 struct smu_context *smu = adev->powerplay.pp_handle; 570 571 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 572 return false; 573 574 return true; 575 } 576 577 578 static int smu_sys_get_pp_table(void *handle, 579 char **table) 580 { 581 struct smu_context *smu = handle; 582 struct smu_table_context *smu_table = &smu->smu_table; 583 584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 585 return -EOPNOTSUPP; 586 587 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 588 return -EINVAL; 589 590 if (smu_table->hardcode_pptable) 591 *table = smu_table->hardcode_pptable; 592 else 593 *table = smu_table->power_play_table; 594 595 return smu_table->power_play_table_size; 596 } 597 598 static int smu_sys_set_pp_table(void *handle, 599 const char *buf, 600 size_t size) 601 { 602 struct smu_context *smu = handle; 603 struct smu_table_context *smu_table = &smu->smu_table; 604 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 605 int ret = 0; 606 607 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 608 return -EOPNOTSUPP; 609 610 if (header->usStructureSize != size) { 611 dev_err(smu->adev->dev, "pp table size not matched !\n"); 612 return -EIO; 613 } 614 615 if (!smu_table->hardcode_pptable) { 616 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 617 if (!smu_table->hardcode_pptable) 618 return -ENOMEM; 619 } 620 621 memcpy(smu_table->hardcode_pptable, buf, size); 622 smu_table->power_play_table = smu_table->hardcode_pptable; 623 smu_table->power_play_table_size = size; 624 625 /* 626 * Special hw_fini action(for Navi1x, the DPMs disablement will be 627 * skipped) may be needed for custom pptable uploading. 628 */ 629 smu->uploading_custom_pp_table = true; 630 631 ret = smu_reset(smu); 632 if (ret) 633 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 634 635 smu->uploading_custom_pp_table = false; 636 637 return ret; 638 } 639 640 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 641 { 642 struct smu_feature *feature = &smu->smu_feature; 643 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 644 int ret = 0; 645 646 /* 647 * With SCPM enabled, the allowed featuremasks setting(via 648 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 649 * That means there is no way to let PMFW knows the settings below. 650 * Thus, we just assume all the features are allowed under 651 * such scenario. 652 */ 653 if (smu->adev->scpm_enabled) { 654 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 655 return 0; 656 } 657 658 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 659 660 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 661 SMU_FEATURE_MAX/32); 662 if (ret) 663 return ret; 664 665 bitmap_or(feature->allowed, feature->allowed, 666 (unsigned long *)allowed_feature_mask, 667 feature->feature_num); 668 669 return ret; 670 } 671 672 static int smu_set_funcs(struct amdgpu_device *adev) 673 { 674 struct smu_context *smu = adev->powerplay.pp_handle; 675 676 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 677 smu->od_enabled = true; 678 679 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 680 case IP_VERSION(11, 0, 0): 681 case IP_VERSION(11, 0, 5): 682 case IP_VERSION(11, 0, 9): 683 navi10_set_ppt_funcs(smu); 684 break; 685 case IP_VERSION(11, 0, 7): 686 case IP_VERSION(11, 0, 11): 687 case IP_VERSION(11, 0, 12): 688 case IP_VERSION(11, 0, 13): 689 sienna_cichlid_set_ppt_funcs(smu); 690 break; 691 case IP_VERSION(12, 0, 0): 692 case IP_VERSION(12, 0, 1): 693 renoir_set_ppt_funcs(smu); 694 break; 695 case IP_VERSION(11, 5, 0): 696 vangogh_set_ppt_funcs(smu); 697 break; 698 case IP_VERSION(13, 0, 1): 699 case IP_VERSION(13, 0, 3): 700 case IP_VERSION(13, 0, 8): 701 yellow_carp_set_ppt_funcs(smu); 702 break; 703 case IP_VERSION(13, 0, 4): 704 case IP_VERSION(13, 0, 11): 705 smu_v13_0_4_set_ppt_funcs(smu); 706 break; 707 case IP_VERSION(13, 0, 5): 708 smu_v13_0_5_set_ppt_funcs(smu); 709 break; 710 case IP_VERSION(11, 0, 8): 711 cyan_skillfish_set_ppt_funcs(smu); 712 break; 713 case IP_VERSION(11, 0, 2): 714 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 715 arcturus_set_ppt_funcs(smu); 716 /* OD is not supported on Arcturus */ 717 smu->od_enabled = false; 718 break; 719 case IP_VERSION(13, 0, 2): 720 aldebaran_set_ppt_funcs(smu); 721 /* Enable pp_od_clk_voltage node */ 722 smu->od_enabled = true; 723 break; 724 case IP_VERSION(13, 0, 0): 725 case IP_VERSION(13, 0, 10): 726 smu_v13_0_0_set_ppt_funcs(smu); 727 break; 728 case IP_VERSION(13, 0, 6): 729 case IP_VERSION(13, 0, 14): 730 smu_v13_0_6_set_ppt_funcs(smu); 731 /* Enable pp_od_clk_voltage node */ 732 smu->od_enabled = true; 733 break; 734 case IP_VERSION(13, 0, 7): 735 smu_v13_0_7_set_ppt_funcs(smu); 736 break; 737 case IP_VERSION(14, 0, 0): 738 case IP_VERSION(14, 0, 1): 739 case IP_VERSION(14, 0, 4): 740 smu_v14_0_0_set_ppt_funcs(smu); 741 break; 742 case IP_VERSION(14, 0, 2): 743 case IP_VERSION(14, 0, 3): 744 smu_v14_0_2_set_ppt_funcs(smu); 745 break; 746 default: 747 return -EINVAL; 748 } 749 750 return 0; 751 } 752 753 static int smu_early_init(struct amdgpu_ip_block *ip_block) 754 { 755 struct amdgpu_device *adev = ip_block->adev; 756 struct smu_context *smu; 757 int r; 758 759 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 760 if (!smu) 761 return -ENOMEM; 762 763 smu->adev = adev; 764 smu->pm_enabled = !!amdgpu_dpm; 765 smu->is_apu = false; 766 smu->smu_baco.state = SMU_BACO_STATE_NONE; 767 smu->smu_baco.platform_support = false; 768 smu->smu_baco.maco_support = false; 769 smu->user_dpm_profile.fan_mode = -1; 770 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 771 772 mutex_init(&smu->message_lock); 773 774 adev->powerplay.pp_handle = smu; 775 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 776 777 r = smu_set_funcs(adev); 778 if (r) 779 return r; 780 return smu_init_microcode(smu); 781 } 782 783 static int smu_set_default_dpm_table(struct smu_context *smu) 784 { 785 struct amdgpu_device *adev = smu->adev; 786 struct smu_power_context *smu_power = &smu->smu_power; 787 struct smu_power_gate *power_gate = &smu_power->power_gate; 788 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 789 int ret = 0; 790 791 if (!smu->ppt_funcs->set_default_dpm_table) 792 return 0; 793 794 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 795 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 796 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 797 } 798 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 799 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 800 801 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 802 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 803 ret = smu_dpm_set_vcn_enable(smu, true, i); 804 if (ret) 805 return ret; 806 } 807 } 808 809 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 810 ret = smu_dpm_set_jpeg_enable(smu, true); 811 if (ret) 812 goto err_out; 813 } 814 815 ret = smu->ppt_funcs->set_default_dpm_table(smu); 816 if (ret) 817 dev_err(smu->adev->dev, 818 "Failed to setup default dpm clock tables!\n"); 819 820 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 821 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 822 err_out: 823 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 824 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 825 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 826 } 827 828 return ret; 829 } 830 831 static int smu_apply_default_config_table_settings(struct smu_context *smu) 832 { 833 struct amdgpu_device *adev = smu->adev; 834 int ret = 0; 835 836 ret = smu_get_default_config_table_settings(smu, 837 &adev->pm.config_table); 838 if (ret) 839 return ret; 840 841 return smu_set_config_table(smu, &adev->pm.config_table); 842 } 843 844 static int smu_late_init(struct amdgpu_ip_block *ip_block) 845 { 846 struct amdgpu_device *adev = ip_block->adev; 847 struct smu_context *smu = adev->powerplay.pp_handle; 848 int ret = 0; 849 850 smu_set_fine_grain_gfx_freq_parameters(smu); 851 852 if (!smu->pm_enabled) 853 return 0; 854 855 ret = smu_post_init(smu); 856 if (ret) { 857 dev_err(adev->dev, "Failed to post smu init!\n"); 858 return ret; 859 } 860 861 /* 862 * Explicitly notify PMFW the power mode the system in. Since 863 * the PMFW may boot the ASIC with a different mode. 864 * For those supporting ACDC switch via gpio, PMFW will 865 * handle the switch automatically. Driver involvement 866 * is unnecessary. 867 */ 868 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 869 smu_set_ac_dc(smu); 870 871 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 872 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 873 return 0; 874 875 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 876 ret = smu_set_default_od_settings(smu); 877 if (ret) { 878 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 879 return ret; 880 } 881 } 882 883 ret = smu_populate_umd_state_clk(smu); 884 if (ret) { 885 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 886 return ret; 887 } 888 889 ret = smu_get_asic_power_limits(smu, 890 &smu->current_power_limit, 891 &smu->default_power_limit, 892 &smu->max_power_limit, 893 &smu->min_power_limit); 894 if (ret) { 895 dev_err(adev->dev, "Failed to get asic power limits!\n"); 896 return ret; 897 } 898 899 if (!amdgpu_sriov_vf(adev)) 900 smu_get_unique_id(smu); 901 902 smu_get_fan_parameters(smu); 903 904 smu_handle_task(smu, 905 smu->smu_dpm.dpm_level, 906 AMD_PP_TASK_COMPLETE_INIT); 907 908 ret = smu_apply_default_config_table_settings(smu); 909 if (ret && (ret != -EOPNOTSUPP)) { 910 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 911 return ret; 912 } 913 914 smu_restore_dpm_user_profile(smu); 915 916 return 0; 917 } 918 919 static int smu_init_fb_allocations(struct smu_context *smu) 920 { 921 struct amdgpu_device *adev = smu->adev; 922 struct smu_table_context *smu_table = &smu->smu_table; 923 struct smu_table *tables = smu_table->tables; 924 struct smu_table *driver_table = &(smu_table->driver_table); 925 uint32_t max_table_size = 0; 926 int ret, i; 927 928 /* VRAM allocation for tool table */ 929 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 930 ret = amdgpu_bo_create_kernel(adev, 931 tables[SMU_TABLE_PMSTATUSLOG].size, 932 tables[SMU_TABLE_PMSTATUSLOG].align, 933 tables[SMU_TABLE_PMSTATUSLOG].domain, 934 &tables[SMU_TABLE_PMSTATUSLOG].bo, 935 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 936 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 937 if (ret) { 938 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 939 return ret; 940 } 941 } 942 943 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 944 /* VRAM allocation for driver table */ 945 for (i = 0; i < SMU_TABLE_COUNT; i++) { 946 if (tables[i].size == 0) 947 continue; 948 949 /* If one of the tables has VRAM domain restriction, keep it in 950 * VRAM 951 */ 952 if ((tables[i].domain & 953 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 954 AMDGPU_GEM_DOMAIN_VRAM) 955 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 956 957 if (i == SMU_TABLE_PMSTATUSLOG) 958 continue; 959 960 if (max_table_size < tables[i].size) 961 max_table_size = tables[i].size; 962 } 963 964 driver_table->size = max_table_size; 965 driver_table->align = PAGE_SIZE; 966 967 ret = amdgpu_bo_create_kernel(adev, 968 driver_table->size, 969 driver_table->align, 970 driver_table->domain, 971 &driver_table->bo, 972 &driver_table->mc_address, 973 &driver_table->cpu_addr); 974 if (ret) { 975 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 976 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 977 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 978 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 979 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 980 } 981 982 return ret; 983 } 984 985 static int smu_fini_fb_allocations(struct smu_context *smu) 986 { 987 struct smu_table_context *smu_table = &smu->smu_table; 988 struct smu_table *tables = smu_table->tables; 989 struct smu_table *driver_table = &(smu_table->driver_table); 990 991 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 992 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 993 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 994 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 995 996 amdgpu_bo_free_kernel(&driver_table->bo, 997 &driver_table->mc_address, 998 &driver_table->cpu_addr); 999 1000 return 0; 1001 } 1002 1003 /** 1004 * smu_alloc_memory_pool - allocate memory pool in the system memory 1005 * 1006 * @smu: amdgpu_device pointer 1007 * 1008 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1009 * and DramLogSetDramAddr can notify it changed. 1010 * 1011 * Returns 0 on success, error on failure. 1012 */ 1013 static int smu_alloc_memory_pool(struct smu_context *smu) 1014 { 1015 struct amdgpu_device *adev = smu->adev; 1016 struct smu_table_context *smu_table = &smu->smu_table; 1017 struct smu_table *memory_pool = &smu_table->memory_pool; 1018 uint64_t pool_size = smu->pool_size; 1019 int ret = 0; 1020 1021 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1022 return ret; 1023 1024 memory_pool->size = pool_size; 1025 memory_pool->align = PAGE_SIZE; 1026 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1027 1028 switch (pool_size) { 1029 case SMU_MEMORY_POOL_SIZE_256_MB: 1030 case SMU_MEMORY_POOL_SIZE_512_MB: 1031 case SMU_MEMORY_POOL_SIZE_1_GB: 1032 case SMU_MEMORY_POOL_SIZE_2_GB: 1033 ret = amdgpu_bo_create_kernel(adev, 1034 memory_pool->size, 1035 memory_pool->align, 1036 memory_pool->domain, 1037 &memory_pool->bo, 1038 &memory_pool->mc_address, 1039 &memory_pool->cpu_addr); 1040 if (ret) 1041 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1042 break; 1043 default: 1044 break; 1045 } 1046 1047 return ret; 1048 } 1049 1050 static int smu_free_memory_pool(struct smu_context *smu) 1051 { 1052 struct smu_table_context *smu_table = &smu->smu_table; 1053 struct smu_table *memory_pool = &smu_table->memory_pool; 1054 1055 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1056 return 0; 1057 1058 amdgpu_bo_free_kernel(&memory_pool->bo, 1059 &memory_pool->mc_address, 1060 &memory_pool->cpu_addr); 1061 1062 memset(memory_pool, 0, sizeof(struct smu_table)); 1063 1064 return 0; 1065 } 1066 1067 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1068 { 1069 struct smu_table_context *smu_table = &smu->smu_table; 1070 struct smu_table *dummy_read_1_table = 1071 &smu_table->dummy_read_1_table; 1072 struct amdgpu_device *adev = smu->adev; 1073 int ret = 0; 1074 1075 if (!dummy_read_1_table->size) 1076 return 0; 1077 1078 ret = amdgpu_bo_create_kernel(adev, 1079 dummy_read_1_table->size, 1080 dummy_read_1_table->align, 1081 dummy_read_1_table->domain, 1082 &dummy_read_1_table->bo, 1083 &dummy_read_1_table->mc_address, 1084 &dummy_read_1_table->cpu_addr); 1085 if (ret) 1086 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1087 1088 return ret; 1089 } 1090 1091 static void smu_free_dummy_read_table(struct smu_context *smu) 1092 { 1093 struct smu_table_context *smu_table = &smu->smu_table; 1094 struct smu_table *dummy_read_1_table = 1095 &smu_table->dummy_read_1_table; 1096 1097 1098 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1099 &dummy_read_1_table->mc_address, 1100 &dummy_read_1_table->cpu_addr); 1101 1102 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1103 } 1104 1105 static int smu_smc_table_sw_init(struct smu_context *smu) 1106 { 1107 int ret; 1108 1109 /** 1110 * Create smu_table structure, and init smc tables such as 1111 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1112 */ 1113 ret = smu_init_smc_tables(smu); 1114 if (ret) { 1115 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1116 return ret; 1117 } 1118 1119 /** 1120 * Create smu_power_context structure, and allocate smu_dpm_context and 1121 * context size to fill the smu_power_context data. 1122 */ 1123 ret = smu_init_power(smu); 1124 if (ret) { 1125 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1126 return ret; 1127 } 1128 1129 /* 1130 * allocate vram bos to store smc table contents. 1131 */ 1132 ret = smu_init_fb_allocations(smu); 1133 if (ret) 1134 return ret; 1135 1136 ret = smu_alloc_memory_pool(smu); 1137 if (ret) 1138 return ret; 1139 1140 ret = smu_alloc_dummy_read_table(smu); 1141 if (ret) 1142 return ret; 1143 1144 ret = smu_i2c_init(smu); 1145 if (ret) 1146 return ret; 1147 1148 return 0; 1149 } 1150 1151 static int smu_smc_table_sw_fini(struct smu_context *smu) 1152 { 1153 int ret; 1154 1155 smu_i2c_fini(smu); 1156 1157 smu_free_dummy_read_table(smu); 1158 1159 ret = smu_free_memory_pool(smu); 1160 if (ret) 1161 return ret; 1162 1163 ret = smu_fini_fb_allocations(smu); 1164 if (ret) 1165 return ret; 1166 1167 ret = smu_fini_power(smu); 1168 if (ret) { 1169 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1170 return ret; 1171 } 1172 1173 ret = smu_fini_smc_tables(smu); 1174 if (ret) { 1175 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1176 return ret; 1177 } 1178 1179 return 0; 1180 } 1181 1182 static void smu_throttling_logging_work_fn(struct work_struct *work) 1183 { 1184 struct smu_context *smu = container_of(work, struct smu_context, 1185 throttling_logging_work); 1186 1187 smu_log_thermal_throttling(smu); 1188 } 1189 1190 static void smu_interrupt_work_fn(struct work_struct *work) 1191 { 1192 struct smu_context *smu = container_of(work, struct smu_context, 1193 interrupt_work); 1194 1195 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1196 smu->ppt_funcs->interrupt_work(smu); 1197 } 1198 1199 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1200 { 1201 struct smu_context *smu = 1202 container_of(work, struct smu_context, swctf_delayed_work.work); 1203 struct smu_temperature_range *range = 1204 &smu->thermal_range; 1205 struct amdgpu_device *adev = smu->adev; 1206 uint32_t hotspot_tmp, size; 1207 1208 /* 1209 * If the hotspot temperature is confirmed as below SW CTF setting point 1210 * after the delay enforced, nothing will be done. 1211 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1212 */ 1213 if (range->software_shutdown_temp && 1214 smu->ppt_funcs->read_sensor && 1215 !smu->ppt_funcs->read_sensor(smu, 1216 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1217 &hotspot_tmp, 1218 &size) && 1219 hotspot_tmp / 1000 < range->software_shutdown_temp) 1220 return; 1221 1222 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1223 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1224 orderly_poweroff(true); 1225 } 1226 1227 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1228 { 1229 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1230 struct smu_dpm_policy_ctxt *policy_ctxt; 1231 struct smu_dpm_policy *policy; 1232 1233 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1234 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1235 if (policy) 1236 policy->current_level = XGMI_PLPD_DEFAULT; 1237 return; 1238 } 1239 1240 /* PMFW put PLPD into default policy after enabling the feature */ 1241 if (smu_feature_is_enabled(smu, 1242 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1243 if (policy) 1244 policy->current_level = XGMI_PLPD_DEFAULT; 1245 } else { 1246 policy_ctxt = dpm_ctxt->dpm_policies; 1247 if (policy_ctxt) 1248 policy_ctxt->policy_mask &= 1249 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1250 } 1251 } 1252 1253 static bool smu_is_workload_profile_available(struct smu_context *smu, 1254 u32 profile) 1255 { 1256 if (profile >= PP_SMC_POWER_PROFILE_COUNT) 1257 return false; 1258 return smu->workload_map && smu->workload_map[profile].valid_mapping; 1259 } 1260 1261 static void smu_init_power_profile(struct smu_context *smu) 1262 { 1263 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) { 1264 if (smu->is_apu || 1265 !smu_is_workload_profile_available( 1266 smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) 1267 smu->power_profile_mode = 1268 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1269 else 1270 smu->power_profile_mode = 1271 PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1272 } 1273 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1274 } 1275 1276 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1277 { 1278 struct amdgpu_device *adev = ip_block->adev; 1279 struct smu_context *smu = adev->powerplay.pp_handle; 1280 int i, ret; 1281 1282 smu->pool_size = adev->pm.smu_prv_buffer_size; 1283 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1284 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1285 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1286 1287 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1288 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1289 atomic64_set(&smu->throttle_int_counter, 0); 1290 smu->watermarks_bitmap = 0; 1291 1292 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1293 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1294 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1295 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1296 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1297 1298 smu_init_power_profile(smu); 1299 smu->display_config = &adev->pm.pm_display_cfg; 1300 1301 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1302 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1303 1304 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1305 smu_swctf_delayed_work_handler); 1306 1307 ret = smu_smc_table_sw_init(smu); 1308 if (ret) { 1309 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1310 return ret; 1311 } 1312 1313 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1314 ret = smu_get_vbios_bootup_values(smu); 1315 if (ret) { 1316 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1317 return ret; 1318 } 1319 1320 ret = smu_init_pptable_microcode(smu); 1321 if (ret) { 1322 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1323 return ret; 1324 } 1325 1326 ret = smu_register_irq_handler(smu); 1327 if (ret) { 1328 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1329 return ret; 1330 } 1331 1332 /* If there is no way to query fan control mode, fan control is not supported */ 1333 if (!smu->ppt_funcs->get_fan_control_mode) 1334 smu->adev->pm.no_fan = true; 1335 1336 return 0; 1337 } 1338 1339 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1340 { 1341 struct amdgpu_device *adev = ip_block->adev; 1342 struct smu_context *smu = adev->powerplay.pp_handle; 1343 int ret; 1344 1345 ret = smu_smc_table_sw_fini(smu); 1346 if (ret) { 1347 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1348 return ret; 1349 } 1350 1351 if (smu->custom_profile_params) { 1352 kfree(smu->custom_profile_params); 1353 smu->custom_profile_params = NULL; 1354 } 1355 1356 smu_fini_microcode(smu); 1357 1358 return 0; 1359 } 1360 1361 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1362 { 1363 struct amdgpu_device *adev = smu->adev; 1364 struct smu_temperature_range *range = 1365 &smu->thermal_range; 1366 int ret = 0; 1367 1368 if (!smu->ppt_funcs->get_thermal_temperature_range) 1369 return 0; 1370 1371 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1372 if (ret) 1373 return ret; 1374 1375 adev->pm.dpm.thermal.min_temp = range->min; 1376 adev->pm.dpm.thermal.max_temp = range->max; 1377 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1378 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1379 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1380 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1381 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1382 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1383 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1384 1385 return ret; 1386 } 1387 1388 /** 1389 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1390 * 1391 * @smu: smu_context pointer 1392 * 1393 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1394 * Returns 0 on success, error on failure. 1395 */ 1396 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1397 { 1398 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1399 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1400 struct amdgpu_device *adev = smu->adev; 1401 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1402 uint64_t start, end; 1403 int ret, i, j; 1404 1405 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1406 if (ret) { 1407 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1408 return ret; 1409 } 1410 1411 /* 1412 * The exclusion ranges array we got might be filled with holes and duplicate 1413 * entries. For example: 1414 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1415 * We need to do some sortups to eliminate those holes and duplicate entries. 1416 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1417 */ 1418 for (i = 0; i < num_of_wbrf_ranges; i++) { 1419 start = wifi_bands[i].start; 1420 end = wifi_bands[i].end; 1421 1422 /* get the last valid entry to fill the intermediate hole */ 1423 if (!start && !end) { 1424 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1425 if (wifi_bands[j].start && wifi_bands[j].end) 1426 break; 1427 1428 /* no valid entry left */ 1429 if (j <= i) 1430 break; 1431 1432 start = wifi_bands[i].start = wifi_bands[j].start; 1433 end = wifi_bands[i].end = wifi_bands[j].end; 1434 wifi_bands[j].start = 0; 1435 wifi_bands[j].end = 0; 1436 num_of_wbrf_ranges = j; 1437 } 1438 1439 /* eliminate duplicate entries */ 1440 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1441 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1442 wifi_bands[j].start = 0; 1443 wifi_bands[j].end = 0; 1444 } 1445 } 1446 } 1447 1448 /* Send the sorted wifi_bands to PMFW */ 1449 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1450 /* Try to set the wifi_bands again */ 1451 if (unlikely(ret == -EBUSY)) { 1452 mdelay(5); 1453 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1454 } 1455 1456 return ret; 1457 } 1458 1459 /** 1460 * smu_wbrf_event_handler - handle notify events 1461 * 1462 * @nb: notifier block 1463 * @action: event type 1464 * @_arg: event data 1465 * 1466 * Calls relevant amdgpu function in response to wbrf event 1467 * notification from kernel. 1468 */ 1469 static int smu_wbrf_event_handler(struct notifier_block *nb, 1470 unsigned long action, void *_arg) 1471 { 1472 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1473 1474 switch (action) { 1475 case WBRF_CHANGED: 1476 schedule_delayed_work(&smu->wbrf_delayed_work, 1477 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1478 break; 1479 default: 1480 return NOTIFY_DONE; 1481 } 1482 1483 return NOTIFY_OK; 1484 } 1485 1486 /** 1487 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1488 * 1489 * @work: struct work_struct pointer 1490 * 1491 * Flood is over and driver will consume the latest exclusion ranges. 1492 */ 1493 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1494 { 1495 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1496 1497 smu_wbrf_handle_exclusion_ranges(smu); 1498 } 1499 1500 /** 1501 * smu_wbrf_support_check - check wbrf support 1502 * 1503 * @smu: smu_context pointer 1504 * 1505 * Verifies the ACPI interface whether wbrf is supported. 1506 */ 1507 static void smu_wbrf_support_check(struct smu_context *smu) 1508 { 1509 struct amdgpu_device *adev = smu->adev; 1510 1511 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1512 acpi_amd_wbrf_supported_consumer(adev->dev); 1513 1514 if (smu->wbrf_supported) 1515 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1516 } 1517 1518 /** 1519 * smu_wbrf_init - init driver wbrf support 1520 * 1521 * @smu: smu_context pointer 1522 * 1523 * Verifies the AMD ACPI interfaces and registers with the wbrf 1524 * notifier chain if wbrf feature is supported. 1525 * Returns 0 on success, error on failure. 1526 */ 1527 static int smu_wbrf_init(struct smu_context *smu) 1528 { 1529 int ret; 1530 1531 if (!smu->wbrf_supported) 1532 return 0; 1533 1534 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1535 1536 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1537 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1538 if (ret) 1539 return ret; 1540 1541 /* 1542 * Some wifiband exclusion ranges may be already there 1543 * before our driver loaded. To make sure our driver 1544 * is awared of those exclusion ranges. 1545 */ 1546 schedule_delayed_work(&smu->wbrf_delayed_work, 1547 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1548 1549 return 0; 1550 } 1551 1552 /** 1553 * smu_wbrf_fini - tear down driver wbrf support 1554 * 1555 * @smu: smu_context pointer 1556 * 1557 * Unregisters with the wbrf notifier chain. 1558 */ 1559 static void smu_wbrf_fini(struct smu_context *smu) 1560 { 1561 if (!smu->wbrf_supported) 1562 return; 1563 1564 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1565 1566 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1567 } 1568 1569 static int smu_smc_hw_setup(struct smu_context *smu) 1570 { 1571 struct smu_feature *feature = &smu->smu_feature; 1572 struct amdgpu_device *adev = smu->adev; 1573 uint8_t pcie_gen = 0, pcie_width = 0; 1574 uint64_t features_supported; 1575 int ret = 0; 1576 1577 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1578 case IP_VERSION(11, 0, 7): 1579 case IP_VERSION(11, 0, 11): 1580 case IP_VERSION(11, 5, 0): 1581 case IP_VERSION(11, 0, 12): 1582 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1583 dev_info(adev->dev, "dpm has been enabled\n"); 1584 ret = smu_system_features_control(smu, true); 1585 if (ret) 1586 dev_err(adev->dev, "Failed system features control!\n"); 1587 return ret; 1588 } 1589 break; 1590 default: 1591 break; 1592 } 1593 1594 ret = smu_init_display_count(smu, 0); 1595 if (ret) { 1596 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1597 return ret; 1598 } 1599 1600 ret = smu_set_driver_table_location(smu); 1601 if (ret) { 1602 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1603 return ret; 1604 } 1605 1606 /* 1607 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1608 */ 1609 ret = smu_set_tool_table_location(smu); 1610 if (ret) { 1611 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1612 return ret; 1613 } 1614 1615 /* 1616 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1617 * pool location. 1618 */ 1619 ret = smu_notify_memory_pool_location(smu); 1620 if (ret) { 1621 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1622 return ret; 1623 } 1624 1625 /* 1626 * It is assumed the pptable used before runpm is same as 1627 * the one used afterwards. Thus, we can reuse the stored 1628 * copy and do not need to resetup the pptable again. 1629 */ 1630 if (!adev->in_runpm) { 1631 ret = smu_setup_pptable(smu); 1632 if (ret) { 1633 dev_err(adev->dev, "Failed to setup pptable!\n"); 1634 return ret; 1635 } 1636 } 1637 1638 /* smu_dump_pptable(smu); */ 1639 1640 /* 1641 * With SCPM enabled, PSP is responsible for the PPTable transferring 1642 * (to SMU). Driver involvement is not needed and permitted. 1643 */ 1644 if (!adev->scpm_enabled) { 1645 /* 1646 * Copy pptable bo in the vram to smc with SMU MSGs such as 1647 * SetDriverDramAddr and TransferTableDram2Smu. 1648 */ 1649 ret = smu_write_pptable(smu); 1650 if (ret) { 1651 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1652 return ret; 1653 } 1654 } 1655 1656 /* issue Run*Btc msg */ 1657 ret = smu_run_btc(smu); 1658 if (ret) 1659 return ret; 1660 1661 /* Enable UclkShadow on wbrf supported */ 1662 if (smu->wbrf_supported) { 1663 ret = smu_enable_uclk_shadow(smu, true); 1664 if (ret) { 1665 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1666 return ret; 1667 } 1668 } 1669 1670 /* 1671 * With SCPM enabled, these actions(and relevant messages) are 1672 * not needed and permitted. 1673 */ 1674 if (!adev->scpm_enabled) { 1675 ret = smu_feature_set_allowed_mask(smu); 1676 if (ret) { 1677 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1678 return ret; 1679 } 1680 } 1681 1682 ret = smu_system_features_control(smu, true); 1683 if (ret) { 1684 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1685 return ret; 1686 } 1687 1688 smu_init_xgmi_plpd_mode(smu); 1689 1690 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1691 if (ret) { 1692 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1693 return ret; 1694 } 1695 bitmap_copy(feature->supported, 1696 (unsigned long *)&features_supported, 1697 feature->feature_num); 1698 1699 if (!smu_is_dpm_running(smu)) 1700 dev_info(adev->dev, "dpm has been disabled\n"); 1701 1702 /* 1703 * Set initialized values (get from vbios) to dpm tables context such as 1704 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1705 * type of clks. 1706 */ 1707 ret = smu_set_default_dpm_table(smu); 1708 if (ret) { 1709 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1710 return ret; 1711 } 1712 1713 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1714 pcie_gen = 4; 1715 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1716 pcie_gen = 3; 1717 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1718 pcie_gen = 2; 1719 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1720 pcie_gen = 1; 1721 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1722 pcie_gen = 0; 1723 1724 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1725 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1726 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1727 */ 1728 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1729 pcie_width = 7; 1730 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1731 pcie_width = 6; 1732 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1733 pcie_width = 5; 1734 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1735 pcie_width = 4; 1736 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1737 pcie_width = 3; 1738 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1739 pcie_width = 2; 1740 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1741 pcie_width = 1; 1742 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1743 if (ret) { 1744 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1745 return ret; 1746 } 1747 1748 ret = smu_get_thermal_temperature_range(smu); 1749 if (ret) { 1750 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1751 return ret; 1752 } 1753 1754 ret = smu_enable_thermal_alert(smu); 1755 if (ret) { 1756 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1757 return ret; 1758 } 1759 1760 ret = smu_notify_display_change(smu); 1761 if (ret) { 1762 dev_err(adev->dev, "Failed to notify display change!\n"); 1763 return ret; 1764 } 1765 1766 /* 1767 * Set min deep sleep dce fclk with bootup value from vbios via 1768 * SetMinDeepSleepDcefclk MSG. 1769 */ 1770 ret = smu_set_min_dcef_deep_sleep(smu, 1771 smu->smu_table.boot_values.dcefclk / 100); 1772 if (ret) { 1773 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1774 return ret; 1775 } 1776 1777 /* Init wbrf support. Properly setup the notifier */ 1778 ret = smu_wbrf_init(smu); 1779 if (ret) 1780 dev_err(adev->dev, "Error during wbrf init call\n"); 1781 1782 return ret; 1783 } 1784 1785 static int smu_start_smc_engine(struct smu_context *smu) 1786 { 1787 struct amdgpu_device *adev = smu->adev; 1788 int ret = 0; 1789 1790 smu->smc_fw_state = SMU_FW_INIT; 1791 1792 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1793 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1794 if (smu->ppt_funcs->load_microcode) { 1795 ret = smu->ppt_funcs->load_microcode(smu); 1796 if (ret) 1797 return ret; 1798 } 1799 } 1800 } 1801 1802 if (smu->ppt_funcs->check_fw_status) { 1803 ret = smu->ppt_funcs->check_fw_status(smu); 1804 if (ret) { 1805 dev_err(adev->dev, "SMC is not ready\n"); 1806 return ret; 1807 } 1808 } 1809 1810 /* 1811 * Send msg GetDriverIfVersion to check if the return value is equal 1812 * with DRIVER_IF_VERSION of smc header. 1813 */ 1814 ret = smu_check_fw_version(smu); 1815 if (ret) 1816 return ret; 1817 1818 return ret; 1819 } 1820 1821 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1822 { 1823 int i, ret; 1824 struct amdgpu_device *adev = ip_block->adev; 1825 struct smu_context *smu = adev->powerplay.pp_handle; 1826 1827 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1828 smu->pm_enabled = false; 1829 return 0; 1830 } 1831 1832 ret = smu_start_smc_engine(smu); 1833 if (ret) { 1834 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1835 return ret; 1836 } 1837 1838 /* 1839 * Check whether wbrf is supported. This needs to be done 1840 * before SMU setup starts since part of SMU configuration 1841 * relies on this. 1842 */ 1843 smu_wbrf_support_check(smu); 1844 1845 if (smu->is_apu) { 1846 ret = smu_set_gfx_imu_enable(smu); 1847 if (ret) 1848 return ret; 1849 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1850 smu_dpm_set_vcn_enable(smu, true, i); 1851 smu_dpm_set_jpeg_enable(smu, true); 1852 smu_dpm_set_vpe_enable(smu, true); 1853 smu_dpm_set_umsch_mm_enable(smu, true); 1854 smu_set_mall_enable(smu); 1855 smu_set_gfx_cgpg(smu, true); 1856 } 1857 1858 if (!smu->pm_enabled) 1859 return 0; 1860 1861 ret = smu_get_driver_allowed_feature_mask(smu); 1862 if (ret) 1863 return ret; 1864 1865 ret = smu_smc_hw_setup(smu); 1866 if (ret) { 1867 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1868 return ret; 1869 } 1870 1871 /* 1872 * Move maximum sustainable clock retrieving here considering 1873 * 1. It is not needed on resume(from S3). 1874 * 2. DAL settings come between .hw_init and .late_init of SMU. 1875 * And DAL needs to know the maximum sustainable clocks. Thus 1876 * it cannot be put in .late_init(). 1877 */ 1878 ret = smu_init_max_sustainable_clocks(smu); 1879 if (ret) { 1880 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1881 return ret; 1882 } 1883 1884 adev->pm.dpm_enabled = true; 1885 1886 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1887 1888 return 0; 1889 } 1890 1891 static int smu_disable_dpms(struct smu_context *smu) 1892 { 1893 struct amdgpu_device *adev = smu->adev; 1894 int ret = 0; 1895 bool use_baco = !smu->is_apu && 1896 ((amdgpu_in_reset(adev) && 1897 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1898 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1899 1900 /* 1901 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1902 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1903 */ 1904 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1905 case IP_VERSION(13, 0, 0): 1906 case IP_VERSION(13, 0, 7): 1907 case IP_VERSION(13, 0, 10): 1908 case IP_VERSION(14, 0, 2): 1909 case IP_VERSION(14, 0, 3): 1910 return 0; 1911 default: 1912 break; 1913 } 1914 1915 /* 1916 * For custom pptable uploading, skip the DPM features 1917 * disable process on Navi1x ASICs. 1918 * - As the gfx related features are under control of 1919 * RLC on those ASICs. RLC reinitialization will be 1920 * needed to reenable them. That will cost much more 1921 * efforts. 1922 * 1923 * - SMU firmware can handle the DPM reenablement 1924 * properly. 1925 */ 1926 if (smu->uploading_custom_pp_table) { 1927 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1928 case IP_VERSION(11, 0, 0): 1929 case IP_VERSION(11, 0, 5): 1930 case IP_VERSION(11, 0, 9): 1931 case IP_VERSION(11, 0, 7): 1932 case IP_VERSION(11, 0, 11): 1933 case IP_VERSION(11, 5, 0): 1934 case IP_VERSION(11, 0, 12): 1935 case IP_VERSION(11, 0, 13): 1936 return 0; 1937 default: 1938 break; 1939 } 1940 } 1941 1942 /* 1943 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1944 * on BACO in. Driver involvement is unnecessary. 1945 */ 1946 if (use_baco) { 1947 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1948 case IP_VERSION(11, 0, 7): 1949 case IP_VERSION(11, 0, 0): 1950 case IP_VERSION(11, 0, 5): 1951 case IP_VERSION(11, 0, 9): 1952 case IP_VERSION(13, 0, 7): 1953 return 0; 1954 default: 1955 break; 1956 } 1957 } 1958 1959 /* 1960 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1961 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1962 */ 1963 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1964 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1965 return 0; 1966 1967 /* 1968 * For gpu reset, runpm and hibernation through BACO, 1969 * BACO feature has to be kept enabled. 1970 */ 1971 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1972 ret = smu_disable_all_features_with_exception(smu, 1973 SMU_FEATURE_BACO_BIT); 1974 if (ret) 1975 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1976 } else { 1977 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1978 if (!adev->scpm_enabled) { 1979 ret = smu_system_features_control(smu, false); 1980 if (ret) 1981 dev_err(adev->dev, "Failed to disable smu features.\n"); 1982 } 1983 } 1984 1985 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1986 * otherwise SMU will hang while interacting with RLC if RLC is halted 1987 * this is a WA for Vangogh asic which fix the SMU hang issue. 1988 */ 1989 ret = smu_notify_rlc_state(smu, false); 1990 if (ret) { 1991 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1992 return ret; 1993 } 1994 1995 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1996 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1997 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1998 adev->gfx.rlc.funcs->stop(adev); 1999 2000 return ret; 2001 } 2002 2003 static int smu_smc_hw_cleanup(struct smu_context *smu) 2004 { 2005 struct amdgpu_device *adev = smu->adev; 2006 int ret = 0; 2007 2008 smu_wbrf_fini(smu); 2009 2010 cancel_work_sync(&smu->throttling_logging_work); 2011 cancel_work_sync(&smu->interrupt_work); 2012 2013 ret = smu_disable_thermal_alert(smu); 2014 if (ret) { 2015 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2016 return ret; 2017 } 2018 2019 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2020 2021 ret = smu_disable_dpms(smu); 2022 if (ret) { 2023 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2024 return ret; 2025 } 2026 2027 return 0; 2028 } 2029 2030 static int smu_reset_mp1_state(struct smu_context *smu) 2031 { 2032 struct amdgpu_device *adev = smu->adev; 2033 int ret = 0; 2034 2035 if ((!adev->in_runpm) && (!adev->in_suspend) && 2036 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2037 IP_VERSION(13, 0, 10) && 2038 !amdgpu_device_has_display_hardware(adev)) 2039 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2040 2041 return ret; 2042 } 2043 2044 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2045 { 2046 struct amdgpu_device *adev = ip_block->adev; 2047 struct smu_context *smu = adev->powerplay.pp_handle; 2048 int i, ret; 2049 2050 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2051 return 0; 2052 2053 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 2054 smu_dpm_set_vcn_enable(smu, false, i); 2055 smu_dpm_set_jpeg_enable(smu, false); 2056 smu_dpm_set_vpe_enable(smu, false); 2057 smu_dpm_set_umsch_mm_enable(smu, false); 2058 2059 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2060 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2061 2062 if (!smu->pm_enabled) 2063 return 0; 2064 2065 adev->pm.dpm_enabled = false; 2066 2067 ret = smu_smc_hw_cleanup(smu); 2068 if (ret) 2069 return ret; 2070 2071 ret = smu_reset_mp1_state(smu); 2072 if (ret) 2073 return ret; 2074 2075 return 0; 2076 } 2077 2078 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2079 { 2080 struct amdgpu_device *adev = ip_block->adev; 2081 struct smu_context *smu = adev->powerplay.pp_handle; 2082 2083 kfree(smu); 2084 } 2085 2086 static int smu_reset(struct smu_context *smu) 2087 { 2088 struct amdgpu_device *adev = smu->adev; 2089 struct amdgpu_ip_block *ip_block; 2090 int ret; 2091 2092 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2093 if (!ip_block) 2094 return -EINVAL; 2095 2096 ret = smu_hw_fini(ip_block); 2097 if (ret) 2098 return ret; 2099 2100 ret = smu_hw_init(ip_block); 2101 if (ret) 2102 return ret; 2103 2104 ret = smu_late_init(ip_block); 2105 if (ret) 2106 return ret; 2107 2108 return 0; 2109 } 2110 2111 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2112 { 2113 struct amdgpu_device *adev = ip_block->adev; 2114 struct smu_context *smu = adev->powerplay.pp_handle; 2115 int ret; 2116 uint64_t count; 2117 2118 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2119 return 0; 2120 2121 if (!smu->pm_enabled) 2122 return 0; 2123 2124 adev->pm.dpm_enabled = false; 2125 2126 ret = smu_smc_hw_cleanup(smu); 2127 if (ret) 2128 return ret; 2129 2130 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2131 2132 smu_set_gfx_cgpg(smu, false); 2133 2134 /* 2135 * pwfw resets entrycount when device is suspended, so we save the 2136 * last value to be used when we resume to keep it consistent 2137 */ 2138 ret = smu_get_entrycount_gfxoff(smu, &count); 2139 if (!ret) 2140 adev->gfx.gfx_off_entrycount = count; 2141 2142 /* clear this on suspend so it will get reprogrammed on resume */ 2143 smu->workload_mask = 0; 2144 2145 return 0; 2146 } 2147 2148 static int smu_resume(struct amdgpu_ip_block *ip_block) 2149 { 2150 int ret; 2151 struct amdgpu_device *adev = ip_block->adev; 2152 struct smu_context *smu = adev->powerplay.pp_handle; 2153 2154 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2155 return 0; 2156 2157 if (!smu->pm_enabled) 2158 return 0; 2159 2160 dev_info(adev->dev, "SMU is resuming...\n"); 2161 2162 ret = smu_start_smc_engine(smu); 2163 if (ret) { 2164 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2165 return ret; 2166 } 2167 2168 ret = smu_smc_hw_setup(smu); 2169 if (ret) { 2170 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2171 return ret; 2172 } 2173 2174 ret = smu_set_gfx_imu_enable(smu); 2175 if (ret) 2176 return ret; 2177 2178 smu_set_gfx_cgpg(smu, true); 2179 2180 smu->disable_uclk_switch = 0; 2181 2182 adev->pm.dpm_enabled = true; 2183 2184 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2185 2186 return 0; 2187 } 2188 2189 static int smu_display_configuration_change(void *handle, 2190 const struct amd_pp_display_configuration *display_config) 2191 { 2192 struct smu_context *smu = handle; 2193 2194 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2195 return -EOPNOTSUPP; 2196 2197 if (!display_config) 2198 return -EINVAL; 2199 2200 smu_set_min_dcef_deep_sleep(smu, 2201 display_config->min_dcef_deep_sleep_set_clk / 100); 2202 2203 return 0; 2204 } 2205 2206 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2207 enum amd_clockgating_state state) 2208 { 2209 return 0; 2210 } 2211 2212 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2213 enum amd_powergating_state state) 2214 { 2215 return 0; 2216 } 2217 2218 static int smu_enable_umd_pstate(void *handle, 2219 enum amd_dpm_forced_level *level) 2220 { 2221 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2222 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2223 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2224 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2225 2226 struct smu_context *smu = (struct smu_context*)(handle); 2227 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2228 2229 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2230 return -EINVAL; 2231 2232 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2233 /* enter umd pstate, save current level, disable gfx cg*/ 2234 if (*level & profile_mode_mask) { 2235 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2236 smu_gpo_control(smu, false); 2237 smu_gfx_ulv_control(smu, false); 2238 smu_deep_sleep_control(smu, false); 2239 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2240 } 2241 } else { 2242 /* exit umd pstate, restore level, enable gfx cg*/ 2243 if (!(*level & profile_mode_mask)) { 2244 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2245 *level = smu_dpm_ctx->saved_dpm_level; 2246 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2247 smu_deep_sleep_control(smu, true); 2248 smu_gfx_ulv_control(smu, true); 2249 smu_gpo_control(smu, true); 2250 } 2251 } 2252 2253 return 0; 2254 } 2255 2256 static int smu_bump_power_profile_mode(struct smu_context *smu, 2257 long *custom_params, 2258 u32 custom_params_max_idx) 2259 { 2260 u32 workload_mask = 0; 2261 int i, ret = 0; 2262 2263 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2264 if (smu->workload_refcount[i]) 2265 workload_mask |= 1 << i; 2266 } 2267 2268 if (smu->workload_mask == workload_mask) 2269 return 0; 2270 2271 if (smu->ppt_funcs->set_power_profile_mode) 2272 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2273 custom_params, 2274 custom_params_max_idx); 2275 2276 if (!ret) 2277 smu->workload_mask = workload_mask; 2278 2279 return ret; 2280 } 2281 2282 static void smu_power_profile_mode_get(struct smu_context *smu, 2283 enum PP_SMC_POWER_PROFILE profile_mode) 2284 { 2285 smu->workload_refcount[profile_mode]++; 2286 } 2287 2288 static void smu_power_profile_mode_put(struct smu_context *smu, 2289 enum PP_SMC_POWER_PROFILE profile_mode) 2290 { 2291 if (smu->workload_refcount[profile_mode]) 2292 smu->workload_refcount[profile_mode]--; 2293 } 2294 2295 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2296 enum amd_dpm_forced_level level, 2297 bool skip_display_settings) 2298 { 2299 int ret = 0; 2300 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2301 2302 if (!skip_display_settings) { 2303 ret = smu_display_config_changed(smu); 2304 if (ret) { 2305 dev_err(smu->adev->dev, "Failed to change display config!"); 2306 return ret; 2307 } 2308 } 2309 2310 ret = smu_apply_clocks_adjust_rules(smu); 2311 if (ret) { 2312 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2313 return ret; 2314 } 2315 2316 if (!skip_display_settings) { 2317 ret = smu_notify_smc_display_config(smu); 2318 if (ret) { 2319 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2320 return ret; 2321 } 2322 } 2323 2324 if (smu_dpm_ctx->dpm_level != level) { 2325 ret = smu_asic_set_performance_level(smu, level); 2326 if (ret) { 2327 dev_err(smu->adev->dev, "Failed to set performance level!"); 2328 return ret; 2329 } 2330 2331 /* update the saved copy */ 2332 smu_dpm_ctx->dpm_level = level; 2333 } 2334 2335 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2336 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2337 smu_bump_power_profile_mode(smu, NULL, 0); 2338 2339 return ret; 2340 } 2341 2342 static int smu_handle_task(struct smu_context *smu, 2343 enum amd_dpm_forced_level level, 2344 enum amd_pp_task task_id) 2345 { 2346 int ret = 0; 2347 2348 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2349 return -EOPNOTSUPP; 2350 2351 switch (task_id) { 2352 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2353 ret = smu_pre_display_config_changed(smu); 2354 if (ret) 2355 return ret; 2356 ret = smu_adjust_power_state_dynamic(smu, level, false); 2357 break; 2358 case AMD_PP_TASK_COMPLETE_INIT: 2359 ret = smu_adjust_power_state_dynamic(smu, level, true); 2360 break; 2361 case AMD_PP_TASK_READJUST_POWER_STATE: 2362 ret = smu_adjust_power_state_dynamic(smu, level, true); 2363 break; 2364 default: 2365 break; 2366 } 2367 2368 return ret; 2369 } 2370 2371 static int smu_handle_dpm_task(void *handle, 2372 enum amd_pp_task task_id, 2373 enum amd_pm_state_type *user_state) 2374 { 2375 struct smu_context *smu = handle; 2376 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2377 2378 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2379 2380 } 2381 2382 static int smu_switch_power_profile(void *handle, 2383 enum PP_SMC_POWER_PROFILE type, 2384 bool enable) 2385 { 2386 struct smu_context *smu = handle; 2387 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2388 int ret; 2389 2390 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2391 return -EOPNOTSUPP; 2392 2393 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2394 return -EINVAL; 2395 2396 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2397 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2398 if (enable) 2399 smu_power_profile_mode_get(smu, type); 2400 else 2401 smu_power_profile_mode_put(smu, type); 2402 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2403 if (ret) { 2404 if (enable) 2405 smu_power_profile_mode_put(smu, type); 2406 else 2407 smu_power_profile_mode_get(smu, type); 2408 return ret; 2409 } 2410 } 2411 2412 return 0; 2413 } 2414 2415 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2416 { 2417 struct smu_context *smu = handle; 2418 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2419 2420 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2421 return -EOPNOTSUPP; 2422 2423 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2424 return -EINVAL; 2425 2426 return smu_dpm_ctx->dpm_level; 2427 } 2428 2429 static int smu_force_performance_level(void *handle, 2430 enum amd_dpm_forced_level level) 2431 { 2432 struct smu_context *smu = handle; 2433 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2434 int ret = 0; 2435 2436 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2437 return -EOPNOTSUPP; 2438 2439 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2440 return -EINVAL; 2441 2442 ret = smu_enable_umd_pstate(smu, &level); 2443 if (ret) 2444 return ret; 2445 2446 ret = smu_handle_task(smu, level, 2447 AMD_PP_TASK_READJUST_POWER_STATE); 2448 2449 /* reset user dpm clock state */ 2450 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2451 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2452 smu->user_dpm_profile.clk_dependency = 0; 2453 } 2454 2455 return ret; 2456 } 2457 2458 static int smu_set_display_count(void *handle, uint32_t count) 2459 { 2460 struct smu_context *smu = handle; 2461 2462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2463 return -EOPNOTSUPP; 2464 2465 return smu_init_display_count(smu, count); 2466 } 2467 2468 static int smu_force_smuclk_levels(struct smu_context *smu, 2469 enum smu_clk_type clk_type, 2470 uint32_t mask) 2471 { 2472 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2473 int ret = 0; 2474 2475 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2476 return -EOPNOTSUPP; 2477 2478 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2479 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2480 return -EINVAL; 2481 } 2482 2483 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2484 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2485 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2486 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2487 smu_set_user_clk_dependencies(smu, clk_type); 2488 } 2489 } 2490 2491 return ret; 2492 } 2493 2494 static int smu_force_ppclk_levels(void *handle, 2495 enum pp_clock_type type, 2496 uint32_t mask) 2497 { 2498 struct smu_context *smu = handle; 2499 enum smu_clk_type clk_type; 2500 2501 switch (type) { 2502 case PP_SCLK: 2503 clk_type = SMU_SCLK; break; 2504 case PP_MCLK: 2505 clk_type = SMU_MCLK; break; 2506 case PP_PCIE: 2507 clk_type = SMU_PCIE; break; 2508 case PP_SOCCLK: 2509 clk_type = SMU_SOCCLK; break; 2510 case PP_FCLK: 2511 clk_type = SMU_FCLK; break; 2512 case PP_DCEFCLK: 2513 clk_type = SMU_DCEFCLK; break; 2514 case PP_VCLK: 2515 clk_type = SMU_VCLK; break; 2516 case PP_VCLK1: 2517 clk_type = SMU_VCLK1; break; 2518 case PP_DCLK: 2519 clk_type = SMU_DCLK; break; 2520 case PP_DCLK1: 2521 clk_type = SMU_DCLK1; break; 2522 case OD_SCLK: 2523 clk_type = SMU_OD_SCLK; break; 2524 case OD_MCLK: 2525 clk_type = SMU_OD_MCLK; break; 2526 case OD_VDDC_CURVE: 2527 clk_type = SMU_OD_VDDC_CURVE; break; 2528 case OD_RANGE: 2529 clk_type = SMU_OD_RANGE; break; 2530 default: 2531 return -EINVAL; 2532 } 2533 2534 return smu_force_smuclk_levels(smu, clk_type, mask); 2535 } 2536 2537 /* 2538 * On system suspending or resetting, the dpm_enabled 2539 * flag will be cleared. So that those SMU services which 2540 * are not supported will be gated. 2541 * However, the mp1 state setting should still be granted 2542 * even if the dpm_enabled cleared. 2543 */ 2544 static int smu_set_mp1_state(void *handle, 2545 enum pp_mp1_state mp1_state) 2546 { 2547 struct smu_context *smu = handle; 2548 int ret = 0; 2549 2550 if (!smu->pm_enabled) 2551 return -EOPNOTSUPP; 2552 2553 if (smu->ppt_funcs && 2554 smu->ppt_funcs->set_mp1_state) 2555 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2556 2557 return ret; 2558 } 2559 2560 static int smu_set_df_cstate(void *handle, 2561 enum pp_df_cstate state) 2562 { 2563 struct smu_context *smu = handle; 2564 int ret = 0; 2565 2566 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2567 return -EOPNOTSUPP; 2568 2569 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2570 return 0; 2571 2572 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2573 if (ret) 2574 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2575 2576 return ret; 2577 } 2578 2579 int smu_write_watermarks_table(struct smu_context *smu) 2580 { 2581 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2582 return -EOPNOTSUPP; 2583 2584 return smu_set_watermarks_table(smu, NULL); 2585 } 2586 2587 static int smu_set_watermarks_for_clock_ranges(void *handle, 2588 struct pp_smu_wm_range_sets *clock_ranges) 2589 { 2590 struct smu_context *smu = handle; 2591 2592 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2593 return -EOPNOTSUPP; 2594 2595 if (smu->disable_watermark) 2596 return 0; 2597 2598 return smu_set_watermarks_table(smu, clock_ranges); 2599 } 2600 2601 int smu_set_ac_dc(struct smu_context *smu) 2602 { 2603 int ret = 0; 2604 2605 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2606 return -EOPNOTSUPP; 2607 2608 /* controlled by firmware */ 2609 if (smu->dc_controlled_by_gpio) 2610 return 0; 2611 2612 ret = smu_set_power_source(smu, 2613 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2614 SMU_POWER_SOURCE_DC); 2615 if (ret) 2616 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2617 smu->adev->pm.ac_power ? "AC" : "DC"); 2618 2619 return ret; 2620 } 2621 2622 const struct amd_ip_funcs smu_ip_funcs = { 2623 .name = "smu", 2624 .early_init = smu_early_init, 2625 .late_init = smu_late_init, 2626 .sw_init = smu_sw_init, 2627 .sw_fini = smu_sw_fini, 2628 .hw_init = smu_hw_init, 2629 .hw_fini = smu_hw_fini, 2630 .late_fini = smu_late_fini, 2631 .suspend = smu_suspend, 2632 .resume = smu_resume, 2633 .is_idle = NULL, 2634 .check_soft_reset = NULL, 2635 .wait_for_idle = NULL, 2636 .soft_reset = NULL, 2637 .set_clockgating_state = smu_set_clockgating_state, 2638 .set_powergating_state = smu_set_powergating_state, 2639 }; 2640 2641 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2642 .type = AMD_IP_BLOCK_TYPE_SMC, 2643 .major = 11, 2644 .minor = 0, 2645 .rev = 0, 2646 .funcs = &smu_ip_funcs, 2647 }; 2648 2649 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2650 .type = AMD_IP_BLOCK_TYPE_SMC, 2651 .major = 12, 2652 .minor = 0, 2653 .rev = 0, 2654 .funcs = &smu_ip_funcs, 2655 }; 2656 2657 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2658 .type = AMD_IP_BLOCK_TYPE_SMC, 2659 .major = 13, 2660 .minor = 0, 2661 .rev = 0, 2662 .funcs = &smu_ip_funcs, 2663 }; 2664 2665 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2666 .type = AMD_IP_BLOCK_TYPE_SMC, 2667 .major = 14, 2668 .minor = 0, 2669 .rev = 0, 2670 .funcs = &smu_ip_funcs, 2671 }; 2672 2673 static int smu_load_microcode(void *handle) 2674 { 2675 struct smu_context *smu = handle; 2676 struct amdgpu_device *adev = smu->adev; 2677 int ret = 0; 2678 2679 if (!smu->pm_enabled) 2680 return -EOPNOTSUPP; 2681 2682 /* This should be used for non PSP loading */ 2683 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2684 return 0; 2685 2686 if (smu->ppt_funcs->load_microcode) { 2687 ret = smu->ppt_funcs->load_microcode(smu); 2688 if (ret) { 2689 dev_err(adev->dev, "Load microcode failed\n"); 2690 return ret; 2691 } 2692 } 2693 2694 if (smu->ppt_funcs->check_fw_status) { 2695 ret = smu->ppt_funcs->check_fw_status(smu); 2696 if (ret) { 2697 dev_err(adev->dev, "SMC is not ready\n"); 2698 return ret; 2699 } 2700 } 2701 2702 return ret; 2703 } 2704 2705 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2706 { 2707 int ret = 0; 2708 2709 if (smu->ppt_funcs->set_gfx_cgpg) 2710 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2711 2712 return ret; 2713 } 2714 2715 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2716 { 2717 struct smu_context *smu = handle; 2718 int ret = 0; 2719 2720 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2721 return -EOPNOTSUPP; 2722 2723 if (!smu->ppt_funcs->set_fan_speed_rpm) 2724 return -EOPNOTSUPP; 2725 2726 if (speed == U32_MAX) 2727 return -EINVAL; 2728 2729 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2730 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2731 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2732 smu->user_dpm_profile.fan_speed_rpm = speed; 2733 2734 /* Override custom PWM setting as they cannot co-exist */ 2735 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2736 smu->user_dpm_profile.fan_speed_pwm = 0; 2737 } 2738 2739 return ret; 2740 } 2741 2742 /** 2743 * smu_get_power_limit - Request one of the SMU Power Limits 2744 * 2745 * @handle: pointer to smu context 2746 * @limit: requested limit is written back to this variable 2747 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2748 * @pp_power_type: &pp_power_type type of power 2749 * Return: 0 on success, <0 on error 2750 * 2751 */ 2752 int smu_get_power_limit(void *handle, 2753 uint32_t *limit, 2754 enum pp_power_limit_level pp_limit_level, 2755 enum pp_power_type pp_power_type) 2756 { 2757 struct smu_context *smu = handle; 2758 struct amdgpu_device *adev = smu->adev; 2759 enum smu_ppt_limit_level limit_level; 2760 uint32_t limit_type; 2761 int ret = 0; 2762 2763 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2764 return -EOPNOTSUPP; 2765 2766 switch (pp_power_type) { 2767 case PP_PWR_TYPE_SUSTAINED: 2768 limit_type = SMU_DEFAULT_PPT_LIMIT; 2769 break; 2770 case PP_PWR_TYPE_FAST: 2771 limit_type = SMU_FAST_PPT_LIMIT; 2772 break; 2773 default: 2774 return -EOPNOTSUPP; 2775 } 2776 2777 switch (pp_limit_level) { 2778 case PP_PWR_LIMIT_CURRENT: 2779 limit_level = SMU_PPT_LIMIT_CURRENT; 2780 break; 2781 case PP_PWR_LIMIT_DEFAULT: 2782 limit_level = SMU_PPT_LIMIT_DEFAULT; 2783 break; 2784 case PP_PWR_LIMIT_MAX: 2785 limit_level = SMU_PPT_LIMIT_MAX; 2786 break; 2787 case PP_PWR_LIMIT_MIN: 2788 limit_level = SMU_PPT_LIMIT_MIN; 2789 break; 2790 default: 2791 return -EOPNOTSUPP; 2792 } 2793 2794 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2795 if (smu->ppt_funcs->get_ppt_limit) 2796 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2797 } else { 2798 switch (limit_level) { 2799 case SMU_PPT_LIMIT_CURRENT: 2800 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2801 case IP_VERSION(13, 0, 2): 2802 case IP_VERSION(13, 0, 6): 2803 case IP_VERSION(13, 0, 14): 2804 case IP_VERSION(11, 0, 7): 2805 case IP_VERSION(11, 0, 11): 2806 case IP_VERSION(11, 0, 12): 2807 case IP_VERSION(11, 0, 13): 2808 ret = smu_get_asic_power_limits(smu, 2809 &smu->current_power_limit, 2810 NULL, NULL, NULL); 2811 break; 2812 default: 2813 break; 2814 } 2815 *limit = smu->current_power_limit; 2816 break; 2817 case SMU_PPT_LIMIT_DEFAULT: 2818 *limit = smu->default_power_limit; 2819 break; 2820 case SMU_PPT_LIMIT_MAX: 2821 *limit = smu->max_power_limit; 2822 break; 2823 case SMU_PPT_LIMIT_MIN: 2824 *limit = smu->min_power_limit; 2825 break; 2826 default: 2827 return -EINVAL; 2828 } 2829 } 2830 2831 return ret; 2832 } 2833 2834 static int smu_set_power_limit(void *handle, uint32_t limit) 2835 { 2836 struct smu_context *smu = handle; 2837 uint32_t limit_type = limit >> 24; 2838 int ret = 0; 2839 2840 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2841 return -EOPNOTSUPP; 2842 2843 limit &= (1<<24)-1; 2844 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2845 if (smu->ppt_funcs->set_power_limit) 2846 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2847 2848 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2849 dev_err(smu->adev->dev, 2850 "New power limit (%d) is out of range [%d,%d]\n", 2851 limit, smu->min_power_limit, smu->max_power_limit); 2852 return -EINVAL; 2853 } 2854 2855 if (!limit) 2856 limit = smu->current_power_limit; 2857 2858 if (smu->ppt_funcs->set_power_limit) { 2859 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2860 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2861 smu->user_dpm_profile.power_limit = limit; 2862 } 2863 2864 return ret; 2865 } 2866 2867 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2868 { 2869 int ret = 0; 2870 2871 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2872 return -EOPNOTSUPP; 2873 2874 if (smu->ppt_funcs->print_clk_levels) 2875 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2876 2877 return ret; 2878 } 2879 2880 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2881 { 2882 enum smu_clk_type clk_type; 2883 2884 switch (type) { 2885 case PP_SCLK: 2886 clk_type = SMU_SCLK; break; 2887 case PP_MCLK: 2888 clk_type = SMU_MCLK; break; 2889 case PP_PCIE: 2890 clk_type = SMU_PCIE; break; 2891 case PP_SOCCLK: 2892 clk_type = SMU_SOCCLK; break; 2893 case PP_FCLK: 2894 clk_type = SMU_FCLK; break; 2895 case PP_DCEFCLK: 2896 clk_type = SMU_DCEFCLK; break; 2897 case PP_VCLK: 2898 clk_type = SMU_VCLK; break; 2899 case PP_VCLK1: 2900 clk_type = SMU_VCLK1; break; 2901 case PP_DCLK: 2902 clk_type = SMU_DCLK; break; 2903 case PP_DCLK1: 2904 clk_type = SMU_DCLK1; break; 2905 case OD_SCLK: 2906 clk_type = SMU_OD_SCLK; break; 2907 case OD_MCLK: 2908 clk_type = SMU_OD_MCLK; break; 2909 case OD_VDDC_CURVE: 2910 clk_type = SMU_OD_VDDC_CURVE; break; 2911 case OD_RANGE: 2912 clk_type = SMU_OD_RANGE; break; 2913 case OD_VDDGFX_OFFSET: 2914 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2915 case OD_CCLK: 2916 clk_type = SMU_OD_CCLK; break; 2917 case OD_FAN_CURVE: 2918 clk_type = SMU_OD_FAN_CURVE; break; 2919 case OD_ACOUSTIC_LIMIT: 2920 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2921 case OD_ACOUSTIC_TARGET: 2922 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2923 case OD_FAN_TARGET_TEMPERATURE: 2924 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2925 case OD_FAN_MINIMUM_PWM: 2926 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2927 case OD_FAN_ZERO_RPM_ENABLE: 2928 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2929 case OD_FAN_ZERO_RPM_STOP_TEMP: 2930 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2931 default: 2932 clk_type = SMU_CLK_COUNT; break; 2933 } 2934 2935 return clk_type; 2936 } 2937 2938 static int smu_print_ppclk_levels(void *handle, 2939 enum pp_clock_type type, 2940 char *buf) 2941 { 2942 struct smu_context *smu = handle; 2943 enum smu_clk_type clk_type; 2944 2945 clk_type = smu_convert_to_smuclk(type); 2946 if (clk_type == SMU_CLK_COUNT) 2947 return -EINVAL; 2948 2949 return smu_print_smuclk_levels(smu, clk_type, buf); 2950 } 2951 2952 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2953 { 2954 struct smu_context *smu = handle; 2955 enum smu_clk_type clk_type; 2956 2957 clk_type = smu_convert_to_smuclk(type); 2958 if (clk_type == SMU_CLK_COUNT) 2959 return -EINVAL; 2960 2961 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2962 return -EOPNOTSUPP; 2963 2964 if (!smu->ppt_funcs->emit_clk_levels) 2965 return -ENOENT; 2966 2967 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2968 2969 } 2970 2971 static int smu_od_edit_dpm_table(void *handle, 2972 enum PP_OD_DPM_TABLE_COMMAND type, 2973 long *input, uint32_t size) 2974 { 2975 struct smu_context *smu = handle; 2976 int ret = 0; 2977 2978 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2979 return -EOPNOTSUPP; 2980 2981 if (smu->ppt_funcs->od_edit_dpm_table) { 2982 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2983 } 2984 2985 return ret; 2986 } 2987 2988 static int smu_read_sensor(void *handle, 2989 int sensor, 2990 void *data, 2991 int *size_arg) 2992 { 2993 struct smu_context *smu = handle; 2994 struct amdgpu_device *adev = smu->adev; 2995 struct smu_umd_pstate_table *pstate_table = 2996 &smu->pstate_table; 2997 int i, ret = 0; 2998 uint32_t *size, size_val; 2999 3000 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3001 return -EOPNOTSUPP; 3002 3003 if (!data || !size_arg) 3004 return -EINVAL; 3005 3006 size_val = *size_arg; 3007 size = &size_val; 3008 3009 if (smu->ppt_funcs->read_sensor) 3010 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3011 goto unlock; 3012 3013 switch (sensor) { 3014 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3015 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3016 *size = 4; 3017 break; 3018 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3019 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3020 *size = 4; 3021 break; 3022 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3023 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3024 *size = 4; 3025 break; 3026 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3027 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3028 *size = 4; 3029 break; 3030 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3031 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3032 *size = 8; 3033 break; 3034 case AMDGPU_PP_SENSOR_UVD_POWER: 3035 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3036 *size = 4; 3037 break; 3038 case AMDGPU_PP_SENSOR_VCE_POWER: 3039 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3040 *size = 4; 3041 break; 3042 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3043 *(uint32_t *)data = 0; 3044 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3045 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3046 *(uint32_t *)data = 1; 3047 break; 3048 } 3049 } 3050 *size = 4; 3051 break; 3052 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3053 *(uint32_t *)data = 0; 3054 *size = 4; 3055 break; 3056 default: 3057 *size = 0; 3058 ret = -EOPNOTSUPP; 3059 break; 3060 } 3061 3062 unlock: 3063 // assign uint32_t to int 3064 *size_arg = size_val; 3065 3066 return ret; 3067 } 3068 3069 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3070 { 3071 int ret = -EOPNOTSUPP; 3072 struct smu_context *smu = handle; 3073 3074 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3075 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3076 3077 return ret; 3078 } 3079 3080 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3081 { 3082 int ret = -EOPNOTSUPP; 3083 struct smu_context *smu = handle; 3084 3085 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3086 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3087 3088 return ret; 3089 } 3090 3091 static int smu_get_power_profile_mode(void *handle, char *buf) 3092 { 3093 struct smu_context *smu = handle; 3094 3095 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3096 !smu->ppt_funcs->get_power_profile_mode) 3097 return -EOPNOTSUPP; 3098 if (!buf) 3099 return -EINVAL; 3100 3101 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3102 } 3103 3104 static int smu_set_power_profile_mode(void *handle, 3105 long *param, 3106 uint32_t param_size) 3107 { 3108 struct smu_context *smu = handle; 3109 bool custom = false; 3110 int ret = 0; 3111 3112 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3113 !smu->ppt_funcs->set_power_profile_mode) 3114 return -EOPNOTSUPP; 3115 3116 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3117 custom = true; 3118 /* clear frontend mask so custom changes propogate */ 3119 smu->workload_mask = 0; 3120 } 3121 3122 if ((param[param_size] != smu->power_profile_mode) || custom) { 3123 /* clear the old user preference */ 3124 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3125 /* set the new user preference */ 3126 smu_power_profile_mode_get(smu, param[param_size]); 3127 ret = smu_bump_power_profile_mode(smu, 3128 custom ? param : NULL, 3129 custom ? param_size : 0); 3130 if (ret) 3131 smu_power_profile_mode_put(smu, param[param_size]); 3132 else 3133 /* store the user's preference */ 3134 smu->power_profile_mode = param[param_size]; 3135 } 3136 3137 return ret; 3138 } 3139 3140 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3141 { 3142 struct smu_context *smu = handle; 3143 3144 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3145 return -EOPNOTSUPP; 3146 3147 if (!smu->ppt_funcs->get_fan_control_mode) 3148 return -EOPNOTSUPP; 3149 3150 if (!fan_mode) 3151 return -EINVAL; 3152 3153 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3154 3155 return 0; 3156 } 3157 3158 static int smu_set_fan_control_mode(void *handle, u32 value) 3159 { 3160 struct smu_context *smu = handle; 3161 int ret = 0; 3162 3163 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3164 return -EOPNOTSUPP; 3165 3166 if (!smu->ppt_funcs->set_fan_control_mode) 3167 return -EOPNOTSUPP; 3168 3169 if (value == U32_MAX) 3170 return -EINVAL; 3171 3172 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3173 if (ret) 3174 goto out; 3175 3176 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3177 smu->user_dpm_profile.fan_mode = value; 3178 3179 /* reset user dpm fan speed */ 3180 if (value != AMD_FAN_CTRL_MANUAL) { 3181 smu->user_dpm_profile.fan_speed_pwm = 0; 3182 smu->user_dpm_profile.fan_speed_rpm = 0; 3183 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3184 } 3185 } 3186 3187 out: 3188 return ret; 3189 } 3190 3191 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3192 { 3193 struct smu_context *smu = handle; 3194 int ret = 0; 3195 3196 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3197 return -EOPNOTSUPP; 3198 3199 if (!smu->ppt_funcs->get_fan_speed_pwm) 3200 return -EOPNOTSUPP; 3201 3202 if (!speed) 3203 return -EINVAL; 3204 3205 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3206 3207 return ret; 3208 } 3209 3210 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3211 { 3212 struct smu_context *smu = handle; 3213 int ret = 0; 3214 3215 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3216 return -EOPNOTSUPP; 3217 3218 if (!smu->ppt_funcs->set_fan_speed_pwm) 3219 return -EOPNOTSUPP; 3220 3221 if (speed == U32_MAX) 3222 return -EINVAL; 3223 3224 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3225 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3226 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3227 smu->user_dpm_profile.fan_speed_pwm = speed; 3228 3229 /* Override custom RPM setting as they cannot co-exist */ 3230 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3231 smu->user_dpm_profile.fan_speed_rpm = 0; 3232 } 3233 3234 return ret; 3235 } 3236 3237 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3238 { 3239 struct smu_context *smu = handle; 3240 int ret = 0; 3241 3242 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3243 return -EOPNOTSUPP; 3244 3245 if (!smu->ppt_funcs->get_fan_speed_rpm) 3246 return -EOPNOTSUPP; 3247 3248 if (!speed) 3249 return -EINVAL; 3250 3251 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3252 3253 return ret; 3254 } 3255 3256 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3257 { 3258 struct smu_context *smu = handle; 3259 3260 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3261 return -EOPNOTSUPP; 3262 3263 return smu_set_min_dcef_deep_sleep(smu, clk); 3264 } 3265 3266 static int smu_get_clock_by_type_with_latency(void *handle, 3267 enum amd_pp_clock_type type, 3268 struct pp_clock_levels_with_latency *clocks) 3269 { 3270 struct smu_context *smu = handle; 3271 enum smu_clk_type clk_type; 3272 int ret = 0; 3273 3274 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3275 return -EOPNOTSUPP; 3276 3277 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3278 switch (type) { 3279 case amd_pp_sys_clock: 3280 clk_type = SMU_GFXCLK; 3281 break; 3282 case amd_pp_mem_clock: 3283 clk_type = SMU_MCLK; 3284 break; 3285 case amd_pp_dcef_clock: 3286 clk_type = SMU_DCEFCLK; 3287 break; 3288 case amd_pp_disp_clock: 3289 clk_type = SMU_DISPCLK; 3290 break; 3291 default: 3292 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3293 return -EINVAL; 3294 } 3295 3296 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3297 } 3298 3299 return ret; 3300 } 3301 3302 static int smu_display_clock_voltage_request(void *handle, 3303 struct pp_display_clock_request *clock_req) 3304 { 3305 struct smu_context *smu = handle; 3306 int ret = 0; 3307 3308 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3309 return -EOPNOTSUPP; 3310 3311 if (smu->ppt_funcs->display_clock_voltage_request) 3312 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3313 3314 return ret; 3315 } 3316 3317 3318 static int smu_display_disable_memory_clock_switch(void *handle, 3319 bool disable_memory_clock_switch) 3320 { 3321 struct smu_context *smu = handle; 3322 int ret = -EINVAL; 3323 3324 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3325 return -EOPNOTSUPP; 3326 3327 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3328 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3329 3330 return ret; 3331 } 3332 3333 static int smu_set_xgmi_pstate(void *handle, 3334 uint32_t pstate) 3335 { 3336 struct smu_context *smu = handle; 3337 int ret = 0; 3338 3339 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3340 return -EOPNOTSUPP; 3341 3342 if (smu->ppt_funcs->set_xgmi_pstate) 3343 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3344 3345 if (ret) 3346 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3347 3348 return ret; 3349 } 3350 3351 static int smu_get_baco_capability(void *handle) 3352 { 3353 struct smu_context *smu = handle; 3354 3355 if (!smu->pm_enabled) 3356 return false; 3357 3358 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3359 return false; 3360 3361 return smu->ppt_funcs->get_bamaco_support(smu); 3362 } 3363 3364 static int smu_baco_set_state(void *handle, int state) 3365 { 3366 struct smu_context *smu = handle; 3367 int ret = 0; 3368 3369 if (!smu->pm_enabled) 3370 return -EOPNOTSUPP; 3371 3372 if (state == 0) { 3373 if (smu->ppt_funcs->baco_exit) 3374 ret = smu->ppt_funcs->baco_exit(smu); 3375 } else if (state == 1) { 3376 if (smu->ppt_funcs->baco_enter) 3377 ret = smu->ppt_funcs->baco_enter(smu); 3378 } else { 3379 return -EINVAL; 3380 } 3381 3382 if (ret) 3383 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3384 (state)?"enter":"exit"); 3385 3386 return ret; 3387 } 3388 3389 bool smu_mode1_reset_is_support(struct smu_context *smu) 3390 { 3391 bool ret = false; 3392 3393 if (!smu->pm_enabled) 3394 return false; 3395 3396 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3397 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3398 3399 return ret; 3400 } 3401 3402 bool smu_mode2_reset_is_support(struct smu_context *smu) 3403 { 3404 bool ret = false; 3405 3406 if (!smu->pm_enabled) 3407 return false; 3408 3409 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3410 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3411 3412 return ret; 3413 } 3414 3415 int smu_mode1_reset(struct smu_context *smu) 3416 { 3417 int ret = 0; 3418 3419 if (!smu->pm_enabled) 3420 return -EOPNOTSUPP; 3421 3422 if (smu->ppt_funcs->mode1_reset) 3423 ret = smu->ppt_funcs->mode1_reset(smu); 3424 3425 return ret; 3426 } 3427 3428 static int smu_mode2_reset(void *handle) 3429 { 3430 struct smu_context *smu = handle; 3431 int ret = 0; 3432 3433 if (!smu->pm_enabled) 3434 return -EOPNOTSUPP; 3435 3436 if (smu->ppt_funcs->mode2_reset) 3437 ret = smu->ppt_funcs->mode2_reset(smu); 3438 3439 if (ret) 3440 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3441 3442 return ret; 3443 } 3444 3445 static int smu_enable_gfx_features(void *handle) 3446 { 3447 struct smu_context *smu = handle; 3448 int ret = 0; 3449 3450 if (!smu->pm_enabled) 3451 return -EOPNOTSUPP; 3452 3453 if (smu->ppt_funcs->enable_gfx_features) 3454 ret = smu->ppt_funcs->enable_gfx_features(smu); 3455 3456 if (ret) 3457 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3458 3459 return ret; 3460 } 3461 3462 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3463 struct pp_smu_nv_clock_table *max_clocks) 3464 { 3465 struct smu_context *smu = handle; 3466 int ret = 0; 3467 3468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3469 return -EOPNOTSUPP; 3470 3471 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3472 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3473 3474 return ret; 3475 } 3476 3477 static int smu_get_uclk_dpm_states(void *handle, 3478 unsigned int *clock_values_in_khz, 3479 unsigned int *num_states) 3480 { 3481 struct smu_context *smu = handle; 3482 int ret = 0; 3483 3484 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3485 return -EOPNOTSUPP; 3486 3487 if (smu->ppt_funcs->get_uclk_dpm_states) 3488 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3489 3490 return ret; 3491 } 3492 3493 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3494 { 3495 struct smu_context *smu = handle; 3496 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3497 3498 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3499 return -EOPNOTSUPP; 3500 3501 if (smu->ppt_funcs->get_current_power_state) 3502 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3503 3504 return pm_state; 3505 } 3506 3507 static int smu_get_dpm_clock_table(void *handle, 3508 struct dpm_clocks *clock_table) 3509 { 3510 struct smu_context *smu = handle; 3511 int ret = 0; 3512 3513 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3514 return -EOPNOTSUPP; 3515 3516 if (smu->ppt_funcs->get_dpm_clock_table) 3517 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3518 3519 return ret; 3520 } 3521 3522 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3523 { 3524 struct smu_context *smu = handle; 3525 3526 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3527 return -EOPNOTSUPP; 3528 3529 if (!smu->ppt_funcs->get_gpu_metrics) 3530 return -EOPNOTSUPP; 3531 3532 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3533 } 3534 3535 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3536 size_t size) 3537 { 3538 struct smu_context *smu = handle; 3539 3540 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3541 return -EOPNOTSUPP; 3542 3543 if (!smu->ppt_funcs->get_pm_metrics) 3544 return -EOPNOTSUPP; 3545 3546 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3547 } 3548 3549 static int smu_enable_mgpu_fan_boost(void *handle) 3550 { 3551 struct smu_context *smu = handle; 3552 int ret = 0; 3553 3554 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3555 return -EOPNOTSUPP; 3556 3557 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3558 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3559 3560 return ret; 3561 } 3562 3563 static int smu_gfx_state_change_set(void *handle, 3564 uint32_t state) 3565 { 3566 struct smu_context *smu = handle; 3567 int ret = 0; 3568 3569 if (smu->ppt_funcs->gfx_state_change_set) 3570 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3571 3572 return ret; 3573 } 3574 3575 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3576 { 3577 int ret = 0; 3578 3579 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3580 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3581 3582 return ret; 3583 } 3584 3585 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3586 { 3587 int ret = -EOPNOTSUPP; 3588 3589 if (smu->ppt_funcs && 3590 smu->ppt_funcs->get_ecc_info) 3591 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3592 3593 return ret; 3594 3595 } 3596 3597 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3598 { 3599 struct smu_context *smu = handle; 3600 struct smu_table_context *smu_table = &smu->smu_table; 3601 struct smu_table *memory_pool = &smu_table->memory_pool; 3602 3603 if (!addr || !size) 3604 return -EINVAL; 3605 3606 *addr = NULL; 3607 *size = 0; 3608 if (memory_pool->bo) { 3609 *addr = memory_pool->cpu_addr; 3610 *size = memory_pool->size; 3611 } 3612 3613 return 0; 3614 } 3615 3616 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3617 size_t *size) 3618 { 3619 size_t offset = *size; 3620 int level; 3621 3622 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3623 if (level == policy->current_level) 3624 offset += sysfs_emit_at(sysbuf, offset, 3625 "%d : %s*\n", level, 3626 policy->desc->get_desc(policy, level)); 3627 else 3628 offset += sysfs_emit_at(sysbuf, offset, 3629 "%d : %s\n", level, 3630 policy->desc->get_desc(policy, level)); 3631 } 3632 3633 *size = offset; 3634 } 3635 3636 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3637 enum pp_pm_policy p_type, char *sysbuf) 3638 { 3639 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3640 struct smu_dpm_policy_ctxt *policy_ctxt; 3641 struct smu_dpm_policy *dpm_policy; 3642 size_t offset = 0; 3643 3644 policy_ctxt = dpm_ctxt->dpm_policies; 3645 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3646 !policy_ctxt->policy_mask) 3647 return -EOPNOTSUPP; 3648 3649 if (p_type == PP_PM_POLICY_NONE) 3650 return -EINVAL; 3651 3652 dpm_policy = smu_get_pm_policy(smu, p_type); 3653 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3654 return -ENOENT; 3655 3656 if (!sysbuf) 3657 return -EINVAL; 3658 3659 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3660 3661 return offset; 3662 } 3663 3664 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3665 enum pp_pm_policy p_type) 3666 { 3667 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3668 struct smu_dpm_policy_ctxt *policy_ctxt; 3669 int i; 3670 3671 policy_ctxt = dpm_ctxt->dpm_policies; 3672 if (!policy_ctxt) 3673 return NULL; 3674 3675 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3676 if (policy_ctxt->policies[i].policy_type == p_type) 3677 return &policy_ctxt->policies[i]; 3678 } 3679 3680 return NULL; 3681 } 3682 3683 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3684 int level) 3685 { 3686 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3687 struct smu_dpm_policy *dpm_policy = NULL; 3688 struct smu_dpm_policy_ctxt *policy_ctxt; 3689 int ret = -EOPNOTSUPP; 3690 3691 policy_ctxt = dpm_ctxt->dpm_policies; 3692 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3693 !policy_ctxt->policy_mask) 3694 return ret; 3695 3696 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3697 return -EINVAL; 3698 3699 dpm_policy = smu_get_pm_policy(smu, p_type); 3700 3701 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3702 return ret; 3703 3704 if (dpm_policy->current_level == level) 3705 return 0; 3706 3707 ret = dpm_policy->set_policy(smu, level); 3708 3709 if (!ret) 3710 dpm_policy->current_level = level; 3711 3712 return ret; 3713 } 3714 3715 static const struct amd_pm_funcs swsmu_pm_funcs = { 3716 /* export for sysfs */ 3717 .set_fan_control_mode = smu_set_fan_control_mode, 3718 .get_fan_control_mode = smu_get_fan_control_mode, 3719 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3720 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3721 .force_clock_level = smu_force_ppclk_levels, 3722 .print_clock_levels = smu_print_ppclk_levels, 3723 .emit_clock_levels = smu_emit_ppclk_levels, 3724 .force_performance_level = smu_force_performance_level, 3725 .read_sensor = smu_read_sensor, 3726 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3727 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3728 .get_performance_level = smu_get_performance_level, 3729 .get_current_power_state = smu_get_current_power_state, 3730 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3731 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3732 .get_pp_num_states = smu_get_power_num_states, 3733 .get_pp_table = smu_sys_get_pp_table, 3734 .set_pp_table = smu_sys_set_pp_table, 3735 .switch_power_profile = smu_switch_power_profile, 3736 /* export to amdgpu */ 3737 .dispatch_tasks = smu_handle_dpm_task, 3738 .load_firmware = smu_load_microcode, 3739 .set_powergating_by_smu = smu_dpm_set_power_gate, 3740 .set_power_limit = smu_set_power_limit, 3741 .get_power_limit = smu_get_power_limit, 3742 .get_power_profile_mode = smu_get_power_profile_mode, 3743 .set_power_profile_mode = smu_set_power_profile_mode, 3744 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3745 .set_mp1_state = smu_set_mp1_state, 3746 .gfx_state_change_set = smu_gfx_state_change_set, 3747 /* export to DC */ 3748 .get_sclk = smu_get_sclk, 3749 .get_mclk = smu_get_mclk, 3750 .display_configuration_change = smu_display_configuration_change, 3751 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3752 .display_clock_voltage_request = smu_display_clock_voltage_request, 3753 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3754 .set_active_display_count = smu_set_display_count, 3755 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3756 .get_asic_baco_capability = smu_get_baco_capability, 3757 .set_asic_baco_state = smu_baco_set_state, 3758 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3759 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3760 .asic_reset_mode_2 = smu_mode2_reset, 3761 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3762 .set_df_cstate = smu_set_df_cstate, 3763 .set_xgmi_pstate = smu_set_xgmi_pstate, 3764 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3765 .get_pm_metrics = smu_sys_get_pm_metrics, 3766 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3767 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3768 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3769 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3770 .get_dpm_clock_table = smu_get_dpm_clock_table, 3771 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3772 }; 3773 3774 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3775 uint64_t event_arg) 3776 { 3777 int ret = -EINVAL; 3778 3779 if (smu->ppt_funcs->wait_for_event) 3780 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3781 3782 return ret; 3783 } 3784 3785 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3786 { 3787 3788 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3789 return -EOPNOTSUPP; 3790 3791 /* Confirm the buffer allocated is of correct size */ 3792 if (size != smu->stb_context.stb_buf_size) 3793 return -EINVAL; 3794 3795 /* 3796 * No need to lock smu mutex as we access STB directly through MMIO 3797 * and not going through SMU messaging route (for now at least). 3798 * For registers access rely on implementation internal locking. 3799 */ 3800 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3801 } 3802 3803 #if defined(CONFIG_DEBUG_FS) 3804 3805 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3806 { 3807 struct amdgpu_device *adev = filp->f_inode->i_private; 3808 struct smu_context *smu = adev->powerplay.pp_handle; 3809 unsigned char *buf; 3810 int r; 3811 3812 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3813 if (!buf) 3814 return -ENOMEM; 3815 3816 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3817 if (r) 3818 goto out; 3819 3820 filp->private_data = buf; 3821 3822 return 0; 3823 3824 out: 3825 kvfree(buf); 3826 return r; 3827 } 3828 3829 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3830 loff_t *pos) 3831 { 3832 struct amdgpu_device *adev = filp->f_inode->i_private; 3833 struct smu_context *smu = adev->powerplay.pp_handle; 3834 3835 3836 if (!filp->private_data) 3837 return -EINVAL; 3838 3839 return simple_read_from_buffer(buf, 3840 size, 3841 pos, filp->private_data, 3842 smu->stb_context.stb_buf_size); 3843 } 3844 3845 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3846 { 3847 kvfree(filp->private_data); 3848 filp->private_data = NULL; 3849 3850 return 0; 3851 } 3852 3853 /* 3854 * We have to define not only read method but also 3855 * open and release because .read takes up to PAGE_SIZE 3856 * data each time so and so is invoked multiple times. 3857 * We allocate the STB buffer in .open and release it 3858 * in .release 3859 */ 3860 static const struct file_operations smu_stb_debugfs_fops = { 3861 .owner = THIS_MODULE, 3862 .open = smu_stb_debugfs_open, 3863 .read = smu_stb_debugfs_read, 3864 .release = smu_stb_debugfs_release, 3865 .llseek = default_llseek, 3866 }; 3867 3868 #endif 3869 3870 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3871 { 3872 #if defined(CONFIG_DEBUG_FS) 3873 3874 struct smu_context *smu = adev->powerplay.pp_handle; 3875 3876 if (!smu || (!smu->stb_context.stb_buf_size)) 3877 return; 3878 3879 debugfs_create_file_size("amdgpu_smu_stb_dump", 3880 S_IRUSR, 3881 adev_to_drm(adev)->primary->debugfs_root, 3882 adev, 3883 &smu_stb_debugfs_fops, 3884 smu->stb_context.stb_buf_size); 3885 #endif 3886 } 3887 3888 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3889 { 3890 int ret = 0; 3891 3892 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3893 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3894 3895 return ret; 3896 } 3897 3898 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3899 { 3900 int ret = 0; 3901 3902 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3903 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3904 3905 return ret; 3906 } 3907 3908 int smu_send_rma_reason(struct smu_context *smu) 3909 { 3910 int ret = 0; 3911 3912 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3913 ret = smu->ppt_funcs->send_rma_reason(smu); 3914 3915 return ret; 3916 } 3917 3918 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 3919 { 3920 int ret = 0; 3921 3922 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 3923 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 3924 3925 return ret; 3926 } 3927