1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max); 144 145 return ret; 146 } 147 148 int smu_get_dpm_freq_range(struct smu_context *smu, 149 enum smu_clk_type clk_type, 150 uint32_t *min, 151 uint32_t *max) 152 { 153 int ret = -ENOTSUPP; 154 155 if (!min && !max) 156 return -EINVAL; 157 158 if (smu->ppt_funcs->get_dpm_ultimate_freq) 159 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 160 clk_type, 161 min, 162 max); 163 164 return ret; 165 } 166 167 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 168 { 169 int ret = 0; 170 struct amdgpu_device *adev = smu->adev; 171 172 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 173 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 174 if (ret) 175 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 176 } 177 return ret; 178 } 179 180 static u32 smu_get_mclk(void *handle, bool low) 181 { 182 struct smu_context *smu = handle; 183 uint32_t clk_freq; 184 int ret = 0; 185 186 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 187 low ? &clk_freq : NULL, 188 !low ? &clk_freq : NULL); 189 if (ret) 190 return 0; 191 return clk_freq * 100; 192 } 193 194 static u32 smu_get_sclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static int smu_set_gfx_imu_enable(struct smu_context *smu) 209 { 210 struct amdgpu_device *adev = smu->adev; 211 212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 213 return 0; 214 215 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 216 return 0; 217 218 return smu_set_gfx_power_up_by_imu(smu); 219 } 220 221 static bool is_vcn_enabled(struct amdgpu_device *adev) 222 { 223 int i; 224 225 for (i = 0; i < adev->num_ip_blocks; i++) { 226 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 227 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 228 !adev->ip_blocks[i].status.valid) 229 return false; 230 } 231 232 return true; 233 } 234 235 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 236 bool enable) 237 { 238 struct smu_power_context *smu_power = &smu->smu_power; 239 struct smu_power_gate *power_gate = &smu_power->power_gate; 240 struct amdgpu_device *adev = smu->adev; 241 int ret = 0; 242 243 /* 244 * don't poweron vcn/jpeg when they are skipped. 245 */ 246 if (!is_vcn_enabled(smu->adev)) 247 return 0; 248 249 if (!smu->ppt_funcs->dpm_set_vcn_enable) 250 return 0; 251 252 if (atomic_read(&power_gate->vcn_gated) ^ enable) 253 return 0; 254 255 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 256 if (!ret && !adev->enable_jpeg_test) 257 atomic_set(&power_gate->vcn_gated, !enable); 258 259 return ret; 260 } 261 262 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 263 bool enable) 264 { 265 struct smu_power_context *smu_power = &smu->smu_power; 266 struct smu_power_gate *power_gate = &smu_power->power_gate; 267 int ret = 0; 268 269 if (!is_vcn_enabled(smu->adev)) 270 return 0; 271 272 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 273 return 0; 274 275 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 276 return 0; 277 278 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 279 if (!ret) 280 atomic_set(&power_gate->jpeg_gated, !enable); 281 282 return ret; 283 } 284 285 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 286 bool enable) 287 { 288 struct smu_power_context *smu_power = &smu->smu_power; 289 struct smu_power_gate *power_gate = &smu_power->power_gate; 290 int ret = 0; 291 292 if (!smu->ppt_funcs->dpm_set_vpe_enable) 293 return 0; 294 295 if (atomic_read(&power_gate->vpe_gated) ^ enable) 296 return 0; 297 298 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 299 if (!ret) 300 atomic_set(&power_gate->vpe_gated, !enable); 301 302 return ret; 303 } 304 305 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 306 bool enable) 307 { 308 struct smu_power_context *smu_power = &smu->smu_power; 309 struct smu_power_gate *power_gate = &smu_power->power_gate; 310 int ret = 0; 311 312 if (!smu->adev->enable_umsch_mm) 313 return 0; 314 315 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 316 return 0; 317 318 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 319 return 0; 320 321 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 322 if (!ret) 323 atomic_set(&power_gate->umsch_mm_gated, !enable); 324 325 return ret; 326 } 327 328 /** 329 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 330 * 331 * @handle: smu_context pointer 332 * @block_type: the IP block to power gate/ungate 333 * @gate: to power gate if true, ungate otherwise 334 * 335 * This API uses no smu->mutex lock protection due to: 336 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 337 * This is guarded to be race condition free by the caller. 338 * 2. Or get called on user setting request of power_dpm_force_performance_level. 339 * Under this case, the smu->mutex lock protection is already enforced on 340 * the parent API smu_force_performance_level of the call path. 341 */ 342 static int smu_dpm_set_power_gate(void *handle, 343 uint32_t block_type, 344 bool gate) 345 { 346 struct smu_context *smu = handle; 347 int ret = 0; 348 349 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 350 dev_WARN(smu->adev->dev, 351 "SMU uninitialized but power %s requested for %u!\n", 352 gate ? "gate" : "ungate", block_type); 353 return -EOPNOTSUPP; 354 } 355 356 switch (block_type) { 357 /* 358 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 359 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 360 */ 361 case AMD_IP_BLOCK_TYPE_UVD: 362 case AMD_IP_BLOCK_TYPE_VCN: 363 ret = smu_dpm_set_vcn_enable(smu, !gate); 364 if (ret) 365 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 366 gate ? "gate" : "ungate"); 367 break; 368 case AMD_IP_BLOCK_TYPE_GFX: 369 ret = smu_gfx_off_control(smu, gate); 370 if (ret) 371 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 372 gate ? "enable" : "disable"); 373 break; 374 case AMD_IP_BLOCK_TYPE_SDMA: 375 ret = smu_powergate_sdma(smu, gate); 376 if (ret) 377 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 378 gate ? "gate" : "ungate"); 379 break; 380 case AMD_IP_BLOCK_TYPE_JPEG: 381 ret = smu_dpm_set_jpeg_enable(smu, !gate); 382 if (ret) 383 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 384 gate ? "gate" : "ungate"); 385 break; 386 case AMD_IP_BLOCK_TYPE_VPE: 387 ret = smu_dpm_set_vpe_enable(smu, !gate); 388 if (ret) 389 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 390 gate ? "gate" : "ungate"); 391 break; 392 default: 393 dev_err(smu->adev->dev, "Unsupported block type!\n"); 394 return -EINVAL; 395 } 396 397 return ret; 398 } 399 400 /** 401 * smu_set_user_clk_dependencies - set user profile clock dependencies 402 * 403 * @smu: smu_context pointer 404 * @clk: enum smu_clk_type type 405 * 406 * Enable/Disable the clock dependency for the @clk type. 407 */ 408 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 409 { 410 if (smu->adev->in_suspend) 411 return; 412 413 if (clk == SMU_MCLK) { 414 smu->user_dpm_profile.clk_dependency = 0; 415 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 416 } else if (clk == SMU_FCLK) { 417 /* MCLK takes precedence over FCLK */ 418 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 419 return; 420 421 smu->user_dpm_profile.clk_dependency = 0; 422 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 423 } else if (clk == SMU_SOCCLK) { 424 /* MCLK takes precedence over SOCCLK */ 425 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 426 return; 427 428 smu->user_dpm_profile.clk_dependency = 0; 429 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 430 } else 431 /* Add clk dependencies here, if any */ 432 return; 433 } 434 435 /** 436 * smu_restore_dpm_user_profile - reinstate user dpm profile 437 * 438 * @smu: smu_context pointer 439 * 440 * Restore the saved user power configurations include power limit, 441 * clock frequencies, fan control mode and fan speed. 442 */ 443 static void smu_restore_dpm_user_profile(struct smu_context *smu) 444 { 445 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 446 int ret = 0; 447 448 if (!smu->adev->in_suspend) 449 return; 450 451 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 452 return; 453 454 /* Enable restore flag */ 455 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 456 457 /* set the user dpm power limit */ 458 if (smu->user_dpm_profile.power_limit) { 459 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 460 if (ret) 461 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 462 } 463 464 /* set the user dpm clock configurations */ 465 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 466 enum smu_clk_type clk_type; 467 468 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 469 /* 470 * Iterate over smu clk type and force the saved user clk 471 * configs, skip if clock dependency is enabled 472 */ 473 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 474 smu->user_dpm_profile.clk_mask[clk_type]) { 475 ret = smu_force_smuclk_levels(smu, clk_type, 476 smu->user_dpm_profile.clk_mask[clk_type]); 477 if (ret) 478 dev_err(smu->adev->dev, 479 "Failed to set clock type = %d\n", clk_type); 480 } 481 } 482 } 483 484 /* set the user dpm fan configurations */ 485 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 486 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 487 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 488 if (ret != -EOPNOTSUPP) { 489 smu->user_dpm_profile.fan_speed_pwm = 0; 490 smu->user_dpm_profile.fan_speed_rpm = 0; 491 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 492 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 493 } 494 495 if (smu->user_dpm_profile.fan_speed_pwm) { 496 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 497 if (ret != -EOPNOTSUPP) 498 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 499 } 500 501 if (smu->user_dpm_profile.fan_speed_rpm) { 502 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 503 if (ret != -EOPNOTSUPP) 504 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 505 } 506 } 507 508 /* Restore user customized OD settings */ 509 if (smu->user_dpm_profile.user_od) { 510 if (smu->ppt_funcs->restore_user_od_settings) { 511 ret = smu->ppt_funcs->restore_user_od_settings(smu); 512 if (ret) 513 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 514 } 515 } 516 517 /* Disable restore flag */ 518 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 519 } 520 521 static int smu_get_power_num_states(void *handle, 522 struct pp_states_info *state_info) 523 { 524 if (!state_info) 525 return -EINVAL; 526 527 /* not support power state */ 528 memset(state_info, 0, sizeof(struct pp_states_info)); 529 state_info->nums = 1; 530 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 531 532 return 0; 533 } 534 535 bool is_support_sw_smu(struct amdgpu_device *adev) 536 { 537 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 538 if (adev->asic_type == CHIP_VEGA20) 539 return false; 540 541 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 542 return true; 543 544 return false; 545 } 546 547 bool is_support_cclk_dpm(struct amdgpu_device *adev) 548 { 549 struct smu_context *smu = adev->powerplay.pp_handle; 550 551 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 552 return false; 553 554 return true; 555 } 556 557 558 static int smu_sys_get_pp_table(void *handle, 559 char **table) 560 { 561 struct smu_context *smu = handle; 562 struct smu_table_context *smu_table = &smu->smu_table; 563 564 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 565 return -EOPNOTSUPP; 566 567 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 568 return -EINVAL; 569 570 if (smu_table->hardcode_pptable) 571 *table = smu_table->hardcode_pptable; 572 else 573 *table = smu_table->power_play_table; 574 575 return smu_table->power_play_table_size; 576 } 577 578 static int smu_sys_set_pp_table(void *handle, 579 const char *buf, 580 size_t size) 581 { 582 struct smu_context *smu = handle; 583 struct smu_table_context *smu_table = &smu->smu_table; 584 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 585 int ret = 0; 586 587 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 588 return -EOPNOTSUPP; 589 590 if (header->usStructureSize != size) { 591 dev_err(smu->adev->dev, "pp table size not matched !\n"); 592 return -EIO; 593 } 594 595 if (!smu_table->hardcode_pptable) { 596 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 597 if (!smu_table->hardcode_pptable) 598 return -ENOMEM; 599 } 600 601 memcpy(smu_table->hardcode_pptable, buf, size); 602 smu_table->power_play_table = smu_table->hardcode_pptable; 603 smu_table->power_play_table_size = size; 604 605 /* 606 * Special hw_fini action(for Navi1x, the DPMs disablement will be 607 * skipped) may be needed for custom pptable uploading. 608 */ 609 smu->uploading_custom_pp_table = true; 610 611 ret = smu_reset(smu); 612 if (ret) 613 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 614 615 smu->uploading_custom_pp_table = false; 616 617 return ret; 618 } 619 620 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 621 { 622 struct smu_feature *feature = &smu->smu_feature; 623 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 624 int ret = 0; 625 626 /* 627 * With SCPM enabled, the allowed featuremasks setting(via 628 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 629 * That means there is no way to let PMFW knows the settings below. 630 * Thus, we just assume all the features are allowed under 631 * such scenario. 632 */ 633 if (smu->adev->scpm_enabled) { 634 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 635 return 0; 636 } 637 638 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 639 640 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 641 SMU_FEATURE_MAX/32); 642 if (ret) 643 return ret; 644 645 bitmap_or(feature->allowed, feature->allowed, 646 (unsigned long *)allowed_feature_mask, 647 feature->feature_num); 648 649 return ret; 650 } 651 652 static int smu_set_funcs(struct amdgpu_device *adev) 653 { 654 struct smu_context *smu = adev->powerplay.pp_handle; 655 656 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 657 smu->od_enabled = true; 658 659 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 660 case IP_VERSION(11, 0, 0): 661 case IP_VERSION(11, 0, 5): 662 case IP_VERSION(11, 0, 9): 663 navi10_set_ppt_funcs(smu); 664 break; 665 case IP_VERSION(11, 0, 7): 666 case IP_VERSION(11, 0, 11): 667 case IP_VERSION(11, 0, 12): 668 case IP_VERSION(11, 0, 13): 669 sienna_cichlid_set_ppt_funcs(smu); 670 break; 671 case IP_VERSION(12, 0, 0): 672 case IP_VERSION(12, 0, 1): 673 renoir_set_ppt_funcs(smu); 674 break; 675 case IP_VERSION(11, 5, 0): 676 vangogh_set_ppt_funcs(smu); 677 break; 678 case IP_VERSION(13, 0, 1): 679 case IP_VERSION(13, 0, 3): 680 case IP_VERSION(13, 0, 8): 681 yellow_carp_set_ppt_funcs(smu); 682 break; 683 case IP_VERSION(13, 0, 4): 684 case IP_VERSION(13, 0, 11): 685 smu_v13_0_4_set_ppt_funcs(smu); 686 break; 687 case IP_VERSION(13, 0, 5): 688 smu_v13_0_5_set_ppt_funcs(smu); 689 break; 690 case IP_VERSION(11, 0, 8): 691 cyan_skillfish_set_ppt_funcs(smu); 692 break; 693 case IP_VERSION(11, 0, 2): 694 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 695 arcturus_set_ppt_funcs(smu); 696 /* OD is not supported on Arcturus */ 697 smu->od_enabled = false; 698 break; 699 case IP_VERSION(13, 0, 2): 700 aldebaran_set_ppt_funcs(smu); 701 /* Enable pp_od_clk_voltage node */ 702 smu->od_enabled = true; 703 break; 704 case IP_VERSION(13, 0, 0): 705 case IP_VERSION(13, 0, 10): 706 smu_v13_0_0_set_ppt_funcs(smu); 707 break; 708 case IP_VERSION(13, 0, 6): 709 case IP_VERSION(13, 0, 14): 710 smu_v13_0_6_set_ppt_funcs(smu); 711 /* Enable pp_od_clk_voltage node */ 712 smu->od_enabled = true; 713 break; 714 case IP_VERSION(13, 0, 7): 715 smu_v13_0_7_set_ppt_funcs(smu); 716 break; 717 case IP_VERSION(14, 0, 0): 718 case IP_VERSION(14, 0, 1): 719 smu_v14_0_0_set_ppt_funcs(smu); 720 break; 721 case IP_VERSION(14, 0, 2): 722 case IP_VERSION(14, 0, 3): 723 smu_v14_0_2_set_ppt_funcs(smu); 724 break; 725 default: 726 return -EINVAL; 727 } 728 729 return 0; 730 } 731 732 static int smu_early_init(void *handle) 733 { 734 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 735 struct smu_context *smu; 736 int r; 737 738 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 739 if (!smu) 740 return -ENOMEM; 741 742 smu->adev = adev; 743 smu->pm_enabled = !!amdgpu_dpm; 744 smu->is_apu = false; 745 smu->smu_baco.state = SMU_BACO_STATE_NONE; 746 smu->smu_baco.platform_support = false; 747 smu->smu_baco.maco_support = false; 748 smu->user_dpm_profile.fan_mode = -1; 749 750 mutex_init(&smu->message_lock); 751 752 adev->powerplay.pp_handle = smu; 753 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 754 755 r = smu_set_funcs(adev); 756 if (r) 757 return r; 758 return smu_init_microcode(smu); 759 } 760 761 static int smu_set_default_dpm_table(struct smu_context *smu) 762 { 763 struct amdgpu_device *adev = smu->adev; 764 struct smu_power_context *smu_power = &smu->smu_power; 765 struct smu_power_gate *power_gate = &smu_power->power_gate; 766 int vcn_gate, jpeg_gate; 767 int ret = 0; 768 769 if (!smu->ppt_funcs->set_default_dpm_table) 770 return 0; 771 772 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 773 vcn_gate = atomic_read(&power_gate->vcn_gated); 774 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 775 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 776 777 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 778 ret = smu_dpm_set_vcn_enable(smu, true); 779 if (ret) 780 return ret; 781 } 782 783 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 784 ret = smu_dpm_set_jpeg_enable(smu, true); 785 if (ret) 786 goto err_out; 787 } 788 789 ret = smu->ppt_funcs->set_default_dpm_table(smu); 790 if (ret) 791 dev_err(smu->adev->dev, 792 "Failed to setup default dpm clock tables!\n"); 793 794 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 795 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 796 err_out: 797 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 798 smu_dpm_set_vcn_enable(smu, !vcn_gate); 799 800 return ret; 801 } 802 803 static int smu_apply_default_config_table_settings(struct smu_context *smu) 804 { 805 struct amdgpu_device *adev = smu->adev; 806 int ret = 0; 807 808 ret = smu_get_default_config_table_settings(smu, 809 &adev->pm.config_table); 810 if (ret) 811 return ret; 812 813 return smu_set_config_table(smu, &adev->pm.config_table); 814 } 815 816 static int smu_late_init(void *handle) 817 { 818 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 819 struct smu_context *smu = adev->powerplay.pp_handle; 820 int ret = 0; 821 822 smu_set_fine_grain_gfx_freq_parameters(smu); 823 824 if (!smu->pm_enabled) 825 return 0; 826 827 ret = smu_post_init(smu); 828 if (ret) { 829 dev_err(adev->dev, "Failed to post smu init!\n"); 830 return ret; 831 } 832 833 /* 834 * Explicitly notify PMFW the power mode the system in. Since 835 * the PMFW may boot the ASIC with a different mode. 836 * For those supporting ACDC switch via gpio, PMFW will 837 * handle the switch automatically. Driver involvement 838 * is unnecessary. 839 */ 840 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 841 smu_set_ac_dc(smu); 842 843 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 844 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 845 return 0; 846 847 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 848 ret = smu_set_default_od_settings(smu); 849 if (ret) { 850 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 851 return ret; 852 } 853 } 854 855 ret = smu_populate_umd_state_clk(smu); 856 if (ret) { 857 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 858 return ret; 859 } 860 861 ret = smu_get_asic_power_limits(smu, 862 &smu->current_power_limit, 863 &smu->default_power_limit, 864 &smu->max_power_limit, 865 &smu->min_power_limit); 866 if (ret) { 867 dev_err(adev->dev, "Failed to get asic power limits!\n"); 868 return ret; 869 } 870 871 if (!amdgpu_sriov_vf(adev)) 872 smu_get_unique_id(smu); 873 874 smu_get_fan_parameters(smu); 875 876 smu_handle_task(smu, 877 smu->smu_dpm.dpm_level, 878 AMD_PP_TASK_COMPLETE_INIT); 879 880 ret = smu_apply_default_config_table_settings(smu); 881 if (ret && (ret != -EOPNOTSUPP)) { 882 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 883 return ret; 884 } 885 886 smu_restore_dpm_user_profile(smu); 887 888 return 0; 889 } 890 891 static int smu_init_fb_allocations(struct smu_context *smu) 892 { 893 struct amdgpu_device *adev = smu->adev; 894 struct smu_table_context *smu_table = &smu->smu_table; 895 struct smu_table *tables = smu_table->tables; 896 struct smu_table *driver_table = &(smu_table->driver_table); 897 uint32_t max_table_size = 0; 898 int ret, i; 899 900 /* VRAM allocation for tool table */ 901 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 902 ret = amdgpu_bo_create_kernel(adev, 903 tables[SMU_TABLE_PMSTATUSLOG].size, 904 tables[SMU_TABLE_PMSTATUSLOG].align, 905 tables[SMU_TABLE_PMSTATUSLOG].domain, 906 &tables[SMU_TABLE_PMSTATUSLOG].bo, 907 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 908 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 909 if (ret) { 910 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 911 return ret; 912 } 913 } 914 915 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 916 /* VRAM allocation for driver table */ 917 for (i = 0; i < SMU_TABLE_COUNT; i++) { 918 if (tables[i].size == 0) 919 continue; 920 921 /* If one of the tables has VRAM domain restriction, keep it in 922 * VRAM 923 */ 924 if ((tables[i].domain & 925 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 926 AMDGPU_GEM_DOMAIN_VRAM) 927 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 928 929 if (i == SMU_TABLE_PMSTATUSLOG) 930 continue; 931 932 if (max_table_size < tables[i].size) 933 max_table_size = tables[i].size; 934 } 935 936 driver_table->size = max_table_size; 937 driver_table->align = PAGE_SIZE; 938 939 ret = amdgpu_bo_create_kernel(adev, 940 driver_table->size, 941 driver_table->align, 942 driver_table->domain, 943 &driver_table->bo, 944 &driver_table->mc_address, 945 &driver_table->cpu_addr); 946 if (ret) { 947 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 948 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 949 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 950 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 951 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 952 } 953 954 return ret; 955 } 956 957 static int smu_fini_fb_allocations(struct smu_context *smu) 958 { 959 struct smu_table_context *smu_table = &smu->smu_table; 960 struct smu_table *tables = smu_table->tables; 961 struct smu_table *driver_table = &(smu_table->driver_table); 962 963 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 964 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 965 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 966 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 967 968 amdgpu_bo_free_kernel(&driver_table->bo, 969 &driver_table->mc_address, 970 &driver_table->cpu_addr); 971 972 return 0; 973 } 974 975 /** 976 * smu_alloc_memory_pool - allocate memory pool in the system memory 977 * 978 * @smu: amdgpu_device pointer 979 * 980 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 981 * and DramLogSetDramAddr can notify it changed. 982 * 983 * Returns 0 on success, error on failure. 984 */ 985 static int smu_alloc_memory_pool(struct smu_context *smu) 986 { 987 struct amdgpu_device *adev = smu->adev; 988 struct smu_table_context *smu_table = &smu->smu_table; 989 struct smu_table *memory_pool = &smu_table->memory_pool; 990 uint64_t pool_size = smu->pool_size; 991 int ret = 0; 992 993 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 994 return ret; 995 996 memory_pool->size = pool_size; 997 memory_pool->align = PAGE_SIZE; 998 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 999 1000 switch (pool_size) { 1001 case SMU_MEMORY_POOL_SIZE_256_MB: 1002 case SMU_MEMORY_POOL_SIZE_512_MB: 1003 case SMU_MEMORY_POOL_SIZE_1_GB: 1004 case SMU_MEMORY_POOL_SIZE_2_GB: 1005 ret = amdgpu_bo_create_kernel(adev, 1006 memory_pool->size, 1007 memory_pool->align, 1008 memory_pool->domain, 1009 &memory_pool->bo, 1010 &memory_pool->mc_address, 1011 &memory_pool->cpu_addr); 1012 if (ret) 1013 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1014 break; 1015 default: 1016 break; 1017 } 1018 1019 return ret; 1020 } 1021 1022 static int smu_free_memory_pool(struct smu_context *smu) 1023 { 1024 struct smu_table_context *smu_table = &smu->smu_table; 1025 struct smu_table *memory_pool = &smu_table->memory_pool; 1026 1027 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1028 return 0; 1029 1030 amdgpu_bo_free_kernel(&memory_pool->bo, 1031 &memory_pool->mc_address, 1032 &memory_pool->cpu_addr); 1033 1034 memset(memory_pool, 0, sizeof(struct smu_table)); 1035 1036 return 0; 1037 } 1038 1039 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1040 { 1041 struct smu_table_context *smu_table = &smu->smu_table; 1042 struct smu_table *dummy_read_1_table = 1043 &smu_table->dummy_read_1_table; 1044 struct amdgpu_device *adev = smu->adev; 1045 int ret = 0; 1046 1047 if (!dummy_read_1_table->size) 1048 return 0; 1049 1050 ret = amdgpu_bo_create_kernel(adev, 1051 dummy_read_1_table->size, 1052 dummy_read_1_table->align, 1053 dummy_read_1_table->domain, 1054 &dummy_read_1_table->bo, 1055 &dummy_read_1_table->mc_address, 1056 &dummy_read_1_table->cpu_addr); 1057 if (ret) 1058 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1059 1060 return ret; 1061 } 1062 1063 static void smu_free_dummy_read_table(struct smu_context *smu) 1064 { 1065 struct smu_table_context *smu_table = &smu->smu_table; 1066 struct smu_table *dummy_read_1_table = 1067 &smu_table->dummy_read_1_table; 1068 1069 1070 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1071 &dummy_read_1_table->mc_address, 1072 &dummy_read_1_table->cpu_addr); 1073 1074 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1075 } 1076 1077 static int smu_smc_table_sw_init(struct smu_context *smu) 1078 { 1079 int ret; 1080 1081 /** 1082 * Create smu_table structure, and init smc tables such as 1083 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1084 */ 1085 ret = smu_init_smc_tables(smu); 1086 if (ret) { 1087 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1088 return ret; 1089 } 1090 1091 /** 1092 * Create smu_power_context structure, and allocate smu_dpm_context and 1093 * context size to fill the smu_power_context data. 1094 */ 1095 ret = smu_init_power(smu); 1096 if (ret) { 1097 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1098 return ret; 1099 } 1100 1101 /* 1102 * allocate vram bos to store smc table contents. 1103 */ 1104 ret = smu_init_fb_allocations(smu); 1105 if (ret) 1106 return ret; 1107 1108 ret = smu_alloc_memory_pool(smu); 1109 if (ret) 1110 return ret; 1111 1112 ret = smu_alloc_dummy_read_table(smu); 1113 if (ret) 1114 return ret; 1115 1116 ret = smu_i2c_init(smu); 1117 if (ret) 1118 return ret; 1119 1120 return 0; 1121 } 1122 1123 static int smu_smc_table_sw_fini(struct smu_context *smu) 1124 { 1125 int ret; 1126 1127 smu_i2c_fini(smu); 1128 1129 smu_free_dummy_read_table(smu); 1130 1131 ret = smu_free_memory_pool(smu); 1132 if (ret) 1133 return ret; 1134 1135 ret = smu_fini_fb_allocations(smu); 1136 if (ret) 1137 return ret; 1138 1139 ret = smu_fini_power(smu); 1140 if (ret) { 1141 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1142 return ret; 1143 } 1144 1145 ret = smu_fini_smc_tables(smu); 1146 if (ret) { 1147 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1148 return ret; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static void smu_throttling_logging_work_fn(struct work_struct *work) 1155 { 1156 struct smu_context *smu = container_of(work, struct smu_context, 1157 throttling_logging_work); 1158 1159 smu_log_thermal_throttling(smu); 1160 } 1161 1162 static void smu_interrupt_work_fn(struct work_struct *work) 1163 { 1164 struct smu_context *smu = container_of(work, struct smu_context, 1165 interrupt_work); 1166 1167 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1168 smu->ppt_funcs->interrupt_work(smu); 1169 } 1170 1171 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1172 { 1173 struct smu_context *smu = 1174 container_of(work, struct smu_context, swctf_delayed_work.work); 1175 struct smu_temperature_range *range = 1176 &smu->thermal_range; 1177 struct amdgpu_device *adev = smu->adev; 1178 uint32_t hotspot_tmp, size; 1179 1180 /* 1181 * If the hotspot temperature is confirmed as below SW CTF setting point 1182 * after the delay enforced, nothing will be done. 1183 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1184 */ 1185 if (range->software_shutdown_temp && 1186 smu->ppt_funcs->read_sensor && 1187 !smu->ppt_funcs->read_sensor(smu, 1188 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1189 &hotspot_tmp, 1190 &size) && 1191 hotspot_tmp / 1000 < range->software_shutdown_temp) 1192 return; 1193 1194 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1195 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1196 orderly_poweroff(true); 1197 } 1198 1199 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1200 { 1201 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1202 struct smu_dpm_policy_ctxt *policy_ctxt; 1203 struct smu_dpm_policy *policy; 1204 1205 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1206 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1207 if (policy) 1208 policy->current_level = XGMI_PLPD_DEFAULT; 1209 return; 1210 } 1211 1212 /* PMFW put PLPD into default policy after enabling the feature */ 1213 if (smu_feature_is_enabled(smu, 1214 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1215 if (policy) 1216 policy->current_level = XGMI_PLPD_DEFAULT; 1217 } else { 1218 policy_ctxt = dpm_ctxt->dpm_policies; 1219 if (policy_ctxt) 1220 policy_ctxt->policy_mask &= 1221 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1222 } 1223 } 1224 1225 static int smu_sw_init(void *handle) 1226 { 1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1228 struct smu_context *smu = adev->powerplay.pp_handle; 1229 int ret; 1230 1231 smu->pool_size = adev->pm.smu_prv_buffer_size; 1232 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1233 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1234 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1235 1236 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1237 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1238 atomic64_set(&smu->throttle_int_counter, 0); 1239 smu->watermarks_bitmap = 0; 1240 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1241 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1242 1243 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1244 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1245 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1246 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1247 1248 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1249 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1250 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1251 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1252 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1253 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1254 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1255 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1256 1257 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1258 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1259 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1260 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1261 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1262 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1263 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1264 smu->display_config = &adev->pm.pm_display_cfg; 1265 1266 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1267 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1268 1269 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1270 smu_swctf_delayed_work_handler); 1271 1272 ret = smu_smc_table_sw_init(smu); 1273 if (ret) { 1274 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1275 return ret; 1276 } 1277 1278 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1279 ret = smu_get_vbios_bootup_values(smu); 1280 if (ret) { 1281 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1282 return ret; 1283 } 1284 1285 ret = smu_init_pptable_microcode(smu); 1286 if (ret) { 1287 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1288 return ret; 1289 } 1290 1291 ret = smu_register_irq_handler(smu); 1292 if (ret) { 1293 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1294 return ret; 1295 } 1296 1297 /* If there is no way to query fan control mode, fan control is not supported */ 1298 if (!smu->ppt_funcs->get_fan_control_mode) 1299 smu->adev->pm.no_fan = true; 1300 1301 return 0; 1302 } 1303 1304 static int smu_sw_fini(void *handle) 1305 { 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 struct smu_context *smu = adev->powerplay.pp_handle; 1308 int ret; 1309 1310 ret = smu_smc_table_sw_fini(smu); 1311 if (ret) { 1312 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1313 return ret; 1314 } 1315 1316 smu_fini_microcode(smu); 1317 1318 return 0; 1319 } 1320 1321 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1322 { 1323 struct amdgpu_device *adev = smu->adev; 1324 struct smu_temperature_range *range = 1325 &smu->thermal_range; 1326 int ret = 0; 1327 1328 if (!smu->ppt_funcs->get_thermal_temperature_range) 1329 return 0; 1330 1331 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1332 if (ret) 1333 return ret; 1334 1335 adev->pm.dpm.thermal.min_temp = range->min; 1336 adev->pm.dpm.thermal.max_temp = range->max; 1337 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1338 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1339 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1340 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1341 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1342 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1343 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1344 1345 return ret; 1346 } 1347 1348 /** 1349 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1350 * 1351 * @smu: smu_context pointer 1352 * 1353 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1354 * Returns 0 on success, error on failure. 1355 */ 1356 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1357 { 1358 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1359 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1360 struct amdgpu_device *adev = smu->adev; 1361 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1362 uint64_t start, end; 1363 int ret, i, j; 1364 1365 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1366 if (ret) { 1367 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1368 return ret; 1369 } 1370 1371 /* 1372 * The exclusion ranges array we got might be filled with holes and duplicate 1373 * entries. For example: 1374 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1375 * We need to do some sortups to eliminate those holes and duplicate entries. 1376 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1377 */ 1378 for (i = 0; i < num_of_wbrf_ranges; i++) { 1379 start = wifi_bands[i].start; 1380 end = wifi_bands[i].end; 1381 1382 /* get the last valid entry to fill the intermediate hole */ 1383 if (!start && !end) { 1384 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1385 if (wifi_bands[j].start && wifi_bands[j].end) 1386 break; 1387 1388 /* no valid entry left */ 1389 if (j <= i) 1390 break; 1391 1392 start = wifi_bands[i].start = wifi_bands[j].start; 1393 end = wifi_bands[i].end = wifi_bands[j].end; 1394 wifi_bands[j].start = 0; 1395 wifi_bands[j].end = 0; 1396 num_of_wbrf_ranges = j; 1397 } 1398 1399 /* eliminate duplicate entries */ 1400 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1401 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1402 wifi_bands[j].start = 0; 1403 wifi_bands[j].end = 0; 1404 } 1405 } 1406 } 1407 1408 /* Send the sorted wifi_bands to PMFW */ 1409 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1410 /* Try to set the wifi_bands again */ 1411 if (unlikely(ret == -EBUSY)) { 1412 mdelay(5); 1413 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1414 } 1415 1416 return ret; 1417 } 1418 1419 /** 1420 * smu_wbrf_event_handler - handle notify events 1421 * 1422 * @nb: notifier block 1423 * @action: event type 1424 * @_arg: event data 1425 * 1426 * Calls relevant amdgpu function in response to wbrf event 1427 * notification from kernel. 1428 */ 1429 static int smu_wbrf_event_handler(struct notifier_block *nb, 1430 unsigned long action, void *_arg) 1431 { 1432 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1433 1434 switch (action) { 1435 case WBRF_CHANGED: 1436 schedule_delayed_work(&smu->wbrf_delayed_work, 1437 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1438 break; 1439 default: 1440 return NOTIFY_DONE; 1441 } 1442 1443 return NOTIFY_OK; 1444 } 1445 1446 /** 1447 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1448 * 1449 * @work: struct work_struct pointer 1450 * 1451 * Flood is over and driver will consume the latest exclusion ranges. 1452 */ 1453 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1454 { 1455 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1456 1457 smu_wbrf_handle_exclusion_ranges(smu); 1458 } 1459 1460 /** 1461 * smu_wbrf_support_check - check wbrf support 1462 * 1463 * @smu: smu_context pointer 1464 * 1465 * Verifies the ACPI interface whether wbrf is supported. 1466 */ 1467 static void smu_wbrf_support_check(struct smu_context *smu) 1468 { 1469 struct amdgpu_device *adev = smu->adev; 1470 1471 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1472 acpi_amd_wbrf_supported_consumer(adev->dev); 1473 1474 if (smu->wbrf_supported) 1475 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1476 } 1477 1478 /** 1479 * smu_wbrf_init - init driver wbrf support 1480 * 1481 * @smu: smu_context pointer 1482 * 1483 * Verifies the AMD ACPI interfaces and registers with the wbrf 1484 * notifier chain if wbrf feature is supported. 1485 * Returns 0 on success, error on failure. 1486 */ 1487 static int smu_wbrf_init(struct smu_context *smu) 1488 { 1489 int ret; 1490 1491 if (!smu->wbrf_supported) 1492 return 0; 1493 1494 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1495 1496 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1497 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1498 if (ret) 1499 return ret; 1500 1501 /* 1502 * Some wifiband exclusion ranges may be already there 1503 * before our driver loaded. To make sure our driver 1504 * is awared of those exclusion ranges. 1505 */ 1506 schedule_delayed_work(&smu->wbrf_delayed_work, 1507 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1508 1509 return 0; 1510 } 1511 1512 /** 1513 * smu_wbrf_fini - tear down driver wbrf support 1514 * 1515 * @smu: smu_context pointer 1516 * 1517 * Unregisters with the wbrf notifier chain. 1518 */ 1519 static void smu_wbrf_fini(struct smu_context *smu) 1520 { 1521 if (!smu->wbrf_supported) 1522 return; 1523 1524 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1525 1526 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1527 } 1528 1529 static int smu_smc_hw_setup(struct smu_context *smu) 1530 { 1531 struct smu_feature *feature = &smu->smu_feature; 1532 struct amdgpu_device *adev = smu->adev; 1533 uint8_t pcie_gen = 0, pcie_width = 0; 1534 uint64_t features_supported; 1535 int ret = 0; 1536 1537 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1538 case IP_VERSION(11, 0, 7): 1539 case IP_VERSION(11, 0, 11): 1540 case IP_VERSION(11, 5, 0): 1541 case IP_VERSION(11, 0, 12): 1542 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1543 dev_info(adev->dev, "dpm has been enabled\n"); 1544 ret = smu_system_features_control(smu, true); 1545 if (ret) 1546 dev_err(adev->dev, "Failed system features control!\n"); 1547 return ret; 1548 } 1549 break; 1550 default: 1551 break; 1552 } 1553 1554 ret = smu_init_display_count(smu, 0); 1555 if (ret) { 1556 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1557 return ret; 1558 } 1559 1560 ret = smu_set_driver_table_location(smu); 1561 if (ret) { 1562 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1563 return ret; 1564 } 1565 1566 /* 1567 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1568 */ 1569 ret = smu_set_tool_table_location(smu); 1570 if (ret) { 1571 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1572 return ret; 1573 } 1574 1575 /* 1576 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1577 * pool location. 1578 */ 1579 ret = smu_notify_memory_pool_location(smu); 1580 if (ret) { 1581 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1582 return ret; 1583 } 1584 1585 /* 1586 * It is assumed the pptable used before runpm is same as 1587 * the one used afterwards. Thus, we can reuse the stored 1588 * copy and do not need to resetup the pptable again. 1589 */ 1590 if (!adev->in_runpm) { 1591 ret = smu_setup_pptable(smu); 1592 if (ret) { 1593 dev_err(adev->dev, "Failed to setup pptable!\n"); 1594 return ret; 1595 } 1596 } 1597 1598 /* smu_dump_pptable(smu); */ 1599 1600 /* 1601 * With SCPM enabled, PSP is responsible for the PPTable transferring 1602 * (to SMU). Driver involvement is not needed and permitted. 1603 */ 1604 if (!adev->scpm_enabled) { 1605 /* 1606 * Copy pptable bo in the vram to smc with SMU MSGs such as 1607 * SetDriverDramAddr and TransferTableDram2Smu. 1608 */ 1609 ret = smu_write_pptable(smu); 1610 if (ret) { 1611 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1612 return ret; 1613 } 1614 } 1615 1616 /* issue Run*Btc msg */ 1617 ret = smu_run_btc(smu); 1618 if (ret) 1619 return ret; 1620 1621 /* Enable UclkShadow on wbrf supported */ 1622 if (smu->wbrf_supported) { 1623 ret = smu_enable_uclk_shadow(smu, true); 1624 if (ret) { 1625 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1626 return ret; 1627 } 1628 } 1629 1630 /* 1631 * With SCPM enabled, these actions(and relevant messages) are 1632 * not needed and permitted. 1633 */ 1634 if (!adev->scpm_enabled) { 1635 ret = smu_feature_set_allowed_mask(smu); 1636 if (ret) { 1637 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1638 return ret; 1639 } 1640 } 1641 1642 ret = smu_system_features_control(smu, true); 1643 if (ret) { 1644 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1645 return ret; 1646 } 1647 1648 smu_init_xgmi_plpd_mode(smu); 1649 1650 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1651 if (ret) { 1652 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1653 return ret; 1654 } 1655 bitmap_copy(feature->supported, 1656 (unsigned long *)&features_supported, 1657 feature->feature_num); 1658 1659 if (!smu_is_dpm_running(smu)) 1660 dev_info(adev->dev, "dpm has been disabled\n"); 1661 1662 /* 1663 * Set initialized values (get from vbios) to dpm tables context such as 1664 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1665 * type of clks. 1666 */ 1667 ret = smu_set_default_dpm_table(smu); 1668 if (ret) { 1669 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1670 return ret; 1671 } 1672 1673 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1674 pcie_gen = 3; 1675 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1676 pcie_gen = 2; 1677 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1678 pcie_gen = 1; 1679 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1680 pcie_gen = 0; 1681 1682 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1683 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1684 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1685 */ 1686 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1687 pcie_width = 6; 1688 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1689 pcie_width = 5; 1690 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1691 pcie_width = 4; 1692 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1693 pcie_width = 3; 1694 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1695 pcie_width = 2; 1696 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1697 pcie_width = 1; 1698 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1699 if (ret) { 1700 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1701 return ret; 1702 } 1703 1704 ret = smu_get_thermal_temperature_range(smu); 1705 if (ret) { 1706 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1707 return ret; 1708 } 1709 1710 ret = smu_enable_thermal_alert(smu); 1711 if (ret) { 1712 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1713 return ret; 1714 } 1715 1716 ret = smu_notify_display_change(smu); 1717 if (ret) { 1718 dev_err(adev->dev, "Failed to notify display change!\n"); 1719 return ret; 1720 } 1721 1722 /* 1723 * Set min deep sleep dce fclk with bootup value from vbios via 1724 * SetMinDeepSleepDcefclk MSG. 1725 */ 1726 ret = smu_set_min_dcef_deep_sleep(smu, 1727 smu->smu_table.boot_values.dcefclk / 100); 1728 if (ret) { 1729 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1730 return ret; 1731 } 1732 1733 /* Init wbrf support. Properly setup the notifier */ 1734 ret = smu_wbrf_init(smu); 1735 if (ret) 1736 dev_err(adev->dev, "Error during wbrf init call\n"); 1737 1738 return ret; 1739 } 1740 1741 static int smu_start_smc_engine(struct smu_context *smu) 1742 { 1743 struct amdgpu_device *adev = smu->adev; 1744 int ret = 0; 1745 1746 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1747 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1748 if (smu->ppt_funcs->load_microcode) { 1749 ret = smu->ppt_funcs->load_microcode(smu); 1750 if (ret) 1751 return ret; 1752 } 1753 } 1754 } 1755 1756 if (smu->ppt_funcs->check_fw_status) { 1757 ret = smu->ppt_funcs->check_fw_status(smu); 1758 if (ret) { 1759 dev_err(adev->dev, "SMC is not ready\n"); 1760 return ret; 1761 } 1762 } 1763 1764 /* 1765 * Send msg GetDriverIfVersion to check if the return value is equal 1766 * with DRIVER_IF_VERSION of smc header. 1767 */ 1768 ret = smu_check_fw_version(smu); 1769 if (ret) 1770 return ret; 1771 1772 return ret; 1773 } 1774 1775 static int smu_hw_init(void *handle) 1776 { 1777 int ret; 1778 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1779 struct smu_context *smu = adev->powerplay.pp_handle; 1780 1781 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1782 smu->pm_enabled = false; 1783 return 0; 1784 } 1785 1786 ret = smu_start_smc_engine(smu); 1787 if (ret) { 1788 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1789 return ret; 1790 } 1791 1792 /* 1793 * Check whether wbrf is supported. This needs to be done 1794 * before SMU setup starts since part of SMU configuration 1795 * relies on this. 1796 */ 1797 smu_wbrf_support_check(smu); 1798 1799 if (smu->is_apu) { 1800 ret = smu_set_gfx_imu_enable(smu); 1801 if (ret) 1802 return ret; 1803 smu_dpm_set_vcn_enable(smu, true); 1804 smu_dpm_set_jpeg_enable(smu, true); 1805 smu_dpm_set_vpe_enable(smu, true); 1806 smu_dpm_set_umsch_mm_enable(smu, true); 1807 smu_set_gfx_cgpg(smu, true); 1808 } 1809 1810 if (!smu->pm_enabled) 1811 return 0; 1812 1813 ret = smu_get_driver_allowed_feature_mask(smu); 1814 if (ret) 1815 return ret; 1816 1817 ret = smu_smc_hw_setup(smu); 1818 if (ret) { 1819 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1820 return ret; 1821 } 1822 1823 /* 1824 * Move maximum sustainable clock retrieving here considering 1825 * 1. It is not needed on resume(from S3). 1826 * 2. DAL settings come between .hw_init and .late_init of SMU. 1827 * And DAL needs to know the maximum sustainable clocks. Thus 1828 * it cannot be put in .late_init(). 1829 */ 1830 ret = smu_init_max_sustainable_clocks(smu); 1831 if (ret) { 1832 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1833 return ret; 1834 } 1835 1836 adev->pm.dpm_enabled = true; 1837 1838 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1839 1840 return 0; 1841 } 1842 1843 static int smu_disable_dpms(struct smu_context *smu) 1844 { 1845 struct amdgpu_device *adev = smu->adev; 1846 int ret = 0; 1847 bool use_baco = !smu->is_apu && 1848 ((amdgpu_in_reset(adev) && 1849 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1850 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1851 1852 /* 1853 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1854 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1855 */ 1856 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1857 case IP_VERSION(13, 0, 0): 1858 case IP_VERSION(13, 0, 7): 1859 case IP_VERSION(13, 0, 10): 1860 case IP_VERSION(14, 0, 2): 1861 case IP_VERSION(14, 0, 3): 1862 return 0; 1863 default: 1864 break; 1865 } 1866 1867 /* 1868 * For custom pptable uploading, skip the DPM features 1869 * disable process on Navi1x ASICs. 1870 * - As the gfx related features are under control of 1871 * RLC on those ASICs. RLC reinitialization will be 1872 * needed to reenable them. That will cost much more 1873 * efforts. 1874 * 1875 * - SMU firmware can handle the DPM reenablement 1876 * properly. 1877 */ 1878 if (smu->uploading_custom_pp_table) { 1879 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1880 case IP_VERSION(11, 0, 0): 1881 case IP_VERSION(11, 0, 5): 1882 case IP_VERSION(11, 0, 9): 1883 case IP_VERSION(11, 0, 7): 1884 case IP_VERSION(11, 0, 11): 1885 case IP_VERSION(11, 5, 0): 1886 case IP_VERSION(11, 0, 12): 1887 case IP_VERSION(11, 0, 13): 1888 return 0; 1889 default: 1890 break; 1891 } 1892 } 1893 1894 /* 1895 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1896 * on BACO in. Driver involvement is unnecessary. 1897 */ 1898 if (use_baco) { 1899 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1900 case IP_VERSION(11, 0, 7): 1901 case IP_VERSION(11, 0, 0): 1902 case IP_VERSION(11, 0, 5): 1903 case IP_VERSION(11, 0, 9): 1904 case IP_VERSION(13, 0, 7): 1905 return 0; 1906 default: 1907 break; 1908 } 1909 } 1910 1911 /* 1912 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1913 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1914 */ 1915 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1916 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1917 case IP_VERSION(13, 0, 4): 1918 case IP_VERSION(13, 0, 11): 1919 case IP_VERSION(14, 0, 0): 1920 case IP_VERSION(14, 0, 1): 1921 return 0; 1922 default: 1923 break; 1924 } 1925 } 1926 1927 /* 1928 * For gpu reset, runpm and hibernation through BACO, 1929 * BACO feature has to be kept enabled. 1930 */ 1931 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1932 ret = smu_disable_all_features_with_exception(smu, 1933 SMU_FEATURE_BACO_BIT); 1934 if (ret) 1935 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1936 } else { 1937 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1938 if (!adev->scpm_enabled) { 1939 ret = smu_system_features_control(smu, false); 1940 if (ret) 1941 dev_err(adev->dev, "Failed to disable smu features.\n"); 1942 } 1943 } 1944 1945 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1946 * otherwise SMU will hang while interacting with RLC if RLC is halted 1947 * this is a WA for Vangogh asic which fix the SMU hang issue. 1948 */ 1949 ret = smu_notify_rlc_state(smu, false); 1950 if (ret) { 1951 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1952 return ret; 1953 } 1954 1955 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1956 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1957 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1958 adev->gfx.rlc.funcs->stop(adev); 1959 1960 return ret; 1961 } 1962 1963 static int smu_smc_hw_cleanup(struct smu_context *smu) 1964 { 1965 struct amdgpu_device *adev = smu->adev; 1966 int ret = 0; 1967 1968 smu_wbrf_fini(smu); 1969 1970 cancel_work_sync(&smu->throttling_logging_work); 1971 cancel_work_sync(&smu->interrupt_work); 1972 1973 ret = smu_disable_thermal_alert(smu); 1974 if (ret) { 1975 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1976 return ret; 1977 } 1978 1979 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1980 1981 ret = smu_disable_dpms(smu); 1982 if (ret) { 1983 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1984 return ret; 1985 } 1986 1987 return 0; 1988 } 1989 1990 static int smu_reset_mp1_state(struct smu_context *smu) 1991 { 1992 struct amdgpu_device *adev = smu->adev; 1993 int ret = 0; 1994 1995 if ((!adev->in_runpm) && (!adev->in_suspend) && 1996 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 1997 IP_VERSION(13, 0, 10) && 1998 !amdgpu_device_has_display_hardware(adev)) 1999 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2000 2001 return ret; 2002 } 2003 2004 static int smu_hw_fini(void *handle) 2005 { 2006 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2007 struct smu_context *smu = adev->powerplay.pp_handle; 2008 int ret; 2009 2010 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2011 return 0; 2012 2013 smu_dpm_set_vcn_enable(smu, false); 2014 smu_dpm_set_jpeg_enable(smu, false); 2015 smu_dpm_set_vpe_enable(smu, false); 2016 smu_dpm_set_umsch_mm_enable(smu, false); 2017 2018 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2019 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2020 2021 if (!smu->pm_enabled) 2022 return 0; 2023 2024 adev->pm.dpm_enabled = false; 2025 2026 ret = smu_smc_hw_cleanup(smu); 2027 if (ret) 2028 return ret; 2029 2030 ret = smu_reset_mp1_state(smu); 2031 if (ret) 2032 return ret; 2033 2034 return 0; 2035 } 2036 2037 static void smu_late_fini(void *handle) 2038 { 2039 struct amdgpu_device *adev = handle; 2040 struct smu_context *smu = adev->powerplay.pp_handle; 2041 2042 kfree(smu); 2043 } 2044 2045 static int smu_reset(struct smu_context *smu) 2046 { 2047 struct amdgpu_device *adev = smu->adev; 2048 int ret; 2049 2050 ret = smu_hw_fini(adev); 2051 if (ret) 2052 return ret; 2053 2054 ret = smu_hw_init(adev); 2055 if (ret) 2056 return ret; 2057 2058 ret = smu_late_init(adev); 2059 if (ret) 2060 return ret; 2061 2062 return 0; 2063 } 2064 2065 static int smu_suspend(void *handle) 2066 { 2067 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2068 struct smu_context *smu = adev->powerplay.pp_handle; 2069 int ret; 2070 uint64_t count; 2071 2072 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2073 return 0; 2074 2075 if (!smu->pm_enabled) 2076 return 0; 2077 2078 adev->pm.dpm_enabled = false; 2079 2080 ret = smu_smc_hw_cleanup(smu); 2081 if (ret) 2082 return ret; 2083 2084 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2085 2086 smu_set_gfx_cgpg(smu, false); 2087 2088 /* 2089 * pwfw resets entrycount when device is suspended, so we save the 2090 * last value to be used when we resume to keep it consistent 2091 */ 2092 ret = smu_get_entrycount_gfxoff(smu, &count); 2093 if (!ret) 2094 adev->gfx.gfx_off_entrycount = count; 2095 2096 return 0; 2097 } 2098 2099 static int smu_resume(void *handle) 2100 { 2101 int ret; 2102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2103 struct smu_context *smu = adev->powerplay.pp_handle; 2104 2105 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2106 return 0; 2107 2108 if (!smu->pm_enabled) 2109 return 0; 2110 2111 dev_info(adev->dev, "SMU is resuming...\n"); 2112 2113 ret = smu_start_smc_engine(smu); 2114 if (ret) { 2115 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2116 return ret; 2117 } 2118 2119 ret = smu_smc_hw_setup(smu); 2120 if (ret) { 2121 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2122 return ret; 2123 } 2124 2125 ret = smu_set_gfx_imu_enable(smu); 2126 if (ret) 2127 return ret; 2128 2129 smu_set_gfx_cgpg(smu, true); 2130 2131 smu->disable_uclk_switch = 0; 2132 2133 adev->pm.dpm_enabled = true; 2134 2135 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2136 2137 return 0; 2138 } 2139 2140 static int smu_display_configuration_change(void *handle, 2141 const struct amd_pp_display_configuration *display_config) 2142 { 2143 struct smu_context *smu = handle; 2144 2145 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2146 return -EOPNOTSUPP; 2147 2148 if (!display_config) 2149 return -EINVAL; 2150 2151 smu_set_min_dcef_deep_sleep(smu, 2152 display_config->min_dcef_deep_sleep_set_clk / 100); 2153 2154 return 0; 2155 } 2156 2157 static int smu_set_clockgating_state(void *handle, 2158 enum amd_clockgating_state state) 2159 { 2160 return 0; 2161 } 2162 2163 static int smu_set_powergating_state(void *handle, 2164 enum amd_powergating_state state) 2165 { 2166 return 0; 2167 } 2168 2169 static int smu_enable_umd_pstate(void *handle, 2170 enum amd_dpm_forced_level *level) 2171 { 2172 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2173 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2174 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2175 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2176 2177 struct smu_context *smu = (struct smu_context*)(handle); 2178 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2179 2180 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2181 return -EINVAL; 2182 2183 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2184 /* enter umd pstate, save current level, disable gfx cg*/ 2185 if (*level & profile_mode_mask) { 2186 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2187 smu_gpo_control(smu, false); 2188 smu_gfx_ulv_control(smu, false); 2189 smu_deep_sleep_control(smu, false); 2190 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2191 } 2192 } else { 2193 /* exit umd pstate, restore level, enable gfx cg*/ 2194 if (!(*level & profile_mode_mask)) { 2195 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2196 *level = smu_dpm_ctx->saved_dpm_level; 2197 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2198 smu_deep_sleep_control(smu, true); 2199 smu_gfx_ulv_control(smu, true); 2200 smu_gpo_control(smu, true); 2201 } 2202 } 2203 2204 return 0; 2205 } 2206 2207 static int smu_bump_power_profile_mode(struct smu_context *smu, 2208 long *param, 2209 uint32_t param_size) 2210 { 2211 int ret = 0; 2212 2213 if (smu->ppt_funcs->set_power_profile_mode) 2214 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2215 2216 return ret; 2217 } 2218 2219 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2220 enum amd_dpm_forced_level level, 2221 bool skip_display_settings) 2222 { 2223 int ret = 0; 2224 int index = 0; 2225 long workload[1]; 2226 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2227 2228 if (!skip_display_settings) { 2229 ret = smu_display_config_changed(smu); 2230 if (ret) { 2231 dev_err(smu->adev->dev, "Failed to change display config!"); 2232 return ret; 2233 } 2234 } 2235 2236 ret = smu_apply_clocks_adjust_rules(smu); 2237 if (ret) { 2238 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2239 return ret; 2240 } 2241 2242 if (!skip_display_settings) { 2243 ret = smu_notify_smc_display_config(smu); 2244 if (ret) { 2245 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2246 return ret; 2247 } 2248 } 2249 2250 if (smu_dpm_ctx->dpm_level != level) { 2251 ret = smu_asic_set_performance_level(smu, level); 2252 if (ret) { 2253 dev_err(smu->adev->dev, "Failed to set performance level!"); 2254 return ret; 2255 } 2256 2257 /* update the saved copy */ 2258 smu_dpm_ctx->dpm_level = level; 2259 } 2260 2261 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2262 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2263 index = fls(smu->workload_mask); 2264 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2265 workload[0] = smu->workload_setting[index]; 2266 2267 if (smu->power_profile_mode != workload[0]) 2268 smu_bump_power_profile_mode(smu, workload, 0); 2269 } 2270 2271 return ret; 2272 } 2273 2274 static int smu_handle_task(struct smu_context *smu, 2275 enum amd_dpm_forced_level level, 2276 enum amd_pp_task task_id) 2277 { 2278 int ret = 0; 2279 2280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2281 return -EOPNOTSUPP; 2282 2283 switch (task_id) { 2284 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2285 ret = smu_pre_display_config_changed(smu); 2286 if (ret) 2287 return ret; 2288 ret = smu_adjust_power_state_dynamic(smu, level, false); 2289 break; 2290 case AMD_PP_TASK_COMPLETE_INIT: 2291 case AMD_PP_TASK_READJUST_POWER_STATE: 2292 ret = smu_adjust_power_state_dynamic(smu, level, true); 2293 break; 2294 default: 2295 break; 2296 } 2297 2298 return ret; 2299 } 2300 2301 static int smu_handle_dpm_task(void *handle, 2302 enum amd_pp_task task_id, 2303 enum amd_pm_state_type *user_state) 2304 { 2305 struct smu_context *smu = handle; 2306 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2307 2308 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2309 2310 } 2311 2312 static int smu_switch_power_profile(void *handle, 2313 enum PP_SMC_POWER_PROFILE type, 2314 bool en) 2315 { 2316 struct smu_context *smu = handle; 2317 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2318 long workload[1]; 2319 uint32_t index; 2320 2321 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2322 return -EOPNOTSUPP; 2323 2324 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2325 return -EINVAL; 2326 2327 if (!en) { 2328 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2329 index = fls(smu->workload_mask); 2330 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2331 workload[0] = smu->workload_setting[index]; 2332 } else { 2333 smu->workload_mask |= (1 << smu->workload_prority[type]); 2334 index = fls(smu->workload_mask); 2335 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2336 workload[0] = smu->workload_setting[index]; 2337 } 2338 2339 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2340 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2341 smu_bump_power_profile_mode(smu, workload, 0); 2342 2343 return 0; 2344 } 2345 2346 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2347 { 2348 struct smu_context *smu = handle; 2349 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2350 2351 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2352 return -EOPNOTSUPP; 2353 2354 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2355 return -EINVAL; 2356 2357 return smu_dpm_ctx->dpm_level; 2358 } 2359 2360 static int smu_force_performance_level(void *handle, 2361 enum amd_dpm_forced_level level) 2362 { 2363 struct smu_context *smu = handle; 2364 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2365 int ret = 0; 2366 2367 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2368 return -EOPNOTSUPP; 2369 2370 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2371 return -EINVAL; 2372 2373 ret = smu_enable_umd_pstate(smu, &level); 2374 if (ret) 2375 return ret; 2376 2377 ret = smu_handle_task(smu, level, 2378 AMD_PP_TASK_READJUST_POWER_STATE); 2379 2380 /* reset user dpm clock state */ 2381 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2382 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2383 smu->user_dpm_profile.clk_dependency = 0; 2384 } 2385 2386 return ret; 2387 } 2388 2389 static int smu_set_display_count(void *handle, uint32_t count) 2390 { 2391 struct smu_context *smu = handle; 2392 2393 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2394 return -EOPNOTSUPP; 2395 2396 return smu_init_display_count(smu, count); 2397 } 2398 2399 static int smu_force_smuclk_levels(struct smu_context *smu, 2400 enum smu_clk_type clk_type, 2401 uint32_t mask) 2402 { 2403 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2404 int ret = 0; 2405 2406 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2407 return -EOPNOTSUPP; 2408 2409 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2410 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2411 return -EINVAL; 2412 } 2413 2414 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2415 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2416 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2417 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2418 smu_set_user_clk_dependencies(smu, clk_type); 2419 } 2420 } 2421 2422 return ret; 2423 } 2424 2425 static int smu_force_ppclk_levels(void *handle, 2426 enum pp_clock_type type, 2427 uint32_t mask) 2428 { 2429 struct smu_context *smu = handle; 2430 enum smu_clk_type clk_type; 2431 2432 switch (type) { 2433 case PP_SCLK: 2434 clk_type = SMU_SCLK; break; 2435 case PP_MCLK: 2436 clk_type = SMU_MCLK; break; 2437 case PP_PCIE: 2438 clk_type = SMU_PCIE; break; 2439 case PP_SOCCLK: 2440 clk_type = SMU_SOCCLK; break; 2441 case PP_FCLK: 2442 clk_type = SMU_FCLK; break; 2443 case PP_DCEFCLK: 2444 clk_type = SMU_DCEFCLK; break; 2445 case PP_VCLK: 2446 clk_type = SMU_VCLK; break; 2447 case PP_VCLK1: 2448 clk_type = SMU_VCLK1; break; 2449 case PP_DCLK: 2450 clk_type = SMU_DCLK; break; 2451 case PP_DCLK1: 2452 clk_type = SMU_DCLK1; break; 2453 case OD_SCLK: 2454 clk_type = SMU_OD_SCLK; break; 2455 case OD_MCLK: 2456 clk_type = SMU_OD_MCLK; break; 2457 case OD_VDDC_CURVE: 2458 clk_type = SMU_OD_VDDC_CURVE; break; 2459 case OD_RANGE: 2460 clk_type = SMU_OD_RANGE; break; 2461 default: 2462 return -EINVAL; 2463 } 2464 2465 return smu_force_smuclk_levels(smu, clk_type, mask); 2466 } 2467 2468 /* 2469 * On system suspending or resetting, the dpm_enabled 2470 * flag will be cleared. So that those SMU services which 2471 * are not supported will be gated. 2472 * However, the mp1 state setting should still be granted 2473 * even if the dpm_enabled cleared. 2474 */ 2475 static int smu_set_mp1_state(void *handle, 2476 enum pp_mp1_state mp1_state) 2477 { 2478 struct smu_context *smu = handle; 2479 int ret = 0; 2480 2481 if (!smu->pm_enabled) 2482 return -EOPNOTSUPP; 2483 2484 if (smu->ppt_funcs && 2485 smu->ppt_funcs->set_mp1_state) 2486 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2487 2488 return ret; 2489 } 2490 2491 static int smu_set_df_cstate(void *handle, 2492 enum pp_df_cstate state) 2493 { 2494 struct smu_context *smu = handle; 2495 int ret = 0; 2496 2497 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2498 return -EOPNOTSUPP; 2499 2500 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2501 return 0; 2502 2503 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2504 if (ret) 2505 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2506 2507 return ret; 2508 } 2509 2510 int smu_write_watermarks_table(struct smu_context *smu) 2511 { 2512 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2513 return -EOPNOTSUPP; 2514 2515 return smu_set_watermarks_table(smu, NULL); 2516 } 2517 2518 static int smu_set_watermarks_for_clock_ranges(void *handle, 2519 struct pp_smu_wm_range_sets *clock_ranges) 2520 { 2521 struct smu_context *smu = handle; 2522 2523 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2524 return -EOPNOTSUPP; 2525 2526 if (smu->disable_watermark) 2527 return 0; 2528 2529 return smu_set_watermarks_table(smu, clock_ranges); 2530 } 2531 2532 int smu_set_ac_dc(struct smu_context *smu) 2533 { 2534 int ret = 0; 2535 2536 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2537 return -EOPNOTSUPP; 2538 2539 /* controlled by firmware */ 2540 if (smu->dc_controlled_by_gpio) 2541 return 0; 2542 2543 ret = smu_set_power_source(smu, 2544 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2545 SMU_POWER_SOURCE_DC); 2546 if (ret) 2547 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2548 smu->adev->pm.ac_power ? "AC" : "DC"); 2549 2550 return ret; 2551 } 2552 2553 const struct amd_ip_funcs smu_ip_funcs = { 2554 .name = "smu", 2555 .early_init = smu_early_init, 2556 .late_init = smu_late_init, 2557 .sw_init = smu_sw_init, 2558 .sw_fini = smu_sw_fini, 2559 .hw_init = smu_hw_init, 2560 .hw_fini = smu_hw_fini, 2561 .late_fini = smu_late_fini, 2562 .suspend = smu_suspend, 2563 .resume = smu_resume, 2564 .is_idle = NULL, 2565 .check_soft_reset = NULL, 2566 .wait_for_idle = NULL, 2567 .soft_reset = NULL, 2568 .set_clockgating_state = smu_set_clockgating_state, 2569 .set_powergating_state = smu_set_powergating_state, 2570 }; 2571 2572 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2573 .type = AMD_IP_BLOCK_TYPE_SMC, 2574 .major = 11, 2575 .minor = 0, 2576 .rev = 0, 2577 .funcs = &smu_ip_funcs, 2578 }; 2579 2580 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2581 .type = AMD_IP_BLOCK_TYPE_SMC, 2582 .major = 12, 2583 .minor = 0, 2584 .rev = 0, 2585 .funcs = &smu_ip_funcs, 2586 }; 2587 2588 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2589 .type = AMD_IP_BLOCK_TYPE_SMC, 2590 .major = 13, 2591 .minor = 0, 2592 .rev = 0, 2593 .funcs = &smu_ip_funcs, 2594 }; 2595 2596 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2597 .type = AMD_IP_BLOCK_TYPE_SMC, 2598 .major = 14, 2599 .minor = 0, 2600 .rev = 0, 2601 .funcs = &smu_ip_funcs, 2602 }; 2603 2604 static int smu_load_microcode(void *handle) 2605 { 2606 struct smu_context *smu = handle; 2607 struct amdgpu_device *adev = smu->adev; 2608 int ret = 0; 2609 2610 if (!smu->pm_enabled) 2611 return -EOPNOTSUPP; 2612 2613 /* This should be used for non PSP loading */ 2614 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2615 return 0; 2616 2617 if (smu->ppt_funcs->load_microcode) { 2618 ret = smu->ppt_funcs->load_microcode(smu); 2619 if (ret) { 2620 dev_err(adev->dev, "Load microcode failed\n"); 2621 return ret; 2622 } 2623 } 2624 2625 if (smu->ppt_funcs->check_fw_status) { 2626 ret = smu->ppt_funcs->check_fw_status(smu); 2627 if (ret) { 2628 dev_err(adev->dev, "SMC is not ready\n"); 2629 return ret; 2630 } 2631 } 2632 2633 return ret; 2634 } 2635 2636 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2637 { 2638 int ret = 0; 2639 2640 if (smu->ppt_funcs->set_gfx_cgpg) 2641 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2642 2643 return ret; 2644 } 2645 2646 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2647 { 2648 struct smu_context *smu = handle; 2649 int ret = 0; 2650 2651 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2652 return -EOPNOTSUPP; 2653 2654 if (!smu->ppt_funcs->set_fan_speed_rpm) 2655 return -EOPNOTSUPP; 2656 2657 if (speed == U32_MAX) 2658 return -EINVAL; 2659 2660 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2661 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2662 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2663 smu->user_dpm_profile.fan_speed_rpm = speed; 2664 2665 /* Override custom PWM setting as they cannot co-exist */ 2666 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2667 smu->user_dpm_profile.fan_speed_pwm = 0; 2668 } 2669 2670 return ret; 2671 } 2672 2673 /** 2674 * smu_get_power_limit - Request one of the SMU Power Limits 2675 * 2676 * @handle: pointer to smu context 2677 * @limit: requested limit is written back to this variable 2678 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2679 * @pp_power_type: &pp_power_type type of power 2680 * Return: 0 on success, <0 on error 2681 * 2682 */ 2683 int smu_get_power_limit(void *handle, 2684 uint32_t *limit, 2685 enum pp_power_limit_level pp_limit_level, 2686 enum pp_power_type pp_power_type) 2687 { 2688 struct smu_context *smu = handle; 2689 struct amdgpu_device *adev = smu->adev; 2690 enum smu_ppt_limit_level limit_level; 2691 uint32_t limit_type; 2692 int ret = 0; 2693 2694 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2695 return -EOPNOTSUPP; 2696 2697 switch (pp_power_type) { 2698 case PP_PWR_TYPE_SUSTAINED: 2699 limit_type = SMU_DEFAULT_PPT_LIMIT; 2700 break; 2701 case PP_PWR_TYPE_FAST: 2702 limit_type = SMU_FAST_PPT_LIMIT; 2703 break; 2704 default: 2705 return -EOPNOTSUPP; 2706 } 2707 2708 switch (pp_limit_level) { 2709 case PP_PWR_LIMIT_CURRENT: 2710 limit_level = SMU_PPT_LIMIT_CURRENT; 2711 break; 2712 case PP_PWR_LIMIT_DEFAULT: 2713 limit_level = SMU_PPT_LIMIT_DEFAULT; 2714 break; 2715 case PP_PWR_LIMIT_MAX: 2716 limit_level = SMU_PPT_LIMIT_MAX; 2717 break; 2718 case PP_PWR_LIMIT_MIN: 2719 limit_level = SMU_PPT_LIMIT_MIN; 2720 break; 2721 default: 2722 return -EOPNOTSUPP; 2723 } 2724 2725 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2726 if (smu->ppt_funcs->get_ppt_limit) 2727 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2728 } else { 2729 switch (limit_level) { 2730 case SMU_PPT_LIMIT_CURRENT: 2731 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2732 case IP_VERSION(13, 0, 2): 2733 case IP_VERSION(13, 0, 6): 2734 case IP_VERSION(13, 0, 14): 2735 case IP_VERSION(11, 0, 7): 2736 case IP_VERSION(11, 0, 11): 2737 case IP_VERSION(11, 0, 12): 2738 case IP_VERSION(11, 0, 13): 2739 ret = smu_get_asic_power_limits(smu, 2740 &smu->current_power_limit, 2741 NULL, NULL, NULL); 2742 break; 2743 default: 2744 break; 2745 } 2746 *limit = smu->current_power_limit; 2747 break; 2748 case SMU_PPT_LIMIT_DEFAULT: 2749 *limit = smu->default_power_limit; 2750 break; 2751 case SMU_PPT_LIMIT_MAX: 2752 *limit = smu->max_power_limit; 2753 break; 2754 case SMU_PPT_LIMIT_MIN: 2755 *limit = smu->min_power_limit; 2756 break; 2757 default: 2758 return -EINVAL; 2759 } 2760 } 2761 2762 return ret; 2763 } 2764 2765 static int smu_set_power_limit(void *handle, uint32_t limit) 2766 { 2767 struct smu_context *smu = handle; 2768 uint32_t limit_type = limit >> 24; 2769 int ret = 0; 2770 2771 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2772 return -EOPNOTSUPP; 2773 2774 limit &= (1<<24)-1; 2775 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2776 if (smu->ppt_funcs->set_power_limit) 2777 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2778 2779 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2780 dev_err(smu->adev->dev, 2781 "New power limit (%d) is out of range [%d,%d]\n", 2782 limit, smu->min_power_limit, smu->max_power_limit); 2783 return -EINVAL; 2784 } 2785 2786 if (!limit) 2787 limit = smu->current_power_limit; 2788 2789 if (smu->ppt_funcs->set_power_limit) { 2790 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2791 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2792 smu->user_dpm_profile.power_limit = limit; 2793 } 2794 2795 return ret; 2796 } 2797 2798 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2799 { 2800 int ret = 0; 2801 2802 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2803 return -EOPNOTSUPP; 2804 2805 if (smu->ppt_funcs->print_clk_levels) 2806 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2807 2808 return ret; 2809 } 2810 2811 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2812 { 2813 enum smu_clk_type clk_type; 2814 2815 switch (type) { 2816 case PP_SCLK: 2817 clk_type = SMU_SCLK; break; 2818 case PP_MCLK: 2819 clk_type = SMU_MCLK; break; 2820 case PP_PCIE: 2821 clk_type = SMU_PCIE; break; 2822 case PP_SOCCLK: 2823 clk_type = SMU_SOCCLK; break; 2824 case PP_FCLK: 2825 clk_type = SMU_FCLK; break; 2826 case PP_DCEFCLK: 2827 clk_type = SMU_DCEFCLK; break; 2828 case PP_VCLK: 2829 clk_type = SMU_VCLK; break; 2830 case PP_VCLK1: 2831 clk_type = SMU_VCLK1; break; 2832 case PP_DCLK: 2833 clk_type = SMU_DCLK; break; 2834 case PP_DCLK1: 2835 clk_type = SMU_DCLK1; break; 2836 case OD_SCLK: 2837 clk_type = SMU_OD_SCLK; break; 2838 case OD_MCLK: 2839 clk_type = SMU_OD_MCLK; break; 2840 case OD_VDDC_CURVE: 2841 clk_type = SMU_OD_VDDC_CURVE; break; 2842 case OD_RANGE: 2843 clk_type = SMU_OD_RANGE; break; 2844 case OD_VDDGFX_OFFSET: 2845 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2846 case OD_CCLK: 2847 clk_type = SMU_OD_CCLK; break; 2848 case OD_FAN_CURVE: 2849 clk_type = SMU_OD_FAN_CURVE; break; 2850 case OD_ACOUSTIC_LIMIT: 2851 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2852 case OD_ACOUSTIC_TARGET: 2853 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2854 case OD_FAN_TARGET_TEMPERATURE: 2855 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2856 case OD_FAN_MINIMUM_PWM: 2857 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2858 default: 2859 clk_type = SMU_CLK_COUNT; break; 2860 } 2861 2862 return clk_type; 2863 } 2864 2865 static int smu_print_ppclk_levels(void *handle, 2866 enum pp_clock_type type, 2867 char *buf) 2868 { 2869 struct smu_context *smu = handle; 2870 enum smu_clk_type clk_type; 2871 2872 clk_type = smu_convert_to_smuclk(type); 2873 if (clk_type == SMU_CLK_COUNT) 2874 return -EINVAL; 2875 2876 return smu_print_smuclk_levels(smu, clk_type, buf); 2877 } 2878 2879 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2880 { 2881 struct smu_context *smu = handle; 2882 enum smu_clk_type clk_type; 2883 2884 clk_type = smu_convert_to_smuclk(type); 2885 if (clk_type == SMU_CLK_COUNT) 2886 return -EINVAL; 2887 2888 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2889 return -EOPNOTSUPP; 2890 2891 if (!smu->ppt_funcs->emit_clk_levels) 2892 return -ENOENT; 2893 2894 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2895 2896 } 2897 2898 static int smu_od_edit_dpm_table(void *handle, 2899 enum PP_OD_DPM_TABLE_COMMAND type, 2900 long *input, uint32_t size) 2901 { 2902 struct smu_context *smu = handle; 2903 int ret = 0; 2904 2905 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2906 return -EOPNOTSUPP; 2907 2908 if (smu->ppt_funcs->od_edit_dpm_table) { 2909 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2910 } 2911 2912 return ret; 2913 } 2914 2915 static int smu_read_sensor(void *handle, 2916 int sensor, 2917 void *data, 2918 int *size_arg) 2919 { 2920 struct smu_context *smu = handle; 2921 struct smu_umd_pstate_table *pstate_table = 2922 &smu->pstate_table; 2923 int ret = 0; 2924 uint32_t *size, size_val; 2925 2926 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2927 return -EOPNOTSUPP; 2928 2929 if (!data || !size_arg) 2930 return -EINVAL; 2931 2932 size_val = *size_arg; 2933 size = &size_val; 2934 2935 if (smu->ppt_funcs->read_sensor) 2936 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2937 goto unlock; 2938 2939 switch (sensor) { 2940 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2941 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2942 *size = 4; 2943 break; 2944 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2945 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2946 *size = 4; 2947 break; 2948 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2949 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2950 *size = 4; 2951 break; 2952 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2953 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2954 *size = 4; 2955 break; 2956 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2957 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2958 *size = 8; 2959 break; 2960 case AMDGPU_PP_SENSOR_UVD_POWER: 2961 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2962 *size = 4; 2963 break; 2964 case AMDGPU_PP_SENSOR_VCE_POWER: 2965 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2966 *size = 4; 2967 break; 2968 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2969 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2970 *size = 4; 2971 break; 2972 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2973 *(uint32_t *)data = 0; 2974 *size = 4; 2975 break; 2976 default: 2977 *size = 0; 2978 ret = -EOPNOTSUPP; 2979 break; 2980 } 2981 2982 unlock: 2983 // assign uint32_t to int 2984 *size_arg = size_val; 2985 2986 return ret; 2987 } 2988 2989 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2990 { 2991 int ret = -EOPNOTSUPP; 2992 struct smu_context *smu = handle; 2993 2994 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2995 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2996 2997 return ret; 2998 } 2999 3000 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3001 { 3002 int ret = -EOPNOTSUPP; 3003 struct smu_context *smu = handle; 3004 3005 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3006 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3007 3008 return ret; 3009 } 3010 3011 static int smu_get_power_profile_mode(void *handle, char *buf) 3012 { 3013 struct smu_context *smu = handle; 3014 3015 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3016 !smu->ppt_funcs->get_power_profile_mode) 3017 return -EOPNOTSUPP; 3018 if (!buf) 3019 return -EINVAL; 3020 3021 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3022 } 3023 3024 static int smu_set_power_profile_mode(void *handle, 3025 long *param, 3026 uint32_t param_size) 3027 { 3028 struct smu_context *smu = handle; 3029 3030 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3031 !smu->ppt_funcs->set_power_profile_mode) 3032 return -EOPNOTSUPP; 3033 3034 return smu_bump_power_profile_mode(smu, param, param_size); 3035 } 3036 3037 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3038 { 3039 struct smu_context *smu = handle; 3040 3041 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3042 return -EOPNOTSUPP; 3043 3044 if (!smu->ppt_funcs->get_fan_control_mode) 3045 return -EOPNOTSUPP; 3046 3047 if (!fan_mode) 3048 return -EINVAL; 3049 3050 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3051 3052 return 0; 3053 } 3054 3055 static int smu_set_fan_control_mode(void *handle, u32 value) 3056 { 3057 struct smu_context *smu = handle; 3058 int ret = 0; 3059 3060 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3061 return -EOPNOTSUPP; 3062 3063 if (!smu->ppt_funcs->set_fan_control_mode) 3064 return -EOPNOTSUPP; 3065 3066 if (value == U32_MAX) 3067 return -EINVAL; 3068 3069 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3070 if (ret) 3071 goto out; 3072 3073 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3074 smu->user_dpm_profile.fan_mode = value; 3075 3076 /* reset user dpm fan speed */ 3077 if (value != AMD_FAN_CTRL_MANUAL) { 3078 smu->user_dpm_profile.fan_speed_pwm = 0; 3079 smu->user_dpm_profile.fan_speed_rpm = 0; 3080 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3081 } 3082 } 3083 3084 out: 3085 return ret; 3086 } 3087 3088 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3089 { 3090 struct smu_context *smu = handle; 3091 int ret = 0; 3092 3093 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3094 return -EOPNOTSUPP; 3095 3096 if (!smu->ppt_funcs->get_fan_speed_pwm) 3097 return -EOPNOTSUPP; 3098 3099 if (!speed) 3100 return -EINVAL; 3101 3102 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3103 3104 return ret; 3105 } 3106 3107 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3108 { 3109 struct smu_context *smu = handle; 3110 int ret = 0; 3111 3112 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3113 return -EOPNOTSUPP; 3114 3115 if (!smu->ppt_funcs->set_fan_speed_pwm) 3116 return -EOPNOTSUPP; 3117 3118 if (speed == U32_MAX) 3119 return -EINVAL; 3120 3121 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3122 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3123 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3124 smu->user_dpm_profile.fan_speed_pwm = speed; 3125 3126 /* Override custom RPM setting as they cannot co-exist */ 3127 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3128 smu->user_dpm_profile.fan_speed_rpm = 0; 3129 } 3130 3131 return ret; 3132 } 3133 3134 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3135 { 3136 struct smu_context *smu = handle; 3137 int ret = 0; 3138 3139 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3140 return -EOPNOTSUPP; 3141 3142 if (!smu->ppt_funcs->get_fan_speed_rpm) 3143 return -EOPNOTSUPP; 3144 3145 if (!speed) 3146 return -EINVAL; 3147 3148 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3149 3150 return ret; 3151 } 3152 3153 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3154 { 3155 struct smu_context *smu = handle; 3156 3157 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3158 return -EOPNOTSUPP; 3159 3160 return smu_set_min_dcef_deep_sleep(smu, clk); 3161 } 3162 3163 static int smu_get_clock_by_type_with_latency(void *handle, 3164 enum amd_pp_clock_type type, 3165 struct pp_clock_levels_with_latency *clocks) 3166 { 3167 struct smu_context *smu = handle; 3168 enum smu_clk_type clk_type; 3169 int ret = 0; 3170 3171 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3172 return -EOPNOTSUPP; 3173 3174 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3175 switch (type) { 3176 case amd_pp_sys_clock: 3177 clk_type = SMU_GFXCLK; 3178 break; 3179 case amd_pp_mem_clock: 3180 clk_type = SMU_MCLK; 3181 break; 3182 case amd_pp_dcef_clock: 3183 clk_type = SMU_DCEFCLK; 3184 break; 3185 case amd_pp_disp_clock: 3186 clk_type = SMU_DISPCLK; 3187 break; 3188 default: 3189 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3190 return -EINVAL; 3191 } 3192 3193 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3194 } 3195 3196 return ret; 3197 } 3198 3199 static int smu_display_clock_voltage_request(void *handle, 3200 struct pp_display_clock_request *clock_req) 3201 { 3202 struct smu_context *smu = handle; 3203 int ret = 0; 3204 3205 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3206 return -EOPNOTSUPP; 3207 3208 if (smu->ppt_funcs->display_clock_voltage_request) 3209 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3210 3211 return ret; 3212 } 3213 3214 3215 static int smu_display_disable_memory_clock_switch(void *handle, 3216 bool disable_memory_clock_switch) 3217 { 3218 struct smu_context *smu = handle; 3219 int ret = -EINVAL; 3220 3221 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3222 return -EOPNOTSUPP; 3223 3224 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3225 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3226 3227 return ret; 3228 } 3229 3230 static int smu_set_xgmi_pstate(void *handle, 3231 uint32_t pstate) 3232 { 3233 struct smu_context *smu = handle; 3234 int ret = 0; 3235 3236 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3237 return -EOPNOTSUPP; 3238 3239 if (smu->ppt_funcs->set_xgmi_pstate) 3240 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3241 3242 if (ret) 3243 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3244 3245 return ret; 3246 } 3247 3248 static int smu_get_baco_capability(void *handle) 3249 { 3250 struct smu_context *smu = handle; 3251 3252 if (!smu->pm_enabled) 3253 return false; 3254 3255 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3256 return false; 3257 3258 return smu->ppt_funcs->get_bamaco_support(smu); 3259 } 3260 3261 static int smu_baco_set_state(void *handle, int state) 3262 { 3263 struct smu_context *smu = handle; 3264 int ret = 0; 3265 3266 if (!smu->pm_enabled) 3267 return -EOPNOTSUPP; 3268 3269 if (state == 0) { 3270 if (smu->ppt_funcs->baco_exit) 3271 ret = smu->ppt_funcs->baco_exit(smu); 3272 } else if (state == 1) { 3273 if (smu->ppt_funcs->baco_enter) 3274 ret = smu->ppt_funcs->baco_enter(smu); 3275 } else { 3276 return -EINVAL; 3277 } 3278 3279 if (ret) 3280 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3281 (state)?"enter":"exit"); 3282 3283 return ret; 3284 } 3285 3286 bool smu_mode1_reset_is_support(struct smu_context *smu) 3287 { 3288 bool ret = false; 3289 3290 if (!smu->pm_enabled) 3291 return false; 3292 3293 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3294 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3295 3296 return ret; 3297 } 3298 3299 bool smu_mode2_reset_is_support(struct smu_context *smu) 3300 { 3301 bool ret = false; 3302 3303 if (!smu->pm_enabled) 3304 return false; 3305 3306 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3307 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3308 3309 return ret; 3310 } 3311 3312 int smu_mode1_reset(struct smu_context *smu) 3313 { 3314 int ret = 0; 3315 3316 if (!smu->pm_enabled) 3317 return -EOPNOTSUPP; 3318 3319 if (smu->ppt_funcs->mode1_reset) 3320 ret = smu->ppt_funcs->mode1_reset(smu); 3321 3322 return ret; 3323 } 3324 3325 static int smu_mode2_reset(void *handle) 3326 { 3327 struct smu_context *smu = handle; 3328 int ret = 0; 3329 3330 if (!smu->pm_enabled) 3331 return -EOPNOTSUPP; 3332 3333 if (smu->ppt_funcs->mode2_reset) 3334 ret = smu->ppt_funcs->mode2_reset(smu); 3335 3336 if (ret) 3337 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3338 3339 return ret; 3340 } 3341 3342 static int smu_enable_gfx_features(void *handle) 3343 { 3344 struct smu_context *smu = handle; 3345 int ret = 0; 3346 3347 if (!smu->pm_enabled) 3348 return -EOPNOTSUPP; 3349 3350 if (smu->ppt_funcs->enable_gfx_features) 3351 ret = smu->ppt_funcs->enable_gfx_features(smu); 3352 3353 if (ret) 3354 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3355 3356 return ret; 3357 } 3358 3359 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3360 struct pp_smu_nv_clock_table *max_clocks) 3361 { 3362 struct smu_context *smu = handle; 3363 int ret = 0; 3364 3365 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3366 return -EOPNOTSUPP; 3367 3368 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3369 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3370 3371 return ret; 3372 } 3373 3374 static int smu_get_uclk_dpm_states(void *handle, 3375 unsigned int *clock_values_in_khz, 3376 unsigned int *num_states) 3377 { 3378 struct smu_context *smu = handle; 3379 int ret = 0; 3380 3381 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3382 return -EOPNOTSUPP; 3383 3384 if (smu->ppt_funcs->get_uclk_dpm_states) 3385 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3386 3387 return ret; 3388 } 3389 3390 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3391 { 3392 struct smu_context *smu = handle; 3393 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3394 3395 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3396 return -EOPNOTSUPP; 3397 3398 if (smu->ppt_funcs->get_current_power_state) 3399 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3400 3401 return pm_state; 3402 } 3403 3404 static int smu_get_dpm_clock_table(void *handle, 3405 struct dpm_clocks *clock_table) 3406 { 3407 struct smu_context *smu = handle; 3408 int ret = 0; 3409 3410 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3411 return -EOPNOTSUPP; 3412 3413 if (smu->ppt_funcs->get_dpm_clock_table) 3414 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3415 3416 return ret; 3417 } 3418 3419 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3420 { 3421 struct smu_context *smu = handle; 3422 3423 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3424 return -EOPNOTSUPP; 3425 3426 if (!smu->ppt_funcs->get_gpu_metrics) 3427 return -EOPNOTSUPP; 3428 3429 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3430 } 3431 3432 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3433 size_t size) 3434 { 3435 struct smu_context *smu = handle; 3436 3437 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3438 return -EOPNOTSUPP; 3439 3440 if (!smu->ppt_funcs->get_pm_metrics) 3441 return -EOPNOTSUPP; 3442 3443 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3444 } 3445 3446 static int smu_enable_mgpu_fan_boost(void *handle) 3447 { 3448 struct smu_context *smu = handle; 3449 int ret = 0; 3450 3451 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3452 return -EOPNOTSUPP; 3453 3454 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3455 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3456 3457 return ret; 3458 } 3459 3460 static int smu_gfx_state_change_set(void *handle, 3461 uint32_t state) 3462 { 3463 struct smu_context *smu = handle; 3464 int ret = 0; 3465 3466 if (smu->ppt_funcs->gfx_state_change_set) 3467 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3468 3469 return ret; 3470 } 3471 3472 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3473 { 3474 int ret = 0; 3475 3476 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3477 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3478 3479 return ret; 3480 } 3481 3482 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3483 { 3484 int ret = -EOPNOTSUPP; 3485 3486 if (smu->ppt_funcs && 3487 smu->ppt_funcs->get_ecc_info) 3488 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3489 3490 return ret; 3491 3492 } 3493 3494 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3495 { 3496 struct smu_context *smu = handle; 3497 struct smu_table_context *smu_table = &smu->smu_table; 3498 struct smu_table *memory_pool = &smu_table->memory_pool; 3499 3500 if (!addr || !size) 3501 return -EINVAL; 3502 3503 *addr = NULL; 3504 *size = 0; 3505 if (memory_pool->bo) { 3506 *addr = memory_pool->cpu_addr; 3507 *size = memory_pool->size; 3508 } 3509 3510 return 0; 3511 } 3512 3513 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3514 size_t *size) 3515 { 3516 size_t offset = *size; 3517 int level; 3518 3519 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3520 if (level == policy->current_level) 3521 offset += sysfs_emit_at(sysbuf, offset, 3522 "%d : %s*\n", level, 3523 policy->desc->get_desc(policy, level)); 3524 else 3525 offset += sysfs_emit_at(sysbuf, offset, 3526 "%d : %s\n", level, 3527 policy->desc->get_desc(policy, level)); 3528 } 3529 3530 *size = offset; 3531 } 3532 3533 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3534 enum pp_pm_policy p_type, char *sysbuf) 3535 { 3536 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3537 struct smu_dpm_policy_ctxt *policy_ctxt; 3538 struct smu_dpm_policy *dpm_policy; 3539 size_t offset = 0; 3540 3541 policy_ctxt = dpm_ctxt->dpm_policies; 3542 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3543 !policy_ctxt->policy_mask) 3544 return -EOPNOTSUPP; 3545 3546 if (p_type == PP_PM_POLICY_NONE) 3547 return -EINVAL; 3548 3549 dpm_policy = smu_get_pm_policy(smu, p_type); 3550 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3551 return -ENOENT; 3552 3553 if (!sysbuf) 3554 return -EINVAL; 3555 3556 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3557 3558 return offset; 3559 } 3560 3561 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3562 enum pp_pm_policy p_type) 3563 { 3564 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3565 struct smu_dpm_policy_ctxt *policy_ctxt; 3566 int i; 3567 3568 policy_ctxt = dpm_ctxt->dpm_policies; 3569 if (!policy_ctxt) 3570 return NULL; 3571 3572 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3573 if (policy_ctxt->policies[i].policy_type == p_type) 3574 return &policy_ctxt->policies[i]; 3575 } 3576 3577 return NULL; 3578 } 3579 3580 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3581 int level) 3582 { 3583 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3584 struct smu_dpm_policy *dpm_policy = NULL; 3585 struct smu_dpm_policy_ctxt *policy_ctxt; 3586 int ret = -EOPNOTSUPP; 3587 3588 policy_ctxt = dpm_ctxt->dpm_policies; 3589 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3590 !policy_ctxt->policy_mask) 3591 return ret; 3592 3593 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3594 return -EINVAL; 3595 3596 dpm_policy = smu_get_pm_policy(smu, p_type); 3597 3598 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3599 return ret; 3600 3601 if (dpm_policy->current_level == level) 3602 return 0; 3603 3604 ret = dpm_policy->set_policy(smu, level); 3605 3606 if (!ret) 3607 dpm_policy->current_level = level; 3608 3609 return ret; 3610 } 3611 3612 static const struct amd_pm_funcs swsmu_pm_funcs = { 3613 /* export for sysfs */ 3614 .set_fan_control_mode = smu_set_fan_control_mode, 3615 .get_fan_control_mode = smu_get_fan_control_mode, 3616 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3617 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3618 .force_clock_level = smu_force_ppclk_levels, 3619 .print_clock_levels = smu_print_ppclk_levels, 3620 .emit_clock_levels = smu_emit_ppclk_levels, 3621 .force_performance_level = smu_force_performance_level, 3622 .read_sensor = smu_read_sensor, 3623 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3624 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3625 .get_performance_level = smu_get_performance_level, 3626 .get_current_power_state = smu_get_current_power_state, 3627 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3628 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3629 .get_pp_num_states = smu_get_power_num_states, 3630 .get_pp_table = smu_sys_get_pp_table, 3631 .set_pp_table = smu_sys_set_pp_table, 3632 .switch_power_profile = smu_switch_power_profile, 3633 /* export to amdgpu */ 3634 .dispatch_tasks = smu_handle_dpm_task, 3635 .load_firmware = smu_load_microcode, 3636 .set_powergating_by_smu = smu_dpm_set_power_gate, 3637 .set_power_limit = smu_set_power_limit, 3638 .get_power_limit = smu_get_power_limit, 3639 .get_power_profile_mode = smu_get_power_profile_mode, 3640 .set_power_profile_mode = smu_set_power_profile_mode, 3641 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3642 .set_mp1_state = smu_set_mp1_state, 3643 .gfx_state_change_set = smu_gfx_state_change_set, 3644 /* export to DC */ 3645 .get_sclk = smu_get_sclk, 3646 .get_mclk = smu_get_mclk, 3647 .display_configuration_change = smu_display_configuration_change, 3648 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3649 .display_clock_voltage_request = smu_display_clock_voltage_request, 3650 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3651 .set_active_display_count = smu_set_display_count, 3652 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3653 .get_asic_baco_capability = smu_get_baco_capability, 3654 .set_asic_baco_state = smu_baco_set_state, 3655 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3656 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3657 .asic_reset_mode_2 = smu_mode2_reset, 3658 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3659 .set_df_cstate = smu_set_df_cstate, 3660 .set_xgmi_pstate = smu_set_xgmi_pstate, 3661 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3662 .get_pm_metrics = smu_sys_get_pm_metrics, 3663 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3664 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3665 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3666 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3667 .get_dpm_clock_table = smu_get_dpm_clock_table, 3668 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3669 }; 3670 3671 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3672 uint64_t event_arg) 3673 { 3674 int ret = -EINVAL; 3675 3676 if (smu->ppt_funcs->wait_for_event) 3677 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3678 3679 return ret; 3680 } 3681 3682 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3683 { 3684 3685 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3686 return -EOPNOTSUPP; 3687 3688 /* Confirm the buffer allocated is of correct size */ 3689 if (size != smu->stb_context.stb_buf_size) 3690 return -EINVAL; 3691 3692 /* 3693 * No need to lock smu mutex as we access STB directly through MMIO 3694 * and not going through SMU messaging route (for now at least). 3695 * For registers access rely on implementation internal locking. 3696 */ 3697 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3698 } 3699 3700 #if defined(CONFIG_DEBUG_FS) 3701 3702 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3703 { 3704 struct amdgpu_device *adev = filp->f_inode->i_private; 3705 struct smu_context *smu = adev->powerplay.pp_handle; 3706 unsigned char *buf; 3707 int r; 3708 3709 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3710 if (!buf) 3711 return -ENOMEM; 3712 3713 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3714 if (r) 3715 goto out; 3716 3717 filp->private_data = buf; 3718 3719 return 0; 3720 3721 out: 3722 kvfree(buf); 3723 return r; 3724 } 3725 3726 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3727 loff_t *pos) 3728 { 3729 struct amdgpu_device *adev = filp->f_inode->i_private; 3730 struct smu_context *smu = adev->powerplay.pp_handle; 3731 3732 3733 if (!filp->private_data) 3734 return -EINVAL; 3735 3736 return simple_read_from_buffer(buf, 3737 size, 3738 pos, filp->private_data, 3739 smu->stb_context.stb_buf_size); 3740 } 3741 3742 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3743 { 3744 kvfree(filp->private_data); 3745 filp->private_data = NULL; 3746 3747 return 0; 3748 } 3749 3750 /* 3751 * We have to define not only read method but also 3752 * open and release because .read takes up to PAGE_SIZE 3753 * data each time so and so is invoked multiple times. 3754 * We allocate the STB buffer in .open and release it 3755 * in .release 3756 */ 3757 static const struct file_operations smu_stb_debugfs_fops = { 3758 .owner = THIS_MODULE, 3759 .open = smu_stb_debugfs_open, 3760 .read = smu_stb_debugfs_read, 3761 .release = smu_stb_debugfs_release, 3762 .llseek = default_llseek, 3763 }; 3764 3765 #endif 3766 3767 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3768 { 3769 #if defined(CONFIG_DEBUG_FS) 3770 3771 struct smu_context *smu = adev->powerplay.pp_handle; 3772 3773 if (!smu || (!smu->stb_context.stb_buf_size)) 3774 return; 3775 3776 debugfs_create_file_size("amdgpu_smu_stb_dump", 3777 S_IRUSR, 3778 adev_to_drm(adev)->primary->debugfs_root, 3779 adev, 3780 &smu_stb_debugfs_fops, 3781 smu->stb_context.stb_buf_size); 3782 #endif 3783 } 3784 3785 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3786 { 3787 int ret = 0; 3788 3789 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3790 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3791 3792 return ret; 3793 } 3794 3795 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3796 { 3797 int ret = 0; 3798 3799 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3800 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3801 3802 return ret; 3803 } 3804 3805 int smu_send_rma_reason(struct smu_context *smu) 3806 { 3807 int ret = 0; 3808 3809 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3810 ret = smu->ppt_funcs->send_rma_reason(smu); 3811 3812 return ret; 3813 } 3814