1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_reset.h" 32 #include "amdgpu_smu.h" 33 #include "smu_internal.h" 34 #include "atom.h" 35 #include "arcturus_ppt.h" 36 #include "navi10_ppt.h" 37 #include "sienna_cichlid_ppt.h" 38 #include "renoir_ppt.h" 39 #include "vangogh_ppt.h" 40 #include "aldebaran_ppt.h" 41 #include "yellow_carp_ppt.h" 42 #include "cyan_skillfish_ppt.h" 43 #include "smu_v13_0_0_ppt.h" 44 #include "smu_v13_0_4_ppt.h" 45 #include "smu_v13_0_5_ppt.h" 46 #include "smu_v13_0_6_ppt.h" 47 #include "smu_v13_0_7_ppt.h" 48 #include "smu_v14_0_0_ppt.h" 49 #include "smu_v14_0_2_ppt.h" 50 #include "smu_v15_0_0_ppt.h" 51 #include "smu_v15_0_8_ppt.h" 52 #include "amd_pcie.h" 53 54 /* 55 * DO NOT use these for err/warn/info/debug messages. 56 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 57 * They are more MGPU friendly. 58 */ 59 #undef pr_err 60 #undef pr_warn 61 #undef pr_info 62 #undef pr_debug 63 64 static const struct amd_pm_funcs swsmu_pm_funcs; 65 static int smu_force_smuclk_levels(struct smu_context *smu, 66 enum smu_clk_type clk_type, 67 uint32_t mask); 68 static int smu_handle_task(struct smu_context *smu, 69 enum amd_dpm_forced_level level, 70 enum amd_pp_task task_id); 71 static int smu_reset(struct smu_context *smu); 72 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 73 static int smu_set_fan_control_mode(void *handle, u32 value); 74 static int smu_set_ppt_limit(void *handle, uint32_t limit_type, uint32_t limit); 75 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 76 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 77 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 78 static void smu_power_profile_mode_get(struct smu_context *smu, 79 enum PP_SMC_POWER_PROFILE profile_mode); 80 static void smu_power_profile_mode_put(struct smu_context *smu, 81 enum PP_SMC_POWER_PROFILE profile_mode); 82 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); 83 static int smu_od_edit_dpm_table(void *handle, 84 enum PP_OD_DPM_TABLE_COMMAND type, 85 long *input, uint32_t size); 86 87 static int smu_sys_get_pp_feature_mask(void *handle, 88 char *buf) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_get_pp_feature_mask(smu, buf); 96 } 97 98 static int smu_sys_set_pp_feature_mask(void *handle, 99 uint64_t new_mask) 100 { 101 struct smu_context *smu = handle; 102 103 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 104 return -EOPNOTSUPP; 105 106 return smu_set_pp_feature_mask(smu, new_mask); 107 } 108 109 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 110 { 111 if (!smu->ppt_funcs->set_gfx_off_residency) 112 return -EINVAL; 113 114 return smu_set_gfx_off_residency(smu, value); 115 } 116 117 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 118 { 119 if (!smu->ppt_funcs->get_gfx_off_residency) 120 return -EINVAL; 121 122 return smu_get_gfx_off_residency(smu, value); 123 } 124 125 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 126 { 127 if (!smu->ppt_funcs->get_gfx_off_entrycount) 128 return -EINVAL; 129 130 return smu_get_gfx_off_entrycount(smu, value); 131 } 132 133 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 134 { 135 if (!smu->ppt_funcs->get_gfx_off_status) 136 return -EINVAL; 137 138 *value = smu_get_gfx_off_status(smu); 139 140 return 0; 141 } 142 143 int smu_set_soft_freq_range(struct smu_context *smu, 144 enum pp_clock_type type, 145 uint32_t min, 146 uint32_t max) 147 { 148 enum smu_clk_type clk_type; 149 int ret = 0; 150 151 clk_type = smu_convert_to_smuclk(type); 152 if (clk_type == SMU_CLK_COUNT) 153 return -EINVAL; 154 155 if (smu->ppt_funcs->set_soft_freq_limited_range) 156 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 157 clk_type, 158 min, 159 max, 160 false); 161 162 return ret; 163 } 164 165 int smu_get_dpm_freq_range(struct smu_context *smu, 166 enum smu_clk_type clk_type, 167 uint32_t *min, 168 uint32_t *max) 169 { 170 int ret = -ENOTSUPP; 171 172 if (!min && !max) 173 return -EINVAL; 174 175 if (smu->ppt_funcs->get_dpm_ultimate_freq) 176 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 177 clk_type, 178 min, 179 max); 180 181 return ret; 182 } 183 184 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 185 { 186 int ret = 0; 187 struct amdgpu_device *adev = smu->adev; 188 189 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 190 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 191 if (ret) 192 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 193 } 194 return ret; 195 } 196 197 static u32 smu_get_mclk(void *handle, bool low) 198 { 199 struct smu_context *smu = handle; 200 uint32_t clk_freq; 201 int ret = 0; 202 203 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 204 low ? &clk_freq : NULL, 205 !low ? &clk_freq : NULL); 206 if (ret) 207 return 0; 208 return clk_freq * 100; 209 } 210 211 static u32 smu_get_sclk(void *handle, bool low) 212 { 213 struct smu_context *smu = handle; 214 uint32_t clk_freq; 215 int ret = 0; 216 217 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 218 low ? &clk_freq : NULL, 219 !low ? &clk_freq : NULL); 220 if (ret) 221 return 0; 222 return clk_freq * 100; 223 } 224 225 static int smu_set_gfx_imu_enable(struct smu_context *smu) 226 { 227 struct amdgpu_device *adev = smu->adev; 228 229 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 230 return 0; 231 232 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 233 return 0; 234 235 return smu_set_gfx_power_up_by_imu(smu); 236 } 237 238 static bool is_vcn_enabled(struct amdgpu_device *adev) 239 { 240 int i; 241 242 for (i = 0; i < adev->num_ip_blocks; i++) { 243 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 244 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 245 !adev->ip_blocks[i].status.valid) 246 return false; 247 } 248 249 return true; 250 } 251 252 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 253 bool enable, 254 int inst) 255 { 256 struct smu_power_context *smu_power = &smu->smu_power; 257 struct smu_power_gate *power_gate = &smu_power->power_gate; 258 int ret = 0; 259 260 /* 261 * don't poweron vcn/jpeg when they are skipped. 262 */ 263 if (!is_vcn_enabled(smu->adev)) 264 return 0; 265 266 if (!smu->ppt_funcs->dpm_set_vcn_enable) 267 return 0; 268 269 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 270 return 0; 271 272 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 273 if (!ret) 274 atomic_set(&power_gate->vcn_gated[inst], !enable); 275 276 return ret; 277 } 278 279 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 280 bool enable) 281 { 282 struct smu_power_context *smu_power = &smu->smu_power; 283 struct smu_power_gate *power_gate = &smu_power->power_gate; 284 int ret = 0; 285 286 if (!is_vcn_enabled(smu->adev)) 287 return 0; 288 289 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 290 return 0; 291 292 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 293 return 0; 294 295 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 296 if (!ret) 297 atomic_set(&power_gate->jpeg_gated, !enable); 298 299 return ret; 300 } 301 302 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 303 bool enable) 304 { 305 struct smu_power_context *smu_power = &smu->smu_power; 306 struct smu_power_gate *power_gate = &smu_power->power_gate; 307 int ret = 0; 308 309 if (!smu->ppt_funcs->dpm_set_vpe_enable) 310 return 0; 311 312 if (atomic_read(&power_gate->vpe_gated) ^ enable) 313 return 0; 314 315 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 316 if (!ret) 317 atomic_set(&power_gate->vpe_gated, !enable); 318 319 return ret; 320 } 321 322 static int smu_dpm_set_isp_enable(struct smu_context *smu, 323 bool enable) 324 { 325 struct smu_power_context *smu_power = &smu->smu_power; 326 struct smu_power_gate *power_gate = &smu_power->power_gate; 327 int ret; 328 329 if (!smu->ppt_funcs->dpm_set_isp_enable) 330 return 0; 331 332 if (atomic_read(&power_gate->isp_gated) ^ enable) 333 return 0; 334 335 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable); 336 if (!ret) 337 atomic_set(&power_gate->isp_gated, !enable); 338 339 return ret; 340 } 341 342 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 343 bool enable) 344 { 345 struct smu_power_context *smu_power = &smu->smu_power; 346 struct smu_power_gate *power_gate = &smu_power->power_gate; 347 int ret = 0; 348 349 if (!smu->adev->enable_umsch_mm) 350 return 0; 351 352 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 353 return 0; 354 355 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 356 return 0; 357 358 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 359 if (!ret) 360 atomic_set(&power_gate->umsch_mm_gated, !enable); 361 362 return ret; 363 } 364 365 static int smu_set_mall_enable(struct smu_context *smu) 366 { 367 int ret = 0; 368 369 if (!smu->ppt_funcs->set_mall_enable) 370 return 0; 371 372 ret = smu->ppt_funcs->set_mall_enable(smu); 373 374 return ret; 375 } 376 377 /** 378 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 379 * 380 * @handle: smu_context pointer 381 * @block_type: the IP block to power gate/ungate 382 * @gate: to power gate if true, ungate otherwise 383 * @inst: the instance of the IP block to power gate/ungate 384 * 385 * This API uses no smu->mutex lock protection due to: 386 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 387 * This is guarded to be race condition free by the caller. 388 * 2. Or get called on user setting request of power_dpm_force_performance_level. 389 * Under this case, the smu->mutex lock protection is already enforced on 390 * the parent API smu_force_performance_level of the call path. 391 */ 392 static int smu_dpm_set_power_gate(void *handle, 393 uint32_t block_type, 394 bool gate, 395 int inst) 396 { 397 struct smu_context *smu = handle; 398 int ret = 0; 399 400 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 401 dev_WARN(smu->adev->dev, 402 "SMU uninitialized but power %s requested for %u!\n", 403 gate ? "gate" : "ungate", block_type); 404 return -EOPNOTSUPP; 405 } 406 407 switch (block_type) { 408 /* 409 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 410 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 411 */ 412 case AMD_IP_BLOCK_TYPE_UVD: 413 case AMD_IP_BLOCK_TYPE_VCN: 414 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 415 if (ret) 416 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 417 gate ? "gate" : "ungate", inst); 418 break; 419 case AMD_IP_BLOCK_TYPE_GFX: 420 ret = smu_gfx_off_control(smu, gate); 421 if (ret) 422 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 423 gate ? "enable" : "disable"); 424 break; 425 case AMD_IP_BLOCK_TYPE_SDMA: 426 ret = smu_powergate_sdma(smu, gate); 427 if (ret) 428 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 429 gate ? "gate" : "ungate"); 430 break; 431 case AMD_IP_BLOCK_TYPE_JPEG: 432 ret = smu_dpm_set_jpeg_enable(smu, !gate); 433 if (ret) 434 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 435 gate ? "gate" : "ungate"); 436 break; 437 case AMD_IP_BLOCK_TYPE_VPE: 438 ret = smu_dpm_set_vpe_enable(smu, !gate); 439 if (ret) 440 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 441 gate ? "gate" : "ungate"); 442 break; 443 case AMD_IP_BLOCK_TYPE_ISP: 444 ret = smu_dpm_set_isp_enable(smu, !gate); 445 if (ret) 446 dev_err(smu->adev->dev, "Failed to power %s ISP!\n", 447 gate ? "gate" : "ungate"); 448 break; 449 default: 450 dev_err(smu->adev->dev, "Unsupported block type!\n"); 451 return -EINVAL; 452 } 453 454 return ret; 455 } 456 457 /** 458 * smu_set_user_clk_dependencies - set user profile clock dependencies 459 * 460 * @smu: smu_context pointer 461 * @clk: enum smu_clk_type type 462 * 463 * Enable/Disable the clock dependency for the @clk type. 464 */ 465 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 466 { 467 if (smu->adev->in_suspend) 468 return; 469 470 if (clk == SMU_MCLK) { 471 smu->user_dpm_profile.clk_dependency = 0; 472 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 473 } else if (clk == SMU_FCLK) { 474 /* MCLK takes precedence over FCLK */ 475 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 476 return; 477 478 smu->user_dpm_profile.clk_dependency = 0; 479 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 480 } else if (clk == SMU_SOCCLK) { 481 /* MCLK takes precedence over SOCCLK */ 482 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 483 return; 484 485 smu->user_dpm_profile.clk_dependency = 0; 486 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 487 } else 488 /* Add clk dependencies here, if any */ 489 return; 490 } 491 492 static void smu_restore_ppt_limits(struct smu_context *smu, 493 bool restore_defaults) 494 { 495 enum smu_power_src_type power_source; 496 struct smu_ppt_limit_range *range; 497 uint32_t restore_mask; 498 uint32_t limit; 499 int i, ret; 500 501 power_source = smu->adev->pm.ac_power ? 502 SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC; 503 restore_mask = smu->user_dpm_profile.ppt_limit_user_mask[power_source] & 504 smu->ppt_limits.supported_mask; 505 if (!restore_mask && !restore_defaults) 506 return; 507 508 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 509 510 for (i = SMU_PPT_LIMIT_PPT0; i < SMU_LIMIT_TYPE_COUNT; i++) { 511 if (!(smu->ppt_limits.supported_mask & BIT(i))) 512 continue; 513 514 if (restore_mask & BIT(i)) { 515 limit = smu->user_dpm_profile.ppt_limits[power_source][i]; 516 } else if (restore_defaults) { 517 range = &smu->ppt_limits.range[power_source][i]; 518 limit = range->default_value; 519 } else { 520 continue; 521 } 522 523 ret = smu_set_ppt_limit(smu, i, limit); 524 if (ret) 525 dev_err(smu->adev->dev, 526 "Failed to restore PPT%d limit: %d\n", i, ret); 527 } 528 529 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 530 } 531 532 /** 533 * smu_restore_dpm_user_profile - reinstate user dpm profile 534 * 535 * @smu: smu_context pointer 536 * 537 * Restore saved user clock frequencies and fan settings. 538 */ 539 static void smu_restore_dpm_user_profile(struct smu_context *smu) 540 { 541 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 542 int ret = 0; 543 544 if (!smu->adev->in_suspend) 545 return; 546 547 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 548 return; 549 550 /* Enable restore flag */ 551 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 552 553 /* set the user dpm clock configurations */ 554 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 555 enum smu_clk_type clk_type; 556 557 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 558 /* 559 * Iterate over smu clk type and force the saved user clk 560 * configs, skip if clock dependency is enabled 561 */ 562 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 563 smu->user_dpm_profile.clk_mask[clk_type]) { 564 ret = smu_force_smuclk_levels(smu, clk_type, 565 smu->user_dpm_profile.clk_mask[clk_type]); 566 if (ret) 567 dev_err(smu->adev->dev, 568 "Failed to set clock type = %d\n", clk_type); 569 } 570 } 571 } 572 573 /* set the user dpm fan configurations */ 574 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 575 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 576 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 577 if (ret != -EOPNOTSUPP) { 578 smu->user_dpm_profile.fan_speed_pwm = 0; 579 smu->user_dpm_profile.fan_speed_rpm = 0; 580 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 581 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 582 } 583 584 if (smu->user_dpm_profile.fan_speed_pwm) { 585 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 586 if (ret != -EOPNOTSUPP) 587 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 588 } 589 590 if (smu->user_dpm_profile.fan_speed_rpm) { 591 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 592 if (ret != -EOPNOTSUPP) 593 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 594 } 595 } 596 597 /* Restore user customized OD settings */ 598 if (smu->user_dpm_profile.user_od) { 599 if (smu->ppt_funcs->restore_user_od_settings) { 600 ret = smu->ppt_funcs->restore_user_od_settings(smu); 601 if (ret) 602 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 603 } 604 } 605 606 /* Disable restore flag */ 607 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 608 } 609 610 static int smu_get_power_num_states(void *handle, 611 struct pp_states_info *state_info) 612 { 613 if (!state_info) 614 return -EINVAL; 615 616 /* not support power state */ 617 memset(state_info, 0, sizeof(struct pp_states_info)); 618 state_info->nums = 1; 619 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 620 621 return 0; 622 } 623 624 void amdgpu_smu_early_init(struct amdgpu_device *adev) 625 { 626 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 627 adev->is_sw_smu = adev->asic_type != CHIP_VEGA20 && 628 (amdgpu_ip_version(adev, MP1_HWIP, 0) >= 629 IP_VERSION(11, 0, 0) && 630 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)); 631 } 632 633 bool is_support_cclk_dpm(struct amdgpu_device *adev) 634 { 635 struct smu_context *smu = adev->powerplay.pp_handle; 636 637 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 638 return false; 639 640 return true; 641 } 642 643 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 644 uint32_t param, uint32_t *read_arg) 645 { 646 struct smu_context *smu = adev->powerplay.pp_handle; 647 int ret = -EOPNOTSUPP; 648 649 if (!smu) 650 return ret; 651 652 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 653 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 654 655 return ret; 656 } 657 658 int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, 659 enum smu_feature_mask mask) 660 { 661 struct smu_context *smu = adev->powerplay.pp_handle; 662 int ret = 0; 663 664 if (smu->ppt_funcs && smu->ppt_funcs->feature_is_enabled) 665 ret = smu->ppt_funcs->feature_is_enabled(smu, mask); 666 667 return ret; 668 } 669 670 static int smu_sys_get_pp_table(void *handle, 671 char **table) 672 { 673 struct smu_context *smu = handle; 674 struct smu_table_context *smu_table = &smu->smu_table; 675 676 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 677 return -EOPNOTSUPP; 678 679 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 680 return -EOPNOTSUPP; 681 682 if (smu_table->hardcode_pptable) 683 *table = smu_table->hardcode_pptable; 684 else 685 *table = smu_table->power_play_table; 686 687 return smu_table->power_play_table_size; 688 } 689 690 static int smu_sys_set_pp_table(void *handle, 691 const char *buf, 692 size_t size) 693 { 694 struct smu_context *smu = handle; 695 struct smu_table_context *smu_table = &smu->smu_table; 696 ATOM_COMMON_TABLE_HEADER *header; 697 void *hardcode_pptable; 698 int ret = 0; 699 700 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 701 return -EOPNOTSUPP; 702 703 if (!buf || size < sizeof(*header)) 704 return -EINVAL; 705 706 header = (ATOM_COMMON_TABLE_HEADER *)buf; 707 if (header->usStructureSize != size) { 708 dev_err(smu->adev->dev, "pp table size not matched !\n"); 709 return -EIO; 710 } 711 712 hardcode_pptable = kmemdup(buf, size, GFP_KERNEL); 713 if (!hardcode_pptable) 714 return -ENOMEM; 715 716 kfree(smu_table->hardcode_pptable); 717 smu_table->hardcode_pptable = hardcode_pptable; 718 smu_table->power_play_table = smu_table->hardcode_pptable; 719 smu_table->power_play_table_size = size; 720 memset(&smu->ppt_limits, 0, sizeof(smu->ppt_limits)); 721 722 /* 723 * Special hw_fini action(for Navi1x, the DPMs disablement will be 724 * skipped) may be needed for custom pptable uploading. 725 */ 726 smu->uploading_custom_pp_table = true; 727 728 ret = smu_reset(smu); 729 if (ret) 730 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 731 732 smu->uploading_custom_pp_table = false; 733 734 return ret; 735 } 736 737 static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) 738 { 739 /* 740 * With SCPM enabled, the allowed featuremasks setting(via 741 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 742 * That means there is no way to let PMFW knows the settings below. 743 * Thus, we just assume all the features are allowed under 744 * such scenario. 745 */ 746 if (smu->adev->scpm_enabled) { 747 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 748 return 0; 749 } 750 751 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 752 753 return smu_init_allowed_features(smu); 754 } 755 756 static int smu_set_funcs(struct amdgpu_device *adev) 757 { 758 struct smu_context *smu = adev->powerplay.pp_handle; 759 760 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 761 smu->od_enabled = true; 762 763 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 764 case IP_VERSION(11, 0, 0): 765 case IP_VERSION(11, 0, 5): 766 case IP_VERSION(11, 0, 9): 767 navi10_set_ppt_funcs(smu); 768 break; 769 case IP_VERSION(11, 0, 7): 770 case IP_VERSION(11, 0, 11): 771 case IP_VERSION(11, 0, 12): 772 case IP_VERSION(11, 0, 13): 773 sienna_cichlid_set_ppt_funcs(smu); 774 break; 775 case IP_VERSION(12, 0, 0): 776 case IP_VERSION(12, 0, 1): 777 renoir_set_ppt_funcs(smu); 778 break; 779 case IP_VERSION(11, 5, 0): 780 case IP_VERSION(11, 5, 2): 781 vangogh_set_ppt_funcs(smu); 782 break; 783 case IP_VERSION(13, 0, 1): 784 case IP_VERSION(13, 0, 3): 785 case IP_VERSION(13, 0, 8): 786 yellow_carp_set_ppt_funcs(smu); 787 break; 788 case IP_VERSION(13, 0, 4): 789 case IP_VERSION(13, 0, 11): 790 smu_v13_0_4_set_ppt_funcs(smu); 791 break; 792 case IP_VERSION(13, 0, 5): 793 smu_v13_0_5_set_ppt_funcs(smu); 794 break; 795 case IP_VERSION(11, 0, 8): 796 cyan_skillfish_set_ppt_funcs(smu); 797 break; 798 case IP_VERSION(11, 0, 2): 799 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 800 arcturus_set_ppt_funcs(smu); 801 /* OD is not supported on Arcturus */ 802 smu->od_enabled = false; 803 break; 804 case IP_VERSION(13, 0, 2): 805 aldebaran_set_ppt_funcs(smu); 806 /* Enable pp_od_clk_voltage node */ 807 smu->od_enabled = true; 808 break; 809 case IP_VERSION(13, 0, 0): 810 case IP_VERSION(13, 0, 10): 811 smu_v13_0_0_set_ppt_funcs(smu); 812 break; 813 case IP_VERSION(13, 0, 6): 814 case IP_VERSION(13, 0, 14): 815 case IP_VERSION(13, 0, 12): 816 smu_v13_0_6_set_ppt_funcs(smu); 817 /* Enable pp_od_clk_voltage node */ 818 smu->od_enabled = true; 819 break; 820 case IP_VERSION(13, 0, 7): 821 smu_v13_0_7_set_ppt_funcs(smu); 822 break; 823 case IP_VERSION(14, 0, 0): 824 case IP_VERSION(14, 0, 1): 825 case IP_VERSION(14, 0, 4): 826 case IP_VERSION(14, 0, 5): 827 smu_v14_0_0_set_ppt_funcs(smu); 828 break; 829 case IP_VERSION(14, 0, 2): 830 case IP_VERSION(14, 0, 3): 831 smu_v14_0_2_set_ppt_funcs(smu); 832 break; 833 case IP_VERSION(15, 0, 0): 834 case IP_VERSION(15, 0, 5): 835 case IP_VERSION(15, 0, 9): 836 smu_v15_0_0_set_ppt_funcs(smu); 837 break; 838 case IP_VERSION(15, 0, 8): 839 smu_v15_0_8_set_ppt_funcs(smu); 840 smu->od_enabled = true; 841 break; 842 default: 843 return -EINVAL; 844 } 845 846 return 0; 847 } 848 849 static int smu_early_init(struct amdgpu_ip_block *ip_block) 850 { 851 struct amdgpu_device *adev = ip_block->adev; 852 struct smu_context *smu; 853 int r; 854 855 smu = kzalloc_obj(struct smu_context); 856 if (!smu) 857 return -ENOMEM; 858 859 smu->adev = adev; 860 smu->pm_enabled = !!amdgpu_dpm; 861 smu->is_apu = false; 862 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 863 smu->smu_baco.platform_support = false; 864 smu->smu_baco.maco_support = false; 865 smu->user_dpm_profile.fan_mode = -1; 866 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 867 868 adev->powerplay.pp_handle = smu; 869 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 870 871 r = smu_set_funcs(adev); 872 if (r) 873 return r; 874 return smu_init_microcode(smu); 875 } 876 877 static int smu_set_default_dpm_table(struct smu_context *smu) 878 { 879 struct amdgpu_device *adev = smu->adev; 880 struct smu_power_context *smu_power = &smu->smu_power; 881 struct smu_power_gate *power_gate = &smu_power->power_gate; 882 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 883 int ret = 0; 884 885 if (!smu->ppt_funcs->set_default_dpm_table) 886 return 0; 887 888 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 889 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 890 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 891 } 892 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 893 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 894 895 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 896 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 897 ret = smu_dpm_set_vcn_enable(smu, true, i); 898 if (ret) 899 return ret; 900 } 901 } 902 903 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 904 ret = smu_dpm_set_jpeg_enable(smu, true); 905 if (ret) 906 goto err_out; 907 } 908 909 ret = smu->ppt_funcs->set_default_dpm_table(smu); 910 if (ret) 911 dev_err(smu->adev->dev, 912 "Failed to setup default dpm clock tables!\n"); 913 914 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 915 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 916 err_out: 917 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 918 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 919 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 920 } 921 922 return ret; 923 } 924 925 static int smu_apply_default_config_table_settings(struct smu_context *smu) 926 { 927 struct amdgpu_device *adev = smu->adev; 928 int ret = 0; 929 930 ret = smu_get_default_config_table_settings(smu, 931 &adev->pm.config_table); 932 if (ret) 933 return ret; 934 935 return smu_set_config_table(smu, &adev->pm.config_table); 936 } 937 938 static int smu_late_init(struct amdgpu_ip_block *ip_block) 939 { 940 struct amdgpu_device *adev = ip_block->adev; 941 struct smu_context *smu = adev->powerplay.pp_handle; 942 int ret = 0; 943 944 smu_set_fine_grain_gfx_freq_parameters(smu); 945 946 if (!smu->pm_enabled) 947 return 0; 948 949 ret = smu_post_init(smu); 950 if (ret) { 951 dev_err(adev->dev, "Failed to post smu init!\n"); 952 return ret; 953 } 954 955 /* 956 * Explicitly notify PMFW the power mode the system in. Since 957 * the PMFW may boot the ASIC with a different mode. 958 * For those supporting ACDC switch via gpio, PMFW will 959 * handle the switch automatically. Driver involvement 960 * is unnecessary. 961 */ 962 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 963 smu_set_ac_dc(smu, false); 964 965 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 966 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 967 return 0; 968 969 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 970 ret = smu_set_default_od_settings(smu); 971 if (ret) { 972 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 973 return ret; 974 } 975 } 976 977 ret = smu_populate_umd_state_clk(smu); 978 if (ret) { 979 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 980 return ret; 981 } 982 983 if (!amdgpu_sriov_vf(adev)) 984 smu_get_unique_id(smu); 985 986 smu_get_fan_parameters(smu); 987 988 smu_handle_task(smu, 989 smu->smu_dpm.dpm_level, 990 AMD_PP_TASK_COMPLETE_INIT); 991 992 ret = smu_apply_default_config_table_settings(smu); 993 if (ret && (ret != -EOPNOTSUPP)) { 994 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 995 return ret; 996 } 997 998 if (adev->in_suspend || amdgpu_reset_in_recovery(adev)) 999 smu_restore_ppt_limits(smu, false); 1000 smu_restore_dpm_user_profile(smu); 1001 1002 return 0; 1003 } 1004 1005 static int smu_init_fb_allocations(struct smu_context *smu) 1006 { 1007 struct amdgpu_device *adev = smu->adev; 1008 struct smu_table_context *smu_table = &smu->smu_table; 1009 struct smu_table *tables = smu_table->tables; 1010 struct smu_table *driver_table = &(smu_table->driver_table); 1011 uint32_t max_table_size = 0; 1012 int ret, i; 1013 1014 /* VRAM allocation for tool table */ 1015 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 1016 ret = amdgpu_bo_create_kernel(adev, 1017 tables[SMU_TABLE_PMSTATUSLOG].size, 1018 tables[SMU_TABLE_PMSTATUSLOG].align, 1019 tables[SMU_TABLE_PMSTATUSLOG].domain, 1020 &tables[SMU_TABLE_PMSTATUSLOG].bo, 1021 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1022 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1023 if (ret) { 1024 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 1025 return ret; 1026 } 1027 } 1028 1029 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 1030 /* VRAM allocation for driver table */ 1031 for (i = 0; i < SMU_TABLE_COUNT; i++) { 1032 if (tables[i].size == 0) 1033 continue; 1034 1035 /* If one of the tables has VRAM domain restriction, keep it in 1036 * VRAM 1037 */ 1038 if ((tables[i].domain & 1039 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 1040 AMDGPU_GEM_DOMAIN_VRAM) 1041 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 1042 1043 if (i == SMU_TABLE_PMSTATUSLOG) 1044 continue; 1045 1046 if (max_table_size < tables[i].size) 1047 max_table_size = tables[i].size; 1048 } 1049 1050 driver_table->size = max_table_size; 1051 driver_table->align = PAGE_SIZE; 1052 1053 ret = amdgpu_bo_create_kernel(adev, 1054 driver_table->size, 1055 driver_table->align, 1056 driver_table->domain, 1057 &driver_table->bo, 1058 &driver_table->mc_address, 1059 &driver_table->cpu_addr); 1060 if (ret) { 1061 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 1062 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1063 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1064 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1065 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1066 } 1067 1068 return ret; 1069 } 1070 1071 static int smu_fini_fb_allocations(struct smu_context *smu) 1072 { 1073 struct smu_table_context *smu_table = &smu->smu_table; 1074 struct smu_table *tables = smu_table->tables; 1075 struct smu_table *driver_table = &(smu_table->driver_table); 1076 1077 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1078 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1079 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1080 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1081 1082 amdgpu_bo_free_kernel(&driver_table->bo, 1083 &driver_table->mc_address, 1084 &driver_table->cpu_addr); 1085 1086 return 0; 1087 } 1088 1089 static void smu_update_gpu_addresses(struct smu_context *smu) 1090 { 1091 struct smu_table_context *smu_table = &smu->smu_table; 1092 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1093 struct smu_table *driver_table = &(smu_table->driver_table); 1094 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1095 1096 if (pm_status_table->bo) 1097 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1098 if (driver_table->bo) 1099 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1100 if (dummy_read_1_table->bo) 1101 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1102 } 1103 1104 /** 1105 * smu_alloc_memory_pool - allocate memory pool in the system memory 1106 * 1107 * @smu: amdgpu_device pointer 1108 * 1109 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1110 * and DramLogSetDramAddr can notify it changed. 1111 * 1112 * Returns 0 on success, error on failure. 1113 */ 1114 static int smu_alloc_memory_pool(struct smu_context *smu) 1115 { 1116 struct amdgpu_device *adev = smu->adev; 1117 struct smu_table_context *smu_table = &smu->smu_table; 1118 struct smu_table *memory_pool = &smu_table->memory_pool; 1119 uint64_t pool_size = smu->pool_size; 1120 int ret = 0; 1121 1122 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1123 return ret; 1124 1125 memory_pool->size = pool_size; 1126 memory_pool->align = PAGE_SIZE; 1127 memory_pool->domain = 1128 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1129 AMDGPU_GEM_DOMAIN_VRAM : 1130 AMDGPU_GEM_DOMAIN_GTT; 1131 1132 switch (pool_size) { 1133 case SMU_MEMORY_POOL_SIZE_256_MB: 1134 case SMU_MEMORY_POOL_SIZE_512_MB: 1135 case SMU_MEMORY_POOL_SIZE_1_GB: 1136 case SMU_MEMORY_POOL_SIZE_2_GB: 1137 ret = amdgpu_bo_create_kernel(adev, 1138 memory_pool->size, 1139 memory_pool->align, 1140 memory_pool->domain, 1141 &memory_pool->bo, 1142 &memory_pool->mc_address, 1143 &memory_pool->cpu_addr); 1144 if (ret) 1145 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1146 break; 1147 default: 1148 break; 1149 } 1150 1151 return ret; 1152 } 1153 1154 static int smu_free_memory_pool(struct smu_context *smu) 1155 { 1156 struct smu_table_context *smu_table = &smu->smu_table; 1157 struct smu_table *memory_pool = &smu_table->memory_pool; 1158 1159 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1160 return 0; 1161 1162 amdgpu_bo_free_kernel(&memory_pool->bo, 1163 &memory_pool->mc_address, 1164 &memory_pool->cpu_addr); 1165 1166 memset(memory_pool, 0, sizeof(struct smu_table)); 1167 1168 return 0; 1169 } 1170 1171 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1172 { 1173 struct smu_table_context *smu_table = &smu->smu_table; 1174 struct smu_table *dummy_read_1_table = 1175 &smu_table->dummy_read_1_table; 1176 struct amdgpu_device *adev = smu->adev; 1177 int ret = 0; 1178 1179 if (!dummy_read_1_table->size) 1180 return 0; 1181 1182 ret = amdgpu_bo_create_kernel(adev, 1183 dummy_read_1_table->size, 1184 dummy_read_1_table->align, 1185 dummy_read_1_table->domain, 1186 &dummy_read_1_table->bo, 1187 &dummy_read_1_table->mc_address, 1188 &dummy_read_1_table->cpu_addr); 1189 if (ret) 1190 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1191 1192 return ret; 1193 } 1194 1195 static void smu_free_dummy_read_table(struct smu_context *smu) 1196 { 1197 struct smu_table_context *smu_table = &smu->smu_table; 1198 struct smu_table *dummy_read_1_table = 1199 &smu_table->dummy_read_1_table; 1200 1201 1202 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1203 &dummy_read_1_table->mc_address, 1204 &dummy_read_1_table->cpu_addr); 1205 1206 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1207 } 1208 1209 static int smu_smc_table_sw_init(struct smu_context *smu) 1210 { 1211 int ret; 1212 1213 /** 1214 * Create smu_table structure, and init smc tables such as 1215 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1216 */ 1217 ret = smu_init_smc_tables(smu); 1218 if (ret) { 1219 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1220 return ret; 1221 } 1222 1223 /** 1224 * Create smu_power_context structure, and allocate smu_dpm_context and 1225 * context size to fill the smu_power_context data. 1226 */ 1227 ret = smu_init_power(smu); 1228 if (ret) { 1229 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1230 return ret; 1231 } 1232 1233 /* 1234 * allocate vram bos to store smc table contents. 1235 */ 1236 ret = smu_init_fb_allocations(smu); 1237 if (ret) 1238 return ret; 1239 1240 ret = smu_alloc_memory_pool(smu); 1241 if (ret) 1242 return ret; 1243 1244 ret = smu_alloc_dummy_read_table(smu); 1245 if (ret) 1246 return ret; 1247 1248 ret = smu_i2c_init(smu); 1249 if (ret) 1250 return ret; 1251 1252 return 0; 1253 } 1254 1255 static int smu_smc_table_sw_fini(struct smu_context *smu) 1256 { 1257 int ret; 1258 1259 smu_i2c_fini(smu); 1260 1261 smu_free_dummy_read_table(smu); 1262 1263 ret = smu_free_memory_pool(smu); 1264 if (ret) 1265 return ret; 1266 1267 ret = smu_fini_fb_allocations(smu); 1268 if (ret) 1269 return ret; 1270 1271 ret = smu_fini_power(smu); 1272 if (ret) { 1273 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1274 return ret; 1275 } 1276 1277 ret = smu_fini_smc_tables(smu); 1278 if (ret) { 1279 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1280 return ret; 1281 } 1282 1283 return 0; 1284 } 1285 1286 static void smu_throttling_logging_work_fn(struct work_struct *work) 1287 { 1288 struct smu_context *smu = container_of(work, struct smu_context, 1289 throttling_logging_work); 1290 1291 smu_log_thermal_throttling(smu); 1292 } 1293 1294 static void smu_interrupt_work_fn(struct work_struct *work) 1295 { 1296 struct smu_context *smu = container_of(work, struct smu_context, 1297 interrupt_work); 1298 1299 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1300 smu->ppt_funcs->interrupt_work(smu); 1301 } 1302 1303 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1304 { 1305 struct smu_context *smu = 1306 container_of(work, struct smu_context, swctf_delayed_work.work); 1307 struct smu_temperature_range *range = 1308 &smu->thermal_range; 1309 struct amdgpu_device *adev = smu->adev; 1310 uint32_t hotspot_tmp, size; 1311 1312 /* 1313 * If the hotspot temperature is confirmed as below SW CTF setting point 1314 * after the delay enforced, nothing will be done. 1315 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1316 */ 1317 if (range->software_shutdown_temp && 1318 smu->ppt_funcs->read_sensor && 1319 !smu->ppt_funcs->read_sensor(smu, 1320 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1321 &hotspot_tmp, 1322 &size) && 1323 hotspot_tmp / 1000 < range->software_shutdown_temp) 1324 return; 1325 1326 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1327 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1328 orderly_poweroff(true); 1329 } 1330 1331 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1332 { 1333 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1334 struct smu_dpm_policy_ctxt *policy_ctxt; 1335 struct smu_dpm_policy *policy; 1336 1337 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1338 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1339 if (policy) 1340 policy->current_level = XGMI_PLPD_DEFAULT; 1341 return; 1342 } 1343 1344 /* PMFW put PLPD into default policy after enabling the feature */ 1345 if (smu_feature_is_enabled(smu, 1346 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1347 if (policy) 1348 policy->current_level = XGMI_PLPD_DEFAULT; 1349 } else { 1350 policy_ctxt = dpm_ctxt->dpm_policies; 1351 if (policy_ctxt) 1352 policy_ctxt->policy_mask &= 1353 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1354 } 1355 } 1356 1357 static void smu_init_power_profile(struct smu_context *smu) 1358 { 1359 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1360 smu->power_profile_mode = 1361 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1362 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1363 } 1364 1365 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1366 { 1367 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1368 1369 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1370 return; 1371 1372 set_bit(fea_id, fea_cap->cap_map); 1373 } 1374 1375 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1376 { 1377 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1378 1379 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1380 return false; 1381 1382 return test_bit(fea_id, fea_cap->cap_map); 1383 } 1384 1385 static void smu_feature_cap_init(struct smu_context *smu) 1386 { 1387 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1388 1389 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT); 1390 } 1391 1392 static int smu_set_power_dep(struct smu_context *smu, bool enable) 1393 { 1394 if (!smu->ppt_funcs->set_power_dep) 1395 return 0; 1396 1397 return smu->ppt_funcs->set_power_dep(smu, enable); 1398 } 1399 1400 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1401 { 1402 struct amdgpu_device *adev = ip_block->adev; 1403 struct smu_context *smu = adev->powerplay.pp_handle; 1404 int i, ret; 1405 1406 smu->pool_size = adev->pm.smu_prv_buffer_size; 1407 smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT); 1408 1409 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1410 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1411 atomic64_set(&smu->throttle_int_counter, 0); 1412 smu->watermarks_bitmap = 0; 1413 1414 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1415 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1416 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1417 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1418 atomic_set(&smu->smu_power.power_gate.isp_gated, 1); 1419 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1420 1421 smu_init_power_profile(smu); 1422 smu->display_config = &adev->pm.pm_display_cfg; 1423 1424 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1425 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1426 1427 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1428 smu_swctf_delayed_work_handler); 1429 1430 smu_feature_cap_init(smu); 1431 1432 ret = smu_smc_table_sw_init(smu); 1433 if (ret) { 1434 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1435 return ret; 1436 } 1437 1438 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1439 ret = smu_get_vbios_bootup_values(smu); 1440 if (ret) { 1441 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1442 return ret; 1443 } 1444 1445 ret = smu_init_pptable_microcode(smu); 1446 if (ret) { 1447 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1448 return ret; 1449 } 1450 1451 ret = smu_register_irq_handler(smu); 1452 if (ret) { 1453 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1454 return ret; 1455 } 1456 1457 /* If there is no way to query fan control mode, fan control is not supported */ 1458 if (!smu->ppt_funcs->get_fan_control_mode) 1459 smu->adev->pm.no_fan = true; 1460 1461 smu_set_power_dep(smu, true); 1462 1463 return 0; 1464 } 1465 1466 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1467 { 1468 struct amdgpu_device *adev = ip_block->adev; 1469 struct smu_context *smu = adev->powerplay.pp_handle; 1470 int ret; 1471 1472 ret = smu_smc_table_sw_fini(smu); 1473 if (ret) { 1474 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1475 return ret; 1476 } 1477 1478 if (smu->custom_profile_params) { 1479 kfree(smu->custom_profile_params); 1480 smu->custom_profile_params = NULL; 1481 } 1482 1483 smu_fini_microcode(smu); 1484 1485 smu_set_power_dep(smu, false); 1486 1487 return 0; 1488 } 1489 1490 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1491 { 1492 struct amdgpu_device *adev = smu->adev; 1493 struct smu_temperature_range *range = 1494 &smu->thermal_range; 1495 int ret = 0; 1496 1497 if (!smu->ppt_funcs->get_thermal_temperature_range) 1498 return 0; 1499 1500 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1501 if (ret) 1502 return ret; 1503 1504 adev->pm.dpm.thermal.min_temp = range->min; 1505 adev->pm.dpm.thermal.max_temp = range->max; 1506 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1507 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1508 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1509 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1510 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1511 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1512 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1513 1514 return ret; 1515 } 1516 1517 /** 1518 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1519 * 1520 * @smu: smu_context pointer 1521 * 1522 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1523 * Returns 0 on success, error on failure. 1524 */ 1525 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1526 { 1527 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1528 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1529 struct amdgpu_device *adev = smu->adev; 1530 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1531 uint64_t start, end; 1532 int ret, i, j; 1533 1534 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1535 if (ret) { 1536 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1537 return ret; 1538 } 1539 1540 /* 1541 * The exclusion ranges array we got might be filled with holes and duplicate 1542 * entries. For example: 1543 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1544 * We need to do some sortups to eliminate those holes and duplicate entries. 1545 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1546 */ 1547 for (i = 0; i < num_of_wbrf_ranges; i++) { 1548 start = wifi_bands[i].start; 1549 end = wifi_bands[i].end; 1550 1551 /* get the last valid entry to fill the intermediate hole */ 1552 if (!start && !end) { 1553 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1554 if (wifi_bands[j].start && wifi_bands[j].end) 1555 break; 1556 1557 /* no valid entry left */ 1558 if (j <= i) 1559 break; 1560 1561 start = wifi_bands[i].start = wifi_bands[j].start; 1562 end = wifi_bands[i].end = wifi_bands[j].end; 1563 wifi_bands[j].start = 0; 1564 wifi_bands[j].end = 0; 1565 num_of_wbrf_ranges = j; 1566 } 1567 1568 /* eliminate duplicate entries */ 1569 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1570 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1571 wifi_bands[j].start = 0; 1572 wifi_bands[j].end = 0; 1573 } 1574 } 1575 } 1576 1577 /* Send the sorted wifi_bands to PMFW */ 1578 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1579 /* Try to set the wifi_bands again */ 1580 if (unlikely(ret == -EBUSY)) { 1581 mdelay(5); 1582 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1583 } 1584 1585 return ret; 1586 } 1587 1588 /** 1589 * smu_wbrf_event_handler - handle notify events 1590 * 1591 * @nb: notifier block 1592 * @action: event type 1593 * @_arg: event data 1594 * 1595 * Calls relevant amdgpu function in response to wbrf event 1596 * notification from kernel. 1597 */ 1598 static int smu_wbrf_event_handler(struct notifier_block *nb, 1599 unsigned long action, void *_arg) 1600 { 1601 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1602 1603 switch (action) { 1604 case WBRF_CHANGED: 1605 schedule_delayed_work(&smu->wbrf_delayed_work, 1606 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1607 break; 1608 default: 1609 return NOTIFY_DONE; 1610 } 1611 1612 return NOTIFY_OK; 1613 } 1614 1615 /** 1616 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1617 * 1618 * @work: struct work_struct pointer 1619 * 1620 * Flood is over and driver will consume the latest exclusion ranges. 1621 */ 1622 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1623 { 1624 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1625 1626 smu_wbrf_handle_exclusion_ranges(smu); 1627 } 1628 1629 /** 1630 * smu_wbrf_support_check - check wbrf support 1631 * 1632 * @smu: smu_context pointer 1633 * 1634 * Verifies the ACPI interface whether wbrf is supported. 1635 */ 1636 static void smu_wbrf_support_check(struct smu_context *smu) 1637 { 1638 struct amdgpu_device *adev = smu->adev; 1639 1640 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1641 acpi_amd_wbrf_supported_consumer(adev->dev); 1642 1643 if (smu->wbrf_supported) 1644 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1645 } 1646 1647 /** 1648 * smu_wbrf_init - init driver wbrf support 1649 * 1650 * @smu: smu_context pointer 1651 * 1652 * Verifies the AMD ACPI interfaces and registers with the wbrf 1653 * notifier chain if wbrf feature is supported. 1654 * Returns 0 on success, error on failure. 1655 */ 1656 static int smu_wbrf_init(struct smu_context *smu) 1657 { 1658 int ret; 1659 1660 if (!smu->wbrf_supported) 1661 return 0; 1662 1663 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1664 1665 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1666 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1667 if (ret) 1668 return ret; 1669 1670 /* 1671 * Some wifiband exclusion ranges may be already there 1672 * before our driver loaded. To make sure our driver 1673 * is awared of those exclusion ranges. 1674 */ 1675 schedule_delayed_work(&smu->wbrf_delayed_work, 1676 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1677 1678 return 0; 1679 } 1680 1681 /** 1682 * smu_wbrf_fini - tear down driver wbrf support 1683 * 1684 * @smu: smu_context pointer 1685 * 1686 * Unregisters with the wbrf notifier chain. 1687 */ 1688 static void smu_wbrf_fini(struct smu_context *smu) 1689 { 1690 if (!smu->wbrf_supported) 1691 return; 1692 1693 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1694 1695 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1696 } 1697 1698 static int smu_smc_hw_setup(struct smu_context *smu) 1699 { 1700 struct amdgpu_device *adev = smu->adev; 1701 uint8_t pcie_gen = 0, pcie_width = 0; 1702 struct smu_feature_bits features_supported; 1703 int ret = 0; 1704 1705 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1706 case IP_VERSION(11, 0, 7): 1707 case IP_VERSION(11, 0, 11): 1708 case IP_VERSION(11, 5, 0): 1709 case IP_VERSION(11, 5, 2): 1710 case IP_VERSION(11, 0, 12): 1711 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1712 dev_info(adev->dev, "dpm has been enabled\n"); 1713 ret = smu_system_features_control(smu, true); 1714 if (ret) { 1715 dev_err(adev->dev, "Failed system features control!\n"); 1716 return ret; 1717 } 1718 1719 return smu_enable_thermal_alert(smu); 1720 } 1721 break; 1722 default: 1723 break; 1724 } 1725 1726 ret = smu_init_display_count(smu, 0); 1727 if (ret) { 1728 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1729 return ret; 1730 } 1731 1732 ret = smu_set_driver_table_location(smu); 1733 if (ret) { 1734 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1735 return ret; 1736 } 1737 1738 /* 1739 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1740 */ 1741 ret = smu_set_tool_table_location(smu); 1742 if (ret) { 1743 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1744 return ret; 1745 } 1746 1747 /* 1748 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1749 * pool location. 1750 */ 1751 ret = smu_notify_memory_pool_location(smu); 1752 if (ret) { 1753 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1754 return ret; 1755 } 1756 1757 /* 1758 * It is assumed the pptable used before runpm is same as 1759 * the one used afterwards. Thus, we can reuse the stored 1760 * copy and do not need to resetup the pptable again. 1761 */ 1762 if (!adev->in_runpm) { 1763 ret = smu_setup_pptable(smu); 1764 if (ret) { 1765 dev_err(adev->dev, "Failed to setup pptable!\n"); 1766 return ret; 1767 } 1768 } 1769 1770 /* smu_dump_pptable(smu); */ 1771 1772 /* 1773 * With SCPM enabled, PSP is responsible for the PPTable transferring 1774 * (to SMU). Driver involvement is not needed and permitted. 1775 */ 1776 if (!adev->scpm_enabled) { 1777 /* 1778 * Copy pptable bo in the vram to smc with SMU MSGs such as 1779 * SetDriverDramAddr and TransferTableDram2Smu. 1780 */ 1781 ret = smu_write_pptable(smu); 1782 if (ret) { 1783 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1784 return ret; 1785 } 1786 } 1787 1788 /* issue Run*Btc msg */ 1789 ret = smu_run_btc(smu); 1790 if (ret) 1791 return ret; 1792 1793 /* Enable UclkShadow on wbrf supported */ 1794 if (smu->wbrf_supported) { 1795 ret = smu_enable_uclk_shadow(smu, true); 1796 if (ret) { 1797 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1798 return ret; 1799 } 1800 } 1801 1802 /* 1803 * With SCPM enabled, these actions(and relevant messages) are 1804 * not needed and permitted. 1805 */ 1806 if (!adev->scpm_enabled) { 1807 ret = smu_feature_set_allowed_mask(smu); 1808 if (ret) { 1809 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1810 return ret; 1811 } 1812 } 1813 1814 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1815 pcie_gen = 4; 1816 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1817 pcie_gen = 3; 1818 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1819 pcie_gen = 2; 1820 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1821 pcie_gen = 1; 1822 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1823 pcie_gen = 0; 1824 1825 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1826 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1827 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1828 */ 1829 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1830 pcie_width = 7; 1831 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1832 pcie_width = 6; 1833 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1834 pcie_width = 5; 1835 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1836 pcie_width = 4; 1837 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1838 pcie_width = 3; 1839 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1840 pcie_width = 2; 1841 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1842 pcie_width = 1; 1843 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1844 if (ret) { 1845 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1846 return ret; 1847 } 1848 1849 ret = smu_system_features_control(smu, true); 1850 if (ret) { 1851 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1852 return ret; 1853 } 1854 1855 smu_init_xgmi_plpd_mode(smu); 1856 1857 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1858 if (ret) { 1859 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1860 return ret; 1861 } 1862 smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, 1863 features_supported.bits); 1864 1865 if (!smu_is_dpm_running(smu)) 1866 dev_info(adev->dev, "dpm has been disabled\n"); 1867 1868 /* 1869 * Set initialized values (get from vbios) to dpm tables context such as 1870 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1871 * type of clks. 1872 */ 1873 ret = smu_set_default_dpm_table(smu); 1874 if (ret) { 1875 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1876 return ret; 1877 } 1878 1879 ret = smu_get_thermal_temperature_range(smu); 1880 if (ret) { 1881 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1882 return ret; 1883 } 1884 1885 ret = smu_enable_thermal_alert(smu); 1886 if (ret) { 1887 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1888 return ret; 1889 } 1890 1891 ret = smu_notify_display_change(smu); 1892 if (ret) { 1893 dev_err(adev->dev, "Failed to notify display change!\n"); 1894 return ret; 1895 } 1896 1897 /* 1898 * Set min deep sleep dce fclk with bootup value from vbios via 1899 * SetMinDeepSleepDcefclk MSG. 1900 */ 1901 ret = smu_set_min_dcef_deep_sleep(smu, 1902 smu->smu_table.boot_values.dcefclk / 100); 1903 if (ret) { 1904 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1905 return ret; 1906 } 1907 1908 /* Init wbrf support. Properly setup the notifier */ 1909 ret = smu_wbrf_init(smu); 1910 if (ret) 1911 dev_err(adev->dev, "Error during wbrf init call\n"); 1912 1913 return ret; 1914 } 1915 1916 static int smu_start_smc_engine(struct smu_context *smu) 1917 { 1918 struct amdgpu_device *adev = smu->adev; 1919 int ret = 0; 1920 1921 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1922 smu_update_gpu_addresses(smu); 1923 1924 smu->smc_fw_state = SMU_FW_INIT; 1925 1926 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1927 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1928 if (smu->ppt_funcs->load_microcode) { 1929 ret = smu->ppt_funcs->load_microcode(smu); 1930 if (ret) 1931 return ret; 1932 } 1933 } 1934 } 1935 1936 if (smu->ppt_funcs->check_fw_status) { 1937 ret = smu->ppt_funcs->check_fw_status(smu); 1938 if (ret) { 1939 dev_err(adev->dev, "SMC is not ready\n"); 1940 return ret; 1941 } 1942 } 1943 1944 /* 1945 * Send msg GetDriverIfVersion to check if the return value is equal 1946 * with DRIVER_IF_VERSION of smc header. 1947 */ 1948 ret = smu_check_fw_version(smu); 1949 if (ret) 1950 return ret; 1951 1952 return ret; 1953 } 1954 1955 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1956 { 1957 int i, ret; 1958 struct amdgpu_device *adev = ip_block->adev; 1959 struct smu_context *smu = adev->powerplay.pp_handle; 1960 1961 if (amdgpu_sriov_multi_vf_mode(adev)) { 1962 smu->pm_enabled = false; 1963 return 0; 1964 } 1965 1966 ret = smu_start_smc_engine(smu); 1967 if (ret) { 1968 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1969 return ret; 1970 } 1971 1972 /* 1973 * Check whether wbrf is supported. This needs to be done 1974 * before SMU setup starts since part of SMU configuration 1975 * relies on this. 1976 */ 1977 smu_wbrf_support_check(smu); 1978 1979 if (smu->is_apu) { 1980 ret = smu_set_gfx_imu_enable(smu); 1981 if (ret) 1982 return ret; 1983 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1984 smu_dpm_set_vcn_enable(smu, true, i); 1985 smu_dpm_set_jpeg_enable(smu, true); 1986 smu_dpm_set_umsch_mm_enable(smu, true); 1987 smu_set_mall_enable(smu); 1988 smu_set_gfx_cgpg(smu, true); 1989 } 1990 1991 if (!smu->pm_enabled) 1992 return 0; 1993 1994 ret = smu_init_driver_allowed_feature_mask(smu); 1995 if (ret) 1996 return ret; 1997 1998 ret = smu_smc_hw_setup(smu); 1999 if (ret) { 2000 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2001 return ret; 2002 } 2003 2004 /* 2005 * Move maximum sustainable clock retrieving here considering 2006 * 1. It is not needed on resume(from S3). 2007 * 2. DAL settings come between .hw_init and .late_init of SMU. 2008 * And DAL needs to know the maximum sustainable clocks. Thus 2009 * it cannot be put in .late_init(). 2010 */ 2011 ret = smu_init_max_sustainable_clocks(smu); 2012 if (ret) { 2013 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 2014 return ret; 2015 } 2016 2017 adev->pm.dpm_enabled = true; 2018 2019 dev_info(adev->dev, "SMU is initialized successfully!\n"); 2020 2021 return 0; 2022 } 2023 2024 static int smu_disable_dpms(struct smu_context *smu) 2025 { 2026 struct amdgpu_device *adev = smu->adev; 2027 int ret = 0; 2028 bool use_baco = !smu->is_apu && 2029 ((amdgpu_in_reset(adev) && 2030 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 2031 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 2032 2033 /* 2034 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 2035 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 2036 */ 2037 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2038 case IP_VERSION(13, 0, 0): 2039 case IP_VERSION(13, 0, 7): 2040 case IP_VERSION(13, 0, 10): 2041 case IP_VERSION(14, 0, 2): 2042 case IP_VERSION(14, 0, 3): 2043 return 0; 2044 default: 2045 break; 2046 } 2047 2048 /* 2049 * For custom pptable uploading, skip the DPM features 2050 * disable process on Navi1x ASICs. 2051 * - As the gfx related features are under control of 2052 * RLC on those ASICs. RLC reinitialization will be 2053 * needed to reenable them. That will cost much more 2054 * efforts. 2055 * 2056 * - SMU firmware can handle the DPM reenablement 2057 * properly. 2058 */ 2059 if (smu->uploading_custom_pp_table) { 2060 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2061 case IP_VERSION(11, 0, 0): 2062 case IP_VERSION(11, 0, 5): 2063 case IP_VERSION(11, 0, 9): 2064 case IP_VERSION(11, 0, 7): 2065 case IP_VERSION(11, 0, 11): 2066 case IP_VERSION(11, 5, 0): 2067 case IP_VERSION(11, 5, 2): 2068 case IP_VERSION(11, 0, 12): 2069 case IP_VERSION(11, 0, 13): 2070 return 0; 2071 default: 2072 break; 2073 } 2074 } 2075 2076 /* 2077 * For Sienna_Cichlid, PMFW will handle the features disablement properly 2078 * on BACO in. Driver involvement is unnecessary. 2079 */ 2080 if (use_baco) { 2081 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2082 case IP_VERSION(11, 0, 7): 2083 case IP_VERSION(11, 0, 0): 2084 case IP_VERSION(11, 0, 5): 2085 case IP_VERSION(11, 0, 9): 2086 case IP_VERSION(13, 0, 7): 2087 return 0; 2088 default: 2089 break; 2090 } 2091 } 2092 2093 /* 2094 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 2095 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 2096 */ 2097 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 2098 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2099 return 0; 2100 2101 /* vangogh s0ix */ 2102 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2103 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2104 adev->in_s0ix) 2105 return 0; 2106 2107 /* 2108 * For gpu reset, runpm and hibernation through BACO, 2109 * BACO feature has to be kept enabled. 2110 */ 2111 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 2112 ret = smu_disable_all_features_with_exception(smu, 2113 SMU_FEATURE_BACO_BIT); 2114 if (ret) 2115 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 2116 } else { 2117 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 2118 if (!adev->scpm_enabled) { 2119 ret = smu_system_features_control(smu, false); 2120 if (ret) 2121 dev_err(adev->dev, "Failed to disable smu features.\n"); 2122 } 2123 } 2124 2125 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 2126 * otherwise SMU will hang while interacting with RLC if RLC is halted 2127 * this is a WA for Vangogh asic which fix the SMU hang issue. 2128 */ 2129 ret = smu_notify_rlc_state(smu, false); 2130 if (ret) { 2131 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2132 return ret; 2133 } 2134 2135 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2136 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2137 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2138 adev->gfx.rlc.funcs->stop(adev); 2139 2140 return ret; 2141 } 2142 2143 static int smu_smc_hw_cleanup(struct smu_context *smu) 2144 { 2145 struct amdgpu_device *adev = smu->adev; 2146 int ret = 0; 2147 2148 smu_wbrf_fini(smu); 2149 2150 cancel_work_sync(&smu->throttling_logging_work); 2151 cancel_work_sync(&smu->interrupt_work); 2152 2153 ret = smu_disable_thermal_alert(smu); 2154 if (ret) { 2155 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2156 return ret; 2157 } 2158 2159 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2160 2161 ret = smu_disable_dpms(smu); 2162 if (ret) { 2163 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2164 return ret; 2165 } 2166 2167 return 0; 2168 } 2169 2170 static int smu_reset_mp1_state(struct smu_context *smu) 2171 { 2172 struct amdgpu_device *adev = smu->adev; 2173 int ret = 0; 2174 2175 if ((!adev->in_runpm) && (!adev->in_suspend) && 2176 (!amdgpu_in_reset(adev)) && !smu->is_apu && 2177 amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0)) 2178 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2179 2180 return ret; 2181 } 2182 2183 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2184 { 2185 struct amdgpu_device *adev = ip_block->adev; 2186 struct smu_context *smu = adev->powerplay.pp_handle; 2187 int i, ret; 2188 2189 if (amdgpu_sriov_multi_vf_mode(adev)) 2190 return 0; 2191 2192 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2193 smu_dpm_set_vcn_enable(smu, false, i); 2194 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2195 } 2196 smu_dpm_set_jpeg_enable(smu, false); 2197 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2198 smu_dpm_set_umsch_mm_enable(smu, false); 2199 2200 if (!smu->pm_enabled) 2201 return 0; 2202 2203 adev->pm.dpm_enabled = false; 2204 2205 ret = smu_smc_hw_cleanup(smu); 2206 if (ret) 2207 return ret; 2208 2209 ret = smu_reset_mp1_state(smu); 2210 if (ret) 2211 return ret; 2212 2213 return 0; 2214 } 2215 2216 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2217 { 2218 struct amdgpu_device *adev = ip_block->adev; 2219 struct smu_context *smu = adev->powerplay.pp_handle; 2220 2221 kfree(smu); 2222 } 2223 2224 static int smu_reset(struct smu_context *smu) 2225 { 2226 struct amdgpu_device *adev = smu->adev; 2227 struct amdgpu_ip_block *ip_block; 2228 int ret; 2229 2230 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2231 if (!ip_block) 2232 return -EINVAL; 2233 2234 ret = smu_hw_fini(ip_block); 2235 if (ret) 2236 return ret; 2237 2238 ret = smu_hw_init(ip_block); 2239 if (ret) 2240 return ret; 2241 2242 ret = smu_late_init(ip_block); 2243 if (ret) 2244 return ret; 2245 2246 return 0; 2247 } 2248 2249 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2250 { 2251 struct amdgpu_device *adev = ip_block->adev; 2252 struct smu_context *smu = adev->powerplay.pp_handle; 2253 int ret; 2254 uint64_t count; 2255 2256 if (amdgpu_sriov_multi_vf_mode(adev)) 2257 return 0; 2258 2259 if (!smu->pm_enabled) 2260 return 0; 2261 2262 adev->pm.dpm_enabled = false; 2263 2264 ret = smu_smc_hw_cleanup(smu); 2265 if (ret) 2266 return ret; 2267 2268 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2269 2270 smu_set_gfx_cgpg(smu, false); 2271 2272 /* 2273 * pwfw resets entrycount when device is suspended, so we save the 2274 * last value to be used when we resume to keep it consistent 2275 */ 2276 ret = smu_get_entrycount_gfxoff(smu, &count); 2277 if (!ret) 2278 adev->gfx.gfx_off_entrycount = count; 2279 2280 /* clear this on suspend so it will get reprogrammed on resume */ 2281 smu->workload_mask = 0; 2282 2283 return 0; 2284 } 2285 2286 static int smu_resume(struct amdgpu_ip_block *ip_block) 2287 { 2288 int ret; 2289 struct amdgpu_device *adev = ip_block->adev; 2290 struct smu_context *smu = adev->powerplay.pp_handle; 2291 2292 if (amdgpu_sriov_multi_vf_mode(adev)) 2293 return 0; 2294 2295 if (!smu->pm_enabled) 2296 return 0; 2297 2298 dev_info(adev->dev, "SMU is resuming...\n"); 2299 2300 ret = smu_start_smc_engine(smu); 2301 if (ret) { 2302 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2303 return ret; 2304 } 2305 2306 ret = smu_smc_hw_setup(smu); 2307 if (ret) { 2308 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2309 return ret; 2310 } 2311 2312 ret = smu_set_gfx_imu_enable(smu); 2313 if (ret) 2314 return ret; 2315 2316 smu_set_gfx_cgpg(smu, true); 2317 2318 smu->disable_uclk_switch = 0; 2319 2320 adev->pm.dpm_enabled = true; 2321 2322 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2323 2324 return 0; 2325 } 2326 2327 static int smu_display_configuration_change(void *handle, 2328 const struct amd_pp_display_configuration *display_config) 2329 { 2330 struct smu_context *smu = handle; 2331 2332 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2333 return -EOPNOTSUPP; 2334 2335 if (!display_config) 2336 return -EINVAL; 2337 2338 smu_set_min_dcef_deep_sleep(smu, 2339 display_config->min_dcef_deep_sleep_set_clk / 100); 2340 2341 return 0; 2342 } 2343 2344 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2345 enum amd_clockgating_state state) 2346 { 2347 return 0; 2348 } 2349 2350 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2351 enum amd_powergating_state state) 2352 { 2353 return 0; 2354 } 2355 2356 static int smu_enable_umd_pstate(void *handle, 2357 enum amd_dpm_forced_level *level) 2358 { 2359 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2360 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2361 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2362 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2363 2364 struct smu_context *smu = (struct smu_context*)(handle); 2365 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2366 2367 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2368 return -EINVAL; 2369 2370 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2371 /* enter umd pstate, save current level, disable gfx cg*/ 2372 if (*level & profile_mode_mask) { 2373 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2374 smu_gpo_control(smu, false); 2375 smu_gfx_ulv_control(smu, false); 2376 smu_deep_sleep_control(smu, false); 2377 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2378 } 2379 } else { 2380 /* exit umd pstate, restore level, enable gfx cg*/ 2381 if (!(*level & profile_mode_mask)) { 2382 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2383 *level = smu_dpm_ctx->saved_dpm_level; 2384 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2385 smu_deep_sleep_control(smu, true); 2386 smu_gfx_ulv_control(smu, true); 2387 smu_gpo_control(smu, true); 2388 } 2389 } 2390 2391 return 0; 2392 } 2393 2394 static int smu_bump_power_profile_mode(struct smu_context *smu, 2395 long *custom_params, 2396 u32 custom_params_max_idx) 2397 { 2398 u32 workload_mask = 0; 2399 int i, ret = 0; 2400 2401 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2402 if (smu->workload_refcount[i]) 2403 workload_mask |= 1 << i; 2404 } 2405 2406 if (smu->workload_mask == workload_mask) 2407 return 0; 2408 2409 if (smu->ppt_funcs->set_power_profile_mode) 2410 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2411 custom_params, 2412 custom_params_max_idx); 2413 2414 if (!ret) 2415 smu->workload_mask = workload_mask; 2416 2417 return ret; 2418 } 2419 2420 static void smu_power_profile_mode_get(struct smu_context *smu, 2421 enum PP_SMC_POWER_PROFILE profile_mode) 2422 { 2423 smu->workload_refcount[profile_mode]++; 2424 } 2425 2426 static void smu_power_profile_mode_put(struct smu_context *smu, 2427 enum PP_SMC_POWER_PROFILE profile_mode) 2428 { 2429 if (smu->workload_refcount[profile_mode]) 2430 smu->workload_refcount[profile_mode]--; 2431 } 2432 2433 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2434 enum amd_dpm_forced_level level, 2435 bool skip_display_settings) 2436 { 2437 int ret = 0; 2438 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2439 2440 if (!skip_display_settings) { 2441 ret = smu_display_config_changed(smu); 2442 if (ret) { 2443 dev_err(smu->adev->dev, "Failed to change display config!"); 2444 return ret; 2445 } 2446 } 2447 2448 ret = smu_apply_clocks_adjust_rules(smu); 2449 if (ret) { 2450 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2451 return ret; 2452 } 2453 2454 if (!skip_display_settings) { 2455 ret = smu_notify_smc_display_config(smu); 2456 if (ret) { 2457 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2458 return ret; 2459 } 2460 } 2461 2462 if (smu_dpm_ctx->dpm_level != level) { 2463 ret = smu_asic_set_performance_level(smu, level); 2464 if (ret) { 2465 if (ret == -EOPNOTSUPP) 2466 dev_info(smu->adev->dev, "set performance level %d not supported", 2467 level); 2468 else 2469 dev_err(smu->adev->dev, "Failed to set performance level %d", 2470 level); 2471 return ret; 2472 } 2473 2474 /* update the saved copy */ 2475 smu_dpm_ctx->dpm_level = level; 2476 } 2477 2478 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2479 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2480 smu_bump_power_profile_mode(smu, NULL, 0); 2481 2482 return ret; 2483 } 2484 2485 static int smu_handle_task(struct smu_context *smu, 2486 enum amd_dpm_forced_level level, 2487 enum amd_pp_task task_id) 2488 { 2489 int ret = 0; 2490 2491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2492 return -EOPNOTSUPP; 2493 2494 switch (task_id) { 2495 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2496 ret = smu_pre_display_config_changed(smu); 2497 if (ret) 2498 return ret; 2499 ret = smu_adjust_power_state_dynamic(smu, level, false); 2500 break; 2501 case AMD_PP_TASK_COMPLETE_INIT: 2502 ret = smu_adjust_power_state_dynamic(smu, level, true); 2503 break; 2504 case AMD_PP_TASK_READJUST_POWER_STATE: 2505 ret = smu_adjust_power_state_dynamic(smu, level, true); 2506 break; 2507 default: 2508 break; 2509 } 2510 2511 return ret; 2512 } 2513 2514 static int smu_handle_dpm_task(void *handle, 2515 enum amd_pp_task task_id, 2516 enum amd_pm_state_type *user_state) 2517 { 2518 struct smu_context *smu = handle; 2519 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2520 2521 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2522 2523 } 2524 2525 static int smu_switch_power_profile(void *handle, 2526 enum PP_SMC_POWER_PROFILE type, 2527 bool enable) 2528 { 2529 struct smu_context *smu = handle; 2530 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2531 int ret; 2532 2533 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2534 return -EOPNOTSUPP; 2535 2536 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2537 return -EINVAL; 2538 2539 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2540 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2541 if (enable) 2542 smu_power_profile_mode_get(smu, type); 2543 else 2544 smu_power_profile_mode_put(smu, type); 2545 /* don't switch the active workload when paused */ 2546 if (smu->pause_workload) 2547 ret = 0; 2548 else 2549 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2550 if (ret) { 2551 if (enable) 2552 smu_power_profile_mode_put(smu, type); 2553 else 2554 smu_power_profile_mode_get(smu, type); 2555 return ret; 2556 } 2557 } 2558 2559 return 0; 2560 } 2561 2562 static int smu_pause_power_profile(void *handle, 2563 bool pause) 2564 { 2565 struct smu_context *smu = handle; 2566 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2567 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2568 int ret; 2569 2570 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2571 return -EOPNOTSUPP; 2572 2573 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2574 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2575 smu->pause_workload = pause; 2576 2577 /* force to bootup default profile */ 2578 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2579 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2580 workload_mask, 2581 NULL, 2582 0); 2583 else 2584 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2585 return ret; 2586 } 2587 2588 return 0; 2589 } 2590 2591 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2592 { 2593 struct smu_context *smu = handle; 2594 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2595 2596 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2597 return -EOPNOTSUPP; 2598 2599 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2600 return -EINVAL; 2601 2602 return smu_dpm_ctx->dpm_level; 2603 } 2604 2605 static int smu_force_performance_level(void *handle, 2606 enum amd_dpm_forced_level level) 2607 { 2608 struct smu_context *smu = handle; 2609 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2610 int ret = 0; 2611 2612 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2613 return -EOPNOTSUPP; 2614 2615 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2616 return -EINVAL; 2617 2618 ret = smu_enable_umd_pstate(smu, &level); 2619 if (ret) 2620 return ret; 2621 2622 ret = smu_handle_task(smu, level, 2623 AMD_PP_TASK_READJUST_POWER_STATE); 2624 2625 /* reset user dpm clock state */ 2626 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2627 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2628 smu->user_dpm_profile.clk_dependency = 0; 2629 } 2630 2631 return ret; 2632 } 2633 2634 static int smu_set_display_count(void *handle, uint32_t count) 2635 { 2636 struct smu_context *smu = handle; 2637 2638 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2639 return -EOPNOTSUPP; 2640 2641 return smu_init_display_count(smu, count); 2642 } 2643 2644 static int smu_force_smuclk_levels(struct smu_context *smu, 2645 enum smu_clk_type clk_type, 2646 uint32_t mask) 2647 { 2648 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2649 int ret = 0; 2650 2651 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2652 return -EOPNOTSUPP; 2653 2654 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2655 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2656 return -EINVAL; 2657 } 2658 2659 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2660 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2661 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2662 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2663 smu_set_user_clk_dependencies(smu, clk_type); 2664 } 2665 } 2666 2667 return ret; 2668 } 2669 2670 static int smu_force_ppclk_levels(void *handle, 2671 enum pp_clock_type type, 2672 uint32_t mask) 2673 { 2674 struct smu_context *smu = handle; 2675 enum smu_clk_type clk_type; 2676 2677 switch (type) { 2678 case PP_SCLK: 2679 clk_type = SMU_SCLK; break; 2680 case PP_MCLK: 2681 clk_type = SMU_MCLK; break; 2682 case PP_PCIE: 2683 clk_type = SMU_PCIE; break; 2684 case PP_SOCCLK: 2685 clk_type = SMU_SOCCLK; break; 2686 case PP_FCLK: 2687 clk_type = SMU_FCLK; break; 2688 case PP_DCEFCLK: 2689 clk_type = SMU_DCEFCLK; break; 2690 case PP_VCLK: 2691 clk_type = SMU_VCLK; break; 2692 case PP_VCLK1: 2693 clk_type = SMU_VCLK1; break; 2694 case PP_DCLK: 2695 clk_type = SMU_DCLK; break; 2696 case PP_DCLK1: 2697 clk_type = SMU_DCLK1; break; 2698 case OD_SCLK: 2699 clk_type = SMU_OD_SCLK; break; 2700 case OD_MCLK: 2701 clk_type = SMU_OD_MCLK; break; 2702 case OD_VDDC_CURVE: 2703 clk_type = SMU_OD_VDDC_CURVE; break; 2704 case OD_RANGE: 2705 clk_type = SMU_OD_RANGE; break; 2706 default: 2707 return -EINVAL; 2708 } 2709 2710 return smu_force_smuclk_levels(smu, clk_type, mask); 2711 } 2712 2713 /* 2714 * On system suspending or resetting, the dpm_enabled 2715 * flag will be cleared. So that those SMU services which 2716 * are not supported will be gated. 2717 * However, the mp1 state setting should still be granted 2718 * even if the dpm_enabled cleared. 2719 */ 2720 static int smu_set_mp1_state(void *handle, 2721 enum pp_mp1_state mp1_state) 2722 { 2723 struct smu_context *smu = handle; 2724 int ret = 0; 2725 2726 if (!smu->pm_enabled) 2727 return -EOPNOTSUPP; 2728 2729 if (smu->ppt_funcs && 2730 smu->ppt_funcs->set_mp1_state) 2731 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2732 2733 return ret; 2734 } 2735 2736 static int smu_set_df_cstate(void *handle, 2737 enum pp_df_cstate state) 2738 { 2739 struct smu_context *smu = handle; 2740 int ret = 0; 2741 2742 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2743 return -EOPNOTSUPP; 2744 2745 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2746 return 0; 2747 2748 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2749 if (ret) 2750 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2751 2752 return ret; 2753 } 2754 2755 int smu_write_watermarks_table(struct smu_context *smu) 2756 { 2757 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2758 return -EOPNOTSUPP; 2759 2760 return smu_set_watermarks_table(smu, NULL); 2761 } 2762 2763 static int smu_set_watermarks_for_clock_ranges(void *handle, 2764 struct pp_smu_wm_range_sets *clock_ranges) 2765 { 2766 struct smu_context *smu = handle; 2767 2768 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2769 return -EOPNOTSUPP; 2770 2771 if (smu->disable_watermark) 2772 return 0; 2773 2774 return smu_set_watermarks_table(smu, clock_ranges); 2775 } 2776 2777 int smu_set_ac_dc(struct smu_context *smu, bool restore_ppt_policy) 2778 { 2779 int ret = 0; 2780 2781 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2782 return -EOPNOTSUPP; 2783 2784 /* controlled by firmware */ 2785 if (!smu->dc_controlled_by_gpio) { 2786 ret = smu_set_power_source(smu, 2787 smu->adev->pm.ac_power ? 2788 SMU_POWER_SOURCE_AC : 2789 SMU_POWER_SOURCE_DC); 2790 if (ret) { 2791 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2792 smu->adev->pm.ac_power ? "AC" : "DC"); 2793 return ret; 2794 } 2795 } 2796 2797 if (restore_ppt_policy) 2798 smu_restore_ppt_limits(smu, true); 2799 2800 return 0; 2801 } 2802 2803 const struct amd_ip_funcs smu_ip_funcs = { 2804 .name = "smu", 2805 .early_init = smu_early_init, 2806 .late_init = smu_late_init, 2807 .sw_init = smu_sw_init, 2808 .sw_fini = smu_sw_fini, 2809 .hw_init = smu_hw_init, 2810 .hw_fini = smu_hw_fini, 2811 .late_fini = smu_late_fini, 2812 .suspend = smu_suspend, 2813 .resume = smu_resume, 2814 .is_idle = NULL, 2815 .wait_for_idle = NULL, 2816 .soft_reset = NULL, 2817 .set_clockgating_state = smu_set_clockgating_state, 2818 .set_powergating_state = smu_set_powergating_state, 2819 }; 2820 2821 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2822 .type = AMD_IP_BLOCK_TYPE_SMC, 2823 .major = 11, 2824 .minor = 0, 2825 .rev = 0, 2826 .funcs = &smu_ip_funcs, 2827 }; 2828 2829 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2830 .type = AMD_IP_BLOCK_TYPE_SMC, 2831 .major = 12, 2832 .minor = 0, 2833 .rev = 0, 2834 .funcs = &smu_ip_funcs, 2835 }; 2836 2837 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2838 .type = AMD_IP_BLOCK_TYPE_SMC, 2839 .major = 13, 2840 .minor = 0, 2841 .rev = 0, 2842 .funcs = &smu_ip_funcs, 2843 }; 2844 2845 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2846 .type = AMD_IP_BLOCK_TYPE_SMC, 2847 .major = 14, 2848 .minor = 0, 2849 .rev = 0, 2850 .funcs = &smu_ip_funcs, 2851 }; 2852 2853 const struct amdgpu_ip_block_version smu_v15_0_ip_block = { 2854 .type = AMD_IP_BLOCK_TYPE_SMC, 2855 .major = 15, 2856 .minor = 0, 2857 .rev = 0, 2858 .funcs = &smu_ip_funcs, 2859 }; 2860 2861 static int smu_load_microcode(void *handle) 2862 { 2863 struct smu_context *smu = handle; 2864 struct amdgpu_device *adev = smu->adev; 2865 int ret = 0; 2866 2867 if (!smu->pm_enabled) 2868 return -EOPNOTSUPP; 2869 2870 /* This should be used for non PSP loading */ 2871 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2872 return 0; 2873 2874 if (smu->ppt_funcs->load_microcode) { 2875 ret = smu->ppt_funcs->load_microcode(smu); 2876 if (ret) { 2877 dev_err(adev->dev, "Load microcode failed\n"); 2878 return ret; 2879 } 2880 } 2881 2882 if (smu->ppt_funcs->check_fw_status) { 2883 ret = smu->ppt_funcs->check_fw_status(smu); 2884 if (ret) { 2885 dev_err(adev->dev, "SMC is not ready\n"); 2886 return ret; 2887 } 2888 } 2889 2890 return ret; 2891 } 2892 2893 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2894 { 2895 int ret = 0; 2896 2897 if (smu->ppt_funcs->set_gfx_cgpg) 2898 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2899 2900 return ret; 2901 } 2902 2903 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2904 { 2905 struct smu_context *smu = handle; 2906 int ret = 0; 2907 2908 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2909 return -EOPNOTSUPP; 2910 2911 if (!smu->ppt_funcs->set_fan_speed_rpm) 2912 return -EOPNOTSUPP; 2913 2914 if (speed == U32_MAX) 2915 return -EINVAL; 2916 2917 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2918 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2919 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2920 smu->user_dpm_profile.fan_speed_rpm = speed; 2921 2922 /* Override custom PWM setting as they cannot co-exist */ 2923 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2924 smu->user_dpm_profile.fan_speed_pwm = 0; 2925 } 2926 2927 return ret; 2928 } 2929 2930 /** 2931 * smu_get_ppt_limit - Request one of the SMU PPT limits 2932 * 2933 * @handle: pointer to smu context 2934 * @limit: requested limit is written back to this variable 2935 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2936 * @pp_power_type: &pp_power_type type of power 2937 * Return: 0 on success, <0 on error 2938 * 2939 */ 2940 int smu_get_ppt_limit(void *handle, 2941 uint32_t *limit, 2942 enum pp_power_limit_level pp_limit_level, 2943 enum pp_power_type pp_power_type) 2944 { 2945 struct smu_context *smu = handle; 2946 enum smu_power_src_type power_source; 2947 enum smu_ppt_limit_level limit_level; 2948 uint32_t limit_type; 2949 int ret = 0; 2950 2951 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2952 return -EOPNOTSUPP; 2953 2954 if (!limit) 2955 return -EINVAL; 2956 2957 power_source = smu->adev->pm.ac_power ? 2958 SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC; 2959 2960 switch (pp_power_type) { 2961 case PP_PWR_TYPE_SUSTAINED: 2962 limit_type = SMU_SLOW_PPT_LIMIT; 2963 break; 2964 case PP_PWR_TYPE_FAST: 2965 limit_type = SMU_FAST_PPT_LIMIT; 2966 break; 2967 default: 2968 return -EOPNOTSUPP; 2969 } 2970 2971 switch (pp_limit_level) { 2972 case PP_PWR_LIMIT_CURRENT: 2973 limit_level = SMU_PPT_LIMIT_CURRENT; 2974 break; 2975 case PP_PWR_LIMIT_DEFAULT: 2976 limit_level = SMU_PPT_LIMIT_DEFAULT; 2977 break; 2978 case PP_PWR_LIMIT_MAX: 2979 limit_level = SMU_PPT_LIMIT_MAX; 2980 break; 2981 case PP_PWR_LIMIT_MIN: 2982 limit_level = SMU_PPT_LIMIT_MIN; 2983 break; 2984 default: 2985 return -EOPNOTSUPP; 2986 } 2987 2988 if (!(smu->ppt_limits.supported_mask & BIT(limit_type))) 2989 return -EOPNOTSUPP; 2990 2991 switch (limit_level) { 2992 case SMU_PPT_LIMIT_CURRENT: 2993 ret = smu_get_asic_ppt_limit(smu, limit_type, limit); 2994 break; 2995 case SMU_PPT_LIMIT_DEFAULT: 2996 *limit = smu->ppt_limits.range[power_source][limit_type].default_value; 2997 break; 2998 case SMU_PPT_LIMIT_MAX: 2999 *limit = smu->od_enabled ? 3000 smu->ppt_limits.range[power_source][limit_type].od_max : 3001 smu->ppt_limits.range[power_source][limit_type].max; 3002 break; 3003 case SMU_PPT_LIMIT_MIN: 3004 *limit = smu->od_enabled ? 3005 smu->ppt_limits.range[power_source][limit_type].od_min : 3006 smu->ppt_limits.range[power_source][limit_type].min; 3007 break; 3008 default: 3009 return -EINVAL; 3010 } 3011 3012 return ret; 3013 } 3014 3015 static int smu_set_ppt_limit(void *handle, uint32_t limit_type, uint32_t limit) 3016 { 3017 struct smu_context *smu = handle; 3018 enum smu_power_src_type power_source; 3019 struct smu_ppt_limit_range *range; 3020 uint32_t min_limit, max_limit; 3021 int ret = 0; 3022 3023 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3024 return -EOPNOTSUPP; 3025 if (limit_type >= SMU_LIMIT_TYPE_COUNT) 3026 return -EINVAL; 3027 3028 power_source = smu->adev->pm.ac_power ? 3029 SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC; 3030 range = &smu->ppt_limits.range[power_source][limit_type]; 3031 min_limit = smu->od_enabled ? range->od_min : range->min; 3032 max_limit = smu->od_enabled ? range->od_max : range->max; 3033 3034 if (!(smu->ppt_limits.supported_mask & BIT(limit_type))) 3035 return -EOPNOTSUPP; 3036 3037 if (limit_type == SMU_DEFAULT_PPT_LIMIT && !limit) { 3038 ret = smu_get_asic_ppt_limit(smu, limit_type, &limit); 3039 if (ret) 3040 return ret; 3041 } 3042 3043 if (limit > max_limit || limit < min_limit) { 3044 dev_err(smu->adev->dev, 3045 "New PPT limit (%d) is out of range [%d,%d]\n", 3046 limit, min_limit, max_limit); 3047 return -EINVAL; 3048 } 3049 3050 if (!smu->ppt_funcs->set_ppt_limit) 3051 return -EOPNOTSUPP; 3052 3053 ret = smu->ppt_funcs->set_ppt_limit(smu, limit_type, limit); 3054 if (ret) 3055 return ret; 3056 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3057 smu->user_dpm_profile.ppt_limits[power_source][limit_type] = limit; 3058 smu->user_dpm_profile.ppt_limit_user_mask[power_source] |= 3059 BIT(limit_type); 3060 } 3061 3062 return 0; 3063 } 3064 3065 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 3066 { 3067 enum smu_clk_type clk_type; 3068 3069 switch (type) { 3070 case PP_SCLK: 3071 clk_type = SMU_SCLK; break; 3072 case PP_MCLK: 3073 clk_type = SMU_MCLK; break; 3074 case PP_PCIE: 3075 clk_type = SMU_PCIE; break; 3076 case PP_SOCCLK: 3077 clk_type = SMU_SOCCLK; break; 3078 case PP_FCLK: 3079 clk_type = SMU_FCLK; break; 3080 case PP_DCEFCLK: 3081 clk_type = SMU_DCEFCLK; break; 3082 case PP_VCLK: 3083 clk_type = SMU_VCLK; break; 3084 case PP_VCLK1: 3085 clk_type = SMU_VCLK1; break; 3086 case PP_DCLK: 3087 clk_type = SMU_DCLK; break; 3088 case PP_DCLK1: 3089 clk_type = SMU_DCLK1; break; 3090 case PP_ISPICLK: 3091 clk_type = SMU_ISPICLK; 3092 break; 3093 case PP_ISPXCLK: 3094 clk_type = SMU_ISPXCLK; 3095 break; 3096 case OD_SCLK: 3097 clk_type = SMU_OD_SCLK; break; 3098 case OD_MCLK: 3099 clk_type = SMU_OD_MCLK; break; 3100 case OD_FCLK: 3101 clk_type = SMU_OD_FCLK; break; 3102 case OD_VDDC_CURVE: 3103 clk_type = SMU_OD_VDDC_CURVE; break; 3104 case OD_RANGE: 3105 clk_type = SMU_OD_RANGE; break; 3106 case OD_VDDGFX_OFFSET: 3107 clk_type = SMU_OD_VDDGFX_OFFSET; break; 3108 case OD_CCLK: 3109 clk_type = SMU_OD_CCLK; break; 3110 case OD_FAN_CURVE: 3111 clk_type = SMU_OD_FAN_CURVE; break; 3112 case OD_ACOUSTIC_LIMIT: 3113 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 3114 case OD_ACOUSTIC_TARGET: 3115 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 3116 case OD_FAN_TARGET_TEMPERATURE: 3117 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 3118 case OD_FAN_MINIMUM_PWM: 3119 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 3120 case OD_FAN_ZERO_RPM_ENABLE: 3121 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 3122 case OD_FAN_ZERO_RPM_STOP_TEMP: 3123 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 3124 default: 3125 clk_type = SMU_CLK_COUNT; break; 3126 } 3127 3128 return clk_type; 3129 } 3130 3131 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3132 { 3133 struct smu_context *smu = handle; 3134 enum smu_clk_type clk_type; 3135 3136 clk_type = smu_convert_to_smuclk(type); 3137 if (clk_type == SMU_CLK_COUNT) 3138 return -EINVAL; 3139 3140 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3141 return -EOPNOTSUPP; 3142 3143 if (!smu->ppt_funcs->emit_clk_levels) 3144 return -ENOENT; 3145 3146 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3147 3148 } 3149 3150 static int smu_od_edit_dpm_table(void *handle, 3151 enum PP_OD_DPM_TABLE_COMMAND type, 3152 long *input, uint32_t size) 3153 { 3154 struct smu_context *smu = handle; 3155 int ret = 0; 3156 3157 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3158 return -EOPNOTSUPP; 3159 3160 if (smu->ppt_funcs->od_edit_dpm_table) { 3161 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3162 } 3163 3164 return ret; 3165 } 3166 3167 static int smu_read_sensor(void *handle, 3168 int sensor, 3169 void *data, 3170 int *size_arg) 3171 { 3172 struct smu_context *smu = handle; 3173 struct amdgpu_device *adev = smu->adev; 3174 struct smu_umd_pstate_table *pstate_table = 3175 &smu->pstate_table; 3176 int i, ret = 0; 3177 uint32_t *size, size_val; 3178 3179 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3180 return -EOPNOTSUPP; 3181 3182 if (!data || !size_arg) 3183 return -EINVAL; 3184 3185 size_val = *size_arg; 3186 size = &size_val; 3187 3188 if (smu->ppt_funcs->read_sensor) 3189 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3190 goto unlock; 3191 3192 switch (sensor) { 3193 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3194 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3195 *size = 4; 3196 break; 3197 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3198 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3199 *size = 4; 3200 break; 3201 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3202 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3203 *size = 4; 3204 break; 3205 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3206 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3207 *size = 4; 3208 break; 3209 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: { 3210 struct smu_feature_bits feature_mask; 3211 uint32_t features[2]; 3212 3213 /* TBD: need to handle for > 64 bits */ 3214 ret = smu_feature_get_enabled_mask(smu, &feature_mask); 3215 if (!ret) { 3216 smu_feature_bits_to_arr32(&feature_mask, features, 64); 3217 *(uint64_t *)data = *(uint64_t *)features; 3218 } 3219 *size = 8; 3220 break; 3221 } 3222 case AMDGPU_PP_SENSOR_UVD_POWER: 3223 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3224 *size = 4; 3225 break; 3226 case AMDGPU_PP_SENSOR_VCE_POWER: 3227 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3228 *size = 4; 3229 break; 3230 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3231 *(uint32_t *)data = 0; 3232 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3233 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3234 *(uint32_t *)data = 1; 3235 break; 3236 } 3237 } 3238 *size = 4; 3239 break; 3240 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3241 *(uint32_t *)data = 0; 3242 *size = 4; 3243 break; 3244 default: 3245 *size = 0; 3246 ret = -EOPNOTSUPP; 3247 break; 3248 } 3249 3250 unlock: 3251 // assign uint32_t to int 3252 *size_arg = size_val; 3253 3254 return ret; 3255 } 3256 3257 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3258 { 3259 int ret = -EOPNOTSUPP; 3260 struct smu_context *smu = handle; 3261 3262 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3263 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3264 3265 return ret; 3266 } 3267 3268 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3269 { 3270 int ret = -EOPNOTSUPP; 3271 struct smu_context *smu = handle; 3272 3273 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3274 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3275 3276 return ret; 3277 } 3278 3279 static int smu_get_power_profile_mode(void *handle, char *buf) 3280 { 3281 struct smu_context *smu = handle; 3282 3283 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3284 !smu->ppt_funcs->get_power_profile_mode) 3285 return -EOPNOTSUPP; 3286 if (!buf) 3287 return -EINVAL; 3288 3289 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3290 } 3291 3292 static int smu_set_power_profile_mode(void *handle, 3293 long *param, 3294 uint32_t param_size) 3295 { 3296 struct smu_context *smu = handle; 3297 bool custom = false; 3298 int ret = 0; 3299 3300 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3301 !smu->ppt_funcs->set_power_profile_mode) 3302 return -EOPNOTSUPP; 3303 3304 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3305 custom = true; 3306 /* clear frontend mask so custom changes propogate */ 3307 smu->workload_mask = 0; 3308 } 3309 3310 if ((param[param_size] != smu->power_profile_mode) || custom) { 3311 /* clear the old user preference */ 3312 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3313 /* set the new user preference */ 3314 smu_power_profile_mode_get(smu, param[param_size]); 3315 ret = smu_bump_power_profile_mode(smu, 3316 custom ? param : NULL, 3317 custom ? param_size : 0); 3318 if (ret) 3319 smu_power_profile_mode_put(smu, param[param_size]); 3320 else 3321 /* store the user's preference */ 3322 smu->power_profile_mode = param[param_size]; 3323 } 3324 3325 return ret; 3326 } 3327 3328 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3329 { 3330 struct smu_context *smu = handle; 3331 3332 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3333 return -EOPNOTSUPP; 3334 3335 if (!smu->ppt_funcs->get_fan_control_mode) 3336 return -EOPNOTSUPP; 3337 3338 if (!fan_mode) 3339 return -EINVAL; 3340 3341 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3342 3343 return 0; 3344 } 3345 3346 static int smu_set_fan_control_mode(void *handle, u32 value) 3347 { 3348 struct smu_context *smu = handle; 3349 int ret = 0; 3350 3351 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3352 return -EOPNOTSUPP; 3353 3354 if (!smu->ppt_funcs->set_fan_control_mode) 3355 return -EOPNOTSUPP; 3356 3357 if (value == U32_MAX) 3358 return -EINVAL; 3359 3360 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3361 if (ret) 3362 goto out; 3363 3364 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3365 smu->user_dpm_profile.fan_mode = value; 3366 3367 /* reset user dpm fan speed */ 3368 if (value != AMD_FAN_CTRL_MANUAL) { 3369 smu->user_dpm_profile.fan_speed_pwm = 0; 3370 smu->user_dpm_profile.fan_speed_rpm = 0; 3371 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3372 } 3373 } 3374 3375 out: 3376 return ret; 3377 } 3378 3379 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3380 { 3381 struct smu_context *smu = handle; 3382 int ret = 0; 3383 3384 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3385 return -EOPNOTSUPP; 3386 3387 if (!smu->ppt_funcs->get_fan_speed_pwm) 3388 return -EOPNOTSUPP; 3389 3390 if (!speed) 3391 return -EINVAL; 3392 3393 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3394 3395 return ret; 3396 } 3397 3398 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3399 { 3400 struct smu_context *smu = handle; 3401 int ret = 0; 3402 3403 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3404 return -EOPNOTSUPP; 3405 3406 if (!smu->ppt_funcs->set_fan_speed_pwm) 3407 return -EOPNOTSUPP; 3408 3409 if (speed == U32_MAX) 3410 return -EINVAL; 3411 3412 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3413 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3414 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3415 smu->user_dpm_profile.fan_speed_pwm = speed; 3416 3417 /* Override custom RPM setting as they cannot co-exist */ 3418 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3419 smu->user_dpm_profile.fan_speed_rpm = 0; 3420 } 3421 3422 return ret; 3423 } 3424 3425 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3426 { 3427 struct smu_context *smu = handle; 3428 int ret = 0; 3429 3430 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3431 return -EOPNOTSUPP; 3432 3433 if (!smu->ppt_funcs->get_fan_speed_rpm) 3434 return -EOPNOTSUPP; 3435 3436 if (!speed) 3437 return -EINVAL; 3438 3439 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3440 3441 return ret; 3442 } 3443 3444 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3445 { 3446 struct smu_context *smu = handle; 3447 3448 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3449 return -EOPNOTSUPP; 3450 3451 return smu_set_min_dcef_deep_sleep(smu, clk); 3452 } 3453 3454 static int smu_get_clock_by_type_with_latency(void *handle, 3455 enum amd_pp_clock_type type, 3456 struct pp_clock_levels_with_latency *clocks) 3457 { 3458 struct smu_context *smu = handle; 3459 enum smu_clk_type clk_type; 3460 int ret = 0; 3461 3462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3463 return -EOPNOTSUPP; 3464 3465 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3466 switch (type) { 3467 case amd_pp_sys_clock: 3468 clk_type = SMU_GFXCLK; 3469 break; 3470 case amd_pp_mem_clock: 3471 clk_type = SMU_MCLK; 3472 break; 3473 case amd_pp_dcef_clock: 3474 clk_type = SMU_DCEFCLK; 3475 break; 3476 case amd_pp_disp_clock: 3477 clk_type = SMU_DISPCLK; 3478 break; 3479 default: 3480 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3481 return -EINVAL; 3482 } 3483 3484 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3485 } 3486 3487 return ret; 3488 } 3489 3490 static int smu_display_clock_voltage_request(void *handle, 3491 struct pp_display_clock_request *clock_req) 3492 { 3493 struct smu_context *smu = handle; 3494 int ret = 0; 3495 3496 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3497 return -EOPNOTSUPP; 3498 3499 if (smu->ppt_funcs->display_clock_voltage_request) 3500 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3501 3502 return ret; 3503 } 3504 3505 3506 static int smu_display_disable_memory_clock_switch(void *handle, 3507 bool disable_memory_clock_switch) 3508 { 3509 struct smu_context *smu = handle; 3510 int ret = -EINVAL; 3511 3512 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3513 return -EOPNOTSUPP; 3514 3515 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3516 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3517 3518 return ret; 3519 } 3520 3521 static int smu_set_xgmi_pstate(void *handle, 3522 uint32_t pstate) 3523 { 3524 struct smu_context *smu = handle; 3525 int ret = 0; 3526 3527 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3528 return -EOPNOTSUPP; 3529 3530 if (smu->ppt_funcs->set_xgmi_pstate) 3531 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3532 3533 if (ret) 3534 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3535 3536 return ret; 3537 } 3538 3539 static int smu_get_baco_capability(void *handle) 3540 { 3541 struct smu_context *smu = handle; 3542 3543 if (!smu->pm_enabled) 3544 return false; 3545 3546 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3547 return false; 3548 3549 return smu->ppt_funcs->get_bamaco_support(smu); 3550 } 3551 3552 static int smu_baco_set_state(void *handle, int state) 3553 { 3554 struct smu_context *smu = handle; 3555 int ret = 0; 3556 3557 if (!smu->pm_enabled) 3558 return -EOPNOTSUPP; 3559 3560 if (state == 0) { 3561 if (smu->ppt_funcs->baco_exit) 3562 ret = smu->ppt_funcs->baco_exit(smu); 3563 } else if (state == 1) { 3564 if (smu->ppt_funcs->baco_enter) 3565 ret = smu->ppt_funcs->baco_enter(smu); 3566 } else { 3567 return -EINVAL; 3568 } 3569 3570 if (ret) 3571 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3572 (state)?"enter":"exit"); 3573 3574 return ret; 3575 } 3576 3577 bool smu_mode1_reset_is_support(struct smu_context *smu) 3578 { 3579 bool ret = false; 3580 3581 if (!smu->pm_enabled) 3582 return false; 3583 3584 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3585 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3586 3587 return ret; 3588 } 3589 3590 bool smu_link_reset_is_support(struct smu_context *smu) 3591 { 3592 if (!smu->pm_enabled) 3593 return false; 3594 3595 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET); 3596 } 3597 3598 int smu_mode1_reset(struct smu_context *smu) 3599 { 3600 int ret = 0; 3601 3602 if (!smu->pm_enabled) 3603 return -EOPNOTSUPP; 3604 3605 if (smu->ppt_funcs->mode1_reset) 3606 ret = smu->ppt_funcs->mode1_reset(smu); 3607 3608 return ret; 3609 } 3610 3611 static int smu_mode2_reset(void *handle) 3612 { 3613 struct smu_context *smu = handle; 3614 int ret = 0; 3615 3616 if (!smu->pm_enabled) 3617 return -EOPNOTSUPP; 3618 3619 if (smu->ppt_funcs->mode2_reset) 3620 ret = smu->ppt_funcs->mode2_reset(smu); 3621 3622 if (ret) 3623 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3624 3625 return ret; 3626 } 3627 3628 int smu_link_reset(struct smu_context *smu) 3629 { 3630 int ret = 0; 3631 3632 if (!smu->pm_enabled) 3633 return -EOPNOTSUPP; 3634 3635 if (smu->ppt_funcs->link_reset) 3636 ret = smu->ppt_funcs->link_reset(smu); 3637 3638 return ret; 3639 } 3640 3641 static int smu_enable_gfx_features(void *handle) 3642 { 3643 struct smu_context *smu = handle; 3644 int ret = 0; 3645 3646 if (!smu->pm_enabled) 3647 return -EOPNOTSUPP; 3648 3649 if (smu->ppt_funcs->enable_gfx_features) 3650 ret = smu->ppt_funcs->enable_gfx_features(smu); 3651 3652 if (ret) 3653 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3654 3655 return ret; 3656 } 3657 3658 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3659 struct pp_smu_nv_clock_table *max_clocks) 3660 { 3661 struct smu_context *smu = handle; 3662 int ret = 0; 3663 3664 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3665 return -EOPNOTSUPP; 3666 3667 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3668 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3669 3670 return ret; 3671 } 3672 3673 static int smu_get_uclk_dpm_states(void *handle, 3674 unsigned int *clock_values_in_khz, 3675 unsigned int *num_states) 3676 { 3677 struct smu_context *smu = handle; 3678 int ret = 0; 3679 3680 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3681 return -EOPNOTSUPP; 3682 3683 if (smu->ppt_funcs->get_uclk_dpm_states) 3684 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3685 3686 return ret; 3687 } 3688 3689 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3690 { 3691 struct smu_context *smu = handle; 3692 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3693 3694 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3695 return -EOPNOTSUPP; 3696 3697 if (smu->ppt_funcs->get_current_power_state) 3698 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3699 3700 return pm_state; 3701 } 3702 3703 static int smu_get_dpm_clock_table(void *handle, 3704 struct dpm_clocks *clock_table) 3705 { 3706 struct smu_context *smu = handle; 3707 int ret = 0; 3708 3709 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3710 return -EOPNOTSUPP; 3711 3712 if (smu->ppt_funcs->get_dpm_clock_table) 3713 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3714 3715 return ret; 3716 } 3717 3718 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3719 { 3720 struct smu_context *smu = handle; 3721 struct smu_table_context *smu_table = &smu->smu_table; 3722 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3723 struct smu_driver_table *gpu_metrics_table; 3724 3725 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3726 return -EOPNOTSUPP; 3727 3728 if (!smu->ppt_funcs->get_gpu_metrics) 3729 return -EOPNOTSUPP; 3730 3731 gpu_metrics_table = &driver_tables[SMU_DRIVER_TABLE_GPU_METRICS]; 3732 3733 /* If cached table is valid, return it */ 3734 if (smu_driver_table_is_valid(gpu_metrics_table)) { 3735 *table = gpu_metrics_table->cache.buffer; 3736 return gpu_metrics_table->cache.size; 3737 } 3738 3739 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3740 } 3741 3742 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3743 size_t size) 3744 { 3745 struct smu_context *smu = handle; 3746 3747 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3748 return -EOPNOTSUPP; 3749 3750 if (!smu->ppt_funcs->get_pm_metrics) 3751 return -EOPNOTSUPP; 3752 3753 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3754 } 3755 3756 static int smu_enable_mgpu_fan_boost(void *handle) 3757 { 3758 struct smu_context *smu = handle; 3759 int ret = 0; 3760 3761 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3762 return -EOPNOTSUPP; 3763 3764 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3765 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3766 3767 return ret; 3768 } 3769 3770 static int smu_gfx_state_change_set(void *handle, 3771 uint32_t state) 3772 { 3773 struct smu_context *smu = handle; 3774 int ret = 0; 3775 3776 if (smu->ppt_funcs->gfx_state_change_set) 3777 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3778 3779 return ret; 3780 } 3781 3782 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3783 { 3784 int ret = 0; 3785 3786 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3787 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3788 3789 return ret; 3790 } 3791 3792 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3793 { 3794 int ret = -EOPNOTSUPP; 3795 3796 if (smu->ppt_funcs && 3797 smu->ppt_funcs->get_ecc_info) 3798 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3799 3800 return ret; 3801 3802 } 3803 3804 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3805 { 3806 struct smu_context *smu = handle; 3807 struct smu_table_context *smu_table = &smu->smu_table; 3808 struct smu_table *memory_pool = &smu_table->memory_pool; 3809 3810 if (!addr || !size) 3811 return -EINVAL; 3812 3813 *addr = NULL; 3814 *size = 0; 3815 if (memory_pool->bo) { 3816 *addr = memory_pool->cpu_addr; 3817 *size = memory_pool->size; 3818 } 3819 3820 return 0; 3821 } 3822 3823 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3824 size_t *size) 3825 { 3826 size_t offset = *size; 3827 int level; 3828 3829 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3830 if (level == policy->current_level) 3831 offset += sysfs_emit_at(sysbuf, offset, 3832 "%d : %s*\n", level, 3833 policy->desc->get_desc(policy, level)); 3834 else 3835 offset += sysfs_emit_at(sysbuf, offset, 3836 "%d : %s\n", level, 3837 policy->desc->get_desc(policy, level)); 3838 } 3839 3840 *size = offset; 3841 } 3842 3843 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3844 enum pp_pm_policy p_type, char *sysbuf) 3845 { 3846 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3847 struct smu_dpm_policy_ctxt *policy_ctxt; 3848 struct smu_dpm_policy *dpm_policy; 3849 size_t offset = 0; 3850 3851 policy_ctxt = dpm_ctxt->dpm_policies; 3852 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3853 !policy_ctxt->policy_mask) 3854 return -EOPNOTSUPP; 3855 3856 if (p_type == PP_PM_POLICY_NONE) 3857 return -EINVAL; 3858 3859 dpm_policy = smu_get_pm_policy(smu, p_type); 3860 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3861 return -ENOENT; 3862 3863 if (!sysbuf) 3864 return -EINVAL; 3865 3866 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3867 3868 return offset; 3869 } 3870 3871 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3872 enum pp_pm_policy p_type) 3873 { 3874 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3875 struct smu_dpm_policy_ctxt *policy_ctxt; 3876 int i; 3877 3878 policy_ctxt = dpm_ctxt->dpm_policies; 3879 if (!policy_ctxt) 3880 return NULL; 3881 3882 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3883 if (policy_ctxt->policies[i].policy_type == p_type) 3884 return &policy_ctxt->policies[i]; 3885 } 3886 3887 return NULL; 3888 } 3889 3890 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3891 int level) 3892 { 3893 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3894 struct smu_dpm_policy *dpm_policy = NULL; 3895 struct smu_dpm_policy_ctxt *policy_ctxt; 3896 int ret = -EOPNOTSUPP; 3897 3898 policy_ctxt = dpm_ctxt->dpm_policies; 3899 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3900 !policy_ctxt->policy_mask) 3901 return ret; 3902 3903 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3904 return -EINVAL; 3905 3906 dpm_policy = smu_get_pm_policy(smu, p_type); 3907 3908 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3909 return ret; 3910 3911 if (dpm_policy->current_level == level) 3912 return 0; 3913 3914 ret = dpm_policy->set_policy(smu, level); 3915 3916 if (!ret) 3917 dpm_policy->current_level = level; 3918 3919 return ret; 3920 } 3921 3922 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) 3923 { 3924 struct smu_context *smu = handle; 3925 struct smu_table_context *smu_table = &smu->smu_table; 3926 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3927 enum smu_driver_table_id table_id; 3928 struct smu_driver_table *temp_table; 3929 3930 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3931 return -EOPNOTSUPP; 3932 3933 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) 3934 return -EOPNOTSUPP; 3935 3936 table_id = smu_metrics_get_temp_table_id(type); 3937 3938 if (table_id == SMU_DRIVER_TABLE_COUNT) 3939 return -EINVAL; 3940 3941 temp_table = &driver_tables[table_id]; 3942 3943 /* If the request is to get size alone, return the cached table size */ 3944 if (!table && temp_table->cache.size) 3945 return temp_table->cache.size; 3946 3947 if (smu_driver_table_is_valid(temp_table)) { 3948 memcpy(table, temp_table->cache.buffer, temp_table->cache.size); 3949 return temp_table->cache.size; 3950 } 3951 3952 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); 3953 } 3954 3955 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) 3956 { 3957 struct smu_context *smu = handle; 3958 bool ret = false; 3959 3960 if (!smu->pm_enabled) 3961 return false; 3962 3963 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) 3964 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); 3965 3966 return ret; 3967 } 3968 3969 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3970 { 3971 struct smu_context *smu = handle; 3972 3973 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3974 return -EOPNOTSUPP; 3975 3976 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3977 return -EOPNOTSUPP; 3978 3979 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3980 } 3981 3982 static const struct amd_pm_funcs swsmu_pm_funcs = { 3983 /* export for sysfs */ 3984 .set_fan_control_mode = smu_set_fan_control_mode, 3985 .get_fan_control_mode = smu_get_fan_control_mode, 3986 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3987 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3988 .force_clock_level = smu_force_ppclk_levels, 3989 .emit_clock_levels = smu_emit_ppclk_levels, 3990 .force_performance_level = smu_force_performance_level, 3991 .read_sensor = smu_read_sensor, 3992 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3993 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3994 .get_performance_level = smu_get_performance_level, 3995 .get_current_power_state = smu_get_current_power_state, 3996 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3997 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3998 .get_pp_num_states = smu_get_power_num_states, 3999 .get_pp_table = smu_sys_get_pp_table, 4000 .set_pp_table = smu_sys_set_pp_table, 4001 .switch_power_profile = smu_switch_power_profile, 4002 .pause_power_profile = smu_pause_power_profile, 4003 /* export to amdgpu */ 4004 .dispatch_tasks = smu_handle_dpm_task, 4005 .load_firmware = smu_load_microcode, 4006 .set_powergating_by_smu = smu_dpm_set_power_gate, 4007 .set_power_limit = smu_set_ppt_limit, 4008 .get_power_limit = smu_get_ppt_limit, 4009 .get_power_profile_mode = smu_get_power_profile_mode, 4010 .set_power_profile_mode = smu_set_power_profile_mode, 4011 .odn_edit_dpm_table = smu_od_edit_dpm_table, 4012 .set_mp1_state = smu_set_mp1_state, 4013 .gfx_state_change_set = smu_gfx_state_change_set, 4014 /* export to DC */ 4015 .get_sclk = smu_get_sclk, 4016 .get_mclk = smu_get_mclk, 4017 .display_configuration_change = smu_display_configuration_change, 4018 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 4019 .display_clock_voltage_request = smu_display_clock_voltage_request, 4020 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 4021 .set_active_display_count = smu_set_display_count, 4022 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 4023 .get_asic_baco_capability = smu_get_baco_capability, 4024 .set_asic_baco_state = smu_baco_set_state, 4025 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 4026 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 4027 .asic_reset_mode_2 = smu_mode2_reset, 4028 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 4029 .set_df_cstate = smu_set_df_cstate, 4030 .set_xgmi_pstate = smu_set_xgmi_pstate, 4031 .get_gpu_metrics = smu_sys_get_gpu_metrics, 4032 .get_pm_metrics = smu_sys_get_pm_metrics, 4033 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 4034 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 4035 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 4036 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 4037 .get_dpm_clock_table = smu_get_dpm_clock_table, 4038 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 4039 .get_xcp_metrics = smu_sys_get_xcp_metrics, 4040 .get_temp_metrics = smu_sys_get_temp_metrics, 4041 .temp_metrics_is_supported = smu_temp_metrics_is_supported, 4042 }; 4043 4044 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 4045 uint64_t event_arg) 4046 { 4047 int ret = -EINVAL; 4048 4049 if (smu->ppt_funcs->wait_for_event) 4050 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 4051 4052 return ret; 4053 } 4054 4055 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 4056 { 4057 4058 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 4059 return -EOPNOTSUPP; 4060 4061 /* Confirm the buffer allocated is of correct size */ 4062 if (size != smu->stb_context.stb_buf_size) 4063 return -EINVAL; 4064 4065 /* 4066 * No need to lock smu mutex as we access STB directly through MMIO 4067 * and not going through SMU messaging route (for now at least). 4068 * For registers access rely on implementation internal locking. 4069 */ 4070 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 4071 } 4072 4073 #if defined(CONFIG_DEBUG_FS) 4074 4075 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 4076 { 4077 struct amdgpu_device *adev = filp->f_inode->i_private; 4078 struct smu_context *smu = adev->powerplay.pp_handle; 4079 unsigned char *buf; 4080 int r; 4081 4082 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 4083 if (!buf) 4084 return -ENOMEM; 4085 4086 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 4087 if (r) 4088 goto out; 4089 4090 filp->private_data = buf; 4091 4092 return 0; 4093 4094 out: 4095 kvfree(buf); 4096 return r; 4097 } 4098 4099 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 4100 loff_t *pos) 4101 { 4102 struct amdgpu_device *adev = filp->f_inode->i_private; 4103 struct smu_context *smu = adev->powerplay.pp_handle; 4104 4105 4106 if (!filp->private_data) 4107 return -EINVAL; 4108 4109 return simple_read_from_buffer(buf, 4110 size, 4111 pos, filp->private_data, 4112 smu->stb_context.stb_buf_size); 4113 } 4114 4115 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 4116 { 4117 kvfree(filp->private_data); 4118 filp->private_data = NULL; 4119 4120 return 0; 4121 } 4122 4123 /* 4124 * We have to define not only read method but also 4125 * open and release because .read takes up to PAGE_SIZE 4126 * data each time so and so is invoked multiple times. 4127 * We allocate the STB buffer in .open and release it 4128 * in .release 4129 */ 4130 static const struct file_operations smu_stb_debugfs_fops = { 4131 .owner = THIS_MODULE, 4132 .open = smu_stb_debugfs_open, 4133 .read = smu_stb_debugfs_read, 4134 .release = smu_stb_debugfs_release, 4135 .llseek = default_llseek, 4136 }; 4137 4138 #endif 4139 4140 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 4141 { 4142 #if defined(CONFIG_DEBUG_FS) 4143 4144 struct smu_context *smu = adev->powerplay.pp_handle; 4145 4146 if (!smu || (!smu->stb_context.stb_buf_size)) 4147 return; 4148 4149 debugfs_create_file_size("amdgpu_smu_stb_dump", 4150 S_IRUSR, 4151 adev_to_drm(adev)->primary->debugfs_root, 4152 adev, 4153 &smu_stb_debugfs_fops, 4154 smu->stb_context.stb_buf_size); 4155 #endif 4156 } 4157 4158 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 4159 { 4160 int ret = 0; 4161 4162 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 4163 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 4164 4165 return ret; 4166 } 4167 4168 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 4169 { 4170 int ret = 0; 4171 4172 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 4173 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 4174 4175 return ret; 4176 } 4177 4178 int smu_send_rma_reason(struct smu_context *smu) 4179 { 4180 int ret = 0; 4181 4182 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 4183 ret = smu->ppt_funcs->send_rma_reason(smu); 4184 4185 return ret; 4186 } 4187 4188 /** 4189 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 4190 * @smu: smu_context pointer 4191 * 4192 * This function checks if the SMU supports resetting the SDMA engine. 4193 * It returns true if supported, false otherwise. 4194 */ 4195 bool smu_reset_sdma_is_supported(struct smu_context *smu) 4196 { 4197 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); 4198 } 4199 4200 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4201 { 4202 int ret = 0; 4203 4204 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4205 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4206 4207 return ret; 4208 } 4209 4210 bool smu_reset_vcn_is_supported(struct smu_context *smu) 4211 { 4212 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET); 4213 } 4214 4215 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4216 { 4217 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4218 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4219 4220 return 0; 4221 } 4222