1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "amd_pcie.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 static const struct amd_pm_funcs swsmu_pm_funcs; 61 static int smu_force_smuclk_levels(struct smu_context *smu, 62 enum smu_clk_type clk_type, 63 uint32_t mask); 64 static int smu_handle_task(struct smu_context *smu, 65 enum amd_dpm_forced_level level, 66 enum amd_pp_task task_id); 67 static int smu_reset(struct smu_context *smu); 68 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 69 static int smu_set_fan_control_mode(void *handle, u32 value); 70 static int smu_set_power_limit(void *handle, uint32_t limit); 71 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 72 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 73 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 74 75 static int smu_sys_get_pp_feature_mask(void *handle, 76 char *buf) 77 { 78 struct smu_context *smu = handle; 79 80 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 81 return -EOPNOTSUPP; 82 83 return smu_get_pp_feature_mask(smu, buf); 84 } 85 86 static int smu_sys_set_pp_feature_mask(void *handle, 87 uint64_t new_mask) 88 { 89 struct smu_context *smu = handle; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 return smu_set_pp_feature_mask(smu, new_mask); 95 } 96 97 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 98 { 99 if (!smu->ppt_funcs->set_gfx_off_residency) 100 return -EINVAL; 101 102 return smu_set_gfx_off_residency(smu, value); 103 } 104 105 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 106 { 107 if (!smu->ppt_funcs->get_gfx_off_residency) 108 return -EINVAL; 109 110 return smu_get_gfx_off_residency(smu, value); 111 } 112 113 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 114 { 115 if (!smu->ppt_funcs->get_gfx_off_entrycount) 116 return -EINVAL; 117 118 return smu_get_gfx_off_entrycount(smu, value); 119 } 120 121 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 122 { 123 if (!smu->ppt_funcs->get_gfx_off_status) 124 return -EINVAL; 125 126 *value = smu_get_gfx_off_status(smu); 127 128 return 0; 129 } 130 131 int smu_set_soft_freq_range(struct smu_context *smu, 132 enum smu_clk_type clk_type, 133 uint32_t min, 134 uint32_t max) 135 { 136 int ret = 0; 137 138 if (smu->ppt_funcs->set_soft_freq_limited_range) 139 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 140 clk_type, 141 min, 142 max); 143 144 return ret; 145 } 146 147 int smu_get_dpm_freq_range(struct smu_context *smu, 148 enum smu_clk_type clk_type, 149 uint32_t *min, 150 uint32_t *max) 151 { 152 int ret = -ENOTSUPP; 153 154 if (!min && !max) 155 return -EINVAL; 156 157 if (smu->ppt_funcs->get_dpm_ultimate_freq) 158 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 159 clk_type, 160 min, 161 max); 162 163 return ret; 164 } 165 166 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 167 { 168 int ret = 0; 169 struct amdgpu_device *adev = smu->adev; 170 171 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 172 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 173 if (ret) 174 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 175 } 176 return ret; 177 } 178 179 static u32 smu_get_mclk(void *handle, bool low) 180 { 181 struct smu_context *smu = handle; 182 uint32_t clk_freq; 183 int ret = 0; 184 185 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 186 low ? &clk_freq : NULL, 187 !low ? &clk_freq : NULL); 188 if (ret) 189 return 0; 190 return clk_freq * 100; 191 } 192 193 static u32 smu_get_sclk(void *handle, bool low) 194 { 195 struct smu_context *smu = handle; 196 uint32_t clk_freq; 197 int ret = 0; 198 199 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 200 low ? &clk_freq : NULL, 201 !low ? &clk_freq : NULL); 202 if (ret) 203 return 0; 204 return clk_freq * 100; 205 } 206 207 static int smu_set_gfx_imu_enable(struct smu_context *smu) 208 { 209 struct amdgpu_device *adev = smu->adev; 210 211 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 212 return 0; 213 214 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 215 return 0; 216 217 return smu_set_gfx_power_up_by_imu(smu); 218 } 219 220 static bool is_vcn_enabled(struct amdgpu_device *adev) 221 { 222 int i; 223 224 for (i = 0; i < adev->num_ip_blocks; i++) { 225 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 226 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 227 !adev->ip_blocks[i].status.valid) 228 return false; 229 } 230 231 return true; 232 } 233 234 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 235 bool enable) 236 { 237 struct smu_power_context *smu_power = &smu->smu_power; 238 struct smu_power_gate *power_gate = &smu_power->power_gate; 239 int ret = 0; 240 241 /* 242 * don't poweron vcn/jpeg when they are skipped. 243 */ 244 if (!is_vcn_enabled(smu->adev)) 245 return 0; 246 247 if (!smu->ppt_funcs->dpm_set_vcn_enable) 248 return 0; 249 250 if (atomic_read(&power_gate->vcn_gated) ^ enable) 251 return 0; 252 253 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 254 if (!ret) 255 atomic_set(&power_gate->vcn_gated, !enable); 256 257 return ret; 258 } 259 260 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 261 bool enable) 262 { 263 struct smu_power_context *smu_power = &smu->smu_power; 264 struct smu_power_gate *power_gate = &smu_power->power_gate; 265 int ret = 0; 266 267 if (!is_vcn_enabled(smu->adev)) 268 return 0; 269 270 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 271 return 0; 272 273 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 274 return 0; 275 276 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 277 if (!ret) 278 atomic_set(&power_gate->jpeg_gated, !enable); 279 280 return ret; 281 } 282 283 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 284 bool enable) 285 { 286 struct smu_power_context *smu_power = &smu->smu_power; 287 struct smu_power_gate *power_gate = &smu_power->power_gate; 288 int ret = 0; 289 290 if (!smu->ppt_funcs->dpm_set_vpe_enable) 291 return 0; 292 293 if (atomic_read(&power_gate->vpe_gated) ^ enable) 294 return 0; 295 296 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 297 if (!ret) 298 atomic_set(&power_gate->vpe_gated, !enable); 299 300 return ret; 301 } 302 303 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 304 bool enable) 305 { 306 struct smu_power_context *smu_power = &smu->smu_power; 307 struct smu_power_gate *power_gate = &smu_power->power_gate; 308 int ret = 0; 309 310 if (!smu->adev->enable_umsch_mm) 311 return 0; 312 313 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 314 return 0; 315 316 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 317 return 0; 318 319 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 320 if (!ret) 321 atomic_set(&power_gate->umsch_mm_gated, !enable); 322 323 return ret; 324 } 325 326 /** 327 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 328 * 329 * @handle: smu_context pointer 330 * @block_type: the IP block to power gate/ungate 331 * @gate: to power gate if true, ungate otherwise 332 * 333 * This API uses no smu->mutex lock protection due to: 334 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 335 * This is guarded to be race condition free by the caller. 336 * 2. Or get called on user setting request of power_dpm_force_performance_level. 337 * Under this case, the smu->mutex lock protection is already enforced on 338 * the parent API smu_force_performance_level of the call path. 339 */ 340 static int smu_dpm_set_power_gate(void *handle, 341 uint32_t block_type, 342 bool gate) 343 { 344 struct smu_context *smu = handle; 345 int ret = 0; 346 347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 348 dev_WARN(smu->adev->dev, 349 "SMU uninitialized but power %s requested for %u!\n", 350 gate ? "gate" : "ungate", block_type); 351 return -EOPNOTSUPP; 352 } 353 354 switch (block_type) { 355 /* 356 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 357 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 358 */ 359 case AMD_IP_BLOCK_TYPE_UVD: 360 case AMD_IP_BLOCK_TYPE_VCN: 361 ret = smu_dpm_set_vcn_enable(smu, !gate); 362 if (ret) 363 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 364 gate ? "gate" : "ungate"); 365 break; 366 case AMD_IP_BLOCK_TYPE_GFX: 367 ret = smu_gfx_off_control(smu, gate); 368 if (ret) 369 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 370 gate ? "enable" : "disable"); 371 break; 372 case AMD_IP_BLOCK_TYPE_SDMA: 373 ret = smu_powergate_sdma(smu, gate); 374 if (ret) 375 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 376 gate ? "gate" : "ungate"); 377 break; 378 case AMD_IP_BLOCK_TYPE_JPEG: 379 ret = smu_dpm_set_jpeg_enable(smu, !gate); 380 if (ret) 381 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 382 gate ? "gate" : "ungate"); 383 break; 384 case AMD_IP_BLOCK_TYPE_VPE: 385 ret = smu_dpm_set_vpe_enable(smu, !gate); 386 if (ret) 387 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 388 gate ? "gate" : "ungate"); 389 break; 390 default: 391 dev_err(smu->adev->dev, "Unsupported block type!\n"); 392 return -EINVAL; 393 } 394 395 return ret; 396 } 397 398 /** 399 * smu_set_user_clk_dependencies - set user profile clock dependencies 400 * 401 * @smu: smu_context pointer 402 * @clk: enum smu_clk_type type 403 * 404 * Enable/Disable the clock dependency for the @clk type. 405 */ 406 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 407 { 408 if (smu->adev->in_suspend) 409 return; 410 411 if (clk == SMU_MCLK) { 412 smu->user_dpm_profile.clk_dependency = 0; 413 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 414 } else if (clk == SMU_FCLK) { 415 /* MCLK takes precedence over FCLK */ 416 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 417 return; 418 419 smu->user_dpm_profile.clk_dependency = 0; 420 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 421 } else if (clk == SMU_SOCCLK) { 422 /* MCLK takes precedence over SOCCLK */ 423 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 424 return; 425 426 smu->user_dpm_profile.clk_dependency = 0; 427 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 428 } else 429 /* Add clk dependencies here, if any */ 430 return; 431 } 432 433 /** 434 * smu_restore_dpm_user_profile - reinstate user dpm profile 435 * 436 * @smu: smu_context pointer 437 * 438 * Restore the saved user power configurations include power limit, 439 * clock frequencies, fan control mode and fan speed. 440 */ 441 static void smu_restore_dpm_user_profile(struct smu_context *smu) 442 { 443 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 444 int ret = 0; 445 446 if (!smu->adev->in_suspend) 447 return; 448 449 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 450 return; 451 452 /* Enable restore flag */ 453 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 454 455 /* set the user dpm power limit */ 456 if (smu->user_dpm_profile.power_limit) { 457 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 458 if (ret) 459 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 460 } 461 462 /* set the user dpm clock configurations */ 463 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 464 enum smu_clk_type clk_type; 465 466 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 467 /* 468 * Iterate over smu clk type and force the saved user clk 469 * configs, skip if clock dependency is enabled 470 */ 471 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 472 smu->user_dpm_profile.clk_mask[clk_type]) { 473 ret = smu_force_smuclk_levels(smu, clk_type, 474 smu->user_dpm_profile.clk_mask[clk_type]); 475 if (ret) 476 dev_err(smu->adev->dev, 477 "Failed to set clock type = %d\n", clk_type); 478 } 479 } 480 } 481 482 /* set the user dpm fan configurations */ 483 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 484 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 485 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 486 if (ret != -EOPNOTSUPP) { 487 smu->user_dpm_profile.fan_speed_pwm = 0; 488 smu->user_dpm_profile.fan_speed_rpm = 0; 489 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 490 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 491 } 492 493 if (smu->user_dpm_profile.fan_speed_pwm) { 494 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 495 if (ret != -EOPNOTSUPP) 496 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 497 } 498 499 if (smu->user_dpm_profile.fan_speed_rpm) { 500 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 501 if (ret != -EOPNOTSUPP) 502 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 503 } 504 } 505 506 /* Restore user customized OD settings */ 507 if (smu->user_dpm_profile.user_od) { 508 if (smu->ppt_funcs->restore_user_od_settings) { 509 ret = smu->ppt_funcs->restore_user_od_settings(smu); 510 if (ret) 511 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 512 } 513 } 514 515 /* Disable restore flag */ 516 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 517 } 518 519 static int smu_get_power_num_states(void *handle, 520 struct pp_states_info *state_info) 521 { 522 if (!state_info) 523 return -EINVAL; 524 525 /* not support power state */ 526 memset(state_info, 0, sizeof(struct pp_states_info)); 527 state_info->nums = 1; 528 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 529 530 return 0; 531 } 532 533 bool is_support_sw_smu(struct amdgpu_device *adev) 534 { 535 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 536 if (adev->asic_type == CHIP_VEGA20) 537 return false; 538 539 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 540 return true; 541 542 return false; 543 } 544 545 bool is_support_cclk_dpm(struct amdgpu_device *adev) 546 { 547 struct smu_context *smu = adev->powerplay.pp_handle; 548 549 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 550 return false; 551 552 return true; 553 } 554 555 556 static int smu_sys_get_pp_table(void *handle, 557 char **table) 558 { 559 struct smu_context *smu = handle; 560 struct smu_table_context *smu_table = &smu->smu_table; 561 562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 563 return -EOPNOTSUPP; 564 565 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 566 return -EINVAL; 567 568 if (smu_table->hardcode_pptable) 569 *table = smu_table->hardcode_pptable; 570 else 571 *table = smu_table->power_play_table; 572 573 return smu_table->power_play_table_size; 574 } 575 576 static int smu_sys_set_pp_table(void *handle, 577 const char *buf, 578 size_t size) 579 { 580 struct smu_context *smu = handle; 581 struct smu_table_context *smu_table = &smu->smu_table; 582 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 583 int ret = 0; 584 585 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 586 return -EOPNOTSUPP; 587 588 if (header->usStructureSize != size) { 589 dev_err(smu->adev->dev, "pp table size not matched !\n"); 590 return -EIO; 591 } 592 593 if (!smu_table->hardcode_pptable) { 594 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 595 if (!smu_table->hardcode_pptable) 596 return -ENOMEM; 597 } 598 599 memcpy(smu_table->hardcode_pptable, buf, size); 600 smu_table->power_play_table = smu_table->hardcode_pptable; 601 smu_table->power_play_table_size = size; 602 603 /* 604 * Special hw_fini action(for Navi1x, the DPMs disablement will be 605 * skipped) may be needed for custom pptable uploading. 606 */ 607 smu->uploading_custom_pp_table = true; 608 609 ret = smu_reset(smu); 610 if (ret) 611 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 612 613 smu->uploading_custom_pp_table = false; 614 615 return ret; 616 } 617 618 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 619 { 620 struct smu_feature *feature = &smu->smu_feature; 621 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 622 int ret = 0; 623 624 /* 625 * With SCPM enabled, the allowed featuremasks setting(via 626 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 627 * That means there is no way to let PMFW knows the settings below. 628 * Thus, we just assume all the features are allowed under 629 * such scenario. 630 */ 631 if (smu->adev->scpm_enabled) { 632 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 633 return 0; 634 } 635 636 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 637 638 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 639 SMU_FEATURE_MAX/32); 640 if (ret) 641 return ret; 642 643 bitmap_or(feature->allowed, feature->allowed, 644 (unsigned long *)allowed_feature_mask, 645 feature->feature_num); 646 647 return ret; 648 } 649 650 static int smu_set_funcs(struct amdgpu_device *adev) 651 { 652 struct smu_context *smu = adev->powerplay.pp_handle; 653 654 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 655 smu->od_enabled = true; 656 657 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 658 case IP_VERSION(11, 0, 0): 659 case IP_VERSION(11, 0, 5): 660 case IP_VERSION(11, 0, 9): 661 navi10_set_ppt_funcs(smu); 662 break; 663 case IP_VERSION(11, 0, 7): 664 case IP_VERSION(11, 0, 11): 665 case IP_VERSION(11, 0, 12): 666 case IP_VERSION(11, 0, 13): 667 sienna_cichlid_set_ppt_funcs(smu); 668 break; 669 case IP_VERSION(12, 0, 0): 670 case IP_VERSION(12, 0, 1): 671 renoir_set_ppt_funcs(smu); 672 break; 673 case IP_VERSION(11, 5, 0): 674 vangogh_set_ppt_funcs(smu); 675 break; 676 case IP_VERSION(13, 0, 1): 677 case IP_VERSION(13, 0, 3): 678 case IP_VERSION(13, 0, 8): 679 yellow_carp_set_ppt_funcs(smu); 680 break; 681 case IP_VERSION(13, 0, 4): 682 case IP_VERSION(13, 0, 11): 683 smu_v13_0_4_set_ppt_funcs(smu); 684 break; 685 case IP_VERSION(13, 0, 5): 686 smu_v13_0_5_set_ppt_funcs(smu); 687 break; 688 case IP_VERSION(11, 0, 8): 689 cyan_skillfish_set_ppt_funcs(smu); 690 break; 691 case IP_VERSION(11, 0, 2): 692 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 693 arcturus_set_ppt_funcs(smu); 694 /* OD is not supported on Arcturus */ 695 smu->od_enabled = false; 696 break; 697 case IP_VERSION(13, 0, 2): 698 aldebaran_set_ppt_funcs(smu); 699 /* Enable pp_od_clk_voltage node */ 700 smu->od_enabled = true; 701 break; 702 case IP_VERSION(13, 0, 0): 703 case IP_VERSION(13, 0, 10): 704 smu_v13_0_0_set_ppt_funcs(smu); 705 break; 706 case IP_VERSION(13, 0, 6): 707 smu_v13_0_6_set_ppt_funcs(smu); 708 /* Enable pp_od_clk_voltage node */ 709 smu->od_enabled = true; 710 break; 711 case IP_VERSION(13, 0, 7): 712 smu_v13_0_7_set_ppt_funcs(smu); 713 break; 714 case IP_VERSION(14, 0, 0): 715 case IP_VERSION(14, 0, 1): 716 smu_v14_0_0_set_ppt_funcs(smu); 717 break; 718 default: 719 return -EINVAL; 720 } 721 722 return 0; 723 } 724 725 static int smu_early_init(void *handle) 726 { 727 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 728 struct smu_context *smu; 729 int r; 730 731 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 732 if (!smu) 733 return -ENOMEM; 734 735 smu->adev = adev; 736 smu->pm_enabled = !!amdgpu_dpm; 737 smu->is_apu = false; 738 smu->smu_baco.state = SMU_BACO_STATE_NONE; 739 smu->smu_baco.platform_support = false; 740 smu->smu_baco.maco_support = false; 741 smu->user_dpm_profile.fan_mode = -1; 742 743 mutex_init(&smu->message_lock); 744 745 adev->powerplay.pp_handle = smu; 746 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 747 748 r = smu_set_funcs(adev); 749 if (r) 750 return r; 751 return smu_init_microcode(smu); 752 } 753 754 static int smu_set_default_dpm_table(struct smu_context *smu) 755 { 756 struct amdgpu_device *adev = smu->adev; 757 struct smu_power_context *smu_power = &smu->smu_power; 758 struct smu_power_gate *power_gate = &smu_power->power_gate; 759 int vcn_gate, jpeg_gate; 760 int ret = 0; 761 762 if (!smu->ppt_funcs->set_default_dpm_table) 763 return 0; 764 765 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 766 vcn_gate = atomic_read(&power_gate->vcn_gated); 767 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 768 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 769 770 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 771 ret = smu_dpm_set_vcn_enable(smu, true); 772 if (ret) 773 return ret; 774 } 775 776 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 777 ret = smu_dpm_set_jpeg_enable(smu, true); 778 if (ret) 779 goto err_out; 780 } 781 782 ret = smu->ppt_funcs->set_default_dpm_table(smu); 783 if (ret) 784 dev_err(smu->adev->dev, 785 "Failed to setup default dpm clock tables!\n"); 786 787 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 788 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 789 err_out: 790 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 791 smu_dpm_set_vcn_enable(smu, !vcn_gate); 792 793 return ret; 794 } 795 796 static int smu_apply_default_config_table_settings(struct smu_context *smu) 797 { 798 struct amdgpu_device *adev = smu->adev; 799 int ret = 0; 800 801 ret = smu_get_default_config_table_settings(smu, 802 &adev->pm.config_table); 803 if (ret) 804 return ret; 805 806 return smu_set_config_table(smu, &adev->pm.config_table); 807 } 808 809 static int smu_late_init(void *handle) 810 { 811 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 812 struct smu_context *smu = adev->powerplay.pp_handle; 813 int ret = 0; 814 815 smu_set_fine_grain_gfx_freq_parameters(smu); 816 817 if (!smu->pm_enabled) 818 return 0; 819 820 ret = smu_post_init(smu); 821 if (ret) { 822 dev_err(adev->dev, "Failed to post smu init!\n"); 823 return ret; 824 } 825 826 /* 827 * Explicitly notify PMFW the power mode the system in. Since 828 * the PMFW may boot the ASIC with a different mode. 829 * For those supporting ACDC switch via gpio, PMFW will 830 * handle the switch automatically. Driver involvement 831 * is unnecessary. 832 */ 833 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 834 smu_set_ac_dc(smu); 835 836 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 837 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 838 return 0; 839 840 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 841 ret = smu_set_default_od_settings(smu); 842 if (ret) { 843 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 844 return ret; 845 } 846 } 847 848 ret = smu_populate_umd_state_clk(smu); 849 if (ret) { 850 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 851 return ret; 852 } 853 854 ret = smu_get_asic_power_limits(smu, 855 &smu->current_power_limit, 856 &smu->default_power_limit, 857 &smu->max_power_limit, 858 &smu->min_power_limit); 859 if (ret) { 860 dev_err(adev->dev, "Failed to get asic power limits!\n"); 861 return ret; 862 } 863 864 if (!amdgpu_sriov_vf(adev)) 865 smu_get_unique_id(smu); 866 867 smu_get_fan_parameters(smu); 868 869 smu_handle_task(smu, 870 smu->smu_dpm.dpm_level, 871 AMD_PP_TASK_COMPLETE_INIT); 872 873 ret = smu_apply_default_config_table_settings(smu); 874 if (ret && (ret != -EOPNOTSUPP)) { 875 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 876 return ret; 877 } 878 879 smu_restore_dpm_user_profile(smu); 880 881 return 0; 882 } 883 884 static int smu_init_fb_allocations(struct smu_context *smu) 885 { 886 struct amdgpu_device *adev = smu->adev; 887 struct smu_table_context *smu_table = &smu->smu_table; 888 struct smu_table *tables = smu_table->tables; 889 struct smu_table *driver_table = &(smu_table->driver_table); 890 uint32_t max_table_size = 0; 891 int ret, i; 892 893 /* VRAM allocation for tool table */ 894 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 895 ret = amdgpu_bo_create_kernel(adev, 896 tables[SMU_TABLE_PMSTATUSLOG].size, 897 tables[SMU_TABLE_PMSTATUSLOG].align, 898 tables[SMU_TABLE_PMSTATUSLOG].domain, 899 &tables[SMU_TABLE_PMSTATUSLOG].bo, 900 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 901 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 902 if (ret) { 903 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 904 return ret; 905 } 906 } 907 908 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 909 /* VRAM allocation for driver table */ 910 for (i = 0; i < SMU_TABLE_COUNT; i++) { 911 if (tables[i].size == 0) 912 continue; 913 914 /* If one of the tables has VRAM domain restriction, keep it in 915 * VRAM 916 */ 917 if ((tables[i].domain & 918 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 919 AMDGPU_GEM_DOMAIN_VRAM) 920 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 921 922 if (i == SMU_TABLE_PMSTATUSLOG) 923 continue; 924 925 if (max_table_size < tables[i].size) 926 max_table_size = tables[i].size; 927 } 928 929 driver_table->size = max_table_size; 930 driver_table->align = PAGE_SIZE; 931 932 ret = amdgpu_bo_create_kernel(adev, 933 driver_table->size, 934 driver_table->align, 935 driver_table->domain, 936 &driver_table->bo, 937 &driver_table->mc_address, 938 &driver_table->cpu_addr); 939 if (ret) { 940 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 941 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 942 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 943 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 944 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 945 } 946 947 return ret; 948 } 949 950 static int smu_fini_fb_allocations(struct smu_context *smu) 951 { 952 struct smu_table_context *smu_table = &smu->smu_table; 953 struct smu_table *tables = smu_table->tables; 954 struct smu_table *driver_table = &(smu_table->driver_table); 955 956 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 957 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 958 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 959 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 960 961 amdgpu_bo_free_kernel(&driver_table->bo, 962 &driver_table->mc_address, 963 &driver_table->cpu_addr); 964 965 return 0; 966 } 967 968 /** 969 * smu_alloc_memory_pool - allocate memory pool in the system memory 970 * 971 * @smu: amdgpu_device pointer 972 * 973 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 974 * and DramLogSetDramAddr can notify it changed. 975 * 976 * Returns 0 on success, error on failure. 977 */ 978 static int smu_alloc_memory_pool(struct smu_context *smu) 979 { 980 struct amdgpu_device *adev = smu->adev; 981 struct smu_table_context *smu_table = &smu->smu_table; 982 struct smu_table *memory_pool = &smu_table->memory_pool; 983 uint64_t pool_size = smu->pool_size; 984 int ret = 0; 985 986 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 987 return ret; 988 989 memory_pool->size = pool_size; 990 memory_pool->align = PAGE_SIZE; 991 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 992 993 switch (pool_size) { 994 case SMU_MEMORY_POOL_SIZE_256_MB: 995 case SMU_MEMORY_POOL_SIZE_512_MB: 996 case SMU_MEMORY_POOL_SIZE_1_GB: 997 case SMU_MEMORY_POOL_SIZE_2_GB: 998 ret = amdgpu_bo_create_kernel(adev, 999 memory_pool->size, 1000 memory_pool->align, 1001 memory_pool->domain, 1002 &memory_pool->bo, 1003 &memory_pool->mc_address, 1004 &memory_pool->cpu_addr); 1005 if (ret) 1006 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1007 break; 1008 default: 1009 break; 1010 } 1011 1012 return ret; 1013 } 1014 1015 static int smu_free_memory_pool(struct smu_context *smu) 1016 { 1017 struct smu_table_context *smu_table = &smu->smu_table; 1018 struct smu_table *memory_pool = &smu_table->memory_pool; 1019 1020 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1021 return 0; 1022 1023 amdgpu_bo_free_kernel(&memory_pool->bo, 1024 &memory_pool->mc_address, 1025 &memory_pool->cpu_addr); 1026 1027 memset(memory_pool, 0, sizeof(struct smu_table)); 1028 1029 return 0; 1030 } 1031 1032 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1033 { 1034 struct smu_table_context *smu_table = &smu->smu_table; 1035 struct smu_table *dummy_read_1_table = 1036 &smu_table->dummy_read_1_table; 1037 struct amdgpu_device *adev = smu->adev; 1038 int ret = 0; 1039 1040 if (!dummy_read_1_table->size) 1041 return 0; 1042 1043 ret = amdgpu_bo_create_kernel(adev, 1044 dummy_read_1_table->size, 1045 dummy_read_1_table->align, 1046 dummy_read_1_table->domain, 1047 &dummy_read_1_table->bo, 1048 &dummy_read_1_table->mc_address, 1049 &dummy_read_1_table->cpu_addr); 1050 if (ret) 1051 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1052 1053 return ret; 1054 } 1055 1056 static void smu_free_dummy_read_table(struct smu_context *smu) 1057 { 1058 struct smu_table_context *smu_table = &smu->smu_table; 1059 struct smu_table *dummy_read_1_table = 1060 &smu_table->dummy_read_1_table; 1061 1062 1063 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1064 &dummy_read_1_table->mc_address, 1065 &dummy_read_1_table->cpu_addr); 1066 1067 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1068 } 1069 1070 static int smu_smc_table_sw_init(struct smu_context *smu) 1071 { 1072 int ret; 1073 1074 /** 1075 * Create smu_table structure, and init smc tables such as 1076 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1077 */ 1078 ret = smu_init_smc_tables(smu); 1079 if (ret) { 1080 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1081 return ret; 1082 } 1083 1084 /** 1085 * Create smu_power_context structure, and allocate smu_dpm_context and 1086 * context size to fill the smu_power_context data. 1087 */ 1088 ret = smu_init_power(smu); 1089 if (ret) { 1090 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1091 return ret; 1092 } 1093 1094 /* 1095 * allocate vram bos to store smc table contents. 1096 */ 1097 ret = smu_init_fb_allocations(smu); 1098 if (ret) 1099 return ret; 1100 1101 ret = smu_alloc_memory_pool(smu); 1102 if (ret) 1103 return ret; 1104 1105 ret = smu_alloc_dummy_read_table(smu); 1106 if (ret) 1107 return ret; 1108 1109 ret = smu_i2c_init(smu); 1110 if (ret) 1111 return ret; 1112 1113 return 0; 1114 } 1115 1116 static int smu_smc_table_sw_fini(struct smu_context *smu) 1117 { 1118 int ret; 1119 1120 smu_i2c_fini(smu); 1121 1122 smu_free_dummy_read_table(smu); 1123 1124 ret = smu_free_memory_pool(smu); 1125 if (ret) 1126 return ret; 1127 1128 ret = smu_fini_fb_allocations(smu); 1129 if (ret) 1130 return ret; 1131 1132 ret = smu_fini_power(smu); 1133 if (ret) { 1134 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1135 return ret; 1136 } 1137 1138 ret = smu_fini_smc_tables(smu); 1139 if (ret) { 1140 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1141 return ret; 1142 } 1143 1144 return 0; 1145 } 1146 1147 static void smu_throttling_logging_work_fn(struct work_struct *work) 1148 { 1149 struct smu_context *smu = container_of(work, struct smu_context, 1150 throttling_logging_work); 1151 1152 smu_log_thermal_throttling(smu); 1153 } 1154 1155 static void smu_interrupt_work_fn(struct work_struct *work) 1156 { 1157 struct smu_context *smu = container_of(work, struct smu_context, 1158 interrupt_work); 1159 1160 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1161 smu->ppt_funcs->interrupt_work(smu); 1162 } 1163 1164 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1165 { 1166 struct smu_context *smu = 1167 container_of(work, struct smu_context, swctf_delayed_work.work); 1168 struct smu_temperature_range *range = 1169 &smu->thermal_range; 1170 struct amdgpu_device *adev = smu->adev; 1171 uint32_t hotspot_tmp, size; 1172 1173 /* 1174 * If the hotspot temperature is confirmed as below SW CTF setting point 1175 * after the delay enforced, nothing will be done. 1176 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1177 */ 1178 if (range->software_shutdown_temp && 1179 smu->ppt_funcs->read_sensor && 1180 !smu->ppt_funcs->read_sensor(smu, 1181 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1182 &hotspot_tmp, 1183 &size) && 1184 hotspot_tmp / 1000 < range->software_shutdown_temp) 1185 return; 1186 1187 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1188 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1189 orderly_poweroff(true); 1190 } 1191 1192 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1193 { 1194 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1195 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1196 return; 1197 } 1198 1199 /* PMFW put PLPD into default policy after enabling the feature */ 1200 if (smu_feature_is_enabled(smu, 1201 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) 1202 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1203 else 1204 smu->plpd_mode = XGMI_PLPD_NONE; 1205 } 1206 1207 static int smu_sw_init(void *handle) 1208 { 1209 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1210 struct smu_context *smu = adev->powerplay.pp_handle; 1211 int ret; 1212 1213 smu->pool_size = adev->pm.smu_prv_buffer_size; 1214 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1215 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1216 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1217 1218 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1219 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1220 atomic64_set(&smu->throttle_int_counter, 0); 1221 smu->watermarks_bitmap = 0; 1222 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1223 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1224 1225 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1226 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1227 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1228 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1229 1230 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1231 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1232 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1233 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1234 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1235 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1236 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1237 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1238 1239 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1240 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1241 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1242 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1243 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1244 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1245 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1246 smu->display_config = &adev->pm.pm_display_cfg; 1247 1248 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1249 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1250 1251 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1252 smu_swctf_delayed_work_handler); 1253 1254 ret = smu_smc_table_sw_init(smu); 1255 if (ret) { 1256 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1257 return ret; 1258 } 1259 1260 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1261 ret = smu_get_vbios_bootup_values(smu); 1262 if (ret) { 1263 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1264 return ret; 1265 } 1266 1267 ret = smu_init_pptable_microcode(smu); 1268 if (ret) { 1269 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1270 return ret; 1271 } 1272 1273 ret = smu_register_irq_handler(smu); 1274 if (ret) { 1275 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1276 return ret; 1277 } 1278 1279 /* If there is no way to query fan control mode, fan control is not supported */ 1280 if (!smu->ppt_funcs->get_fan_control_mode) 1281 smu->adev->pm.no_fan = true; 1282 1283 return 0; 1284 } 1285 1286 static int smu_sw_fini(void *handle) 1287 { 1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1289 struct smu_context *smu = adev->powerplay.pp_handle; 1290 int ret; 1291 1292 ret = smu_smc_table_sw_fini(smu); 1293 if (ret) { 1294 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1295 return ret; 1296 } 1297 1298 smu_fini_microcode(smu); 1299 1300 return 0; 1301 } 1302 1303 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1304 { 1305 struct amdgpu_device *adev = smu->adev; 1306 struct smu_temperature_range *range = 1307 &smu->thermal_range; 1308 int ret = 0; 1309 1310 if (!smu->ppt_funcs->get_thermal_temperature_range) 1311 return 0; 1312 1313 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1314 if (ret) 1315 return ret; 1316 1317 adev->pm.dpm.thermal.min_temp = range->min; 1318 adev->pm.dpm.thermal.max_temp = range->max; 1319 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1320 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1321 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1322 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1323 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1324 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1325 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1326 1327 return ret; 1328 } 1329 1330 /** 1331 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1332 * 1333 * @smu: smu_context pointer 1334 * 1335 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1336 * Returns 0 on success, error on failure. 1337 */ 1338 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1339 { 1340 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1341 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1342 struct amdgpu_device *adev = smu->adev; 1343 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1344 uint64_t start, end; 1345 int ret, i, j; 1346 1347 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1348 if (ret) { 1349 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1350 return ret; 1351 } 1352 1353 /* 1354 * The exclusion ranges array we got might be filled with holes and duplicate 1355 * entries. For example: 1356 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1357 * We need to do some sortups to eliminate those holes and duplicate entries. 1358 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1359 */ 1360 for (i = 0; i < num_of_wbrf_ranges; i++) { 1361 start = wifi_bands[i].start; 1362 end = wifi_bands[i].end; 1363 1364 /* get the last valid entry to fill the intermediate hole */ 1365 if (!start && !end) { 1366 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1367 if (wifi_bands[j].start && wifi_bands[j].end) 1368 break; 1369 1370 /* no valid entry left */ 1371 if (j <= i) 1372 break; 1373 1374 start = wifi_bands[i].start = wifi_bands[j].start; 1375 end = wifi_bands[i].end = wifi_bands[j].end; 1376 wifi_bands[j].start = 0; 1377 wifi_bands[j].end = 0; 1378 num_of_wbrf_ranges = j; 1379 } 1380 1381 /* eliminate duplicate entries */ 1382 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1383 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1384 wifi_bands[j].start = 0; 1385 wifi_bands[j].end = 0; 1386 } 1387 } 1388 } 1389 1390 /* Send the sorted wifi_bands to PMFW */ 1391 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1392 /* Try to set the wifi_bands again */ 1393 if (unlikely(ret == -EBUSY)) { 1394 mdelay(5); 1395 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1396 } 1397 1398 return ret; 1399 } 1400 1401 /** 1402 * smu_wbrf_event_handler - handle notify events 1403 * 1404 * @nb: notifier block 1405 * @action: event type 1406 * @_arg: event data 1407 * 1408 * Calls relevant amdgpu function in response to wbrf event 1409 * notification from kernel. 1410 */ 1411 static int smu_wbrf_event_handler(struct notifier_block *nb, 1412 unsigned long action, void *_arg) 1413 { 1414 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1415 1416 switch (action) { 1417 case WBRF_CHANGED: 1418 schedule_delayed_work(&smu->wbrf_delayed_work, 1419 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1420 break; 1421 default: 1422 return NOTIFY_DONE; 1423 } 1424 1425 return NOTIFY_OK; 1426 } 1427 1428 /** 1429 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1430 * 1431 * @work: struct work_struct pointer 1432 * 1433 * Flood is over and driver will consume the latest exclusion ranges. 1434 */ 1435 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1436 { 1437 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1438 1439 smu_wbrf_handle_exclusion_ranges(smu); 1440 } 1441 1442 /** 1443 * smu_wbrf_support_check - check wbrf support 1444 * 1445 * @smu: smu_context pointer 1446 * 1447 * Verifies the ACPI interface whether wbrf is supported. 1448 */ 1449 static void smu_wbrf_support_check(struct smu_context *smu) 1450 { 1451 struct amdgpu_device *adev = smu->adev; 1452 1453 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1454 acpi_amd_wbrf_supported_consumer(adev->dev); 1455 1456 if (smu->wbrf_supported) 1457 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1458 } 1459 1460 /** 1461 * smu_wbrf_init - init driver wbrf support 1462 * 1463 * @smu: smu_context pointer 1464 * 1465 * Verifies the AMD ACPI interfaces and registers with the wbrf 1466 * notifier chain if wbrf feature is supported. 1467 * Returns 0 on success, error on failure. 1468 */ 1469 static int smu_wbrf_init(struct smu_context *smu) 1470 { 1471 int ret; 1472 1473 if (!smu->wbrf_supported) 1474 return 0; 1475 1476 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1477 1478 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1479 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1480 if (ret) 1481 return ret; 1482 1483 /* 1484 * Some wifiband exclusion ranges may be already there 1485 * before our driver loaded. To make sure our driver 1486 * is awared of those exclusion ranges. 1487 */ 1488 schedule_delayed_work(&smu->wbrf_delayed_work, 1489 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1490 1491 return 0; 1492 } 1493 1494 /** 1495 * smu_wbrf_fini - tear down driver wbrf support 1496 * 1497 * @smu: smu_context pointer 1498 * 1499 * Unregisters with the wbrf notifier chain. 1500 */ 1501 static void smu_wbrf_fini(struct smu_context *smu) 1502 { 1503 if (!smu->wbrf_supported) 1504 return; 1505 1506 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1507 1508 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1509 } 1510 1511 static int smu_smc_hw_setup(struct smu_context *smu) 1512 { 1513 struct smu_feature *feature = &smu->smu_feature; 1514 struct amdgpu_device *adev = smu->adev; 1515 uint8_t pcie_gen = 0, pcie_width = 0; 1516 uint64_t features_supported; 1517 int ret = 0; 1518 1519 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1520 case IP_VERSION(11, 0, 7): 1521 case IP_VERSION(11, 0, 11): 1522 case IP_VERSION(11, 5, 0): 1523 case IP_VERSION(11, 0, 12): 1524 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1525 dev_info(adev->dev, "dpm has been enabled\n"); 1526 ret = smu_system_features_control(smu, true); 1527 if (ret) 1528 dev_err(adev->dev, "Failed system features control!\n"); 1529 return ret; 1530 } 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 ret = smu_init_display_count(smu, 0); 1537 if (ret) { 1538 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1539 return ret; 1540 } 1541 1542 ret = smu_set_driver_table_location(smu); 1543 if (ret) { 1544 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1545 return ret; 1546 } 1547 1548 /* 1549 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1550 */ 1551 ret = smu_set_tool_table_location(smu); 1552 if (ret) { 1553 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1554 return ret; 1555 } 1556 1557 /* 1558 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1559 * pool location. 1560 */ 1561 ret = smu_notify_memory_pool_location(smu); 1562 if (ret) { 1563 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1564 return ret; 1565 } 1566 1567 /* 1568 * It is assumed the pptable used before runpm is same as 1569 * the one used afterwards. Thus, we can reuse the stored 1570 * copy and do not need to resetup the pptable again. 1571 */ 1572 if (!adev->in_runpm) { 1573 ret = smu_setup_pptable(smu); 1574 if (ret) { 1575 dev_err(adev->dev, "Failed to setup pptable!\n"); 1576 return ret; 1577 } 1578 } 1579 1580 /* smu_dump_pptable(smu); */ 1581 1582 /* 1583 * With SCPM enabled, PSP is responsible for the PPTable transferring 1584 * (to SMU). Driver involvement is not needed and permitted. 1585 */ 1586 if (!adev->scpm_enabled) { 1587 /* 1588 * Copy pptable bo in the vram to smc with SMU MSGs such as 1589 * SetDriverDramAddr and TransferTableDram2Smu. 1590 */ 1591 ret = smu_write_pptable(smu); 1592 if (ret) { 1593 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1594 return ret; 1595 } 1596 } 1597 1598 /* issue Run*Btc msg */ 1599 ret = smu_run_btc(smu); 1600 if (ret) 1601 return ret; 1602 1603 /* Enable UclkShadow on wbrf supported */ 1604 if (smu->wbrf_supported) { 1605 ret = smu_enable_uclk_shadow(smu, true); 1606 if (ret) { 1607 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1608 return ret; 1609 } 1610 } 1611 1612 /* 1613 * With SCPM enabled, these actions(and relevant messages) are 1614 * not needed and permitted. 1615 */ 1616 if (!adev->scpm_enabled) { 1617 ret = smu_feature_set_allowed_mask(smu); 1618 if (ret) { 1619 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1620 return ret; 1621 } 1622 } 1623 1624 ret = smu_system_features_control(smu, true); 1625 if (ret) { 1626 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1627 return ret; 1628 } 1629 1630 smu_init_xgmi_plpd_mode(smu); 1631 1632 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1633 if (ret) { 1634 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1635 return ret; 1636 } 1637 bitmap_copy(feature->supported, 1638 (unsigned long *)&features_supported, 1639 feature->feature_num); 1640 1641 if (!smu_is_dpm_running(smu)) 1642 dev_info(adev->dev, "dpm has been disabled\n"); 1643 1644 /* 1645 * Set initialized values (get from vbios) to dpm tables context such as 1646 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1647 * type of clks. 1648 */ 1649 ret = smu_set_default_dpm_table(smu); 1650 if (ret) { 1651 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1652 return ret; 1653 } 1654 1655 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1656 pcie_gen = 3; 1657 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1658 pcie_gen = 2; 1659 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1660 pcie_gen = 1; 1661 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1662 pcie_gen = 0; 1663 1664 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1665 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1666 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1667 */ 1668 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1669 pcie_width = 6; 1670 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1671 pcie_width = 5; 1672 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1673 pcie_width = 4; 1674 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1675 pcie_width = 3; 1676 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1677 pcie_width = 2; 1678 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1679 pcie_width = 1; 1680 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1681 if (ret) { 1682 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1683 return ret; 1684 } 1685 1686 ret = smu_get_thermal_temperature_range(smu); 1687 if (ret) { 1688 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1689 return ret; 1690 } 1691 1692 ret = smu_enable_thermal_alert(smu); 1693 if (ret) { 1694 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1695 return ret; 1696 } 1697 1698 ret = smu_notify_display_change(smu); 1699 if (ret) { 1700 dev_err(adev->dev, "Failed to notify display change!\n"); 1701 return ret; 1702 } 1703 1704 /* 1705 * Set min deep sleep dce fclk with bootup value from vbios via 1706 * SetMinDeepSleepDcefclk MSG. 1707 */ 1708 ret = smu_set_min_dcef_deep_sleep(smu, 1709 smu->smu_table.boot_values.dcefclk / 100); 1710 if (ret) { 1711 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1712 return ret; 1713 } 1714 1715 /* Init wbrf support. Properly setup the notifier */ 1716 ret = smu_wbrf_init(smu); 1717 if (ret) 1718 dev_err(adev->dev, "Error during wbrf init call\n"); 1719 1720 return ret; 1721 } 1722 1723 static int smu_start_smc_engine(struct smu_context *smu) 1724 { 1725 struct amdgpu_device *adev = smu->adev; 1726 int ret = 0; 1727 1728 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1729 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1730 if (smu->ppt_funcs->load_microcode) { 1731 ret = smu->ppt_funcs->load_microcode(smu); 1732 if (ret) 1733 return ret; 1734 } 1735 } 1736 } 1737 1738 if (smu->ppt_funcs->check_fw_status) { 1739 ret = smu->ppt_funcs->check_fw_status(smu); 1740 if (ret) { 1741 dev_err(adev->dev, "SMC is not ready\n"); 1742 return ret; 1743 } 1744 } 1745 1746 /* 1747 * Send msg GetDriverIfVersion to check if the return value is equal 1748 * with DRIVER_IF_VERSION of smc header. 1749 */ 1750 ret = smu_check_fw_version(smu); 1751 if (ret) 1752 return ret; 1753 1754 return ret; 1755 } 1756 1757 static int smu_hw_init(void *handle) 1758 { 1759 int ret; 1760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1761 struct smu_context *smu = adev->powerplay.pp_handle; 1762 1763 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1764 smu->pm_enabled = false; 1765 return 0; 1766 } 1767 1768 ret = smu_start_smc_engine(smu); 1769 if (ret) { 1770 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1771 return ret; 1772 } 1773 1774 /* 1775 * Check whether wbrf is supported. This needs to be done 1776 * before SMU setup starts since part of SMU configuration 1777 * relies on this. 1778 */ 1779 smu_wbrf_support_check(smu); 1780 1781 if (smu->is_apu) { 1782 ret = smu_set_gfx_imu_enable(smu); 1783 if (ret) 1784 return ret; 1785 smu_dpm_set_vcn_enable(smu, true); 1786 smu_dpm_set_jpeg_enable(smu, true); 1787 smu_dpm_set_vpe_enable(smu, true); 1788 smu_dpm_set_umsch_mm_enable(smu, true); 1789 smu_set_gfx_cgpg(smu, true); 1790 } 1791 1792 if (!smu->pm_enabled) 1793 return 0; 1794 1795 ret = smu_get_driver_allowed_feature_mask(smu); 1796 if (ret) 1797 return ret; 1798 1799 ret = smu_smc_hw_setup(smu); 1800 if (ret) { 1801 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1802 return ret; 1803 } 1804 1805 /* 1806 * Move maximum sustainable clock retrieving here considering 1807 * 1. It is not needed on resume(from S3). 1808 * 2. DAL settings come between .hw_init and .late_init of SMU. 1809 * And DAL needs to know the maximum sustainable clocks. Thus 1810 * it cannot be put in .late_init(). 1811 */ 1812 ret = smu_init_max_sustainable_clocks(smu); 1813 if (ret) { 1814 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1815 return ret; 1816 } 1817 1818 adev->pm.dpm_enabled = true; 1819 1820 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1821 1822 return 0; 1823 } 1824 1825 static int smu_disable_dpms(struct smu_context *smu) 1826 { 1827 struct amdgpu_device *adev = smu->adev; 1828 int ret = 0; 1829 bool use_baco = !smu->is_apu && 1830 ((amdgpu_in_reset(adev) && 1831 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1832 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1833 1834 /* 1835 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1836 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1837 */ 1838 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1839 case IP_VERSION(13, 0, 0): 1840 case IP_VERSION(13, 0, 7): 1841 case IP_VERSION(13, 0, 10): 1842 return 0; 1843 default: 1844 break; 1845 } 1846 1847 /* 1848 * For custom pptable uploading, skip the DPM features 1849 * disable process on Navi1x ASICs. 1850 * - As the gfx related features are under control of 1851 * RLC on those ASICs. RLC reinitialization will be 1852 * needed to reenable them. That will cost much more 1853 * efforts. 1854 * 1855 * - SMU firmware can handle the DPM reenablement 1856 * properly. 1857 */ 1858 if (smu->uploading_custom_pp_table) { 1859 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1860 case IP_VERSION(11, 0, 0): 1861 case IP_VERSION(11, 0, 5): 1862 case IP_VERSION(11, 0, 9): 1863 case IP_VERSION(11, 0, 7): 1864 case IP_VERSION(11, 0, 11): 1865 case IP_VERSION(11, 5, 0): 1866 case IP_VERSION(11, 0, 12): 1867 case IP_VERSION(11, 0, 13): 1868 return 0; 1869 default: 1870 break; 1871 } 1872 } 1873 1874 /* 1875 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1876 * on BACO in. Driver involvement is unnecessary. 1877 */ 1878 if (use_baco) { 1879 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1880 case IP_VERSION(11, 0, 7): 1881 case IP_VERSION(11, 0, 0): 1882 case IP_VERSION(11, 0, 5): 1883 case IP_VERSION(11, 0, 9): 1884 case IP_VERSION(13, 0, 7): 1885 return 0; 1886 default: 1887 break; 1888 } 1889 } 1890 1891 /* 1892 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1893 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1894 */ 1895 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1896 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1897 case IP_VERSION(13, 0, 4): 1898 case IP_VERSION(13, 0, 11): 1899 case IP_VERSION(14, 0, 0): 1900 case IP_VERSION(14, 0, 1): 1901 return 0; 1902 default: 1903 break; 1904 } 1905 } 1906 1907 /* 1908 * For gpu reset, runpm and hibernation through BACO, 1909 * BACO feature has to be kept enabled. 1910 */ 1911 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1912 ret = smu_disable_all_features_with_exception(smu, 1913 SMU_FEATURE_BACO_BIT); 1914 if (ret) 1915 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1916 } else { 1917 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1918 if (!adev->scpm_enabled) { 1919 ret = smu_system_features_control(smu, false); 1920 if (ret) 1921 dev_err(adev->dev, "Failed to disable smu features.\n"); 1922 } 1923 } 1924 1925 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1926 * otherwise SMU will hang while interacting with RLC if RLC is halted 1927 * this is a WA for Vangogh asic which fix the SMU hang issue. 1928 */ 1929 ret = smu_notify_rlc_state(smu, false); 1930 if (ret) { 1931 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1932 return ret; 1933 } 1934 1935 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1936 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1937 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1938 adev->gfx.rlc.funcs->stop(adev); 1939 1940 return ret; 1941 } 1942 1943 static int smu_smc_hw_cleanup(struct smu_context *smu) 1944 { 1945 struct amdgpu_device *adev = smu->adev; 1946 int ret = 0; 1947 1948 smu_wbrf_fini(smu); 1949 1950 cancel_work_sync(&smu->throttling_logging_work); 1951 cancel_work_sync(&smu->interrupt_work); 1952 1953 ret = smu_disable_thermal_alert(smu); 1954 if (ret) { 1955 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1956 return ret; 1957 } 1958 1959 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1960 1961 ret = smu_disable_dpms(smu); 1962 if (ret) { 1963 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1964 return ret; 1965 } 1966 1967 return 0; 1968 } 1969 1970 static int smu_reset_mp1_state(struct smu_context *smu) 1971 { 1972 struct amdgpu_device *adev = smu->adev; 1973 int ret = 0; 1974 1975 if ((!adev->in_runpm) && (!adev->in_suspend) && 1976 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 1977 IP_VERSION(13, 0, 10) && 1978 !amdgpu_device_has_display_hardware(adev)) 1979 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 1980 1981 return ret; 1982 } 1983 1984 static int smu_hw_fini(void *handle) 1985 { 1986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1987 struct smu_context *smu = adev->powerplay.pp_handle; 1988 int ret; 1989 1990 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1991 return 0; 1992 1993 smu_dpm_set_vcn_enable(smu, false); 1994 smu_dpm_set_jpeg_enable(smu, false); 1995 smu_dpm_set_vpe_enable(smu, false); 1996 smu_dpm_set_umsch_mm_enable(smu, false); 1997 1998 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1999 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2000 2001 if (!smu->pm_enabled) 2002 return 0; 2003 2004 adev->pm.dpm_enabled = false; 2005 2006 ret = smu_smc_hw_cleanup(smu); 2007 if (ret) 2008 return ret; 2009 2010 ret = smu_reset_mp1_state(smu); 2011 if (ret) 2012 return ret; 2013 2014 return 0; 2015 } 2016 2017 static void smu_late_fini(void *handle) 2018 { 2019 struct amdgpu_device *adev = handle; 2020 struct smu_context *smu = adev->powerplay.pp_handle; 2021 2022 kfree(smu); 2023 } 2024 2025 static int smu_reset(struct smu_context *smu) 2026 { 2027 struct amdgpu_device *adev = smu->adev; 2028 int ret; 2029 2030 ret = smu_hw_fini(adev); 2031 if (ret) 2032 return ret; 2033 2034 ret = smu_hw_init(adev); 2035 if (ret) 2036 return ret; 2037 2038 ret = smu_late_init(adev); 2039 if (ret) 2040 return ret; 2041 2042 return 0; 2043 } 2044 2045 static int smu_suspend(void *handle) 2046 { 2047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2048 struct smu_context *smu = adev->powerplay.pp_handle; 2049 int ret; 2050 uint64_t count; 2051 2052 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2053 return 0; 2054 2055 if (!smu->pm_enabled) 2056 return 0; 2057 2058 adev->pm.dpm_enabled = false; 2059 2060 ret = smu_smc_hw_cleanup(smu); 2061 if (ret) 2062 return ret; 2063 2064 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2065 2066 smu_set_gfx_cgpg(smu, false); 2067 2068 /* 2069 * pwfw resets entrycount when device is suspended, so we save the 2070 * last value to be used when we resume to keep it consistent 2071 */ 2072 ret = smu_get_entrycount_gfxoff(smu, &count); 2073 if (!ret) 2074 adev->gfx.gfx_off_entrycount = count; 2075 2076 return 0; 2077 } 2078 2079 static int smu_resume(void *handle) 2080 { 2081 int ret; 2082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2083 struct smu_context *smu = adev->powerplay.pp_handle; 2084 2085 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2086 return 0; 2087 2088 if (!smu->pm_enabled) 2089 return 0; 2090 2091 dev_info(adev->dev, "SMU is resuming...\n"); 2092 2093 ret = smu_start_smc_engine(smu); 2094 if (ret) { 2095 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2096 return ret; 2097 } 2098 2099 ret = smu_smc_hw_setup(smu); 2100 if (ret) { 2101 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2102 return ret; 2103 } 2104 2105 ret = smu_set_gfx_imu_enable(smu); 2106 if (ret) 2107 return ret; 2108 2109 smu_set_gfx_cgpg(smu, true); 2110 2111 smu->disable_uclk_switch = 0; 2112 2113 adev->pm.dpm_enabled = true; 2114 2115 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2116 2117 return 0; 2118 } 2119 2120 static int smu_display_configuration_change(void *handle, 2121 const struct amd_pp_display_configuration *display_config) 2122 { 2123 struct smu_context *smu = handle; 2124 2125 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2126 return -EOPNOTSUPP; 2127 2128 if (!display_config) 2129 return -EINVAL; 2130 2131 smu_set_min_dcef_deep_sleep(smu, 2132 display_config->min_dcef_deep_sleep_set_clk / 100); 2133 2134 return 0; 2135 } 2136 2137 static int smu_set_clockgating_state(void *handle, 2138 enum amd_clockgating_state state) 2139 { 2140 return 0; 2141 } 2142 2143 static int smu_set_powergating_state(void *handle, 2144 enum amd_powergating_state state) 2145 { 2146 return 0; 2147 } 2148 2149 static int smu_enable_umd_pstate(void *handle, 2150 enum amd_dpm_forced_level *level) 2151 { 2152 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2153 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2154 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2155 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2156 2157 struct smu_context *smu = (struct smu_context*)(handle); 2158 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2159 2160 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2161 return -EINVAL; 2162 2163 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2164 /* enter umd pstate, save current level, disable gfx cg*/ 2165 if (*level & profile_mode_mask) { 2166 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2167 smu_gpo_control(smu, false); 2168 smu_gfx_ulv_control(smu, false); 2169 smu_deep_sleep_control(smu, false); 2170 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2171 } 2172 } else { 2173 /* exit umd pstate, restore level, enable gfx cg*/ 2174 if (!(*level & profile_mode_mask)) { 2175 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2176 *level = smu_dpm_ctx->saved_dpm_level; 2177 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2178 smu_deep_sleep_control(smu, true); 2179 smu_gfx_ulv_control(smu, true); 2180 smu_gpo_control(smu, true); 2181 } 2182 } 2183 2184 return 0; 2185 } 2186 2187 static int smu_bump_power_profile_mode(struct smu_context *smu, 2188 long *param, 2189 uint32_t param_size) 2190 { 2191 int ret = 0; 2192 2193 if (smu->ppt_funcs->set_power_profile_mode) 2194 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2195 2196 return ret; 2197 } 2198 2199 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2200 enum amd_dpm_forced_level level, 2201 bool skip_display_settings) 2202 { 2203 int ret = 0; 2204 int index = 0; 2205 long workload; 2206 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2207 2208 if (!skip_display_settings) { 2209 ret = smu_display_config_changed(smu); 2210 if (ret) { 2211 dev_err(smu->adev->dev, "Failed to change display config!"); 2212 return ret; 2213 } 2214 } 2215 2216 ret = smu_apply_clocks_adjust_rules(smu); 2217 if (ret) { 2218 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2219 return ret; 2220 } 2221 2222 if (!skip_display_settings) { 2223 ret = smu_notify_smc_display_config(smu); 2224 if (ret) { 2225 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2226 return ret; 2227 } 2228 } 2229 2230 if (smu_dpm_ctx->dpm_level != level) { 2231 ret = smu_asic_set_performance_level(smu, level); 2232 if (ret) { 2233 dev_err(smu->adev->dev, "Failed to set performance level!"); 2234 return ret; 2235 } 2236 2237 /* update the saved copy */ 2238 smu_dpm_ctx->dpm_level = level; 2239 } 2240 2241 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2242 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2243 index = fls(smu->workload_mask); 2244 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2245 workload = smu->workload_setting[index]; 2246 2247 if (smu->power_profile_mode != workload) 2248 smu_bump_power_profile_mode(smu, &workload, 0); 2249 } 2250 2251 return ret; 2252 } 2253 2254 static int smu_handle_task(struct smu_context *smu, 2255 enum amd_dpm_forced_level level, 2256 enum amd_pp_task task_id) 2257 { 2258 int ret = 0; 2259 2260 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2261 return -EOPNOTSUPP; 2262 2263 switch (task_id) { 2264 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2265 ret = smu_pre_display_config_changed(smu); 2266 if (ret) 2267 return ret; 2268 ret = smu_adjust_power_state_dynamic(smu, level, false); 2269 break; 2270 case AMD_PP_TASK_COMPLETE_INIT: 2271 case AMD_PP_TASK_READJUST_POWER_STATE: 2272 ret = smu_adjust_power_state_dynamic(smu, level, true); 2273 break; 2274 default: 2275 break; 2276 } 2277 2278 return ret; 2279 } 2280 2281 static int smu_handle_dpm_task(void *handle, 2282 enum amd_pp_task task_id, 2283 enum amd_pm_state_type *user_state) 2284 { 2285 struct smu_context *smu = handle; 2286 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2287 2288 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2289 2290 } 2291 2292 static int smu_switch_power_profile(void *handle, 2293 enum PP_SMC_POWER_PROFILE type, 2294 bool en) 2295 { 2296 struct smu_context *smu = handle; 2297 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2298 long workload; 2299 uint32_t index; 2300 2301 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2302 return -EOPNOTSUPP; 2303 2304 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2305 return -EINVAL; 2306 2307 if (!en) { 2308 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2309 index = fls(smu->workload_mask); 2310 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2311 workload = smu->workload_setting[index]; 2312 } else { 2313 smu->workload_mask |= (1 << smu->workload_prority[type]); 2314 index = fls(smu->workload_mask); 2315 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2316 workload = smu->workload_setting[index]; 2317 } 2318 2319 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2320 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2321 smu_bump_power_profile_mode(smu, &workload, 0); 2322 2323 return 0; 2324 } 2325 2326 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2327 { 2328 struct smu_context *smu = handle; 2329 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2330 2331 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2332 return -EOPNOTSUPP; 2333 2334 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2335 return -EINVAL; 2336 2337 return smu_dpm_ctx->dpm_level; 2338 } 2339 2340 static int smu_force_performance_level(void *handle, 2341 enum amd_dpm_forced_level level) 2342 { 2343 struct smu_context *smu = handle; 2344 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2345 int ret = 0; 2346 2347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2348 return -EOPNOTSUPP; 2349 2350 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2351 return -EINVAL; 2352 2353 ret = smu_enable_umd_pstate(smu, &level); 2354 if (ret) 2355 return ret; 2356 2357 ret = smu_handle_task(smu, level, 2358 AMD_PP_TASK_READJUST_POWER_STATE); 2359 2360 /* reset user dpm clock state */ 2361 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2362 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2363 smu->user_dpm_profile.clk_dependency = 0; 2364 } 2365 2366 return ret; 2367 } 2368 2369 static int smu_set_display_count(void *handle, uint32_t count) 2370 { 2371 struct smu_context *smu = handle; 2372 2373 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2374 return -EOPNOTSUPP; 2375 2376 return smu_init_display_count(smu, count); 2377 } 2378 2379 static int smu_force_smuclk_levels(struct smu_context *smu, 2380 enum smu_clk_type clk_type, 2381 uint32_t mask) 2382 { 2383 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2384 int ret = 0; 2385 2386 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2387 return -EOPNOTSUPP; 2388 2389 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2390 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2391 return -EINVAL; 2392 } 2393 2394 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2395 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2396 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2397 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2398 smu_set_user_clk_dependencies(smu, clk_type); 2399 } 2400 } 2401 2402 return ret; 2403 } 2404 2405 static int smu_force_ppclk_levels(void *handle, 2406 enum pp_clock_type type, 2407 uint32_t mask) 2408 { 2409 struct smu_context *smu = handle; 2410 enum smu_clk_type clk_type; 2411 2412 switch (type) { 2413 case PP_SCLK: 2414 clk_type = SMU_SCLK; break; 2415 case PP_MCLK: 2416 clk_type = SMU_MCLK; break; 2417 case PP_PCIE: 2418 clk_type = SMU_PCIE; break; 2419 case PP_SOCCLK: 2420 clk_type = SMU_SOCCLK; break; 2421 case PP_FCLK: 2422 clk_type = SMU_FCLK; break; 2423 case PP_DCEFCLK: 2424 clk_type = SMU_DCEFCLK; break; 2425 case PP_VCLK: 2426 clk_type = SMU_VCLK; break; 2427 case PP_VCLK1: 2428 clk_type = SMU_VCLK1; break; 2429 case PP_DCLK: 2430 clk_type = SMU_DCLK; break; 2431 case PP_DCLK1: 2432 clk_type = SMU_DCLK1; break; 2433 case OD_SCLK: 2434 clk_type = SMU_OD_SCLK; break; 2435 case OD_MCLK: 2436 clk_type = SMU_OD_MCLK; break; 2437 case OD_VDDC_CURVE: 2438 clk_type = SMU_OD_VDDC_CURVE; break; 2439 case OD_RANGE: 2440 clk_type = SMU_OD_RANGE; break; 2441 default: 2442 return -EINVAL; 2443 } 2444 2445 return smu_force_smuclk_levels(smu, clk_type, mask); 2446 } 2447 2448 /* 2449 * On system suspending or resetting, the dpm_enabled 2450 * flag will be cleared. So that those SMU services which 2451 * are not supported will be gated. 2452 * However, the mp1 state setting should still be granted 2453 * even if the dpm_enabled cleared. 2454 */ 2455 static int smu_set_mp1_state(void *handle, 2456 enum pp_mp1_state mp1_state) 2457 { 2458 struct smu_context *smu = handle; 2459 int ret = 0; 2460 2461 if (!smu->pm_enabled) 2462 return -EOPNOTSUPP; 2463 2464 if (smu->ppt_funcs && 2465 smu->ppt_funcs->set_mp1_state) 2466 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2467 2468 return ret; 2469 } 2470 2471 static int smu_set_df_cstate(void *handle, 2472 enum pp_df_cstate state) 2473 { 2474 struct smu_context *smu = handle; 2475 int ret = 0; 2476 2477 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2478 return -EOPNOTSUPP; 2479 2480 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2481 return 0; 2482 2483 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2484 if (ret) 2485 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2486 2487 return ret; 2488 } 2489 2490 int smu_write_watermarks_table(struct smu_context *smu) 2491 { 2492 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2493 return -EOPNOTSUPP; 2494 2495 return smu_set_watermarks_table(smu, NULL); 2496 } 2497 2498 static int smu_set_watermarks_for_clock_ranges(void *handle, 2499 struct pp_smu_wm_range_sets *clock_ranges) 2500 { 2501 struct smu_context *smu = handle; 2502 2503 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2504 return -EOPNOTSUPP; 2505 2506 if (smu->disable_watermark) 2507 return 0; 2508 2509 return smu_set_watermarks_table(smu, clock_ranges); 2510 } 2511 2512 int smu_set_ac_dc(struct smu_context *smu) 2513 { 2514 int ret = 0; 2515 2516 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2517 return -EOPNOTSUPP; 2518 2519 /* controlled by firmware */ 2520 if (smu->dc_controlled_by_gpio) 2521 return 0; 2522 2523 ret = smu_set_power_source(smu, 2524 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2525 SMU_POWER_SOURCE_DC); 2526 if (ret) 2527 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2528 smu->adev->pm.ac_power ? "AC" : "DC"); 2529 2530 return ret; 2531 } 2532 2533 const struct amd_ip_funcs smu_ip_funcs = { 2534 .name = "smu", 2535 .early_init = smu_early_init, 2536 .late_init = smu_late_init, 2537 .sw_init = smu_sw_init, 2538 .sw_fini = smu_sw_fini, 2539 .hw_init = smu_hw_init, 2540 .hw_fini = smu_hw_fini, 2541 .late_fini = smu_late_fini, 2542 .suspend = smu_suspend, 2543 .resume = smu_resume, 2544 .is_idle = NULL, 2545 .check_soft_reset = NULL, 2546 .wait_for_idle = NULL, 2547 .soft_reset = NULL, 2548 .set_clockgating_state = smu_set_clockgating_state, 2549 .set_powergating_state = smu_set_powergating_state, 2550 }; 2551 2552 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2553 .type = AMD_IP_BLOCK_TYPE_SMC, 2554 .major = 11, 2555 .minor = 0, 2556 .rev = 0, 2557 .funcs = &smu_ip_funcs, 2558 }; 2559 2560 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2561 .type = AMD_IP_BLOCK_TYPE_SMC, 2562 .major = 12, 2563 .minor = 0, 2564 .rev = 0, 2565 .funcs = &smu_ip_funcs, 2566 }; 2567 2568 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2569 .type = AMD_IP_BLOCK_TYPE_SMC, 2570 .major = 13, 2571 .minor = 0, 2572 .rev = 0, 2573 .funcs = &smu_ip_funcs, 2574 }; 2575 2576 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2577 .type = AMD_IP_BLOCK_TYPE_SMC, 2578 .major = 14, 2579 .minor = 0, 2580 .rev = 0, 2581 .funcs = &smu_ip_funcs, 2582 }; 2583 2584 static int smu_load_microcode(void *handle) 2585 { 2586 struct smu_context *smu = handle; 2587 struct amdgpu_device *adev = smu->adev; 2588 int ret = 0; 2589 2590 if (!smu->pm_enabled) 2591 return -EOPNOTSUPP; 2592 2593 /* This should be used for non PSP loading */ 2594 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2595 return 0; 2596 2597 if (smu->ppt_funcs->load_microcode) { 2598 ret = smu->ppt_funcs->load_microcode(smu); 2599 if (ret) { 2600 dev_err(adev->dev, "Load microcode failed\n"); 2601 return ret; 2602 } 2603 } 2604 2605 if (smu->ppt_funcs->check_fw_status) { 2606 ret = smu->ppt_funcs->check_fw_status(smu); 2607 if (ret) { 2608 dev_err(adev->dev, "SMC is not ready\n"); 2609 return ret; 2610 } 2611 } 2612 2613 return ret; 2614 } 2615 2616 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2617 { 2618 int ret = 0; 2619 2620 if (smu->ppt_funcs->set_gfx_cgpg) 2621 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2622 2623 return ret; 2624 } 2625 2626 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2627 { 2628 struct smu_context *smu = handle; 2629 int ret = 0; 2630 2631 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2632 return -EOPNOTSUPP; 2633 2634 if (!smu->ppt_funcs->set_fan_speed_rpm) 2635 return -EOPNOTSUPP; 2636 2637 if (speed == U32_MAX) 2638 return -EINVAL; 2639 2640 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2641 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2642 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2643 smu->user_dpm_profile.fan_speed_rpm = speed; 2644 2645 /* Override custom PWM setting as they cannot co-exist */ 2646 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2647 smu->user_dpm_profile.fan_speed_pwm = 0; 2648 } 2649 2650 return ret; 2651 } 2652 2653 /** 2654 * smu_get_power_limit - Request one of the SMU Power Limits 2655 * 2656 * @handle: pointer to smu context 2657 * @limit: requested limit is written back to this variable 2658 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2659 * @pp_power_type: &pp_power_type type of power 2660 * Return: 0 on success, <0 on error 2661 * 2662 */ 2663 int smu_get_power_limit(void *handle, 2664 uint32_t *limit, 2665 enum pp_power_limit_level pp_limit_level, 2666 enum pp_power_type pp_power_type) 2667 { 2668 struct smu_context *smu = handle; 2669 struct amdgpu_device *adev = smu->adev; 2670 enum smu_ppt_limit_level limit_level; 2671 uint32_t limit_type; 2672 int ret = 0; 2673 2674 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2675 return -EOPNOTSUPP; 2676 2677 switch (pp_power_type) { 2678 case PP_PWR_TYPE_SUSTAINED: 2679 limit_type = SMU_DEFAULT_PPT_LIMIT; 2680 break; 2681 case PP_PWR_TYPE_FAST: 2682 limit_type = SMU_FAST_PPT_LIMIT; 2683 break; 2684 default: 2685 return -EOPNOTSUPP; 2686 } 2687 2688 switch (pp_limit_level) { 2689 case PP_PWR_LIMIT_CURRENT: 2690 limit_level = SMU_PPT_LIMIT_CURRENT; 2691 break; 2692 case PP_PWR_LIMIT_DEFAULT: 2693 limit_level = SMU_PPT_LIMIT_DEFAULT; 2694 break; 2695 case PP_PWR_LIMIT_MAX: 2696 limit_level = SMU_PPT_LIMIT_MAX; 2697 break; 2698 case PP_PWR_LIMIT_MIN: 2699 limit_level = SMU_PPT_LIMIT_MIN; 2700 break; 2701 default: 2702 return -EOPNOTSUPP; 2703 } 2704 2705 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2706 if (smu->ppt_funcs->get_ppt_limit) 2707 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2708 } else { 2709 switch (limit_level) { 2710 case SMU_PPT_LIMIT_CURRENT: 2711 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2712 case IP_VERSION(13, 0, 2): 2713 case IP_VERSION(13, 0, 6): 2714 case IP_VERSION(11, 0, 7): 2715 case IP_VERSION(11, 0, 11): 2716 case IP_VERSION(11, 0, 12): 2717 case IP_VERSION(11, 0, 13): 2718 ret = smu_get_asic_power_limits(smu, 2719 &smu->current_power_limit, 2720 NULL, NULL, NULL); 2721 break; 2722 default: 2723 break; 2724 } 2725 *limit = smu->current_power_limit; 2726 break; 2727 case SMU_PPT_LIMIT_DEFAULT: 2728 *limit = smu->default_power_limit; 2729 break; 2730 case SMU_PPT_LIMIT_MAX: 2731 *limit = smu->max_power_limit; 2732 break; 2733 case SMU_PPT_LIMIT_MIN: 2734 *limit = smu->min_power_limit; 2735 break; 2736 default: 2737 return -EINVAL; 2738 } 2739 } 2740 2741 return ret; 2742 } 2743 2744 static int smu_set_power_limit(void *handle, uint32_t limit) 2745 { 2746 struct smu_context *smu = handle; 2747 uint32_t limit_type = limit >> 24; 2748 int ret = 0; 2749 2750 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2751 return -EOPNOTSUPP; 2752 2753 limit &= (1<<24)-1; 2754 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2755 if (smu->ppt_funcs->set_power_limit) 2756 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2757 2758 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2759 dev_err(smu->adev->dev, 2760 "New power limit (%d) is out of range [%d,%d]\n", 2761 limit, smu->min_power_limit, smu->max_power_limit); 2762 return -EINVAL; 2763 } 2764 2765 if (!limit) 2766 limit = smu->current_power_limit; 2767 2768 if (smu->ppt_funcs->set_power_limit) { 2769 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2770 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2771 smu->user_dpm_profile.power_limit = limit; 2772 } 2773 2774 return ret; 2775 } 2776 2777 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2778 { 2779 int ret = 0; 2780 2781 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2782 return -EOPNOTSUPP; 2783 2784 if (smu->ppt_funcs->print_clk_levels) 2785 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2786 2787 return ret; 2788 } 2789 2790 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2791 { 2792 enum smu_clk_type clk_type; 2793 2794 switch (type) { 2795 case PP_SCLK: 2796 clk_type = SMU_SCLK; break; 2797 case PP_MCLK: 2798 clk_type = SMU_MCLK; break; 2799 case PP_PCIE: 2800 clk_type = SMU_PCIE; break; 2801 case PP_SOCCLK: 2802 clk_type = SMU_SOCCLK; break; 2803 case PP_FCLK: 2804 clk_type = SMU_FCLK; break; 2805 case PP_DCEFCLK: 2806 clk_type = SMU_DCEFCLK; break; 2807 case PP_VCLK: 2808 clk_type = SMU_VCLK; break; 2809 case PP_VCLK1: 2810 clk_type = SMU_VCLK1; break; 2811 case PP_DCLK: 2812 clk_type = SMU_DCLK; break; 2813 case PP_DCLK1: 2814 clk_type = SMU_DCLK1; break; 2815 case OD_SCLK: 2816 clk_type = SMU_OD_SCLK; break; 2817 case OD_MCLK: 2818 clk_type = SMU_OD_MCLK; break; 2819 case OD_VDDC_CURVE: 2820 clk_type = SMU_OD_VDDC_CURVE; break; 2821 case OD_RANGE: 2822 clk_type = SMU_OD_RANGE; break; 2823 case OD_VDDGFX_OFFSET: 2824 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2825 case OD_CCLK: 2826 clk_type = SMU_OD_CCLK; break; 2827 case OD_FAN_CURVE: 2828 clk_type = SMU_OD_FAN_CURVE; break; 2829 case OD_ACOUSTIC_LIMIT: 2830 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2831 case OD_ACOUSTIC_TARGET: 2832 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2833 case OD_FAN_TARGET_TEMPERATURE: 2834 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2835 case OD_FAN_MINIMUM_PWM: 2836 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2837 default: 2838 clk_type = SMU_CLK_COUNT; break; 2839 } 2840 2841 return clk_type; 2842 } 2843 2844 static int smu_print_ppclk_levels(void *handle, 2845 enum pp_clock_type type, 2846 char *buf) 2847 { 2848 struct smu_context *smu = handle; 2849 enum smu_clk_type clk_type; 2850 2851 clk_type = smu_convert_to_smuclk(type); 2852 if (clk_type == SMU_CLK_COUNT) 2853 return -EINVAL; 2854 2855 return smu_print_smuclk_levels(smu, clk_type, buf); 2856 } 2857 2858 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2859 { 2860 struct smu_context *smu = handle; 2861 enum smu_clk_type clk_type; 2862 2863 clk_type = smu_convert_to_smuclk(type); 2864 if (clk_type == SMU_CLK_COUNT) 2865 return -EINVAL; 2866 2867 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2868 return -EOPNOTSUPP; 2869 2870 if (!smu->ppt_funcs->emit_clk_levels) 2871 return -ENOENT; 2872 2873 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2874 2875 } 2876 2877 static int smu_od_edit_dpm_table(void *handle, 2878 enum PP_OD_DPM_TABLE_COMMAND type, 2879 long *input, uint32_t size) 2880 { 2881 struct smu_context *smu = handle; 2882 int ret = 0; 2883 2884 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2885 return -EOPNOTSUPP; 2886 2887 if (smu->ppt_funcs->od_edit_dpm_table) { 2888 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2889 } 2890 2891 return ret; 2892 } 2893 2894 static int smu_read_sensor(void *handle, 2895 int sensor, 2896 void *data, 2897 int *size_arg) 2898 { 2899 struct smu_context *smu = handle; 2900 struct smu_umd_pstate_table *pstate_table = 2901 &smu->pstate_table; 2902 int ret = 0; 2903 uint32_t *size, size_val; 2904 2905 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2906 return -EOPNOTSUPP; 2907 2908 if (!data || !size_arg) 2909 return -EINVAL; 2910 2911 size_val = *size_arg; 2912 size = &size_val; 2913 2914 if (smu->ppt_funcs->read_sensor) 2915 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2916 goto unlock; 2917 2918 switch (sensor) { 2919 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2920 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2921 *size = 4; 2922 break; 2923 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2924 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2925 *size = 4; 2926 break; 2927 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2928 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2929 *size = 4; 2930 break; 2931 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2932 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2933 *size = 4; 2934 break; 2935 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2936 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2937 *size = 8; 2938 break; 2939 case AMDGPU_PP_SENSOR_UVD_POWER: 2940 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2941 *size = 4; 2942 break; 2943 case AMDGPU_PP_SENSOR_VCE_POWER: 2944 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2945 *size = 4; 2946 break; 2947 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2948 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2949 *size = 4; 2950 break; 2951 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2952 *(uint32_t *)data = 0; 2953 *size = 4; 2954 break; 2955 default: 2956 *size = 0; 2957 ret = -EOPNOTSUPP; 2958 break; 2959 } 2960 2961 unlock: 2962 // assign uint32_t to int 2963 *size_arg = size_val; 2964 2965 return ret; 2966 } 2967 2968 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2969 { 2970 int ret = -EOPNOTSUPP; 2971 struct smu_context *smu = handle; 2972 2973 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2974 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2975 2976 return ret; 2977 } 2978 2979 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2980 { 2981 int ret = -EOPNOTSUPP; 2982 struct smu_context *smu = handle; 2983 2984 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2985 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2986 2987 return ret; 2988 } 2989 2990 static int smu_get_power_profile_mode(void *handle, char *buf) 2991 { 2992 struct smu_context *smu = handle; 2993 2994 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2995 !smu->ppt_funcs->get_power_profile_mode) 2996 return -EOPNOTSUPP; 2997 if (!buf) 2998 return -EINVAL; 2999 3000 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3001 } 3002 3003 static int smu_set_power_profile_mode(void *handle, 3004 long *param, 3005 uint32_t param_size) 3006 { 3007 struct smu_context *smu = handle; 3008 3009 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3010 !smu->ppt_funcs->set_power_profile_mode) 3011 return -EOPNOTSUPP; 3012 3013 return smu_bump_power_profile_mode(smu, param, param_size); 3014 } 3015 3016 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3017 { 3018 struct smu_context *smu = handle; 3019 3020 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3021 return -EOPNOTSUPP; 3022 3023 if (!smu->ppt_funcs->get_fan_control_mode) 3024 return -EOPNOTSUPP; 3025 3026 if (!fan_mode) 3027 return -EINVAL; 3028 3029 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3030 3031 return 0; 3032 } 3033 3034 static int smu_set_fan_control_mode(void *handle, u32 value) 3035 { 3036 struct smu_context *smu = handle; 3037 int ret = 0; 3038 3039 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3040 return -EOPNOTSUPP; 3041 3042 if (!smu->ppt_funcs->set_fan_control_mode) 3043 return -EOPNOTSUPP; 3044 3045 if (value == U32_MAX) 3046 return -EINVAL; 3047 3048 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3049 if (ret) 3050 goto out; 3051 3052 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3053 smu->user_dpm_profile.fan_mode = value; 3054 3055 /* reset user dpm fan speed */ 3056 if (value != AMD_FAN_CTRL_MANUAL) { 3057 smu->user_dpm_profile.fan_speed_pwm = 0; 3058 smu->user_dpm_profile.fan_speed_rpm = 0; 3059 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3060 } 3061 } 3062 3063 out: 3064 return ret; 3065 } 3066 3067 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3068 { 3069 struct smu_context *smu = handle; 3070 int ret = 0; 3071 3072 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3073 return -EOPNOTSUPP; 3074 3075 if (!smu->ppt_funcs->get_fan_speed_pwm) 3076 return -EOPNOTSUPP; 3077 3078 if (!speed) 3079 return -EINVAL; 3080 3081 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3082 3083 return ret; 3084 } 3085 3086 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3087 { 3088 struct smu_context *smu = handle; 3089 int ret = 0; 3090 3091 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3092 return -EOPNOTSUPP; 3093 3094 if (!smu->ppt_funcs->set_fan_speed_pwm) 3095 return -EOPNOTSUPP; 3096 3097 if (speed == U32_MAX) 3098 return -EINVAL; 3099 3100 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3101 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3102 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3103 smu->user_dpm_profile.fan_speed_pwm = speed; 3104 3105 /* Override custom RPM setting as they cannot co-exist */ 3106 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3107 smu->user_dpm_profile.fan_speed_rpm = 0; 3108 } 3109 3110 return ret; 3111 } 3112 3113 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3114 { 3115 struct smu_context *smu = handle; 3116 int ret = 0; 3117 3118 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3119 return -EOPNOTSUPP; 3120 3121 if (!smu->ppt_funcs->get_fan_speed_rpm) 3122 return -EOPNOTSUPP; 3123 3124 if (!speed) 3125 return -EINVAL; 3126 3127 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3128 3129 return ret; 3130 } 3131 3132 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3133 { 3134 struct smu_context *smu = handle; 3135 3136 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3137 return -EOPNOTSUPP; 3138 3139 return smu_set_min_dcef_deep_sleep(smu, clk); 3140 } 3141 3142 static int smu_get_clock_by_type_with_latency(void *handle, 3143 enum amd_pp_clock_type type, 3144 struct pp_clock_levels_with_latency *clocks) 3145 { 3146 struct smu_context *smu = handle; 3147 enum smu_clk_type clk_type; 3148 int ret = 0; 3149 3150 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3151 return -EOPNOTSUPP; 3152 3153 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3154 switch (type) { 3155 case amd_pp_sys_clock: 3156 clk_type = SMU_GFXCLK; 3157 break; 3158 case amd_pp_mem_clock: 3159 clk_type = SMU_MCLK; 3160 break; 3161 case amd_pp_dcef_clock: 3162 clk_type = SMU_DCEFCLK; 3163 break; 3164 case amd_pp_disp_clock: 3165 clk_type = SMU_DISPCLK; 3166 break; 3167 default: 3168 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3169 return -EINVAL; 3170 } 3171 3172 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3173 } 3174 3175 return ret; 3176 } 3177 3178 static int smu_display_clock_voltage_request(void *handle, 3179 struct pp_display_clock_request *clock_req) 3180 { 3181 struct smu_context *smu = handle; 3182 int ret = 0; 3183 3184 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3185 return -EOPNOTSUPP; 3186 3187 if (smu->ppt_funcs->display_clock_voltage_request) 3188 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3189 3190 return ret; 3191 } 3192 3193 3194 static int smu_display_disable_memory_clock_switch(void *handle, 3195 bool disable_memory_clock_switch) 3196 { 3197 struct smu_context *smu = handle; 3198 int ret = -EINVAL; 3199 3200 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3201 return -EOPNOTSUPP; 3202 3203 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3204 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3205 3206 return ret; 3207 } 3208 3209 static int smu_set_xgmi_pstate(void *handle, 3210 uint32_t pstate) 3211 { 3212 struct smu_context *smu = handle; 3213 int ret = 0; 3214 3215 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3216 return -EOPNOTSUPP; 3217 3218 if (smu->ppt_funcs->set_xgmi_pstate) 3219 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3220 3221 if (ret) 3222 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3223 3224 return ret; 3225 } 3226 3227 static int smu_get_baco_capability(void *handle) 3228 { 3229 struct smu_context *smu = handle; 3230 3231 if (!smu->pm_enabled) 3232 return false; 3233 3234 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3235 return false; 3236 3237 return smu->ppt_funcs->get_bamaco_support(smu); 3238 } 3239 3240 static int smu_baco_set_state(void *handle, int state) 3241 { 3242 struct smu_context *smu = handle; 3243 int ret = 0; 3244 3245 if (!smu->pm_enabled) 3246 return -EOPNOTSUPP; 3247 3248 if (state == 0) { 3249 if (smu->ppt_funcs->baco_exit) 3250 ret = smu->ppt_funcs->baco_exit(smu); 3251 } else if (state == 1) { 3252 if (smu->ppt_funcs->baco_enter) 3253 ret = smu->ppt_funcs->baco_enter(smu); 3254 } else { 3255 return -EINVAL; 3256 } 3257 3258 if (ret) 3259 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3260 (state)?"enter":"exit"); 3261 3262 return ret; 3263 } 3264 3265 bool smu_mode1_reset_is_support(struct smu_context *smu) 3266 { 3267 bool ret = false; 3268 3269 if (!smu->pm_enabled) 3270 return false; 3271 3272 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3273 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3274 3275 return ret; 3276 } 3277 3278 bool smu_mode2_reset_is_support(struct smu_context *smu) 3279 { 3280 bool ret = false; 3281 3282 if (!smu->pm_enabled) 3283 return false; 3284 3285 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3286 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3287 3288 return ret; 3289 } 3290 3291 int smu_mode1_reset(struct smu_context *smu) 3292 { 3293 int ret = 0; 3294 3295 if (!smu->pm_enabled) 3296 return -EOPNOTSUPP; 3297 3298 if (smu->ppt_funcs->mode1_reset) 3299 ret = smu->ppt_funcs->mode1_reset(smu); 3300 3301 return ret; 3302 } 3303 3304 static int smu_mode2_reset(void *handle) 3305 { 3306 struct smu_context *smu = handle; 3307 int ret = 0; 3308 3309 if (!smu->pm_enabled) 3310 return -EOPNOTSUPP; 3311 3312 if (smu->ppt_funcs->mode2_reset) 3313 ret = smu->ppt_funcs->mode2_reset(smu); 3314 3315 if (ret) 3316 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3317 3318 return ret; 3319 } 3320 3321 static int smu_enable_gfx_features(void *handle) 3322 { 3323 struct smu_context *smu = handle; 3324 int ret = 0; 3325 3326 if (!smu->pm_enabled) 3327 return -EOPNOTSUPP; 3328 3329 if (smu->ppt_funcs->enable_gfx_features) 3330 ret = smu->ppt_funcs->enable_gfx_features(smu); 3331 3332 if (ret) 3333 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3334 3335 return ret; 3336 } 3337 3338 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3339 struct pp_smu_nv_clock_table *max_clocks) 3340 { 3341 struct smu_context *smu = handle; 3342 int ret = 0; 3343 3344 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3345 return -EOPNOTSUPP; 3346 3347 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3348 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3349 3350 return ret; 3351 } 3352 3353 static int smu_get_uclk_dpm_states(void *handle, 3354 unsigned int *clock_values_in_khz, 3355 unsigned int *num_states) 3356 { 3357 struct smu_context *smu = handle; 3358 int ret = 0; 3359 3360 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3361 return -EOPNOTSUPP; 3362 3363 if (smu->ppt_funcs->get_uclk_dpm_states) 3364 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3365 3366 return ret; 3367 } 3368 3369 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3370 { 3371 struct smu_context *smu = handle; 3372 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3373 3374 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3375 return -EOPNOTSUPP; 3376 3377 if (smu->ppt_funcs->get_current_power_state) 3378 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3379 3380 return pm_state; 3381 } 3382 3383 static int smu_get_dpm_clock_table(void *handle, 3384 struct dpm_clocks *clock_table) 3385 { 3386 struct smu_context *smu = handle; 3387 int ret = 0; 3388 3389 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3390 return -EOPNOTSUPP; 3391 3392 if (smu->ppt_funcs->get_dpm_clock_table) 3393 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3394 3395 return ret; 3396 } 3397 3398 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3399 { 3400 struct smu_context *smu = handle; 3401 3402 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3403 return -EOPNOTSUPP; 3404 3405 if (!smu->ppt_funcs->get_gpu_metrics) 3406 return -EOPNOTSUPP; 3407 3408 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3409 } 3410 3411 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3412 size_t size) 3413 { 3414 struct smu_context *smu = handle; 3415 3416 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3417 return -EOPNOTSUPP; 3418 3419 if (!smu->ppt_funcs->get_pm_metrics) 3420 return -EOPNOTSUPP; 3421 3422 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3423 } 3424 3425 static int smu_enable_mgpu_fan_boost(void *handle) 3426 { 3427 struct smu_context *smu = handle; 3428 int ret = 0; 3429 3430 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3431 return -EOPNOTSUPP; 3432 3433 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3434 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3435 3436 return ret; 3437 } 3438 3439 static int smu_gfx_state_change_set(void *handle, 3440 uint32_t state) 3441 { 3442 struct smu_context *smu = handle; 3443 int ret = 0; 3444 3445 if (smu->ppt_funcs->gfx_state_change_set) 3446 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3447 3448 return ret; 3449 } 3450 3451 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3452 { 3453 int ret = 0; 3454 3455 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3456 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3457 3458 return ret; 3459 } 3460 3461 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3462 { 3463 int ret = -EOPNOTSUPP; 3464 3465 if (smu->ppt_funcs && 3466 smu->ppt_funcs->get_ecc_info) 3467 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3468 3469 return ret; 3470 3471 } 3472 3473 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3474 { 3475 struct smu_context *smu = handle; 3476 struct smu_table_context *smu_table = &smu->smu_table; 3477 struct smu_table *memory_pool = &smu_table->memory_pool; 3478 3479 if (!addr || !size) 3480 return -EINVAL; 3481 3482 *addr = NULL; 3483 *size = 0; 3484 if (memory_pool->bo) { 3485 *addr = memory_pool->cpu_addr; 3486 *size = memory_pool->size; 3487 } 3488 3489 return 0; 3490 } 3491 3492 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 3493 enum pp_xgmi_plpd_mode mode) 3494 { 3495 int ret = -EOPNOTSUPP; 3496 3497 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3498 return ret; 3499 3500 /* PLPD policy is not supported if it's NONE */ 3501 if (smu->plpd_mode == XGMI_PLPD_NONE) 3502 return ret; 3503 3504 if (smu->plpd_mode == mode) 3505 return 0; 3506 3507 if (smu->ppt_funcs && smu->ppt_funcs->select_xgmi_plpd_policy) 3508 ret = smu->ppt_funcs->select_xgmi_plpd_policy(smu, mode); 3509 3510 if (!ret) 3511 smu->plpd_mode = mode; 3512 3513 return ret; 3514 } 3515 3516 static const struct amd_pm_funcs swsmu_pm_funcs = { 3517 /* export for sysfs */ 3518 .set_fan_control_mode = smu_set_fan_control_mode, 3519 .get_fan_control_mode = smu_get_fan_control_mode, 3520 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3521 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3522 .force_clock_level = smu_force_ppclk_levels, 3523 .print_clock_levels = smu_print_ppclk_levels, 3524 .emit_clock_levels = smu_emit_ppclk_levels, 3525 .force_performance_level = smu_force_performance_level, 3526 .read_sensor = smu_read_sensor, 3527 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3528 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3529 .get_performance_level = smu_get_performance_level, 3530 .get_current_power_state = smu_get_current_power_state, 3531 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3532 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3533 .get_pp_num_states = smu_get_power_num_states, 3534 .get_pp_table = smu_sys_get_pp_table, 3535 .set_pp_table = smu_sys_set_pp_table, 3536 .switch_power_profile = smu_switch_power_profile, 3537 /* export to amdgpu */ 3538 .dispatch_tasks = smu_handle_dpm_task, 3539 .load_firmware = smu_load_microcode, 3540 .set_powergating_by_smu = smu_dpm_set_power_gate, 3541 .set_power_limit = smu_set_power_limit, 3542 .get_power_limit = smu_get_power_limit, 3543 .get_power_profile_mode = smu_get_power_profile_mode, 3544 .set_power_profile_mode = smu_set_power_profile_mode, 3545 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3546 .set_mp1_state = smu_set_mp1_state, 3547 .gfx_state_change_set = smu_gfx_state_change_set, 3548 /* export to DC */ 3549 .get_sclk = smu_get_sclk, 3550 .get_mclk = smu_get_mclk, 3551 .display_configuration_change = smu_display_configuration_change, 3552 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3553 .display_clock_voltage_request = smu_display_clock_voltage_request, 3554 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3555 .set_active_display_count = smu_set_display_count, 3556 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3557 .get_asic_baco_capability = smu_get_baco_capability, 3558 .set_asic_baco_state = smu_baco_set_state, 3559 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3560 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3561 .asic_reset_mode_2 = smu_mode2_reset, 3562 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3563 .set_df_cstate = smu_set_df_cstate, 3564 .set_xgmi_pstate = smu_set_xgmi_pstate, 3565 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3566 .get_pm_metrics = smu_sys_get_pm_metrics, 3567 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3568 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3569 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3570 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3571 .get_dpm_clock_table = smu_get_dpm_clock_table, 3572 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3573 }; 3574 3575 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3576 uint64_t event_arg) 3577 { 3578 int ret = -EINVAL; 3579 3580 if (smu->ppt_funcs->wait_for_event) 3581 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3582 3583 return ret; 3584 } 3585 3586 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3587 { 3588 3589 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3590 return -EOPNOTSUPP; 3591 3592 /* Confirm the buffer allocated is of correct size */ 3593 if (size != smu->stb_context.stb_buf_size) 3594 return -EINVAL; 3595 3596 /* 3597 * No need to lock smu mutex as we access STB directly through MMIO 3598 * and not going through SMU messaging route (for now at least). 3599 * For registers access rely on implementation internal locking. 3600 */ 3601 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3602 } 3603 3604 #if defined(CONFIG_DEBUG_FS) 3605 3606 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3607 { 3608 struct amdgpu_device *adev = filp->f_inode->i_private; 3609 struct smu_context *smu = adev->powerplay.pp_handle; 3610 unsigned char *buf; 3611 int r; 3612 3613 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3614 if (!buf) 3615 return -ENOMEM; 3616 3617 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3618 if (r) 3619 goto out; 3620 3621 filp->private_data = buf; 3622 3623 return 0; 3624 3625 out: 3626 kvfree(buf); 3627 return r; 3628 } 3629 3630 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3631 loff_t *pos) 3632 { 3633 struct amdgpu_device *adev = filp->f_inode->i_private; 3634 struct smu_context *smu = adev->powerplay.pp_handle; 3635 3636 3637 if (!filp->private_data) 3638 return -EINVAL; 3639 3640 return simple_read_from_buffer(buf, 3641 size, 3642 pos, filp->private_data, 3643 smu->stb_context.stb_buf_size); 3644 } 3645 3646 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3647 { 3648 kvfree(filp->private_data); 3649 filp->private_data = NULL; 3650 3651 return 0; 3652 } 3653 3654 /* 3655 * We have to define not only read method but also 3656 * open and release because .read takes up to PAGE_SIZE 3657 * data each time so and so is invoked multiple times. 3658 * We allocate the STB buffer in .open and release it 3659 * in .release 3660 */ 3661 static const struct file_operations smu_stb_debugfs_fops = { 3662 .owner = THIS_MODULE, 3663 .open = smu_stb_debugfs_open, 3664 .read = smu_stb_debugfs_read, 3665 .release = smu_stb_debugfs_release, 3666 .llseek = default_llseek, 3667 }; 3668 3669 #endif 3670 3671 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3672 { 3673 #if defined(CONFIG_DEBUG_FS) 3674 3675 struct smu_context *smu = adev->powerplay.pp_handle; 3676 3677 if (!smu || (!smu->stb_context.stb_buf_size)) 3678 return; 3679 3680 debugfs_create_file_size("amdgpu_smu_stb_dump", 3681 S_IRUSR, 3682 adev_to_drm(adev)->primary->debugfs_root, 3683 adev, 3684 &smu_stb_debugfs_fops, 3685 smu->stb_context.stb_buf_size); 3686 #endif 3687 } 3688 3689 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3690 { 3691 int ret = 0; 3692 3693 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3694 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3695 3696 return ret; 3697 } 3698 3699 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3700 { 3701 int ret = 0; 3702 3703 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3704 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3705 3706 return ret; 3707 } 3708 3709 int smu_send_rma_reason(struct smu_context *smu) 3710 { 3711 int ret = 0; 3712 3713 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3714 ret = smu->ppt_funcs->send_rma_reason(smu); 3715 3716 return ret; 3717 } 3718