1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max); 144 145 return ret; 146 } 147 148 int smu_get_dpm_freq_range(struct smu_context *smu, 149 enum smu_clk_type clk_type, 150 uint32_t *min, 151 uint32_t *max) 152 { 153 int ret = -ENOTSUPP; 154 155 if (!min && !max) 156 return -EINVAL; 157 158 if (smu->ppt_funcs->get_dpm_ultimate_freq) 159 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 160 clk_type, 161 min, 162 max); 163 164 return ret; 165 } 166 167 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 168 { 169 int ret = 0; 170 struct amdgpu_device *adev = smu->adev; 171 172 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 173 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 174 if (ret) 175 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 176 } 177 return ret; 178 } 179 180 static u32 smu_get_mclk(void *handle, bool low) 181 { 182 struct smu_context *smu = handle; 183 uint32_t clk_freq; 184 int ret = 0; 185 186 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 187 low ? &clk_freq : NULL, 188 !low ? &clk_freq : NULL); 189 if (ret) 190 return 0; 191 return clk_freq * 100; 192 } 193 194 static u32 smu_get_sclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static int smu_set_gfx_imu_enable(struct smu_context *smu) 209 { 210 struct amdgpu_device *adev = smu->adev; 211 212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 213 return 0; 214 215 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 216 return 0; 217 218 return smu_set_gfx_power_up_by_imu(smu); 219 } 220 221 static bool is_vcn_enabled(struct amdgpu_device *adev) 222 { 223 int i; 224 225 for (i = 0; i < adev->num_ip_blocks; i++) { 226 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 227 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 228 !adev->ip_blocks[i].status.valid) 229 return false; 230 } 231 232 return true; 233 } 234 235 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 236 bool enable) 237 { 238 struct smu_power_context *smu_power = &smu->smu_power; 239 struct smu_power_gate *power_gate = &smu_power->power_gate; 240 int ret = 0; 241 242 /* 243 * don't poweron vcn/jpeg when they are skipped. 244 */ 245 if (!is_vcn_enabled(smu->adev)) 246 return 0; 247 248 if (!smu->ppt_funcs->dpm_set_vcn_enable) 249 return 0; 250 251 if (atomic_read(&power_gate->vcn_gated) ^ enable) 252 return 0; 253 254 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 255 if (!ret) 256 atomic_set(&power_gate->vcn_gated, !enable); 257 258 return ret; 259 } 260 261 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 262 bool enable) 263 { 264 struct smu_power_context *smu_power = &smu->smu_power; 265 struct smu_power_gate *power_gate = &smu_power->power_gate; 266 int ret = 0; 267 268 if (!is_vcn_enabled(smu->adev)) 269 return 0; 270 271 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 272 return 0; 273 274 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 275 return 0; 276 277 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 278 if (!ret) 279 atomic_set(&power_gate->jpeg_gated, !enable); 280 281 return ret; 282 } 283 284 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 285 bool enable) 286 { 287 struct smu_power_context *smu_power = &smu->smu_power; 288 struct smu_power_gate *power_gate = &smu_power->power_gate; 289 int ret = 0; 290 291 if (!smu->ppt_funcs->dpm_set_vpe_enable) 292 return 0; 293 294 if (atomic_read(&power_gate->vpe_gated) ^ enable) 295 return 0; 296 297 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 298 if (!ret) 299 atomic_set(&power_gate->vpe_gated, !enable); 300 301 return ret; 302 } 303 304 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 305 bool enable) 306 { 307 struct smu_power_context *smu_power = &smu->smu_power; 308 struct smu_power_gate *power_gate = &smu_power->power_gate; 309 int ret = 0; 310 311 if (!smu->adev->enable_umsch_mm) 312 return 0; 313 314 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 315 return 0; 316 317 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 318 return 0; 319 320 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 321 if (!ret) 322 atomic_set(&power_gate->umsch_mm_gated, !enable); 323 324 return ret; 325 } 326 327 static int smu_set_mall_enable(struct smu_context *smu) 328 { 329 int ret = 0; 330 331 if (!smu->ppt_funcs->set_mall_enable) 332 return 0; 333 334 ret = smu->ppt_funcs->set_mall_enable(smu); 335 336 return ret; 337 } 338 339 /** 340 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 341 * 342 * @handle: smu_context pointer 343 * @block_type: the IP block to power gate/ungate 344 * @gate: to power gate if true, ungate otherwise 345 * 346 * This API uses no smu->mutex lock protection due to: 347 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 348 * This is guarded to be race condition free by the caller. 349 * 2. Or get called on user setting request of power_dpm_force_performance_level. 350 * Under this case, the smu->mutex lock protection is already enforced on 351 * the parent API smu_force_performance_level of the call path. 352 */ 353 static int smu_dpm_set_power_gate(void *handle, 354 uint32_t block_type, 355 bool gate) 356 { 357 struct smu_context *smu = handle; 358 int ret = 0; 359 360 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 361 dev_WARN(smu->adev->dev, 362 "SMU uninitialized but power %s requested for %u!\n", 363 gate ? "gate" : "ungate", block_type); 364 return -EOPNOTSUPP; 365 } 366 367 switch (block_type) { 368 /* 369 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 370 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 371 */ 372 case AMD_IP_BLOCK_TYPE_UVD: 373 case AMD_IP_BLOCK_TYPE_VCN: 374 ret = smu_dpm_set_vcn_enable(smu, !gate); 375 if (ret) 376 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 377 gate ? "gate" : "ungate"); 378 break; 379 case AMD_IP_BLOCK_TYPE_GFX: 380 ret = smu_gfx_off_control(smu, gate); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 383 gate ? "enable" : "disable"); 384 break; 385 case AMD_IP_BLOCK_TYPE_SDMA: 386 ret = smu_powergate_sdma(smu, gate); 387 if (ret) 388 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 389 gate ? "gate" : "ungate"); 390 break; 391 case AMD_IP_BLOCK_TYPE_JPEG: 392 ret = smu_dpm_set_jpeg_enable(smu, !gate); 393 if (ret) 394 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 395 gate ? "gate" : "ungate"); 396 break; 397 case AMD_IP_BLOCK_TYPE_VPE: 398 ret = smu_dpm_set_vpe_enable(smu, !gate); 399 if (ret) 400 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 401 gate ? "gate" : "ungate"); 402 break; 403 default: 404 dev_err(smu->adev->dev, "Unsupported block type!\n"); 405 return -EINVAL; 406 } 407 408 return ret; 409 } 410 411 /** 412 * smu_set_user_clk_dependencies - set user profile clock dependencies 413 * 414 * @smu: smu_context pointer 415 * @clk: enum smu_clk_type type 416 * 417 * Enable/Disable the clock dependency for the @clk type. 418 */ 419 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 420 { 421 if (smu->adev->in_suspend) 422 return; 423 424 if (clk == SMU_MCLK) { 425 smu->user_dpm_profile.clk_dependency = 0; 426 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 427 } else if (clk == SMU_FCLK) { 428 /* MCLK takes precedence over FCLK */ 429 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 430 return; 431 432 smu->user_dpm_profile.clk_dependency = 0; 433 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 434 } else if (clk == SMU_SOCCLK) { 435 /* MCLK takes precedence over SOCCLK */ 436 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 437 return; 438 439 smu->user_dpm_profile.clk_dependency = 0; 440 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 441 } else 442 /* Add clk dependencies here, if any */ 443 return; 444 } 445 446 /** 447 * smu_restore_dpm_user_profile - reinstate user dpm profile 448 * 449 * @smu: smu_context pointer 450 * 451 * Restore the saved user power configurations include power limit, 452 * clock frequencies, fan control mode and fan speed. 453 */ 454 static void smu_restore_dpm_user_profile(struct smu_context *smu) 455 { 456 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 457 int ret = 0; 458 459 if (!smu->adev->in_suspend) 460 return; 461 462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 463 return; 464 465 /* Enable restore flag */ 466 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 467 468 /* set the user dpm power limit */ 469 if (smu->user_dpm_profile.power_limit) { 470 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 471 if (ret) 472 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 473 } 474 475 /* set the user dpm clock configurations */ 476 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 477 enum smu_clk_type clk_type; 478 479 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 480 /* 481 * Iterate over smu clk type and force the saved user clk 482 * configs, skip if clock dependency is enabled 483 */ 484 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 485 smu->user_dpm_profile.clk_mask[clk_type]) { 486 ret = smu_force_smuclk_levels(smu, clk_type, 487 smu->user_dpm_profile.clk_mask[clk_type]); 488 if (ret) 489 dev_err(smu->adev->dev, 490 "Failed to set clock type = %d\n", clk_type); 491 } 492 } 493 } 494 495 /* set the user dpm fan configurations */ 496 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 497 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 498 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 499 if (ret != -EOPNOTSUPP) { 500 smu->user_dpm_profile.fan_speed_pwm = 0; 501 smu->user_dpm_profile.fan_speed_rpm = 0; 502 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 503 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 504 } 505 506 if (smu->user_dpm_profile.fan_speed_pwm) { 507 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 508 if (ret != -EOPNOTSUPP) 509 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 510 } 511 512 if (smu->user_dpm_profile.fan_speed_rpm) { 513 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 514 if (ret != -EOPNOTSUPP) 515 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 516 } 517 } 518 519 /* Restore user customized OD settings */ 520 if (smu->user_dpm_profile.user_od) { 521 if (smu->ppt_funcs->restore_user_od_settings) { 522 ret = smu->ppt_funcs->restore_user_od_settings(smu); 523 if (ret) 524 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 525 } 526 } 527 528 /* Disable restore flag */ 529 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 530 } 531 532 static int smu_get_power_num_states(void *handle, 533 struct pp_states_info *state_info) 534 { 535 if (!state_info) 536 return -EINVAL; 537 538 /* not support power state */ 539 memset(state_info, 0, sizeof(struct pp_states_info)); 540 state_info->nums = 1; 541 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 542 543 return 0; 544 } 545 546 bool is_support_sw_smu(struct amdgpu_device *adev) 547 { 548 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 549 if (adev->asic_type == CHIP_VEGA20) 550 return false; 551 552 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 553 return true; 554 555 return false; 556 } 557 558 bool is_support_cclk_dpm(struct amdgpu_device *adev) 559 { 560 struct smu_context *smu = adev->powerplay.pp_handle; 561 562 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 563 return false; 564 565 return true; 566 } 567 568 569 static int smu_sys_get_pp_table(void *handle, 570 char **table) 571 { 572 struct smu_context *smu = handle; 573 struct smu_table_context *smu_table = &smu->smu_table; 574 575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 576 return -EOPNOTSUPP; 577 578 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 579 return -EINVAL; 580 581 if (smu_table->hardcode_pptable) 582 *table = smu_table->hardcode_pptable; 583 else 584 *table = smu_table->power_play_table; 585 586 return smu_table->power_play_table_size; 587 } 588 589 static int smu_sys_set_pp_table(void *handle, 590 const char *buf, 591 size_t size) 592 { 593 struct smu_context *smu = handle; 594 struct smu_table_context *smu_table = &smu->smu_table; 595 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 596 int ret = 0; 597 598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 599 return -EOPNOTSUPP; 600 601 if (header->usStructureSize != size) { 602 dev_err(smu->adev->dev, "pp table size not matched !\n"); 603 return -EIO; 604 } 605 606 if (!smu_table->hardcode_pptable) { 607 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 608 if (!smu_table->hardcode_pptable) 609 return -ENOMEM; 610 } 611 612 memcpy(smu_table->hardcode_pptable, buf, size); 613 smu_table->power_play_table = smu_table->hardcode_pptable; 614 smu_table->power_play_table_size = size; 615 616 /* 617 * Special hw_fini action(for Navi1x, the DPMs disablement will be 618 * skipped) may be needed for custom pptable uploading. 619 */ 620 smu->uploading_custom_pp_table = true; 621 622 ret = smu_reset(smu); 623 if (ret) 624 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 625 626 smu->uploading_custom_pp_table = false; 627 628 return ret; 629 } 630 631 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 632 { 633 struct smu_feature *feature = &smu->smu_feature; 634 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 635 int ret = 0; 636 637 /* 638 * With SCPM enabled, the allowed featuremasks setting(via 639 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 640 * That means there is no way to let PMFW knows the settings below. 641 * Thus, we just assume all the features are allowed under 642 * such scenario. 643 */ 644 if (smu->adev->scpm_enabled) { 645 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 646 return 0; 647 } 648 649 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 650 651 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 652 SMU_FEATURE_MAX/32); 653 if (ret) 654 return ret; 655 656 bitmap_or(feature->allowed, feature->allowed, 657 (unsigned long *)allowed_feature_mask, 658 feature->feature_num); 659 660 return ret; 661 } 662 663 static int smu_set_funcs(struct amdgpu_device *adev) 664 { 665 struct smu_context *smu = adev->powerplay.pp_handle; 666 667 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 668 smu->od_enabled = true; 669 670 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 671 case IP_VERSION(11, 0, 0): 672 case IP_VERSION(11, 0, 5): 673 case IP_VERSION(11, 0, 9): 674 navi10_set_ppt_funcs(smu); 675 break; 676 case IP_VERSION(11, 0, 7): 677 case IP_VERSION(11, 0, 11): 678 case IP_VERSION(11, 0, 12): 679 case IP_VERSION(11, 0, 13): 680 sienna_cichlid_set_ppt_funcs(smu); 681 break; 682 case IP_VERSION(12, 0, 0): 683 case IP_VERSION(12, 0, 1): 684 renoir_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 5, 0): 687 vangogh_set_ppt_funcs(smu); 688 break; 689 case IP_VERSION(13, 0, 1): 690 case IP_VERSION(13, 0, 3): 691 case IP_VERSION(13, 0, 8): 692 yellow_carp_set_ppt_funcs(smu); 693 break; 694 case IP_VERSION(13, 0, 4): 695 case IP_VERSION(13, 0, 11): 696 smu_v13_0_4_set_ppt_funcs(smu); 697 break; 698 case IP_VERSION(13, 0, 5): 699 smu_v13_0_5_set_ppt_funcs(smu); 700 break; 701 case IP_VERSION(11, 0, 8): 702 cyan_skillfish_set_ppt_funcs(smu); 703 break; 704 case IP_VERSION(11, 0, 2): 705 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 706 arcturus_set_ppt_funcs(smu); 707 /* OD is not supported on Arcturus */ 708 smu->od_enabled = false; 709 break; 710 case IP_VERSION(13, 0, 2): 711 aldebaran_set_ppt_funcs(smu); 712 /* Enable pp_od_clk_voltage node */ 713 smu->od_enabled = true; 714 break; 715 case IP_VERSION(13, 0, 0): 716 case IP_VERSION(13, 0, 10): 717 smu_v13_0_0_set_ppt_funcs(smu); 718 break; 719 case IP_VERSION(13, 0, 6): 720 case IP_VERSION(13, 0, 14): 721 smu_v13_0_6_set_ppt_funcs(smu); 722 /* Enable pp_od_clk_voltage node */ 723 smu->od_enabled = true; 724 break; 725 case IP_VERSION(13, 0, 7): 726 smu_v13_0_7_set_ppt_funcs(smu); 727 break; 728 case IP_VERSION(14, 0, 0): 729 case IP_VERSION(14, 0, 1): 730 case IP_VERSION(14, 0, 4): 731 smu_v14_0_0_set_ppt_funcs(smu); 732 break; 733 case IP_VERSION(14, 0, 2): 734 case IP_VERSION(14, 0, 3): 735 smu_v14_0_2_set_ppt_funcs(smu); 736 break; 737 default: 738 return -EINVAL; 739 } 740 741 return 0; 742 } 743 744 static int smu_early_init(void *handle) 745 { 746 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 747 struct smu_context *smu; 748 int r; 749 750 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 751 if (!smu) 752 return -ENOMEM; 753 754 smu->adev = adev; 755 smu->pm_enabled = !!amdgpu_dpm; 756 smu->is_apu = false; 757 smu->smu_baco.state = SMU_BACO_STATE_NONE; 758 smu->smu_baco.platform_support = false; 759 smu->smu_baco.maco_support = false; 760 smu->user_dpm_profile.fan_mode = -1; 761 762 mutex_init(&smu->message_lock); 763 764 adev->powerplay.pp_handle = smu; 765 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 766 767 r = smu_set_funcs(adev); 768 if (r) 769 return r; 770 return smu_init_microcode(smu); 771 } 772 773 static int smu_set_default_dpm_table(struct smu_context *smu) 774 { 775 struct amdgpu_device *adev = smu->adev; 776 struct smu_power_context *smu_power = &smu->smu_power; 777 struct smu_power_gate *power_gate = &smu_power->power_gate; 778 int vcn_gate, jpeg_gate; 779 int ret = 0; 780 781 if (!smu->ppt_funcs->set_default_dpm_table) 782 return 0; 783 784 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 785 vcn_gate = atomic_read(&power_gate->vcn_gated); 786 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 787 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 788 789 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 790 ret = smu_dpm_set_vcn_enable(smu, true); 791 if (ret) 792 return ret; 793 } 794 795 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 796 ret = smu_dpm_set_jpeg_enable(smu, true); 797 if (ret) 798 goto err_out; 799 } 800 801 ret = smu->ppt_funcs->set_default_dpm_table(smu); 802 if (ret) 803 dev_err(smu->adev->dev, 804 "Failed to setup default dpm clock tables!\n"); 805 806 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 807 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 808 err_out: 809 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 810 smu_dpm_set_vcn_enable(smu, !vcn_gate); 811 812 return ret; 813 } 814 815 static int smu_apply_default_config_table_settings(struct smu_context *smu) 816 { 817 struct amdgpu_device *adev = smu->adev; 818 int ret = 0; 819 820 ret = smu_get_default_config_table_settings(smu, 821 &adev->pm.config_table); 822 if (ret) 823 return ret; 824 825 return smu_set_config_table(smu, &adev->pm.config_table); 826 } 827 828 static int smu_late_init(void *handle) 829 { 830 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 831 struct smu_context *smu = adev->powerplay.pp_handle; 832 int ret = 0; 833 834 smu_set_fine_grain_gfx_freq_parameters(smu); 835 836 if (!smu->pm_enabled) 837 return 0; 838 839 ret = smu_post_init(smu); 840 if (ret) { 841 dev_err(adev->dev, "Failed to post smu init!\n"); 842 return ret; 843 } 844 845 /* 846 * Explicitly notify PMFW the power mode the system in. Since 847 * the PMFW may boot the ASIC with a different mode. 848 * For those supporting ACDC switch via gpio, PMFW will 849 * handle the switch automatically. Driver involvement 850 * is unnecessary. 851 */ 852 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 853 smu_set_ac_dc(smu); 854 855 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 856 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 857 return 0; 858 859 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 860 ret = smu_set_default_od_settings(smu); 861 if (ret) { 862 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 863 return ret; 864 } 865 } 866 867 ret = smu_populate_umd_state_clk(smu); 868 if (ret) { 869 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 870 return ret; 871 } 872 873 ret = smu_get_asic_power_limits(smu, 874 &smu->current_power_limit, 875 &smu->default_power_limit, 876 &smu->max_power_limit, 877 &smu->min_power_limit); 878 if (ret) { 879 dev_err(adev->dev, "Failed to get asic power limits!\n"); 880 return ret; 881 } 882 883 if (!amdgpu_sriov_vf(adev)) 884 smu_get_unique_id(smu); 885 886 smu_get_fan_parameters(smu); 887 888 smu_handle_task(smu, 889 smu->smu_dpm.dpm_level, 890 AMD_PP_TASK_COMPLETE_INIT); 891 892 ret = smu_apply_default_config_table_settings(smu); 893 if (ret && (ret != -EOPNOTSUPP)) { 894 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 895 return ret; 896 } 897 898 smu_restore_dpm_user_profile(smu); 899 900 return 0; 901 } 902 903 static int smu_init_fb_allocations(struct smu_context *smu) 904 { 905 struct amdgpu_device *adev = smu->adev; 906 struct smu_table_context *smu_table = &smu->smu_table; 907 struct smu_table *tables = smu_table->tables; 908 struct smu_table *driver_table = &(smu_table->driver_table); 909 uint32_t max_table_size = 0; 910 int ret, i; 911 912 /* VRAM allocation for tool table */ 913 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 914 ret = amdgpu_bo_create_kernel(adev, 915 tables[SMU_TABLE_PMSTATUSLOG].size, 916 tables[SMU_TABLE_PMSTATUSLOG].align, 917 tables[SMU_TABLE_PMSTATUSLOG].domain, 918 &tables[SMU_TABLE_PMSTATUSLOG].bo, 919 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 920 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 921 if (ret) { 922 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 923 return ret; 924 } 925 } 926 927 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 928 /* VRAM allocation for driver table */ 929 for (i = 0; i < SMU_TABLE_COUNT; i++) { 930 if (tables[i].size == 0) 931 continue; 932 933 /* If one of the tables has VRAM domain restriction, keep it in 934 * VRAM 935 */ 936 if ((tables[i].domain & 937 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 938 AMDGPU_GEM_DOMAIN_VRAM) 939 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 940 941 if (i == SMU_TABLE_PMSTATUSLOG) 942 continue; 943 944 if (max_table_size < tables[i].size) 945 max_table_size = tables[i].size; 946 } 947 948 driver_table->size = max_table_size; 949 driver_table->align = PAGE_SIZE; 950 951 ret = amdgpu_bo_create_kernel(adev, 952 driver_table->size, 953 driver_table->align, 954 driver_table->domain, 955 &driver_table->bo, 956 &driver_table->mc_address, 957 &driver_table->cpu_addr); 958 if (ret) { 959 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 960 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 961 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 962 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 963 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 964 } 965 966 return ret; 967 } 968 969 static int smu_fini_fb_allocations(struct smu_context *smu) 970 { 971 struct smu_table_context *smu_table = &smu->smu_table; 972 struct smu_table *tables = smu_table->tables; 973 struct smu_table *driver_table = &(smu_table->driver_table); 974 975 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 976 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 977 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 978 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 979 980 amdgpu_bo_free_kernel(&driver_table->bo, 981 &driver_table->mc_address, 982 &driver_table->cpu_addr); 983 984 return 0; 985 } 986 987 /** 988 * smu_alloc_memory_pool - allocate memory pool in the system memory 989 * 990 * @smu: amdgpu_device pointer 991 * 992 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 993 * and DramLogSetDramAddr can notify it changed. 994 * 995 * Returns 0 on success, error on failure. 996 */ 997 static int smu_alloc_memory_pool(struct smu_context *smu) 998 { 999 struct amdgpu_device *adev = smu->adev; 1000 struct smu_table_context *smu_table = &smu->smu_table; 1001 struct smu_table *memory_pool = &smu_table->memory_pool; 1002 uint64_t pool_size = smu->pool_size; 1003 int ret = 0; 1004 1005 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1006 return ret; 1007 1008 memory_pool->size = pool_size; 1009 memory_pool->align = PAGE_SIZE; 1010 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1011 1012 switch (pool_size) { 1013 case SMU_MEMORY_POOL_SIZE_256_MB: 1014 case SMU_MEMORY_POOL_SIZE_512_MB: 1015 case SMU_MEMORY_POOL_SIZE_1_GB: 1016 case SMU_MEMORY_POOL_SIZE_2_GB: 1017 ret = amdgpu_bo_create_kernel(adev, 1018 memory_pool->size, 1019 memory_pool->align, 1020 memory_pool->domain, 1021 &memory_pool->bo, 1022 &memory_pool->mc_address, 1023 &memory_pool->cpu_addr); 1024 if (ret) 1025 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 return ret; 1032 } 1033 1034 static int smu_free_memory_pool(struct smu_context *smu) 1035 { 1036 struct smu_table_context *smu_table = &smu->smu_table; 1037 struct smu_table *memory_pool = &smu_table->memory_pool; 1038 1039 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1040 return 0; 1041 1042 amdgpu_bo_free_kernel(&memory_pool->bo, 1043 &memory_pool->mc_address, 1044 &memory_pool->cpu_addr); 1045 1046 memset(memory_pool, 0, sizeof(struct smu_table)); 1047 1048 return 0; 1049 } 1050 1051 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1052 { 1053 struct smu_table_context *smu_table = &smu->smu_table; 1054 struct smu_table *dummy_read_1_table = 1055 &smu_table->dummy_read_1_table; 1056 struct amdgpu_device *adev = smu->adev; 1057 int ret = 0; 1058 1059 if (!dummy_read_1_table->size) 1060 return 0; 1061 1062 ret = amdgpu_bo_create_kernel(adev, 1063 dummy_read_1_table->size, 1064 dummy_read_1_table->align, 1065 dummy_read_1_table->domain, 1066 &dummy_read_1_table->bo, 1067 &dummy_read_1_table->mc_address, 1068 &dummy_read_1_table->cpu_addr); 1069 if (ret) 1070 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1071 1072 return ret; 1073 } 1074 1075 static void smu_free_dummy_read_table(struct smu_context *smu) 1076 { 1077 struct smu_table_context *smu_table = &smu->smu_table; 1078 struct smu_table *dummy_read_1_table = 1079 &smu_table->dummy_read_1_table; 1080 1081 1082 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1083 &dummy_read_1_table->mc_address, 1084 &dummy_read_1_table->cpu_addr); 1085 1086 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1087 } 1088 1089 static int smu_smc_table_sw_init(struct smu_context *smu) 1090 { 1091 int ret; 1092 1093 /** 1094 * Create smu_table structure, and init smc tables such as 1095 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1096 */ 1097 ret = smu_init_smc_tables(smu); 1098 if (ret) { 1099 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1100 return ret; 1101 } 1102 1103 /** 1104 * Create smu_power_context structure, and allocate smu_dpm_context and 1105 * context size to fill the smu_power_context data. 1106 */ 1107 ret = smu_init_power(smu); 1108 if (ret) { 1109 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1110 return ret; 1111 } 1112 1113 /* 1114 * allocate vram bos to store smc table contents. 1115 */ 1116 ret = smu_init_fb_allocations(smu); 1117 if (ret) 1118 return ret; 1119 1120 ret = smu_alloc_memory_pool(smu); 1121 if (ret) 1122 return ret; 1123 1124 ret = smu_alloc_dummy_read_table(smu); 1125 if (ret) 1126 return ret; 1127 1128 ret = smu_i2c_init(smu); 1129 if (ret) 1130 return ret; 1131 1132 return 0; 1133 } 1134 1135 static int smu_smc_table_sw_fini(struct smu_context *smu) 1136 { 1137 int ret; 1138 1139 smu_i2c_fini(smu); 1140 1141 smu_free_dummy_read_table(smu); 1142 1143 ret = smu_free_memory_pool(smu); 1144 if (ret) 1145 return ret; 1146 1147 ret = smu_fini_fb_allocations(smu); 1148 if (ret) 1149 return ret; 1150 1151 ret = smu_fini_power(smu); 1152 if (ret) { 1153 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1154 return ret; 1155 } 1156 1157 ret = smu_fini_smc_tables(smu); 1158 if (ret) { 1159 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1160 return ret; 1161 } 1162 1163 return 0; 1164 } 1165 1166 static void smu_throttling_logging_work_fn(struct work_struct *work) 1167 { 1168 struct smu_context *smu = container_of(work, struct smu_context, 1169 throttling_logging_work); 1170 1171 smu_log_thermal_throttling(smu); 1172 } 1173 1174 static void smu_interrupt_work_fn(struct work_struct *work) 1175 { 1176 struct smu_context *smu = container_of(work, struct smu_context, 1177 interrupt_work); 1178 1179 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1180 smu->ppt_funcs->interrupt_work(smu); 1181 } 1182 1183 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1184 { 1185 struct smu_context *smu = 1186 container_of(work, struct smu_context, swctf_delayed_work.work); 1187 struct smu_temperature_range *range = 1188 &smu->thermal_range; 1189 struct amdgpu_device *adev = smu->adev; 1190 uint32_t hotspot_tmp, size; 1191 1192 /* 1193 * If the hotspot temperature is confirmed as below SW CTF setting point 1194 * after the delay enforced, nothing will be done. 1195 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1196 */ 1197 if (range->software_shutdown_temp && 1198 smu->ppt_funcs->read_sensor && 1199 !smu->ppt_funcs->read_sensor(smu, 1200 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1201 &hotspot_tmp, 1202 &size) && 1203 hotspot_tmp / 1000 < range->software_shutdown_temp) 1204 return; 1205 1206 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1207 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1208 orderly_poweroff(true); 1209 } 1210 1211 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1212 { 1213 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1214 struct smu_dpm_policy_ctxt *policy_ctxt; 1215 struct smu_dpm_policy *policy; 1216 1217 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1218 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1219 if (policy) 1220 policy->current_level = XGMI_PLPD_DEFAULT; 1221 return; 1222 } 1223 1224 /* PMFW put PLPD into default policy after enabling the feature */ 1225 if (smu_feature_is_enabled(smu, 1226 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1227 if (policy) 1228 policy->current_level = XGMI_PLPD_DEFAULT; 1229 } else { 1230 policy_ctxt = dpm_ctxt->dpm_policies; 1231 if (policy_ctxt) 1232 policy_ctxt->policy_mask &= 1233 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1234 } 1235 } 1236 1237 static bool smu_is_workload_profile_available(struct smu_context *smu, 1238 u32 profile) 1239 { 1240 if (profile >= PP_SMC_POWER_PROFILE_COUNT) 1241 return false; 1242 return smu->workload_map && smu->workload_map[profile].valid_mapping; 1243 } 1244 1245 static int smu_sw_init(void *handle) 1246 { 1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1248 struct smu_context *smu = adev->powerplay.pp_handle; 1249 int ret; 1250 1251 smu->pool_size = adev->pm.smu_prv_buffer_size; 1252 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1253 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1254 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1255 1256 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1257 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1258 atomic64_set(&smu->throttle_int_counter, 0); 1259 smu->watermarks_bitmap = 0; 1260 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1261 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1262 1263 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1264 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1265 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1266 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1267 1268 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1269 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1270 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1271 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1272 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1273 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1274 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1275 1276 if (smu->is_apu || 1277 !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) 1278 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1279 else 1280 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1281 1282 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1283 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1284 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1285 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1286 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1287 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1288 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1289 smu->display_config = &adev->pm.pm_display_cfg; 1290 1291 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1292 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1293 1294 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1295 smu_swctf_delayed_work_handler); 1296 1297 ret = smu_smc_table_sw_init(smu); 1298 if (ret) { 1299 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1300 return ret; 1301 } 1302 1303 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1304 ret = smu_get_vbios_bootup_values(smu); 1305 if (ret) { 1306 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1307 return ret; 1308 } 1309 1310 ret = smu_init_pptable_microcode(smu); 1311 if (ret) { 1312 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1313 return ret; 1314 } 1315 1316 ret = smu_register_irq_handler(smu); 1317 if (ret) { 1318 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1319 return ret; 1320 } 1321 1322 /* If there is no way to query fan control mode, fan control is not supported */ 1323 if (!smu->ppt_funcs->get_fan_control_mode) 1324 smu->adev->pm.no_fan = true; 1325 1326 return 0; 1327 } 1328 1329 static int smu_sw_fini(void *handle) 1330 { 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 struct smu_context *smu = adev->powerplay.pp_handle; 1333 int ret; 1334 1335 ret = smu_smc_table_sw_fini(smu); 1336 if (ret) { 1337 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1338 return ret; 1339 } 1340 1341 smu_fini_microcode(smu); 1342 1343 return 0; 1344 } 1345 1346 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1347 { 1348 struct amdgpu_device *adev = smu->adev; 1349 struct smu_temperature_range *range = 1350 &smu->thermal_range; 1351 int ret = 0; 1352 1353 if (!smu->ppt_funcs->get_thermal_temperature_range) 1354 return 0; 1355 1356 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1357 if (ret) 1358 return ret; 1359 1360 adev->pm.dpm.thermal.min_temp = range->min; 1361 adev->pm.dpm.thermal.max_temp = range->max; 1362 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1363 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1364 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1365 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1366 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1367 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1368 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1369 1370 return ret; 1371 } 1372 1373 /** 1374 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1375 * 1376 * @smu: smu_context pointer 1377 * 1378 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1379 * Returns 0 on success, error on failure. 1380 */ 1381 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1382 { 1383 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1384 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1385 struct amdgpu_device *adev = smu->adev; 1386 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1387 uint64_t start, end; 1388 int ret, i, j; 1389 1390 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1391 if (ret) { 1392 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1393 return ret; 1394 } 1395 1396 /* 1397 * The exclusion ranges array we got might be filled with holes and duplicate 1398 * entries. For example: 1399 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1400 * We need to do some sortups to eliminate those holes and duplicate entries. 1401 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1402 */ 1403 for (i = 0; i < num_of_wbrf_ranges; i++) { 1404 start = wifi_bands[i].start; 1405 end = wifi_bands[i].end; 1406 1407 /* get the last valid entry to fill the intermediate hole */ 1408 if (!start && !end) { 1409 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1410 if (wifi_bands[j].start && wifi_bands[j].end) 1411 break; 1412 1413 /* no valid entry left */ 1414 if (j <= i) 1415 break; 1416 1417 start = wifi_bands[i].start = wifi_bands[j].start; 1418 end = wifi_bands[i].end = wifi_bands[j].end; 1419 wifi_bands[j].start = 0; 1420 wifi_bands[j].end = 0; 1421 num_of_wbrf_ranges = j; 1422 } 1423 1424 /* eliminate duplicate entries */ 1425 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1426 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1427 wifi_bands[j].start = 0; 1428 wifi_bands[j].end = 0; 1429 } 1430 } 1431 } 1432 1433 /* Send the sorted wifi_bands to PMFW */ 1434 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1435 /* Try to set the wifi_bands again */ 1436 if (unlikely(ret == -EBUSY)) { 1437 mdelay(5); 1438 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1439 } 1440 1441 return ret; 1442 } 1443 1444 /** 1445 * smu_wbrf_event_handler - handle notify events 1446 * 1447 * @nb: notifier block 1448 * @action: event type 1449 * @_arg: event data 1450 * 1451 * Calls relevant amdgpu function in response to wbrf event 1452 * notification from kernel. 1453 */ 1454 static int smu_wbrf_event_handler(struct notifier_block *nb, 1455 unsigned long action, void *_arg) 1456 { 1457 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1458 1459 switch (action) { 1460 case WBRF_CHANGED: 1461 schedule_delayed_work(&smu->wbrf_delayed_work, 1462 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1463 break; 1464 default: 1465 return NOTIFY_DONE; 1466 } 1467 1468 return NOTIFY_OK; 1469 } 1470 1471 /** 1472 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1473 * 1474 * @work: struct work_struct pointer 1475 * 1476 * Flood is over and driver will consume the latest exclusion ranges. 1477 */ 1478 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1479 { 1480 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1481 1482 smu_wbrf_handle_exclusion_ranges(smu); 1483 } 1484 1485 /** 1486 * smu_wbrf_support_check - check wbrf support 1487 * 1488 * @smu: smu_context pointer 1489 * 1490 * Verifies the ACPI interface whether wbrf is supported. 1491 */ 1492 static void smu_wbrf_support_check(struct smu_context *smu) 1493 { 1494 struct amdgpu_device *adev = smu->adev; 1495 1496 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1497 acpi_amd_wbrf_supported_consumer(adev->dev); 1498 1499 if (smu->wbrf_supported) 1500 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1501 } 1502 1503 /** 1504 * smu_wbrf_init - init driver wbrf support 1505 * 1506 * @smu: smu_context pointer 1507 * 1508 * Verifies the AMD ACPI interfaces and registers with the wbrf 1509 * notifier chain if wbrf feature is supported. 1510 * Returns 0 on success, error on failure. 1511 */ 1512 static int smu_wbrf_init(struct smu_context *smu) 1513 { 1514 int ret; 1515 1516 if (!smu->wbrf_supported) 1517 return 0; 1518 1519 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1520 1521 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1522 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1523 if (ret) 1524 return ret; 1525 1526 /* 1527 * Some wifiband exclusion ranges may be already there 1528 * before our driver loaded. To make sure our driver 1529 * is awared of those exclusion ranges. 1530 */ 1531 schedule_delayed_work(&smu->wbrf_delayed_work, 1532 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1533 1534 return 0; 1535 } 1536 1537 /** 1538 * smu_wbrf_fini - tear down driver wbrf support 1539 * 1540 * @smu: smu_context pointer 1541 * 1542 * Unregisters with the wbrf notifier chain. 1543 */ 1544 static void smu_wbrf_fini(struct smu_context *smu) 1545 { 1546 if (!smu->wbrf_supported) 1547 return; 1548 1549 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1550 1551 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1552 } 1553 1554 static int smu_smc_hw_setup(struct smu_context *smu) 1555 { 1556 struct smu_feature *feature = &smu->smu_feature; 1557 struct amdgpu_device *adev = smu->adev; 1558 uint8_t pcie_gen = 0, pcie_width = 0; 1559 uint64_t features_supported; 1560 int ret = 0; 1561 1562 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1563 case IP_VERSION(11, 0, 7): 1564 case IP_VERSION(11, 0, 11): 1565 case IP_VERSION(11, 5, 0): 1566 case IP_VERSION(11, 0, 12): 1567 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1568 dev_info(adev->dev, "dpm has been enabled\n"); 1569 ret = smu_system_features_control(smu, true); 1570 if (ret) 1571 dev_err(adev->dev, "Failed system features control!\n"); 1572 return ret; 1573 } 1574 break; 1575 default: 1576 break; 1577 } 1578 1579 ret = smu_init_display_count(smu, 0); 1580 if (ret) { 1581 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1582 return ret; 1583 } 1584 1585 ret = smu_set_driver_table_location(smu); 1586 if (ret) { 1587 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1588 return ret; 1589 } 1590 1591 /* 1592 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1593 */ 1594 ret = smu_set_tool_table_location(smu); 1595 if (ret) { 1596 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1597 return ret; 1598 } 1599 1600 /* 1601 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1602 * pool location. 1603 */ 1604 ret = smu_notify_memory_pool_location(smu); 1605 if (ret) { 1606 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1607 return ret; 1608 } 1609 1610 /* 1611 * It is assumed the pptable used before runpm is same as 1612 * the one used afterwards. Thus, we can reuse the stored 1613 * copy and do not need to resetup the pptable again. 1614 */ 1615 if (!adev->in_runpm) { 1616 ret = smu_setup_pptable(smu); 1617 if (ret) { 1618 dev_err(adev->dev, "Failed to setup pptable!\n"); 1619 return ret; 1620 } 1621 } 1622 1623 /* smu_dump_pptable(smu); */ 1624 1625 /* 1626 * With SCPM enabled, PSP is responsible for the PPTable transferring 1627 * (to SMU). Driver involvement is not needed and permitted. 1628 */ 1629 if (!adev->scpm_enabled) { 1630 /* 1631 * Copy pptable bo in the vram to smc with SMU MSGs such as 1632 * SetDriverDramAddr and TransferTableDram2Smu. 1633 */ 1634 ret = smu_write_pptable(smu); 1635 if (ret) { 1636 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1637 return ret; 1638 } 1639 } 1640 1641 /* issue Run*Btc msg */ 1642 ret = smu_run_btc(smu); 1643 if (ret) 1644 return ret; 1645 1646 /* Enable UclkShadow on wbrf supported */ 1647 if (smu->wbrf_supported) { 1648 ret = smu_enable_uclk_shadow(smu, true); 1649 if (ret) { 1650 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1651 return ret; 1652 } 1653 } 1654 1655 /* 1656 * With SCPM enabled, these actions(and relevant messages) are 1657 * not needed and permitted. 1658 */ 1659 if (!adev->scpm_enabled) { 1660 ret = smu_feature_set_allowed_mask(smu); 1661 if (ret) { 1662 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1663 return ret; 1664 } 1665 } 1666 1667 ret = smu_system_features_control(smu, true); 1668 if (ret) { 1669 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1670 return ret; 1671 } 1672 1673 smu_init_xgmi_plpd_mode(smu); 1674 1675 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1676 if (ret) { 1677 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1678 return ret; 1679 } 1680 bitmap_copy(feature->supported, 1681 (unsigned long *)&features_supported, 1682 feature->feature_num); 1683 1684 if (!smu_is_dpm_running(smu)) 1685 dev_info(adev->dev, "dpm has been disabled\n"); 1686 1687 /* 1688 * Set initialized values (get from vbios) to dpm tables context such as 1689 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1690 * type of clks. 1691 */ 1692 ret = smu_set_default_dpm_table(smu); 1693 if (ret) { 1694 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1695 return ret; 1696 } 1697 1698 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1699 pcie_gen = 3; 1700 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1701 pcie_gen = 2; 1702 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1703 pcie_gen = 1; 1704 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1705 pcie_gen = 0; 1706 1707 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1708 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1709 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1710 */ 1711 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1712 pcie_width = 6; 1713 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1714 pcie_width = 5; 1715 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1716 pcie_width = 4; 1717 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1718 pcie_width = 3; 1719 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1720 pcie_width = 2; 1721 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1722 pcie_width = 1; 1723 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1724 if (ret) { 1725 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1726 return ret; 1727 } 1728 1729 ret = smu_get_thermal_temperature_range(smu); 1730 if (ret) { 1731 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1732 return ret; 1733 } 1734 1735 ret = smu_enable_thermal_alert(smu); 1736 if (ret) { 1737 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1738 return ret; 1739 } 1740 1741 ret = smu_notify_display_change(smu); 1742 if (ret) { 1743 dev_err(adev->dev, "Failed to notify display change!\n"); 1744 return ret; 1745 } 1746 1747 /* 1748 * Set min deep sleep dce fclk with bootup value from vbios via 1749 * SetMinDeepSleepDcefclk MSG. 1750 */ 1751 ret = smu_set_min_dcef_deep_sleep(smu, 1752 smu->smu_table.boot_values.dcefclk / 100); 1753 if (ret) { 1754 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1755 return ret; 1756 } 1757 1758 /* Init wbrf support. Properly setup the notifier */ 1759 ret = smu_wbrf_init(smu); 1760 if (ret) 1761 dev_err(adev->dev, "Error during wbrf init call\n"); 1762 1763 return ret; 1764 } 1765 1766 static int smu_start_smc_engine(struct smu_context *smu) 1767 { 1768 struct amdgpu_device *adev = smu->adev; 1769 int ret = 0; 1770 1771 smu->smc_fw_state = SMU_FW_INIT; 1772 1773 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1774 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1775 if (smu->ppt_funcs->load_microcode) { 1776 ret = smu->ppt_funcs->load_microcode(smu); 1777 if (ret) 1778 return ret; 1779 } 1780 } 1781 } 1782 1783 if (smu->ppt_funcs->check_fw_status) { 1784 ret = smu->ppt_funcs->check_fw_status(smu); 1785 if (ret) { 1786 dev_err(adev->dev, "SMC is not ready\n"); 1787 return ret; 1788 } 1789 } 1790 1791 /* 1792 * Send msg GetDriverIfVersion to check if the return value is equal 1793 * with DRIVER_IF_VERSION of smc header. 1794 */ 1795 ret = smu_check_fw_version(smu); 1796 if (ret) 1797 return ret; 1798 1799 return ret; 1800 } 1801 1802 static int smu_hw_init(void *handle) 1803 { 1804 int ret; 1805 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1806 struct smu_context *smu = adev->powerplay.pp_handle; 1807 1808 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1809 smu->pm_enabled = false; 1810 return 0; 1811 } 1812 1813 ret = smu_start_smc_engine(smu); 1814 if (ret) { 1815 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1816 return ret; 1817 } 1818 1819 /* 1820 * Check whether wbrf is supported. This needs to be done 1821 * before SMU setup starts since part of SMU configuration 1822 * relies on this. 1823 */ 1824 smu_wbrf_support_check(smu); 1825 1826 if (smu->is_apu) { 1827 ret = smu_set_gfx_imu_enable(smu); 1828 if (ret) 1829 return ret; 1830 smu_dpm_set_vcn_enable(smu, true); 1831 smu_dpm_set_jpeg_enable(smu, true); 1832 smu_dpm_set_vpe_enable(smu, true); 1833 smu_dpm_set_umsch_mm_enable(smu, true); 1834 smu_set_mall_enable(smu); 1835 smu_set_gfx_cgpg(smu, true); 1836 } 1837 1838 if (!smu->pm_enabled) 1839 return 0; 1840 1841 ret = smu_get_driver_allowed_feature_mask(smu); 1842 if (ret) 1843 return ret; 1844 1845 ret = smu_smc_hw_setup(smu); 1846 if (ret) { 1847 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1848 return ret; 1849 } 1850 1851 /* 1852 * Move maximum sustainable clock retrieving here considering 1853 * 1. It is not needed on resume(from S3). 1854 * 2. DAL settings come between .hw_init and .late_init of SMU. 1855 * And DAL needs to know the maximum sustainable clocks. Thus 1856 * it cannot be put in .late_init(). 1857 */ 1858 ret = smu_init_max_sustainable_clocks(smu); 1859 if (ret) { 1860 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1861 return ret; 1862 } 1863 1864 adev->pm.dpm_enabled = true; 1865 1866 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1867 1868 return 0; 1869 } 1870 1871 static int smu_disable_dpms(struct smu_context *smu) 1872 { 1873 struct amdgpu_device *adev = smu->adev; 1874 int ret = 0; 1875 bool use_baco = !smu->is_apu && 1876 ((amdgpu_in_reset(adev) && 1877 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1878 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1879 1880 /* 1881 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1882 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1883 */ 1884 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1885 case IP_VERSION(13, 0, 0): 1886 case IP_VERSION(13, 0, 7): 1887 case IP_VERSION(13, 0, 10): 1888 case IP_VERSION(14, 0, 2): 1889 case IP_VERSION(14, 0, 3): 1890 return 0; 1891 default: 1892 break; 1893 } 1894 1895 /* 1896 * For custom pptable uploading, skip the DPM features 1897 * disable process on Navi1x ASICs. 1898 * - As the gfx related features are under control of 1899 * RLC on those ASICs. RLC reinitialization will be 1900 * needed to reenable them. That will cost much more 1901 * efforts. 1902 * 1903 * - SMU firmware can handle the DPM reenablement 1904 * properly. 1905 */ 1906 if (smu->uploading_custom_pp_table) { 1907 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1908 case IP_VERSION(11, 0, 0): 1909 case IP_VERSION(11, 0, 5): 1910 case IP_VERSION(11, 0, 9): 1911 case IP_VERSION(11, 0, 7): 1912 case IP_VERSION(11, 0, 11): 1913 case IP_VERSION(11, 5, 0): 1914 case IP_VERSION(11, 0, 12): 1915 case IP_VERSION(11, 0, 13): 1916 return 0; 1917 default: 1918 break; 1919 } 1920 } 1921 1922 /* 1923 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1924 * on BACO in. Driver involvement is unnecessary. 1925 */ 1926 if (use_baco) { 1927 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1928 case IP_VERSION(11, 0, 7): 1929 case IP_VERSION(11, 0, 0): 1930 case IP_VERSION(11, 0, 5): 1931 case IP_VERSION(11, 0, 9): 1932 case IP_VERSION(13, 0, 7): 1933 return 0; 1934 default: 1935 break; 1936 } 1937 } 1938 1939 /* 1940 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1941 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1942 */ 1943 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1944 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1945 return 0; 1946 1947 /* 1948 * For gpu reset, runpm and hibernation through BACO, 1949 * BACO feature has to be kept enabled. 1950 */ 1951 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1952 ret = smu_disable_all_features_with_exception(smu, 1953 SMU_FEATURE_BACO_BIT); 1954 if (ret) 1955 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1956 } else { 1957 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1958 if (!adev->scpm_enabled) { 1959 ret = smu_system_features_control(smu, false); 1960 if (ret) 1961 dev_err(adev->dev, "Failed to disable smu features.\n"); 1962 } 1963 } 1964 1965 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1966 * otherwise SMU will hang while interacting with RLC if RLC is halted 1967 * this is a WA for Vangogh asic which fix the SMU hang issue. 1968 */ 1969 ret = smu_notify_rlc_state(smu, false); 1970 if (ret) { 1971 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1972 return ret; 1973 } 1974 1975 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1976 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1977 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1978 adev->gfx.rlc.funcs->stop(adev); 1979 1980 return ret; 1981 } 1982 1983 static int smu_smc_hw_cleanup(struct smu_context *smu) 1984 { 1985 struct amdgpu_device *adev = smu->adev; 1986 int ret = 0; 1987 1988 smu_wbrf_fini(smu); 1989 1990 cancel_work_sync(&smu->throttling_logging_work); 1991 cancel_work_sync(&smu->interrupt_work); 1992 1993 ret = smu_disable_thermal_alert(smu); 1994 if (ret) { 1995 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1996 return ret; 1997 } 1998 1999 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2000 2001 ret = smu_disable_dpms(smu); 2002 if (ret) { 2003 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2004 return ret; 2005 } 2006 2007 return 0; 2008 } 2009 2010 static int smu_reset_mp1_state(struct smu_context *smu) 2011 { 2012 struct amdgpu_device *adev = smu->adev; 2013 int ret = 0; 2014 2015 if ((!adev->in_runpm) && (!adev->in_suspend) && 2016 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2017 IP_VERSION(13, 0, 10) && 2018 !amdgpu_device_has_display_hardware(adev)) 2019 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2020 2021 return ret; 2022 } 2023 2024 static int smu_hw_fini(void *handle) 2025 { 2026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2027 struct smu_context *smu = adev->powerplay.pp_handle; 2028 int ret; 2029 2030 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2031 return 0; 2032 2033 smu_dpm_set_vcn_enable(smu, false); 2034 smu_dpm_set_jpeg_enable(smu, false); 2035 smu_dpm_set_vpe_enable(smu, false); 2036 smu_dpm_set_umsch_mm_enable(smu, false); 2037 2038 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2039 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2040 2041 if (!smu->pm_enabled) 2042 return 0; 2043 2044 adev->pm.dpm_enabled = false; 2045 2046 ret = smu_smc_hw_cleanup(smu); 2047 if (ret) 2048 return ret; 2049 2050 ret = smu_reset_mp1_state(smu); 2051 if (ret) 2052 return ret; 2053 2054 return 0; 2055 } 2056 2057 static void smu_late_fini(void *handle) 2058 { 2059 struct amdgpu_device *adev = handle; 2060 struct smu_context *smu = adev->powerplay.pp_handle; 2061 2062 kfree(smu); 2063 } 2064 2065 static int smu_reset(struct smu_context *smu) 2066 { 2067 struct amdgpu_device *adev = smu->adev; 2068 int ret; 2069 2070 ret = smu_hw_fini(adev); 2071 if (ret) 2072 return ret; 2073 2074 ret = smu_hw_init(adev); 2075 if (ret) 2076 return ret; 2077 2078 ret = smu_late_init(adev); 2079 if (ret) 2080 return ret; 2081 2082 return 0; 2083 } 2084 2085 static int smu_suspend(void *handle) 2086 { 2087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2088 struct smu_context *smu = adev->powerplay.pp_handle; 2089 int ret; 2090 uint64_t count; 2091 2092 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2093 return 0; 2094 2095 if (!smu->pm_enabled) 2096 return 0; 2097 2098 adev->pm.dpm_enabled = false; 2099 2100 ret = smu_smc_hw_cleanup(smu); 2101 if (ret) 2102 return ret; 2103 2104 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2105 2106 smu_set_gfx_cgpg(smu, false); 2107 2108 /* 2109 * pwfw resets entrycount when device is suspended, so we save the 2110 * last value to be used when we resume to keep it consistent 2111 */ 2112 ret = smu_get_entrycount_gfxoff(smu, &count); 2113 if (!ret) 2114 adev->gfx.gfx_off_entrycount = count; 2115 2116 return 0; 2117 } 2118 2119 static int smu_resume(void *handle) 2120 { 2121 int ret; 2122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2123 struct smu_context *smu = adev->powerplay.pp_handle; 2124 2125 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2126 return 0; 2127 2128 if (!smu->pm_enabled) 2129 return 0; 2130 2131 dev_info(adev->dev, "SMU is resuming...\n"); 2132 2133 ret = smu_start_smc_engine(smu); 2134 if (ret) { 2135 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2136 return ret; 2137 } 2138 2139 ret = smu_smc_hw_setup(smu); 2140 if (ret) { 2141 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2142 return ret; 2143 } 2144 2145 ret = smu_set_gfx_imu_enable(smu); 2146 if (ret) 2147 return ret; 2148 2149 smu_set_gfx_cgpg(smu, true); 2150 2151 smu->disable_uclk_switch = 0; 2152 2153 adev->pm.dpm_enabled = true; 2154 2155 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2156 2157 return 0; 2158 } 2159 2160 static int smu_display_configuration_change(void *handle, 2161 const struct amd_pp_display_configuration *display_config) 2162 { 2163 struct smu_context *smu = handle; 2164 2165 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2166 return -EOPNOTSUPP; 2167 2168 if (!display_config) 2169 return -EINVAL; 2170 2171 smu_set_min_dcef_deep_sleep(smu, 2172 display_config->min_dcef_deep_sleep_set_clk / 100); 2173 2174 return 0; 2175 } 2176 2177 static int smu_set_clockgating_state(void *handle, 2178 enum amd_clockgating_state state) 2179 { 2180 return 0; 2181 } 2182 2183 static int smu_set_powergating_state(void *handle, 2184 enum amd_powergating_state state) 2185 { 2186 return 0; 2187 } 2188 2189 static int smu_enable_umd_pstate(void *handle, 2190 enum amd_dpm_forced_level *level) 2191 { 2192 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2193 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2194 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2195 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2196 2197 struct smu_context *smu = (struct smu_context*)(handle); 2198 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2199 2200 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2201 return -EINVAL; 2202 2203 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2204 /* enter umd pstate, save current level, disable gfx cg*/ 2205 if (*level & profile_mode_mask) { 2206 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2207 smu_gpo_control(smu, false); 2208 smu_gfx_ulv_control(smu, false); 2209 smu_deep_sleep_control(smu, false); 2210 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2211 } 2212 } else { 2213 /* exit umd pstate, restore level, enable gfx cg*/ 2214 if (!(*level & profile_mode_mask)) { 2215 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2216 *level = smu_dpm_ctx->saved_dpm_level; 2217 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2218 smu_deep_sleep_control(smu, true); 2219 smu_gfx_ulv_control(smu, true); 2220 smu_gpo_control(smu, true); 2221 } 2222 } 2223 2224 return 0; 2225 } 2226 2227 static int smu_bump_power_profile_mode(struct smu_context *smu, 2228 long *param, 2229 uint32_t param_size) 2230 { 2231 int ret = 0; 2232 2233 if (smu->ppt_funcs->set_power_profile_mode) 2234 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2235 2236 return ret; 2237 } 2238 2239 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2240 enum amd_dpm_forced_level level, 2241 bool skip_display_settings, 2242 bool init) 2243 { 2244 int ret = 0; 2245 int index = 0; 2246 long workload[1]; 2247 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2248 2249 if (!skip_display_settings) { 2250 ret = smu_display_config_changed(smu); 2251 if (ret) { 2252 dev_err(smu->adev->dev, "Failed to change display config!"); 2253 return ret; 2254 } 2255 } 2256 2257 ret = smu_apply_clocks_adjust_rules(smu); 2258 if (ret) { 2259 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2260 return ret; 2261 } 2262 2263 if (!skip_display_settings) { 2264 ret = smu_notify_smc_display_config(smu); 2265 if (ret) { 2266 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2267 return ret; 2268 } 2269 } 2270 2271 if (smu_dpm_ctx->dpm_level != level) { 2272 ret = smu_asic_set_performance_level(smu, level); 2273 if (ret) { 2274 dev_err(smu->adev->dev, "Failed to set performance level!"); 2275 return ret; 2276 } 2277 2278 /* update the saved copy */ 2279 smu_dpm_ctx->dpm_level = level; 2280 } 2281 2282 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2283 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2284 index = fls(smu->workload_mask); 2285 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2286 workload[0] = smu->workload_setting[index]; 2287 2288 if (init || smu->power_profile_mode != workload[0]) 2289 smu_bump_power_profile_mode(smu, workload, 0); 2290 } 2291 2292 return ret; 2293 } 2294 2295 static int smu_handle_task(struct smu_context *smu, 2296 enum amd_dpm_forced_level level, 2297 enum amd_pp_task task_id) 2298 { 2299 int ret = 0; 2300 2301 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2302 return -EOPNOTSUPP; 2303 2304 switch (task_id) { 2305 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2306 ret = smu_pre_display_config_changed(smu); 2307 if (ret) 2308 return ret; 2309 ret = smu_adjust_power_state_dynamic(smu, level, false, false); 2310 break; 2311 case AMD_PP_TASK_COMPLETE_INIT: 2312 ret = smu_adjust_power_state_dynamic(smu, level, true, true); 2313 break; 2314 case AMD_PP_TASK_READJUST_POWER_STATE: 2315 ret = smu_adjust_power_state_dynamic(smu, level, true, false); 2316 break; 2317 default: 2318 break; 2319 } 2320 2321 return ret; 2322 } 2323 2324 static int smu_handle_dpm_task(void *handle, 2325 enum amd_pp_task task_id, 2326 enum amd_pm_state_type *user_state) 2327 { 2328 struct smu_context *smu = handle; 2329 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2330 2331 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2332 2333 } 2334 2335 static int smu_switch_power_profile(void *handle, 2336 enum PP_SMC_POWER_PROFILE type, 2337 bool en) 2338 { 2339 struct smu_context *smu = handle; 2340 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2341 long workload[1]; 2342 uint32_t index; 2343 2344 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2345 return -EOPNOTSUPP; 2346 2347 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2348 return -EINVAL; 2349 2350 if (!en) { 2351 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2352 index = fls(smu->workload_mask); 2353 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2354 workload[0] = smu->workload_setting[index]; 2355 } else { 2356 smu->workload_mask |= (1 << smu->workload_prority[type]); 2357 index = fls(smu->workload_mask); 2358 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2359 workload[0] = smu->workload_setting[index]; 2360 } 2361 2362 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2363 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2364 smu_bump_power_profile_mode(smu, workload, 0); 2365 2366 return 0; 2367 } 2368 2369 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2370 { 2371 struct smu_context *smu = handle; 2372 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2373 2374 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2375 return -EOPNOTSUPP; 2376 2377 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2378 return -EINVAL; 2379 2380 return smu_dpm_ctx->dpm_level; 2381 } 2382 2383 static int smu_force_performance_level(void *handle, 2384 enum amd_dpm_forced_level level) 2385 { 2386 struct smu_context *smu = handle; 2387 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2388 int ret = 0; 2389 2390 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2391 return -EOPNOTSUPP; 2392 2393 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2394 return -EINVAL; 2395 2396 ret = smu_enable_umd_pstate(smu, &level); 2397 if (ret) 2398 return ret; 2399 2400 ret = smu_handle_task(smu, level, 2401 AMD_PP_TASK_READJUST_POWER_STATE); 2402 2403 /* reset user dpm clock state */ 2404 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2405 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2406 smu->user_dpm_profile.clk_dependency = 0; 2407 } 2408 2409 return ret; 2410 } 2411 2412 static int smu_set_display_count(void *handle, uint32_t count) 2413 { 2414 struct smu_context *smu = handle; 2415 2416 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2417 return -EOPNOTSUPP; 2418 2419 return smu_init_display_count(smu, count); 2420 } 2421 2422 static int smu_force_smuclk_levels(struct smu_context *smu, 2423 enum smu_clk_type clk_type, 2424 uint32_t mask) 2425 { 2426 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2427 int ret = 0; 2428 2429 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2430 return -EOPNOTSUPP; 2431 2432 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2433 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2434 return -EINVAL; 2435 } 2436 2437 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2438 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2439 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2440 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2441 smu_set_user_clk_dependencies(smu, clk_type); 2442 } 2443 } 2444 2445 return ret; 2446 } 2447 2448 static int smu_force_ppclk_levels(void *handle, 2449 enum pp_clock_type type, 2450 uint32_t mask) 2451 { 2452 struct smu_context *smu = handle; 2453 enum smu_clk_type clk_type; 2454 2455 switch (type) { 2456 case PP_SCLK: 2457 clk_type = SMU_SCLK; break; 2458 case PP_MCLK: 2459 clk_type = SMU_MCLK; break; 2460 case PP_PCIE: 2461 clk_type = SMU_PCIE; break; 2462 case PP_SOCCLK: 2463 clk_type = SMU_SOCCLK; break; 2464 case PP_FCLK: 2465 clk_type = SMU_FCLK; break; 2466 case PP_DCEFCLK: 2467 clk_type = SMU_DCEFCLK; break; 2468 case PP_VCLK: 2469 clk_type = SMU_VCLK; break; 2470 case PP_VCLK1: 2471 clk_type = SMU_VCLK1; break; 2472 case PP_DCLK: 2473 clk_type = SMU_DCLK; break; 2474 case PP_DCLK1: 2475 clk_type = SMU_DCLK1; break; 2476 case OD_SCLK: 2477 clk_type = SMU_OD_SCLK; break; 2478 case OD_MCLK: 2479 clk_type = SMU_OD_MCLK; break; 2480 case OD_VDDC_CURVE: 2481 clk_type = SMU_OD_VDDC_CURVE; break; 2482 case OD_RANGE: 2483 clk_type = SMU_OD_RANGE; break; 2484 default: 2485 return -EINVAL; 2486 } 2487 2488 return smu_force_smuclk_levels(smu, clk_type, mask); 2489 } 2490 2491 /* 2492 * On system suspending or resetting, the dpm_enabled 2493 * flag will be cleared. So that those SMU services which 2494 * are not supported will be gated. 2495 * However, the mp1 state setting should still be granted 2496 * even if the dpm_enabled cleared. 2497 */ 2498 static int smu_set_mp1_state(void *handle, 2499 enum pp_mp1_state mp1_state) 2500 { 2501 struct smu_context *smu = handle; 2502 int ret = 0; 2503 2504 if (!smu->pm_enabled) 2505 return -EOPNOTSUPP; 2506 2507 if (smu->ppt_funcs && 2508 smu->ppt_funcs->set_mp1_state) 2509 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2510 2511 return ret; 2512 } 2513 2514 static int smu_set_df_cstate(void *handle, 2515 enum pp_df_cstate state) 2516 { 2517 struct smu_context *smu = handle; 2518 int ret = 0; 2519 2520 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2521 return -EOPNOTSUPP; 2522 2523 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2524 return 0; 2525 2526 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2527 if (ret) 2528 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2529 2530 return ret; 2531 } 2532 2533 int smu_write_watermarks_table(struct smu_context *smu) 2534 { 2535 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2536 return -EOPNOTSUPP; 2537 2538 return smu_set_watermarks_table(smu, NULL); 2539 } 2540 2541 static int smu_set_watermarks_for_clock_ranges(void *handle, 2542 struct pp_smu_wm_range_sets *clock_ranges) 2543 { 2544 struct smu_context *smu = handle; 2545 2546 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2547 return -EOPNOTSUPP; 2548 2549 if (smu->disable_watermark) 2550 return 0; 2551 2552 return smu_set_watermarks_table(smu, clock_ranges); 2553 } 2554 2555 int smu_set_ac_dc(struct smu_context *smu) 2556 { 2557 int ret = 0; 2558 2559 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2560 return -EOPNOTSUPP; 2561 2562 /* controlled by firmware */ 2563 if (smu->dc_controlled_by_gpio) 2564 return 0; 2565 2566 ret = smu_set_power_source(smu, 2567 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2568 SMU_POWER_SOURCE_DC); 2569 if (ret) 2570 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2571 smu->adev->pm.ac_power ? "AC" : "DC"); 2572 2573 return ret; 2574 } 2575 2576 const struct amd_ip_funcs smu_ip_funcs = { 2577 .name = "smu", 2578 .early_init = smu_early_init, 2579 .late_init = smu_late_init, 2580 .sw_init = smu_sw_init, 2581 .sw_fini = smu_sw_fini, 2582 .hw_init = smu_hw_init, 2583 .hw_fini = smu_hw_fini, 2584 .late_fini = smu_late_fini, 2585 .suspend = smu_suspend, 2586 .resume = smu_resume, 2587 .is_idle = NULL, 2588 .check_soft_reset = NULL, 2589 .wait_for_idle = NULL, 2590 .soft_reset = NULL, 2591 .set_clockgating_state = smu_set_clockgating_state, 2592 .set_powergating_state = smu_set_powergating_state, 2593 }; 2594 2595 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2596 .type = AMD_IP_BLOCK_TYPE_SMC, 2597 .major = 11, 2598 .minor = 0, 2599 .rev = 0, 2600 .funcs = &smu_ip_funcs, 2601 }; 2602 2603 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2604 .type = AMD_IP_BLOCK_TYPE_SMC, 2605 .major = 12, 2606 .minor = 0, 2607 .rev = 0, 2608 .funcs = &smu_ip_funcs, 2609 }; 2610 2611 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2612 .type = AMD_IP_BLOCK_TYPE_SMC, 2613 .major = 13, 2614 .minor = 0, 2615 .rev = 0, 2616 .funcs = &smu_ip_funcs, 2617 }; 2618 2619 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2620 .type = AMD_IP_BLOCK_TYPE_SMC, 2621 .major = 14, 2622 .minor = 0, 2623 .rev = 0, 2624 .funcs = &smu_ip_funcs, 2625 }; 2626 2627 static int smu_load_microcode(void *handle) 2628 { 2629 struct smu_context *smu = handle; 2630 struct amdgpu_device *adev = smu->adev; 2631 int ret = 0; 2632 2633 if (!smu->pm_enabled) 2634 return -EOPNOTSUPP; 2635 2636 /* This should be used for non PSP loading */ 2637 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2638 return 0; 2639 2640 if (smu->ppt_funcs->load_microcode) { 2641 ret = smu->ppt_funcs->load_microcode(smu); 2642 if (ret) { 2643 dev_err(adev->dev, "Load microcode failed\n"); 2644 return ret; 2645 } 2646 } 2647 2648 if (smu->ppt_funcs->check_fw_status) { 2649 ret = smu->ppt_funcs->check_fw_status(smu); 2650 if (ret) { 2651 dev_err(adev->dev, "SMC is not ready\n"); 2652 return ret; 2653 } 2654 } 2655 2656 return ret; 2657 } 2658 2659 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2660 { 2661 int ret = 0; 2662 2663 if (smu->ppt_funcs->set_gfx_cgpg) 2664 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2665 2666 return ret; 2667 } 2668 2669 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2670 { 2671 struct smu_context *smu = handle; 2672 int ret = 0; 2673 2674 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2675 return -EOPNOTSUPP; 2676 2677 if (!smu->ppt_funcs->set_fan_speed_rpm) 2678 return -EOPNOTSUPP; 2679 2680 if (speed == U32_MAX) 2681 return -EINVAL; 2682 2683 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2684 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2685 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2686 smu->user_dpm_profile.fan_speed_rpm = speed; 2687 2688 /* Override custom PWM setting as they cannot co-exist */ 2689 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2690 smu->user_dpm_profile.fan_speed_pwm = 0; 2691 } 2692 2693 return ret; 2694 } 2695 2696 /** 2697 * smu_get_power_limit - Request one of the SMU Power Limits 2698 * 2699 * @handle: pointer to smu context 2700 * @limit: requested limit is written back to this variable 2701 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2702 * @pp_power_type: &pp_power_type type of power 2703 * Return: 0 on success, <0 on error 2704 * 2705 */ 2706 int smu_get_power_limit(void *handle, 2707 uint32_t *limit, 2708 enum pp_power_limit_level pp_limit_level, 2709 enum pp_power_type pp_power_type) 2710 { 2711 struct smu_context *smu = handle; 2712 struct amdgpu_device *adev = smu->adev; 2713 enum smu_ppt_limit_level limit_level; 2714 uint32_t limit_type; 2715 int ret = 0; 2716 2717 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2718 return -EOPNOTSUPP; 2719 2720 switch (pp_power_type) { 2721 case PP_PWR_TYPE_SUSTAINED: 2722 limit_type = SMU_DEFAULT_PPT_LIMIT; 2723 break; 2724 case PP_PWR_TYPE_FAST: 2725 limit_type = SMU_FAST_PPT_LIMIT; 2726 break; 2727 default: 2728 return -EOPNOTSUPP; 2729 } 2730 2731 switch (pp_limit_level) { 2732 case PP_PWR_LIMIT_CURRENT: 2733 limit_level = SMU_PPT_LIMIT_CURRENT; 2734 break; 2735 case PP_PWR_LIMIT_DEFAULT: 2736 limit_level = SMU_PPT_LIMIT_DEFAULT; 2737 break; 2738 case PP_PWR_LIMIT_MAX: 2739 limit_level = SMU_PPT_LIMIT_MAX; 2740 break; 2741 case PP_PWR_LIMIT_MIN: 2742 limit_level = SMU_PPT_LIMIT_MIN; 2743 break; 2744 default: 2745 return -EOPNOTSUPP; 2746 } 2747 2748 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2749 if (smu->ppt_funcs->get_ppt_limit) 2750 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2751 } else { 2752 switch (limit_level) { 2753 case SMU_PPT_LIMIT_CURRENT: 2754 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2755 case IP_VERSION(13, 0, 2): 2756 case IP_VERSION(13, 0, 6): 2757 case IP_VERSION(13, 0, 14): 2758 case IP_VERSION(11, 0, 7): 2759 case IP_VERSION(11, 0, 11): 2760 case IP_VERSION(11, 0, 12): 2761 case IP_VERSION(11, 0, 13): 2762 ret = smu_get_asic_power_limits(smu, 2763 &smu->current_power_limit, 2764 NULL, NULL, NULL); 2765 break; 2766 default: 2767 break; 2768 } 2769 *limit = smu->current_power_limit; 2770 break; 2771 case SMU_PPT_LIMIT_DEFAULT: 2772 *limit = smu->default_power_limit; 2773 break; 2774 case SMU_PPT_LIMIT_MAX: 2775 *limit = smu->max_power_limit; 2776 break; 2777 case SMU_PPT_LIMIT_MIN: 2778 *limit = smu->min_power_limit; 2779 break; 2780 default: 2781 return -EINVAL; 2782 } 2783 } 2784 2785 return ret; 2786 } 2787 2788 static int smu_set_power_limit(void *handle, uint32_t limit) 2789 { 2790 struct smu_context *smu = handle; 2791 uint32_t limit_type = limit >> 24; 2792 int ret = 0; 2793 2794 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2795 return -EOPNOTSUPP; 2796 2797 limit &= (1<<24)-1; 2798 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2799 if (smu->ppt_funcs->set_power_limit) 2800 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2801 2802 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2803 dev_err(smu->adev->dev, 2804 "New power limit (%d) is out of range [%d,%d]\n", 2805 limit, smu->min_power_limit, smu->max_power_limit); 2806 return -EINVAL; 2807 } 2808 2809 if (!limit) 2810 limit = smu->current_power_limit; 2811 2812 if (smu->ppt_funcs->set_power_limit) { 2813 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2814 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2815 smu->user_dpm_profile.power_limit = limit; 2816 } 2817 2818 return ret; 2819 } 2820 2821 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2822 { 2823 int ret = 0; 2824 2825 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2826 return -EOPNOTSUPP; 2827 2828 if (smu->ppt_funcs->print_clk_levels) 2829 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2830 2831 return ret; 2832 } 2833 2834 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2835 { 2836 enum smu_clk_type clk_type; 2837 2838 switch (type) { 2839 case PP_SCLK: 2840 clk_type = SMU_SCLK; break; 2841 case PP_MCLK: 2842 clk_type = SMU_MCLK; break; 2843 case PP_PCIE: 2844 clk_type = SMU_PCIE; break; 2845 case PP_SOCCLK: 2846 clk_type = SMU_SOCCLK; break; 2847 case PP_FCLK: 2848 clk_type = SMU_FCLK; break; 2849 case PP_DCEFCLK: 2850 clk_type = SMU_DCEFCLK; break; 2851 case PP_VCLK: 2852 clk_type = SMU_VCLK; break; 2853 case PP_VCLK1: 2854 clk_type = SMU_VCLK1; break; 2855 case PP_DCLK: 2856 clk_type = SMU_DCLK; break; 2857 case PP_DCLK1: 2858 clk_type = SMU_DCLK1; break; 2859 case OD_SCLK: 2860 clk_type = SMU_OD_SCLK; break; 2861 case OD_MCLK: 2862 clk_type = SMU_OD_MCLK; break; 2863 case OD_VDDC_CURVE: 2864 clk_type = SMU_OD_VDDC_CURVE; break; 2865 case OD_RANGE: 2866 clk_type = SMU_OD_RANGE; break; 2867 case OD_VDDGFX_OFFSET: 2868 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2869 case OD_CCLK: 2870 clk_type = SMU_OD_CCLK; break; 2871 case OD_FAN_CURVE: 2872 clk_type = SMU_OD_FAN_CURVE; break; 2873 case OD_ACOUSTIC_LIMIT: 2874 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2875 case OD_ACOUSTIC_TARGET: 2876 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2877 case OD_FAN_TARGET_TEMPERATURE: 2878 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2879 case OD_FAN_MINIMUM_PWM: 2880 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2881 default: 2882 clk_type = SMU_CLK_COUNT; break; 2883 } 2884 2885 return clk_type; 2886 } 2887 2888 static int smu_print_ppclk_levels(void *handle, 2889 enum pp_clock_type type, 2890 char *buf) 2891 { 2892 struct smu_context *smu = handle; 2893 enum smu_clk_type clk_type; 2894 2895 clk_type = smu_convert_to_smuclk(type); 2896 if (clk_type == SMU_CLK_COUNT) 2897 return -EINVAL; 2898 2899 return smu_print_smuclk_levels(smu, clk_type, buf); 2900 } 2901 2902 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2903 { 2904 struct smu_context *smu = handle; 2905 enum smu_clk_type clk_type; 2906 2907 clk_type = smu_convert_to_smuclk(type); 2908 if (clk_type == SMU_CLK_COUNT) 2909 return -EINVAL; 2910 2911 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2912 return -EOPNOTSUPP; 2913 2914 if (!smu->ppt_funcs->emit_clk_levels) 2915 return -ENOENT; 2916 2917 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2918 2919 } 2920 2921 static int smu_od_edit_dpm_table(void *handle, 2922 enum PP_OD_DPM_TABLE_COMMAND type, 2923 long *input, uint32_t size) 2924 { 2925 struct smu_context *smu = handle; 2926 int ret = 0; 2927 2928 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2929 return -EOPNOTSUPP; 2930 2931 if (smu->ppt_funcs->od_edit_dpm_table) { 2932 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2933 } 2934 2935 return ret; 2936 } 2937 2938 static int smu_read_sensor(void *handle, 2939 int sensor, 2940 void *data, 2941 int *size_arg) 2942 { 2943 struct smu_context *smu = handle; 2944 struct smu_umd_pstate_table *pstate_table = 2945 &smu->pstate_table; 2946 int ret = 0; 2947 uint32_t *size, size_val; 2948 2949 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2950 return -EOPNOTSUPP; 2951 2952 if (!data || !size_arg) 2953 return -EINVAL; 2954 2955 size_val = *size_arg; 2956 size = &size_val; 2957 2958 if (smu->ppt_funcs->read_sensor) 2959 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2960 goto unlock; 2961 2962 switch (sensor) { 2963 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2964 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2965 *size = 4; 2966 break; 2967 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2968 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2969 *size = 4; 2970 break; 2971 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2972 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2973 *size = 4; 2974 break; 2975 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2976 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2977 *size = 4; 2978 break; 2979 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2980 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2981 *size = 8; 2982 break; 2983 case AMDGPU_PP_SENSOR_UVD_POWER: 2984 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2985 *size = 4; 2986 break; 2987 case AMDGPU_PP_SENSOR_VCE_POWER: 2988 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2989 *size = 4; 2990 break; 2991 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2992 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2993 *size = 4; 2994 break; 2995 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2996 *(uint32_t *)data = 0; 2997 *size = 4; 2998 break; 2999 default: 3000 *size = 0; 3001 ret = -EOPNOTSUPP; 3002 break; 3003 } 3004 3005 unlock: 3006 // assign uint32_t to int 3007 *size_arg = size_val; 3008 3009 return ret; 3010 } 3011 3012 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3013 { 3014 int ret = -EOPNOTSUPP; 3015 struct smu_context *smu = handle; 3016 3017 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3018 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3019 3020 return ret; 3021 } 3022 3023 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3024 { 3025 int ret = -EOPNOTSUPP; 3026 struct smu_context *smu = handle; 3027 3028 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3029 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3030 3031 return ret; 3032 } 3033 3034 static int smu_get_power_profile_mode(void *handle, char *buf) 3035 { 3036 struct smu_context *smu = handle; 3037 3038 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3039 !smu->ppt_funcs->get_power_profile_mode) 3040 return -EOPNOTSUPP; 3041 if (!buf) 3042 return -EINVAL; 3043 3044 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3045 } 3046 3047 static int smu_set_power_profile_mode(void *handle, 3048 long *param, 3049 uint32_t param_size) 3050 { 3051 struct smu_context *smu = handle; 3052 3053 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3054 !smu->ppt_funcs->set_power_profile_mode) 3055 return -EOPNOTSUPP; 3056 3057 return smu_bump_power_profile_mode(smu, param, param_size); 3058 } 3059 3060 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3061 { 3062 struct smu_context *smu = handle; 3063 3064 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3065 return -EOPNOTSUPP; 3066 3067 if (!smu->ppt_funcs->get_fan_control_mode) 3068 return -EOPNOTSUPP; 3069 3070 if (!fan_mode) 3071 return -EINVAL; 3072 3073 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3074 3075 return 0; 3076 } 3077 3078 static int smu_set_fan_control_mode(void *handle, u32 value) 3079 { 3080 struct smu_context *smu = handle; 3081 int ret = 0; 3082 3083 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3084 return -EOPNOTSUPP; 3085 3086 if (!smu->ppt_funcs->set_fan_control_mode) 3087 return -EOPNOTSUPP; 3088 3089 if (value == U32_MAX) 3090 return -EINVAL; 3091 3092 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3093 if (ret) 3094 goto out; 3095 3096 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3097 smu->user_dpm_profile.fan_mode = value; 3098 3099 /* reset user dpm fan speed */ 3100 if (value != AMD_FAN_CTRL_MANUAL) { 3101 smu->user_dpm_profile.fan_speed_pwm = 0; 3102 smu->user_dpm_profile.fan_speed_rpm = 0; 3103 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3104 } 3105 } 3106 3107 out: 3108 return ret; 3109 } 3110 3111 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3112 { 3113 struct smu_context *smu = handle; 3114 int ret = 0; 3115 3116 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3117 return -EOPNOTSUPP; 3118 3119 if (!smu->ppt_funcs->get_fan_speed_pwm) 3120 return -EOPNOTSUPP; 3121 3122 if (!speed) 3123 return -EINVAL; 3124 3125 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3126 3127 return ret; 3128 } 3129 3130 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3131 { 3132 struct smu_context *smu = handle; 3133 int ret = 0; 3134 3135 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3136 return -EOPNOTSUPP; 3137 3138 if (!smu->ppt_funcs->set_fan_speed_pwm) 3139 return -EOPNOTSUPP; 3140 3141 if (speed == U32_MAX) 3142 return -EINVAL; 3143 3144 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3145 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3146 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3147 smu->user_dpm_profile.fan_speed_pwm = speed; 3148 3149 /* Override custom RPM setting as they cannot co-exist */ 3150 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3151 smu->user_dpm_profile.fan_speed_rpm = 0; 3152 } 3153 3154 return ret; 3155 } 3156 3157 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3158 { 3159 struct smu_context *smu = handle; 3160 int ret = 0; 3161 3162 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3163 return -EOPNOTSUPP; 3164 3165 if (!smu->ppt_funcs->get_fan_speed_rpm) 3166 return -EOPNOTSUPP; 3167 3168 if (!speed) 3169 return -EINVAL; 3170 3171 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3172 3173 return ret; 3174 } 3175 3176 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3177 { 3178 struct smu_context *smu = handle; 3179 3180 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3181 return -EOPNOTSUPP; 3182 3183 return smu_set_min_dcef_deep_sleep(smu, clk); 3184 } 3185 3186 static int smu_get_clock_by_type_with_latency(void *handle, 3187 enum amd_pp_clock_type type, 3188 struct pp_clock_levels_with_latency *clocks) 3189 { 3190 struct smu_context *smu = handle; 3191 enum smu_clk_type clk_type; 3192 int ret = 0; 3193 3194 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3195 return -EOPNOTSUPP; 3196 3197 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3198 switch (type) { 3199 case amd_pp_sys_clock: 3200 clk_type = SMU_GFXCLK; 3201 break; 3202 case amd_pp_mem_clock: 3203 clk_type = SMU_MCLK; 3204 break; 3205 case amd_pp_dcef_clock: 3206 clk_type = SMU_DCEFCLK; 3207 break; 3208 case amd_pp_disp_clock: 3209 clk_type = SMU_DISPCLK; 3210 break; 3211 default: 3212 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3213 return -EINVAL; 3214 } 3215 3216 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3217 } 3218 3219 return ret; 3220 } 3221 3222 static int smu_display_clock_voltage_request(void *handle, 3223 struct pp_display_clock_request *clock_req) 3224 { 3225 struct smu_context *smu = handle; 3226 int ret = 0; 3227 3228 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3229 return -EOPNOTSUPP; 3230 3231 if (smu->ppt_funcs->display_clock_voltage_request) 3232 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3233 3234 return ret; 3235 } 3236 3237 3238 static int smu_display_disable_memory_clock_switch(void *handle, 3239 bool disable_memory_clock_switch) 3240 { 3241 struct smu_context *smu = handle; 3242 int ret = -EINVAL; 3243 3244 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3245 return -EOPNOTSUPP; 3246 3247 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3248 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3249 3250 return ret; 3251 } 3252 3253 static int smu_set_xgmi_pstate(void *handle, 3254 uint32_t pstate) 3255 { 3256 struct smu_context *smu = handle; 3257 int ret = 0; 3258 3259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3260 return -EOPNOTSUPP; 3261 3262 if (smu->ppt_funcs->set_xgmi_pstate) 3263 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3264 3265 if (ret) 3266 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3267 3268 return ret; 3269 } 3270 3271 static int smu_get_baco_capability(void *handle) 3272 { 3273 struct smu_context *smu = handle; 3274 3275 if (!smu->pm_enabled) 3276 return false; 3277 3278 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3279 return false; 3280 3281 return smu->ppt_funcs->get_bamaco_support(smu); 3282 } 3283 3284 static int smu_baco_set_state(void *handle, int state) 3285 { 3286 struct smu_context *smu = handle; 3287 int ret = 0; 3288 3289 if (!smu->pm_enabled) 3290 return -EOPNOTSUPP; 3291 3292 if (state == 0) { 3293 if (smu->ppt_funcs->baco_exit) 3294 ret = smu->ppt_funcs->baco_exit(smu); 3295 } else if (state == 1) { 3296 if (smu->ppt_funcs->baco_enter) 3297 ret = smu->ppt_funcs->baco_enter(smu); 3298 } else { 3299 return -EINVAL; 3300 } 3301 3302 if (ret) 3303 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3304 (state)?"enter":"exit"); 3305 3306 return ret; 3307 } 3308 3309 bool smu_mode1_reset_is_support(struct smu_context *smu) 3310 { 3311 bool ret = false; 3312 3313 if (!smu->pm_enabled) 3314 return false; 3315 3316 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3317 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3318 3319 return ret; 3320 } 3321 3322 bool smu_mode2_reset_is_support(struct smu_context *smu) 3323 { 3324 bool ret = false; 3325 3326 if (!smu->pm_enabled) 3327 return false; 3328 3329 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3330 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3331 3332 return ret; 3333 } 3334 3335 int smu_mode1_reset(struct smu_context *smu) 3336 { 3337 int ret = 0; 3338 3339 if (!smu->pm_enabled) 3340 return -EOPNOTSUPP; 3341 3342 if (smu->ppt_funcs->mode1_reset) 3343 ret = smu->ppt_funcs->mode1_reset(smu); 3344 3345 return ret; 3346 } 3347 3348 static int smu_mode2_reset(void *handle) 3349 { 3350 struct smu_context *smu = handle; 3351 int ret = 0; 3352 3353 if (!smu->pm_enabled) 3354 return -EOPNOTSUPP; 3355 3356 if (smu->ppt_funcs->mode2_reset) 3357 ret = smu->ppt_funcs->mode2_reset(smu); 3358 3359 if (ret) 3360 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3361 3362 return ret; 3363 } 3364 3365 static int smu_enable_gfx_features(void *handle) 3366 { 3367 struct smu_context *smu = handle; 3368 int ret = 0; 3369 3370 if (!smu->pm_enabled) 3371 return -EOPNOTSUPP; 3372 3373 if (smu->ppt_funcs->enable_gfx_features) 3374 ret = smu->ppt_funcs->enable_gfx_features(smu); 3375 3376 if (ret) 3377 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3378 3379 return ret; 3380 } 3381 3382 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3383 struct pp_smu_nv_clock_table *max_clocks) 3384 { 3385 struct smu_context *smu = handle; 3386 int ret = 0; 3387 3388 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3389 return -EOPNOTSUPP; 3390 3391 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3392 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3393 3394 return ret; 3395 } 3396 3397 static int smu_get_uclk_dpm_states(void *handle, 3398 unsigned int *clock_values_in_khz, 3399 unsigned int *num_states) 3400 { 3401 struct smu_context *smu = handle; 3402 int ret = 0; 3403 3404 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3405 return -EOPNOTSUPP; 3406 3407 if (smu->ppt_funcs->get_uclk_dpm_states) 3408 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3409 3410 return ret; 3411 } 3412 3413 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3414 { 3415 struct smu_context *smu = handle; 3416 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3417 3418 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3419 return -EOPNOTSUPP; 3420 3421 if (smu->ppt_funcs->get_current_power_state) 3422 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3423 3424 return pm_state; 3425 } 3426 3427 static int smu_get_dpm_clock_table(void *handle, 3428 struct dpm_clocks *clock_table) 3429 { 3430 struct smu_context *smu = handle; 3431 int ret = 0; 3432 3433 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3434 return -EOPNOTSUPP; 3435 3436 if (smu->ppt_funcs->get_dpm_clock_table) 3437 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3438 3439 return ret; 3440 } 3441 3442 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3443 { 3444 struct smu_context *smu = handle; 3445 3446 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3447 return -EOPNOTSUPP; 3448 3449 if (!smu->ppt_funcs->get_gpu_metrics) 3450 return -EOPNOTSUPP; 3451 3452 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3453 } 3454 3455 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3456 size_t size) 3457 { 3458 struct smu_context *smu = handle; 3459 3460 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3461 return -EOPNOTSUPP; 3462 3463 if (!smu->ppt_funcs->get_pm_metrics) 3464 return -EOPNOTSUPP; 3465 3466 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3467 } 3468 3469 static int smu_enable_mgpu_fan_boost(void *handle) 3470 { 3471 struct smu_context *smu = handle; 3472 int ret = 0; 3473 3474 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3475 return -EOPNOTSUPP; 3476 3477 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3478 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3479 3480 return ret; 3481 } 3482 3483 static int smu_gfx_state_change_set(void *handle, 3484 uint32_t state) 3485 { 3486 struct smu_context *smu = handle; 3487 int ret = 0; 3488 3489 if (smu->ppt_funcs->gfx_state_change_set) 3490 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3491 3492 return ret; 3493 } 3494 3495 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3496 { 3497 int ret = 0; 3498 3499 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3500 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3501 3502 return ret; 3503 } 3504 3505 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3506 { 3507 int ret = -EOPNOTSUPP; 3508 3509 if (smu->ppt_funcs && 3510 smu->ppt_funcs->get_ecc_info) 3511 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3512 3513 return ret; 3514 3515 } 3516 3517 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3518 { 3519 struct smu_context *smu = handle; 3520 struct smu_table_context *smu_table = &smu->smu_table; 3521 struct smu_table *memory_pool = &smu_table->memory_pool; 3522 3523 if (!addr || !size) 3524 return -EINVAL; 3525 3526 *addr = NULL; 3527 *size = 0; 3528 if (memory_pool->bo) { 3529 *addr = memory_pool->cpu_addr; 3530 *size = memory_pool->size; 3531 } 3532 3533 return 0; 3534 } 3535 3536 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3537 size_t *size) 3538 { 3539 size_t offset = *size; 3540 int level; 3541 3542 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3543 if (level == policy->current_level) 3544 offset += sysfs_emit_at(sysbuf, offset, 3545 "%d : %s*\n", level, 3546 policy->desc->get_desc(policy, level)); 3547 else 3548 offset += sysfs_emit_at(sysbuf, offset, 3549 "%d : %s\n", level, 3550 policy->desc->get_desc(policy, level)); 3551 } 3552 3553 *size = offset; 3554 } 3555 3556 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3557 enum pp_pm_policy p_type, char *sysbuf) 3558 { 3559 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3560 struct smu_dpm_policy_ctxt *policy_ctxt; 3561 struct smu_dpm_policy *dpm_policy; 3562 size_t offset = 0; 3563 3564 policy_ctxt = dpm_ctxt->dpm_policies; 3565 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3566 !policy_ctxt->policy_mask) 3567 return -EOPNOTSUPP; 3568 3569 if (p_type == PP_PM_POLICY_NONE) 3570 return -EINVAL; 3571 3572 dpm_policy = smu_get_pm_policy(smu, p_type); 3573 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3574 return -ENOENT; 3575 3576 if (!sysbuf) 3577 return -EINVAL; 3578 3579 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3580 3581 return offset; 3582 } 3583 3584 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3585 enum pp_pm_policy p_type) 3586 { 3587 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3588 struct smu_dpm_policy_ctxt *policy_ctxt; 3589 int i; 3590 3591 policy_ctxt = dpm_ctxt->dpm_policies; 3592 if (!policy_ctxt) 3593 return NULL; 3594 3595 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3596 if (policy_ctxt->policies[i].policy_type == p_type) 3597 return &policy_ctxt->policies[i]; 3598 } 3599 3600 return NULL; 3601 } 3602 3603 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3604 int level) 3605 { 3606 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3607 struct smu_dpm_policy *dpm_policy = NULL; 3608 struct smu_dpm_policy_ctxt *policy_ctxt; 3609 int ret = -EOPNOTSUPP; 3610 3611 policy_ctxt = dpm_ctxt->dpm_policies; 3612 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3613 !policy_ctxt->policy_mask) 3614 return ret; 3615 3616 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3617 return -EINVAL; 3618 3619 dpm_policy = smu_get_pm_policy(smu, p_type); 3620 3621 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3622 return ret; 3623 3624 if (dpm_policy->current_level == level) 3625 return 0; 3626 3627 ret = dpm_policy->set_policy(smu, level); 3628 3629 if (!ret) 3630 dpm_policy->current_level = level; 3631 3632 return ret; 3633 } 3634 3635 static const struct amd_pm_funcs swsmu_pm_funcs = { 3636 /* export for sysfs */ 3637 .set_fan_control_mode = smu_set_fan_control_mode, 3638 .get_fan_control_mode = smu_get_fan_control_mode, 3639 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3640 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3641 .force_clock_level = smu_force_ppclk_levels, 3642 .print_clock_levels = smu_print_ppclk_levels, 3643 .emit_clock_levels = smu_emit_ppclk_levels, 3644 .force_performance_level = smu_force_performance_level, 3645 .read_sensor = smu_read_sensor, 3646 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3647 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3648 .get_performance_level = smu_get_performance_level, 3649 .get_current_power_state = smu_get_current_power_state, 3650 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3651 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3652 .get_pp_num_states = smu_get_power_num_states, 3653 .get_pp_table = smu_sys_get_pp_table, 3654 .set_pp_table = smu_sys_set_pp_table, 3655 .switch_power_profile = smu_switch_power_profile, 3656 /* export to amdgpu */ 3657 .dispatch_tasks = smu_handle_dpm_task, 3658 .load_firmware = smu_load_microcode, 3659 .set_powergating_by_smu = smu_dpm_set_power_gate, 3660 .set_power_limit = smu_set_power_limit, 3661 .get_power_limit = smu_get_power_limit, 3662 .get_power_profile_mode = smu_get_power_profile_mode, 3663 .set_power_profile_mode = smu_set_power_profile_mode, 3664 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3665 .set_mp1_state = smu_set_mp1_state, 3666 .gfx_state_change_set = smu_gfx_state_change_set, 3667 /* export to DC */ 3668 .get_sclk = smu_get_sclk, 3669 .get_mclk = smu_get_mclk, 3670 .display_configuration_change = smu_display_configuration_change, 3671 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3672 .display_clock_voltage_request = smu_display_clock_voltage_request, 3673 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3674 .set_active_display_count = smu_set_display_count, 3675 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3676 .get_asic_baco_capability = smu_get_baco_capability, 3677 .set_asic_baco_state = smu_baco_set_state, 3678 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3679 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3680 .asic_reset_mode_2 = smu_mode2_reset, 3681 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3682 .set_df_cstate = smu_set_df_cstate, 3683 .set_xgmi_pstate = smu_set_xgmi_pstate, 3684 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3685 .get_pm_metrics = smu_sys_get_pm_metrics, 3686 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3687 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3688 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3689 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3690 .get_dpm_clock_table = smu_get_dpm_clock_table, 3691 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3692 }; 3693 3694 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3695 uint64_t event_arg) 3696 { 3697 int ret = -EINVAL; 3698 3699 if (smu->ppt_funcs->wait_for_event) 3700 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3701 3702 return ret; 3703 } 3704 3705 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3706 { 3707 3708 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3709 return -EOPNOTSUPP; 3710 3711 /* Confirm the buffer allocated is of correct size */ 3712 if (size != smu->stb_context.stb_buf_size) 3713 return -EINVAL; 3714 3715 /* 3716 * No need to lock smu mutex as we access STB directly through MMIO 3717 * and not going through SMU messaging route (for now at least). 3718 * For registers access rely on implementation internal locking. 3719 */ 3720 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3721 } 3722 3723 #if defined(CONFIG_DEBUG_FS) 3724 3725 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3726 { 3727 struct amdgpu_device *adev = filp->f_inode->i_private; 3728 struct smu_context *smu = adev->powerplay.pp_handle; 3729 unsigned char *buf; 3730 int r; 3731 3732 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3733 if (!buf) 3734 return -ENOMEM; 3735 3736 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3737 if (r) 3738 goto out; 3739 3740 filp->private_data = buf; 3741 3742 return 0; 3743 3744 out: 3745 kvfree(buf); 3746 return r; 3747 } 3748 3749 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3750 loff_t *pos) 3751 { 3752 struct amdgpu_device *adev = filp->f_inode->i_private; 3753 struct smu_context *smu = adev->powerplay.pp_handle; 3754 3755 3756 if (!filp->private_data) 3757 return -EINVAL; 3758 3759 return simple_read_from_buffer(buf, 3760 size, 3761 pos, filp->private_data, 3762 smu->stb_context.stb_buf_size); 3763 } 3764 3765 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3766 { 3767 kvfree(filp->private_data); 3768 filp->private_data = NULL; 3769 3770 return 0; 3771 } 3772 3773 /* 3774 * We have to define not only read method but also 3775 * open and release because .read takes up to PAGE_SIZE 3776 * data each time so and so is invoked multiple times. 3777 * We allocate the STB buffer in .open and release it 3778 * in .release 3779 */ 3780 static const struct file_operations smu_stb_debugfs_fops = { 3781 .owner = THIS_MODULE, 3782 .open = smu_stb_debugfs_open, 3783 .read = smu_stb_debugfs_read, 3784 .release = smu_stb_debugfs_release, 3785 .llseek = default_llseek, 3786 }; 3787 3788 #endif 3789 3790 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3791 { 3792 #if defined(CONFIG_DEBUG_FS) 3793 3794 struct smu_context *smu = adev->powerplay.pp_handle; 3795 3796 if (!smu || (!smu->stb_context.stb_buf_size)) 3797 return; 3798 3799 debugfs_create_file_size("amdgpu_smu_stb_dump", 3800 S_IRUSR, 3801 adev_to_drm(adev)->primary->debugfs_root, 3802 adev, 3803 &smu_stb_debugfs_fops, 3804 smu->stb_context.stb_buf_size); 3805 #endif 3806 } 3807 3808 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3809 { 3810 int ret = 0; 3811 3812 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3813 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3814 3815 return ret; 3816 } 3817 3818 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3819 { 3820 int ret = 0; 3821 3822 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3823 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3824 3825 return ret; 3826 } 3827 3828 int smu_send_rma_reason(struct smu_context *smu) 3829 { 3830 int ret = 0; 3831 3832 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3833 ret = smu->ppt_funcs->send_rma_reason(smu); 3834 3835 return ret; 3836 } 3837