1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/reboot.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "smu_internal.h" 32 #include "atom.h" 33 #include "arcturus_ppt.h" 34 #include "navi10_ppt.h" 35 #include "sienna_cichlid_ppt.h" 36 #include "renoir_ppt.h" 37 #include "vangogh_ppt.h" 38 #include "aldebaran_ppt.h" 39 #include "yellow_carp_ppt.h" 40 #include "cyan_skillfish_ppt.h" 41 #include "smu_v13_0_0_ppt.h" 42 #include "smu_v13_0_4_ppt.h" 43 #include "smu_v13_0_5_ppt.h" 44 #include "smu_v13_0_6_ppt.h" 45 #include "smu_v13_0_7_ppt.h" 46 #include "smu_v14_0_0_ppt.h" 47 #include "amd_pcie.h" 48 49 /* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54 #undef pr_err 55 #undef pr_warn 56 #undef pr_info 57 #undef pr_debug 58 59 static const struct amd_pm_funcs swsmu_pm_funcs; 60 static int smu_force_smuclk_levels(struct smu_context *smu, 61 enum smu_clk_type clk_type, 62 uint32_t mask); 63 static int smu_handle_task(struct smu_context *smu, 64 enum amd_dpm_forced_level level, 65 enum amd_pp_task task_id); 66 static int smu_reset(struct smu_context *smu); 67 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 68 static int smu_set_fan_control_mode(void *handle, u32 value); 69 static int smu_set_power_limit(void *handle, uint32_t limit); 70 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 71 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 72 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 73 74 static int smu_sys_get_pp_feature_mask(void *handle, 75 char *buf) 76 { 77 struct smu_context *smu = handle; 78 79 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 80 return -EOPNOTSUPP; 81 82 return smu_get_pp_feature_mask(smu, buf); 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 90 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 91 return -EOPNOTSUPP; 92 93 return smu_set_pp_feature_mask(smu, new_mask); 94 } 95 96 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 97 { 98 if (!smu->ppt_funcs->set_gfx_off_residency) 99 return -EINVAL; 100 101 return smu_set_gfx_off_residency(smu, value); 102 } 103 104 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 105 { 106 if (!smu->ppt_funcs->get_gfx_off_residency) 107 return -EINVAL; 108 109 return smu_get_gfx_off_residency(smu, value); 110 } 111 112 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 113 { 114 if (!smu->ppt_funcs->get_gfx_off_entrycount) 115 return -EINVAL; 116 117 return smu_get_gfx_off_entrycount(smu, value); 118 } 119 120 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 121 { 122 if (!smu->ppt_funcs->get_gfx_off_status) 123 return -EINVAL; 124 125 *value = smu_get_gfx_off_status(smu); 126 127 return 0; 128 } 129 130 int smu_set_soft_freq_range(struct smu_context *smu, 131 enum smu_clk_type clk_type, 132 uint32_t min, 133 uint32_t max) 134 { 135 int ret = 0; 136 137 if (smu->ppt_funcs->set_soft_freq_limited_range) 138 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 139 clk_type, 140 min, 141 max); 142 143 return ret; 144 } 145 146 int smu_get_dpm_freq_range(struct smu_context *smu, 147 enum smu_clk_type clk_type, 148 uint32_t *min, 149 uint32_t *max) 150 { 151 int ret = -ENOTSUPP; 152 153 if (!min && !max) 154 return -EINVAL; 155 156 if (smu->ppt_funcs->get_dpm_ultimate_freq) 157 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 158 clk_type, 159 min, 160 max); 161 162 return ret; 163 } 164 165 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 166 { 167 int ret = 0; 168 struct amdgpu_device *adev = smu->adev; 169 170 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 171 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 172 if (ret) 173 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 174 } 175 return ret; 176 } 177 178 static u32 smu_get_mclk(void *handle, bool low) 179 { 180 struct smu_context *smu = handle; 181 uint32_t clk_freq; 182 int ret = 0; 183 184 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 185 low ? &clk_freq : NULL, 186 !low ? &clk_freq : NULL); 187 if (ret) 188 return 0; 189 return clk_freq * 100; 190 } 191 192 static u32 smu_get_sclk(void *handle, bool low) 193 { 194 struct smu_context *smu = handle; 195 uint32_t clk_freq; 196 int ret = 0; 197 198 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 199 low ? &clk_freq : NULL, 200 !low ? &clk_freq : NULL); 201 if (ret) 202 return 0; 203 return clk_freq * 100; 204 } 205 206 static int smu_set_gfx_imu_enable(struct smu_context *smu) 207 { 208 struct amdgpu_device *adev = smu->adev; 209 210 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 211 return 0; 212 213 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 214 return 0; 215 216 return smu_set_gfx_power_up_by_imu(smu); 217 } 218 219 static bool is_vcn_enabled(struct amdgpu_device *adev) 220 { 221 int i; 222 223 for (i = 0; i < adev->num_ip_blocks; i++) { 224 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 225 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 226 !adev->ip_blocks[i].status.valid) 227 return false; 228 } 229 230 return true; 231 } 232 233 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 234 bool enable) 235 { 236 struct smu_power_context *smu_power = &smu->smu_power; 237 struct smu_power_gate *power_gate = &smu_power->power_gate; 238 int ret = 0; 239 240 /* 241 * don't poweron vcn/jpeg when they are skipped. 242 */ 243 if (!is_vcn_enabled(smu->adev)) 244 return 0; 245 246 if (!smu->ppt_funcs->dpm_set_vcn_enable) 247 return 0; 248 249 if (atomic_read(&power_gate->vcn_gated) ^ enable) 250 return 0; 251 252 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 253 if (!ret) 254 atomic_set(&power_gate->vcn_gated, !enable); 255 256 return ret; 257 } 258 259 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 260 bool enable) 261 { 262 struct smu_power_context *smu_power = &smu->smu_power; 263 struct smu_power_gate *power_gate = &smu_power->power_gate; 264 int ret = 0; 265 266 if (!is_vcn_enabled(smu->adev)) 267 return 0; 268 269 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 270 return 0; 271 272 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 273 return 0; 274 275 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 276 if (!ret) 277 atomic_set(&power_gate->jpeg_gated, !enable); 278 279 return ret; 280 } 281 282 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 283 bool enable) 284 { 285 struct smu_power_context *smu_power = &smu->smu_power; 286 struct smu_power_gate *power_gate = &smu_power->power_gate; 287 int ret = 0; 288 289 if (!smu->ppt_funcs->dpm_set_vpe_enable) 290 return 0; 291 292 if (atomic_read(&power_gate->vpe_gated) ^ enable) 293 return 0; 294 295 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 296 if (!ret) 297 atomic_set(&power_gate->vpe_gated, !enable); 298 299 return ret; 300 } 301 302 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 303 bool enable) 304 { 305 struct smu_power_context *smu_power = &smu->smu_power; 306 struct smu_power_gate *power_gate = &smu_power->power_gate; 307 int ret = 0; 308 309 if (!smu->adev->enable_umsch_mm) 310 return 0; 311 312 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 313 return 0; 314 315 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 316 return 0; 317 318 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 319 if (!ret) 320 atomic_set(&power_gate->umsch_mm_gated, !enable); 321 322 return ret; 323 } 324 325 /** 326 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 327 * 328 * @handle: smu_context pointer 329 * @block_type: the IP block to power gate/ungate 330 * @gate: to power gate if true, ungate otherwise 331 * 332 * This API uses no smu->mutex lock protection due to: 333 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 334 * This is guarded to be race condition free by the caller. 335 * 2. Or get called on user setting request of power_dpm_force_performance_level. 336 * Under this case, the smu->mutex lock protection is already enforced on 337 * the parent API smu_force_performance_level of the call path. 338 */ 339 static int smu_dpm_set_power_gate(void *handle, 340 uint32_t block_type, 341 bool gate) 342 { 343 struct smu_context *smu = handle; 344 int ret = 0; 345 346 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 347 dev_WARN(smu->adev->dev, 348 "SMU uninitialized but power %s requested for %u!\n", 349 gate ? "gate" : "ungate", block_type); 350 return -EOPNOTSUPP; 351 } 352 353 switch (block_type) { 354 /* 355 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 356 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 357 */ 358 case AMD_IP_BLOCK_TYPE_UVD: 359 case AMD_IP_BLOCK_TYPE_VCN: 360 ret = smu_dpm_set_vcn_enable(smu, !gate); 361 if (ret) 362 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 363 gate ? "gate" : "ungate"); 364 break; 365 case AMD_IP_BLOCK_TYPE_GFX: 366 ret = smu_gfx_off_control(smu, gate); 367 if (ret) 368 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 369 gate ? "enable" : "disable"); 370 break; 371 case AMD_IP_BLOCK_TYPE_SDMA: 372 ret = smu_powergate_sdma(smu, gate); 373 if (ret) 374 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 375 gate ? "gate" : "ungate"); 376 break; 377 case AMD_IP_BLOCK_TYPE_JPEG: 378 ret = smu_dpm_set_jpeg_enable(smu, !gate); 379 if (ret) 380 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 381 gate ? "gate" : "ungate"); 382 break; 383 case AMD_IP_BLOCK_TYPE_VPE: 384 ret = smu_dpm_set_vpe_enable(smu, !gate); 385 if (ret) 386 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 387 gate ? "gate" : "ungate"); 388 break; 389 default: 390 dev_err(smu->adev->dev, "Unsupported block type!\n"); 391 return -EINVAL; 392 } 393 394 return ret; 395 } 396 397 /** 398 * smu_set_user_clk_dependencies - set user profile clock dependencies 399 * 400 * @smu: smu_context pointer 401 * @clk: enum smu_clk_type type 402 * 403 * Enable/Disable the clock dependency for the @clk type. 404 */ 405 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 406 { 407 if (smu->adev->in_suspend) 408 return; 409 410 if (clk == SMU_MCLK) { 411 smu->user_dpm_profile.clk_dependency = 0; 412 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 413 } else if (clk == SMU_FCLK) { 414 /* MCLK takes precedence over FCLK */ 415 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 416 return; 417 418 smu->user_dpm_profile.clk_dependency = 0; 419 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 420 } else if (clk == SMU_SOCCLK) { 421 /* MCLK takes precedence over SOCCLK */ 422 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 423 return; 424 425 smu->user_dpm_profile.clk_dependency = 0; 426 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 427 } else 428 /* Add clk dependencies here, if any */ 429 return; 430 } 431 432 /** 433 * smu_restore_dpm_user_profile - reinstate user dpm profile 434 * 435 * @smu: smu_context pointer 436 * 437 * Restore the saved user power configurations include power limit, 438 * clock frequencies, fan control mode and fan speed. 439 */ 440 static void smu_restore_dpm_user_profile(struct smu_context *smu) 441 { 442 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 443 int ret = 0; 444 445 if (!smu->adev->in_suspend) 446 return; 447 448 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 449 return; 450 451 /* Enable restore flag */ 452 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 453 454 /* set the user dpm power limit */ 455 if (smu->user_dpm_profile.power_limit) { 456 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 457 if (ret) 458 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 459 } 460 461 /* set the user dpm clock configurations */ 462 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 463 enum smu_clk_type clk_type; 464 465 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 466 /* 467 * Iterate over smu clk type and force the saved user clk 468 * configs, skip if clock dependency is enabled 469 */ 470 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 471 smu->user_dpm_profile.clk_mask[clk_type]) { 472 ret = smu_force_smuclk_levels(smu, clk_type, 473 smu->user_dpm_profile.clk_mask[clk_type]); 474 if (ret) 475 dev_err(smu->adev->dev, 476 "Failed to set clock type = %d\n", clk_type); 477 } 478 } 479 } 480 481 /* set the user dpm fan configurations */ 482 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 483 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 484 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 485 if (ret != -EOPNOTSUPP) { 486 smu->user_dpm_profile.fan_speed_pwm = 0; 487 smu->user_dpm_profile.fan_speed_rpm = 0; 488 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 489 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 490 } 491 492 if (smu->user_dpm_profile.fan_speed_pwm) { 493 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 494 if (ret != -EOPNOTSUPP) 495 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 496 } 497 498 if (smu->user_dpm_profile.fan_speed_rpm) { 499 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 500 if (ret != -EOPNOTSUPP) 501 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 502 } 503 } 504 505 /* Restore user customized OD settings */ 506 if (smu->user_dpm_profile.user_od) { 507 if (smu->ppt_funcs->restore_user_od_settings) { 508 ret = smu->ppt_funcs->restore_user_od_settings(smu); 509 if (ret) 510 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 511 } 512 } 513 514 /* Disable restore flag */ 515 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 516 } 517 518 static int smu_get_power_num_states(void *handle, 519 struct pp_states_info *state_info) 520 { 521 if (!state_info) 522 return -EINVAL; 523 524 /* not support power state */ 525 memset(state_info, 0, sizeof(struct pp_states_info)); 526 state_info->nums = 1; 527 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 528 529 return 0; 530 } 531 532 bool is_support_sw_smu(struct amdgpu_device *adev) 533 { 534 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 535 if (adev->asic_type == CHIP_VEGA20) 536 return false; 537 538 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 539 return true; 540 541 return false; 542 } 543 544 bool is_support_cclk_dpm(struct amdgpu_device *adev) 545 { 546 struct smu_context *smu = adev->powerplay.pp_handle; 547 548 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 549 return false; 550 551 return true; 552 } 553 554 555 static int smu_sys_get_pp_table(void *handle, 556 char **table) 557 { 558 struct smu_context *smu = handle; 559 struct smu_table_context *smu_table = &smu->smu_table; 560 561 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 562 return -EOPNOTSUPP; 563 564 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 565 return -EINVAL; 566 567 if (smu_table->hardcode_pptable) 568 *table = smu_table->hardcode_pptable; 569 else 570 *table = smu_table->power_play_table; 571 572 return smu_table->power_play_table_size; 573 } 574 575 static int smu_sys_set_pp_table(void *handle, 576 const char *buf, 577 size_t size) 578 { 579 struct smu_context *smu = handle; 580 struct smu_table_context *smu_table = &smu->smu_table; 581 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 582 int ret = 0; 583 584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 585 return -EOPNOTSUPP; 586 587 if (header->usStructureSize != size) { 588 dev_err(smu->adev->dev, "pp table size not matched !\n"); 589 return -EIO; 590 } 591 592 if (!smu_table->hardcode_pptable) { 593 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 594 if (!smu_table->hardcode_pptable) 595 return -ENOMEM; 596 } 597 598 memcpy(smu_table->hardcode_pptable, buf, size); 599 smu_table->power_play_table = smu_table->hardcode_pptable; 600 smu_table->power_play_table_size = size; 601 602 /* 603 * Special hw_fini action(for Navi1x, the DPMs disablement will be 604 * skipped) may be needed for custom pptable uploading. 605 */ 606 smu->uploading_custom_pp_table = true; 607 608 ret = smu_reset(smu); 609 if (ret) 610 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 611 612 smu->uploading_custom_pp_table = false; 613 614 return ret; 615 } 616 617 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 618 { 619 struct smu_feature *feature = &smu->smu_feature; 620 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 621 int ret = 0; 622 623 /* 624 * With SCPM enabled, the allowed featuremasks setting(via 625 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 626 * That means there is no way to let PMFW knows the settings below. 627 * Thus, we just assume all the features are allowed under 628 * such scenario. 629 */ 630 if (smu->adev->scpm_enabled) { 631 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 632 return 0; 633 } 634 635 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 636 637 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 638 SMU_FEATURE_MAX/32); 639 if (ret) 640 return ret; 641 642 bitmap_or(feature->allowed, feature->allowed, 643 (unsigned long *)allowed_feature_mask, 644 feature->feature_num); 645 646 return ret; 647 } 648 649 static int smu_set_funcs(struct amdgpu_device *adev) 650 { 651 struct smu_context *smu = adev->powerplay.pp_handle; 652 653 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 654 smu->od_enabled = true; 655 656 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 657 case IP_VERSION(11, 0, 0): 658 case IP_VERSION(11, 0, 5): 659 case IP_VERSION(11, 0, 9): 660 navi10_set_ppt_funcs(smu); 661 break; 662 case IP_VERSION(11, 0, 7): 663 case IP_VERSION(11, 0, 11): 664 case IP_VERSION(11, 0, 12): 665 case IP_VERSION(11, 0, 13): 666 sienna_cichlid_set_ppt_funcs(smu); 667 break; 668 case IP_VERSION(12, 0, 0): 669 case IP_VERSION(12, 0, 1): 670 renoir_set_ppt_funcs(smu); 671 break; 672 case IP_VERSION(11, 5, 0): 673 vangogh_set_ppt_funcs(smu); 674 break; 675 case IP_VERSION(13, 0, 1): 676 case IP_VERSION(13, 0, 3): 677 case IP_VERSION(13, 0, 8): 678 yellow_carp_set_ppt_funcs(smu); 679 break; 680 case IP_VERSION(13, 0, 4): 681 case IP_VERSION(13, 0, 11): 682 smu_v13_0_4_set_ppt_funcs(smu); 683 break; 684 case IP_VERSION(13, 0, 5): 685 smu_v13_0_5_set_ppt_funcs(smu); 686 break; 687 case IP_VERSION(11, 0, 8): 688 cyan_skillfish_set_ppt_funcs(smu); 689 break; 690 case IP_VERSION(11, 0, 2): 691 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 692 arcturus_set_ppt_funcs(smu); 693 /* OD is not supported on Arcturus */ 694 smu->od_enabled = false; 695 break; 696 case IP_VERSION(13, 0, 2): 697 aldebaran_set_ppt_funcs(smu); 698 /* Enable pp_od_clk_voltage node */ 699 smu->od_enabled = true; 700 break; 701 case IP_VERSION(13, 0, 0): 702 case IP_VERSION(13, 0, 10): 703 smu_v13_0_0_set_ppt_funcs(smu); 704 break; 705 case IP_VERSION(13, 0, 6): 706 smu_v13_0_6_set_ppt_funcs(smu); 707 /* Enable pp_od_clk_voltage node */ 708 smu->od_enabled = true; 709 break; 710 case IP_VERSION(13, 0, 7): 711 smu_v13_0_7_set_ppt_funcs(smu); 712 break; 713 case IP_VERSION(14, 0, 0): 714 smu_v14_0_0_set_ppt_funcs(smu); 715 break; 716 default: 717 return -EINVAL; 718 } 719 720 return 0; 721 } 722 723 static int smu_early_init(void *handle) 724 { 725 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 726 struct smu_context *smu; 727 int r; 728 729 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 730 if (!smu) 731 return -ENOMEM; 732 733 smu->adev = adev; 734 smu->pm_enabled = !!amdgpu_dpm; 735 smu->is_apu = false; 736 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 737 smu->smu_baco.platform_support = false; 738 smu->user_dpm_profile.fan_mode = -1; 739 740 mutex_init(&smu->message_lock); 741 742 adev->powerplay.pp_handle = smu; 743 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 744 745 r = smu_set_funcs(adev); 746 if (r) 747 return r; 748 return smu_init_microcode(smu); 749 } 750 751 static int smu_set_default_dpm_table(struct smu_context *smu) 752 { 753 struct smu_power_context *smu_power = &smu->smu_power; 754 struct smu_power_gate *power_gate = &smu_power->power_gate; 755 int vcn_gate, jpeg_gate; 756 int ret = 0; 757 758 if (!smu->ppt_funcs->set_default_dpm_table) 759 return 0; 760 761 vcn_gate = atomic_read(&power_gate->vcn_gated); 762 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 763 764 ret = smu_dpm_set_vcn_enable(smu, true); 765 if (ret) 766 return ret; 767 768 ret = smu_dpm_set_jpeg_enable(smu, true); 769 if (ret) 770 goto err_out; 771 772 ret = smu->ppt_funcs->set_default_dpm_table(smu); 773 if (ret) 774 dev_err(smu->adev->dev, 775 "Failed to setup default dpm clock tables!\n"); 776 777 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 778 err_out: 779 smu_dpm_set_vcn_enable(smu, !vcn_gate); 780 return ret; 781 } 782 783 static int smu_apply_default_config_table_settings(struct smu_context *smu) 784 { 785 struct amdgpu_device *adev = smu->adev; 786 int ret = 0; 787 788 ret = smu_get_default_config_table_settings(smu, 789 &adev->pm.config_table); 790 if (ret) 791 return ret; 792 793 return smu_set_config_table(smu, &adev->pm.config_table); 794 } 795 796 static int smu_late_init(void *handle) 797 { 798 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 799 struct smu_context *smu = adev->powerplay.pp_handle; 800 int ret = 0; 801 802 smu_set_fine_grain_gfx_freq_parameters(smu); 803 804 if (!smu->pm_enabled) 805 return 0; 806 807 ret = smu_post_init(smu); 808 if (ret) { 809 dev_err(adev->dev, "Failed to post smu init!\n"); 810 return ret; 811 } 812 813 /* 814 * Explicitly notify PMFW the power mode the system in. Since 815 * the PMFW may boot the ASIC with a different mode. 816 * For those supporting ACDC switch via gpio, PMFW will 817 * handle the switch automatically. Driver involvement 818 * is unnecessary. 819 */ 820 if (!smu->dc_controlled_by_gpio) { 821 ret = smu_set_power_source(smu, 822 adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 823 SMU_POWER_SOURCE_DC); 824 if (ret) { 825 dev_err(adev->dev, "Failed to switch to %s mode!\n", 826 adev->pm.ac_power ? "AC" : "DC"); 827 return ret; 828 } 829 } 830 831 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 832 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 833 return 0; 834 835 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 836 ret = smu_set_default_od_settings(smu); 837 if (ret) { 838 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 839 return ret; 840 } 841 } 842 843 ret = smu_populate_umd_state_clk(smu); 844 if (ret) { 845 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 846 return ret; 847 } 848 849 ret = smu_get_asic_power_limits(smu, 850 &smu->current_power_limit, 851 &smu->default_power_limit, 852 &smu->max_power_limit, 853 &smu->min_power_limit); 854 if (ret) { 855 dev_err(adev->dev, "Failed to get asic power limits!\n"); 856 return ret; 857 } 858 859 if (!amdgpu_sriov_vf(adev)) 860 smu_get_unique_id(smu); 861 862 smu_get_fan_parameters(smu); 863 864 smu_handle_task(smu, 865 smu->smu_dpm.dpm_level, 866 AMD_PP_TASK_COMPLETE_INIT); 867 868 ret = smu_apply_default_config_table_settings(smu); 869 if (ret && (ret != -EOPNOTSUPP)) { 870 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 871 return ret; 872 } 873 874 smu_restore_dpm_user_profile(smu); 875 876 return 0; 877 } 878 879 static int smu_init_fb_allocations(struct smu_context *smu) 880 { 881 struct amdgpu_device *adev = smu->adev; 882 struct smu_table_context *smu_table = &smu->smu_table; 883 struct smu_table *tables = smu_table->tables; 884 struct smu_table *driver_table = &(smu_table->driver_table); 885 uint32_t max_table_size = 0; 886 int ret, i; 887 888 /* VRAM allocation for tool table */ 889 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 890 ret = amdgpu_bo_create_kernel(adev, 891 tables[SMU_TABLE_PMSTATUSLOG].size, 892 tables[SMU_TABLE_PMSTATUSLOG].align, 893 tables[SMU_TABLE_PMSTATUSLOG].domain, 894 &tables[SMU_TABLE_PMSTATUSLOG].bo, 895 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 896 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 897 if (ret) { 898 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 899 return ret; 900 } 901 } 902 903 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 904 /* VRAM allocation for driver table */ 905 for (i = 0; i < SMU_TABLE_COUNT; i++) { 906 if (tables[i].size == 0) 907 continue; 908 909 /* If one of the tables has VRAM domain restriction, keep it in 910 * VRAM 911 */ 912 if ((tables[i].domain & 913 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 914 AMDGPU_GEM_DOMAIN_VRAM) 915 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 916 917 if (i == SMU_TABLE_PMSTATUSLOG) 918 continue; 919 920 if (max_table_size < tables[i].size) 921 max_table_size = tables[i].size; 922 } 923 924 driver_table->size = max_table_size; 925 driver_table->align = PAGE_SIZE; 926 927 ret = amdgpu_bo_create_kernel(adev, 928 driver_table->size, 929 driver_table->align, 930 driver_table->domain, 931 &driver_table->bo, 932 &driver_table->mc_address, 933 &driver_table->cpu_addr); 934 if (ret) { 935 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 936 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 937 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 938 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 939 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 940 } 941 942 return ret; 943 } 944 945 static int smu_fini_fb_allocations(struct smu_context *smu) 946 { 947 struct smu_table_context *smu_table = &smu->smu_table; 948 struct smu_table *tables = smu_table->tables; 949 struct smu_table *driver_table = &(smu_table->driver_table); 950 951 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 952 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 953 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 954 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 955 956 amdgpu_bo_free_kernel(&driver_table->bo, 957 &driver_table->mc_address, 958 &driver_table->cpu_addr); 959 960 return 0; 961 } 962 963 /** 964 * smu_alloc_memory_pool - allocate memory pool in the system memory 965 * 966 * @smu: amdgpu_device pointer 967 * 968 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 969 * and DramLogSetDramAddr can notify it changed. 970 * 971 * Returns 0 on success, error on failure. 972 */ 973 static int smu_alloc_memory_pool(struct smu_context *smu) 974 { 975 struct amdgpu_device *adev = smu->adev; 976 struct smu_table_context *smu_table = &smu->smu_table; 977 struct smu_table *memory_pool = &smu_table->memory_pool; 978 uint64_t pool_size = smu->pool_size; 979 int ret = 0; 980 981 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 982 return ret; 983 984 memory_pool->size = pool_size; 985 memory_pool->align = PAGE_SIZE; 986 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 987 988 switch (pool_size) { 989 case SMU_MEMORY_POOL_SIZE_256_MB: 990 case SMU_MEMORY_POOL_SIZE_512_MB: 991 case SMU_MEMORY_POOL_SIZE_1_GB: 992 case SMU_MEMORY_POOL_SIZE_2_GB: 993 ret = amdgpu_bo_create_kernel(adev, 994 memory_pool->size, 995 memory_pool->align, 996 memory_pool->domain, 997 &memory_pool->bo, 998 &memory_pool->mc_address, 999 &memory_pool->cpu_addr); 1000 if (ret) 1001 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1002 break; 1003 default: 1004 break; 1005 } 1006 1007 return ret; 1008 } 1009 1010 static int smu_free_memory_pool(struct smu_context *smu) 1011 { 1012 struct smu_table_context *smu_table = &smu->smu_table; 1013 struct smu_table *memory_pool = &smu_table->memory_pool; 1014 1015 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1016 return 0; 1017 1018 amdgpu_bo_free_kernel(&memory_pool->bo, 1019 &memory_pool->mc_address, 1020 &memory_pool->cpu_addr); 1021 1022 memset(memory_pool, 0, sizeof(struct smu_table)); 1023 1024 return 0; 1025 } 1026 1027 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1028 { 1029 struct smu_table_context *smu_table = &smu->smu_table; 1030 struct smu_table *dummy_read_1_table = 1031 &smu_table->dummy_read_1_table; 1032 struct amdgpu_device *adev = smu->adev; 1033 int ret = 0; 1034 1035 if (!dummy_read_1_table->size) 1036 return 0; 1037 1038 ret = amdgpu_bo_create_kernel(adev, 1039 dummy_read_1_table->size, 1040 dummy_read_1_table->align, 1041 dummy_read_1_table->domain, 1042 &dummy_read_1_table->bo, 1043 &dummy_read_1_table->mc_address, 1044 &dummy_read_1_table->cpu_addr); 1045 if (ret) 1046 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1047 1048 return ret; 1049 } 1050 1051 static void smu_free_dummy_read_table(struct smu_context *smu) 1052 { 1053 struct smu_table_context *smu_table = &smu->smu_table; 1054 struct smu_table *dummy_read_1_table = 1055 &smu_table->dummy_read_1_table; 1056 1057 1058 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1059 &dummy_read_1_table->mc_address, 1060 &dummy_read_1_table->cpu_addr); 1061 1062 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1063 } 1064 1065 static int smu_smc_table_sw_init(struct smu_context *smu) 1066 { 1067 int ret; 1068 1069 /** 1070 * Create smu_table structure, and init smc tables such as 1071 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1072 */ 1073 ret = smu_init_smc_tables(smu); 1074 if (ret) { 1075 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1076 return ret; 1077 } 1078 1079 /** 1080 * Create smu_power_context structure, and allocate smu_dpm_context and 1081 * context size to fill the smu_power_context data. 1082 */ 1083 ret = smu_init_power(smu); 1084 if (ret) { 1085 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1086 return ret; 1087 } 1088 1089 /* 1090 * allocate vram bos to store smc table contents. 1091 */ 1092 ret = smu_init_fb_allocations(smu); 1093 if (ret) 1094 return ret; 1095 1096 ret = smu_alloc_memory_pool(smu); 1097 if (ret) 1098 return ret; 1099 1100 ret = smu_alloc_dummy_read_table(smu); 1101 if (ret) 1102 return ret; 1103 1104 ret = smu_i2c_init(smu); 1105 if (ret) 1106 return ret; 1107 1108 return 0; 1109 } 1110 1111 static int smu_smc_table_sw_fini(struct smu_context *smu) 1112 { 1113 int ret; 1114 1115 smu_i2c_fini(smu); 1116 1117 smu_free_dummy_read_table(smu); 1118 1119 ret = smu_free_memory_pool(smu); 1120 if (ret) 1121 return ret; 1122 1123 ret = smu_fini_fb_allocations(smu); 1124 if (ret) 1125 return ret; 1126 1127 ret = smu_fini_power(smu); 1128 if (ret) { 1129 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1130 return ret; 1131 } 1132 1133 ret = smu_fini_smc_tables(smu); 1134 if (ret) { 1135 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1136 return ret; 1137 } 1138 1139 return 0; 1140 } 1141 1142 static void smu_throttling_logging_work_fn(struct work_struct *work) 1143 { 1144 struct smu_context *smu = container_of(work, struct smu_context, 1145 throttling_logging_work); 1146 1147 smu_log_thermal_throttling(smu); 1148 } 1149 1150 static void smu_interrupt_work_fn(struct work_struct *work) 1151 { 1152 struct smu_context *smu = container_of(work, struct smu_context, 1153 interrupt_work); 1154 1155 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1156 smu->ppt_funcs->interrupt_work(smu); 1157 } 1158 1159 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1160 { 1161 struct smu_context *smu = 1162 container_of(work, struct smu_context, swctf_delayed_work.work); 1163 struct smu_temperature_range *range = 1164 &smu->thermal_range; 1165 struct amdgpu_device *adev = smu->adev; 1166 uint32_t hotspot_tmp, size; 1167 1168 /* 1169 * If the hotspot temperature is confirmed as below SW CTF setting point 1170 * after the delay enforced, nothing will be done. 1171 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1172 */ 1173 if (range->software_shutdown_temp && 1174 smu->ppt_funcs->read_sensor && 1175 !smu->ppt_funcs->read_sensor(smu, 1176 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1177 &hotspot_tmp, 1178 &size) && 1179 hotspot_tmp / 1000 < range->software_shutdown_temp) 1180 return; 1181 1182 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1183 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1184 orderly_poweroff(true); 1185 } 1186 1187 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1188 { 1189 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1190 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1191 return; 1192 } 1193 1194 /* PMFW put PLPD into default policy after enabling the feature */ 1195 if (smu_feature_is_enabled(smu, 1196 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) 1197 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1198 else 1199 smu->plpd_mode = XGMI_PLPD_NONE; 1200 } 1201 1202 static int smu_sw_init(void *handle) 1203 { 1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1205 struct smu_context *smu = adev->powerplay.pp_handle; 1206 int ret; 1207 1208 smu->pool_size = adev->pm.smu_prv_buffer_size; 1209 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1210 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1211 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1212 1213 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1214 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1215 atomic64_set(&smu->throttle_int_counter, 0); 1216 smu->watermarks_bitmap = 0; 1217 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1218 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1219 1220 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1221 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1222 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1223 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1224 1225 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1226 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1227 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1228 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1229 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1230 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1231 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1232 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1233 1234 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1235 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1236 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1237 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1238 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1239 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1240 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1241 smu->display_config = &adev->pm.pm_display_cfg; 1242 1243 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1244 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1245 1246 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1247 smu_swctf_delayed_work_handler); 1248 1249 ret = smu_smc_table_sw_init(smu); 1250 if (ret) { 1251 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1252 return ret; 1253 } 1254 1255 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1256 ret = smu_get_vbios_bootup_values(smu); 1257 if (ret) { 1258 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1259 return ret; 1260 } 1261 1262 ret = smu_init_pptable_microcode(smu); 1263 if (ret) { 1264 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1265 return ret; 1266 } 1267 1268 ret = smu_register_irq_handler(smu); 1269 if (ret) { 1270 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1271 return ret; 1272 } 1273 1274 /* If there is no way to query fan control mode, fan control is not supported */ 1275 if (!smu->ppt_funcs->get_fan_control_mode) 1276 smu->adev->pm.no_fan = true; 1277 1278 return 0; 1279 } 1280 1281 static int smu_sw_fini(void *handle) 1282 { 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 struct smu_context *smu = adev->powerplay.pp_handle; 1285 int ret; 1286 1287 ret = smu_smc_table_sw_fini(smu); 1288 if (ret) { 1289 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1290 return ret; 1291 } 1292 1293 smu_fini_microcode(smu); 1294 1295 return 0; 1296 } 1297 1298 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1299 { 1300 struct amdgpu_device *adev = smu->adev; 1301 struct smu_temperature_range *range = 1302 &smu->thermal_range; 1303 int ret = 0; 1304 1305 if (!smu->ppt_funcs->get_thermal_temperature_range) 1306 return 0; 1307 1308 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1309 if (ret) 1310 return ret; 1311 1312 adev->pm.dpm.thermal.min_temp = range->min; 1313 adev->pm.dpm.thermal.max_temp = range->max; 1314 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1315 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1316 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1317 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1318 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1319 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1320 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1321 1322 return ret; 1323 } 1324 1325 static int smu_smc_hw_setup(struct smu_context *smu) 1326 { 1327 struct smu_feature *feature = &smu->smu_feature; 1328 struct amdgpu_device *adev = smu->adev; 1329 uint8_t pcie_gen = 0, pcie_width = 0; 1330 uint64_t features_supported; 1331 int ret = 0; 1332 1333 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1334 case IP_VERSION(11, 0, 7): 1335 case IP_VERSION(11, 0, 11): 1336 case IP_VERSION(11, 5, 0): 1337 case IP_VERSION(11, 0, 12): 1338 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1339 dev_info(adev->dev, "dpm has been enabled\n"); 1340 ret = smu_system_features_control(smu, true); 1341 if (ret) 1342 dev_err(adev->dev, "Failed system features control!\n"); 1343 return ret; 1344 } 1345 break; 1346 default: 1347 break; 1348 } 1349 1350 ret = smu_init_display_count(smu, 0); 1351 if (ret) { 1352 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1353 return ret; 1354 } 1355 1356 ret = smu_set_driver_table_location(smu); 1357 if (ret) { 1358 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1359 return ret; 1360 } 1361 1362 /* 1363 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1364 */ 1365 ret = smu_set_tool_table_location(smu); 1366 if (ret) { 1367 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1368 return ret; 1369 } 1370 1371 /* 1372 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1373 * pool location. 1374 */ 1375 ret = smu_notify_memory_pool_location(smu); 1376 if (ret) { 1377 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1378 return ret; 1379 } 1380 1381 /* 1382 * It is assumed the pptable used before runpm is same as 1383 * the one used afterwards. Thus, we can reuse the stored 1384 * copy and do not need to resetup the pptable again. 1385 */ 1386 if (!adev->in_runpm) { 1387 ret = smu_setup_pptable(smu); 1388 if (ret) { 1389 dev_err(adev->dev, "Failed to setup pptable!\n"); 1390 return ret; 1391 } 1392 } 1393 1394 /* smu_dump_pptable(smu); */ 1395 1396 /* 1397 * With SCPM enabled, PSP is responsible for the PPTable transferring 1398 * (to SMU). Driver involvement is not needed and permitted. 1399 */ 1400 if (!adev->scpm_enabled) { 1401 /* 1402 * Copy pptable bo in the vram to smc with SMU MSGs such as 1403 * SetDriverDramAddr and TransferTableDram2Smu. 1404 */ 1405 ret = smu_write_pptable(smu); 1406 if (ret) { 1407 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1408 return ret; 1409 } 1410 } 1411 1412 /* issue Run*Btc msg */ 1413 ret = smu_run_btc(smu); 1414 if (ret) 1415 return ret; 1416 1417 /* 1418 * With SCPM enabled, these actions(and relevant messages) are 1419 * not needed and permitted. 1420 */ 1421 if (!adev->scpm_enabled) { 1422 ret = smu_feature_set_allowed_mask(smu); 1423 if (ret) { 1424 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1425 return ret; 1426 } 1427 } 1428 1429 ret = smu_system_features_control(smu, true); 1430 if (ret) { 1431 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1432 return ret; 1433 } 1434 1435 smu_init_xgmi_plpd_mode(smu); 1436 1437 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1438 if (ret) { 1439 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1440 return ret; 1441 } 1442 bitmap_copy(feature->supported, 1443 (unsigned long *)&features_supported, 1444 feature->feature_num); 1445 1446 if (!smu_is_dpm_running(smu)) 1447 dev_info(adev->dev, "dpm has been disabled\n"); 1448 1449 /* 1450 * Set initialized values (get from vbios) to dpm tables context such as 1451 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1452 * type of clks. 1453 */ 1454 ret = smu_set_default_dpm_table(smu); 1455 if (ret) { 1456 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1457 return ret; 1458 } 1459 1460 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1461 pcie_gen = 3; 1462 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1463 pcie_gen = 2; 1464 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1465 pcie_gen = 1; 1466 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1467 pcie_gen = 0; 1468 1469 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1470 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1471 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1472 */ 1473 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1474 pcie_width = 6; 1475 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1476 pcie_width = 5; 1477 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1478 pcie_width = 4; 1479 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1480 pcie_width = 3; 1481 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1482 pcie_width = 2; 1483 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1484 pcie_width = 1; 1485 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1486 if (ret) { 1487 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1488 return ret; 1489 } 1490 1491 ret = smu_get_thermal_temperature_range(smu); 1492 if (ret) { 1493 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1494 return ret; 1495 } 1496 1497 ret = smu_enable_thermal_alert(smu); 1498 if (ret) { 1499 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1500 return ret; 1501 } 1502 1503 ret = smu_notify_display_change(smu); 1504 if (ret) { 1505 dev_err(adev->dev, "Failed to notify display change!\n"); 1506 return ret; 1507 } 1508 1509 /* 1510 * Set min deep sleep dce fclk with bootup value from vbios via 1511 * SetMinDeepSleepDcefclk MSG. 1512 */ 1513 ret = smu_set_min_dcef_deep_sleep(smu, 1514 smu->smu_table.boot_values.dcefclk / 100); 1515 1516 return ret; 1517 } 1518 1519 static int smu_start_smc_engine(struct smu_context *smu) 1520 { 1521 struct amdgpu_device *adev = smu->adev; 1522 int ret = 0; 1523 1524 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1525 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1526 if (smu->ppt_funcs->load_microcode) { 1527 ret = smu->ppt_funcs->load_microcode(smu); 1528 if (ret) 1529 return ret; 1530 } 1531 } 1532 } 1533 1534 if (smu->ppt_funcs->check_fw_status) { 1535 ret = smu->ppt_funcs->check_fw_status(smu); 1536 if (ret) { 1537 dev_err(adev->dev, "SMC is not ready\n"); 1538 return ret; 1539 } 1540 } 1541 1542 /* 1543 * Send msg GetDriverIfVersion to check if the return value is equal 1544 * with DRIVER_IF_VERSION of smc header. 1545 */ 1546 ret = smu_check_fw_version(smu); 1547 if (ret) 1548 return ret; 1549 1550 return ret; 1551 } 1552 1553 static int smu_hw_init(void *handle) 1554 { 1555 int ret; 1556 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1557 struct smu_context *smu = adev->powerplay.pp_handle; 1558 1559 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1560 smu->pm_enabled = false; 1561 return 0; 1562 } 1563 1564 ret = smu_start_smc_engine(smu); 1565 if (ret) { 1566 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1567 return ret; 1568 } 1569 1570 if (smu->is_apu) { 1571 ret = smu_set_gfx_imu_enable(smu); 1572 if (ret) 1573 return ret; 1574 smu_dpm_set_vcn_enable(smu, true); 1575 smu_dpm_set_jpeg_enable(smu, true); 1576 smu_dpm_set_vpe_enable(smu, true); 1577 smu_dpm_set_umsch_mm_enable(smu, true); 1578 smu_set_gfx_cgpg(smu, true); 1579 } 1580 1581 if (!smu->pm_enabled) 1582 return 0; 1583 1584 ret = smu_get_driver_allowed_feature_mask(smu); 1585 if (ret) 1586 return ret; 1587 1588 ret = smu_smc_hw_setup(smu); 1589 if (ret) { 1590 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1591 return ret; 1592 } 1593 1594 /* 1595 * Move maximum sustainable clock retrieving here considering 1596 * 1. It is not needed on resume(from S3). 1597 * 2. DAL settings come between .hw_init and .late_init of SMU. 1598 * And DAL needs to know the maximum sustainable clocks. Thus 1599 * it cannot be put in .late_init(). 1600 */ 1601 ret = smu_init_max_sustainable_clocks(smu); 1602 if (ret) { 1603 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1604 return ret; 1605 } 1606 1607 adev->pm.dpm_enabled = true; 1608 1609 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1610 1611 return 0; 1612 } 1613 1614 static int smu_disable_dpms(struct smu_context *smu) 1615 { 1616 struct amdgpu_device *adev = smu->adev; 1617 int ret = 0; 1618 bool use_baco = !smu->is_apu && 1619 ((amdgpu_in_reset(adev) && 1620 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1621 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1622 1623 /* 1624 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1625 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1626 */ 1627 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1628 case IP_VERSION(13, 0, 0): 1629 case IP_VERSION(13, 0, 7): 1630 case IP_VERSION(13, 0, 10): 1631 return 0; 1632 default: 1633 break; 1634 } 1635 1636 /* 1637 * For custom pptable uploading, skip the DPM features 1638 * disable process on Navi1x ASICs. 1639 * - As the gfx related features are under control of 1640 * RLC on those ASICs. RLC reinitialization will be 1641 * needed to reenable them. That will cost much more 1642 * efforts. 1643 * 1644 * - SMU firmware can handle the DPM reenablement 1645 * properly. 1646 */ 1647 if (smu->uploading_custom_pp_table) { 1648 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1649 case IP_VERSION(11, 0, 0): 1650 case IP_VERSION(11, 0, 5): 1651 case IP_VERSION(11, 0, 9): 1652 case IP_VERSION(11, 0, 7): 1653 case IP_VERSION(11, 0, 11): 1654 case IP_VERSION(11, 5, 0): 1655 case IP_VERSION(11, 0, 12): 1656 case IP_VERSION(11, 0, 13): 1657 return 0; 1658 default: 1659 break; 1660 } 1661 } 1662 1663 /* 1664 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1665 * on BACO in. Driver involvement is unnecessary. 1666 */ 1667 if (use_baco) { 1668 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1669 case IP_VERSION(11, 0, 7): 1670 case IP_VERSION(11, 0, 0): 1671 case IP_VERSION(11, 0, 5): 1672 case IP_VERSION(11, 0, 9): 1673 case IP_VERSION(13, 0, 7): 1674 return 0; 1675 default: 1676 break; 1677 } 1678 } 1679 1680 /* 1681 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1682 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1683 */ 1684 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1685 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1686 case IP_VERSION(13, 0, 4): 1687 case IP_VERSION(13, 0, 11): 1688 case IP_VERSION(14, 0, 0): 1689 return 0; 1690 default: 1691 break; 1692 } 1693 } 1694 1695 /* 1696 * For gpu reset, runpm and hibernation through BACO, 1697 * BACO feature has to be kept enabled. 1698 */ 1699 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1700 ret = smu_disable_all_features_with_exception(smu, 1701 SMU_FEATURE_BACO_BIT); 1702 if (ret) 1703 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1704 } else { 1705 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1706 if (!adev->scpm_enabled) { 1707 ret = smu_system_features_control(smu, false); 1708 if (ret) 1709 dev_err(adev->dev, "Failed to disable smu features.\n"); 1710 } 1711 } 1712 1713 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1714 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1715 adev->gfx.rlc.funcs->stop(adev); 1716 1717 return ret; 1718 } 1719 1720 static int smu_smc_hw_cleanup(struct smu_context *smu) 1721 { 1722 struct amdgpu_device *adev = smu->adev; 1723 int ret = 0; 1724 1725 cancel_work_sync(&smu->throttling_logging_work); 1726 cancel_work_sync(&smu->interrupt_work); 1727 1728 ret = smu_disable_thermal_alert(smu); 1729 if (ret) { 1730 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1731 return ret; 1732 } 1733 1734 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1735 1736 ret = smu_disable_dpms(smu); 1737 if (ret) { 1738 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1739 return ret; 1740 } 1741 1742 return 0; 1743 } 1744 1745 static int smu_hw_fini(void *handle) 1746 { 1747 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1748 struct smu_context *smu = adev->powerplay.pp_handle; 1749 1750 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1751 return 0; 1752 1753 smu_dpm_set_vcn_enable(smu, false); 1754 smu_dpm_set_jpeg_enable(smu, false); 1755 smu_dpm_set_vpe_enable(smu, false); 1756 smu_dpm_set_umsch_mm_enable(smu, false); 1757 1758 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1759 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1760 1761 if (!smu->pm_enabled) 1762 return 0; 1763 1764 adev->pm.dpm_enabled = false; 1765 1766 return smu_smc_hw_cleanup(smu); 1767 } 1768 1769 static void smu_late_fini(void *handle) 1770 { 1771 struct amdgpu_device *adev = handle; 1772 struct smu_context *smu = adev->powerplay.pp_handle; 1773 1774 kfree(smu); 1775 } 1776 1777 static int smu_reset(struct smu_context *smu) 1778 { 1779 struct amdgpu_device *adev = smu->adev; 1780 int ret; 1781 1782 ret = smu_hw_fini(adev); 1783 if (ret) 1784 return ret; 1785 1786 ret = smu_hw_init(adev); 1787 if (ret) 1788 return ret; 1789 1790 ret = smu_late_init(adev); 1791 if (ret) 1792 return ret; 1793 1794 return 0; 1795 } 1796 1797 static int smu_suspend(void *handle) 1798 { 1799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1800 struct smu_context *smu = adev->powerplay.pp_handle; 1801 int ret; 1802 uint64_t count; 1803 1804 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1805 return 0; 1806 1807 if (!smu->pm_enabled) 1808 return 0; 1809 1810 adev->pm.dpm_enabled = false; 1811 1812 ret = smu_smc_hw_cleanup(smu); 1813 if (ret) 1814 return ret; 1815 1816 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1817 1818 smu_set_gfx_cgpg(smu, false); 1819 1820 /* 1821 * pwfw resets entrycount when device is suspended, so we save the 1822 * last value to be used when we resume to keep it consistent 1823 */ 1824 ret = smu_get_entrycount_gfxoff(smu, &count); 1825 if (!ret) 1826 adev->gfx.gfx_off_entrycount = count; 1827 1828 return 0; 1829 } 1830 1831 static int smu_resume(void *handle) 1832 { 1833 int ret; 1834 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1835 struct smu_context *smu = adev->powerplay.pp_handle; 1836 1837 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1838 return 0; 1839 1840 if (!smu->pm_enabled) 1841 return 0; 1842 1843 dev_info(adev->dev, "SMU is resuming...\n"); 1844 1845 ret = smu_start_smc_engine(smu); 1846 if (ret) { 1847 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1848 return ret; 1849 } 1850 1851 ret = smu_smc_hw_setup(smu); 1852 if (ret) { 1853 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1854 return ret; 1855 } 1856 1857 ret = smu_set_gfx_imu_enable(smu); 1858 if (ret) 1859 return ret; 1860 1861 smu_set_gfx_cgpg(smu, true); 1862 1863 smu->disable_uclk_switch = 0; 1864 1865 adev->pm.dpm_enabled = true; 1866 1867 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1868 1869 return 0; 1870 } 1871 1872 static int smu_display_configuration_change(void *handle, 1873 const struct amd_pp_display_configuration *display_config) 1874 { 1875 struct smu_context *smu = handle; 1876 1877 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1878 return -EOPNOTSUPP; 1879 1880 if (!display_config) 1881 return -EINVAL; 1882 1883 smu_set_min_dcef_deep_sleep(smu, 1884 display_config->min_dcef_deep_sleep_set_clk / 100); 1885 1886 return 0; 1887 } 1888 1889 static int smu_set_clockgating_state(void *handle, 1890 enum amd_clockgating_state state) 1891 { 1892 return 0; 1893 } 1894 1895 static int smu_set_powergating_state(void *handle, 1896 enum amd_powergating_state state) 1897 { 1898 return 0; 1899 } 1900 1901 static int smu_enable_umd_pstate(void *handle, 1902 enum amd_dpm_forced_level *level) 1903 { 1904 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1905 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1906 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1907 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1908 1909 struct smu_context *smu = (struct smu_context*)(handle); 1910 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1911 1912 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1913 return -EINVAL; 1914 1915 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1916 /* enter umd pstate, save current level, disable gfx cg*/ 1917 if (*level & profile_mode_mask) { 1918 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1919 smu_gpo_control(smu, false); 1920 smu_gfx_ulv_control(smu, false); 1921 smu_deep_sleep_control(smu, false); 1922 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1923 } 1924 } else { 1925 /* exit umd pstate, restore level, enable gfx cg*/ 1926 if (!(*level & profile_mode_mask)) { 1927 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1928 *level = smu_dpm_ctx->saved_dpm_level; 1929 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1930 smu_deep_sleep_control(smu, true); 1931 smu_gfx_ulv_control(smu, true); 1932 smu_gpo_control(smu, true); 1933 } 1934 } 1935 1936 return 0; 1937 } 1938 1939 static int smu_bump_power_profile_mode(struct smu_context *smu, 1940 long *param, 1941 uint32_t param_size) 1942 { 1943 int ret = 0; 1944 1945 if (smu->ppt_funcs->set_power_profile_mode) 1946 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1947 1948 return ret; 1949 } 1950 1951 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1952 enum amd_dpm_forced_level level, 1953 bool skip_display_settings) 1954 { 1955 int ret = 0; 1956 int index = 0; 1957 long workload; 1958 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1959 1960 if (!skip_display_settings) { 1961 ret = smu_display_config_changed(smu); 1962 if (ret) { 1963 dev_err(smu->adev->dev, "Failed to change display config!"); 1964 return ret; 1965 } 1966 } 1967 1968 ret = smu_apply_clocks_adjust_rules(smu); 1969 if (ret) { 1970 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1971 return ret; 1972 } 1973 1974 if (!skip_display_settings) { 1975 ret = smu_notify_smc_display_config(smu); 1976 if (ret) { 1977 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1978 return ret; 1979 } 1980 } 1981 1982 if (smu_dpm_ctx->dpm_level != level) { 1983 ret = smu_asic_set_performance_level(smu, level); 1984 if (ret) { 1985 dev_err(smu->adev->dev, "Failed to set performance level!"); 1986 return ret; 1987 } 1988 1989 /* update the saved copy */ 1990 smu_dpm_ctx->dpm_level = level; 1991 } 1992 1993 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1994 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1995 index = fls(smu->workload_mask); 1996 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1997 workload = smu->workload_setting[index]; 1998 1999 if (smu->power_profile_mode != workload) 2000 smu_bump_power_profile_mode(smu, &workload, 0); 2001 } 2002 2003 return ret; 2004 } 2005 2006 static int smu_handle_task(struct smu_context *smu, 2007 enum amd_dpm_forced_level level, 2008 enum amd_pp_task task_id) 2009 { 2010 int ret = 0; 2011 2012 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2013 return -EOPNOTSUPP; 2014 2015 switch (task_id) { 2016 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2017 ret = smu_pre_display_config_changed(smu); 2018 if (ret) 2019 return ret; 2020 ret = smu_adjust_power_state_dynamic(smu, level, false); 2021 break; 2022 case AMD_PP_TASK_COMPLETE_INIT: 2023 case AMD_PP_TASK_READJUST_POWER_STATE: 2024 ret = smu_adjust_power_state_dynamic(smu, level, true); 2025 break; 2026 default: 2027 break; 2028 } 2029 2030 return ret; 2031 } 2032 2033 static int smu_handle_dpm_task(void *handle, 2034 enum amd_pp_task task_id, 2035 enum amd_pm_state_type *user_state) 2036 { 2037 struct smu_context *smu = handle; 2038 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2039 2040 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2041 2042 } 2043 2044 static int smu_switch_power_profile(void *handle, 2045 enum PP_SMC_POWER_PROFILE type, 2046 bool en) 2047 { 2048 struct smu_context *smu = handle; 2049 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2050 long workload; 2051 uint32_t index; 2052 2053 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2054 return -EOPNOTSUPP; 2055 2056 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2057 return -EINVAL; 2058 2059 if (!en) { 2060 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2061 index = fls(smu->workload_mask); 2062 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2063 workload = smu->workload_setting[index]; 2064 } else { 2065 smu->workload_mask |= (1 << smu->workload_prority[type]); 2066 index = fls(smu->workload_mask); 2067 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2068 workload = smu->workload_setting[index]; 2069 } 2070 2071 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2072 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2073 smu_bump_power_profile_mode(smu, &workload, 0); 2074 2075 return 0; 2076 } 2077 2078 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2079 { 2080 struct smu_context *smu = handle; 2081 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2082 2083 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2084 return -EOPNOTSUPP; 2085 2086 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2087 return -EINVAL; 2088 2089 return smu_dpm_ctx->dpm_level; 2090 } 2091 2092 static int smu_force_performance_level(void *handle, 2093 enum amd_dpm_forced_level level) 2094 { 2095 struct smu_context *smu = handle; 2096 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2097 int ret = 0; 2098 2099 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2100 return -EOPNOTSUPP; 2101 2102 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2103 return -EINVAL; 2104 2105 ret = smu_enable_umd_pstate(smu, &level); 2106 if (ret) 2107 return ret; 2108 2109 ret = smu_handle_task(smu, level, 2110 AMD_PP_TASK_READJUST_POWER_STATE); 2111 2112 /* reset user dpm clock state */ 2113 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2114 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2115 smu->user_dpm_profile.clk_dependency = 0; 2116 } 2117 2118 return ret; 2119 } 2120 2121 static int smu_set_display_count(void *handle, uint32_t count) 2122 { 2123 struct smu_context *smu = handle; 2124 2125 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2126 return -EOPNOTSUPP; 2127 2128 return smu_init_display_count(smu, count); 2129 } 2130 2131 static int smu_force_smuclk_levels(struct smu_context *smu, 2132 enum smu_clk_type clk_type, 2133 uint32_t mask) 2134 { 2135 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2136 int ret = 0; 2137 2138 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2139 return -EOPNOTSUPP; 2140 2141 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2142 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2143 return -EINVAL; 2144 } 2145 2146 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2147 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2148 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2149 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2150 smu_set_user_clk_dependencies(smu, clk_type); 2151 } 2152 } 2153 2154 return ret; 2155 } 2156 2157 static int smu_force_ppclk_levels(void *handle, 2158 enum pp_clock_type type, 2159 uint32_t mask) 2160 { 2161 struct smu_context *smu = handle; 2162 enum smu_clk_type clk_type; 2163 2164 switch (type) { 2165 case PP_SCLK: 2166 clk_type = SMU_SCLK; break; 2167 case PP_MCLK: 2168 clk_type = SMU_MCLK; break; 2169 case PP_PCIE: 2170 clk_type = SMU_PCIE; break; 2171 case PP_SOCCLK: 2172 clk_type = SMU_SOCCLK; break; 2173 case PP_FCLK: 2174 clk_type = SMU_FCLK; break; 2175 case PP_DCEFCLK: 2176 clk_type = SMU_DCEFCLK; break; 2177 case PP_VCLK: 2178 clk_type = SMU_VCLK; break; 2179 case PP_VCLK1: 2180 clk_type = SMU_VCLK1; break; 2181 case PP_DCLK: 2182 clk_type = SMU_DCLK; break; 2183 case PP_DCLK1: 2184 clk_type = SMU_DCLK1; break; 2185 case OD_SCLK: 2186 clk_type = SMU_OD_SCLK; break; 2187 case OD_MCLK: 2188 clk_type = SMU_OD_MCLK; break; 2189 case OD_VDDC_CURVE: 2190 clk_type = SMU_OD_VDDC_CURVE; break; 2191 case OD_RANGE: 2192 clk_type = SMU_OD_RANGE; break; 2193 default: 2194 return -EINVAL; 2195 } 2196 2197 return smu_force_smuclk_levels(smu, clk_type, mask); 2198 } 2199 2200 /* 2201 * On system suspending or resetting, the dpm_enabled 2202 * flag will be cleared. So that those SMU services which 2203 * are not supported will be gated. 2204 * However, the mp1 state setting should still be granted 2205 * even if the dpm_enabled cleared. 2206 */ 2207 static int smu_set_mp1_state(void *handle, 2208 enum pp_mp1_state mp1_state) 2209 { 2210 struct smu_context *smu = handle; 2211 int ret = 0; 2212 2213 if (!smu->pm_enabled) 2214 return -EOPNOTSUPP; 2215 2216 if (smu->ppt_funcs && 2217 smu->ppt_funcs->set_mp1_state) 2218 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2219 2220 return ret; 2221 } 2222 2223 static int smu_set_df_cstate(void *handle, 2224 enum pp_df_cstate state) 2225 { 2226 struct smu_context *smu = handle; 2227 int ret = 0; 2228 2229 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2230 return -EOPNOTSUPP; 2231 2232 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2233 return 0; 2234 2235 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2236 if (ret) 2237 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2238 2239 return ret; 2240 } 2241 2242 int smu_write_watermarks_table(struct smu_context *smu) 2243 { 2244 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2245 return -EOPNOTSUPP; 2246 2247 return smu_set_watermarks_table(smu, NULL); 2248 } 2249 2250 static int smu_set_watermarks_for_clock_ranges(void *handle, 2251 struct pp_smu_wm_range_sets *clock_ranges) 2252 { 2253 struct smu_context *smu = handle; 2254 2255 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2256 return -EOPNOTSUPP; 2257 2258 if (smu->disable_watermark) 2259 return 0; 2260 2261 return smu_set_watermarks_table(smu, clock_ranges); 2262 } 2263 2264 int smu_set_ac_dc(struct smu_context *smu) 2265 { 2266 int ret = 0; 2267 2268 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2269 return -EOPNOTSUPP; 2270 2271 /* controlled by firmware */ 2272 if (smu->dc_controlled_by_gpio) 2273 return 0; 2274 2275 ret = smu_set_power_source(smu, 2276 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2277 SMU_POWER_SOURCE_DC); 2278 if (ret) 2279 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2280 smu->adev->pm.ac_power ? "AC" : "DC"); 2281 2282 return ret; 2283 } 2284 2285 const struct amd_ip_funcs smu_ip_funcs = { 2286 .name = "smu", 2287 .early_init = smu_early_init, 2288 .late_init = smu_late_init, 2289 .sw_init = smu_sw_init, 2290 .sw_fini = smu_sw_fini, 2291 .hw_init = smu_hw_init, 2292 .hw_fini = smu_hw_fini, 2293 .late_fini = smu_late_fini, 2294 .suspend = smu_suspend, 2295 .resume = smu_resume, 2296 .is_idle = NULL, 2297 .check_soft_reset = NULL, 2298 .wait_for_idle = NULL, 2299 .soft_reset = NULL, 2300 .set_clockgating_state = smu_set_clockgating_state, 2301 .set_powergating_state = smu_set_powergating_state, 2302 }; 2303 2304 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2305 .type = AMD_IP_BLOCK_TYPE_SMC, 2306 .major = 11, 2307 .minor = 0, 2308 .rev = 0, 2309 .funcs = &smu_ip_funcs, 2310 }; 2311 2312 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2313 .type = AMD_IP_BLOCK_TYPE_SMC, 2314 .major = 12, 2315 .minor = 0, 2316 .rev = 0, 2317 .funcs = &smu_ip_funcs, 2318 }; 2319 2320 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2321 .type = AMD_IP_BLOCK_TYPE_SMC, 2322 .major = 13, 2323 .minor = 0, 2324 .rev = 0, 2325 .funcs = &smu_ip_funcs, 2326 }; 2327 2328 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2329 .type = AMD_IP_BLOCK_TYPE_SMC, 2330 .major = 14, 2331 .minor = 0, 2332 .rev = 0, 2333 .funcs = &smu_ip_funcs, 2334 }; 2335 2336 static int smu_load_microcode(void *handle) 2337 { 2338 struct smu_context *smu = handle; 2339 struct amdgpu_device *adev = smu->adev; 2340 int ret = 0; 2341 2342 if (!smu->pm_enabled) 2343 return -EOPNOTSUPP; 2344 2345 /* This should be used for non PSP loading */ 2346 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2347 return 0; 2348 2349 if (smu->ppt_funcs->load_microcode) { 2350 ret = smu->ppt_funcs->load_microcode(smu); 2351 if (ret) { 2352 dev_err(adev->dev, "Load microcode failed\n"); 2353 return ret; 2354 } 2355 } 2356 2357 if (smu->ppt_funcs->check_fw_status) { 2358 ret = smu->ppt_funcs->check_fw_status(smu); 2359 if (ret) { 2360 dev_err(adev->dev, "SMC is not ready\n"); 2361 return ret; 2362 } 2363 } 2364 2365 return ret; 2366 } 2367 2368 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2369 { 2370 int ret = 0; 2371 2372 if (smu->ppt_funcs->set_gfx_cgpg) 2373 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2374 2375 return ret; 2376 } 2377 2378 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2379 { 2380 struct smu_context *smu = handle; 2381 int ret = 0; 2382 2383 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2384 return -EOPNOTSUPP; 2385 2386 if (!smu->ppt_funcs->set_fan_speed_rpm) 2387 return -EOPNOTSUPP; 2388 2389 if (speed == U32_MAX) 2390 return -EINVAL; 2391 2392 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2393 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2394 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2395 smu->user_dpm_profile.fan_speed_rpm = speed; 2396 2397 /* Override custom PWM setting as they cannot co-exist */ 2398 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2399 smu->user_dpm_profile.fan_speed_pwm = 0; 2400 } 2401 2402 return ret; 2403 } 2404 2405 /** 2406 * smu_get_power_limit - Request one of the SMU Power Limits 2407 * 2408 * @handle: pointer to smu context 2409 * @limit: requested limit is written back to this variable 2410 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2411 * @pp_power_type: &pp_power_type type of power 2412 * Return: 0 on success, <0 on error 2413 * 2414 */ 2415 int smu_get_power_limit(void *handle, 2416 uint32_t *limit, 2417 enum pp_power_limit_level pp_limit_level, 2418 enum pp_power_type pp_power_type) 2419 { 2420 struct smu_context *smu = handle; 2421 struct amdgpu_device *adev = smu->adev; 2422 enum smu_ppt_limit_level limit_level; 2423 uint32_t limit_type; 2424 int ret = 0; 2425 2426 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2427 return -EOPNOTSUPP; 2428 2429 switch (pp_power_type) { 2430 case PP_PWR_TYPE_SUSTAINED: 2431 limit_type = SMU_DEFAULT_PPT_LIMIT; 2432 break; 2433 case PP_PWR_TYPE_FAST: 2434 limit_type = SMU_FAST_PPT_LIMIT; 2435 break; 2436 default: 2437 return -EOPNOTSUPP; 2438 } 2439 2440 switch (pp_limit_level) { 2441 case PP_PWR_LIMIT_CURRENT: 2442 limit_level = SMU_PPT_LIMIT_CURRENT; 2443 break; 2444 case PP_PWR_LIMIT_DEFAULT: 2445 limit_level = SMU_PPT_LIMIT_DEFAULT; 2446 break; 2447 case PP_PWR_LIMIT_MAX: 2448 limit_level = SMU_PPT_LIMIT_MAX; 2449 break; 2450 case PP_PWR_LIMIT_MIN: 2451 limit_level = SMU_PPT_LIMIT_MIN; 2452 break; 2453 default: 2454 return -EOPNOTSUPP; 2455 } 2456 2457 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2458 if (smu->ppt_funcs->get_ppt_limit) 2459 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2460 } else { 2461 switch (limit_level) { 2462 case SMU_PPT_LIMIT_CURRENT: 2463 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2464 case IP_VERSION(13, 0, 2): 2465 case IP_VERSION(11, 0, 7): 2466 case IP_VERSION(11, 0, 11): 2467 case IP_VERSION(11, 0, 12): 2468 case IP_VERSION(11, 0, 13): 2469 ret = smu_get_asic_power_limits(smu, 2470 &smu->current_power_limit, 2471 NULL, NULL, NULL); 2472 break; 2473 default: 2474 break; 2475 } 2476 *limit = smu->current_power_limit; 2477 break; 2478 case SMU_PPT_LIMIT_DEFAULT: 2479 *limit = smu->default_power_limit; 2480 break; 2481 case SMU_PPT_LIMIT_MAX: 2482 *limit = smu->max_power_limit; 2483 break; 2484 case SMU_PPT_LIMIT_MIN: 2485 *limit = smu->min_power_limit; 2486 break; 2487 default: 2488 return -EINVAL; 2489 } 2490 } 2491 2492 return ret; 2493 } 2494 2495 static int smu_set_power_limit(void *handle, uint32_t limit) 2496 { 2497 struct smu_context *smu = handle; 2498 uint32_t limit_type = limit >> 24; 2499 int ret = 0; 2500 2501 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2502 return -EOPNOTSUPP; 2503 2504 limit &= (1<<24)-1; 2505 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2506 if (smu->ppt_funcs->set_power_limit) 2507 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2508 2509 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2510 dev_err(smu->adev->dev, 2511 "New power limit (%d) is out of range [%d,%d]\n", 2512 limit, smu->min_power_limit, smu->max_power_limit); 2513 return -EINVAL; 2514 } 2515 2516 if (!limit) 2517 limit = smu->current_power_limit; 2518 2519 if (smu->ppt_funcs->set_power_limit) { 2520 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2521 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2522 smu->user_dpm_profile.power_limit = limit; 2523 } 2524 2525 return ret; 2526 } 2527 2528 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2529 { 2530 int ret = 0; 2531 2532 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2533 return -EOPNOTSUPP; 2534 2535 if (smu->ppt_funcs->print_clk_levels) 2536 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2537 2538 return ret; 2539 } 2540 2541 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2542 { 2543 enum smu_clk_type clk_type; 2544 2545 switch (type) { 2546 case PP_SCLK: 2547 clk_type = SMU_SCLK; break; 2548 case PP_MCLK: 2549 clk_type = SMU_MCLK; break; 2550 case PP_PCIE: 2551 clk_type = SMU_PCIE; break; 2552 case PP_SOCCLK: 2553 clk_type = SMU_SOCCLK; break; 2554 case PP_FCLK: 2555 clk_type = SMU_FCLK; break; 2556 case PP_DCEFCLK: 2557 clk_type = SMU_DCEFCLK; break; 2558 case PP_VCLK: 2559 clk_type = SMU_VCLK; break; 2560 case PP_VCLK1: 2561 clk_type = SMU_VCLK1; break; 2562 case PP_DCLK: 2563 clk_type = SMU_DCLK; break; 2564 case PP_DCLK1: 2565 clk_type = SMU_DCLK1; break; 2566 case OD_SCLK: 2567 clk_type = SMU_OD_SCLK; break; 2568 case OD_MCLK: 2569 clk_type = SMU_OD_MCLK; break; 2570 case OD_VDDC_CURVE: 2571 clk_type = SMU_OD_VDDC_CURVE; break; 2572 case OD_RANGE: 2573 clk_type = SMU_OD_RANGE; break; 2574 case OD_VDDGFX_OFFSET: 2575 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2576 case OD_CCLK: 2577 clk_type = SMU_OD_CCLK; break; 2578 case OD_FAN_CURVE: 2579 clk_type = SMU_OD_FAN_CURVE; break; 2580 case OD_ACOUSTIC_LIMIT: 2581 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2582 case OD_ACOUSTIC_TARGET: 2583 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2584 case OD_FAN_TARGET_TEMPERATURE: 2585 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2586 case OD_FAN_MINIMUM_PWM: 2587 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2588 default: 2589 clk_type = SMU_CLK_COUNT; break; 2590 } 2591 2592 return clk_type; 2593 } 2594 2595 static int smu_print_ppclk_levels(void *handle, 2596 enum pp_clock_type type, 2597 char *buf) 2598 { 2599 struct smu_context *smu = handle; 2600 enum smu_clk_type clk_type; 2601 2602 clk_type = smu_convert_to_smuclk(type); 2603 if (clk_type == SMU_CLK_COUNT) 2604 return -EINVAL; 2605 2606 return smu_print_smuclk_levels(smu, clk_type, buf); 2607 } 2608 2609 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2610 { 2611 struct smu_context *smu = handle; 2612 enum smu_clk_type clk_type; 2613 2614 clk_type = smu_convert_to_smuclk(type); 2615 if (clk_type == SMU_CLK_COUNT) 2616 return -EINVAL; 2617 2618 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2619 return -EOPNOTSUPP; 2620 2621 if (!smu->ppt_funcs->emit_clk_levels) 2622 return -ENOENT; 2623 2624 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2625 2626 } 2627 2628 static int smu_od_edit_dpm_table(void *handle, 2629 enum PP_OD_DPM_TABLE_COMMAND type, 2630 long *input, uint32_t size) 2631 { 2632 struct smu_context *smu = handle; 2633 int ret = 0; 2634 2635 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2636 return -EOPNOTSUPP; 2637 2638 if (smu->ppt_funcs->od_edit_dpm_table) { 2639 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2640 } 2641 2642 return ret; 2643 } 2644 2645 static int smu_read_sensor(void *handle, 2646 int sensor, 2647 void *data, 2648 int *size_arg) 2649 { 2650 struct smu_context *smu = handle; 2651 struct smu_umd_pstate_table *pstate_table = 2652 &smu->pstate_table; 2653 int ret = 0; 2654 uint32_t *size, size_val; 2655 2656 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2657 return -EOPNOTSUPP; 2658 2659 if (!data || !size_arg) 2660 return -EINVAL; 2661 2662 size_val = *size_arg; 2663 size = &size_val; 2664 2665 if (smu->ppt_funcs->read_sensor) 2666 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2667 goto unlock; 2668 2669 switch (sensor) { 2670 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2671 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2672 *size = 4; 2673 break; 2674 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2675 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2676 *size = 4; 2677 break; 2678 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2679 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2680 *size = 4; 2681 break; 2682 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2683 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2684 *size = 4; 2685 break; 2686 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2687 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2688 *size = 8; 2689 break; 2690 case AMDGPU_PP_SENSOR_UVD_POWER: 2691 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2692 *size = 4; 2693 break; 2694 case AMDGPU_PP_SENSOR_VCE_POWER: 2695 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2696 *size = 4; 2697 break; 2698 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2699 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2700 *size = 4; 2701 break; 2702 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2703 *(uint32_t *)data = 0; 2704 *size = 4; 2705 break; 2706 default: 2707 *size = 0; 2708 ret = -EOPNOTSUPP; 2709 break; 2710 } 2711 2712 unlock: 2713 // assign uint32_t to int 2714 *size_arg = size_val; 2715 2716 return ret; 2717 } 2718 2719 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2720 { 2721 int ret = -EINVAL; 2722 struct smu_context *smu = handle; 2723 2724 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2725 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2726 2727 return ret; 2728 } 2729 2730 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2731 { 2732 int ret = -EINVAL; 2733 struct smu_context *smu = handle; 2734 2735 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2736 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2737 2738 return ret; 2739 } 2740 2741 static int smu_get_power_profile_mode(void *handle, char *buf) 2742 { 2743 struct smu_context *smu = handle; 2744 2745 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2746 !smu->ppt_funcs->get_power_profile_mode) 2747 return -EOPNOTSUPP; 2748 if (!buf) 2749 return -EINVAL; 2750 2751 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2752 } 2753 2754 static int smu_set_power_profile_mode(void *handle, 2755 long *param, 2756 uint32_t param_size) 2757 { 2758 struct smu_context *smu = handle; 2759 2760 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2761 !smu->ppt_funcs->set_power_profile_mode) 2762 return -EOPNOTSUPP; 2763 2764 return smu_bump_power_profile_mode(smu, param, param_size); 2765 } 2766 2767 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2768 { 2769 struct smu_context *smu = handle; 2770 2771 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2772 return -EOPNOTSUPP; 2773 2774 if (!smu->ppt_funcs->get_fan_control_mode) 2775 return -EOPNOTSUPP; 2776 2777 if (!fan_mode) 2778 return -EINVAL; 2779 2780 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2781 2782 return 0; 2783 } 2784 2785 static int smu_set_fan_control_mode(void *handle, u32 value) 2786 { 2787 struct smu_context *smu = handle; 2788 int ret = 0; 2789 2790 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2791 return -EOPNOTSUPP; 2792 2793 if (!smu->ppt_funcs->set_fan_control_mode) 2794 return -EOPNOTSUPP; 2795 2796 if (value == U32_MAX) 2797 return -EINVAL; 2798 2799 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2800 if (ret) 2801 goto out; 2802 2803 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2804 smu->user_dpm_profile.fan_mode = value; 2805 2806 /* reset user dpm fan speed */ 2807 if (value != AMD_FAN_CTRL_MANUAL) { 2808 smu->user_dpm_profile.fan_speed_pwm = 0; 2809 smu->user_dpm_profile.fan_speed_rpm = 0; 2810 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2811 } 2812 } 2813 2814 out: 2815 return ret; 2816 } 2817 2818 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2819 { 2820 struct smu_context *smu = handle; 2821 int ret = 0; 2822 2823 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2824 return -EOPNOTSUPP; 2825 2826 if (!smu->ppt_funcs->get_fan_speed_pwm) 2827 return -EOPNOTSUPP; 2828 2829 if (!speed) 2830 return -EINVAL; 2831 2832 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2833 2834 return ret; 2835 } 2836 2837 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2838 { 2839 struct smu_context *smu = handle; 2840 int ret = 0; 2841 2842 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2843 return -EOPNOTSUPP; 2844 2845 if (!smu->ppt_funcs->set_fan_speed_pwm) 2846 return -EOPNOTSUPP; 2847 2848 if (speed == U32_MAX) 2849 return -EINVAL; 2850 2851 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2852 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2853 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2854 smu->user_dpm_profile.fan_speed_pwm = speed; 2855 2856 /* Override custom RPM setting as they cannot co-exist */ 2857 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2858 smu->user_dpm_profile.fan_speed_rpm = 0; 2859 } 2860 2861 return ret; 2862 } 2863 2864 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2865 { 2866 struct smu_context *smu = handle; 2867 int ret = 0; 2868 2869 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2870 return -EOPNOTSUPP; 2871 2872 if (!smu->ppt_funcs->get_fan_speed_rpm) 2873 return -EOPNOTSUPP; 2874 2875 if (!speed) 2876 return -EINVAL; 2877 2878 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2879 2880 return ret; 2881 } 2882 2883 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2884 { 2885 struct smu_context *smu = handle; 2886 2887 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2888 return -EOPNOTSUPP; 2889 2890 return smu_set_min_dcef_deep_sleep(smu, clk); 2891 } 2892 2893 static int smu_get_clock_by_type_with_latency(void *handle, 2894 enum amd_pp_clock_type type, 2895 struct pp_clock_levels_with_latency *clocks) 2896 { 2897 struct smu_context *smu = handle; 2898 enum smu_clk_type clk_type; 2899 int ret = 0; 2900 2901 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2902 return -EOPNOTSUPP; 2903 2904 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2905 switch (type) { 2906 case amd_pp_sys_clock: 2907 clk_type = SMU_GFXCLK; 2908 break; 2909 case amd_pp_mem_clock: 2910 clk_type = SMU_MCLK; 2911 break; 2912 case amd_pp_dcef_clock: 2913 clk_type = SMU_DCEFCLK; 2914 break; 2915 case amd_pp_disp_clock: 2916 clk_type = SMU_DISPCLK; 2917 break; 2918 default: 2919 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2920 return -EINVAL; 2921 } 2922 2923 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2924 } 2925 2926 return ret; 2927 } 2928 2929 static int smu_display_clock_voltage_request(void *handle, 2930 struct pp_display_clock_request *clock_req) 2931 { 2932 struct smu_context *smu = handle; 2933 int ret = 0; 2934 2935 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2936 return -EOPNOTSUPP; 2937 2938 if (smu->ppt_funcs->display_clock_voltage_request) 2939 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2940 2941 return ret; 2942 } 2943 2944 2945 static int smu_display_disable_memory_clock_switch(void *handle, 2946 bool disable_memory_clock_switch) 2947 { 2948 struct smu_context *smu = handle; 2949 int ret = -EINVAL; 2950 2951 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2952 return -EOPNOTSUPP; 2953 2954 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2955 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2956 2957 return ret; 2958 } 2959 2960 static int smu_set_xgmi_pstate(void *handle, 2961 uint32_t pstate) 2962 { 2963 struct smu_context *smu = handle; 2964 int ret = 0; 2965 2966 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2967 return -EOPNOTSUPP; 2968 2969 if (smu->ppt_funcs->set_xgmi_pstate) 2970 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2971 2972 if (ret) 2973 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2974 2975 return ret; 2976 } 2977 2978 static int smu_get_baco_capability(void *handle, bool *cap) 2979 { 2980 struct smu_context *smu = handle; 2981 2982 *cap = false; 2983 2984 if (!smu->pm_enabled) 2985 return 0; 2986 2987 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2988 *cap = smu->ppt_funcs->baco_is_support(smu); 2989 2990 return 0; 2991 } 2992 2993 static int smu_baco_set_state(void *handle, int state) 2994 { 2995 struct smu_context *smu = handle; 2996 int ret = 0; 2997 2998 if (!smu->pm_enabled) 2999 return -EOPNOTSUPP; 3000 3001 if (state == 0) { 3002 if (smu->ppt_funcs->baco_exit) 3003 ret = smu->ppt_funcs->baco_exit(smu); 3004 } else if (state == 1) { 3005 if (smu->ppt_funcs->baco_enter) 3006 ret = smu->ppt_funcs->baco_enter(smu); 3007 } else { 3008 return -EINVAL; 3009 } 3010 3011 if (ret) 3012 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3013 (state)?"enter":"exit"); 3014 3015 return ret; 3016 } 3017 3018 bool smu_mode1_reset_is_support(struct smu_context *smu) 3019 { 3020 bool ret = false; 3021 3022 if (!smu->pm_enabled) 3023 return false; 3024 3025 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3026 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3027 3028 return ret; 3029 } 3030 3031 bool smu_mode2_reset_is_support(struct smu_context *smu) 3032 { 3033 bool ret = false; 3034 3035 if (!smu->pm_enabled) 3036 return false; 3037 3038 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3039 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3040 3041 return ret; 3042 } 3043 3044 int smu_mode1_reset(struct smu_context *smu) 3045 { 3046 int ret = 0; 3047 3048 if (!smu->pm_enabled) 3049 return -EOPNOTSUPP; 3050 3051 if (smu->ppt_funcs->mode1_reset) 3052 ret = smu->ppt_funcs->mode1_reset(smu); 3053 3054 return ret; 3055 } 3056 3057 static int smu_mode2_reset(void *handle) 3058 { 3059 struct smu_context *smu = handle; 3060 int ret = 0; 3061 3062 if (!smu->pm_enabled) 3063 return -EOPNOTSUPP; 3064 3065 if (smu->ppt_funcs->mode2_reset) 3066 ret = smu->ppt_funcs->mode2_reset(smu); 3067 3068 if (ret) 3069 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3070 3071 return ret; 3072 } 3073 3074 static int smu_enable_gfx_features(void *handle) 3075 { 3076 struct smu_context *smu = handle; 3077 int ret = 0; 3078 3079 if (!smu->pm_enabled) 3080 return -EOPNOTSUPP; 3081 3082 if (smu->ppt_funcs->enable_gfx_features) 3083 ret = smu->ppt_funcs->enable_gfx_features(smu); 3084 3085 if (ret) 3086 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3087 3088 return ret; 3089 } 3090 3091 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3092 struct pp_smu_nv_clock_table *max_clocks) 3093 { 3094 struct smu_context *smu = handle; 3095 int ret = 0; 3096 3097 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3098 return -EOPNOTSUPP; 3099 3100 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3101 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3102 3103 return ret; 3104 } 3105 3106 static int smu_get_uclk_dpm_states(void *handle, 3107 unsigned int *clock_values_in_khz, 3108 unsigned int *num_states) 3109 { 3110 struct smu_context *smu = handle; 3111 int ret = 0; 3112 3113 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3114 return -EOPNOTSUPP; 3115 3116 if (smu->ppt_funcs->get_uclk_dpm_states) 3117 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3118 3119 return ret; 3120 } 3121 3122 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3123 { 3124 struct smu_context *smu = handle; 3125 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3126 3127 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3128 return -EOPNOTSUPP; 3129 3130 if (smu->ppt_funcs->get_current_power_state) 3131 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3132 3133 return pm_state; 3134 } 3135 3136 static int smu_get_dpm_clock_table(void *handle, 3137 struct dpm_clocks *clock_table) 3138 { 3139 struct smu_context *smu = handle; 3140 int ret = 0; 3141 3142 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3143 return -EOPNOTSUPP; 3144 3145 if (smu->ppt_funcs->get_dpm_clock_table) 3146 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3147 3148 return ret; 3149 } 3150 3151 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3152 { 3153 struct smu_context *smu = handle; 3154 3155 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3156 return -EOPNOTSUPP; 3157 3158 if (!smu->ppt_funcs->get_gpu_metrics) 3159 return -EOPNOTSUPP; 3160 3161 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3162 } 3163 3164 static int smu_enable_mgpu_fan_boost(void *handle) 3165 { 3166 struct smu_context *smu = handle; 3167 int ret = 0; 3168 3169 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3170 return -EOPNOTSUPP; 3171 3172 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3173 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3174 3175 return ret; 3176 } 3177 3178 static int smu_gfx_state_change_set(void *handle, 3179 uint32_t state) 3180 { 3181 struct smu_context *smu = handle; 3182 int ret = 0; 3183 3184 if (smu->ppt_funcs->gfx_state_change_set) 3185 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3186 3187 return ret; 3188 } 3189 3190 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3191 { 3192 int ret = 0; 3193 3194 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3195 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3196 3197 return ret; 3198 } 3199 3200 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3201 { 3202 int ret = -EOPNOTSUPP; 3203 3204 if (smu->ppt_funcs && 3205 smu->ppt_funcs->get_ecc_info) 3206 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3207 3208 return ret; 3209 3210 } 3211 3212 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3213 { 3214 struct smu_context *smu = handle; 3215 struct smu_table_context *smu_table = &smu->smu_table; 3216 struct smu_table *memory_pool = &smu_table->memory_pool; 3217 3218 if (!addr || !size) 3219 return -EINVAL; 3220 3221 *addr = NULL; 3222 *size = 0; 3223 if (memory_pool->bo) { 3224 *addr = memory_pool->cpu_addr; 3225 *size = memory_pool->size; 3226 } 3227 3228 return 0; 3229 } 3230 3231 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 3232 enum pp_xgmi_plpd_mode mode) 3233 { 3234 int ret = -EOPNOTSUPP; 3235 3236 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3237 return ret; 3238 3239 /* PLPD policy is not supported if it's NONE */ 3240 if (smu->plpd_mode == XGMI_PLPD_NONE) 3241 return ret; 3242 3243 if (smu->plpd_mode == mode) 3244 return 0; 3245 3246 if (smu->ppt_funcs && smu->ppt_funcs->select_xgmi_plpd_policy) 3247 ret = smu->ppt_funcs->select_xgmi_plpd_policy(smu, mode); 3248 3249 if (!ret) 3250 smu->plpd_mode = mode; 3251 3252 return ret; 3253 } 3254 3255 static const struct amd_pm_funcs swsmu_pm_funcs = { 3256 /* export for sysfs */ 3257 .set_fan_control_mode = smu_set_fan_control_mode, 3258 .get_fan_control_mode = smu_get_fan_control_mode, 3259 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3260 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3261 .force_clock_level = smu_force_ppclk_levels, 3262 .print_clock_levels = smu_print_ppclk_levels, 3263 .emit_clock_levels = smu_emit_ppclk_levels, 3264 .force_performance_level = smu_force_performance_level, 3265 .read_sensor = smu_read_sensor, 3266 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3267 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3268 .get_performance_level = smu_get_performance_level, 3269 .get_current_power_state = smu_get_current_power_state, 3270 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3271 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3272 .get_pp_num_states = smu_get_power_num_states, 3273 .get_pp_table = smu_sys_get_pp_table, 3274 .set_pp_table = smu_sys_set_pp_table, 3275 .switch_power_profile = smu_switch_power_profile, 3276 /* export to amdgpu */ 3277 .dispatch_tasks = smu_handle_dpm_task, 3278 .load_firmware = smu_load_microcode, 3279 .set_powergating_by_smu = smu_dpm_set_power_gate, 3280 .set_power_limit = smu_set_power_limit, 3281 .get_power_limit = smu_get_power_limit, 3282 .get_power_profile_mode = smu_get_power_profile_mode, 3283 .set_power_profile_mode = smu_set_power_profile_mode, 3284 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3285 .set_mp1_state = smu_set_mp1_state, 3286 .gfx_state_change_set = smu_gfx_state_change_set, 3287 /* export to DC */ 3288 .get_sclk = smu_get_sclk, 3289 .get_mclk = smu_get_mclk, 3290 .display_configuration_change = smu_display_configuration_change, 3291 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3292 .display_clock_voltage_request = smu_display_clock_voltage_request, 3293 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3294 .set_active_display_count = smu_set_display_count, 3295 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3296 .get_asic_baco_capability = smu_get_baco_capability, 3297 .set_asic_baco_state = smu_baco_set_state, 3298 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3299 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3300 .asic_reset_mode_2 = smu_mode2_reset, 3301 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3302 .set_df_cstate = smu_set_df_cstate, 3303 .set_xgmi_pstate = smu_set_xgmi_pstate, 3304 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3305 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3306 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3307 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3308 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3309 .get_dpm_clock_table = smu_get_dpm_clock_table, 3310 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3311 }; 3312 3313 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3314 uint64_t event_arg) 3315 { 3316 int ret = -EINVAL; 3317 3318 if (smu->ppt_funcs->wait_for_event) 3319 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3320 3321 return ret; 3322 } 3323 3324 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3325 { 3326 3327 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3328 return -EOPNOTSUPP; 3329 3330 /* Confirm the buffer allocated is of correct size */ 3331 if (size != smu->stb_context.stb_buf_size) 3332 return -EINVAL; 3333 3334 /* 3335 * No need to lock smu mutex as we access STB directly through MMIO 3336 * and not going through SMU messaging route (for now at least). 3337 * For registers access rely on implementation internal locking. 3338 */ 3339 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3340 } 3341 3342 #if defined(CONFIG_DEBUG_FS) 3343 3344 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3345 { 3346 struct amdgpu_device *adev = filp->f_inode->i_private; 3347 struct smu_context *smu = adev->powerplay.pp_handle; 3348 unsigned char *buf; 3349 int r; 3350 3351 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3352 if (!buf) 3353 return -ENOMEM; 3354 3355 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3356 if (r) 3357 goto out; 3358 3359 filp->private_data = buf; 3360 3361 return 0; 3362 3363 out: 3364 kvfree(buf); 3365 return r; 3366 } 3367 3368 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3369 loff_t *pos) 3370 { 3371 struct amdgpu_device *adev = filp->f_inode->i_private; 3372 struct smu_context *smu = adev->powerplay.pp_handle; 3373 3374 3375 if (!filp->private_data) 3376 return -EINVAL; 3377 3378 return simple_read_from_buffer(buf, 3379 size, 3380 pos, filp->private_data, 3381 smu->stb_context.stb_buf_size); 3382 } 3383 3384 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3385 { 3386 kvfree(filp->private_data); 3387 filp->private_data = NULL; 3388 3389 return 0; 3390 } 3391 3392 /* 3393 * We have to define not only read method but also 3394 * open and release because .read takes up to PAGE_SIZE 3395 * data each time so and so is invoked multiple times. 3396 * We allocate the STB buffer in .open and release it 3397 * in .release 3398 */ 3399 static const struct file_operations smu_stb_debugfs_fops = { 3400 .owner = THIS_MODULE, 3401 .open = smu_stb_debugfs_open, 3402 .read = smu_stb_debugfs_read, 3403 .release = smu_stb_debugfs_release, 3404 .llseek = default_llseek, 3405 }; 3406 3407 #endif 3408 3409 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3410 { 3411 #if defined(CONFIG_DEBUG_FS) 3412 3413 struct smu_context *smu = adev->powerplay.pp_handle; 3414 3415 if (!smu || (!smu->stb_context.stb_buf_size)) 3416 return; 3417 3418 debugfs_create_file_size("amdgpu_smu_stb_dump", 3419 S_IRUSR, 3420 adev_to_drm(adev)->primary->debugfs_root, 3421 adev, 3422 &smu_stb_debugfs_fops, 3423 smu->stb_context.stb_buf_size); 3424 #endif 3425 } 3426 3427 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3428 { 3429 int ret = 0; 3430 3431 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3432 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3433 3434 return ret; 3435 } 3436 3437 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3438 { 3439 int ret = 0; 3440 3441 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3442 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3443 3444 return ret; 3445 } 3446