1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77 static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); 80 static int smu_od_edit_dpm_table(void *handle, 81 enum PP_OD_DPM_TABLE_COMMAND type, 82 long *input, uint32_t size); 83 84 static int smu_sys_get_pp_feature_mask(void *handle, 85 char *buf) 86 { 87 struct smu_context *smu = handle; 88 89 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 90 return -EOPNOTSUPP; 91 92 return smu_get_pp_feature_mask(smu, buf); 93 } 94 95 static int smu_sys_set_pp_feature_mask(void *handle, 96 uint64_t new_mask) 97 { 98 struct smu_context *smu = handle; 99 100 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 101 return -EOPNOTSUPP; 102 103 return smu_set_pp_feature_mask(smu, new_mask); 104 } 105 106 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 107 { 108 if (!smu->ppt_funcs->set_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_set_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_residency) 117 return -EINVAL; 118 119 return smu_get_gfx_off_residency(smu, value); 120 } 121 122 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_entrycount) 125 return -EINVAL; 126 127 return smu_get_gfx_off_entrycount(smu, value); 128 } 129 130 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 131 { 132 if (!smu->ppt_funcs->get_gfx_off_status) 133 return -EINVAL; 134 135 *value = smu_get_gfx_off_status(smu); 136 137 return 0; 138 } 139 140 int smu_set_soft_freq_range(struct smu_context *smu, 141 enum pp_clock_type type, 142 uint32_t min, 143 uint32_t max) 144 { 145 enum smu_clk_type clk_type; 146 int ret = 0; 147 148 clk_type = smu_convert_to_smuclk(type); 149 if (clk_type == SMU_CLK_COUNT) 150 return -EINVAL; 151 152 if (smu->ppt_funcs->set_soft_freq_limited_range) 153 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 154 clk_type, 155 min, 156 max, 157 false); 158 159 return ret; 160 } 161 162 int smu_get_dpm_freq_range(struct smu_context *smu, 163 enum smu_clk_type clk_type, 164 uint32_t *min, 165 uint32_t *max) 166 { 167 int ret = -ENOTSUPP; 168 169 if (!min && !max) 170 return -EINVAL; 171 172 if (smu->ppt_funcs->get_dpm_ultimate_freq) 173 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 174 clk_type, 175 min, 176 max); 177 178 return ret; 179 } 180 181 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 182 { 183 int ret = 0; 184 struct amdgpu_device *adev = smu->adev; 185 186 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 187 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 188 if (ret) 189 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 190 } 191 return ret; 192 } 193 194 static u32 smu_get_mclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static u32 smu_get_sclk(void *handle, bool low) 209 { 210 struct smu_context *smu = handle; 211 uint32_t clk_freq; 212 int ret = 0; 213 214 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 215 low ? &clk_freq : NULL, 216 !low ? &clk_freq : NULL); 217 if (ret) 218 return 0; 219 return clk_freq * 100; 220 } 221 222 static int smu_set_gfx_imu_enable(struct smu_context *smu) 223 { 224 struct amdgpu_device *adev = smu->adev; 225 226 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 227 return 0; 228 229 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 230 return 0; 231 232 return smu_set_gfx_power_up_by_imu(smu); 233 } 234 235 static bool is_vcn_enabled(struct amdgpu_device *adev) 236 { 237 int i; 238 239 for (i = 0; i < adev->num_ip_blocks; i++) { 240 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 241 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 242 !adev->ip_blocks[i].status.valid) 243 return false; 244 } 245 246 return true; 247 } 248 249 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 250 bool enable, 251 int inst) 252 { 253 struct smu_power_context *smu_power = &smu->smu_power; 254 struct smu_power_gate *power_gate = &smu_power->power_gate; 255 int ret = 0; 256 257 /* 258 * don't poweron vcn/jpeg when they are skipped. 259 */ 260 if (!is_vcn_enabled(smu->adev)) 261 return 0; 262 263 if (!smu->ppt_funcs->dpm_set_vcn_enable) 264 return 0; 265 266 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 267 return 0; 268 269 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 270 if (!ret) 271 atomic_set(&power_gate->vcn_gated[inst], !enable); 272 273 return ret; 274 } 275 276 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 277 bool enable) 278 { 279 struct smu_power_context *smu_power = &smu->smu_power; 280 struct smu_power_gate *power_gate = &smu_power->power_gate; 281 int ret = 0; 282 283 if (!is_vcn_enabled(smu->adev)) 284 return 0; 285 286 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 287 return 0; 288 289 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 290 return 0; 291 292 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 293 if (!ret) 294 atomic_set(&power_gate->jpeg_gated, !enable); 295 296 return ret; 297 } 298 299 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 300 bool enable) 301 { 302 struct smu_power_context *smu_power = &smu->smu_power; 303 struct smu_power_gate *power_gate = &smu_power->power_gate; 304 int ret = 0; 305 306 if (!smu->ppt_funcs->dpm_set_vpe_enable) 307 return 0; 308 309 if (atomic_read(&power_gate->vpe_gated) ^ enable) 310 return 0; 311 312 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 313 if (!ret) 314 atomic_set(&power_gate->vpe_gated, !enable); 315 316 return ret; 317 } 318 319 static int smu_dpm_set_isp_enable(struct smu_context *smu, 320 bool enable) 321 { 322 struct smu_power_context *smu_power = &smu->smu_power; 323 struct smu_power_gate *power_gate = &smu_power->power_gate; 324 int ret; 325 326 if (!smu->ppt_funcs->dpm_set_isp_enable) 327 return 0; 328 329 if (atomic_read(&power_gate->isp_gated) ^ enable) 330 return 0; 331 332 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable); 333 if (!ret) 334 atomic_set(&power_gate->isp_gated, !enable); 335 336 return ret; 337 } 338 339 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 340 bool enable) 341 { 342 struct smu_power_context *smu_power = &smu->smu_power; 343 struct smu_power_gate *power_gate = &smu_power->power_gate; 344 int ret = 0; 345 346 if (!smu->adev->enable_umsch_mm) 347 return 0; 348 349 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 350 return 0; 351 352 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 353 return 0; 354 355 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 356 if (!ret) 357 atomic_set(&power_gate->umsch_mm_gated, !enable); 358 359 return ret; 360 } 361 362 static int smu_set_mall_enable(struct smu_context *smu) 363 { 364 int ret = 0; 365 366 if (!smu->ppt_funcs->set_mall_enable) 367 return 0; 368 369 ret = smu->ppt_funcs->set_mall_enable(smu); 370 371 return ret; 372 } 373 374 /** 375 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 376 * 377 * @handle: smu_context pointer 378 * @block_type: the IP block to power gate/ungate 379 * @gate: to power gate if true, ungate otherwise 380 * @inst: the instance of the IP block to power gate/ungate 381 * 382 * This API uses no smu->mutex lock protection due to: 383 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 384 * This is guarded to be race condition free by the caller. 385 * 2. Or get called on user setting request of power_dpm_force_performance_level. 386 * Under this case, the smu->mutex lock protection is already enforced on 387 * the parent API smu_force_performance_level of the call path. 388 */ 389 static int smu_dpm_set_power_gate(void *handle, 390 uint32_t block_type, 391 bool gate, 392 int inst) 393 { 394 struct smu_context *smu = handle; 395 int ret = 0; 396 397 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 398 dev_WARN(smu->adev->dev, 399 "SMU uninitialized but power %s requested for %u!\n", 400 gate ? "gate" : "ungate", block_type); 401 return -EOPNOTSUPP; 402 } 403 404 switch (block_type) { 405 /* 406 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 407 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 408 */ 409 case AMD_IP_BLOCK_TYPE_UVD: 410 case AMD_IP_BLOCK_TYPE_VCN: 411 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 412 if (ret) 413 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 414 gate ? "gate" : "ungate", inst); 415 break; 416 case AMD_IP_BLOCK_TYPE_GFX: 417 ret = smu_gfx_off_control(smu, gate); 418 if (ret) 419 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 420 gate ? "enable" : "disable"); 421 break; 422 case AMD_IP_BLOCK_TYPE_SDMA: 423 ret = smu_powergate_sdma(smu, gate); 424 if (ret) 425 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 426 gate ? "gate" : "ungate"); 427 break; 428 case AMD_IP_BLOCK_TYPE_JPEG: 429 ret = smu_dpm_set_jpeg_enable(smu, !gate); 430 if (ret) 431 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 432 gate ? "gate" : "ungate"); 433 break; 434 case AMD_IP_BLOCK_TYPE_VPE: 435 ret = smu_dpm_set_vpe_enable(smu, !gate); 436 if (ret) 437 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 438 gate ? "gate" : "ungate"); 439 break; 440 case AMD_IP_BLOCK_TYPE_ISP: 441 ret = smu_dpm_set_isp_enable(smu, !gate); 442 if (ret) 443 dev_err(smu->adev->dev, "Failed to power %s ISP!\n", 444 gate ? "gate" : "ungate"); 445 break; 446 default: 447 dev_err(smu->adev->dev, "Unsupported block type!\n"); 448 return -EINVAL; 449 } 450 451 return ret; 452 } 453 454 /** 455 * smu_set_user_clk_dependencies - set user profile clock dependencies 456 * 457 * @smu: smu_context pointer 458 * @clk: enum smu_clk_type type 459 * 460 * Enable/Disable the clock dependency for the @clk type. 461 */ 462 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 463 { 464 if (smu->adev->in_suspend) 465 return; 466 467 if (clk == SMU_MCLK) { 468 smu->user_dpm_profile.clk_dependency = 0; 469 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 470 } else if (clk == SMU_FCLK) { 471 /* MCLK takes precedence over FCLK */ 472 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 473 return; 474 475 smu->user_dpm_profile.clk_dependency = 0; 476 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 477 } else if (clk == SMU_SOCCLK) { 478 /* MCLK takes precedence over SOCCLK */ 479 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 480 return; 481 482 smu->user_dpm_profile.clk_dependency = 0; 483 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 484 } else 485 /* Add clk dependencies here, if any */ 486 return; 487 } 488 489 /** 490 * smu_restore_dpm_user_profile - reinstate user dpm profile 491 * 492 * @smu: smu_context pointer 493 * 494 * Restore the saved user power configurations include power limit, 495 * clock frequencies, fan control mode and fan speed. 496 */ 497 static void smu_restore_dpm_user_profile(struct smu_context *smu) 498 { 499 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 500 int ret = 0; 501 502 if (!smu->adev->in_suspend) 503 return; 504 505 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 506 return; 507 508 /* Enable restore flag */ 509 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 510 511 /* set the user dpm power limit */ 512 if (smu->user_dpm_profile.power_limit) { 513 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 514 if (ret) 515 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 516 } 517 518 /* set the user dpm clock configurations */ 519 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 520 enum smu_clk_type clk_type; 521 522 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 523 /* 524 * Iterate over smu clk type and force the saved user clk 525 * configs, skip if clock dependency is enabled 526 */ 527 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 528 smu->user_dpm_profile.clk_mask[clk_type]) { 529 ret = smu_force_smuclk_levels(smu, clk_type, 530 smu->user_dpm_profile.clk_mask[clk_type]); 531 if (ret) 532 dev_err(smu->adev->dev, 533 "Failed to set clock type = %d\n", clk_type); 534 } 535 } 536 } 537 538 /* set the user dpm fan configurations */ 539 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 540 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 541 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 542 if (ret != -EOPNOTSUPP) { 543 smu->user_dpm_profile.fan_speed_pwm = 0; 544 smu->user_dpm_profile.fan_speed_rpm = 0; 545 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 546 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 547 } 548 549 if (smu->user_dpm_profile.fan_speed_pwm) { 550 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 551 if (ret != -EOPNOTSUPP) 552 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 553 } 554 555 if (smu->user_dpm_profile.fan_speed_rpm) { 556 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 557 if (ret != -EOPNOTSUPP) 558 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 559 } 560 } 561 562 /* Restore user customized OD settings */ 563 if (smu->user_dpm_profile.user_od) { 564 if (smu->ppt_funcs->restore_user_od_settings) { 565 ret = smu->ppt_funcs->restore_user_od_settings(smu); 566 if (ret) 567 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 568 } 569 } 570 571 /* Disable restore flag */ 572 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 573 } 574 575 static int smu_get_power_num_states(void *handle, 576 struct pp_states_info *state_info) 577 { 578 if (!state_info) 579 return -EINVAL; 580 581 /* not support power state */ 582 memset(state_info, 0, sizeof(struct pp_states_info)); 583 state_info->nums = 1; 584 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 585 586 return 0; 587 } 588 589 bool is_support_sw_smu(struct amdgpu_device *adev) 590 { 591 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 592 if (adev->asic_type == CHIP_VEGA20) 593 return false; 594 595 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 596 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 597 return true; 598 599 return false; 600 } 601 602 bool is_support_cclk_dpm(struct amdgpu_device *adev) 603 { 604 struct smu_context *smu = adev->powerplay.pp_handle; 605 606 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 607 return false; 608 609 return true; 610 } 611 612 613 static int smu_sys_get_pp_table(void *handle, 614 char **table) 615 { 616 struct smu_context *smu = handle; 617 struct smu_table_context *smu_table = &smu->smu_table; 618 619 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 620 return -EOPNOTSUPP; 621 622 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 623 return -EINVAL; 624 625 if (smu_table->hardcode_pptable) 626 *table = smu_table->hardcode_pptable; 627 else 628 *table = smu_table->power_play_table; 629 630 return smu_table->power_play_table_size; 631 } 632 633 static int smu_sys_set_pp_table(void *handle, 634 const char *buf, 635 size_t size) 636 { 637 struct smu_context *smu = handle; 638 struct smu_table_context *smu_table = &smu->smu_table; 639 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 640 int ret = 0; 641 642 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 643 return -EOPNOTSUPP; 644 645 if (header->usStructureSize != size) { 646 dev_err(smu->adev->dev, "pp table size not matched !\n"); 647 return -EIO; 648 } 649 650 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 651 kfree(smu_table->hardcode_pptable); 652 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 653 if (!smu_table->hardcode_pptable) 654 return -ENOMEM; 655 } 656 657 memcpy(smu_table->hardcode_pptable, buf, size); 658 smu_table->power_play_table = smu_table->hardcode_pptable; 659 smu_table->power_play_table_size = size; 660 661 /* 662 * Special hw_fini action(for Navi1x, the DPMs disablement will be 663 * skipped) may be needed for custom pptable uploading. 664 */ 665 smu->uploading_custom_pp_table = true; 666 667 ret = smu_reset(smu); 668 if (ret) 669 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 670 671 smu->uploading_custom_pp_table = false; 672 673 return ret; 674 } 675 676 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 677 { 678 struct smu_feature *feature = &smu->smu_feature; 679 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 680 int ret = 0; 681 682 /* 683 * With SCPM enabled, the allowed featuremasks setting(via 684 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 685 * That means there is no way to let PMFW knows the settings below. 686 * Thus, we just assume all the features are allowed under 687 * such scenario. 688 */ 689 if (smu->adev->scpm_enabled) { 690 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 691 return 0; 692 } 693 694 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 695 696 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 697 SMU_FEATURE_MAX/32); 698 if (ret) 699 return ret; 700 701 bitmap_or(feature->allowed, feature->allowed, 702 (unsigned long *)allowed_feature_mask, 703 feature->feature_num); 704 705 return ret; 706 } 707 708 static int smu_set_funcs(struct amdgpu_device *adev) 709 { 710 struct smu_context *smu = adev->powerplay.pp_handle; 711 712 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 713 smu->od_enabled = true; 714 715 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 716 case IP_VERSION(11, 0, 0): 717 case IP_VERSION(11, 0, 5): 718 case IP_VERSION(11, 0, 9): 719 navi10_set_ppt_funcs(smu); 720 break; 721 case IP_VERSION(11, 0, 7): 722 case IP_VERSION(11, 0, 11): 723 case IP_VERSION(11, 0, 12): 724 case IP_VERSION(11, 0, 13): 725 sienna_cichlid_set_ppt_funcs(smu); 726 break; 727 case IP_VERSION(12, 0, 0): 728 case IP_VERSION(12, 0, 1): 729 renoir_set_ppt_funcs(smu); 730 break; 731 case IP_VERSION(11, 5, 0): 732 case IP_VERSION(11, 5, 2): 733 vangogh_set_ppt_funcs(smu); 734 break; 735 case IP_VERSION(13, 0, 1): 736 case IP_VERSION(13, 0, 3): 737 case IP_VERSION(13, 0, 8): 738 yellow_carp_set_ppt_funcs(smu); 739 break; 740 case IP_VERSION(13, 0, 4): 741 case IP_VERSION(13, 0, 11): 742 smu_v13_0_4_set_ppt_funcs(smu); 743 break; 744 case IP_VERSION(13, 0, 5): 745 smu_v13_0_5_set_ppt_funcs(smu); 746 break; 747 case IP_VERSION(11, 0, 8): 748 cyan_skillfish_set_ppt_funcs(smu); 749 break; 750 case IP_VERSION(11, 0, 2): 751 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 752 arcturus_set_ppt_funcs(smu); 753 /* OD is not supported on Arcturus */ 754 smu->od_enabled = false; 755 break; 756 case IP_VERSION(13, 0, 2): 757 aldebaran_set_ppt_funcs(smu); 758 /* Enable pp_od_clk_voltage node */ 759 smu->od_enabled = true; 760 break; 761 case IP_VERSION(13, 0, 0): 762 case IP_VERSION(13, 0, 10): 763 smu_v13_0_0_set_ppt_funcs(smu); 764 break; 765 case IP_VERSION(13, 0, 6): 766 case IP_VERSION(13, 0, 14): 767 case IP_VERSION(13, 0, 12): 768 smu_v13_0_6_set_ppt_funcs(smu); 769 smu_v13_0_6_set_temp_funcs(smu); 770 /* Enable pp_od_clk_voltage node */ 771 smu->od_enabled = true; 772 break; 773 case IP_VERSION(13, 0, 7): 774 smu_v13_0_7_set_ppt_funcs(smu); 775 break; 776 case IP_VERSION(14, 0, 0): 777 case IP_VERSION(14, 0, 1): 778 case IP_VERSION(14, 0, 4): 779 case IP_VERSION(14, 0, 5): 780 smu_v14_0_0_set_ppt_funcs(smu); 781 break; 782 case IP_VERSION(14, 0, 2): 783 case IP_VERSION(14, 0, 3): 784 smu_v14_0_2_set_ppt_funcs(smu); 785 break; 786 default: 787 return -EINVAL; 788 } 789 790 return 0; 791 } 792 793 static int smu_early_init(struct amdgpu_ip_block *ip_block) 794 { 795 struct amdgpu_device *adev = ip_block->adev; 796 struct smu_context *smu; 797 int r; 798 799 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 800 if (!smu) 801 return -ENOMEM; 802 803 smu->adev = adev; 804 smu->pm_enabled = !!amdgpu_dpm; 805 smu->is_apu = false; 806 smu->smu_baco.state = SMU_BACO_STATE_NONE; 807 smu->smu_baco.platform_support = false; 808 smu->smu_baco.maco_support = false; 809 smu->user_dpm_profile.fan_mode = -1; 810 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 811 812 mutex_init(&smu->message_lock); 813 814 adev->powerplay.pp_handle = smu; 815 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 816 817 r = smu_set_funcs(adev); 818 if (r) 819 return r; 820 return smu_init_microcode(smu); 821 } 822 823 static int smu_set_default_dpm_table(struct smu_context *smu) 824 { 825 struct amdgpu_device *adev = smu->adev; 826 struct smu_power_context *smu_power = &smu->smu_power; 827 struct smu_power_gate *power_gate = &smu_power->power_gate; 828 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 829 int ret = 0; 830 831 if (!smu->ppt_funcs->set_default_dpm_table) 832 return 0; 833 834 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 835 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 836 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 837 } 838 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 839 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 840 841 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 842 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 843 ret = smu_dpm_set_vcn_enable(smu, true, i); 844 if (ret) 845 return ret; 846 } 847 } 848 849 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 850 ret = smu_dpm_set_jpeg_enable(smu, true); 851 if (ret) 852 goto err_out; 853 } 854 855 ret = smu->ppt_funcs->set_default_dpm_table(smu); 856 if (ret) 857 dev_err(smu->adev->dev, 858 "Failed to setup default dpm clock tables!\n"); 859 860 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 861 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 862 err_out: 863 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 864 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 865 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 866 } 867 868 return ret; 869 } 870 871 static int smu_apply_default_config_table_settings(struct smu_context *smu) 872 { 873 struct amdgpu_device *adev = smu->adev; 874 int ret = 0; 875 876 ret = smu_get_default_config_table_settings(smu, 877 &adev->pm.config_table); 878 if (ret) 879 return ret; 880 881 return smu_set_config_table(smu, &adev->pm.config_table); 882 } 883 884 static int smu_late_init(struct amdgpu_ip_block *ip_block) 885 { 886 struct amdgpu_device *adev = ip_block->adev; 887 struct smu_context *smu = adev->powerplay.pp_handle; 888 int ret = 0; 889 890 smu_set_fine_grain_gfx_freq_parameters(smu); 891 892 if (!smu->pm_enabled) 893 return 0; 894 895 ret = smu_post_init(smu); 896 if (ret) { 897 dev_err(adev->dev, "Failed to post smu init!\n"); 898 return ret; 899 } 900 901 /* 902 * Explicitly notify PMFW the power mode the system in. Since 903 * the PMFW may boot the ASIC with a different mode. 904 * For those supporting ACDC switch via gpio, PMFW will 905 * handle the switch automatically. Driver involvement 906 * is unnecessary. 907 */ 908 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 909 smu_set_ac_dc(smu); 910 911 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 912 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 913 return 0; 914 915 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 916 ret = smu_set_default_od_settings(smu); 917 if (ret) { 918 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 919 return ret; 920 } 921 } 922 923 ret = smu_populate_umd_state_clk(smu); 924 if (ret) { 925 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 926 return ret; 927 } 928 929 ret = smu_get_asic_power_limits(smu, 930 &smu->current_power_limit, 931 &smu->default_power_limit, 932 &smu->max_power_limit, 933 &smu->min_power_limit); 934 if (ret) { 935 dev_err(adev->dev, "Failed to get asic power limits!\n"); 936 return ret; 937 } 938 939 if (!amdgpu_sriov_vf(adev)) 940 smu_get_unique_id(smu); 941 942 smu_get_fan_parameters(smu); 943 944 smu_handle_task(smu, 945 smu->smu_dpm.dpm_level, 946 AMD_PP_TASK_COMPLETE_INIT); 947 948 ret = smu_apply_default_config_table_settings(smu); 949 if (ret && (ret != -EOPNOTSUPP)) { 950 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 951 return ret; 952 } 953 954 smu_restore_dpm_user_profile(smu); 955 956 return 0; 957 } 958 959 static int smu_init_fb_allocations(struct smu_context *smu) 960 { 961 struct amdgpu_device *adev = smu->adev; 962 struct smu_table_context *smu_table = &smu->smu_table; 963 struct smu_table *tables = smu_table->tables; 964 struct smu_table *driver_table = &(smu_table->driver_table); 965 uint32_t max_table_size = 0; 966 int ret, i; 967 968 /* VRAM allocation for tool table */ 969 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 970 ret = amdgpu_bo_create_kernel(adev, 971 tables[SMU_TABLE_PMSTATUSLOG].size, 972 tables[SMU_TABLE_PMSTATUSLOG].align, 973 tables[SMU_TABLE_PMSTATUSLOG].domain, 974 &tables[SMU_TABLE_PMSTATUSLOG].bo, 975 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 976 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 977 if (ret) { 978 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 979 return ret; 980 } 981 } 982 983 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 984 /* VRAM allocation for driver table */ 985 for (i = 0; i < SMU_TABLE_COUNT; i++) { 986 if (tables[i].size == 0) 987 continue; 988 989 /* If one of the tables has VRAM domain restriction, keep it in 990 * VRAM 991 */ 992 if ((tables[i].domain & 993 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 994 AMDGPU_GEM_DOMAIN_VRAM) 995 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 996 997 if (i == SMU_TABLE_PMSTATUSLOG) 998 continue; 999 1000 if (max_table_size < tables[i].size) 1001 max_table_size = tables[i].size; 1002 } 1003 1004 driver_table->size = max_table_size; 1005 driver_table->align = PAGE_SIZE; 1006 1007 ret = amdgpu_bo_create_kernel(adev, 1008 driver_table->size, 1009 driver_table->align, 1010 driver_table->domain, 1011 &driver_table->bo, 1012 &driver_table->mc_address, 1013 &driver_table->cpu_addr); 1014 if (ret) { 1015 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 1016 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1017 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1018 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1019 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1020 } 1021 1022 return ret; 1023 } 1024 1025 static int smu_fini_fb_allocations(struct smu_context *smu) 1026 { 1027 struct smu_table_context *smu_table = &smu->smu_table; 1028 struct smu_table *tables = smu_table->tables; 1029 struct smu_table *driver_table = &(smu_table->driver_table); 1030 1031 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1032 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1033 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1034 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1035 1036 amdgpu_bo_free_kernel(&driver_table->bo, 1037 &driver_table->mc_address, 1038 &driver_table->cpu_addr); 1039 1040 return 0; 1041 } 1042 1043 static void smu_update_gpu_addresses(struct smu_context *smu) 1044 { 1045 struct smu_table_context *smu_table = &smu->smu_table; 1046 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1047 struct smu_table *driver_table = &(smu_table->driver_table); 1048 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1049 1050 if (pm_status_table->bo) 1051 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1052 if (driver_table->bo) 1053 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1054 if (dummy_read_1_table->bo) 1055 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1056 } 1057 1058 /** 1059 * smu_alloc_memory_pool - allocate memory pool in the system memory 1060 * 1061 * @smu: amdgpu_device pointer 1062 * 1063 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1064 * and DramLogSetDramAddr can notify it changed. 1065 * 1066 * Returns 0 on success, error on failure. 1067 */ 1068 static int smu_alloc_memory_pool(struct smu_context *smu) 1069 { 1070 struct amdgpu_device *adev = smu->adev; 1071 struct smu_table_context *smu_table = &smu->smu_table; 1072 struct smu_table *memory_pool = &smu_table->memory_pool; 1073 uint64_t pool_size = smu->pool_size; 1074 int ret = 0; 1075 1076 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1077 return ret; 1078 1079 memory_pool->size = pool_size; 1080 memory_pool->align = PAGE_SIZE; 1081 memory_pool->domain = 1082 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1083 AMDGPU_GEM_DOMAIN_VRAM : 1084 AMDGPU_GEM_DOMAIN_GTT; 1085 1086 switch (pool_size) { 1087 case SMU_MEMORY_POOL_SIZE_256_MB: 1088 case SMU_MEMORY_POOL_SIZE_512_MB: 1089 case SMU_MEMORY_POOL_SIZE_1_GB: 1090 case SMU_MEMORY_POOL_SIZE_2_GB: 1091 ret = amdgpu_bo_create_kernel(adev, 1092 memory_pool->size, 1093 memory_pool->align, 1094 memory_pool->domain, 1095 &memory_pool->bo, 1096 &memory_pool->mc_address, 1097 &memory_pool->cpu_addr); 1098 if (ret) 1099 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1100 break; 1101 default: 1102 break; 1103 } 1104 1105 return ret; 1106 } 1107 1108 static int smu_free_memory_pool(struct smu_context *smu) 1109 { 1110 struct smu_table_context *smu_table = &smu->smu_table; 1111 struct smu_table *memory_pool = &smu_table->memory_pool; 1112 1113 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1114 return 0; 1115 1116 amdgpu_bo_free_kernel(&memory_pool->bo, 1117 &memory_pool->mc_address, 1118 &memory_pool->cpu_addr); 1119 1120 memset(memory_pool, 0, sizeof(struct smu_table)); 1121 1122 return 0; 1123 } 1124 1125 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1126 { 1127 struct smu_table_context *smu_table = &smu->smu_table; 1128 struct smu_table *dummy_read_1_table = 1129 &smu_table->dummy_read_1_table; 1130 struct amdgpu_device *adev = smu->adev; 1131 int ret = 0; 1132 1133 if (!dummy_read_1_table->size) 1134 return 0; 1135 1136 ret = amdgpu_bo_create_kernel(adev, 1137 dummy_read_1_table->size, 1138 dummy_read_1_table->align, 1139 dummy_read_1_table->domain, 1140 &dummy_read_1_table->bo, 1141 &dummy_read_1_table->mc_address, 1142 &dummy_read_1_table->cpu_addr); 1143 if (ret) 1144 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1145 1146 return ret; 1147 } 1148 1149 static void smu_free_dummy_read_table(struct smu_context *smu) 1150 { 1151 struct smu_table_context *smu_table = &smu->smu_table; 1152 struct smu_table *dummy_read_1_table = 1153 &smu_table->dummy_read_1_table; 1154 1155 1156 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1157 &dummy_read_1_table->mc_address, 1158 &dummy_read_1_table->cpu_addr); 1159 1160 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1161 } 1162 1163 static int smu_smc_table_sw_init(struct smu_context *smu) 1164 { 1165 int ret; 1166 1167 /** 1168 * Create smu_table structure, and init smc tables such as 1169 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1170 */ 1171 ret = smu_init_smc_tables(smu); 1172 if (ret) { 1173 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1174 return ret; 1175 } 1176 1177 /** 1178 * Create smu_power_context structure, and allocate smu_dpm_context and 1179 * context size to fill the smu_power_context data. 1180 */ 1181 ret = smu_init_power(smu); 1182 if (ret) { 1183 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1184 return ret; 1185 } 1186 1187 /* 1188 * allocate vram bos to store smc table contents. 1189 */ 1190 ret = smu_init_fb_allocations(smu); 1191 if (ret) 1192 return ret; 1193 1194 ret = smu_alloc_memory_pool(smu); 1195 if (ret) 1196 return ret; 1197 1198 ret = smu_alloc_dummy_read_table(smu); 1199 if (ret) 1200 return ret; 1201 1202 ret = smu_i2c_init(smu); 1203 if (ret) 1204 return ret; 1205 1206 return 0; 1207 } 1208 1209 static int smu_smc_table_sw_fini(struct smu_context *smu) 1210 { 1211 int ret; 1212 1213 smu_i2c_fini(smu); 1214 1215 smu_free_dummy_read_table(smu); 1216 1217 ret = smu_free_memory_pool(smu); 1218 if (ret) 1219 return ret; 1220 1221 ret = smu_fini_fb_allocations(smu); 1222 if (ret) 1223 return ret; 1224 1225 ret = smu_fini_power(smu); 1226 if (ret) { 1227 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1228 return ret; 1229 } 1230 1231 ret = smu_fini_smc_tables(smu); 1232 if (ret) { 1233 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1234 return ret; 1235 } 1236 1237 return 0; 1238 } 1239 1240 static void smu_throttling_logging_work_fn(struct work_struct *work) 1241 { 1242 struct smu_context *smu = container_of(work, struct smu_context, 1243 throttling_logging_work); 1244 1245 smu_log_thermal_throttling(smu); 1246 } 1247 1248 static void smu_interrupt_work_fn(struct work_struct *work) 1249 { 1250 struct smu_context *smu = container_of(work, struct smu_context, 1251 interrupt_work); 1252 1253 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1254 smu->ppt_funcs->interrupt_work(smu); 1255 } 1256 1257 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1258 { 1259 struct smu_context *smu = 1260 container_of(work, struct smu_context, swctf_delayed_work.work); 1261 struct smu_temperature_range *range = 1262 &smu->thermal_range; 1263 struct amdgpu_device *adev = smu->adev; 1264 uint32_t hotspot_tmp, size; 1265 1266 /* 1267 * If the hotspot temperature is confirmed as below SW CTF setting point 1268 * after the delay enforced, nothing will be done. 1269 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1270 */ 1271 if (range->software_shutdown_temp && 1272 smu->ppt_funcs->read_sensor && 1273 !smu->ppt_funcs->read_sensor(smu, 1274 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1275 &hotspot_tmp, 1276 &size) && 1277 hotspot_tmp / 1000 < range->software_shutdown_temp) 1278 return; 1279 1280 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1281 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1282 orderly_poweroff(true); 1283 } 1284 1285 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1286 { 1287 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1288 struct smu_dpm_policy_ctxt *policy_ctxt; 1289 struct smu_dpm_policy *policy; 1290 1291 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1292 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1293 if (policy) 1294 policy->current_level = XGMI_PLPD_DEFAULT; 1295 return; 1296 } 1297 1298 /* PMFW put PLPD into default policy after enabling the feature */ 1299 if (smu_feature_is_enabled(smu, 1300 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1301 if (policy) 1302 policy->current_level = XGMI_PLPD_DEFAULT; 1303 } else { 1304 policy_ctxt = dpm_ctxt->dpm_policies; 1305 if (policy_ctxt) 1306 policy_ctxt->policy_mask &= 1307 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1308 } 1309 } 1310 1311 static void smu_init_power_profile(struct smu_context *smu) 1312 { 1313 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1314 smu->power_profile_mode = 1315 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1316 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1317 } 1318 1319 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1320 { 1321 struct amdgpu_device *adev = ip_block->adev; 1322 struct smu_context *smu = adev->powerplay.pp_handle; 1323 int i, ret; 1324 1325 smu->pool_size = adev->pm.smu_prv_buffer_size; 1326 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1327 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1328 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1329 1330 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1331 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1332 atomic64_set(&smu->throttle_int_counter, 0); 1333 smu->watermarks_bitmap = 0; 1334 1335 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1336 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1337 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1338 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1339 atomic_set(&smu->smu_power.power_gate.isp_gated, 1); 1340 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1341 1342 smu_init_power_profile(smu); 1343 smu->display_config = &adev->pm.pm_display_cfg; 1344 1345 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1346 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1347 1348 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1349 smu_swctf_delayed_work_handler); 1350 1351 ret = smu_smc_table_sw_init(smu); 1352 if (ret) { 1353 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1354 return ret; 1355 } 1356 1357 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1358 ret = smu_get_vbios_bootup_values(smu); 1359 if (ret) { 1360 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1361 return ret; 1362 } 1363 1364 ret = smu_init_pptable_microcode(smu); 1365 if (ret) { 1366 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1367 return ret; 1368 } 1369 1370 ret = smu_register_irq_handler(smu); 1371 if (ret) { 1372 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1373 return ret; 1374 } 1375 1376 /* If there is no way to query fan control mode, fan control is not supported */ 1377 if (!smu->ppt_funcs->get_fan_control_mode) 1378 smu->adev->pm.no_fan = true; 1379 1380 return 0; 1381 } 1382 1383 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1384 { 1385 struct amdgpu_device *adev = ip_block->adev; 1386 struct smu_context *smu = adev->powerplay.pp_handle; 1387 int ret; 1388 1389 ret = smu_smc_table_sw_fini(smu); 1390 if (ret) { 1391 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1392 return ret; 1393 } 1394 1395 if (smu->custom_profile_params) { 1396 kfree(smu->custom_profile_params); 1397 smu->custom_profile_params = NULL; 1398 } 1399 1400 smu_fini_microcode(smu); 1401 1402 return 0; 1403 } 1404 1405 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1406 { 1407 struct amdgpu_device *adev = smu->adev; 1408 struct smu_temperature_range *range = 1409 &smu->thermal_range; 1410 int ret = 0; 1411 1412 if (!smu->ppt_funcs->get_thermal_temperature_range) 1413 return 0; 1414 1415 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1416 if (ret) 1417 return ret; 1418 1419 adev->pm.dpm.thermal.min_temp = range->min; 1420 adev->pm.dpm.thermal.max_temp = range->max; 1421 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1422 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1423 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1424 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1425 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1426 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1427 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1428 1429 return ret; 1430 } 1431 1432 /** 1433 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1434 * 1435 * @smu: smu_context pointer 1436 * 1437 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1438 * Returns 0 on success, error on failure. 1439 */ 1440 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1441 { 1442 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1443 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1444 struct amdgpu_device *adev = smu->adev; 1445 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1446 uint64_t start, end; 1447 int ret, i, j; 1448 1449 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1450 if (ret) { 1451 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1452 return ret; 1453 } 1454 1455 /* 1456 * The exclusion ranges array we got might be filled with holes and duplicate 1457 * entries. For example: 1458 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1459 * We need to do some sortups to eliminate those holes and duplicate entries. 1460 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1461 */ 1462 for (i = 0; i < num_of_wbrf_ranges; i++) { 1463 start = wifi_bands[i].start; 1464 end = wifi_bands[i].end; 1465 1466 /* get the last valid entry to fill the intermediate hole */ 1467 if (!start && !end) { 1468 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1469 if (wifi_bands[j].start && wifi_bands[j].end) 1470 break; 1471 1472 /* no valid entry left */ 1473 if (j <= i) 1474 break; 1475 1476 start = wifi_bands[i].start = wifi_bands[j].start; 1477 end = wifi_bands[i].end = wifi_bands[j].end; 1478 wifi_bands[j].start = 0; 1479 wifi_bands[j].end = 0; 1480 num_of_wbrf_ranges = j; 1481 } 1482 1483 /* eliminate duplicate entries */ 1484 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1485 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1486 wifi_bands[j].start = 0; 1487 wifi_bands[j].end = 0; 1488 } 1489 } 1490 } 1491 1492 /* Send the sorted wifi_bands to PMFW */ 1493 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1494 /* Try to set the wifi_bands again */ 1495 if (unlikely(ret == -EBUSY)) { 1496 mdelay(5); 1497 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1498 } 1499 1500 return ret; 1501 } 1502 1503 /** 1504 * smu_wbrf_event_handler - handle notify events 1505 * 1506 * @nb: notifier block 1507 * @action: event type 1508 * @_arg: event data 1509 * 1510 * Calls relevant amdgpu function in response to wbrf event 1511 * notification from kernel. 1512 */ 1513 static int smu_wbrf_event_handler(struct notifier_block *nb, 1514 unsigned long action, void *_arg) 1515 { 1516 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1517 1518 switch (action) { 1519 case WBRF_CHANGED: 1520 schedule_delayed_work(&smu->wbrf_delayed_work, 1521 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1522 break; 1523 default: 1524 return NOTIFY_DONE; 1525 } 1526 1527 return NOTIFY_OK; 1528 } 1529 1530 /** 1531 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1532 * 1533 * @work: struct work_struct pointer 1534 * 1535 * Flood is over and driver will consume the latest exclusion ranges. 1536 */ 1537 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1538 { 1539 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1540 1541 smu_wbrf_handle_exclusion_ranges(smu); 1542 } 1543 1544 /** 1545 * smu_wbrf_support_check - check wbrf support 1546 * 1547 * @smu: smu_context pointer 1548 * 1549 * Verifies the ACPI interface whether wbrf is supported. 1550 */ 1551 static void smu_wbrf_support_check(struct smu_context *smu) 1552 { 1553 struct amdgpu_device *adev = smu->adev; 1554 1555 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1556 acpi_amd_wbrf_supported_consumer(adev->dev); 1557 1558 if (smu->wbrf_supported) 1559 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1560 } 1561 1562 /** 1563 * smu_wbrf_init - init driver wbrf support 1564 * 1565 * @smu: smu_context pointer 1566 * 1567 * Verifies the AMD ACPI interfaces and registers with the wbrf 1568 * notifier chain if wbrf feature is supported. 1569 * Returns 0 on success, error on failure. 1570 */ 1571 static int smu_wbrf_init(struct smu_context *smu) 1572 { 1573 int ret; 1574 1575 if (!smu->wbrf_supported) 1576 return 0; 1577 1578 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1579 1580 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1581 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1582 if (ret) 1583 return ret; 1584 1585 /* 1586 * Some wifiband exclusion ranges may be already there 1587 * before our driver loaded. To make sure our driver 1588 * is awared of those exclusion ranges. 1589 */ 1590 schedule_delayed_work(&smu->wbrf_delayed_work, 1591 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1592 1593 return 0; 1594 } 1595 1596 /** 1597 * smu_wbrf_fini - tear down driver wbrf support 1598 * 1599 * @smu: smu_context pointer 1600 * 1601 * Unregisters with the wbrf notifier chain. 1602 */ 1603 static void smu_wbrf_fini(struct smu_context *smu) 1604 { 1605 if (!smu->wbrf_supported) 1606 return; 1607 1608 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1609 1610 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1611 } 1612 1613 static int smu_smc_hw_setup(struct smu_context *smu) 1614 { 1615 struct smu_feature *feature = &smu->smu_feature; 1616 struct amdgpu_device *adev = smu->adev; 1617 uint8_t pcie_gen = 0, pcie_width = 0; 1618 uint64_t features_supported; 1619 int ret = 0; 1620 1621 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1622 case IP_VERSION(11, 0, 7): 1623 case IP_VERSION(11, 0, 11): 1624 case IP_VERSION(11, 5, 0): 1625 case IP_VERSION(11, 5, 2): 1626 case IP_VERSION(11, 0, 12): 1627 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1628 dev_info(adev->dev, "dpm has been enabled\n"); 1629 ret = smu_system_features_control(smu, true); 1630 if (ret) 1631 dev_err(adev->dev, "Failed system features control!\n"); 1632 return ret; 1633 } 1634 break; 1635 default: 1636 break; 1637 } 1638 1639 ret = smu_init_display_count(smu, 0); 1640 if (ret) { 1641 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1642 return ret; 1643 } 1644 1645 ret = smu_set_driver_table_location(smu); 1646 if (ret) { 1647 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1648 return ret; 1649 } 1650 1651 /* 1652 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1653 */ 1654 ret = smu_set_tool_table_location(smu); 1655 if (ret) { 1656 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1657 return ret; 1658 } 1659 1660 /* 1661 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1662 * pool location. 1663 */ 1664 ret = smu_notify_memory_pool_location(smu); 1665 if (ret) { 1666 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1667 return ret; 1668 } 1669 1670 /* 1671 * It is assumed the pptable used before runpm is same as 1672 * the one used afterwards. Thus, we can reuse the stored 1673 * copy and do not need to resetup the pptable again. 1674 */ 1675 if (!adev->in_runpm) { 1676 ret = smu_setup_pptable(smu); 1677 if (ret) { 1678 dev_err(adev->dev, "Failed to setup pptable!\n"); 1679 return ret; 1680 } 1681 } 1682 1683 /* smu_dump_pptable(smu); */ 1684 1685 /* 1686 * With SCPM enabled, PSP is responsible for the PPTable transferring 1687 * (to SMU). Driver involvement is not needed and permitted. 1688 */ 1689 if (!adev->scpm_enabled) { 1690 /* 1691 * Copy pptable bo in the vram to smc with SMU MSGs such as 1692 * SetDriverDramAddr and TransferTableDram2Smu. 1693 */ 1694 ret = smu_write_pptable(smu); 1695 if (ret) { 1696 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1697 return ret; 1698 } 1699 } 1700 1701 /* issue Run*Btc msg */ 1702 ret = smu_run_btc(smu); 1703 if (ret) 1704 return ret; 1705 1706 /* Enable UclkShadow on wbrf supported */ 1707 if (smu->wbrf_supported) { 1708 ret = smu_enable_uclk_shadow(smu, true); 1709 if (ret) { 1710 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1711 return ret; 1712 } 1713 } 1714 1715 /* 1716 * With SCPM enabled, these actions(and relevant messages) are 1717 * not needed and permitted. 1718 */ 1719 if (!adev->scpm_enabled) { 1720 ret = smu_feature_set_allowed_mask(smu); 1721 if (ret) { 1722 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1723 return ret; 1724 } 1725 } 1726 1727 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1728 pcie_gen = 4; 1729 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1730 pcie_gen = 3; 1731 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1732 pcie_gen = 2; 1733 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1734 pcie_gen = 1; 1735 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1736 pcie_gen = 0; 1737 1738 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1739 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1740 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1741 */ 1742 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1743 pcie_width = 7; 1744 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1745 pcie_width = 6; 1746 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1747 pcie_width = 5; 1748 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1749 pcie_width = 4; 1750 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1751 pcie_width = 3; 1752 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1753 pcie_width = 2; 1754 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1755 pcie_width = 1; 1756 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1757 if (ret) { 1758 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1759 return ret; 1760 } 1761 1762 ret = smu_system_features_control(smu, true); 1763 if (ret) { 1764 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1765 return ret; 1766 } 1767 1768 smu_init_xgmi_plpd_mode(smu); 1769 1770 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1771 if (ret) { 1772 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1773 return ret; 1774 } 1775 bitmap_copy(feature->supported, 1776 (unsigned long *)&features_supported, 1777 feature->feature_num); 1778 1779 if (!smu_is_dpm_running(smu)) 1780 dev_info(adev->dev, "dpm has been disabled\n"); 1781 1782 /* 1783 * Set initialized values (get from vbios) to dpm tables context such as 1784 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1785 * type of clks. 1786 */ 1787 ret = smu_set_default_dpm_table(smu); 1788 if (ret) { 1789 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1790 return ret; 1791 } 1792 1793 ret = smu_get_thermal_temperature_range(smu); 1794 if (ret) { 1795 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1796 return ret; 1797 } 1798 1799 ret = smu_enable_thermal_alert(smu); 1800 if (ret) { 1801 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1802 return ret; 1803 } 1804 1805 ret = smu_notify_display_change(smu); 1806 if (ret) { 1807 dev_err(adev->dev, "Failed to notify display change!\n"); 1808 return ret; 1809 } 1810 1811 /* 1812 * Set min deep sleep dce fclk with bootup value from vbios via 1813 * SetMinDeepSleepDcefclk MSG. 1814 */ 1815 ret = smu_set_min_dcef_deep_sleep(smu, 1816 smu->smu_table.boot_values.dcefclk / 100); 1817 if (ret) { 1818 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1819 return ret; 1820 } 1821 1822 /* Init wbrf support. Properly setup the notifier */ 1823 ret = smu_wbrf_init(smu); 1824 if (ret) 1825 dev_err(adev->dev, "Error during wbrf init call\n"); 1826 1827 return ret; 1828 } 1829 1830 static int smu_start_smc_engine(struct smu_context *smu) 1831 { 1832 struct amdgpu_device *adev = smu->adev; 1833 int ret = 0; 1834 1835 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1836 smu_update_gpu_addresses(smu); 1837 1838 smu->smc_fw_state = SMU_FW_INIT; 1839 1840 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1841 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1842 if (smu->ppt_funcs->load_microcode) { 1843 ret = smu->ppt_funcs->load_microcode(smu); 1844 if (ret) 1845 return ret; 1846 } 1847 } 1848 } 1849 1850 if (smu->ppt_funcs->check_fw_status) { 1851 ret = smu->ppt_funcs->check_fw_status(smu); 1852 if (ret) { 1853 dev_err(adev->dev, "SMC is not ready\n"); 1854 return ret; 1855 } 1856 } 1857 1858 /* 1859 * Send msg GetDriverIfVersion to check if the return value is equal 1860 * with DRIVER_IF_VERSION of smc header. 1861 */ 1862 ret = smu_check_fw_version(smu); 1863 if (ret) 1864 return ret; 1865 1866 return ret; 1867 } 1868 1869 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1870 { 1871 int i, ret; 1872 struct amdgpu_device *adev = ip_block->adev; 1873 struct smu_context *smu = adev->powerplay.pp_handle; 1874 1875 if (amdgpu_sriov_multi_vf_mode(adev)) { 1876 smu->pm_enabled = false; 1877 return 0; 1878 } 1879 1880 ret = smu_start_smc_engine(smu); 1881 if (ret) { 1882 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1883 return ret; 1884 } 1885 1886 /* 1887 * Check whether wbrf is supported. This needs to be done 1888 * before SMU setup starts since part of SMU configuration 1889 * relies on this. 1890 */ 1891 smu_wbrf_support_check(smu); 1892 1893 if (smu->is_apu) { 1894 ret = smu_set_gfx_imu_enable(smu); 1895 if (ret) 1896 return ret; 1897 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1898 smu_dpm_set_vcn_enable(smu, true, i); 1899 smu_dpm_set_jpeg_enable(smu, true); 1900 smu_dpm_set_vpe_enable(smu, true); 1901 smu_dpm_set_umsch_mm_enable(smu, true); 1902 smu_set_mall_enable(smu); 1903 smu_set_gfx_cgpg(smu, true); 1904 } 1905 1906 if (!smu->pm_enabled) 1907 return 0; 1908 1909 ret = smu_get_driver_allowed_feature_mask(smu); 1910 if (ret) 1911 return ret; 1912 1913 ret = smu_smc_hw_setup(smu); 1914 if (ret) { 1915 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1916 return ret; 1917 } 1918 1919 /* 1920 * Move maximum sustainable clock retrieving here considering 1921 * 1. It is not needed on resume(from S3). 1922 * 2. DAL settings come between .hw_init and .late_init of SMU. 1923 * And DAL needs to know the maximum sustainable clocks. Thus 1924 * it cannot be put in .late_init(). 1925 */ 1926 ret = smu_init_max_sustainable_clocks(smu); 1927 if (ret) { 1928 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1929 return ret; 1930 } 1931 1932 adev->pm.dpm_enabled = true; 1933 1934 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1935 1936 return 0; 1937 } 1938 1939 static int smu_disable_dpms(struct smu_context *smu) 1940 { 1941 struct amdgpu_device *adev = smu->adev; 1942 int ret = 0; 1943 bool use_baco = !smu->is_apu && 1944 ((amdgpu_in_reset(adev) && 1945 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1946 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1947 1948 /* 1949 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1950 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1951 */ 1952 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1953 case IP_VERSION(13, 0, 0): 1954 case IP_VERSION(13, 0, 7): 1955 case IP_VERSION(13, 0, 10): 1956 case IP_VERSION(14, 0, 2): 1957 case IP_VERSION(14, 0, 3): 1958 return 0; 1959 default: 1960 break; 1961 } 1962 1963 /* 1964 * For custom pptable uploading, skip the DPM features 1965 * disable process on Navi1x ASICs. 1966 * - As the gfx related features are under control of 1967 * RLC on those ASICs. RLC reinitialization will be 1968 * needed to reenable them. That will cost much more 1969 * efforts. 1970 * 1971 * - SMU firmware can handle the DPM reenablement 1972 * properly. 1973 */ 1974 if (smu->uploading_custom_pp_table) { 1975 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1976 case IP_VERSION(11, 0, 0): 1977 case IP_VERSION(11, 0, 5): 1978 case IP_VERSION(11, 0, 9): 1979 case IP_VERSION(11, 0, 7): 1980 case IP_VERSION(11, 0, 11): 1981 case IP_VERSION(11, 5, 0): 1982 case IP_VERSION(11, 5, 2): 1983 case IP_VERSION(11, 0, 12): 1984 case IP_VERSION(11, 0, 13): 1985 return 0; 1986 default: 1987 break; 1988 } 1989 } 1990 1991 /* 1992 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1993 * on BACO in. Driver involvement is unnecessary. 1994 */ 1995 if (use_baco) { 1996 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1997 case IP_VERSION(11, 0, 7): 1998 case IP_VERSION(11, 0, 0): 1999 case IP_VERSION(11, 0, 5): 2000 case IP_VERSION(11, 0, 9): 2001 case IP_VERSION(13, 0, 7): 2002 return 0; 2003 default: 2004 break; 2005 } 2006 } 2007 2008 /* 2009 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 2010 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 2011 */ 2012 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 2013 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2014 return 0; 2015 2016 /* 2017 * For gpu reset, runpm and hibernation through BACO, 2018 * BACO feature has to be kept enabled. 2019 */ 2020 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 2021 ret = smu_disable_all_features_with_exception(smu, 2022 SMU_FEATURE_BACO_BIT); 2023 if (ret) 2024 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 2025 } else { 2026 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 2027 if (!adev->scpm_enabled) { 2028 ret = smu_system_features_control(smu, false); 2029 if (ret) 2030 dev_err(adev->dev, "Failed to disable smu features.\n"); 2031 } 2032 } 2033 2034 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 2035 * otherwise SMU will hang while interacting with RLC if RLC is halted 2036 * this is a WA for Vangogh asic which fix the SMU hang issue. 2037 */ 2038 ret = smu_notify_rlc_state(smu, false); 2039 if (ret) { 2040 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2041 return ret; 2042 } 2043 2044 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2045 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2046 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2047 adev->gfx.rlc.funcs->stop(adev); 2048 2049 return ret; 2050 } 2051 2052 static int smu_smc_hw_cleanup(struct smu_context *smu) 2053 { 2054 struct amdgpu_device *adev = smu->adev; 2055 int ret = 0; 2056 2057 smu_wbrf_fini(smu); 2058 2059 cancel_work_sync(&smu->throttling_logging_work); 2060 cancel_work_sync(&smu->interrupt_work); 2061 2062 ret = smu_disable_thermal_alert(smu); 2063 if (ret) { 2064 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2065 return ret; 2066 } 2067 2068 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2069 2070 ret = smu_disable_dpms(smu); 2071 if (ret) { 2072 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2073 return ret; 2074 } 2075 2076 return 0; 2077 } 2078 2079 static int smu_reset_mp1_state(struct smu_context *smu) 2080 { 2081 struct amdgpu_device *adev = smu->adev; 2082 int ret = 0; 2083 2084 if ((!adev->in_runpm) && (!adev->in_suspend) && 2085 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2086 IP_VERSION(13, 0, 10) && 2087 !amdgpu_device_has_display_hardware(adev)) 2088 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2089 2090 return ret; 2091 } 2092 2093 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2094 { 2095 struct amdgpu_device *adev = ip_block->adev; 2096 struct smu_context *smu = adev->powerplay.pp_handle; 2097 int i, ret; 2098 2099 if (amdgpu_sriov_multi_vf_mode(adev)) 2100 return 0; 2101 2102 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2103 smu_dpm_set_vcn_enable(smu, false, i); 2104 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2105 } 2106 smu_dpm_set_jpeg_enable(smu, false); 2107 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2108 smu_dpm_set_vpe_enable(smu, false); 2109 smu_dpm_set_umsch_mm_enable(smu, false); 2110 2111 if (!smu->pm_enabled) 2112 return 0; 2113 2114 adev->pm.dpm_enabled = false; 2115 2116 ret = smu_smc_hw_cleanup(smu); 2117 if (ret) 2118 return ret; 2119 2120 ret = smu_reset_mp1_state(smu); 2121 if (ret) 2122 return ret; 2123 2124 return 0; 2125 } 2126 2127 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2128 { 2129 struct amdgpu_device *adev = ip_block->adev; 2130 struct smu_context *smu = adev->powerplay.pp_handle; 2131 2132 kfree(smu); 2133 } 2134 2135 static int smu_reset(struct smu_context *smu) 2136 { 2137 struct amdgpu_device *adev = smu->adev; 2138 struct amdgpu_ip_block *ip_block; 2139 int ret; 2140 2141 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2142 if (!ip_block) 2143 return -EINVAL; 2144 2145 ret = smu_hw_fini(ip_block); 2146 if (ret) 2147 return ret; 2148 2149 ret = smu_hw_init(ip_block); 2150 if (ret) 2151 return ret; 2152 2153 ret = smu_late_init(ip_block); 2154 if (ret) 2155 return ret; 2156 2157 return 0; 2158 } 2159 2160 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2161 { 2162 struct amdgpu_device *adev = ip_block->adev; 2163 struct smu_context *smu = adev->powerplay.pp_handle; 2164 int ret; 2165 uint64_t count; 2166 2167 if (amdgpu_sriov_multi_vf_mode(adev)) 2168 return 0; 2169 2170 if (!smu->pm_enabled) 2171 return 0; 2172 2173 adev->pm.dpm_enabled = false; 2174 2175 ret = smu_smc_hw_cleanup(smu); 2176 if (ret) 2177 return ret; 2178 2179 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2180 2181 smu_set_gfx_cgpg(smu, false); 2182 2183 /* 2184 * pwfw resets entrycount when device is suspended, so we save the 2185 * last value to be used when we resume to keep it consistent 2186 */ 2187 ret = smu_get_entrycount_gfxoff(smu, &count); 2188 if (!ret) 2189 adev->gfx.gfx_off_entrycount = count; 2190 2191 /* clear this on suspend so it will get reprogrammed on resume */ 2192 smu->workload_mask = 0; 2193 2194 return 0; 2195 } 2196 2197 static int smu_resume(struct amdgpu_ip_block *ip_block) 2198 { 2199 int ret; 2200 struct amdgpu_device *adev = ip_block->adev; 2201 struct smu_context *smu = adev->powerplay.pp_handle; 2202 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2203 2204 if (amdgpu_sriov_multi_vf_mode(adev)) 2205 return 0; 2206 2207 if (!smu->pm_enabled) 2208 return 0; 2209 2210 dev_info(adev->dev, "SMU is resuming...\n"); 2211 2212 ret = smu_start_smc_engine(smu); 2213 if (ret) { 2214 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2215 return ret; 2216 } 2217 2218 ret = smu_smc_hw_setup(smu); 2219 if (ret) { 2220 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2221 return ret; 2222 } 2223 2224 ret = smu_set_gfx_imu_enable(smu); 2225 if (ret) 2226 return ret; 2227 2228 smu_set_gfx_cgpg(smu, true); 2229 2230 smu->disable_uclk_switch = 0; 2231 2232 adev->pm.dpm_enabled = true; 2233 2234 if (smu->current_power_limit) { 2235 ret = smu_set_power_limit(smu, smu->current_power_limit); 2236 if (ret && ret != -EOPNOTSUPP) 2237 return ret; 2238 } 2239 2240 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 2241 ret = smu_od_edit_dpm_table(smu, PP_OD_COMMIT_DPM_TABLE, NULL, 0); 2242 if (ret) 2243 return ret; 2244 } 2245 2246 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2247 2248 return 0; 2249 } 2250 2251 static int smu_display_configuration_change(void *handle, 2252 const struct amd_pp_display_configuration *display_config) 2253 { 2254 struct smu_context *smu = handle; 2255 2256 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2257 return -EOPNOTSUPP; 2258 2259 if (!display_config) 2260 return -EINVAL; 2261 2262 smu_set_min_dcef_deep_sleep(smu, 2263 display_config->min_dcef_deep_sleep_set_clk / 100); 2264 2265 return 0; 2266 } 2267 2268 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2269 enum amd_clockgating_state state) 2270 { 2271 return 0; 2272 } 2273 2274 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2275 enum amd_powergating_state state) 2276 { 2277 return 0; 2278 } 2279 2280 static int smu_enable_umd_pstate(void *handle, 2281 enum amd_dpm_forced_level *level) 2282 { 2283 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2284 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2285 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2286 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2287 2288 struct smu_context *smu = (struct smu_context*)(handle); 2289 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2290 2291 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2292 return -EINVAL; 2293 2294 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2295 /* enter umd pstate, save current level, disable gfx cg*/ 2296 if (*level & profile_mode_mask) { 2297 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2298 smu_gpo_control(smu, false); 2299 smu_gfx_ulv_control(smu, false); 2300 smu_deep_sleep_control(smu, false); 2301 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2302 } 2303 } else { 2304 /* exit umd pstate, restore level, enable gfx cg*/ 2305 if (!(*level & profile_mode_mask)) { 2306 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2307 *level = smu_dpm_ctx->saved_dpm_level; 2308 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2309 smu_deep_sleep_control(smu, true); 2310 smu_gfx_ulv_control(smu, true); 2311 smu_gpo_control(smu, true); 2312 } 2313 } 2314 2315 return 0; 2316 } 2317 2318 static int smu_bump_power_profile_mode(struct smu_context *smu, 2319 long *custom_params, 2320 u32 custom_params_max_idx) 2321 { 2322 u32 workload_mask = 0; 2323 int i, ret = 0; 2324 2325 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2326 if (smu->workload_refcount[i]) 2327 workload_mask |= 1 << i; 2328 } 2329 2330 if (smu->workload_mask == workload_mask) 2331 return 0; 2332 2333 if (smu->ppt_funcs->set_power_profile_mode) 2334 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2335 custom_params, 2336 custom_params_max_idx); 2337 2338 if (!ret) 2339 smu->workload_mask = workload_mask; 2340 2341 return ret; 2342 } 2343 2344 static void smu_power_profile_mode_get(struct smu_context *smu, 2345 enum PP_SMC_POWER_PROFILE profile_mode) 2346 { 2347 smu->workload_refcount[profile_mode]++; 2348 } 2349 2350 static void smu_power_profile_mode_put(struct smu_context *smu, 2351 enum PP_SMC_POWER_PROFILE profile_mode) 2352 { 2353 if (smu->workload_refcount[profile_mode]) 2354 smu->workload_refcount[profile_mode]--; 2355 } 2356 2357 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2358 enum amd_dpm_forced_level level, 2359 bool skip_display_settings) 2360 { 2361 int ret = 0; 2362 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2363 2364 if (!skip_display_settings) { 2365 ret = smu_display_config_changed(smu); 2366 if (ret) { 2367 dev_err(smu->adev->dev, "Failed to change display config!"); 2368 return ret; 2369 } 2370 } 2371 2372 ret = smu_apply_clocks_adjust_rules(smu); 2373 if (ret) { 2374 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2375 return ret; 2376 } 2377 2378 if (!skip_display_settings) { 2379 ret = smu_notify_smc_display_config(smu); 2380 if (ret) { 2381 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2382 return ret; 2383 } 2384 } 2385 2386 if (smu_dpm_ctx->dpm_level != level) { 2387 ret = smu_asic_set_performance_level(smu, level); 2388 if (ret) { 2389 if (ret == -EOPNOTSUPP) 2390 dev_info(smu->adev->dev, "set performance level %d not supported", 2391 level); 2392 else 2393 dev_err(smu->adev->dev, "Failed to set performance level %d", 2394 level); 2395 return ret; 2396 } 2397 2398 /* update the saved copy */ 2399 smu_dpm_ctx->dpm_level = level; 2400 } 2401 2402 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2403 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2404 smu_bump_power_profile_mode(smu, NULL, 0); 2405 2406 return ret; 2407 } 2408 2409 static int smu_handle_task(struct smu_context *smu, 2410 enum amd_dpm_forced_level level, 2411 enum amd_pp_task task_id) 2412 { 2413 int ret = 0; 2414 2415 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2416 return -EOPNOTSUPP; 2417 2418 switch (task_id) { 2419 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2420 ret = smu_pre_display_config_changed(smu); 2421 if (ret) 2422 return ret; 2423 ret = smu_adjust_power_state_dynamic(smu, level, false); 2424 break; 2425 case AMD_PP_TASK_COMPLETE_INIT: 2426 ret = smu_adjust_power_state_dynamic(smu, level, true); 2427 break; 2428 case AMD_PP_TASK_READJUST_POWER_STATE: 2429 ret = smu_adjust_power_state_dynamic(smu, level, true); 2430 break; 2431 default: 2432 break; 2433 } 2434 2435 return ret; 2436 } 2437 2438 static int smu_handle_dpm_task(void *handle, 2439 enum amd_pp_task task_id, 2440 enum amd_pm_state_type *user_state) 2441 { 2442 struct smu_context *smu = handle; 2443 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2444 2445 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2446 2447 } 2448 2449 static int smu_switch_power_profile(void *handle, 2450 enum PP_SMC_POWER_PROFILE type, 2451 bool enable) 2452 { 2453 struct smu_context *smu = handle; 2454 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2455 int ret; 2456 2457 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2458 return -EOPNOTSUPP; 2459 2460 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2461 return -EINVAL; 2462 2463 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2464 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2465 if (enable) 2466 smu_power_profile_mode_get(smu, type); 2467 else 2468 smu_power_profile_mode_put(smu, type); 2469 /* don't switch the active workload when paused */ 2470 if (smu->pause_workload) 2471 ret = 0; 2472 else 2473 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2474 if (ret) { 2475 if (enable) 2476 smu_power_profile_mode_put(smu, type); 2477 else 2478 smu_power_profile_mode_get(smu, type); 2479 return ret; 2480 } 2481 } 2482 2483 return 0; 2484 } 2485 2486 static int smu_pause_power_profile(void *handle, 2487 bool pause) 2488 { 2489 struct smu_context *smu = handle; 2490 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2491 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2492 int ret; 2493 2494 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2495 return -EOPNOTSUPP; 2496 2497 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2498 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2499 smu->pause_workload = pause; 2500 2501 /* force to bootup default profile */ 2502 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2503 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2504 workload_mask, 2505 NULL, 2506 0); 2507 else 2508 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2509 return ret; 2510 } 2511 2512 return 0; 2513 } 2514 2515 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2516 { 2517 struct smu_context *smu = handle; 2518 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2519 2520 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2521 return -EOPNOTSUPP; 2522 2523 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2524 return -EINVAL; 2525 2526 return smu_dpm_ctx->dpm_level; 2527 } 2528 2529 static int smu_force_performance_level(void *handle, 2530 enum amd_dpm_forced_level level) 2531 { 2532 struct smu_context *smu = handle; 2533 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2534 int ret = 0; 2535 2536 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2537 return -EOPNOTSUPP; 2538 2539 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2540 return -EINVAL; 2541 2542 ret = smu_enable_umd_pstate(smu, &level); 2543 if (ret) 2544 return ret; 2545 2546 ret = smu_handle_task(smu, level, 2547 AMD_PP_TASK_READJUST_POWER_STATE); 2548 2549 /* reset user dpm clock state */ 2550 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2551 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2552 smu->user_dpm_profile.clk_dependency = 0; 2553 } 2554 2555 return ret; 2556 } 2557 2558 static int smu_set_display_count(void *handle, uint32_t count) 2559 { 2560 struct smu_context *smu = handle; 2561 2562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2563 return -EOPNOTSUPP; 2564 2565 return smu_init_display_count(smu, count); 2566 } 2567 2568 static int smu_force_smuclk_levels(struct smu_context *smu, 2569 enum smu_clk_type clk_type, 2570 uint32_t mask) 2571 { 2572 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2573 int ret = 0; 2574 2575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2576 return -EOPNOTSUPP; 2577 2578 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2579 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2580 return -EINVAL; 2581 } 2582 2583 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2584 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2585 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2586 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2587 smu_set_user_clk_dependencies(smu, clk_type); 2588 } 2589 } 2590 2591 return ret; 2592 } 2593 2594 static int smu_force_ppclk_levels(void *handle, 2595 enum pp_clock_type type, 2596 uint32_t mask) 2597 { 2598 struct smu_context *smu = handle; 2599 enum smu_clk_type clk_type; 2600 2601 switch (type) { 2602 case PP_SCLK: 2603 clk_type = SMU_SCLK; break; 2604 case PP_MCLK: 2605 clk_type = SMU_MCLK; break; 2606 case PP_PCIE: 2607 clk_type = SMU_PCIE; break; 2608 case PP_SOCCLK: 2609 clk_type = SMU_SOCCLK; break; 2610 case PP_FCLK: 2611 clk_type = SMU_FCLK; break; 2612 case PP_DCEFCLK: 2613 clk_type = SMU_DCEFCLK; break; 2614 case PP_VCLK: 2615 clk_type = SMU_VCLK; break; 2616 case PP_VCLK1: 2617 clk_type = SMU_VCLK1; break; 2618 case PP_DCLK: 2619 clk_type = SMU_DCLK; break; 2620 case PP_DCLK1: 2621 clk_type = SMU_DCLK1; break; 2622 case OD_SCLK: 2623 clk_type = SMU_OD_SCLK; break; 2624 case OD_MCLK: 2625 clk_type = SMU_OD_MCLK; break; 2626 case OD_VDDC_CURVE: 2627 clk_type = SMU_OD_VDDC_CURVE; break; 2628 case OD_RANGE: 2629 clk_type = SMU_OD_RANGE; break; 2630 default: 2631 return -EINVAL; 2632 } 2633 2634 return smu_force_smuclk_levels(smu, clk_type, mask); 2635 } 2636 2637 /* 2638 * On system suspending or resetting, the dpm_enabled 2639 * flag will be cleared. So that those SMU services which 2640 * are not supported will be gated. 2641 * However, the mp1 state setting should still be granted 2642 * even if the dpm_enabled cleared. 2643 */ 2644 static int smu_set_mp1_state(void *handle, 2645 enum pp_mp1_state mp1_state) 2646 { 2647 struct smu_context *smu = handle; 2648 int ret = 0; 2649 2650 if (!smu->pm_enabled) 2651 return -EOPNOTSUPP; 2652 2653 if (smu->ppt_funcs && 2654 smu->ppt_funcs->set_mp1_state) 2655 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2656 2657 return ret; 2658 } 2659 2660 static int smu_set_df_cstate(void *handle, 2661 enum pp_df_cstate state) 2662 { 2663 struct smu_context *smu = handle; 2664 int ret = 0; 2665 2666 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2667 return -EOPNOTSUPP; 2668 2669 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2670 return 0; 2671 2672 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2673 if (ret) 2674 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2675 2676 return ret; 2677 } 2678 2679 int smu_write_watermarks_table(struct smu_context *smu) 2680 { 2681 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2682 return -EOPNOTSUPP; 2683 2684 return smu_set_watermarks_table(smu, NULL); 2685 } 2686 2687 static int smu_set_watermarks_for_clock_ranges(void *handle, 2688 struct pp_smu_wm_range_sets *clock_ranges) 2689 { 2690 struct smu_context *smu = handle; 2691 2692 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2693 return -EOPNOTSUPP; 2694 2695 if (smu->disable_watermark) 2696 return 0; 2697 2698 return smu_set_watermarks_table(smu, clock_ranges); 2699 } 2700 2701 int smu_set_ac_dc(struct smu_context *smu) 2702 { 2703 int ret = 0; 2704 2705 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2706 return -EOPNOTSUPP; 2707 2708 /* controlled by firmware */ 2709 if (smu->dc_controlled_by_gpio) 2710 return 0; 2711 2712 ret = smu_set_power_source(smu, 2713 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2714 SMU_POWER_SOURCE_DC); 2715 if (ret) 2716 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2717 smu->adev->pm.ac_power ? "AC" : "DC"); 2718 2719 return ret; 2720 } 2721 2722 const struct amd_ip_funcs smu_ip_funcs = { 2723 .name = "smu", 2724 .early_init = smu_early_init, 2725 .late_init = smu_late_init, 2726 .sw_init = smu_sw_init, 2727 .sw_fini = smu_sw_fini, 2728 .hw_init = smu_hw_init, 2729 .hw_fini = smu_hw_fini, 2730 .late_fini = smu_late_fini, 2731 .suspend = smu_suspend, 2732 .resume = smu_resume, 2733 .is_idle = NULL, 2734 .check_soft_reset = NULL, 2735 .wait_for_idle = NULL, 2736 .soft_reset = NULL, 2737 .set_clockgating_state = smu_set_clockgating_state, 2738 .set_powergating_state = smu_set_powergating_state, 2739 }; 2740 2741 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2742 .type = AMD_IP_BLOCK_TYPE_SMC, 2743 .major = 11, 2744 .minor = 0, 2745 .rev = 0, 2746 .funcs = &smu_ip_funcs, 2747 }; 2748 2749 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2750 .type = AMD_IP_BLOCK_TYPE_SMC, 2751 .major = 12, 2752 .minor = 0, 2753 .rev = 0, 2754 .funcs = &smu_ip_funcs, 2755 }; 2756 2757 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2758 .type = AMD_IP_BLOCK_TYPE_SMC, 2759 .major = 13, 2760 .minor = 0, 2761 .rev = 0, 2762 .funcs = &smu_ip_funcs, 2763 }; 2764 2765 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2766 .type = AMD_IP_BLOCK_TYPE_SMC, 2767 .major = 14, 2768 .minor = 0, 2769 .rev = 0, 2770 .funcs = &smu_ip_funcs, 2771 }; 2772 2773 static int smu_load_microcode(void *handle) 2774 { 2775 struct smu_context *smu = handle; 2776 struct amdgpu_device *adev = smu->adev; 2777 int ret = 0; 2778 2779 if (!smu->pm_enabled) 2780 return -EOPNOTSUPP; 2781 2782 /* This should be used for non PSP loading */ 2783 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2784 return 0; 2785 2786 if (smu->ppt_funcs->load_microcode) { 2787 ret = smu->ppt_funcs->load_microcode(smu); 2788 if (ret) { 2789 dev_err(adev->dev, "Load microcode failed\n"); 2790 return ret; 2791 } 2792 } 2793 2794 if (smu->ppt_funcs->check_fw_status) { 2795 ret = smu->ppt_funcs->check_fw_status(smu); 2796 if (ret) { 2797 dev_err(adev->dev, "SMC is not ready\n"); 2798 return ret; 2799 } 2800 } 2801 2802 return ret; 2803 } 2804 2805 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2806 { 2807 int ret = 0; 2808 2809 if (smu->ppt_funcs->set_gfx_cgpg) 2810 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2811 2812 return ret; 2813 } 2814 2815 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2816 { 2817 struct smu_context *smu = handle; 2818 int ret = 0; 2819 2820 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2821 return -EOPNOTSUPP; 2822 2823 if (!smu->ppt_funcs->set_fan_speed_rpm) 2824 return -EOPNOTSUPP; 2825 2826 if (speed == U32_MAX) 2827 return -EINVAL; 2828 2829 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2830 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2831 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2832 smu->user_dpm_profile.fan_speed_rpm = speed; 2833 2834 /* Override custom PWM setting as they cannot co-exist */ 2835 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2836 smu->user_dpm_profile.fan_speed_pwm = 0; 2837 } 2838 2839 return ret; 2840 } 2841 2842 /** 2843 * smu_get_power_limit - Request one of the SMU Power Limits 2844 * 2845 * @handle: pointer to smu context 2846 * @limit: requested limit is written back to this variable 2847 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2848 * @pp_power_type: &pp_power_type type of power 2849 * Return: 0 on success, <0 on error 2850 * 2851 */ 2852 int smu_get_power_limit(void *handle, 2853 uint32_t *limit, 2854 enum pp_power_limit_level pp_limit_level, 2855 enum pp_power_type pp_power_type) 2856 { 2857 struct smu_context *smu = handle; 2858 struct amdgpu_device *adev = smu->adev; 2859 enum smu_ppt_limit_level limit_level; 2860 uint32_t limit_type; 2861 int ret = 0; 2862 2863 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2864 return -EOPNOTSUPP; 2865 2866 switch (pp_power_type) { 2867 case PP_PWR_TYPE_SUSTAINED: 2868 limit_type = SMU_DEFAULT_PPT_LIMIT; 2869 break; 2870 case PP_PWR_TYPE_FAST: 2871 limit_type = SMU_FAST_PPT_LIMIT; 2872 break; 2873 default: 2874 return -EOPNOTSUPP; 2875 } 2876 2877 switch (pp_limit_level) { 2878 case PP_PWR_LIMIT_CURRENT: 2879 limit_level = SMU_PPT_LIMIT_CURRENT; 2880 break; 2881 case PP_PWR_LIMIT_DEFAULT: 2882 limit_level = SMU_PPT_LIMIT_DEFAULT; 2883 break; 2884 case PP_PWR_LIMIT_MAX: 2885 limit_level = SMU_PPT_LIMIT_MAX; 2886 break; 2887 case PP_PWR_LIMIT_MIN: 2888 limit_level = SMU_PPT_LIMIT_MIN; 2889 break; 2890 default: 2891 return -EOPNOTSUPP; 2892 } 2893 2894 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2895 if (smu->ppt_funcs->get_ppt_limit) 2896 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2897 } else { 2898 switch (limit_level) { 2899 case SMU_PPT_LIMIT_CURRENT: 2900 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2901 case IP_VERSION(13, 0, 2): 2902 case IP_VERSION(13, 0, 6): 2903 case IP_VERSION(13, 0, 12): 2904 case IP_VERSION(13, 0, 14): 2905 case IP_VERSION(11, 0, 7): 2906 case IP_VERSION(11, 0, 11): 2907 case IP_VERSION(11, 0, 12): 2908 case IP_VERSION(11, 0, 13): 2909 ret = smu_get_asic_power_limits(smu, 2910 &smu->current_power_limit, 2911 NULL, NULL, NULL); 2912 break; 2913 default: 2914 break; 2915 } 2916 *limit = smu->current_power_limit; 2917 break; 2918 case SMU_PPT_LIMIT_DEFAULT: 2919 *limit = smu->default_power_limit; 2920 break; 2921 case SMU_PPT_LIMIT_MAX: 2922 *limit = smu->max_power_limit; 2923 break; 2924 case SMU_PPT_LIMIT_MIN: 2925 *limit = smu->min_power_limit; 2926 break; 2927 default: 2928 return -EINVAL; 2929 } 2930 } 2931 2932 return ret; 2933 } 2934 2935 static int smu_set_power_limit(void *handle, uint32_t limit) 2936 { 2937 struct smu_context *smu = handle; 2938 uint32_t limit_type = limit >> 24; 2939 int ret = 0; 2940 2941 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2942 return -EOPNOTSUPP; 2943 2944 limit &= (1<<24)-1; 2945 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2946 if (smu->ppt_funcs->set_power_limit) 2947 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2948 2949 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2950 dev_err(smu->adev->dev, 2951 "New power limit (%d) is out of range [%d,%d]\n", 2952 limit, smu->min_power_limit, smu->max_power_limit); 2953 return -EINVAL; 2954 } 2955 2956 if (!limit) 2957 limit = smu->current_power_limit; 2958 2959 if (smu->ppt_funcs->set_power_limit) { 2960 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2961 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2962 smu->user_dpm_profile.power_limit = limit; 2963 } 2964 2965 return ret; 2966 } 2967 2968 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2969 { 2970 int ret = 0; 2971 2972 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2973 return -EOPNOTSUPP; 2974 2975 if (smu->ppt_funcs->print_clk_levels) 2976 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2977 2978 return ret; 2979 } 2980 2981 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2982 { 2983 enum smu_clk_type clk_type; 2984 2985 switch (type) { 2986 case PP_SCLK: 2987 clk_type = SMU_SCLK; break; 2988 case PP_MCLK: 2989 clk_type = SMU_MCLK; break; 2990 case PP_PCIE: 2991 clk_type = SMU_PCIE; break; 2992 case PP_SOCCLK: 2993 clk_type = SMU_SOCCLK; break; 2994 case PP_FCLK: 2995 clk_type = SMU_FCLK; break; 2996 case PP_DCEFCLK: 2997 clk_type = SMU_DCEFCLK; break; 2998 case PP_VCLK: 2999 clk_type = SMU_VCLK; break; 3000 case PP_VCLK1: 3001 clk_type = SMU_VCLK1; break; 3002 case PP_DCLK: 3003 clk_type = SMU_DCLK; break; 3004 case PP_DCLK1: 3005 clk_type = SMU_DCLK1; break; 3006 case PP_ISPICLK: 3007 clk_type = SMU_ISPICLK; 3008 break; 3009 case PP_ISPXCLK: 3010 clk_type = SMU_ISPXCLK; 3011 break; 3012 case OD_SCLK: 3013 clk_type = SMU_OD_SCLK; break; 3014 case OD_MCLK: 3015 clk_type = SMU_OD_MCLK; break; 3016 case OD_VDDC_CURVE: 3017 clk_type = SMU_OD_VDDC_CURVE; break; 3018 case OD_RANGE: 3019 clk_type = SMU_OD_RANGE; break; 3020 case OD_VDDGFX_OFFSET: 3021 clk_type = SMU_OD_VDDGFX_OFFSET; break; 3022 case OD_CCLK: 3023 clk_type = SMU_OD_CCLK; break; 3024 case OD_FAN_CURVE: 3025 clk_type = SMU_OD_FAN_CURVE; break; 3026 case OD_ACOUSTIC_LIMIT: 3027 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 3028 case OD_ACOUSTIC_TARGET: 3029 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 3030 case OD_FAN_TARGET_TEMPERATURE: 3031 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 3032 case OD_FAN_MINIMUM_PWM: 3033 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 3034 case OD_FAN_ZERO_RPM_ENABLE: 3035 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 3036 case OD_FAN_ZERO_RPM_STOP_TEMP: 3037 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 3038 default: 3039 clk_type = SMU_CLK_COUNT; break; 3040 } 3041 3042 return clk_type; 3043 } 3044 3045 static int smu_print_ppclk_levels(void *handle, 3046 enum pp_clock_type type, 3047 char *buf) 3048 { 3049 struct smu_context *smu = handle; 3050 enum smu_clk_type clk_type; 3051 3052 clk_type = smu_convert_to_smuclk(type); 3053 if (clk_type == SMU_CLK_COUNT) 3054 return -EINVAL; 3055 3056 return smu_print_smuclk_levels(smu, clk_type, buf); 3057 } 3058 3059 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3060 { 3061 struct smu_context *smu = handle; 3062 enum smu_clk_type clk_type; 3063 3064 clk_type = smu_convert_to_smuclk(type); 3065 if (clk_type == SMU_CLK_COUNT) 3066 return -EINVAL; 3067 3068 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3069 return -EOPNOTSUPP; 3070 3071 if (!smu->ppt_funcs->emit_clk_levels) 3072 return -ENOENT; 3073 3074 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3075 3076 } 3077 3078 static int smu_od_edit_dpm_table(void *handle, 3079 enum PP_OD_DPM_TABLE_COMMAND type, 3080 long *input, uint32_t size) 3081 { 3082 struct smu_context *smu = handle; 3083 int ret = 0; 3084 3085 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3086 return -EOPNOTSUPP; 3087 3088 if (smu->ppt_funcs->od_edit_dpm_table) { 3089 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3090 } 3091 3092 return ret; 3093 } 3094 3095 static int smu_read_sensor(void *handle, 3096 int sensor, 3097 void *data, 3098 int *size_arg) 3099 { 3100 struct smu_context *smu = handle; 3101 struct amdgpu_device *adev = smu->adev; 3102 struct smu_umd_pstate_table *pstate_table = 3103 &smu->pstate_table; 3104 int i, ret = 0; 3105 uint32_t *size, size_val; 3106 3107 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3108 return -EOPNOTSUPP; 3109 3110 if (!data || !size_arg) 3111 return -EINVAL; 3112 3113 size_val = *size_arg; 3114 size = &size_val; 3115 3116 if (smu->ppt_funcs->read_sensor) 3117 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3118 goto unlock; 3119 3120 switch (sensor) { 3121 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3122 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3123 *size = 4; 3124 break; 3125 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3126 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3127 *size = 4; 3128 break; 3129 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3130 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3131 *size = 4; 3132 break; 3133 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3134 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3135 *size = 4; 3136 break; 3137 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3138 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3139 *size = 8; 3140 break; 3141 case AMDGPU_PP_SENSOR_UVD_POWER: 3142 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3143 *size = 4; 3144 break; 3145 case AMDGPU_PP_SENSOR_VCE_POWER: 3146 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3147 *size = 4; 3148 break; 3149 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3150 *(uint32_t *)data = 0; 3151 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3152 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3153 *(uint32_t *)data = 1; 3154 break; 3155 } 3156 } 3157 *size = 4; 3158 break; 3159 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3160 *(uint32_t *)data = 0; 3161 *size = 4; 3162 break; 3163 default: 3164 *size = 0; 3165 ret = -EOPNOTSUPP; 3166 break; 3167 } 3168 3169 unlock: 3170 // assign uint32_t to int 3171 *size_arg = size_val; 3172 3173 return ret; 3174 } 3175 3176 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3177 { 3178 int ret = -EOPNOTSUPP; 3179 struct smu_context *smu = handle; 3180 3181 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3182 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3183 3184 return ret; 3185 } 3186 3187 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3188 { 3189 int ret = -EOPNOTSUPP; 3190 struct smu_context *smu = handle; 3191 3192 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3193 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3194 3195 return ret; 3196 } 3197 3198 static int smu_get_power_profile_mode(void *handle, char *buf) 3199 { 3200 struct smu_context *smu = handle; 3201 3202 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3203 !smu->ppt_funcs->get_power_profile_mode) 3204 return -EOPNOTSUPP; 3205 if (!buf) 3206 return -EINVAL; 3207 3208 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3209 } 3210 3211 static int smu_set_power_profile_mode(void *handle, 3212 long *param, 3213 uint32_t param_size) 3214 { 3215 struct smu_context *smu = handle; 3216 bool custom = false; 3217 int ret = 0; 3218 3219 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3220 !smu->ppt_funcs->set_power_profile_mode) 3221 return -EOPNOTSUPP; 3222 3223 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3224 custom = true; 3225 /* clear frontend mask so custom changes propogate */ 3226 smu->workload_mask = 0; 3227 } 3228 3229 if ((param[param_size] != smu->power_profile_mode) || custom) { 3230 /* clear the old user preference */ 3231 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3232 /* set the new user preference */ 3233 smu_power_profile_mode_get(smu, param[param_size]); 3234 ret = smu_bump_power_profile_mode(smu, 3235 custom ? param : NULL, 3236 custom ? param_size : 0); 3237 if (ret) 3238 smu_power_profile_mode_put(smu, param[param_size]); 3239 else 3240 /* store the user's preference */ 3241 smu->power_profile_mode = param[param_size]; 3242 } 3243 3244 return ret; 3245 } 3246 3247 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3248 { 3249 struct smu_context *smu = handle; 3250 3251 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3252 return -EOPNOTSUPP; 3253 3254 if (!smu->ppt_funcs->get_fan_control_mode) 3255 return -EOPNOTSUPP; 3256 3257 if (!fan_mode) 3258 return -EINVAL; 3259 3260 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3261 3262 return 0; 3263 } 3264 3265 static int smu_set_fan_control_mode(void *handle, u32 value) 3266 { 3267 struct smu_context *smu = handle; 3268 int ret = 0; 3269 3270 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3271 return -EOPNOTSUPP; 3272 3273 if (!smu->ppt_funcs->set_fan_control_mode) 3274 return -EOPNOTSUPP; 3275 3276 if (value == U32_MAX) 3277 return -EINVAL; 3278 3279 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3280 if (ret) 3281 goto out; 3282 3283 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3284 smu->user_dpm_profile.fan_mode = value; 3285 3286 /* reset user dpm fan speed */ 3287 if (value != AMD_FAN_CTRL_MANUAL) { 3288 smu->user_dpm_profile.fan_speed_pwm = 0; 3289 smu->user_dpm_profile.fan_speed_rpm = 0; 3290 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3291 } 3292 } 3293 3294 out: 3295 return ret; 3296 } 3297 3298 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3299 { 3300 struct smu_context *smu = handle; 3301 int ret = 0; 3302 3303 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3304 return -EOPNOTSUPP; 3305 3306 if (!smu->ppt_funcs->get_fan_speed_pwm) 3307 return -EOPNOTSUPP; 3308 3309 if (!speed) 3310 return -EINVAL; 3311 3312 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3313 3314 return ret; 3315 } 3316 3317 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3318 { 3319 struct smu_context *smu = handle; 3320 int ret = 0; 3321 3322 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3323 return -EOPNOTSUPP; 3324 3325 if (!smu->ppt_funcs->set_fan_speed_pwm) 3326 return -EOPNOTSUPP; 3327 3328 if (speed == U32_MAX) 3329 return -EINVAL; 3330 3331 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3332 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3333 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3334 smu->user_dpm_profile.fan_speed_pwm = speed; 3335 3336 /* Override custom RPM setting as they cannot co-exist */ 3337 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3338 smu->user_dpm_profile.fan_speed_rpm = 0; 3339 } 3340 3341 return ret; 3342 } 3343 3344 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3345 { 3346 struct smu_context *smu = handle; 3347 int ret = 0; 3348 3349 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3350 return -EOPNOTSUPP; 3351 3352 if (!smu->ppt_funcs->get_fan_speed_rpm) 3353 return -EOPNOTSUPP; 3354 3355 if (!speed) 3356 return -EINVAL; 3357 3358 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3359 3360 return ret; 3361 } 3362 3363 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3364 { 3365 struct smu_context *smu = handle; 3366 3367 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3368 return -EOPNOTSUPP; 3369 3370 return smu_set_min_dcef_deep_sleep(smu, clk); 3371 } 3372 3373 static int smu_get_clock_by_type_with_latency(void *handle, 3374 enum amd_pp_clock_type type, 3375 struct pp_clock_levels_with_latency *clocks) 3376 { 3377 struct smu_context *smu = handle; 3378 enum smu_clk_type clk_type; 3379 int ret = 0; 3380 3381 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3382 return -EOPNOTSUPP; 3383 3384 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3385 switch (type) { 3386 case amd_pp_sys_clock: 3387 clk_type = SMU_GFXCLK; 3388 break; 3389 case amd_pp_mem_clock: 3390 clk_type = SMU_MCLK; 3391 break; 3392 case amd_pp_dcef_clock: 3393 clk_type = SMU_DCEFCLK; 3394 break; 3395 case amd_pp_disp_clock: 3396 clk_type = SMU_DISPCLK; 3397 break; 3398 default: 3399 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3400 return -EINVAL; 3401 } 3402 3403 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3404 } 3405 3406 return ret; 3407 } 3408 3409 static int smu_display_clock_voltage_request(void *handle, 3410 struct pp_display_clock_request *clock_req) 3411 { 3412 struct smu_context *smu = handle; 3413 int ret = 0; 3414 3415 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3416 return -EOPNOTSUPP; 3417 3418 if (smu->ppt_funcs->display_clock_voltage_request) 3419 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3420 3421 return ret; 3422 } 3423 3424 3425 static int smu_display_disable_memory_clock_switch(void *handle, 3426 bool disable_memory_clock_switch) 3427 { 3428 struct smu_context *smu = handle; 3429 int ret = -EINVAL; 3430 3431 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3432 return -EOPNOTSUPP; 3433 3434 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3435 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3436 3437 return ret; 3438 } 3439 3440 static int smu_set_xgmi_pstate(void *handle, 3441 uint32_t pstate) 3442 { 3443 struct smu_context *smu = handle; 3444 int ret = 0; 3445 3446 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3447 return -EOPNOTSUPP; 3448 3449 if (smu->ppt_funcs->set_xgmi_pstate) 3450 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3451 3452 if (ret) 3453 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3454 3455 return ret; 3456 } 3457 3458 static int smu_get_baco_capability(void *handle) 3459 { 3460 struct smu_context *smu = handle; 3461 3462 if (!smu->pm_enabled) 3463 return false; 3464 3465 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3466 return false; 3467 3468 return smu->ppt_funcs->get_bamaco_support(smu); 3469 } 3470 3471 static int smu_baco_set_state(void *handle, int state) 3472 { 3473 struct smu_context *smu = handle; 3474 int ret = 0; 3475 3476 if (!smu->pm_enabled) 3477 return -EOPNOTSUPP; 3478 3479 if (state == 0) { 3480 if (smu->ppt_funcs->baco_exit) 3481 ret = smu->ppt_funcs->baco_exit(smu); 3482 } else if (state == 1) { 3483 if (smu->ppt_funcs->baco_enter) 3484 ret = smu->ppt_funcs->baco_enter(smu); 3485 } else { 3486 return -EINVAL; 3487 } 3488 3489 if (ret) 3490 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3491 (state)?"enter":"exit"); 3492 3493 return ret; 3494 } 3495 3496 bool smu_mode1_reset_is_support(struct smu_context *smu) 3497 { 3498 bool ret = false; 3499 3500 if (!smu->pm_enabled) 3501 return false; 3502 3503 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3504 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3505 3506 return ret; 3507 } 3508 3509 bool smu_link_reset_is_support(struct smu_context *smu) 3510 { 3511 bool ret = false; 3512 3513 if (!smu->pm_enabled) 3514 return false; 3515 3516 if (smu->ppt_funcs && smu->ppt_funcs->link_reset_is_support) 3517 ret = smu->ppt_funcs->link_reset_is_support(smu); 3518 3519 return ret; 3520 } 3521 3522 int smu_mode1_reset(struct smu_context *smu) 3523 { 3524 int ret = 0; 3525 3526 if (!smu->pm_enabled) 3527 return -EOPNOTSUPP; 3528 3529 if (smu->ppt_funcs->mode1_reset) 3530 ret = smu->ppt_funcs->mode1_reset(smu); 3531 3532 return ret; 3533 } 3534 3535 static int smu_mode2_reset(void *handle) 3536 { 3537 struct smu_context *smu = handle; 3538 int ret = 0; 3539 3540 if (!smu->pm_enabled) 3541 return -EOPNOTSUPP; 3542 3543 if (smu->ppt_funcs->mode2_reset) 3544 ret = smu->ppt_funcs->mode2_reset(smu); 3545 3546 if (ret) 3547 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3548 3549 return ret; 3550 } 3551 3552 int smu_link_reset(struct smu_context *smu) 3553 { 3554 int ret = 0; 3555 3556 if (!smu->pm_enabled) 3557 return -EOPNOTSUPP; 3558 3559 if (smu->ppt_funcs->link_reset) 3560 ret = smu->ppt_funcs->link_reset(smu); 3561 3562 return ret; 3563 } 3564 3565 static int smu_enable_gfx_features(void *handle) 3566 { 3567 struct smu_context *smu = handle; 3568 int ret = 0; 3569 3570 if (!smu->pm_enabled) 3571 return -EOPNOTSUPP; 3572 3573 if (smu->ppt_funcs->enable_gfx_features) 3574 ret = smu->ppt_funcs->enable_gfx_features(smu); 3575 3576 if (ret) 3577 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3578 3579 return ret; 3580 } 3581 3582 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3583 struct pp_smu_nv_clock_table *max_clocks) 3584 { 3585 struct smu_context *smu = handle; 3586 int ret = 0; 3587 3588 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3589 return -EOPNOTSUPP; 3590 3591 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3592 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3593 3594 return ret; 3595 } 3596 3597 static int smu_get_uclk_dpm_states(void *handle, 3598 unsigned int *clock_values_in_khz, 3599 unsigned int *num_states) 3600 { 3601 struct smu_context *smu = handle; 3602 int ret = 0; 3603 3604 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3605 return -EOPNOTSUPP; 3606 3607 if (smu->ppt_funcs->get_uclk_dpm_states) 3608 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3609 3610 return ret; 3611 } 3612 3613 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3614 { 3615 struct smu_context *smu = handle; 3616 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3617 3618 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3619 return -EOPNOTSUPP; 3620 3621 if (smu->ppt_funcs->get_current_power_state) 3622 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3623 3624 return pm_state; 3625 } 3626 3627 static int smu_get_dpm_clock_table(void *handle, 3628 struct dpm_clocks *clock_table) 3629 { 3630 struct smu_context *smu = handle; 3631 int ret = 0; 3632 3633 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3634 return -EOPNOTSUPP; 3635 3636 if (smu->ppt_funcs->get_dpm_clock_table) 3637 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3638 3639 return ret; 3640 } 3641 3642 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3643 { 3644 struct smu_context *smu = handle; 3645 3646 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3647 return -EOPNOTSUPP; 3648 3649 if (!smu->ppt_funcs->get_gpu_metrics) 3650 return -EOPNOTSUPP; 3651 3652 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3653 } 3654 3655 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3656 size_t size) 3657 { 3658 struct smu_context *smu = handle; 3659 3660 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3661 return -EOPNOTSUPP; 3662 3663 if (!smu->ppt_funcs->get_pm_metrics) 3664 return -EOPNOTSUPP; 3665 3666 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3667 } 3668 3669 static int smu_enable_mgpu_fan_boost(void *handle) 3670 { 3671 struct smu_context *smu = handle; 3672 int ret = 0; 3673 3674 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3675 return -EOPNOTSUPP; 3676 3677 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3678 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3679 3680 return ret; 3681 } 3682 3683 static int smu_gfx_state_change_set(void *handle, 3684 uint32_t state) 3685 { 3686 struct smu_context *smu = handle; 3687 int ret = 0; 3688 3689 if (smu->ppt_funcs->gfx_state_change_set) 3690 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3691 3692 return ret; 3693 } 3694 3695 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3696 { 3697 int ret = 0; 3698 3699 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3700 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3701 3702 return ret; 3703 } 3704 3705 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3706 { 3707 int ret = -EOPNOTSUPP; 3708 3709 if (smu->ppt_funcs && 3710 smu->ppt_funcs->get_ecc_info) 3711 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3712 3713 return ret; 3714 3715 } 3716 3717 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3718 { 3719 struct smu_context *smu = handle; 3720 struct smu_table_context *smu_table = &smu->smu_table; 3721 struct smu_table *memory_pool = &smu_table->memory_pool; 3722 3723 if (!addr || !size) 3724 return -EINVAL; 3725 3726 *addr = NULL; 3727 *size = 0; 3728 if (memory_pool->bo) { 3729 *addr = memory_pool->cpu_addr; 3730 *size = memory_pool->size; 3731 } 3732 3733 return 0; 3734 } 3735 3736 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3737 size_t *size) 3738 { 3739 size_t offset = *size; 3740 int level; 3741 3742 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3743 if (level == policy->current_level) 3744 offset += sysfs_emit_at(sysbuf, offset, 3745 "%d : %s*\n", level, 3746 policy->desc->get_desc(policy, level)); 3747 else 3748 offset += sysfs_emit_at(sysbuf, offset, 3749 "%d : %s\n", level, 3750 policy->desc->get_desc(policy, level)); 3751 } 3752 3753 *size = offset; 3754 } 3755 3756 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3757 enum pp_pm_policy p_type, char *sysbuf) 3758 { 3759 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3760 struct smu_dpm_policy_ctxt *policy_ctxt; 3761 struct smu_dpm_policy *dpm_policy; 3762 size_t offset = 0; 3763 3764 policy_ctxt = dpm_ctxt->dpm_policies; 3765 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3766 !policy_ctxt->policy_mask) 3767 return -EOPNOTSUPP; 3768 3769 if (p_type == PP_PM_POLICY_NONE) 3770 return -EINVAL; 3771 3772 dpm_policy = smu_get_pm_policy(smu, p_type); 3773 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3774 return -ENOENT; 3775 3776 if (!sysbuf) 3777 return -EINVAL; 3778 3779 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3780 3781 return offset; 3782 } 3783 3784 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3785 enum pp_pm_policy p_type) 3786 { 3787 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3788 struct smu_dpm_policy_ctxt *policy_ctxt; 3789 int i; 3790 3791 policy_ctxt = dpm_ctxt->dpm_policies; 3792 if (!policy_ctxt) 3793 return NULL; 3794 3795 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3796 if (policy_ctxt->policies[i].policy_type == p_type) 3797 return &policy_ctxt->policies[i]; 3798 } 3799 3800 return NULL; 3801 } 3802 3803 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3804 int level) 3805 { 3806 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3807 struct smu_dpm_policy *dpm_policy = NULL; 3808 struct smu_dpm_policy_ctxt *policy_ctxt; 3809 int ret = -EOPNOTSUPP; 3810 3811 policy_ctxt = dpm_ctxt->dpm_policies; 3812 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3813 !policy_ctxt->policy_mask) 3814 return ret; 3815 3816 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3817 return -EINVAL; 3818 3819 dpm_policy = smu_get_pm_policy(smu, p_type); 3820 3821 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3822 return ret; 3823 3824 if (dpm_policy->current_level == level) 3825 return 0; 3826 3827 ret = dpm_policy->set_policy(smu, level); 3828 3829 if (!ret) 3830 dpm_policy->current_level = level; 3831 3832 return ret; 3833 } 3834 3835 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) 3836 { 3837 struct smu_context *smu = handle; 3838 struct smu_table_context *smu_table = &smu->smu_table; 3839 struct smu_table *tables = smu_table->tables; 3840 enum smu_table_id table_id; 3841 3842 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3843 return -EOPNOTSUPP; 3844 3845 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) 3846 return -EOPNOTSUPP; 3847 3848 table_id = smu_metrics_get_temp_table_id(type); 3849 3850 if (table_id == SMU_TABLE_COUNT) 3851 return -EINVAL; 3852 3853 /* If the request is to get size alone, return the cached table size */ 3854 if (!table && tables[table_id].cache.size) 3855 return tables[table_id].cache.size; 3856 3857 if (smu_table_cache_is_valid(&tables[table_id])) { 3858 memcpy(table, tables[table_id].cache.buffer, 3859 tables[table_id].cache.size); 3860 return tables[table_id].cache.size; 3861 } 3862 3863 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); 3864 } 3865 3866 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) 3867 { 3868 struct smu_context *smu = handle; 3869 bool ret = false; 3870 3871 if (!smu->pm_enabled) 3872 return false; 3873 3874 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) 3875 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); 3876 3877 return ret; 3878 } 3879 3880 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3881 { 3882 struct smu_context *smu = handle; 3883 3884 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3885 return -EOPNOTSUPP; 3886 3887 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3888 return -EOPNOTSUPP; 3889 3890 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3891 } 3892 3893 static const struct amd_pm_funcs swsmu_pm_funcs = { 3894 /* export for sysfs */ 3895 .set_fan_control_mode = smu_set_fan_control_mode, 3896 .get_fan_control_mode = smu_get_fan_control_mode, 3897 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3898 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3899 .force_clock_level = smu_force_ppclk_levels, 3900 .print_clock_levels = smu_print_ppclk_levels, 3901 .emit_clock_levels = smu_emit_ppclk_levels, 3902 .force_performance_level = smu_force_performance_level, 3903 .read_sensor = smu_read_sensor, 3904 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3905 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3906 .get_performance_level = smu_get_performance_level, 3907 .get_current_power_state = smu_get_current_power_state, 3908 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3909 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3910 .get_pp_num_states = smu_get_power_num_states, 3911 .get_pp_table = smu_sys_get_pp_table, 3912 .set_pp_table = smu_sys_set_pp_table, 3913 .switch_power_profile = smu_switch_power_profile, 3914 .pause_power_profile = smu_pause_power_profile, 3915 /* export to amdgpu */ 3916 .dispatch_tasks = smu_handle_dpm_task, 3917 .load_firmware = smu_load_microcode, 3918 .set_powergating_by_smu = smu_dpm_set_power_gate, 3919 .set_power_limit = smu_set_power_limit, 3920 .get_power_limit = smu_get_power_limit, 3921 .get_power_profile_mode = smu_get_power_profile_mode, 3922 .set_power_profile_mode = smu_set_power_profile_mode, 3923 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3924 .set_mp1_state = smu_set_mp1_state, 3925 .gfx_state_change_set = smu_gfx_state_change_set, 3926 /* export to DC */ 3927 .get_sclk = smu_get_sclk, 3928 .get_mclk = smu_get_mclk, 3929 .display_configuration_change = smu_display_configuration_change, 3930 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3931 .display_clock_voltage_request = smu_display_clock_voltage_request, 3932 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3933 .set_active_display_count = smu_set_display_count, 3934 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3935 .get_asic_baco_capability = smu_get_baco_capability, 3936 .set_asic_baco_state = smu_baco_set_state, 3937 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3938 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3939 .asic_reset_mode_2 = smu_mode2_reset, 3940 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3941 .set_df_cstate = smu_set_df_cstate, 3942 .set_xgmi_pstate = smu_set_xgmi_pstate, 3943 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3944 .get_pm_metrics = smu_sys_get_pm_metrics, 3945 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3946 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3947 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3948 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3949 .get_dpm_clock_table = smu_get_dpm_clock_table, 3950 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3951 .get_xcp_metrics = smu_sys_get_xcp_metrics, 3952 .get_temp_metrics = smu_sys_get_temp_metrics, 3953 .temp_metrics_is_supported = smu_temp_metrics_is_supported, 3954 }; 3955 3956 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3957 uint64_t event_arg) 3958 { 3959 int ret = -EINVAL; 3960 3961 if (smu->ppt_funcs->wait_for_event) 3962 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3963 3964 return ret; 3965 } 3966 3967 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3968 { 3969 3970 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3971 return -EOPNOTSUPP; 3972 3973 /* Confirm the buffer allocated is of correct size */ 3974 if (size != smu->stb_context.stb_buf_size) 3975 return -EINVAL; 3976 3977 /* 3978 * No need to lock smu mutex as we access STB directly through MMIO 3979 * and not going through SMU messaging route (for now at least). 3980 * For registers access rely on implementation internal locking. 3981 */ 3982 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3983 } 3984 3985 #if defined(CONFIG_DEBUG_FS) 3986 3987 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3988 { 3989 struct amdgpu_device *adev = filp->f_inode->i_private; 3990 struct smu_context *smu = adev->powerplay.pp_handle; 3991 unsigned char *buf; 3992 int r; 3993 3994 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3995 if (!buf) 3996 return -ENOMEM; 3997 3998 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3999 if (r) 4000 goto out; 4001 4002 filp->private_data = buf; 4003 4004 return 0; 4005 4006 out: 4007 kvfree(buf); 4008 return r; 4009 } 4010 4011 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 4012 loff_t *pos) 4013 { 4014 struct amdgpu_device *adev = filp->f_inode->i_private; 4015 struct smu_context *smu = adev->powerplay.pp_handle; 4016 4017 4018 if (!filp->private_data) 4019 return -EINVAL; 4020 4021 return simple_read_from_buffer(buf, 4022 size, 4023 pos, filp->private_data, 4024 smu->stb_context.stb_buf_size); 4025 } 4026 4027 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 4028 { 4029 kvfree(filp->private_data); 4030 filp->private_data = NULL; 4031 4032 return 0; 4033 } 4034 4035 /* 4036 * We have to define not only read method but also 4037 * open and release because .read takes up to PAGE_SIZE 4038 * data each time so and so is invoked multiple times. 4039 * We allocate the STB buffer in .open and release it 4040 * in .release 4041 */ 4042 static const struct file_operations smu_stb_debugfs_fops = { 4043 .owner = THIS_MODULE, 4044 .open = smu_stb_debugfs_open, 4045 .read = smu_stb_debugfs_read, 4046 .release = smu_stb_debugfs_release, 4047 .llseek = default_llseek, 4048 }; 4049 4050 #endif 4051 4052 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 4053 { 4054 #if defined(CONFIG_DEBUG_FS) 4055 4056 struct smu_context *smu = adev->powerplay.pp_handle; 4057 4058 if (!smu || (!smu->stb_context.stb_buf_size)) 4059 return; 4060 4061 debugfs_create_file_size("amdgpu_smu_stb_dump", 4062 S_IRUSR, 4063 adev_to_drm(adev)->primary->debugfs_root, 4064 adev, 4065 &smu_stb_debugfs_fops, 4066 smu->stb_context.stb_buf_size); 4067 #endif 4068 } 4069 4070 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 4071 { 4072 int ret = 0; 4073 4074 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 4075 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 4076 4077 return ret; 4078 } 4079 4080 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 4081 { 4082 int ret = 0; 4083 4084 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 4085 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 4086 4087 return ret; 4088 } 4089 4090 int smu_send_rma_reason(struct smu_context *smu) 4091 { 4092 int ret = 0; 4093 4094 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 4095 ret = smu->ppt_funcs->send_rma_reason(smu); 4096 4097 return ret; 4098 } 4099 4100 /** 4101 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 4102 * @smu: smu_context pointer 4103 * 4104 * This function checks if the SMU supports resetting the SDMA engine. 4105 * It returns true if supported, false otherwise. 4106 */ 4107 bool smu_reset_sdma_is_supported(struct smu_context *smu) 4108 { 4109 bool ret = false; 4110 4111 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma_is_supported) 4112 ret = smu->ppt_funcs->reset_sdma_is_supported(smu); 4113 4114 return ret; 4115 } 4116 4117 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4118 { 4119 int ret = 0; 4120 4121 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4122 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4123 4124 return ret; 4125 } 4126 4127 bool smu_reset_vcn_is_supported(struct smu_context *smu) 4128 { 4129 bool ret = false; 4130 4131 if (smu->ppt_funcs && smu->ppt_funcs->reset_vcn_is_supported) 4132 ret = smu->ppt_funcs->reset_vcn_is_supported(smu); 4133 4134 return ret; 4135 } 4136 4137 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4138 { 4139 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4140 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4141 4142 return 0; 4143 } 4144