1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include "smumgr.h" 25 #include "smu_ucode_xfer_vi.h" 26 #include "vegam_smumgr.h" 27 #include "smu/smu_7_1_3_d.h" 28 #include "smu/smu_7_1_3_sh_mask.h" 29 #include "gmc/gmc_8_1_d.h" 30 #include "gmc/gmc_8_1_sh_mask.h" 31 #include "oss/oss_3_0_d.h" 32 #include "gca/gfx_8_0_d.h" 33 #include "bif/bif_5_0_d.h" 34 #include "bif/bif_5_0_sh_mask.h" 35 #include "ppatomctrl.h" 36 #include "cgs_common.h" 37 #include "smu7_ppsmc.h" 38 39 #include "smu7_dyn_defaults.h" 40 41 #include "smu7_hwmgr.h" 42 #include "hardwaremanager.h" 43 #include "atombios.h" 44 #include "pppcielanes.h" 45 46 #include "dce/dce_11_2_d.h" 47 #include "dce/dce_11_2_sh_mask.h" 48 49 #define PPVEGAM_TARGETACTIVITY_DFLT 50 50 51 #define VOLTAGE_VID_OFFSET_SCALE1 625 52 #define VOLTAGE_VID_OFFSET_SCALE2 100 53 #define POWERTUNE_DEFAULT_SET_MAX 1 54 #define VDDC_VDDCI_DELTA 200 55 #define MC_CG_ARB_FREQ_F1 0x0b 56 57 #define STRAP_ASIC_RO_LSB 2168 58 #define STRAP_ASIC_RO_MSB 2175 59 60 #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415) 61 #define PPSMC_MSG_EnableModeSwitchRLCNotification ((uint16_t) 0x305) 62 63 static const struct vegam_pt_defaults 64 vegam_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { 65 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, 66 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */ 67 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 68 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, 69 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } }, 70 }; 71 72 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { 73 {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112}, 74 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160}, 75 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112}, 76 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160}, 77 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112}, 78 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160}, 79 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108}, 80 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} }; 81 82 static int vegam_smu_init(struct pp_hwmgr *hwmgr) 83 { 84 struct vegam_smumgr *smu_data; 85 86 smu_data = kzalloc(sizeof(struct vegam_smumgr), GFP_KERNEL); 87 if (smu_data == NULL) 88 return -ENOMEM; 89 90 hwmgr->smu_backend = smu_data; 91 92 if (smu7_init(hwmgr)) { 93 kfree(smu_data); 94 return -EINVAL; 95 } 96 97 return 0; 98 } 99 100 static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) 101 { 102 int result = 0; 103 104 /* Wait for smc boot up */ 105 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ 106 107 /* Assert reset */ 108 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 109 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 110 111 result = smu7_upload_smu_firmware_image(hwmgr); 112 if (result != 0) 113 return result; 114 115 /* Clear status */ 116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); 117 118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 119 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 120 121 /* De-assert reset */ 122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 123 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 124 125 126 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); 127 128 129 /* Call Test SMU message with 0x20000 offset to trigger SMU start */ 130 smu7_send_msg_to_smc_offset(hwmgr); 131 132 /* Wait done bit to be set */ 133 /* Check pass/failed indicator */ 134 135 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); 136 137 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 138 SMU_STATUS, SMU_PASS)) 139 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); 140 141 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); 142 143 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 144 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 145 146 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 147 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 148 149 /* Wait for firmware to initialize */ 150 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 151 152 return result; 153 } 154 155 static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) 156 { 157 int result = 0; 158 159 /* wait for smc boot up */ 160 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); 161 162 /* Clear firmware interrupt enable flag */ 163 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ 164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 165 ixFIRMWARE_FLAGS, 0); 166 167 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 168 SMC_SYSCON_RESET_CNTL, 169 rst_reg, 1); 170 171 result = smu7_upload_smu_firmware_image(hwmgr); 172 if (result != 0) 173 return result; 174 175 /* Set smc instruct start point at 0x0 */ 176 smu7_program_jump_on_start(hwmgr); 177 178 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 179 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 180 181 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 182 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 183 184 /* Wait for firmware to initialize */ 185 186 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, 187 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 188 189 return result; 190 } 191 192 static int vegam_start_smu(struct pp_hwmgr *hwmgr) 193 { 194 int result = 0; 195 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 196 197 /* Only start SMC if SMC RAM is not running */ 198 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) { 199 smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 200 CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); 201 smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD( 202 hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); 203 204 /* Check if SMU is running in protected mode */ 205 if (smu_data->protected_mode == 0) 206 result = vegam_start_smu_in_non_protection_mode(hwmgr); 207 else 208 result = vegam_start_smu_in_protection_mode(hwmgr); 209 210 if (result != 0) 211 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); 212 } 213 214 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ 215 smu7_read_smc_sram_dword(hwmgr, 216 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU75_Firmware_Header, SoftRegisters), 217 &(smu_data->smu7_data.soft_regs_start), 218 0x40000); 219 220 result = smu7_request_smu_load_fw(hwmgr); 221 222 return result; 223 } 224 225 static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr) 226 { 227 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 228 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 229 uint32_t tmp; 230 int result; 231 bool error = false; 232 233 result = smu7_read_smc_sram_dword(hwmgr, 234 SMU7_FIRMWARE_HEADER_LOCATION + 235 offsetof(SMU75_Firmware_Header, DpmTable), 236 &tmp, SMC_RAM_END); 237 238 if (0 == result) 239 smu_data->smu7_data.dpm_table_start = tmp; 240 241 error |= (0 != result); 242 243 result = smu7_read_smc_sram_dword(hwmgr, 244 SMU7_FIRMWARE_HEADER_LOCATION + 245 offsetof(SMU75_Firmware_Header, SoftRegisters), 246 &tmp, SMC_RAM_END); 247 248 if (!result) { 249 data->soft_regs_start = tmp; 250 smu_data->smu7_data.soft_regs_start = tmp; 251 } 252 253 error |= (0 != result); 254 255 result = smu7_read_smc_sram_dword(hwmgr, 256 SMU7_FIRMWARE_HEADER_LOCATION + 257 offsetof(SMU75_Firmware_Header, mcRegisterTable), 258 &tmp, SMC_RAM_END); 259 260 if (!result) 261 smu_data->smu7_data.mc_reg_table_start = tmp; 262 263 result = smu7_read_smc_sram_dword(hwmgr, 264 SMU7_FIRMWARE_HEADER_LOCATION + 265 offsetof(SMU75_Firmware_Header, FanTable), 266 &tmp, SMC_RAM_END); 267 268 if (!result) 269 smu_data->smu7_data.fan_table_start = tmp; 270 271 error |= (0 != result); 272 273 result = smu7_read_smc_sram_dword(hwmgr, 274 SMU7_FIRMWARE_HEADER_LOCATION + 275 offsetof(SMU75_Firmware_Header, mcArbDramTimingTable), 276 &tmp, SMC_RAM_END); 277 278 if (!result) 279 smu_data->smu7_data.arb_table_start = tmp; 280 281 error |= (0 != result); 282 283 result = smu7_read_smc_sram_dword(hwmgr, 284 SMU7_FIRMWARE_HEADER_LOCATION + 285 offsetof(SMU75_Firmware_Header, Version), 286 &tmp, SMC_RAM_END); 287 288 if (!result) 289 hwmgr->microcode_version_info.SMC = tmp; 290 291 error |= (0 != result); 292 293 return error ? -1 : 0; 294 } 295 296 static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr) 297 { 298 return 1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, 299 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON); 300 } 301 302 static uint32_t vegam_get_mac_definition(uint32_t value) 303 { 304 switch (value) { 305 case SMU_MAX_LEVELS_GRAPHICS: 306 return SMU75_MAX_LEVELS_GRAPHICS; 307 case SMU_MAX_LEVELS_MEMORY: 308 return SMU75_MAX_LEVELS_MEMORY; 309 case SMU_MAX_LEVELS_LINK: 310 return SMU75_MAX_LEVELS_LINK; 311 case SMU_MAX_ENTRIES_SMIO: 312 return SMU75_MAX_ENTRIES_SMIO; 313 case SMU_MAX_LEVELS_VDDC: 314 return SMU75_MAX_LEVELS_VDDC; 315 case SMU_MAX_LEVELS_VDDGFX: 316 return SMU75_MAX_LEVELS_VDDGFX; 317 case SMU_MAX_LEVELS_VDDCI: 318 return SMU75_MAX_LEVELS_VDDCI; 319 case SMU_MAX_LEVELS_MVDD: 320 return SMU75_MAX_LEVELS_MVDD; 321 case SMU_UVD_MCLK_HANDSHAKE_DISABLE: 322 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE | 323 SMU7_VCE_MCLK_HANDSHAKE_DISABLE; 324 } 325 326 pr_warn("can't get the mac of %x\n", value); 327 return 0; 328 } 329 330 static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr) 331 { 332 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 333 uint32_t mm_boot_level_offset, mm_boot_level_value; 334 struct phm_ppt_v1_information *table_info = 335 (struct phm_ppt_v1_information *)(hwmgr->pptable); 336 337 smu_data->smc_state_table.UvdBootLevel = 0; 338 if (table_info->mm_dep_table->count > 0) 339 smu_data->smc_state_table.UvdBootLevel = 340 (uint8_t) (table_info->mm_dep_table->count - 1); 341 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable, 342 UvdBootLevel); 343 mm_boot_level_offset /= 4; 344 mm_boot_level_offset *= 4; 345 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, 346 CGS_IND_REG__SMC, mm_boot_level_offset); 347 mm_boot_level_value &= 0x00FFFFFF; 348 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; 349 cgs_write_ind_register(hwmgr->device, 350 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); 351 352 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 353 PHM_PlatformCaps_UVDDPM) || 354 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 355 PHM_PlatformCaps_StablePState)) 356 smum_send_msg_to_smc_with_parameter(hwmgr, 357 PPSMC_MSG_UVDDPM_SetEnabledMask, 358 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), 359 NULL); 360 return 0; 361 } 362 363 static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr) 364 { 365 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 366 uint32_t mm_boot_level_offset, mm_boot_level_value; 367 struct phm_ppt_v1_information *table_info = 368 (struct phm_ppt_v1_information *)(hwmgr->pptable); 369 370 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 371 PHM_PlatformCaps_StablePState)) 372 smu_data->smc_state_table.VceBootLevel = 373 (uint8_t) (table_info->mm_dep_table->count - 1); 374 else 375 smu_data->smc_state_table.VceBootLevel = 0; 376 377 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + 378 offsetof(SMU75_Discrete_DpmTable, VceBootLevel); 379 mm_boot_level_offset /= 4; 380 mm_boot_level_offset *= 4; 381 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, 382 CGS_IND_REG__SMC, mm_boot_level_offset); 383 mm_boot_level_value &= 0xFF00FFFF; 384 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; 385 cgs_write_ind_register(hwmgr->device, 386 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); 387 388 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) 389 smum_send_msg_to_smc_with_parameter(hwmgr, 390 PPSMC_MSG_VCEDPM_SetEnabledMask, 391 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel, 392 NULL); 393 return 0; 394 } 395 396 static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr) 397 { 398 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 399 struct phm_ppt_v1_information *table_info = 400 (struct phm_ppt_v1_information *)(hwmgr->pptable); 401 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; 402 int max_entry, i; 403 404 max_entry = (SMU75_MAX_LEVELS_LINK < pcie_table->count) ? 405 SMU75_MAX_LEVELS_LINK : 406 pcie_table->count; 407 /* Setup BIF_SCLK levels */ 408 for (i = 0; i < max_entry; i++) 409 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk; 410 return 0; 411 } 412 413 static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) 414 { 415 switch (type) { 416 case SMU_UVD_TABLE: 417 vegam_update_uvd_smc_table(hwmgr); 418 break; 419 case SMU_VCE_TABLE: 420 vegam_update_vce_smc_table(hwmgr); 421 break; 422 case SMU_BIF_TABLE: 423 vegam_update_bif_smc_table(hwmgr); 424 break; 425 default: 426 break; 427 } 428 return 0; 429 } 430 431 static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 432 { 433 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 434 struct phm_ppt_v1_information *table_info = 435 (struct phm_ppt_v1_information *)(hwmgr->pptable); 436 437 if (table_info && 438 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX && 439 table_info->cac_dtp_table->usPowerTuneDataSetID) 440 smu_data->power_tune_defaults = 441 &vegam_power_tune_data_set_array 442 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1]; 443 else 444 smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0]; 445 446 } 447 448 static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, 449 SMU75_Discrete_DpmTable *table) 450 { 451 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 452 uint32_t count, level; 453 454 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 455 count = data->mvdd_voltage_table.count; 456 if (count > SMU_MAX_SMIO_LEVELS) 457 count = SMU_MAX_SMIO_LEVELS; 458 for (level = 0; level < count; level++) { 459 table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US( 460 data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE); 461 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ 462 table->SmioTable2.Pattern[level].Smio = 463 (uint8_t) level; 464 table->Smio[level] |= 465 data->mvdd_voltage_table.entries[level].smio_low; 466 } 467 table->SmioMask2 = data->mvdd_voltage_table.mask_low; 468 469 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); 470 } 471 472 return 0; 473 } 474 475 static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr, 476 struct SMU75_Discrete_DpmTable *table) 477 { 478 uint32_t count, level; 479 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 480 481 count = data->vddci_voltage_table.count; 482 483 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 484 if (count > SMU_MAX_SMIO_LEVELS) 485 count = SMU_MAX_SMIO_LEVELS; 486 for (level = 0; level < count; ++level) { 487 table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US( 488 data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE); 489 table->SmioTable1.Pattern[level].Smio = (uint8_t) level; 490 491 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low; 492 } 493 } 494 495 table->SmioMask1 = data->vddci_voltage_table.mask_low; 496 497 return 0; 498 } 499 500 static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr, 501 struct SMU75_Discrete_DpmTable *table) 502 { 503 uint32_t count; 504 uint8_t index; 505 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 506 struct phm_ppt_v1_information *table_info = 507 (struct phm_ppt_v1_information *)(hwmgr->pptable); 508 struct phm_ppt_v1_voltage_lookup_table *lookup_table = 509 table_info->vddc_lookup_table; 510 /* tables is already swapped, so in order to use the value from it, 511 * we need to swap it back. 512 * We are populating vddc CAC data to BapmVddc table 513 * in split and merged mode 514 */ 515 for (count = 0; count < lookup_table->count; count++) { 516 index = phm_get_voltage_index(lookup_table, 517 data->vddc_voltage_table.entries[count].value); 518 table->BapmVddcVidLoSidd[count] = 519 convert_to_vid(lookup_table->entries[index].us_cac_low); 520 table->BapmVddcVidHiSidd[count] = 521 convert_to_vid(lookup_table->entries[index].us_cac_mid); 522 table->BapmVddcVidHiSidd2[count] = 523 convert_to_vid(lookup_table->entries[index].us_cac_high); 524 } 525 526 return 0; 527 } 528 529 static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, 530 struct SMU75_Discrete_DpmTable *table) 531 { 532 vegam_populate_smc_vddci_table(hwmgr, table); 533 vegam_populate_smc_mvdd_table(hwmgr, table); 534 vegam_populate_cac_table(hwmgr, table); 535 536 return 0; 537 } 538 539 static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr, 540 struct SMU75_Discrete_Ulv *state) 541 { 542 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 543 struct phm_ppt_v1_information *table_info = 544 (struct phm_ppt_v1_information *)(hwmgr->pptable); 545 546 state->CcPwrDynRm = 0; 547 state->CcPwrDynRm1 = 0; 548 549 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset; 550 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * 551 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 552 553 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; 554 555 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); 556 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); 557 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); 558 559 return 0; 560 } 561 562 static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr, 563 struct SMU75_Discrete_DpmTable *table) 564 { 565 return vegam_populate_ulv_level(hwmgr, &table->Ulv); 566 } 567 568 static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr, 569 struct SMU75_Discrete_DpmTable *table) 570 { 571 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 572 struct vegam_smumgr *smu_data = 573 (struct vegam_smumgr *)(hwmgr->smu_backend); 574 struct smu7_dpm_table *dpm_table = &data->dpm_table; 575 int i; 576 577 /* Index (dpm_table->pcie_speed_table.count) 578 * is reserved for PCIE boot level. */ 579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { 580 table->LinkLevel[i].PcieGenSpeed = 581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 582 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( 583 dpm_table->pcie_speed_table.dpm_levels[i].param1); 584 table->LinkLevel[i].EnabledForActivity = 1; 585 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); 586 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); 587 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); 588 } 589 590 smu_data->smc_state_table.LinkLevelCount = 591 (uint8_t)dpm_table->pcie_speed_table.count; 592 593 /* To Do move to hwmgr */ 594 data->dpm_level_enable_mask.pcie_dpm_enable_mask = 595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 596 597 return 0; 598 } 599 600 static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, 601 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, 602 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) 603 { 604 uint32_t i; 605 uint16_t vddci; 606 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 607 608 *voltage = *mvdd = 0; 609 610 /* clock - voltage dependency table is empty table */ 611 if (dep_table->count == 0) 612 return -EINVAL; 613 614 for (i = 0; i < dep_table->count; i++) { 615 /* find first sclk bigger than request */ 616 if (dep_table->entries[i].clk >= clock) { 617 *voltage |= (dep_table->entries[i].vddc * 618 VOLTAGE_SCALE) << VDDC_SHIFT; 619 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control) 620 *voltage |= (data->vbios_boot_state.vddci_bootup_value * 621 VOLTAGE_SCALE) << VDDCI_SHIFT; 622 else if (dep_table->entries[i].vddci) 623 *voltage |= (dep_table->entries[i].vddci * 624 VOLTAGE_SCALE) << VDDCI_SHIFT; 625 else { 626 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), 627 (dep_table->entries[i].vddc - 628 (uint16_t)VDDC_VDDCI_DELTA)); 629 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 630 } 631 632 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) 633 *mvdd = data->vbios_boot_state.mvdd_bootup_value * 634 VOLTAGE_SCALE; 635 else if (dep_table->entries[i].mvdd) 636 *mvdd = (uint32_t) dep_table->entries[i].mvdd * 637 VOLTAGE_SCALE; 638 639 *voltage |= 1 << PHASES_SHIFT; 640 return 0; 641 } 642 } 643 644 /* sclk is bigger than max sclk in the dependence table */ 645 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; 646 647 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control) 648 *voltage |= (data->vbios_boot_state.vddci_bootup_value * 649 VOLTAGE_SCALE) << VDDCI_SHIFT; 650 else if (dep_table->entries[i - 1].vddci) 651 *voltage |= (dep_table->entries[i - 1].vddci * 652 VOLTAGE_SCALE) << VDDC_SHIFT; 653 else { 654 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), 655 (dep_table->entries[i - 1].vddc - 656 (uint16_t)VDDC_VDDCI_DELTA)); 657 658 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 659 } 660 661 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) 662 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE; 663 else if (dep_table->entries[i].mvdd) 664 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; 665 666 return 0; 667 } 668 669 static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr, 670 SMU75_Discrete_DpmTable *table) 671 { 672 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 673 uint32_t i, ref_clk; 674 675 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; 676 677 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 678 679 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { 680 for (i = 0; i < NUM_SCLK_RANGE; i++) { 681 table->SclkFcwRangeTable[i].vco_setting = 682 range_table_from_vbios.entry[i].ucVco_setting; 683 table->SclkFcwRangeTable[i].postdiv = 684 range_table_from_vbios.entry[i].ucPostdiv; 685 table->SclkFcwRangeTable[i].fcw_pcc = 686 range_table_from_vbios.entry[i].usFcw_pcc; 687 688 table->SclkFcwRangeTable[i].fcw_trans_upper = 689 range_table_from_vbios.entry[i].usFcw_trans_upper; 690 table->SclkFcwRangeTable[i].fcw_trans_lower = 691 range_table_from_vbios.entry[i].usRcw_trans_lower; 692 693 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); 694 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); 695 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); 696 } 697 return; 698 } 699 700 for (i = 0; i < NUM_SCLK_RANGE; i++) { 701 smu_data->range_table[i].trans_lower_frequency = 702 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; 703 smu_data->range_table[i].trans_upper_frequency = 704 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; 705 706 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting; 707 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; 708 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc; 709 710 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper; 711 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower; 712 713 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); 714 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); 715 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); 716 } 717 } 718 719 static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr, 720 uint32_t clock, SMU_SclkSetting *sclk_setting) 721 { 722 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 723 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); 724 struct pp_atomctrl_clock_dividers_ai dividers; 725 uint32_t ref_clock; 726 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq; 727 uint8_t i; 728 int result; 729 uint64_t temp; 730 731 sclk_setting->SclkFrequency = clock; 732 /* get the engine clock dividers for this clock value */ 733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); 734 if (result == 0) { 735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; 736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; 737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; 738 sclk_setting->PllRange = dividers.ucSclkPllRange; 739 sclk_setting->Sclk_slew_rate = 0x400; 740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; 741 sclk_setting->Pcc_down_slew_rate = 0xffff; 742 sclk_setting->SSc_En = dividers.ucSscEnable; 743 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; 744 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; 745 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac; 746 return result; 747 } 748 749 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 750 751 for (i = 0; i < NUM_SCLK_RANGE; i++) { 752 if (clock > smu_data->range_table[i].trans_lower_frequency 753 && clock <= smu_data->range_table[i].trans_upper_frequency) { 754 sclk_setting->PllRange = i; 755 break; 756 } 757 } 758 759 sclk_setting->Fcw_int = (uint16_t) 760 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / 761 ref_clock); 762 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; 763 temp <<= 0x10; 764 do_div(temp, ref_clock); 765 sclk_setting->Fcw_frac = temp & 0xffff; 766 767 pcc_target_percent = 10; /* Hardcode 10% for now. */ 768 pcc_target_freq = clock - (clock * pcc_target_percent / 100); 769 sclk_setting->Pcc_fcw_int = (uint16_t) 770 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / 771 ref_clock); 772 773 ss_target_percent = 2; /* Hardcode 2% for now. */ 774 sclk_setting->SSc_En = 0; 775 if (ss_target_percent) { 776 sclk_setting->SSc_En = 1; 777 ss_target_freq = clock - (clock * ss_target_percent / 100); 778 sclk_setting->Fcw1_int = (uint16_t) 779 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / 780 ref_clock); 781 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; 782 temp <<= 0x10; 783 do_div(temp, ref_clock); 784 sclk_setting->Fcw1_frac = temp & 0xffff; 785 } 786 787 return 0; 788 } 789 790 static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock, 791 uint32_t clock_insr) 792 { 793 uint8_t i; 794 uint32_t temp; 795 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK); 796 797 PP_ASSERT_WITH_CODE((clock >= min), 798 "Engine clock can't satisfy stutter requirement!", 799 return 0); 800 for (i = 31; ; i--) { 801 temp = clock / (i + 1); 802 803 if (temp >= min || i == 0) 804 break; 805 } 806 return i; 807 } 808 809 static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr, 810 uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level) 811 { 812 int result; 813 /* PP_Clocks minClocks; */ 814 uint32_t mvdd; 815 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 816 struct phm_ppt_v1_information *table_info = 817 (struct phm_ppt_v1_information *)(hwmgr->pptable); 818 SMU_SclkSetting curr_sclk_setting = { 0 }; 819 820 result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting); 821 822 /* populate graphics levels */ 823 result = vegam_get_dependency_volt_by_clk(hwmgr, 824 table_info->vdd_dep_on_sclk, clock, 825 &level->MinVoltage, &mvdd); 826 827 PP_ASSERT_WITH_CODE((0 == result), 828 "can not find VDDC voltage value for " 829 "VDDC engine clock dependency table", 830 return result); 831 level->ActivityLevel = (uint16_t)(SclkDPMTuning_VEGAM >> DPMTuning_Activity_Shift); 832 833 level->CcPwrDynRm = 0; 834 level->CcPwrDynRm1 = 0; 835 level->EnabledForActivity = 0; 836 level->EnabledForThrottle = 1; 837 level->VoltageDownHyst = 0; 838 level->PowerThrottle = 0; 839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; 840 841 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) 842 level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock, 843 hwmgr->display_config->min_core_set_clock_in_sr); 844 845 level->SclkSetting = curr_sclk_setting; 846 847 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage); 848 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm); 849 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1); 850 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel); 851 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency); 852 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int); 853 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac); 854 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int); 855 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate); 856 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate); 857 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate); 858 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int); 859 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac); 860 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate); 861 return 0; 862 } 863 864 static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 865 { 866 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 867 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 868 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; 869 struct phm_ppt_v1_information *table_info = 870 (struct phm_ppt_v1_information *)(hwmgr->pptable); 871 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; 872 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; 873 int result = 0; 874 uint32_t array = smu_data->smu7_data.dpm_table_start + 875 offsetof(SMU75_Discrete_DpmTable, GraphicsLevel); 876 uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) * 877 SMU75_MAX_LEVELS_GRAPHICS; 878 struct SMU75_Discrete_GraphicsLevel *levels = 879 smu_data->smc_state_table.GraphicsLevel; 880 uint32_t i, max_entry; 881 uint8_t hightest_pcie_level_enabled = 0, 882 lowest_pcie_level_enabled = 0, 883 mid_pcie_level_enabled = 0, 884 count = 0; 885 886 vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table)); 887 888 for (i = 0; i < dpm_table->sclk_table.count; i++) { 889 890 result = vegam_populate_single_graphic_level(hwmgr, 891 dpm_table->sclk_table.dpm_levels[i].value, 892 &(smu_data->smc_state_table.GraphicsLevel[i])); 893 if (result) 894 return result; 895 896 levels[i].UpHyst = (uint8_t) 897 (SclkDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift); 898 levels[i].DownHyst = (uint8_t) 899 (SclkDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift); 900 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ 901 if (i > 1) 902 levels[i].DeepSleepDivId = 0; 903 } 904 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 905 PHM_PlatformCaps_SPLLShutdownSupport)) 906 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; 907 908 smu_data->smc_state_table.GraphicsDpmLevelCount = 909 (uint8_t)dpm_table->sclk_table.count; 910 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = 911 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 912 913 for (i = 0; i < dpm_table->sclk_table.count; i++) 914 levels[i].EnabledForActivity = 915 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; 916 917 if (pcie_table != NULL) { 918 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), 919 "There must be 1 or more PCIE levels defined in PPTable.", 920 return -EINVAL); 921 max_entry = pcie_entry_cnt - 1; 922 for (i = 0; i < dpm_table->sclk_table.count; i++) 923 levels[i].pcieDpmLevel = 924 (uint8_t) ((i < max_entry) ? i : max_entry); 925 } else { 926 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && 927 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & 928 (1 << (hightest_pcie_level_enabled + 1))) != 0)) 929 hightest_pcie_level_enabled++; 930 931 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && 932 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & 933 (1 << lowest_pcie_level_enabled)) == 0)) 934 lowest_pcie_level_enabled++; 935 936 while ((count < hightest_pcie_level_enabled) && 937 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & 938 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) 939 count++; 940 941 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) < 942 hightest_pcie_level_enabled ? 943 (lowest_pcie_level_enabled + 1 + count) : 944 hightest_pcie_level_enabled; 945 946 /* set pcieDpmLevel to hightest_pcie_level_enabled */ 947 for (i = 2; i < dpm_table->sclk_table.count; i++) 948 levels[i].pcieDpmLevel = hightest_pcie_level_enabled; 949 950 /* set pcieDpmLevel to lowest_pcie_level_enabled */ 951 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; 952 953 /* set pcieDpmLevel to mid_pcie_level_enabled */ 954 levels[1].pcieDpmLevel = mid_pcie_level_enabled; 955 } 956 /* level count will send to smc once at init smc table and never change */ 957 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, 958 (uint32_t)array_size, SMC_RAM_END); 959 960 return result; 961 } 962 963 static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr, 964 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) 965 { 966 struct pp_atomctrl_memory_clock_param_ai mpll_param; 967 968 PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr, 969 clock, &mpll_param), 970 "Failed to retrieve memory pll parameter.", 971 return -EINVAL); 972 973 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock; 974 mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int; 975 mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac; 976 mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv; 977 978 return 0; 979 } 980 981 static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr, 982 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) 983 { 984 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 985 struct phm_ppt_v1_information *table_info = 986 (struct phm_ppt_v1_information *)(hwmgr->pptable); 987 int result = 0; 988 uint32_t mclk_stutter_mode_threshold = 60000; 989 990 991 if (table_info->vdd_dep_on_mclk) { 992 result = vegam_get_dependency_volt_by_clk(hwmgr, 993 table_info->vdd_dep_on_mclk, clock, 994 &mem_level->MinVoltage, &mem_level->MinMvdd); 995 PP_ASSERT_WITH_CODE(!result, 996 "can not find MinVddc voltage value from memory " 997 "VDDC voltage dependency table", return result); 998 } 999 1000 result = vegam_calculate_mclk_params(hwmgr, clock, mem_level); 1001 PP_ASSERT_WITH_CODE(!result, 1002 "Failed to calculate mclk params.", 1003 return -EINVAL); 1004 1005 mem_level->EnabledForThrottle = 1; 1006 mem_level->EnabledForActivity = 0; 1007 mem_level->VoltageDownHyst = 0; 1008 mem_level->ActivityLevel = (uint16_t) 1009 (MemoryDPMTuning_VEGAM >> DPMTuning_Activity_Shift); 1010 mem_level->StutterEnable = false; 1011 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1012 1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; 1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; 1015 1016 if (mclk_stutter_mode_threshold && 1017 (clock <= mclk_stutter_mode_threshold) && 1018 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, 1019 STUTTER_ENABLE) & 0x1)) 1020 mem_level->StutterEnable = true; 1021 1022 if (!result) { 1023 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd); 1024 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency); 1025 CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_int); 1026 CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_frac); 1027 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel); 1028 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage); 1029 } 1030 1031 return result; 1032 } 1033 1034 static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1035 { 1036 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1037 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1038 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; 1039 int result; 1040 /* populate MCLK dpm table to SMU7 */ 1041 uint32_t array = smu_data->smu7_data.dpm_table_start + 1042 offsetof(SMU75_Discrete_DpmTable, MemoryLevel); 1043 uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) * 1044 SMU75_MAX_LEVELS_MEMORY; 1045 struct SMU75_Discrete_MemoryLevel *levels = 1046 smu_data->smc_state_table.MemoryLevel; 1047 uint32_t i; 1048 1049 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1050 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1051 "can not populate memory level as memory clock is zero", 1052 return -EINVAL); 1053 result = vegam_populate_single_memory_level(hwmgr, 1054 dpm_table->mclk_table.dpm_levels[i].value, 1055 &levels[i]); 1056 1057 if (result) 1058 return result; 1059 1060 levels[i].UpHyst = (uint8_t) 1061 (MemoryDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift); 1062 levels[i].DownHyst = (uint8_t) 1063 (MemoryDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift); 1064 } 1065 1066 smu_data->smc_state_table.MemoryDpmLevelCount = 1067 (uint8_t)dpm_table->mclk_table.count; 1068 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = 1069 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1070 1071 for (i = 0; i < dpm_table->mclk_table.count; i++) 1072 levels[i].EnabledForActivity = 1073 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1; 1074 1075 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = 1076 PPSMC_DISPLAY_WATERMARK_HIGH; 1077 1078 /* level count will send to smc once at init smc table and never change */ 1079 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, 1080 (uint32_t)array_size, SMC_RAM_END); 1081 1082 return result; 1083 } 1084 1085 static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr, 1086 uint32_t mclk, SMIO_Pattern *smio_pat) 1087 { 1088 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1089 struct phm_ppt_v1_information *table_info = 1090 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1091 uint32_t i = 0; 1092 1093 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { 1094 /* find mvdd value which clock is more than request */ 1095 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { 1096 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { 1097 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value; 1098 break; 1099 } 1100 } 1101 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, 1102 "MVDD Voltage is outside the supported range.", 1103 return -EINVAL); 1104 } else 1105 return -EINVAL; 1106 1107 return 0; 1108 } 1109 1110 static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, 1111 SMU75_Discrete_DpmTable *table) 1112 { 1113 int result = 0; 1114 uint32_t sclk_frequency; 1115 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1116 struct phm_ppt_v1_information *table_info = 1117 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1118 SMIO_Pattern vol_level; 1119 uint32_t mvdd; 1120 1121 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1122 1123 /* Get MinVoltage and Frequency from DPM0, 1124 * already converted to SMC_UL */ 1125 sclk_frequency = data->vbios_boot_state.sclk_bootup_value; 1126 result = vegam_get_dependency_volt_by_clk(hwmgr, 1127 table_info->vdd_dep_on_sclk, 1128 sclk_frequency, 1129 &table->ACPILevel.MinVoltage, &mvdd); 1130 PP_ASSERT_WITH_CODE(!result, 1131 "Cannot find ACPI VDDC voltage value " 1132 "in Clock Dependency Table", 1133 ); 1134 1135 result = vegam_calculate_sclk_params(hwmgr, sclk_frequency, 1136 &(table->ACPILevel.SclkSetting)); 1137 PP_ASSERT_WITH_CODE(!result, 1138 "Error retrieving Engine Clock dividers from VBIOS.", 1139 return result); 1140 1141 table->ACPILevel.DeepSleepDivId = 0; 1142 table->ACPILevel.CcPwrDynRm = 0; 1143 table->ACPILevel.CcPwrDynRm1 = 0; 1144 1145 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); 1146 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage); 1147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); 1148 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); 1149 1150 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency); 1151 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int); 1152 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac); 1153 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int); 1154 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate); 1155 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate); 1156 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate); 1157 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int); 1158 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac); 1159 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate); 1160 1161 1162 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */ 1163 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value; 1164 result = vegam_get_dependency_volt_by_clk(hwmgr, 1165 table_info->vdd_dep_on_mclk, 1166 table->MemoryACPILevel.MclkFrequency, 1167 &table->MemoryACPILevel.MinVoltage, &mvdd); 1168 PP_ASSERT_WITH_CODE((0 == result), 1169 "Cannot find ACPI VDDCI voltage value " 1170 "in Clock Dependency Table", 1171 ); 1172 1173 if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level)) 1174 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage); 1175 else 1176 table->MemoryACPILevel.MinMvdd = 0; 1177 1178 table->MemoryACPILevel.StutterEnable = false; 1179 1180 table->MemoryACPILevel.EnabledForThrottle = 0; 1181 table->MemoryACPILevel.EnabledForActivity = 0; 1182 table->MemoryACPILevel.UpHyst = 0; 1183 table->MemoryACPILevel.DownHyst = 100; 1184 table->MemoryACPILevel.VoltageDownHyst = 0; 1185 table->MemoryACPILevel.ActivityLevel = 1186 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity); 1187 1188 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency); 1189 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage); 1190 1191 return result; 1192 } 1193 1194 static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr, 1195 SMU75_Discrete_DpmTable *table) 1196 { 1197 int result = -EINVAL; 1198 uint8_t count; 1199 struct pp_atomctrl_clock_dividers_vi dividers; 1200 struct phm_ppt_v1_information *table_info = 1201 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1202 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1203 table_info->mm_dep_table; 1204 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1205 uint32_t vddci; 1206 1207 table->VceLevelCount = (uint8_t)(mm_table->count); 1208 table->VceBootLevel = 0; 1209 1210 for (count = 0; count < table->VceLevelCount; count++) { 1211 table->VceLevel[count].Frequency = mm_table->entries[count].eclk; 1212 table->VceLevel[count].MinVoltage = 0; 1213 table->VceLevel[count].MinVoltage |= 1214 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; 1215 1216 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) 1217 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), 1218 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); 1219 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) 1220 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; 1221 else 1222 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT; 1223 1224 1225 table->VceLevel[count].MinVoltage |= 1226 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 1227 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; 1228 1229 /*retrieve divider value for VBIOS */ 1230 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1231 table->VceLevel[count].Frequency, ÷rs); 1232 PP_ASSERT_WITH_CODE((0 == result), 1233 "can not find divide id for VCE engine clock", 1234 return result); 1235 1236 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; 1237 1238 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); 1239 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); 1240 } 1241 return result; 1242 } 1243 1244 static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, 1245 int32_t eng_clock, int32_t mem_clock, 1246 SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs) 1247 { 1248 uint32_t dram_timing; 1249 uint32_t dram_timing2; 1250 uint32_t burst_time; 1251 uint32_t rfsh_rate; 1252 uint32_t misc3; 1253 1254 int result; 1255 1256 result = atomctrl_set_engine_dram_timings_rv770(hwmgr, 1257 eng_clock, mem_clock); 1258 PP_ASSERT_WITH_CODE(result == 0, 1259 "Error calling VBIOS to set DRAM_TIMING.", 1260 return result); 1261 1262 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); 1263 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); 1264 burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME); 1265 rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE); 1266 misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3); 1267 1268 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); 1269 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); 1270 arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time); 1271 arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate); 1272 arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3); 1273 1274 return 0; 1275 } 1276 1277 static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) 1278 { 1279 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1280 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1281 struct SMU75_Discrete_MCArbDramTimingTable arb_regs; 1282 uint32_t i, j; 1283 int result = 0; 1284 1285 memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable)); 1286 1287 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { 1288 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { 1289 result = vegam_populate_memory_timing_parameters(hwmgr, 1290 hw_data->dpm_table.sclk_table.dpm_levels[i].value, 1291 hw_data->dpm_table.mclk_table.dpm_levels[j].value, 1292 &arb_regs.entries[i][j]); 1293 if (result) 1294 return result; 1295 } 1296 } 1297 1298 result = smu7_copy_bytes_to_smc( 1299 hwmgr, 1300 smu_data->smu7_data.arb_table_start, 1301 (uint8_t *)&arb_regs, 1302 sizeof(SMU75_Discrete_MCArbDramTimingTable), 1303 SMC_RAM_END); 1304 return result; 1305 } 1306 1307 static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, 1308 struct SMU75_Discrete_DpmTable *table) 1309 { 1310 int result = -EINVAL; 1311 uint8_t count; 1312 struct pp_atomctrl_clock_dividers_vi dividers; 1313 struct phm_ppt_v1_information *table_info = 1314 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1315 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1316 table_info->mm_dep_table; 1317 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1318 uint32_t vddci; 1319 1320 table->UvdLevelCount = (uint8_t)(mm_table->count); 1321 table->UvdBootLevel = 0; 1322 1323 for (count = 0; count < table->UvdLevelCount; count++) { 1324 table->UvdLevel[count].MinVoltage = 0; 1325 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; 1326 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; 1327 table->UvdLevel[count].MinVoltage |= 1328 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; 1329 1330 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) 1331 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), 1332 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); 1333 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) 1334 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; 1335 else 1336 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT; 1337 1338 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 1339 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; 1340 1341 /* retrieve divider value for VBIOS */ 1342 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1343 table->UvdLevel[count].VclkFrequency, ÷rs); 1344 PP_ASSERT_WITH_CODE((0 == result), 1345 "can not find divide id for Vclk clock", return result); 1346 1347 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; 1348 1349 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1350 table->UvdLevel[count].DclkFrequency, ÷rs); 1351 PP_ASSERT_WITH_CODE((0 == result), 1352 "can not find divide id for Dclk clock", return result); 1353 1354 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; 1355 1356 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); 1357 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); 1358 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage); 1359 } 1360 1361 return result; 1362 } 1363 1364 static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr, 1365 struct SMU75_Discrete_DpmTable *table) 1366 { 1367 int result = 0; 1368 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1369 1370 table->GraphicsBootLevel = 0; 1371 table->MemoryBootLevel = 0; 1372 1373 /* find boot level from dpm table */ 1374 result = phm_find_boot_level(&(data->dpm_table.sclk_table), 1375 data->vbios_boot_state.sclk_bootup_value, 1376 (uint32_t *)&(table->GraphicsBootLevel)); 1377 if (result) 1378 return result; 1379 1380 result = phm_find_boot_level(&(data->dpm_table.mclk_table), 1381 data->vbios_boot_state.mclk_bootup_value, 1382 (uint32_t *)&(table->MemoryBootLevel)); 1383 1384 if (result) 1385 return result; 1386 1387 table->BootVddc = data->vbios_boot_state.vddc_bootup_value * 1388 VOLTAGE_SCALE; 1389 table->BootVddci = data->vbios_boot_state.vddci_bootup_value * 1390 VOLTAGE_SCALE; 1391 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value * 1392 VOLTAGE_SCALE; 1393 1394 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc); 1395 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci); 1396 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); 1397 1398 return 0; 1399 } 1400 1401 static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr) 1402 { 1403 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1404 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1405 struct phm_ppt_v1_information *table_info = 1406 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1407 uint8_t count, level; 1408 1409 count = (uint8_t)(table_info->vdd_dep_on_sclk->count); 1410 1411 for (level = 0; level < count; level++) { 1412 if (table_info->vdd_dep_on_sclk->entries[level].clk >= 1413 hw_data->vbios_boot_state.sclk_bootup_value) { 1414 smu_data->smc_state_table.GraphicsBootLevel = level; 1415 break; 1416 } 1417 } 1418 1419 count = (uint8_t)(table_info->vdd_dep_on_mclk->count); 1420 for (level = 0; level < count; level++) { 1421 if (table_info->vdd_dep_on_mclk->entries[level].clk >= 1422 hw_data->vbios_boot_state.mclk_bootup_value) { 1423 smu_data->smc_state_table.MemoryBootLevel = level; 1424 break; 1425 } 1426 } 1427 1428 return 0; 1429 } 1430 1431 static uint16_t scale_fan_gain_settings(uint16_t raw_setting) 1432 { 1433 uint32_t tmp; 1434 tmp = raw_setting * 4096 / 100; 1435 return (uint16_t)tmp; 1436 } 1437 1438 static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) 1439 { 1440 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1441 1442 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults; 1443 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1444 struct phm_ppt_v1_information *table_info = 1445 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1446 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table; 1447 struct pp_advance_fan_control_parameters *fan_table = 1448 &hwmgr->thermal_controller.advanceFanControlParameters; 1449 int i, j, k; 1450 const uint16_t *pdef1; 1451 const uint16_t *pdef2; 1452 1453 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); 1454 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); 1455 1456 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, 1457 "Target Operating Temp is out of Range!", 1458 ); 1459 1460 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( 1461 cac_dtp_table->usTargetOperatingTemp * 256); 1462 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( 1463 cac_dtp_table->usTemperatureLimitHotspot * 256); 1464 table->FanGainEdge = PP_HOST_TO_SMC_US( 1465 scale_fan_gain_settings(fan_table->usFanGainEdge)); 1466 table->FanGainHotspot = PP_HOST_TO_SMC_US( 1467 scale_fan_gain_settings(fan_table->usFanGainHotspot)); 1468 1469 pdef1 = defaults->BAPMTI_R; 1470 pdef2 = defaults->BAPMTI_RC; 1471 1472 for (i = 0; i < SMU75_DTE_ITERATIONS; i++) { 1473 for (j = 0; j < SMU75_DTE_SOURCES; j++) { 1474 for (k = 0; k < SMU75_DTE_SINKS; k++) { 1475 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1); 1476 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2); 1477 pdef1++; 1478 pdef2++; 1479 } 1480 } 1481 } 1482 1483 return 0; 1484 } 1485 1486 static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) 1487 { 1488 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; 1489 struct vegam_smumgr *smu_data = 1490 (struct vegam_smumgr *)(hwmgr->smu_backend); 1491 1492 uint8_t i, stretch_amount, volt_offset = 0; 1493 struct phm_ppt_v1_information *table_info = 1494 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1495 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1496 table_info->vdd_dep_on_sclk; 1497 1498 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount; 1499 1500 atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB, 1501 &efuse); 1502 1503 min = 1200; 1504 max = 2500; 1505 1506 ro = efuse * (max - min) / 255 + min; 1507 1508 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ 1509 for (i = 0; i < sclk_table->count; i++) { 1510 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= 1511 sclk_table->entries[i].cks_enable << i; 1512 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 1513 136418 - (ro - 70) * 1000000) / 1514 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000)); 1515 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 1516 3232 - (ro - 65) * 1000000) / 1517 (2522480 - sclk_table->entries[i].clk/100 * 115764/100)); 1518 1519 if (volt_without_cks >= volt_with_cks) 1520 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + 1521 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625); 1522 1523 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; 1524 } 1525 1526 smu_data->smc_state_table.LdoRefSel = 1527 (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? 1528 table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5; 1529 /* Populate CKS Lookup Table */ 1530 if (!(stretch_amount == 1 || stretch_amount == 2 || 1531 stretch_amount == 5 || stretch_amount == 3 || 1532 stretch_amount == 4)) { 1533 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1534 PHM_PlatformCaps_ClockStretcher); 1535 PP_ASSERT_WITH_CODE(false, 1536 "Stretch Amount in PPTable not supported\n", 1537 return -EINVAL); 1538 } 1539 1540 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); 1541 value &= 0xFFFFFFFE; 1542 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); 1543 1544 return 0; 1545 } 1546 1547 static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr) 1548 { 1549 uint32_t efuse; 1550 1551 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1552 ixSMU_EFUSE_0 + (49 * 4)); 1553 efuse &= 0x00000001; 1554 1555 if (efuse) 1556 return true; 1557 1558 return false; 1559 } 1560 1561 static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 1562 { 1563 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1564 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1565 1566 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1567 int result = 0; 1568 struct pp_atom_ctrl__avfs_parameters avfs_params = {0}; 1569 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} }; 1570 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} }; 1571 uint32_t tmp, i; 1572 1573 struct phm_ppt_v1_information *table_info = 1574 (struct phm_ppt_v1_information *)hwmgr->pptable; 1575 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1576 table_info->vdd_dep_on_sclk; 1577 1578 if (!hwmgr->avfs_supported) 1579 return 0; 1580 1581 result = atomctrl_get_avfs_information(hwmgr, &avfs_params); 1582 1583 if (0 == result) { 1584 table->BTCGB_VDROOP_TABLE[0].a0 = 1585 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0); 1586 table->BTCGB_VDROOP_TABLE[0].a1 = 1587 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1); 1588 table->BTCGB_VDROOP_TABLE[0].a2 = 1589 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2); 1590 table->BTCGB_VDROOP_TABLE[1].a0 = 1591 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0); 1592 table->BTCGB_VDROOP_TABLE[1].a1 = 1593 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1); 1594 table->BTCGB_VDROOP_TABLE[1].a2 = 1595 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2); 1596 table->AVFSGB_FUSE_TABLE[0].m1 = 1597 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1); 1598 table->AVFSGB_FUSE_TABLE[0].m2 = 1599 PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2); 1600 table->AVFSGB_FUSE_TABLE[0].b = 1601 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b); 1602 table->AVFSGB_FUSE_TABLE[0].m1_shift = 24; 1603 table->AVFSGB_FUSE_TABLE[0].m2_shift = 12; 1604 table->AVFSGB_FUSE_TABLE[1].m1 = 1605 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1); 1606 table->AVFSGB_FUSE_TABLE[1].m2 = 1607 PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2); 1608 table->AVFSGB_FUSE_TABLE[1].b = 1609 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b); 1610 table->AVFSGB_FUSE_TABLE[1].m1_shift = 24; 1611 table->AVFSGB_FUSE_TABLE[1].m2_shift = 12; 1612 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv); 1613 AVFS_meanNsigma.Aconstant[0] = 1614 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0); 1615 AVFS_meanNsigma.Aconstant[1] = 1616 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1); 1617 AVFS_meanNsigma.Aconstant[2] = 1618 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2); 1619 AVFS_meanNsigma.DC_tol_sigma = 1620 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma); 1621 AVFS_meanNsigma.Platform_mean = 1622 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean); 1623 AVFS_meanNsigma.PSM_Age_CompFactor = 1624 PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor); 1625 AVFS_meanNsigma.Platform_sigma = 1626 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma); 1627 1628 for (i = 0; i < sclk_table->count; i++) { 1629 AVFS_meanNsigma.Static_Voltage_Offset[i] = 1630 (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625); 1631 AVFS_SclkOffset.Sclk_Offset[i] = 1632 PP_HOST_TO_SMC_US((uint16_t) 1633 (sclk_table->entries[i].sclk_offset) / 100); 1634 } 1635 1636 result = smu7_read_smc_sram_dword(hwmgr, 1637 SMU7_FIRMWARE_HEADER_LOCATION + 1638 offsetof(SMU75_Firmware_Header, AvfsMeanNSigma), 1639 &tmp, SMC_RAM_END); 1640 smu7_copy_bytes_to_smc(hwmgr, 1641 tmp, 1642 (uint8_t *)&AVFS_meanNsigma, 1643 sizeof(AVFS_meanNsigma_t), 1644 SMC_RAM_END); 1645 1646 result = smu7_read_smc_sram_dword(hwmgr, 1647 SMU7_FIRMWARE_HEADER_LOCATION + 1648 offsetof(SMU75_Firmware_Header, AvfsSclkOffsetTable), 1649 &tmp, SMC_RAM_END); 1650 smu7_copy_bytes_to_smc(hwmgr, 1651 tmp, 1652 (uint8_t *)&AVFS_SclkOffset, 1653 sizeof(AVFS_Sclk_Offset_t), 1654 SMC_RAM_END); 1655 1656 data->avfs_vdroop_override_setting = 1657 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) | 1658 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) | 1659 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) | 1660 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT); 1661 data->apply_avfs_cks_off_voltage = 1662 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1; 1663 } 1664 return result; 1665 } 1666 1667 static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr, 1668 struct SMU75_Discrete_DpmTable *table) 1669 { 1670 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1671 struct vegam_smumgr *smu_data = 1672 (struct vegam_smumgr *)(hwmgr->smu_backend); 1673 uint16_t config; 1674 1675 config = VR_MERGED_WITH_VDDC; 1676 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT); 1677 1678 /* Set Vddc Voltage Controller */ 1679 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 1680 config = VR_SVI2_PLANE_1; 1681 table->VRConfig |= config; 1682 } else { 1683 PP_ASSERT_WITH_CODE(false, 1684 "VDDC should be on SVI2 control in merged mode!", 1685 ); 1686 } 1687 /* Set Vddci Voltage Controller */ 1688 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { 1689 config = VR_SVI2_PLANE_2; /* only in merged mode */ 1690 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); 1691 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 1692 config = VR_SMIO_PATTERN_1; 1693 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); 1694 } else { 1695 config = VR_STATIC_VOLTAGE; 1696 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); 1697 } 1698 /* Set Mvdd Voltage Controller */ 1699 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { 1700 if (config != VR_SVI2_PLANE_2) { 1701 config = VR_SVI2_PLANE_2; 1702 table->VRConfig |= (config << VRCONF_MVDD_SHIFT); 1703 cgs_write_ind_register(hwmgr->device, 1704 CGS_IND_REG__SMC, 1705 smu_data->smu7_data.soft_regs_start + 1706 offsetof(SMU75_SoftRegisters, AllowMvddSwitch), 1707 0x1); 1708 } else { 1709 PP_ASSERT_WITH_CODE(false, 1710 "SVI2 Plane 2 is already taken, set MVDD as Static",); 1711 config = VR_STATIC_VOLTAGE; 1712 table->VRConfig = (config << VRCONF_MVDD_SHIFT); 1713 } 1714 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 1715 config = VR_SMIO_PATTERN_2; 1716 table->VRConfig = (config << VRCONF_MVDD_SHIFT); 1717 cgs_write_ind_register(hwmgr->device, 1718 CGS_IND_REG__SMC, 1719 smu_data->smu7_data.soft_regs_start + 1720 offsetof(SMU75_SoftRegisters, AllowMvddSwitch), 1721 0x1); 1722 } else { 1723 config = VR_STATIC_VOLTAGE; 1724 table->VRConfig |= (config << VRCONF_MVDD_SHIFT); 1725 } 1726 1727 return 0; 1728 } 1729 1730 static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr) 1731 { 1732 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1733 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults; 1734 1735 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; 1736 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC; 1737 smu_data->power_tune_table.SviLoadLineTrimVddC = 3; 1738 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; 1739 1740 return 0; 1741 } 1742 1743 static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr) 1744 { 1745 uint16_t tdc_limit; 1746 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1747 struct phm_ppt_v1_information *table_info = 1748 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1749 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults; 1750 1751 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128); 1752 smu_data->power_tune_table.TDC_VDDC_PkgLimit = 1753 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit); 1754 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 1755 defaults->TDC_VDDC_ThrottleReleaseLimitPerc; 1756 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt; 1757 1758 return 0; 1759 } 1760 1761 static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 1762 { 1763 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1764 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults; 1765 uint32_t temp; 1766 1767 if (smu7_read_smc_sram_dword(hwmgr, 1768 fuse_table_offset + 1769 offsetof(SMU75_Discrete_PmFuses, TdcWaterfallCtl), 1770 (uint32_t *)&temp, SMC_RAM_END)) 1771 PP_ASSERT_WITH_CODE(false, 1772 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!", 1773 return -EINVAL); 1774 else { 1775 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl; 1776 smu_data->power_tune_table.LPMLTemperatureMin = 1777 (uint8_t)((temp >> 16) & 0xff); 1778 smu_data->power_tune_table.LPMLTemperatureMax = 1779 (uint8_t)((temp >> 8) & 0xff); 1780 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff); 1781 } 1782 return 0; 1783 } 1784 1785 static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr) 1786 { 1787 int i; 1788 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1789 1790 /* Currently not used. Set all to zero. */ 1791 for (i = 0; i < 16; i++) 1792 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0; 1793 1794 return 0; 1795 } 1796 1797 static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) 1798 { 1799 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1800 1801 /* TO DO move to hwmgr */ 1802 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) 1803 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) 1804 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = 1805 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity; 1806 1807 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US( 1808 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity); 1809 return 0; 1810 } 1811 1812 static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr) 1813 { 1814 int i; 1815 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1816 1817 /* Currently not used. Set all to zero. */ 1818 for (i = 0; i < 16; i++) 1819 smu_data->power_tune_table.GnbLPML[i] = 0; 1820 1821 return 0; 1822 } 1823 1824 static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) 1825 { 1826 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1827 struct phm_ppt_v1_information *table_info = 1828 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1829 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; 1830 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; 1831 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; 1832 1833 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256); 1834 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256); 1835 1836 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd = 1837 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd); 1838 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd = 1839 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd); 1840 1841 return 0; 1842 } 1843 1844 static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr) 1845 { 1846 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1847 uint32_t pm_fuse_table_offset; 1848 1849 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1850 PHM_PlatformCaps_PowerContainment)) { 1851 if (smu7_read_smc_sram_dword(hwmgr, 1852 SMU7_FIRMWARE_HEADER_LOCATION + 1853 offsetof(SMU75_Firmware_Header, PmFuseTable), 1854 &pm_fuse_table_offset, SMC_RAM_END)) 1855 PP_ASSERT_WITH_CODE(false, 1856 "Attempt to get pm_fuse_table_offset Failed!", 1857 return -EINVAL); 1858 1859 if (vegam_populate_svi_load_line(hwmgr)) 1860 PP_ASSERT_WITH_CODE(false, 1861 "Attempt to populate SviLoadLine Failed!", 1862 return -EINVAL); 1863 1864 if (vegam_populate_tdc_limit(hwmgr)) 1865 PP_ASSERT_WITH_CODE(false, 1866 "Attempt to populate TDCLimit Failed!", return -EINVAL); 1867 1868 if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset)) 1869 PP_ASSERT_WITH_CODE(false, 1870 "Attempt to populate TdcWaterfallCtl, " 1871 "LPMLTemperature Min and Max Failed!", 1872 return -EINVAL); 1873 1874 if (0 != vegam_populate_temperature_scaler(hwmgr)) 1875 PP_ASSERT_WITH_CODE(false, 1876 "Attempt to populate LPMLTemperatureScaler Failed!", 1877 return -EINVAL); 1878 1879 if (vegam_populate_fuzzy_fan(hwmgr)) 1880 PP_ASSERT_WITH_CODE(false, 1881 "Attempt to populate Fuzzy Fan Control parameters Failed!", 1882 return -EINVAL); 1883 1884 if (vegam_populate_gnb_lpml(hwmgr)) 1885 PP_ASSERT_WITH_CODE(false, 1886 "Attempt to populate GnbLPML Failed!", 1887 return -EINVAL); 1888 1889 if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr)) 1890 PP_ASSERT_WITH_CODE(false, 1891 "Attempt to populate BapmVddCBaseLeakage Hi and Lo " 1892 "Sidd Failed!", return -EINVAL); 1893 1894 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, 1895 (uint8_t *)&smu_data->power_tune_table, 1896 (sizeof(struct SMU75_Discrete_PmFuses) - PMFUSES_AVFSSIZE), 1897 SMC_RAM_END)) 1898 PP_ASSERT_WITH_CODE(false, 1899 "Attempt to download PmFuseTable Failed!", 1900 return -EINVAL); 1901 } 1902 return 0; 1903 } 1904 1905 static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr) 1906 { 1907 struct amdgpu_device *adev = hwmgr->adev; 1908 1909 smum_send_msg_to_smc_with_parameter(hwmgr, 1910 PPSMC_MSG_EnableModeSwitchRLCNotification, 1911 adev->gfx.cu_info.number, 1912 NULL); 1913 1914 return 0; 1915 } 1916 1917 static int vegam_init_smc_table(struct pp_hwmgr *hwmgr) 1918 { 1919 int result; 1920 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1921 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); 1922 1923 struct phm_ppt_v1_information *table_info = 1924 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1925 struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1926 uint8_t i; 1927 struct pp_atomctrl_gpio_pin_assignment gpio_pin; 1928 struct phm_ppt_v1_gpio_table *gpio_table = 1929 (struct phm_ppt_v1_gpio_table *)table_info->gpio_table; 1930 pp_atomctrl_clock_dividers_vi dividers; 1931 1932 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1933 PHM_PlatformCaps_AutomaticDCTransition); 1934 1935 vegam_initialize_power_tune_defaults(hwmgr); 1936 1937 if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control) 1938 vegam_populate_smc_voltage_tables(hwmgr, table); 1939 1940 table->SystemFlags = 0; 1941 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1942 PHM_PlatformCaps_AutomaticDCTransition)) 1943 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 1944 1945 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1946 PHM_PlatformCaps_StepVddc)) 1947 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 1948 1949 if (hw_data->is_memory_gddr5) 1950 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 1951 1952 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) { 1953 result = vegam_populate_ulv_state(hwmgr, table); 1954 PP_ASSERT_WITH_CODE(!result, 1955 "Failed to initialize ULV state!", return result); 1956 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1957 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT); 1958 } 1959 1960 result = vegam_populate_smc_link_level(hwmgr, table); 1961 PP_ASSERT_WITH_CODE(!result, 1962 "Failed to initialize Link Level!", return result); 1963 1964 result = vegam_populate_all_graphic_levels(hwmgr); 1965 PP_ASSERT_WITH_CODE(!result, 1966 "Failed to initialize Graphics Level!", return result); 1967 1968 result = vegam_populate_all_memory_levels(hwmgr); 1969 PP_ASSERT_WITH_CODE(!result, 1970 "Failed to initialize Memory Level!", return result); 1971 1972 result = vegam_populate_smc_acpi_level(hwmgr, table); 1973 PP_ASSERT_WITH_CODE(!result, 1974 "Failed to initialize ACPI Level!", return result); 1975 1976 result = vegam_populate_smc_vce_level(hwmgr, table); 1977 PP_ASSERT_WITH_CODE(!result, 1978 "Failed to initialize VCE Level!", return result); 1979 1980 /* Since only the initial state is completely set up at this point 1981 * (the other states are just copies of the boot state) we only 1982 * need to populate the ARB settings for the initial state. 1983 */ 1984 result = vegam_program_memory_timing_parameters(hwmgr); 1985 PP_ASSERT_WITH_CODE(!result, 1986 "Failed to Write ARB settings for the initial state.", return result); 1987 1988 result = vegam_populate_smc_uvd_level(hwmgr, table); 1989 PP_ASSERT_WITH_CODE(!result, 1990 "Failed to initialize UVD Level!", return result); 1991 1992 result = vegam_populate_smc_boot_level(hwmgr, table); 1993 PP_ASSERT_WITH_CODE(!result, 1994 "Failed to initialize Boot Level!", return result); 1995 1996 result = vegam_populate_smc_initial_state(hwmgr); 1997 PP_ASSERT_WITH_CODE(!result, 1998 "Failed to initialize Boot State!", return result); 1999 2000 result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr); 2001 PP_ASSERT_WITH_CODE(!result, 2002 "Failed to populate BAPM Parameters!", return result); 2003 2004 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2005 PHM_PlatformCaps_ClockStretcher)) { 2006 result = vegam_populate_clock_stretcher_data_table(hwmgr); 2007 PP_ASSERT_WITH_CODE(!result, 2008 "Failed to populate Clock Stretcher Data Table!", 2009 return result); 2010 } 2011 2012 result = vegam_populate_avfs_parameters(hwmgr); 2013 PP_ASSERT_WITH_CODE(!result, 2014 "Failed to populate AVFS Parameters!", return result;); 2015 2016 table->CurrSclkPllRange = 0xff; 2017 table->GraphicsVoltageChangeEnable = 1; 2018 table->GraphicsThermThrottleEnable = 1; 2019 table->GraphicsInterval = 1; 2020 table->VoltageInterval = 1; 2021 table->ThermalInterval = 1; 2022 table->TemperatureLimitHigh = 2023 table_info->cac_dtp_table->usTargetOperatingTemp * 2024 SMU7_Q88_FORMAT_CONVERSION_UNIT; 2025 table->TemperatureLimitLow = 2026 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) * 2027 SMU7_Q88_FORMAT_CONVERSION_UNIT; 2028 table->MemoryVoltageChangeEnable = 1; 2029 table->MemoryInterval = 1; 2030 table->VoltageResponseTime = 0; 2031 table->PhaseResponseTime = 0; 2032 table->MemoryThermThrottleEnable = 1; 2033 2034 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1, 2035 "There must be 1 or more PCIE levels defined in PPTable.", 2036 return -EINVAL); 2037 table->PCIeBootLinkLevel = 2038 hw_data->dpm_table.pcie_speed_table.count; 2039 table->PCIeGenInterval = 1; 2040 table->VRConfig = 0; 2041 2042 result = vegam_populate_vr_config(hwmgr, table); 2043 PP_ASSERT_WITH_CODE(!result, 2044 "Failed to populate VRConfig setting!", return result); 2045 2046 table->ThermGpio = 17; 2047 table->SclkStepSize = 0x4000; 2048 2049 if (atomctrl_get_pp_assign_pin(hwmgr, 2050 VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { 2051 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; 2052 if (gpio_table) 2053 table->VRHotLevel = 2054 table_info->gpio_table->vrhot_triggered_sclk_dpm_index; 2055 } else { 2056 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN; 2057 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2058 PHM_PlatformCaps_RegulatorHot); 2059 } 2060 2061 if (atomctrl_get_pp_assign_pin(hwmgr, 2062 PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin)) { 2063 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift; 2064 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2065 PHM_PlatformCaps_AutomaticDCTransition) && 2066 !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL)) 2067 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2068 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 2069 } else { 2070 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN; 2071 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2072 PHM_PlatformCaps_AutomaticDCTransition); 2073 } 2074 2075 /* Thermal Output GPIO */ 2076 if (atomctrl_get_pp_assign_pin(hwmgr, 2077 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin)) { 2078 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift; 2079 2080 /* For porlarity read GPIOPAD_A with assigned Gpio pin 2081 * since VBIOS will program this register to set 'inactive state', 2082 * driver can then determine 'active state' from this and 2083 * program SMU with correct polarity 2084 */ 2085 table->ThermOutPolarity = 2086 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & 2087 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; 2088 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; 2089 2090 /* if required, combine VRHot/PCC with thermal out GPIO */ 2091 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2092 PHM_PlatformCaps_RegulatorHot) && 2093 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2094 PHM_PlatformCaps_CombinePCCWithThermalSignal)) 2095 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; 2096 } else { 2097 table->ThermOutGpio = 17; 2098 table->ThermOutPolarity = 1; 2099 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; 2100 } 2101 2102 /* Populate BIF_SCLK levels into SMC DPM table */ 2103 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { 2104 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 2105 smu_data->bif_sclk_table[i], ÷rs); 2106 PP_ASSERT_WITH_CODE(!result, 2107 "Can not find DFS divide id for Sclk", 2108 return result); 2109 2110 if (i == 0) 2111 table->Ulv.BifSclkDfs = 2112 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider)); 2113 else 2114 table->LinkLevel[i - 1].BifSclkDfs = 2115 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider)); 2116 } 2117 2118 for (i = 0; i < SMU75_MAX_ENTRIES_SMIO; i++) 2119 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); 2120 2121 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); 2122 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); 2123 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); 2124 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); 2125 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); 2126 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange); 2127 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); 2128 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); 2129 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); 2130 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); 2131 2132 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ 2133 result = smu7_copy_bytes_to_smc(hwmgr, 2134 smu_data->smu7_data.dpm_table_start + 2135 offsetof(SMU75_Discrete_DpmTable, SystemFlags), 2136 (uint8_t *)&(table->SystemFlags), 2137 sizeof(SMU75_Discrete_DpmTable) - 3 * sizeof(SMU75_PIDController), 2138 SMC_RAM_END); 2139 PP_ASSERT_WITH_CODE(!result, 2140 "Failed to upload dpm data to SMC memory!", return result); 2141 2142 result = vegam_populate_pm_fuses(hwmgr); 2143 PP_ASSERT_WITH_CODE(!result, 2144 "Failed to populate PM fuses to SMC memory!", return result); 2145 2146 result = vegam_enable_reconfig_cus(hwmgr); 2147 PP_ASSERT_WITH_CODE(!result, 2148 "Failed to enable reconfigurable CUs!", return result); 2149 2150 return 0; 2151 } 2152 2153 static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member) 2154 { 2155 switch (type) { 2156 case SMU_SoftRegisters: 2157 switch (member) { 2158 case HandshakeDisables: 2159 return offsetof(SMU75_SoftRegisters, HandshakeDisables); 2160 case VoltageChangeTimeout: 2161 return offsetof(SMU75_SoftRegisters, VoltageChangeTimeout); 2162 case AverageGraphicsActivity: 2163 return offsetof(SMU75_SoftRegisters, AverageGraphicsActivity); 2164 case AverageMemoryActivity: 2165 return offsetof(SMU75_SoftRegisters, AverageMemoryActivity); 2166 case PreVBlankGap: 2167 return offsetof(SMU75_SoftRegisters, PreVBlankGap); 2168 case VBlankTimeout: 2169 return offsetof(SMU75_SoftRegisters, VBlankTimeout); 2170 case UcodeLoadStatus: 2171 return offsetof(SMU75_SoftRegisters, UcodeLoadStatus); 2172 case DRAM_LOG_ADDR_H: 2173 return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_H); 2174 case DRAM_LOG_ADDR_L: 2175 return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_L); 2176 case DRAM_LOG_PHY_ADDR_H: 2177 return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_H); 2178 case DRAM_LOG_PHY_ADDR_L: 2179 return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_L); 2180 case DRAM_LOG_BUFF_SIZE: 2181 return offsetof(SMU75_SoftRegisters, DRAM_LOG_BUFF_SIZE); 2182 } 2183 break; 2184 case SMU_Discrete_DpmTable: 2185 switch (member) { 2186 case UvdBootLevel: 2187 return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel); 2188 case VceBootLevel: 2189 return offsetof(SMU75_Discrete_DpmTable, VceBootLevel); 2190 case LowSclkInterruptThreshold: 2191 return offsetof(SMU75_Discrete_DpmTable, LowSclkInterruptThreshold); 2192 } 2193 break; 2194 } 2195 pr_warn("can't get the offset of type %x member %x\n", type, member); 2196 return 0; 2197 } 2198 2199 static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) 2200 { 2201 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2202 2203 if (data->need_update_smu7_dpm_table & 2204 (DPMTABLE_OD_UPDATE_SCLK + 2205 DPMTABLE_UPDATE_SCLK + 2206 DPMTABLE_UPDATE_MCLK)) 2207 return vegam_program_memory_timing_parameters(hwmgr); 2208 2209 return 0; 2210 } 2211 2212 static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr) 2213 { 2214 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2215 struct vegam_smumgr *smu_data = 2216 (struct vegam_smumgr *)(hwmgr->smu_backend); 2217 int result = 0; 2218 uint32_t low_sclk_interrupt_threshold = 0; 2219 2220 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2221 PHM_PlatformCaps_SclkThrottleLowNotification) 2222 && (data->low_sclk_interrupt_threshold != 0)) { 2223 low_sclk_interrupt_threshold = 2224 data->low_sclk_interrupt_threshold; 2225 2226 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); 2227 2228 result = smu7_copy_bytes_to_smc( 2229 hwmgr, 2230 smu_data->smu7_data.dpm_table_start + 2231 offsetof(SMU75_Discrete_DpmTable, 2232 LowSclkInterruptThreshold), 2233 (uint8_t *)&low_sclk_interrupt_threshold, 2234 sizeof(uint32_t), 2235 SMC_RAM_END); 2236 } 2237 PP_ASSERT_WITH_CODE((result == 0), 2238 "Failed to update SCLK threshold!", return result); 2239 2240 result = vegam_program_mem_timing_parameters(hwmgr); 2241 PP_ASSERT_WITH_CODE((result == 0), 2242 "Failed to program memory timing parameters!", 2243 ); 2244 2245 return result; 2246 } 2247 2248 static int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr) 2249 { 2250 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2251 int ret; 2252 2253 if (!hwmgr->avfs_supported) 2254 return 0; 2255 2256 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL); 2257 if (!ret) { 2258 if (data->apply_avfs_cks_off_voltage) 2259 ret = smum_send_msg_to_smc(hwmgr, 2260 PPSMC_MSG_ApplyAvfsCksOffVoltage, 2261 NULL); 2262 } 2263 2264 return ret; 2265 } 2266 2267 static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 2268 { 2269 PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan, 2270 "VBIOS fan info is not correct!", 2271 ); 2272 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2273 PHM_PlatformCaps_MicrocodeFanControl); 2274 return 0; 2275 } 2276 2277 const struct pp_smumgr_func vegam_smu_funcs = { 2278 .name = "vegam_smu", 2279 .smu_init = vegam_smu_init, 2280 .smu_fini = smu7_smu_fini, 2281 .start_smu = vegam_start_smu, 2282 .check_fw_load_finish = smu7_check_fw_load_finish, 2283 .request_smu_load_fw = smu7_reload_firmware, 2284 .request_smu_load_specific_fw = NULL, 2285 .send_msg_to_smc = smu7_send_msg_to_smc, 2286 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter, 2287 .get_argument = smu7_get_argument, 2288 .process_firmware_header = vegam_process_firmware_header, 2289 .is_dpm_running = vegam_is_dpm_running, 2290 .get_mac_definition = vegam_get_mac_definition, 2291 .update_smc_table = vegam_update_smc_table, 2292 .init_smc_table = vegam_init_smc_table, 2293 .get_offsetof = vegam_get_offsetof, 2294 .populate_all_graphic_levels = vegam_populate_all_graphic_levels, 2295 .populate_all_memory_levels = vegam_populate_all_memory_levels, 2296 .update_sclk_threshold = vegam_update_sclk_threshold, 2297 .is_hw_avfs_present = vegam_is_hw_avfs_present, 2298 .thermal_avfs_enable = vegam_thermal_avfs_enable, 2299 .thermal_setup_fan_table = vegam_thermal_setup_fan_table, 2300 }; 2301