1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2015 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan 24e098bc96SEvan Quan #ifndef _POLARIS10_SMUMANAGER_H 25e098bc96SEvan Quan #define _POLARIS10_SMUMANAGER_H 26e098bc96SEvan Quan 27e098bc96SEvan Quan 28e098bc96SEvan Quan #include <pp_endian.h> 29e098bc96SEvan Quan #include "smu74.h" 30e098bc96SEvan Quan #include "smu74_discrete.h" 31e098bc96SEvan Quan #include "smu7_smumgr.h" 32e098bc96SEvan Quan 33e098bc96SEvan Quan #define SMC_RAM_END 0x40000 34e098bc96SEvan Quan 35e098bc96SEvan Quan struct polaris10_pt_defaults { 36e098bc96SEvan Quan uint8_t SviLoadLineEn; 37e098bc96SEvan Quan uint8_t SviLoadLineVddC; 38e098bc96SEvan Quan uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 39e098bc96SEvan Quan uint8_t TDC_MAWt; 40e098bc96SEvan Quan uint8_t TdcWaterfallCtl; 41e098bc96SEvan Quan uint8_t DTEAmbientTempBase; 42e098bc96SEvan Quan 43e098bc96SEvan Quan uint32_t DisplayCac; 44e098bc96SEvan Quan uint32_t BAPM_TEMP_GRADIENT; 45e098bc96SEvan Quan uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; 46e098bc96SEvan Quan uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; 47e098bc96SEvan Quan }; 48e098bc96SEvan Quan 49e098bc96SEvan Quan struct polaris10_range_table { 50e098bc96SEvan Quan uint32_t trans_lower_frequency; /* in 10khz */ 51e098bc96SEvan Quan uint32_t trans_upper_frequency; 52e098bc96SEvan Quan }; 53e098bc96SEvan Quan 54e098bc96SEvan Quan struct polaris10_smumgr { 55e098bc96SEvan Quan struct smu7_smumgr smu7_data; 56e098bc96SEvan Quan uint8_t protected_mode; 57e098bc96SEvan Quan SMU74_Discrete_DpmTable smc_state_table; 58e098bc96SEvan Quan struct SMU74_Discrete_Ulv ulv_setting; 59e098bc96SEvan Quan struct SMU74_Discrete_PmFuses power_tune_table; 60e098bc96SEvan Quan struct polaris10_range_table range_table[NUM_SCLK_RANGE]; 61e098bc96SEvan Quan const struct polaris10_pt_defaults *power_tune_defaults; 62e098bc96SEvan Quan uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK]; 63*5f92b48cSEvan Quan pp_atomctrl_mc_reg_table mc_reg_table; 64e098bc96SEvan Quan }; 65e098bc96SEvan Quan 66e098bc96SEvan Quan 67e098bc96SEvan Quan #endif 68