1*e098bc96SEvan Quan /* 2*e098bc96SEvan Quan * Copyright 2016 Advanced Micro Devices, Inc. 3*e098bc96SEvan Quan * 4*e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6*e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7*e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10*e098bc96SEvan Quan * 11*e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12*e098bc96SEvan Quan * all copies or substantial portions of the Software. 13*e098bc96SEvan Quan * 14*e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*e098bc96SEvan Quan * 22*e098bc96SEvan Quan * Author: Huang Rui <ray.huang@amd.com> 23*e098bc96SEvan Quan * 24*e098bc96SEvan Quan */ 25*e098bc96SEvan Quan 26*e098bc96SEvan Quan #ifndef _ICELAND_SMUMGR_H_ 27*e098bc96SEvan Quan #define _ICELAND_SMUMGR_H_ 28*e098bc96SEvan Quan 29*e098bc96SEvan Quan 30*e098bc96SEvan Quan #include "smu7_smumgr.h" 31*e098bc96SEvan Quan #include "pp_endian.h" 32*e098bc96SEvan Quan #include "smu71_discrete.h" 33*e098bc96SEvan Quan 34*e098bc96SEvan Quan struct iceland_pt_defaults { 35*e098bc96SEvan Quan uint8_t svi_load_line_en; 36*e098bc96SEvan Quan uint8_t svi_load_line_vddc; 37*e098bc96SEvan Quan uint8_t tdc_vddc_throttle_release_limit_perc; 38*e098bc96SEvan Quan uint8_t tdc_mawt; 39*e098bc96SEvan Quan uint8_t tdc_waterfall_ctl; 40*e098bc96SEvan Quan uint8_t dte_ambient_temp_base; 41*e098bc96SEvan Quan uint32_t display_cac; 42*e098bc96SEvan Quan uint32_t bapm_temp_gradient; 43*e098bc96SEvan Quan uint16_t bapmti_r[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS]; 44*e098bc96SEvan Quan uint16_t bapmti_rc[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS]; 45*e098bc96SEvan Quan }; 46*e098bc96SEvan Quan 47*e098bc96SEvan Quan struct iceland_mc_reg_entry { 48*e098bc96SEvan Quan uint32_t mclk_max; 49*e098bc96SEvan Quan uint32_t mc_data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 50*e098bc96SEvan Quan }; 51*e098bc96SEvan Quan 52*e098bc96SEvan Quan struct iceland_mc_reg_table { 53*e098bc96SEvan Quan uint8_t last; /* number of registers*/ 54*e098bc96SEvan Quan uint8_t num_entries; /* number of entries in mc_reg_table_entry used*/ 55*e098bc96SEvan Quan uint16_t validflag; /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/ 56*e098bc96SEvan Quan struct iceland_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 57*e098bc96SEvan Quan SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 58*e098bc96SEvan Quan }; 59*e098bc96SEvan Quan 60*e098bc96SEvan Quan struct iceland_smumgr { 61*e098bc96SEvan Quan struct smu7_smumgr smu7_data; 62*e098bc96SEvan Quan struct SMU71_Discrete_DpmTable smc_state_table; 63*e098bc96SEvan Quan struct SMU71_Discrete_PmFuses power_tune_table; 64*e098bc96SEvan Quan struct SMU71_Discrete_Ulv ulv_setting; 65*e098bc96SEvan Quan const struct iceland_pt_defaults *power_tune_defaults; 66*e098bc96SEvan Quan SMU71_Discrete_MCRegisters mc_regs; 67*e098bc96SEvan Quan struct iceland_mc_reg_table mc_reg_table; 68*e098bc96SEvan Quan }; 69*e098bc96SEvan Quan 70*e098bc96SEvan Quan #endif 71