1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _SMU73_H_ 24 #define _SMU73_H_ 25 26 #pragma pack(push, 1) 27 enum SID_OPTION { 28 SID_OPTION_HI, 29 SID_OPTION_LO, 30 SID_OPTION_COUNT 31 }; 32 33 enum Poly3rdOrderCoeff { 34 LEAKAGE_TEMPERATURE_SCALAR, 35 LEAKAGE_VOLTAGE_SCALAR, 36 DYNAMIC_VOLTAGE_SCALAR, 37 POLY_3RD_ORDER_COUNT 38 }; 39 40 struct SMU7_Poly3rdOrder_Data { 41 int32_t a; 42 int32_t b; 43 int32_t c; 44 int32_t d; 45 uint8_t a_shift; 46 uint8_t b_shift; 47 uint8_t c_shift; 48 uint8_t x_shift; 49 }; 50 51 typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; 52 53 struct Power_Calculator_Data { 54 uint16_t NoLoadVoltage; 55 uint16_t LoadVoltage; 56 uint16_t Resistance; 57 uint16_t Temperature; 58 uint16_t BaseLeakage; 59 uint16_t LkgTempScalar; 60 uint16_t LkgVoltScalar; 61 uint16_t LkgAreaScalar; 62 uint16_t LkgPower; 63 uint16_t DynVoltScalar; 64 uint32_t Cac; 65 uint32_t DynPower; 66 uint32_t TotalCurrent; 67 uint32_t TotalPower; 68 }; 69 70 typedef struct Power_Calculator_Data PowerCalculatorData_t; 71 72 struct Gc_Cac_Weight_Data { 73 uint8_t index; 74 uint32_t value; 75 }; 76 77 typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; 78 79 80 typedef struct { 81 uint32_t high; 82 uint32_t low; 83 } data_64_t; 84 85 typedef struct { 86 data_64_t high; 87 data_64_t low; 88 } data_128_t; 89 90 #define SMU__NUM_SCLK_DPM_STATE 8 91 #define SMU__NUM_MCLK_DPM_LEVELS 4 92 #define SMU__NUM_LCLK_DPM_LEVELS 8 93 #define SMU__NUM_PCIE_DPM_LEVELS 8 94 95 #define SMU7_CONTEXT_ID_SMC 1 96 #define SMU7_CONTEXT_ID_VBIOS 2 97 98 #define SMU73_MAX_LEVELS_VDDC 16 99 #define SMU73_MAX_LEVELS_VDDGFX 16 100 #define SMU73_MAX_LEVELS_VDDCI 8 101 #define SMU73_MAX_LEVELS_MVDD 4 102 103 #define SMU_MAX_SMIO_LEVELS 4 104 105 #define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV 106 #define SMU73_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM 107 #define SMU73_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels 108 #define SMU73_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. 109 #define SMU73_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. 110 #define SMU73_MAX_LEVELS_VCE 8 // ECLK levels for VCE. 111 #define SMU73_MAX_LEVELS_ACP 8 // ACLK levels for ACP. 112 #define SMU73_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. 113 #define SMU73_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. 114 115 #define DPM_NO_LIMIT 0 116 #define DPM_NO_UP 1 117 #define DPM_GO_DOWN 2 118 #define DPM_GO_UP 3 119 120 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 121 #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 122 123 #define GPIO_CLAMP_MODE_VRHOT 1 124 #define GPIO_CLAMP_MODE_THERM 2 125 #define GPIO_CLAMP_MODE_DC 4 126 127 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 128 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 129 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 130 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 131 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 132 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 133 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 134 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 135 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 136 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 137 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 138 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 139 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 140 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 141 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 142 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 143 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 144 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 145 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 146 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 147 148 // Virtualization Defines 149 #define CG_XDMA_MASK 0x1 150 #define CG_XDMA_SHIFT 0 151 #define CG_UVD_MASK 0x2 152 #define CG_UVD_SHIFT 1 153 #define CG_VCE_MASK 0x4 154 #define CG_VCE_SHIFT 2 155 #define CG_SAMU_MASK 0x8 156 #define CG_SAMU_SHIFT 3 157 #define CG_GFX_MASK 0x10 158 #define CG_GFX_SHIFT 4 159 #define CG_SDMA_MASK 0x20 160 #define CG_SDMA_SHIFT 5 161 #define CG_HDP_MASK 0x40 162 #define CG_HDP_SHIFT 6 163 #define CG_MC_MASK 0x80 164 #define CG_MC_SHIFT 7 165 #define CG_DRM_MASK 0x100 166 #define CG_DRM_SHIFT 8 167 #define CG_ROM_MASK 0x200 168 #define CG_ROM_SHIFT 9 169 #define CG_BIF_MASK 0x400 170 #define CG_BIF_SHIFT 10 171 172 #define SMU73_DTE_ITERATIONS 5 173 #define SMU73_DTE_SOURCES 3 174 #define SMU73_DTE_SINKS 1 175 #define SMU73_NUM_CPU_TES 0 176 #define SMU73_NUM_GPU_TES 1 177 #define SMU73_NUM_NON_TES 2 178 #define SMU73_DTE_FAN_SCALAR_MIN 0x100 179 #define SMU73_DTE_FAN_SCALAR_MAX 0x166 180 #define SMU73_DTE_FAN_TEMP_MAX 93 181 #define SMU73_DTE_FAN_TEMP_MIN 83 182 183 #define SMU73_THERMAL_INPUT_LOOP_COUNT 6 184 #define SMU73_THERMAL_CLAMP_MODE_COUNT 8 185 186 187 struct SMU7_HystController_Data { 188 uint16_t waterfall_up; 189 uint16_t waterfall_down; 190 uint16_t waterfall_limit; 191 uint16_t release_cnt; 192 uint16_t release_limit; 193 uint16_t spare; 194 }; 195 196 typedef struct SMU7_HystController_Data SMU7_HystController_Data; 197 198 struct SMU73_PIDController { 199 uint32_t Ki; 200 int32_t LFWindupUpperLim; 201 int32_t LFWindupLowerLim; 202 uint32_t StatePrecision; 203 204 uint32_t LfPrecision; 205 uint32_t LfOffset; 206 uint32_t MaxState; 207 uint32_t MaxLfFraction; 208 uint32_t StateShift; 209 }; 210 211 typedef struct SMU73_PIDController SMU73_PIDController; 212 213 struct SMU7_LocalDpmScoreboard { 214 uint32_t PercentageBusy; 215 216 int32_t PIDError; 217 int32_t PIDIntegral; 218 int32_t PIDOutput; 219 220 uint32_t SigmaDeltaAccum; 221 uint32_t SigmaDeltaOutput; 222 uint32_t SigmaDeltaLevel; 223 224 uint32_t UtilizationSetpoint; 225 226 uint8_t TdpClampMode; 227 uint8_t TdcClampMode; 228 uint8_t ThermClampMode; 229 uint8_t VoltageBusy; 230 231 int8_t CurrLevel; 232 int8_t TargLevel; 233 uint8_t LevelChangeInProgress; 234 uint8_t UpHyst; 235 236 uint8_t DownHyst; 237 uint8_t VoltageDownHyst; 238 uint8_t DpmEnable; 239 uint8_t DpmRunning; 240 241 uint8_t DpmForce; 242 uint8_t DpmForceLevel; 243 uint8_t DisplayWatermark; 244 uint8_t McArbIndex; 245 246 uint32_t MinimumPerfSclk; 247 248 uint8_t AcpiReq; 249 uint8_t AcpiAck; 250 uint8_t GfxClkSlow; 251 uint8_t GpioClampMode; 252 253 uint8_t spare2; 254 uint8_t EnabledLevelsChange; 255 uint8_t DteClampMode; 256 uint8_t FpsClampMode; 257 258 uint16_t LevelResidencyCounters[SMU73_MAX_LEVELS_GRAPHICS]; 259 uint16_t LevelSwitchCounters[SMU73_MAX_LEVELS_GRAPHICS]; 260 261 void (*TargetStateCalculator)(uint8_t); 262 void (*SavedTargetStateCalculator)(uint8_t); 263 264 uint16_t AutoDpmInterval; 265 uint16_t AutoDpmRange; 266 267 uint8_t FpsEnabled; 268 uint8_t MaxPerfLevel; 269 uint8_t AllowLowClkInterruptToHost; 270 uint8_t FpsRunning; 271 272 uint32_t MaxAllowedFrequency; 273 274 uint32_t FilteredSclkFrequency; 275 uint32_t LastSclkFrequency; 276 uint32_t FilteredSclkFrequencyCnt; 277 278 uint8_t LedEnable; 279 uint8_t LedPin0; 280 uint8_t LedPin1; 281 uint8_t LedPin2; 282 uint32_t LedAndMask; 283 284 uint16_t FpsAlpha; 285 uint16_t DeltaTime; 286 uint32_t CurrentFps; 287 uint32_t FilteredFps; 288 uint32_t FrameCount; 289 uint32_t FrameCountLast; 290 uint16_t FpsTargetScalar; 291 uint16_t FpsWaterfallLimitScalar; 292 uint16_t FpsAlphaScalar; 293 uint16_t spare8; 294 SMU7_HystController_Data HystControllerData; 295 }; 296 297 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 298 299 #define SMU7_MAX_VOLTAGE_CLIENTS 12 300 301 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); 302 303 #define VDDC_MASK 0x00007FFF 304 #define VDDC_SHIFT 0 305 #define VDDCI_MASK 0x3FFF8000 306 #define VDDCI_SHIFT 15 307 #define PHASES_MASK 0xC0000000 308 #define PHASES_SHIFT 30 309 310 typedef uint32_t SMU_VoltageLevel; 311 312 struct SMU7_VoltageScoreboard { 313 SMU_VoltageLevel TargetVoltage; 314 uint16_t MaxVid; 315 uint8_t HighestVidOffset; 316 uint8_t CurrentVidOffset; 317 318 uint16_t CurrentVddc; 319 uint16_t CurrentVddci; 320 321 322 uint8_t ControllerBusy; 323 uint8_t CurrentVid; 324 uint8_t CurrentVddciVid; 325 uint8_t padding; 326 327 SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 328 SMU_VoltageLevel TargetVoltageState; 329 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 330 331 uint8_t padding2; 332 uint8_t padding3; 333 uint8_t ControllerEnable; 334 uint8_t ControllerRunning; 335 uint16_t CurrentStdVoltageHiSidd; 336 uint16_t CurrentStdVoltageLoSidd; 337 uint8_t OverrideVoltage; 338 uint8_t padding4; 339 uint8_t padding5; 340 uint8_t CurrentPhases; 341 342 VoltageChangeHandler_t ChangeVddc; 343 344 VoltageChangeHandler_t ChangeVddci; 345 VoltageChangeHandler_t ChangePhase; 346 VoltageChangeHandler_t ChangeMvdd; 347 348 VoltageChangeHandler_t functionLinks[6]; 349 350 uint16_t *VddcFollower1; 351 352 int16_t Driver_OD_RequestedVidOffset1; 353 int16_t Driver_OD_RequestedVidOffset2; 354 355 }; 356 357 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 358 359 // ------------------------------------------------------------------------------------------------------------------------- 360 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 361 362 struct SMU7_PCIeLinkSpeedScoreboard { 363 uint8_t DpmEnable; 364 uint8_t DpmRunning; 365 uint8_t DpmForce; 366 uint8_t DpmForceLevel; 367 368 uint8_t CurrentLinkSpeed; 369 uint8_t EnabledLevelsChange; 370 uint16_t AutoDpmInterval; 371 372 uint16_t AutoDpmRange; 373 uint16_t AutoDpmCount; 374 375 uint8_t DpmMode; 376 uint8_t AcpiReq; 377 uint8_t AcpiAck; 378 uint8_t CurrentLinkLevel; 379 380 }; 381 382 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 383 384 // -------------------------------------------------------- CAC table ------------------------------------------------------ 385 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 386 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 387 388 #define SMU7_SCALE_I 7 389 #define SMU7_SCALE_R 12 390 391 struct SMU7_PowerScoreboard { 392 uint32_t GpuPower; 393 394 uint32_t VddcPower; 395 uint32_t VddcVoltage; 396 uint32_t VddcCurrent; 397 398 uint32_t MvddPower; 399 uint32_t MvddVoltage; 400 uint32_t MvddCurrent; 401 402 uint32_t RocPower; 403 404 uint16_t Telemetry_1_slope; 405 uint16_t Telemetry_2_slope; 406 int32_t Telemetry_1_offset; 407 int32_t Telemetry_2_offset; 408 }; 409 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 410 411 // For FeatureEnables: 412 #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 413 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 414 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 415 #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 416 #define SMU7_UVD_DPM_CONFIG_MASK 0x10 417 #define SMU7_VCE_DPM_CONFIG_MASK 0x20 418 #define SMU7_ACP_DPM_CONFIG_MASK 0x40 419 #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 420 #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 421 422 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 423 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 424 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 425 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 426 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 427 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 428 429 // All 'soft registers' should be uint32_t. 430 struct SMU73_SoftRegisters { 431 uint32_t RefClockFrequency; 432 uint32_t PmTimerPeriod; 433 uint32_t FeatureEnables; 434 435 uint32_t PreVBlankGap; 436 uint32_t VBlankTimeout; 437 uint32_t TrainTimeGap; 438 439 uint32_t MvddSwitchTime; 440 uint32_t LongestAcpiTrainTime; 441 uint32_t AcpiDelay; 442 uint32_t G5TrainTime; 443 uint32_t DelayMpllPwron; 444 uint32_t VoltageChangeTimeout; 445 446 uint32_t HandshakeDisables; 447 448 uint8_t DisplayPhy1Config; 449 uint8_t DisplayPhy2Config; 450 uint8_t DisplayPhy3Config; 451 uint8_t DisplayPhy4Config; 452 453 uint8_t DisplayPhy5Config; 454 uint8_t DisplayPhy6Config; 455 uint8_t DisplayPhy7Config; 456 uint8_t DisplayPhy8Config; 457 458 uint32_t AverageGraphicsActivity; 459 uint32_t AverageMemoryActivity; 460 uint32_t AverageGioActivity; 461 462 uint8_t SClkDpmEnabledLevels; 463 uint8_t MClkDpmEnabledLevels; 464 uint8_t LClkDpmEnabledLevels; 465 uint8_t PCIeDpmEnabledLevels; 466 467 uint8_t UVDDpmEnabledLevels; 468 uint8_t SAMUDpmEnabledLevels; 469 uint8_t ACPDpmEnabledLevels; 470 uint8_t VCEDpmEnabledLevels; 471 472 uint32_t DRAM_LOG_ADDR_H; 473 uint32_t DRAM_LOG_ADDR_L; 474 uint32_t DRAM_LOG_PHY_ADDR_H; 475 uint32_t DRAM_LOG_PHY_ADDR_L; 476 uint32_t DRAM_LOG_BUFF_SIZE; 477 uint32_t UlvEnterCount; 478 uint32_t UlvTime; 479 uint32_t UcodeLoadStatus; 480 uint32_t Reserved[2]; 481 482 }; 483 484 typedef struct SMU73_SoftRegisters SMU73_SoftRegisters; 485 486 struct SMU73_Firmware_Header { 487 uint32_t Digest[5]; 488 uint32_t Version; 489 uint32_t HeaderSize; 490 uint32_t Flags; 491 uint32_t EntryPoint; 492 uint32_t CodeSize; 493 uint32_t ImageSize; 494 495 uint32_t Rtos; 496 uint32_t SoftRegisters; 497 uint32_t DpmTable; 498 uint32_t FanTable; 499 uint32_t CacConfigTable; 500 uint32_t CacStatusTable; 501 502 503 uint32_t mcRegisterTable; 504 505 506 uint32_t mcArbDramTimingTable; 507 508 509 510 511 uint32_t PmFuseTable; 512 uint32_t Globals; 513 uint32_t ClockStretcherTable; 514 uint32_t Reserved[41]; 515 uint32_t Signature; 516 }; 517 518 typedef struct SMU73_Firmware_Header SMU73_Firmware_Header; 519 520 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 521 522 enum DisplayConfig { 523 PowerDown = 1, 524 DP54x4, 525 DP54x2, 526 DP54x1, 527 DP27x4, 528 DP27x2, 529 DP27x1, 530 HDMI297, 531 HDMI162, 532 LVDS, 533 DP324x4, 534 DP324x2, 535 DP324x1 536 }; 537 538 539 #define MC_BLOCK_COUNT 1 540 #define CPL_BLOCK_COUNT 5 541 #define SE_BLOCK_COUNT 15 542 #define GC_BLOCK_COUNT 24 543 544 struct SMU7_Local_Cac { 545 uint8_t BlockId; 546 uint8_t SignalId; 547 uint8_t Threshold; 548 uint8_t Padding; 549 }; 550 551 typedef struct SMU7_Local_Cac SMU7_Local_Cac; 552 553 struct SMU7_Local_Cac_Table { 554 555 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 556 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 557 SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; 558 SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; 559 }; 560 561 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 562 563 #if !defined(SMC_MICROCODE) 564 #pragma pack(pop) 565 #endif 566 567 // Description of Clock Gating bitmask for Tonga: 568 // System Clock Gating 569 #define CG_SYS_BITMASK_FIRST_BIT 0 // First bit of Sys CG bitmask 570 #define CG_SYS_BITMASK_LAST_BIT 9 // Last bit of Sys CG bitmask 571 #define CG_SYS_BIF_MGLS_SHIFT 0 572 #define CG_SYS_ROM_SHIFT 1 573 #define CG_SYS_MC_MGCG_SHIFT 2 574 #define CG_SYS_MC_MGLS_SHIFT 3 575 #define CG_SYS_SDMA_MGCG_SHIFT 4 576 #define CG_SYS_SDMA_MGLS_SHIFT 5 577 #define CG_SYS_DRM_MGCG_SHIFT 6 578 #define CG_SYS_HDP_MGCG_SHIFT 7 579 #define CG_SYS_HDP_MGLS_SHIFT 8 580 #define CG_SYS_DRM_MGLS_SHIFT 9 581 582 #define CG_SYS_BIF_MGLS_MASK 0x1 583 #define CG_SYS_ROM_MASK 0x2 584 #define CG_SYS_MC_MGCG_MASK 0x4 585 #define CG_SYS_MC_MGLS_MASK 0x8 586 #define CG_SYS_SDMA_MGCG_MASK 0x10 587 #define CG_SYS_SDMA_MGLS_MASK 0x20 588 #define CG_SYS_DRM_MGCG_MASK 0x40 589 #define CG_SYS_HDP_MGCG_MASK 0x80 590 #define CG_SYS_HDP_MGLS_MASK 0x100 591 #define CG_SYS_DRM_MGLS_MASK 0x200 592 593 // Graphics Clock Gating 594 #define CG_GFX_BITMASK_FIRST_BIT 16 // First bit of Gfx CG bitmask 595 #define CG_GFX_BITMASK_LAST_BIT 20 // Last bit of Gfx CG bitmask 596 #define CG_GFX_CGCG_SHIFT 16 597 #define CG_GFX_CGLS_SHIFT 17 598 #define CG_CPF_MGCG_SHIFT 18 599 #define CG_RLC_MGCG_SHIFT 19 600 #define CG_GFX_OTHERS_MGCG_SHIFT 20 601 602 #define CG_GFX_CGCG_MASK 0x00010000 603 #define CG_GFX_CGLS_MASK 0x00020000 604 #define CG_CPF_MGCG_MASK 0x00040000 605 #define CG_RLC_MGCG_MASK 0x00080000 606 #define CG_GFX_OTHERS_MGCG_MASK 0x00100000 607 608 609 610 // Voltage Regulator Configuration 611 // VR Config info is contained in dpmTable.VRConfig 612 613 #define VRCONF_VDDC_MASK 0x000000FF 614 #define VRCONF_VDDC_SHIFT 0 615 #define VRCONF_VDDGFX_MASK 0x0000FF00 616 #define VRCONF_VDDGFX_SHIFT 8 617 #define VRCONF_VDDCI_MASK 0x00FF0000 618 #define VRCONF_VDDCI_SHIFT 16 619 #define VRCONF_MVDD_MASK 0xFF000000 620 #define VRCONF_MVDD_SHIFT 24 621 622 #define VR_MERGED_WITH_VDDC 0 623 #define VR_SVI2_PLANE_1 1 624 #define VR_SVI2_PLANE_2 2 625 #define VR_SMIO_PATTERN_1 3 626 #define VR_SMIO_PATTERN_2 4 627 #define VR_STATIC_VOLTAGE 5 628 629 // Clock Stretcher Configuration 630 631 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4 632 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4 633 634 // The 'settings' field is subdivided in the following way: 635 #define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 636 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 637 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E 638 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 639 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 640 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 641 642 struct SMU_ClockStretcherDataTableEntry { 643 uint8_t minVID; 644 uint8_t maxVID; 645 646 647 uint16_t setting; 648 }; 649 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; 650 651 struct SMU_ClockStretcherDataTable { 652 SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; 653 }; 654 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; 655 656 struct SMU_CKS_LOOKUPTableEntry { 657 uint16_t minFreq; 658 uint16_t maxFreq; 659 660 uint8_t setting; 661 uint8_t padding[3]; 662 }; 663 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; 664 665 struct SMU_CKS_LOOKUPTable { 666 SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; 667 }; 668 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; 669 670 struct AgmAvfsData_t { 671 uint16_t avgPsmCount[28]; 672 uint16_t minPsmCount[28]; 673 }; 674 typedef struct AgmAvfsData_t AgmAvfsData_t; 675 676 // AVFS DEFINES 677 678 enum VFT_COLUMNS { 679 SCLK0, 680 SCLK1, 681 SCLK2, 682 SCLK3, 683 SCLK4, 684 SCLK5, 685 SCLK6, 686 SCLK7, 687 688 NUM_VFT_COLUMNS 689 }; 690 691 #define TEMP_RANGE_MAXSTEPS 12 692 struct VFT_CELL_t { 693 uint16_t Voltage; 694 }; 695 696 typedef struct VFT_CELL_t VFT_CELL_t; 697 698 struct VFT_TABLE_t { 699 VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; 700 uint16_t AvfsGbv[NUM_VFT_COLUMNS]; 701 uint16_t BtcGbv[NUM_VFT_COLUMNS]; 702 uint16_t Temperature[TEMP_RANGE_MAXSTEPS]; 703 704 uint8_t NumTemperatureSteps; 705 uint8_t padding[3]; 706 }; 707 typedef struct VFT_TABLE_t VFT_TABLE_t; 708 709 #endif 710