1*e098bc96SEvan Quan /* 2*e098bc96SEvan Quan * Copyright 2016 Advanced Micro Devices, Inc. 3*e098bc96SEvan Quan * 4*e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6*e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7*e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10*e098bc96SEvan Quan * 11*e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12*e098bc96SEvan Quan * all copies or substantial portions of the Software. 13*e098bc96SEvan Quan * 14*e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*e098bc96SEvan Quan * 22*e098bc96SEvan Quan */ 23*e098bc96SEvan Quan 24*e098bc96SEvan Quan #ifndef VEGA10_PROCESSPPTABLES_H 25*e098bc96SEvan Quan #define VEGA10_PROCESSPPTABLES_H 26*e098bc96SEvan Quan 27*e098bc96SEvan Quan #include "hwmgr.h" 28*e098bc96SEvan Quan 29*e098bc96SEvan Quan enum Vega10_I2CLineID { 30*e098bc96SEvan Quan Vega10_I2CLineID_DDC1 = 0x90, 31*e098bc96SEvan Quan Vega10_I2CLineID_DDC2 = 0x91, 32*e098bc96SEvan Quan Vega10_I2CLineID_DDC3 = 0x92, 33*e098bc96SEvan Quan Vega10_I2CLineID_DDC4 = 0x93, 34*e098bc96SEvan Quan Vega10_I2CLineID_DDC5 = 0x94, 35*e098bc96SEvan Quan Vega10_I2CLineID_DDC6 = 0x95, 36*e098bc96SEvan Quan Vega10_I2CLineID_SCLSDA = 0x96, 37*e098bc96SEvan Quan Vega10_I2CLineID_DDCVGA = 0x97 38*e098bc96SEvan Quan }; 39*e098bc96SEvan Quan 40*e098bc96SEvan Quan #define Vega10_I2C_DDC1DATA 0 41*e098bc96SEvan Quan #define Vega10_I2C_DDC1CLK 1 42*e098bc96SEvan Quan #define Vega10_I2C_DDC2DATA 2 43*e098bc96SEvan Quan #define Vega10_I2C_DDC2CLK 3 44*e098bc96SEvan Quan #define Vega10_I2C_DDC3DATA 4 45*e098bc96SEvan Quan #define Vega10_I2C_DDC3CLK 5 46*e098bc96SEvan Quan #define Vega10_I2C_SDA 40 47*e098bc96SEvan Quan #define Vega10_I2C_SCL 41 48*e098bc96SEvan Quan #define Vega10_I2C_DDC4DATA 65 49*e098bc96SEvan Quan #define Vega10_I2C_DDC4CLK 66 50*e098bc96SEvan Quan #define Vega10_I2C_DDC5DATA 0x48 51*e098bc96SEvan Quan #define Vega10_I2C_DDC5CLK 0x49 52*e098bc96SEvan Quan #define Vega10_I2C_DDC6DATA 0x4a 53*e098bc96SEvan Quan #define Vega10_I2C_DDC6CLK 0x4b 54*e098bc96SEvan Quan #define Vega10_I2C_DDCVGADATA 0x4c 55*e098bc96SEvan Quan #define Vega10_I2C_DDCVGACLK 0x4d 56*e098bc96SEvan Quan 57*e098bc96SEvan Quan extern const struct pp_table_func vega10_pptable_funcs; 58*e098bc96SEvan Quan extern int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr); 59*e098bc96SEvan Quan extern int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index, 60*e098bc96SEvan Quan struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *, 61*e098bc96SEvan Quan struct pp_power_state *, void *, uint32_t)); 62*e098bc96SEvan Quan extern int vega10_baco_set_cap(struct pp_hwmgr *hwmgr); 63*e098bc96SEvan Quan #endif 64