1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/slab.h> 28 29 #include "hwmgr.h" 30 #include "amd_powerplay.h" 31 #include "hardwaremanager.h" 32 #include "ppatomfwctrl.h" 33 #include "atomfirmware.h" 34 #include "cgs_common.h" 35 #include "vega10_powertune.h" 36 #include "smu9.h" 37 #include "smu9_driver_if.h" 38 #include "vega10_inc.h" 39 #include "soc15_common.h" 40 #include "pppcielanes.h" 41 #include "vega10_hwmgr.h" 42 #include "vega10_smumgr.h" 43 #include "vega10_processpptables.h" 44 #include "vega10_pptable.h" 45 #include "vega10_thermal.h" 46 #include "pp_debug.h" 47 #include "amd_pcie_helpers.h" 48 #include "ppinterrupt.h" 49 #include "pp_overdriver.h" 50 #include "pp_thermal.h" 51 #include "vega10_baco.h" 52 53 #include "smuio/smuio_9_0_offset.h" 54 #include "smuio/smuio_9_0_sh_mask.h" 55 56 #define smnPCIE_LC_SPEED_CNTL 0x11140290 57 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 58 59 #define HBM_MEMORY_CHANNEL_WIDTH 128 60 61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; 62 63 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 64 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 65 66 //DF_CS_AON0_DramBaseAddress0 67 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 68 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 69 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 70 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 71 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 72 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 73 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 74 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 75 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 76 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 77 78 typedef enum { 79 CLK_SMNCLK = 0, 80 CLK_SOCCLK, 81 CLK_MP0CLK, 82 CLK_MP1CLK, 83 CLK_LCLK, 84 CLK_DCEFCLK, 85 CLK_VCLK, 86 CLK_DCLK, 87 CLK_ECLK, 88 CLK_UCLK, 89 CLK_GFXCLK, 90 CLK_COUNT, 91 } CLOCK_ID_e; 92 93 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic); 94 95 static struct vega10_power_state *cast_phw_vega10_power_state( 96 struct pp_hw_power_state *hw_ps) 97 { 98 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), 99 "Invalid Powerstate Type!", 100 return NULL;); 101 102 return (struct vega10_power_state *)hw_ps; 103 } 104 105 static const struct vega10_power_state *cast_const_phw_vega10_power_state( 106 const struct pp_hw_power_state *hw_ps) 107 { 108 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), 109 "Invalid Powerstate Type!", 110 return NULL;); 111 112 return (const struct vega10_power_state *)hw_ps; 113 } 114 115 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) 116 { 117 struct vega10_hwmgr *data = hwmgr->backend; 118 119 data->registry_data.sclk_dpm_key_disabled = 120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 121 data->registry_data.socclk_dpm_key_disabled = 122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; 123 data->registry_data.mclk_dpm_key_disabled = 124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 125 data->registry_data.pcie_dpm_key_disabled = 126 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; 127 128 data->registry_data.dcefclk_dpm_key_disabled = 129 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; 130 131 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { 132 data->registry_data.power_containment_support = 1; 133 data->registry_data.enable_pkg_pwr_tracking_feature = 1; 134 data->registry_data.enable_tdc_limit_feature = 1; 135 } 136 137 data->registry_data.clock_stretcher_support = 138 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; 139 140 data->registry_data.ulv_support = 141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; 142 143 data->registry_data.sclk_deep_sleep_support = 144 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; 145 146 data->registry_data.disable_water_mark = 0; 147 148 data->registry_data.fan_control_support = 1; 149 data->registry_data.thermal_support = 1; 150 data->registry_data.fw_ctf_enabled = 1; 151 152 data->registry_data.avfs_support = 153 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; 154 data->registry_data.led_dpm_enabled = 1; 155 156 data->registry_data.vr0hot_enabled = 1; 157 data->registry_data.vr1hot_enabled = 1; 158 data->registry_data.regulator_hot_gpio_support = 1; 159 160 data->registry_data.didt_support = 1; 161 if (data->registry_data.didt_support) { 162 data->registry_data.didt_mode = 6; 163 data->registry_data.sq_ramping_support = 1; 164 data->registry_data.db_ramping_support = 0; 165 data->registry_data.td_ramping_support = 0; 166 data->registry_data.tcp_ramping_support = 0; 167 data->registry_data.dbr_ramping_support = 0; 168 data->registry_data.edc_didt_support = 1; 169 data->registry_data.gc_didt_support = 0; 170 data->registry_data.psm_didt_support = 0; 171 } 172 173 data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT; 174 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 175 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 176 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 177 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 178 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 179 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 180 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 181 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 182 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 183 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 184 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 185 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 186 187 data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT; 188 data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT; 189 data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT; 190 data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT; 191 } 192 193 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) 194 { 195 struct vega10_hwmgr *data = hwmgr->backend; 196 struct phm_ppt_v2_information *table_info = 197 (struct phm_ppt_v2_information *)hwmgr->pptable; 198 struct amdgpu_device *adev = hwmgr->adev; 199 200 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 201 PHM_PlatformCaps_SclkDeepSleep); 202 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 PHM_PlatformCaps_DynamicPatchPowerState); 205 206 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) 207 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 208 PHM_PlatformCaps_ControlVDDCI); 209 210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 211 PHM_PlatformCaps_EnableSMU7ThermalManagement); 212 213 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 214 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 215 PHM_PlatformCaps_UVDPowerGating); 216 217 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 218 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 219 PHM_PlatformCaps_VCEPowerGating); 220 221 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 222 PHM_PlatformCaps_UnTabledHardwareInterface); 223 224 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 225 PHM_PlatformCaps_FanSpeedInTableIsRPM); 226 227 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 228 PHM_PlatformCaps_ODFuzzyFanControlSupport); 229 230 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 231 PHM_PlatformCaps_DynamicPowerManagement); 232 233 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 234 PHM_PlatformCaps_SMC); 235 236 /* power tune caps */ 237 /* assume disabled */ 238 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 239 PHM_PlatformCaps_PowerContainment); 240 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 241 PHM_PlatformCaps_DiDtSupport); 242 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 243 PHM_PlatformCaps_SQRamping); 244 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 245 PHM_PlatformCaps_DBRamping); 246 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 247 PHM_PlatformCaps_TDRamping); 248 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 249 PHM_PlatformCaps_TCPRamping); 250 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 251 PHM_PlatformCaps_DBRRamping); 252 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 253 PHM_PlatformCaps_DiDtEDCEnable); 254 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 255 PHM_PlatformCaps_GCEDC); 256 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 257 PHM_PlatformCaps_PSM); 258 259 if (data->registry_data.didt_support) { 260 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); 261 if (data->registry_data.sq_ramping_support) 262 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); 263 if (data->registry_data.db_ramping_support) 264 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); 265 if (data->registry_data.td_ramping_support) 266 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); 267 if (data->registry_data.tcp_ramping_support) 268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); 269 if (data->registry_data.dbr_ramping_support) 270 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); 271 if (data->registry_data.edc_didt_support) 272 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); 273 if (data->registry_data.gc_didt_support) 274 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); 275 if (data->registry_data.psm_didt_support) 276 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); 277 } 278 279 if (data->registry_data.power_containment_support) 280 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 281 PHM_PlatformCaps_PowerContainment); 282 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 283 PHM_PlatformCaps_CAC); 284 285 if (table_info->tdp_table->usClockStretchAmount && 286 data->registry_data.clock_stretcher_support) 287 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 288 PHM_PlatformCaps_ClockStretcher); 289 290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 291 PHM_PlatformCaps_RegulatorHot); 292 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 293 PHM_PlatformCaps_AutomaticDCTransition); 294 295 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 296 PHM_PlatformCaps_UVDDPM); 297 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 298 PHM_PlatformCaps_VCEDPM); 299 300 return 0; 301 } 302 303 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr) 304 { 305 struct vega10_hwmgr *data = hwmgr->backend; 306 struct phm_ppt_v2_information *table_info = 307 (struct phm_ppt_v2_information *)(hwmgr->pptable); 308 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 309 struct vega10_odn_vddc_lookup_table *od_lookup_table; 310 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 311 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3]; 312 struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3]; 313 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; 314 uint32_t i; 315 int result; 316 317 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); 318 if (!result) { 319 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc; 320 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc; 321 } 322 323 od_lookup_table = &odn_table->vddc_lookup_table; 324 vddc_lookup_table = table_info->vddc_lookup_table; 325 326 for (i = 0; i < vddc_lookup_table->count; i++) 327 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd; 328 329 od_lookup_table->count = vddc_lookup_table->count; 330 331 dep_table[0] = table_info->vdd_dep_on_sclk; 332 dep_table[1] = table_info->vdd_dep_on_mclk; 333 dep_table[2] = table_info->vdd_dep_on_socclk; 334 od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk; 335 od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk; 336 od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk; 337 338 for (i = 0; i < 3; i++) 339 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]); 340 341 if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000) 342 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc; 343 if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000) 344 odn_table->min_vddc = dep_table[0]->entries[0].vddc; 345 346 i = od_table[2]->count - 1; 347 od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ? 348 hwmgr->platform_descriptor.overdriveLimit.memoryClock : 349 od_table[2]->entries[i].clk; 350 od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ? 351 odn_table->max_vddc : 352 od_table[2]->entries[i].vddc; 353 354 return 0; 355 } 356 357 static int vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) 358 { 359 struct vega10_hwmgr *data = hwmgr->backend; 360 uint32_t sub_vendor_id, hw_revision; 361 uint32_t top32, bottom32; 362 struct amdgpu_device *adev = hwmgr->adev; 363 int ret, i; 364 365 vega10_initialize_power_tune_defaults(hwmgr); 366 367 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 368 data->smu_features[i].smu_feature_id = 0xffff; 369 data->smu_features[i].smu_feature_bitmap = 1 << i; 370 data->smu_features[i].enabled = false; 371 data->smu_features[i].supported = false; 372 } 373 374 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 375 FEATURE_DPM_PREFETCHER_BIT; 376 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 377 FEATURE_DPM_GFXCLK_BIT; 378 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 379 FEATURE_DPM_UCLK_BIT; 380 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 381 FEATURE_DPM_SOCCLK_BIT; 382 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 383 FEATURE_DPM_UVD_BIT; 384 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 385 FEATURE_DPM_VCE_BIT; 386 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 387 FEATURE_DPM_MP0CLK_BIT; 388 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 389 FEATURE_DPM_LINK_BIT; 390 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 391 FEATURE_DPM_DCEFCLK_BIT; 392 data->smu_features[GNLD_ULV].smu_feature_id = 393 FEATURE_ULV_BIT; 394 data->smu_features[GNLD_AVFS].smu_feature_id = 395 FEATURE_AVFS_BIT; 396 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 397 FEATURE_DS_GFXCLK_BIT; 398 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 399 FEATURE_DS_SOCCLK_BIT; 400 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 401 FEATURE_DS_LCLK_BIT; 402 data->smu_features[GNLD_PPT].smu_feature_id = 403 FEATURE_PPT_BIT; 404 data->smu_features[GNLD_TDC].smu_feature_id = 405 FEATURE_TDC_BIT; 406 data->smu_features[GNLD_THERMAL].smu_feature_id = 407 FEATURE_THERMAL_BIT; 408 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 409 FEATURE_GFX_PER_CU_CG_BIT; 410 data->smu_features[GNLD_RM].smu_feature_id = 411 FEATURE_RM_BIT; 412 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 413 FEATURE_DS_DCEFCLK_BIT; 414 data->smu_features[GNLD_ACDC].smu_feature_id = 415 FEATURE_ACDC_BIT; 416 data->smu_features[GNLD_VR0HOT].smu_feature_id = 417 FEATURE_VR0HOT_BIT; 418 data->smu_features[GNLD_VR1HOT].smu_feature_id = 419 FEATURE_VR1HOT_BIT; 420 data->smu_features[GNLD_FW_CTF].smu_feature_id = 421 FEATURE_FW_CTF_BIT; 422 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 423 FEATURE_LED_DISPLAY_BIT; 424 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 425 FEATURE_FAN_CONTROL_BIT; 426 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; 427 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 428 data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT; 429 430 if (!data->registry_data.prefetcher_dpm_key_disabled) 431 data->smu_features[GNLD_DPM_PREFETCHER].supported = true; 432 433 if (!data->registry_data.sclk_dpm_key_disabled) 434 data->smu_features[GNLD_DPM_GFXCLK].supported = true; 435 436 if (!data->registry_data.mclk_dpm_key_disabled) 437 data->smu_features[GNLD_DPM_UCLK].supported = true; 438 439 if (!data->registry_data.socclk_dpm_key_disabled) 440 data->smu_features[GNLD_DPM_SOCCLK].supported = true; 441 442 if (PP_CAP(PHM_PlatformCaps_UVDDPM)) 443 data->smu_features[GNLD_DPM_UVD].supported = true; 444 445 if (PP_CAP(PHM_PlatformCaps_VCEDPM)) 446 data->smu_features[GNLD_DPM_VCE].supported = true; 447 448 data->smu_features[GNLD_DPM_LINK].supported = true; 449 450 if (!data->registry_data.dcefclk_dpm_key_disabled) 451 data->smu_features[GNLD_DPM_DCEFCLK].supported = true; 452 453 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) && 454 data->registry_data.sclk_deep_sleep_support) { 455 data->smu_features[GNLD_DS_GFXCLK].supported = true; 456 data->smu_features[GNLD_DS_SOCCLK].supported = true; 457 data->smu_features[GNLD_DS_LCLK].supported = true; 458 data->smu_features[GNLD_DS_DCEFCLK].supported = true; 459 } 460 461 if (data->registry_data.enable_pkg_pwr_tracking_feature) 462 data->smu_features[GNLD_PPT].supported = true; 463 464 if (data->registry_data.enable_tdc_limit_feature) 465 data->smu_features[GNLD_TDC].supported = true; 466 467 if (data->registry_data.thermal_support) 468 data->smu_features[GNLD_THERMAL].supported = true; 469 470 if (data->registry_data.fan_control_support) 471 data->smu_features[GNLD_FAN_CONTROL].supported = true; 472 473 if (data->registry_data.fw_ctf_enabled) 474 data->smu_features[GNLD_FW_CTF].supported = true; 475 476 if (data->registry_data.avfs_support) 477 data->smu_features[GNLD_AVFS].supported = true; 478 479 if (data->registry_data.led_dpm_enabled) 480 data->smu_features[GNLD_LED_DISPLAY].supported = true; 481 482 if (data->registry_data.vr1hot_enabled) 483 data->smu_features[GNLD_VR1HOT].supported = true; 484 485 if (data->registry_data.vr0hot_enabled) 486 data->smu_features[GNLD_VR0HOT].supported = true; 487 488 ret = smum_send_msg_to_smc(hwmgr, 489 PPSMC_MSG_GetSmuVersion, 490 &hwmgr->smu_version); 491 if (ret) 492 return ret; 493 494 /* ACG firmware has major version 5 */ 495 if ((hwmgr->smu_version & 0xff000000) == 0x5000000) 496 data->smu_features[GNLD_ACG].supported = true; 497 if (data->registry_data.didt_support) 498 data->smu_features[GNLD_DIDT].supported = true; 499 500 hw_revision = adev->pdev->revision; 501 sub_vendor_id = adev->pdev->subsystem_vendor; 502 503 if ((hwmgr->chip_id == 0x6862 || 504 hwmgr->chip_id == 0x6861 || 505 hwmgr->chip_id == 0x6868) && 506 (hw_revision == 0) && 507 (sub_vendor_id != 0x1002)) 508 data->smu_features[GNLD_PCC_LIMIT].supported = true; 509 510 /* Get the SN to turn into a Unique ID */ 511 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 512 if (ret) 513 return ret; 514 515 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 516 if (ret) 517 return ret; 518 519 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 520 return 0; 521 } 522 523 #ifdef PPLIB_VEGA10_EVV_SUPPORT 524 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, 525 phm_ppt_v1_voltage_lookup_table *lookup_table, 526 uint16_t virtual_voltage_id, int32_t *socclk) 527 { 528 uint8_t entry_id; 529 uint8_t voltage_id; 530 struct phm_ppt_v2_information *table_info = 531 (struct phm_ppt_v2_information *)(hwmgr->pptable); 532 533 PP_ASSERT_WITH_CODE(lookup_table->count != 0, 534 "Lookup table is empty", 535 return -EINVAL); 536 537 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */ 538 for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) { 539 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd; 540 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id) 541 break; 542 } 543 544 PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count, 545 "Can't find requested voltage id in vdd_dep_on_socclk table!", 546 return -EINVAL); 547 548 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk; 549 550 return 0; 551 } 552 553 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 554 /** 555 * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID. 556 * 557 * @hwmgr: the address of the powerplay hardware manager. 558 * return: always 0. 559 */ 560 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) 561 { 562 struct vega10_hwmgr *data = hwmgr->backend; 563 uint16_t vv_id; 564 uint32_t vddc = 0; 565 uint16_t i, j; 566 uint32_t sclk = 0; 567 struct phm_ppt_v2_information *table_info = 568 (struct phm_ppt_v2_information *)hwmgr->pptable; 569 struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table = 570 table_info->vdd_dep_on_socclk; 571 int result; 572 573 for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) { 574 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 575 576 if (!vega10_get_socclk_for_voltage_evv(hwmgr, 577 table_info->vddc_lookup_table, vv_id, &sclk)) { 578 if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) { 579 for (j = 1; j < socclk_table->count; j++) { 580 if (socclk_table->entries[j].clk == sclk && 581 socclk_table->entries[j].cks_enable == 0) { 582 sclk += 5000; 583 break; 584 } 585 } 586 } 587 588 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, 589 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), 590 "Error retrieving EVV voltage value!", 591 continue); 592 593 594 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ 595 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), 596 "Invalid VDDC value", result = -EINVAL;); 597 598 /* the voltage should not be zero nor equal to leakage ID */ 599 if (vddc != 0 && vddc != vv_id) { 600 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100); 601 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; 602 data->vddc_leakage.count++; 603 } 604 } 605 } 606 607 return 0; 608 } 609 610 /** 611 * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value. 612 * 613 * @hwmgr: the address of the powerplay hardware manager. 614 * @voltage: pointer to changing voltage 615 * @leakage_table: pointer to leakage table 616 */ 617 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, 618 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table) 619 { 620 uint32_t index; 621 622 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 623 for (index = 0; index < leakage_table->count; index++) { 624 /* if this voltage matches a leakage voltage ID */ 625 /* patch with actual leakage voltage */ 626 if (leakage_table->leakage_id[index] == *voltage) { 627 *voltage = leakage_table->actual_voltage[index]; 628 break; 629 } 630 } 631 632 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 633 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 634 } 635 636 /** 637 * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. 638 * 639 * @hwmgr: the address of the powerplay hardware manager. 640 * @lookup_table: pointer to voltage lookup table 641 * @leakage_table: pointer to leakage table 642 * return: always 0 643 */ 644 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, 645 phm_ppt_v1_voltage_lookup_table *lookup_table, 646 struct vega10_leakage_voltage *leakage_table) 647 { 648 uint32_t i; 649 650 for (i = 0; i < lookup_table->count; i++) 651 vega10_patch_with_vdd_leakage(hwmgr, 652 &lookup_table->entries[i].us_vdd, leakage_table); 653 654 return 0; 655 } 656 657 static int vega10_patch_clock_voltage_limits_with_vddc_leakage( 658 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table, 659 uint16_t *vddc) 660 { 661 vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); 662 663 return 0; 664 } 665 #endif 666 667 static int vega10_patch_voltage_dependency_tables_with_lookup_table( 668 struct pp_hwmgr *hwmgr) 669 { 670 uint8_t entry_id, voltage_id; 671 unsigned i; 672 struct phm_ppt_v2_information *table_info = 673 (struct phm_ppt_v2_information *)(hwmgr->pptable); 674 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 675 table_info->mm_dep_table; 676 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = 677 table_info->vdd_dep_on_mclk; 678 679 for (i = 0; i < 6; i++) { 680 struct phm_ppt_v1_clock_voltage_dependency_table *vdt; 681 switch (i) { 682 case 0: vdt = table_info->vdd_dep_on_socclk; break; 683 case 1: vdt = table_info->vdd_dep_on_sclk; break; 684 case 2: vdt = table_info->vdd_dep_on_dcefclk; break; 685 case 3: vdt = table_info->vdd_dep_on_pixclk; break; 686 case 4: vdt = table_info->vdd_dep_on_dispclk; break; 687 case 5: vdt = table_info->vdd_dep_on_phyclk; break; 688 } 689 690 for (entry_id = 0; entry_id < vdt->count; entry_id++) { 691 voltage_id = vdt->entries[entry_id].vddInd; 692 vdt->entries[entry_id].vddc = 693 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 694 } 695 } 696 697 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { 698 voltage_id = mm_table->entries[entry_id].vddcInd; 699 mm_table->entries[entry_id].vddc = 700 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 701 } 702 703 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 704 voltage_id = mclk_table->entries[entry_id].vddInd; 705 mclk_table->entries[entry_id].vddc = 706 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 707 voltage_id = mclk_table->entries[entry_id].vddciInd; 708 mclk_table->entries[entry_id].vddci = 709 table_info->vddci_lookup_table->entries[voltage_id].us_vdd; 710 voltage_id = mclk_table->entries[entry_id].mvddInd; 711 mclk_table->entries[entry_id].mvdd = 712 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd; 713 } 714 715 716 return 0; 717 718 } 719 720 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr, 721 struct phm_ppt_v1_voltage_lookup_table *lookup_table) 722 { 723 uint32_t table_size, i, j; 724 725 PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count, 726 "Lookup table is empty", return -EINVAL); 727 728 table_size = lookup_table->count; 729 730 /* Sorting voltages */ 731 for (i = 0; i < table_size - 1; i++) { 732 for (j = i + 1; j > 0; j--) { 733 if (lookup_table->entries[j].us_vdd < 734 lookup_table->entries[j - 1].us_vdd) { 735 swap(lookup_table->entries[j - 1], 736 lookup_table->entries[j]); 737 } 738 } 739 } 740 741 return 0; 742 } 743 744 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr) 745 { 746 int result = 0; 747 int tmp_result; 748 struct phm_ppt_v2_information *table_info = 749 (struct phm_ppt_v2_information *)(hwmgr->pptable); 750 #ifdef PPLIB_VEGA10_EVV_SUPPORT 751 struct vega10_hwmgr *data = hwmgr->backend; 752 753 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr, 754 table_info->vddc_lookup_table, &(data->vddc_leakage)); 755 if (tmp_result) 756 result = tmp_result; 757 758 tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, 759 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); 760 if (tmp_result) 761 result = tmp_result; 762 #endif 763 764 tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); 765 if (tmp_result) 766 result = tmp_result; 767 768 tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); 769 if (tmp_result) 770 result = tmp_result; 771 772 return result; 773 } 774 775 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 776 { 777 struct phm_ppt_v2_information *table_info = 778 (struct phm_ppt_v2_information *)(hwmgr->pptable); 779 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 780 table_info->vdd_dep_on_socclk; 781 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = 782 table_info->vdd_dep_on_mclk; 783 784 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, 785 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); 786 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, 787 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); 788 789 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, 790 "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); 791 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 792 "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); 793 794 table_info->max_clock_voltage_on_ac.sclk = 795 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; 796 table_info->max_clock_voltage_on_ac.mclk = 797 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 798 table_info->max_clock_voltage_on_ac.vddc = 799 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 800 table_info->max_clock_voltage_on_ac.vddci = 801 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; 802 803 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = 804 table_info->max_clock_voltage_on_ac.sclk; 805 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = 806 table_info->max_clock_voltage_on_ac.mclk; 807 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = 808 table_info->max_clock_voltage_on_ac.vddc; 809 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = 810 table_info->max_clock_voltage_on_ac.vddci; 811 812 return 0; 813 } 814 815 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 816 { 817 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 818 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 819 820 kfree(hwmgr->backend); 821 hwmgr->backend = NULL; 822 823 return 0; 824 } 825 826 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 827 { 828 int result = 0; 829 struct vega10_hwmgr *data; 830 uint32_t config_telemetry = 0; 831 struct pp_atomfwctrl_voltage_table vol_table; 832 struct amdgpu_device *adev = hwmgr->adev; 833 834 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); 835 if (data == NULL) 836 return -ENOMEM; 837 838 hwmgr->backend = data; 839 840 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 841 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 842 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 843 844 vega10_set_default_registry_data(hwmgr); 845 data->disable_dpm_mask = 0xff; 846 847 /* need to set voltage control types before EVV patching */ 848 data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE; 849 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE; 850 data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE; 851 852 /* VDDCR_SOC */ 853 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 854 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { 855 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, 856 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2, 857 &vol_table)) { 858 config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) | 859 (vol_table.telemetry_offset & 0xff); 860 data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; 861 } 862 } else { 863 kfree(hwmgr->backend); 864 hwmgr->backend = NULL; 865 PP_ASSERT_WITH_CODE(false, 866 "VDDCR_SOC is not SVID2!", 867 return -1); 868 } 869 870 /* MVDDC */ 871 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 872 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) { 873 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, 874 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2, 875 &vol_table)) { 876 config_telemetry |= 877 ((vol_table.telemetry_slope << 24) & 0xff000000) | 878 ((vol_table.telemetry_offset << 16) & 0xff0000); 879 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; 880 } 881 } 882 883 /* VDDCI_MEM */ 884 if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) { 885 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 886 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 887 data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO; 888 } 889 890 data->config_telemetry = config_telemetry; 891 892 vega10_set_features_platform_caps(hwmgr); 893 894 result = vega10_init_dpm_defaults(hwmgr); 895 if (result) 896 return result; 897 898 #ifdef PPLIB_VEGA10_EVV_SUPPORT 899 /* Get leakage voltage based on leakage ID. */ 900 PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr), 901 "Get EVV Voltage Failed. Abort Driver loading!", 902 return -1); 903 #endif 904 905 /* Patch our voltage dependency table with actual leakage voltage 906 * We need to perform leakage translation before it's used by other functions 907 */ 908 vega10_complete_dependency_tables(hwmgr); 909 910 /* Parse pptable data read from VBIOS */ 911 vega10_set_private_data_based_on_pptable(hwmgr); 912 913 data->is_tlu_enabled = false; 914 915 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 916 VEGA10_MAX_HARDWARE_POWERLEVELS; 917 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 918 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 919 920 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 921 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 922 hwmgr->platform_descriptor.clockStep.engineClock = 500; 923 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 924 925 data->total_active_cus = adev->gfx.cu_info.number; 926 if (!hwmgr->not_vf) 927 return result; 928 929 /* Setup default Overdrive Fan control settings */ 930 data->odn_fan_table.target_fan_speed = 931 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; 932 data->odn_fan_table.target_temperature = 933 hwmgr->thermal_controller. 934 advanceFanControlParameters.ucTargetTemperature; 935 data->odn_fan_table.min_performance_clock = 936 hwmgr->thermal_controller.advanceFanControlParameters. 937 ulMinFanSCLKAcousticLimit; 938 data->odn_fan_table.min_fan_limit = 939 hwmgr->thermal_controller. 940 advanceFanControlParameters.usFanPWMMinLimit * 941 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 942 943 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & 944 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> 945 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 946 PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), 947 "Mem Channel Index Exceeded maximum!", 948 return -EINVAL); 949 950 return result; 951 } 952 953 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr) 954 { 955 struct vega10_hwmgr *data = hwmgr->backend; 956 957 data->low_sclk_interrupt_threshold = 0; 958 959 return 0; 960 } 961 962 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr) 963 { 964 struct vega10_hwmgr *data = hwmgr->backend; 965 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 966 967 struct pp_atomfwctrl_voltage_table table; 968 uint8_t i, j; 969 uint32_t mask = 0; 970 uint32_t tmp; 971 int32_t ret = 0; 972 973 ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM, 974 VOLTAGE_OBJ_GPIO_LUT, &table); 975 976 if (!ret) { 977 tmp = table.mask_low; 978 for (i = 0, j = 0; i < 32; i++) { 979 if (tmp & 1) { 980 mask |= (uint32_t)(i << (8 * j)); 981 if (++j >= 3) 982 break; 983 } 984 tmp >>= 1; 985 } 986 } 987 988 pp_table->LedPin0 = (uint8_t)(mask & 0xff); 989 pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff); 990 pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff); 991 return 0; 992 } 993 994 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr) 995 { 996 if (!hwmgr->not_vf) 997 return 0; 998 999 PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr), 1000 "Failed to init sclk threshold!", 1001 return -EINVAL); 1002 1003 PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr), 1004 "Failed to set up led dpm config!", 1005 return -EINVAL); 1006 1007 smum_send_msg_to_smc_with_parameter(hwmgr, 1008 PPSMC_MSG_NumOfDisplays, 1009 0, 1010 NULL); 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values. 1017 * 1018 * @hwmgr: the address of the powerplay hardware manager. 1019 * @vol_table: the pointer to changing voltage table 1020 * return: 0 in success 1021 */ 1022 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr, 1023 struct pp_atomfwctrl_voltage_table *vol_table) 1024 { 1025 uint32_t i, j; 1026 uint16_t vvalue; 1027 bool found = false; 1028 struct pp_atomfwctrl_voltage_table *table; 1029 1030 PP_ASSERT_WITH_CODE(vol_table, 1031 "Voltage Table empty.", return -EINVAL); 1032 table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table), 1033 GFP_KERNEL); 1034 1035 if (!table) 1036 return -ENOMEM; 1037 1038 table->mask_low = vol_table->mask_low; 1039 table->phase_delay = vol_table->phase_delay; 1040 1041 for (i = 0; i < vol_table->count; i++) { 1042 vvalue = vol_table->entries[i].value; 1043 found = false; 1044 1045 for (j = 0; j < table->count; j++) { 1046 if (vvalue == table->entries[j].value) { 1047 found = true; 1048 break; 1049 } 1050 } 1051 1052 if (!found) { 1053 table->entries[table->count].value = vvalue; 1054 table->entries[table->count].smio_low = 1055 vol_table->entries[i].smio_low; 1056 table->count++; 1057 } 1058 } 1059 1060 memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table)); 1061 kfree(table); 1062 1063 return 0; 1064 } 1065 1066 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr, 1067 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1068 struct pp_atomfwctrl_voltage_table *vol_table) 1069 { 1070 int i; 1071 1072 PP_ASSERT_WITH_CODE(dep_table->count, 1073 "Voltage Dependency Table empty.", 1074 return -EINVAL); 1075 1076 vol_table->mask_low = 0; 1077 vol_table->phase_delay = 0; 1078 vol_table->count = dep_table->count; 1079 1080 for (i = 0; i < vol_table->count; i++) { 1081 vol_table->entries[i].value = dep_table->entries[i].mvdd; 1082 vol_table->entries[i].smio_low = 0; 1083 } 1084 1085 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, 1086 vol_table), 1087 "Failed to trim MVDD Table!", 1088 return -1); 1089 1090 return 0; 1091 } 1092 1093 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr, 1094 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1095 struct pp_atomfwctrl_voltage_table *vol_table) 1096 { 1097 uint32_t i; 1098 1099 PP_ASSERT_WITH_CODE(dep_table->count, 1100 "Voltage Dependency Table empty.", 1101 return -EINVAL); 1102 1103 vol_table->mask_low = 0; 1104 vol_table->phase_delay = 0; 1105 vol_table->count = dep_table->count; 1106 1107 for (i = 0; i < dep_table->count; i++) { 1108 vol_table->entries[i].value = dep_table->entries[i].vddci; 1109 vol_table->entries[i].smio_low = 0; 1110 } 1111 1112 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table), 1113 "Failed to trim VDDCI table.", 1114 return -1); 1115 1116 return 0; 1117 } 1118 1119 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr, 1120 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1121 struct pp_atomfwctrl_voltage_table *vol_table) 1122 { 1123 int i; 1124 1125 PP_ASSERT_WITH_CODE(dep_table->count, 1126 "Voltage Dependency Table empty.", 1127 return -EINVAL); 1128 1129 vol_table->mask_low = 0; 1130 vol_table->phase_delay = 0; 1131 vol_table->count = dep_table->count; 1132 1133 for (i = 0; i < vol_table->count; i++) { 1134 vol_table->entries[i].value = dep_table->entries[i].vddc; 1135 vol_table->entries[i].smio_low = 0; 1136 } 1137 1138 return 0; 1139 } 1140 1141 /* ---- Voltage Tables ---- 1142 * If the voltage table would be bigger than 1143 * what will fit into the state table on 1144 * the SMC keep only the higher entries. 1145 */ 1146 static void vega10_trim_voltage_table_to_fit_state_table( 1147 struct pp_hwmgr *hwmgr, 1148 uint32_t max_vol_steps, 1149 struct pp_atomfwctrl_voltage_table *vol_table) 1150 { 1151 unsigned int i, diff; 1152 1153 if (vol_table->count <= max_vol_steps) 1154 return; 1155 1156 diff = vol_table->count - max_vol_steps; 1157 1158 for (i = 0; i < max_vol_steps; i++) 1159 vol_table->entries[i] = vol_table->entries[i + diff]; 1160 1161 vol_table->count = max_vol_steps; 1162 } 1163 1164 /** 1165 * vega10_construct_voltage_tables - Create Voltage Tables. 1166 * 1167 * @hwmgr: the address of the powerplay hardware manager. 1168 * return: always 0 1169 */ 1170 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr) 1171 { 1172 struct vega10_hwmgr *data = hwmgr->backend; 1173 struct phm_ppt_v2_information *table_info = 1174 (struct phm_ppt_v2_information *)hwmgr->pptable; 1175 int result; 1176 1177 if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || 1178 data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1179 result = vega10_get_mvdd_voltage_table(hwmgr, 1180 table_info->vdd_dep_on_mclk, 1181 &(data->mvdd_voltage_table)); 1182 PP_ASSERT_WITH_CODE(!result, 1183 "Failed to retrieve MVDDC table!", 1184 return result); 1185 } 1186 1187 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1188 result = vega10_get_vddci_voltage_table(hwmgr, 1189 table_info->vdd_dep_on_mclk, 1190 &(data->vddci_voltage_table)); 1191 PP_ASSERT_WITH_CODE(!result, 1192 "Failed to retrieve VDDCI_MEM table!", 1193 return result); 1194 } 1195 1196 if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || 1197 data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1198 result = vega10_get_vdd_voltage_table(hwmgr, 1199 table_info->vdd_dep_on_sclk, 1200 &(data->vddc_voltage_table)); 1201 PP_ASSERT_WITH_CODE(!result, 1202 "Failed to retrieve VDDCR_SOC table!", 1203 return result); 1204 } 1205 1206 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16, 1207 "Too many voltage values for VDDC. Trimming to fit state table.", 1208 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1209 16, &(data->vddc_voltage_table))); 1210 1211 PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16, 1212 "Too many voltage values for VDDCI. Trimming to fit state table.", 1213 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1214 16, &(data->vddci_voltage_table))); 1215 1216 PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16, 1217 "Too many voltage values for MVDD. Trimming to fit state table.", 1218 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1219 16, &(data->mvdd_voltage_table))); 1220 1221 1222 return 0; 1223 } 1224 1225 /* 1226 * vega10_init_dpm_state 1227 * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 1228 * 1229 * @dpm_state: - the address of the DPM Table to initiailize. 1230 * return: None. 1231 */ 1232 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state) 1233 { 1234 dpm_state->soft_min_level = 0xff; 1235 dpm_state->soft_max_level = 0xff; 1236 dpm_state->hard_min_level = 0xff; 1237 dpm_state->hard_max_level = 0xff; 1238 } 1239 1240 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, 1241 struct vega10_single_dpm_table *dpm_table, 1242 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) 1243 { 1244 int i; 1245 1246 dpm_table->count = 0; 1247 1248 for (i = 0; i < dep_table->count; i++) { 1249 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= 1250 dep_table->entries[i].clk) { 1251 dpm_table->dpm_levels[dpm_table->count].value = 1252 dep_table->entries[i].clk; 1253 dpm_table->dpm_levels[dpm_table->count].enabled = true; 1254 dpm_table->count++; 1255 } 1256 } 1257 } 1258 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 1259 { 1260 struct vega10_hwmgr *data = hwmgr->backend; 1261 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); 1262 struct phm_ppt_v2_information *table_info = 1263 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1264 struct phm_ppt_v1_pcie_table *bios_pcie_table = 1265 table_info->pcie_table; 1266 uint32_t i; 1267 1268 PP_ASSERT_WITH_CODE(bios_pcie_table->count, 1269 "Incorrect number of PCIE States from VBIOS!", 1270 return -1); 1271 1272 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1273 if (data->registry_data.pcieSpeedOverride) 1274 pcie_table->pcie_gen[i] = 1275 data->registry_data.pcieSpeedOverride; 1276 else 1277 pcie_table->pcie_gen[i] = 1278 bios_pcie_table->entries[i].gen_speed; 1279 1280 if (data->registry_data.pcieLaneOverride) 1281 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1282 data->registry_data.pcieLaneOverride); 1283 else 1284 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1285 bios_pcie_table->entries[i].lane_width); 1286 if (data->registry_data.pcieClockOverride) 1287 pcie_table->lclk[i] = 1288 data->registry_data.pcieClockOverride; 1289 else 1290 pcie_table->lclk[i] = 1291 bios_pcie_table->entries[i].pcie_sclk; 1292 } 1293 1294 pcie_table->count = NUM_LINK_LEVELS; 1295 1296 return 0; 1297 } 1298 1299 /* 1300 * This function is to initialize all DPM state tables 1301 * for SMU based on the dependency table. 1302 * Dynamic state patching function will then trim these 1303 * state tables to the allowed range based 1304 * on the power policy or external client requests, 1305 * such as UVD request, etc. 1306 */ 1307 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 1308 { 1309 struct vega10_hwmgr *data = hwmgr->backend; 1310 struct phm_ppt_v2_information *table_info = 1311 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1312 struct vega10_single_dpm_table *dpm_table; 1313 uint32_t i; 1314 1315 struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table = 1316 table_info->vdd_dep_on_socclk; 1317 struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table = 1318 table_info->vdd_dep_on_sclk; 1319 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 1320 table_info->vdd_dep_on_mclk; 1321 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table = 1322 table_info->mm_dep_table; 1323 struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table = 1324 table_info->vdd_dep_on_dcefclk; 1325 struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table = 1326 table_info->vdd_dep_on_pixclk; 1327 struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table = 1328 table_info->vdd_dep_on_dispclk; 1329 struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table = 1330 table_info->vdd_dep_on_phyclk; 1331 1332 PP_ASSERT_WITH_CODE(dep_soc_table, 1333 "SOCCLK dependency table is missing. This table is mandatory", 1334 return -EINVAL); 1335 PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1, 1336 "SOCCLK dependency table is empty. This table is mandatory", 1337 return -EINVAL); 1338 1339 PP_ASSERT_WITH_CODE(dep_gfx_table, 1340 "GFXCLK dependency table is missing. This table is mandatory", 1341 return -EINVAL); 1342 PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1, 1343 "GFXCLK dependency table is empty. This table is mandatory", 1344 return -EINVAL); 1345 1346 PP_ASSERT_WITH_CODE(dep_mclk_table, 1347 "MCLK dependency table is missing. This table is mandatory", 1348 return -EINVAL); 1349 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, 1350 "MCLK dependency table has to have is missing. This table is mandatory", 1351 return -EINVAL); 1352 1353 /* Initialize Sclk DPM table based on allow Sclk values */ 1354 dpm_table = &(data->dpm_table.soc_table); 1355 vega10_setup_default_single_dpm_table(hwmgr, 1356 dpm_table, 1357 dep_soc_table); 1358 1359 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1360 1361 dpm_table = &(data->dpm_table.gfx_table); 1362 vega10_setup_default_single_dpm_table(hwmgr, 1363 dpm_table, 1364 dep_gfx_table); 1365 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) 1366 hwmgr->platform_descriptor.overdriveLimit.engineClock = 1367 dpm_table->dpm_levels[dpm_table->count-1].value; 1368 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1369 1370 /* Initialize Mclk DPM table based on allow Mclk values */ 1371 data->dpm_table.mem_table.count = 0; 1372 dpm_table = &(data->dpm_table.mem_table); 1373 vega10_setup_default_single_dpm_table(hwmgr, 1374 dpm_table, 1375 dep_mclk_table); 1376 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) 1377 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 1378 dpm_table->dpm_levels[dpm_table->count-1].value; 1379 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1380 1381 data->dpm_table.eclk_table.count = 0; 1382 dpm_table = &(data->dpm_table.eclk_table); 1383 for (i = 0; i < dep_mm_table->count; i++) { 1384 if (i == 0 || dpm_table->dpm_levels 1385 [dpm_table->count - 1].value <= 1386 dep_mm_table->entries[i].eclk) { 1387 dpm_table->dpm_levels[dpm_table->count].value = 1388 dep_mm_table->entries[i].eclk; 1389 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1390 dpm_table->count++; 1391 } 1392 } 1393 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1394 1395 data->dpm_table.vclk_table.count = 0; 1396 data->dpm_table.dclk_table.count = 0; 1397 dpm_table = &(data->dpm_table.vclk_table); 1398 for (i = 0; i < dep_mm_table->count; i++) { 1399 if (i == 0 || dpm_table->dpm_levels 1400 [dpm_table->count - 1].value <= 1401 dep_mm_table->entries[i].vclk) { 1402 dpm_table->dpm_levels[dpm_table->count].value = 1403 dep_mm_table->entries[i].vclk; 1404 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1405 dpm_table->count++; 1406 } 1407 } 1408 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1409 1410 dpm_table = &(data->dpm_table.dclk_table); 1411 for (i = 0; i < dep_mm_table->count; i++) { 1412 if (i == 0 || dpm_table->dpm_levels 1413 [dpm_table->count - 1].value <= 1414 dep_mm_table->entries[i].dclk) { 1415 dpm_table->dpm_levels[dpm_table->count].value = 1416 dep_mm_table->entries[i].dclk; 1417 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1418 dpm_table->count++; 1419 } 1420 } 1421 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1422 1423 /* Assume there is no headless Vega10 for now */ 1424 dpm_table = &(data->dpm_table.dcef_table); 1425 vega10_setup_default_single_dpm_table(hwmgr, 1426 dpm_table, 1427 dep_dcef_table); 1428 1429 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1430 1431 dpm_table = &(data->dpm_table.pixel_table); 1432 vega10_setup_default_single_dpm_table(hwmgr, 1433 dpm_table, 1434 dep_pix_table); 1435 1436 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1437 1438 dpm_table = &(data->dpm_table.display_table); 1439 vega10_setup_default_single_dpm_table(hwmgr, 1440 dpm_table, 1441 dep_disp_table); 1442 1443 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1444 1445 dpm_table = &(data->dpm_table.phy_table); 1446 vega10_setup_default_single_dpm_table(hwmgr, 1447 dpm_table, 1448 dep_phy_table); 1449 1450 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1451 1452 vega10_setup_default_pcie_table(hwmgr); 1453 1454 /* Zero out the saved copy of the CUSTOM profile 1455 * This will be checked when trying to set the profile 1456 * and will require that new values be passed in 1457 */ 1458 data->custom_profile_mode[0] = 0; 1459 data->custom_profile_mode[1] = 0; 1460 data->custom_profile_mode[2] = 0; 1461 data->custom_profile_mode[3] = 0; 1462 1463 /* save a copy of the default DPM table */ 1464 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 1465 sizeof(struct vega10_dpm_table)); 1466 1467 return 0; 1468 } 1469 1470 /* 1471 * vega10_populate_ulv_state 1472 * Function to provide parameters for Utral Low Voltage state to SMC. 1473 * 1474 * @hwmgr: - the address of the hardware manager. 1475 * return: Always 0. 1476 */ 1477 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr) 1478 { 1479 struct vega10_hwmgr *data = hwmgr->backend; 1480 struct phm_ppt_v2_information *table_info = 1481 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1482 1483 data->smc_state_table.pp_table.UlvOffsetVid = 1484 (uint8_t)table_info->us_ulv_voltage_offset; 1485 1486 data->smc_state_table.pp_table.UlvSmnclkDid = 1487 (uint8_t)(table_info->us_ulv_smnclk_did); 1488 data->smc_state_table.pp_table.UlvMp1clkDid = 1489 (uint8_t)(table_info->us_ulv_mp1clk_did); 1490 data->smc_state_table.pp_table.UlvGfxclkBypass = 1491 (uint8_t)(table_info->us_ulv_gfxclk_bypass); 1492 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = 1493 (uint8_t)(data->vddc_voltage_table.psi0_enable); 1494 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = 1495 (uint8_t)(data->vddc_voltage_table.psi1_enable); 1496 1497 return 0; 1498 } 1499 1500 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, 1501 uint32_t lclock, uint8_t *curr_lclk_did) 1502 { 1503 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1504 1505 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( 1506 hwmgr, 1507 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1508 lclock, ÷rs), 1509 "Failed to get LCLK clock settings from VBIOS!", 1510 return -1); 1511 1512 *curr_lclk_did = dividers.ulDid; 1513 1514 return 0; 1515 } 1516 1517 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr) 1518 { 1519 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 1520 struct vega10_hwmgr *data = 1521 (struct vega10_hwmgr *)(hwmgr->backend); 1522 uint32_t pcie_gen = 0, pcie_width = 0; 1523 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1524 int i; 1525 1526 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1527 pcie_gen = 3; 1528 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1529 pcie_gen = 2; 1530 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1531 pcie_gen = 1; 1532 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1533 pcie_gen = 0; 1534 1535 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1536 pcie_width = 6; 1537 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1538 pcie_width = 5; 1539 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1540 pcie_width = 4; 1541 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1542 pcie_width = 3; 1543 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1544 pcie_width = 2; 1545 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1546 pcie_width = 1; 1547 1548 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1549 if (pp_table->PcieGenSpeed[i] > pcie_gen) 1550 pp_table->PcieGenSpeed[i] = pcie_gen; 1551 1552 if (pp_table->PcieLaneCount[i] > pcie_width) 1553 pp_table->PcieLaneCount[i] = pcie_width; 1554 } 1555 1556 if (data->registry_data.pcie_dpm_key_disabled) { 1557 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1558 pp_table->PcieGenSpeed[i] = pcie_gen; 1559 pp_table->PcieLaneCount[i] = pcie_width; 1560 } 1561 } 1562 1563 return 0; 1564 } 1565 1566 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) 1567 { 1568 int result = -1; 1569 struct vega10_hwmgr *data = hwmgr->backend; 1570 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1571 struct vega10_pcie_table *pcie_table = 1572 &(data->dpm_table.pcie_table); 1573 uint32_t i, j; 1574 1575 for (i = 0; i < pcie_table->count; i++) { 1576 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i]; 1577 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; 1578 1579 result = vega10_populate_single_lclk_level(hwmgr, 1580 pcie_table->lclk[i], &(pp_table->LclkDid[i])); 1581 if (result) { 1582 pr_info("Populate LClock Level %d Failed!\n", i); 1583 return result; 1584 } 1585 } 1586 1587 j = i - 1; 1588 while (i < NUM_LINK_LEVELS) { 1589 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j]; 1590 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; 1591 1592 result = vega10_populate_single_lclk_level(hwmgr, 1593 pcie_table->lclk[j], &(pp_table->LclkDid[i])); 1594 if (result) { 1595 pr_info("Populate LClock Level %d Failed!\n", i); 1596 return result; 1597 } 1598 i++; 1599 } 1600 1601 return result; 1602 } 1603 1604 /** 1605 * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure 1606 * using the provided engine clock 1607 * 1608 * @hwmgr: the address of the hardware manager 1609 * @gfx_clock: the GFX clock to use to populate the structure. 1610 * @current_gfxclk_level: location in PPTable for the SMC GFXCLK structure. 1611 * @acg_freq: ACG frequenty to return (MHz) 1612 */ 1613 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, 1614 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level, 1615 uint32_t *acg_freq) 1616 { 1617 struct phm_ppt_v2_information *table_info = 1618 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1619 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk; 1620 struct vega10_hwmgr *data = hwmgr->backend; 1621 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1622 uint32_t gfx_max_clock = 1623 hwmgr->platform_descriptor.overdriveLimit.engineClock; 1624 uint32_t i = 0; 1625 1626 if (hwmgr->od_enabled) 1627 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1628 &(data->odn_dpm_table.vdd_dep_on_sclk); 1629 else 1630 dep_on_sclk = table_info->vdd_dep_on_sclk; 1631 1632 PP_ASSERT_WITH_CODE(dep_on_sclk, 1633 "Invalid SOC_VDD-GFX_CLK Dependency Table!", 1634 return -EINVAL); 1635 1636 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 1637 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock; 1638 else { 1639 for (i = 0; i < dep_on_sclk->count; i++) { 1640 if (dep_on_sclk->entries[i].clk == gfx_clock) 1641 break; 1642 } 1643 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, 1644 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", 1645 return -EINVAL); 1646 } 1647 1648 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1649 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK, 1650 gfx_clock, ÷rs), 1651 "Failed to get GFX Clock settings from VBIOS!", 1652 return -EINVAL); 1653 1654 /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */ 1655 current_gfxclk_level->FbMult = 1656 cpu_to_le32(dividers.ulPll_fb_mult); 1657 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */ 1658 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; 1659 current_gfxclk_level->SsFbMult = 1660 cpu_to_le32(dividers.ulPll_ss_fbsmult); 1661 current_gfxclk_level->SsSlewFrac = 1662 cpu_to_le16(dividers.usPll_ss_slew_frac); 1663 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); 1664 1665 *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */ 1666 1667 return 0; 1668 } 1669 1670 /** 1671 * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure 1672 * using the provided clock. 1673 * 1674 * @hwmgr: the address of the hardware manager. 1675 * @soc_clock: the SOC clock to use to populate the structure. 1676 * @current_soc_did: DFS divider to pass back to caller 1677 * @current_vol_index: index of current VDD to pass back to caller 1678 * return: 0 on success 1679 */ 1680 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr, 1681 uint32_t soc_clock, uint8_t *current_soc_did, 1682 uint8_t *current_vol_index) 1683 { 1684 struct vega10_hwmgr *data = hwmgr->backend; 1685 struct phm_ppt_v2_information *table_info = 1686 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1687 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc; 1688 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1689 uint32_t i; 1690 1691 if (hwmgr->od_enabled) { 1692 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1693 &data->odn_dpm_table.vdd_dep_on_socclk; 1694 for (i = 0; i < dep_on_soc->count; i++) { 1695 if (dep_on_soc->entries[i].clk >= soc_clock) 1696 break; 1697 } 1698 } else { 1699 dep_on_soc = table_info->vdd_dep_on_socclk; 1700 for (i = 0; i < dep_on_soc->count; i++) { 1701 if (dep_on_soc->entries[i].clk == soc_clock) 1702 break; 1703 } 1704 } 1705 1706 PP_ASSERT_WITH_CODE(dep_on_soc->count > i, 1707 "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table", 1708 return -EINVAL); 1709 1710 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1711 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1712 soc_clock, ÷rs), 1713 "Failed to get SOC Clock settings from VBIOS!", 1714 return -EINVAL); 1715 1716 *current_soc_did = (uint8_t)dividers.ulDid; 1717 *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd); 1718 return 0; 1719 } 1720 1721 /** 1722 * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure 1723 * based on the trimmed allowed dpm engine clock states 1724 * 1725 * @hwmgr: the address of the hardware manager 1726 */ 1727 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 1728 { 1729 struct vega10_hwmgr *data = hwmgr->backend; 1730 struct phm_ppt_v2_information *table_info = 1731 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1732 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1733 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 1734 int result = 0; 1735 uint32_t i, j; 1736 1737 for (i = 0; i < dpm_table->count; i++) { 1738 result = vega10_populate_single_gfx_level(hwmgr, 1739 dpm_table->dpm_levels[i].value, 1740 &(pp_table->GfxclkLevel[i]), 1741 &(pp_table->AcgFreqTable[i])); 1742 if (result) 1743 return result; 1744 } 1745 1746 j = i - 1; 1747 while (i < NUM_GFXCLK_DPM_LEVELS) { 1748 result = vega10_populate_single_gfx_level(hwmgr, 1749 dpm_table->dpm_levels[j].value, 1750 &(pp_table->GfxclkLevel[i]), 1751 &(pp_table->AcgFreqTable[i])); 1752 if (result) 1753 return result; 1754 i++; 1755 } 1756 1757 pp_table->GfxclkSlewRate = 1758 cpu_to_le16(table_info->us_gfxclk_slew_rate); 1759 1760 dpm_table = &(data->dpm_table.soc_table); 1761 for (i = 0; i < dpm_table->count; i++) { 1762 result = vega10_populate_single_soc_level(hwmgr, 1763 dpm_table->dpm_levels[i].value, 1764 &(pp_table->SocclkDid[i]), 1765 &(pp_table->SocDpmVoltageIndex[i])); 1766 if (result) 1767 return result; 1768 } 1769 1770 j = i - 1; 1771 while (i < NUM_SOCCLK_DPM_LEVELS) { 1772 result = vega10_populate_single_soc_level(hwmgr, 1773 dpm_table->dpm_levels[j].value, 1774 &(pp_table->SocclkDid[i]), 1775 &(pp_table->SocDpmVoltageIndex[i])); 1776 if (result) 1777 return result; 1778 i++; 1779 } 1780 1781 return result; 1782 } 1783 1784 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr) 1785 { 1786 struct vega10_hwmgr *data = hwmgr->backend; 1787 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1788 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 1789 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 1790 1791 uint8_t soc_vid = 0; 1792 uint32_t i, max_vddc_level; 1793 1794 if (hwmgr->od_enabled) 1795 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table; 1796 else 1797 vddc_lookup_table = table_info->vddc_lookup_table; 1798 1799 max_vddc_level = vddc_lookup_table->count; 1800 for (i = 0; i < max_vddc_level; i++) { 1801 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd); 1802 pp_table->SocVid[i] = soc_vid; 1803 } 1804 while (i < MAX_REGULAR_DPM_NUMBER) { 1805 pp_table->SocVid[i] = soc_vid; 1806 i++; 1807 } 1808 } 1809 1810 /* 1811 * Populates single SMC GFXCLK structure using the provided clock. 1812 * 1813 * @hwmgr: the address of the hardware manager. 1814 * @mem_clock: the memory clock to use to populate the structure. 1815 * return: 0 on success.. 1816 */ 1817 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, 1818 uint32_t mem_clock, uint8_t *current_mem_vid, 1819 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind) 1820 { 1821 struct vega10_hwmgr *data = hwmgr->backend; 1822 struct phm_ppt_v2_information *table_info = 1823 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1824 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk; 1825 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1826 uint32_t mem_max_clock = 1827 hwmgr->platform_descriptor.overdriveLimit.memoryClock; 1828 uint32_t i = 0; 1829 1830 if (hwmgr->od_enabled) 1831 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1832 &data->odn_dpm_table.vdd_dep_on_mclk; 1833 else 1834 dep_on_mclk = table_info->vdd_dep_on_mclk; 1835 1836 PP_ASSERT_WITH_CODE(dep_on_mclk, 1837 "Invalid SOC_VDD-UCLK Dependency Table!", 1838 return -EINVAL); 1839 1840 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 1841 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock; 1842 } else { 1843 for (i = 0; i < dep_on_mclk->count; i++) { 1844 if (dep_on_mclk->entries[i].clk == mem_clock) 1845 break; 1846 } 1847 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, 1848 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", 1849 return -EINVAL); 1850 } 1851 1852 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( 1853 hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs), 1854 "Failed to get UCLK settings from VBIOS!", 1855 return -1); 1856 1857 *current_mem_vid = 1858 (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd)); 1859 *current_mem_soc_vind = 1860 (uint8_t)(dep_on_mclk->entries[i].vddInd); 1861 current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult); 1862 current_memclk_level->Did = (uint8_t)(dividers.ulDid); 1863 1864 PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1, 1865 "Invalid Divider ID!", 1866 return -EINVAL); 1867 1868 return 0; 1869 } 1870 1871 /** 1872 * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure 1873 * based on the trimmed allowed dpm memory clock states. 1874 * 1875 * @hwmgr: the address of the hardware manager. 1876 * return: PP_Result_OK on success. 1877 */ 1878 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1879 { 1880 struct vega10_hwmgr *data = hwmgr->backend; 1881 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1882 struct vega10_single_dpm_table *dpm_table = 1883 &(data->dpm_table.mem_table); 1884 int result = 0; 1885 uint32_t i, j; 1886 1887 for (i = 0; i < dpm_table->count; i++) { 1888 result = vega10_populate_single_memory_level(hwmgr, 1889 dpm_table->dpm_levels[i].value, 1890 &(pp_table->MemVid[i]), 1891 &(pp_table->UclkLevel[i]), 1892 &(pp_table->MemSocVoltageIndex[i])); 1893 if (result) 1894 return result; 1895 } 1896 1897 j = i - 1; 1898 while (i < NUM_UCLK_DPM_LEVELS) { 1899 result = vega10_populate_single_memory_level(hwmgr, 1900 dpm_table->dpm_levels[j].value, 1901 &(pp_table->MemVid[i]), 1902 &(pp_table->UclkLevel[i]), 1903 &(pp_table->MemSocVoltageIndex[i])); 1904 if (result) 1905 return result; 1906 i++; 1907 } 1908 1909 pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels); 1910 pp_table->MemoryChannelWidth = 1911 (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH * 1912 channel_number[data->mem_channels]); 1913 1914 pp_table->LowestUclkReservedForUlv = 1915 (uint8_t)(data->lowest_uclk_reserved_for_ulv); 1916 1917 return result; 1918 } 1919 1920 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr, 1921 DSPCLK_e disp_clock) 1922 { 1923 struct vega10_hwmgr *data = hwmgr->backend; 1924 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1925 struct phm_ppt_v2_information *table_info = 1926 (struct phm_ppt_v2_information *) 1927 (hwmgr->pptable); 1928 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 1929 uint32_t i; 1930 uint16_t clk = 0, vddc = 0; 1931 uint8_t vid = 0; 1932 1933 switch (disp_clock) { 1934 case DSPCLK_DCEFCLK: 1935 dep_table = table_info->vdd_dep_on_dcefclk; 1936 break; 1937 case DSPCLK_DISPCLK: 1938 dep_table = table_info->vdd_dep_on_dispclk; 1939 break; 1940 case DSPCLK_PIXCLK: 1941 dep_table = table_info->vdd_dep_on_pixclk; 1942 break; 1943 case DSPCLK_PHYCLK: 1944 dep_table = table_info->vdd_dep_on_phyclk; 1945 break; 1946 default: 1947 return -1; 1948 } 1949 1950 PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS, 1951 "Number Of Entries Exceeded maximum!", 1952 return -1); 1953 1954 for (i = 0; i < dep_table->count; i++) { 1955 clk = (uint16_t)(dep_table->entries[i].clk / 100); 1956 vddc = table_info->vddc_lookup_table-> 1957 entries[dep_table->entries[i].vddInd].us_vdd; 1958 vid = (uint8_t)convert_to_vid(vddc); 1959 pp_table->DisplayClockTable[disp_clock][i].Freq = 1960 cpu_to_le16(clk); 1961 pp_table->DisplayClockTable[disp_clock][i].Vid = 1962 cpu_to_le16(vid); 1963 } 1964 1965 while (i < NUM_DSPCLK_LEVELS) { 1966 pp_table->DisplayClockTable[disp_clock][i].Freq = 1967 cpu_to_le16(clk); 1968 pp_table->DisplayClockTable[disp_clock][i].Vid = 1969 cpu_to_le16(vid); 1970 i++; 1971 } 1972 1973 return 0; 1974 } 1975 1976 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr) 1977 { 1978 uint32_t i; 1979 1980 for (i = 0; i < DSPCLK_COUNT; i++) { 1981 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i), 1982 "Failed to populate Clock in DisplayClockTable!", 1983 return -1); 1984 } 1985 1986 return 0; 1987 } 1988 1989 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr, 1990 uint32_t eclock, uint8_t *current_eclk_did, 1991 uint8_t *current_soc_vol) 1992 { 1993 struct phm_ppt_v2_information *table_info = 1994 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1995 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = 1996 table_info->mm_dep_table; 1997 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1998 uint32_t i; 1999 2000 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2001 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2002 eclock, ÷rs), 2003 "Failed to get ECLK clock settings from VBIOS!", 2004 return -1); 2005 2006 *current_eclk_did = (uint8_t)dividers.ulDid; 2007 2008 for (i = 0; i < dep_table->count; i++) { 2009 if (dep_table->entries[i].eclk == eclock) 2010 *current_soc_vol = dep_table->entries[i].vddcInd; 2011 } 2012 2013 return 0; 2014 } 2015 2016 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr) 2017 { 2018 struct vega10_hwmgr *data = hwmgr->backend; 2019 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2020 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); 2021 int result = -EINVAL; 2022 uint32_t i, j; 2023 2024 for (i = 0; i < dpm_table->count; i++) { 2025 result = vega10_populate_single_eclock_level(hwmgr, 2026 dpm_table->dpm_levels[i].value, 2027 &(pp_table->EclkDid[i]), 2028 &(pp_table->VceDpmVoltageIndex[i])); 2029 if (result) 2030 return result; 2031 } 2032 2033 j = i - 1; 2034 while (i < NUM_VCE_DPM_LEVELS) { 2035 result = vega10_populate_single_eclock_level(hwmgr, 2036 dpm_table->dpm_levels[j].value, 2037 &(pp_table->EclkDid[i]), 2038 &(pp_table->VceDpmVoltageIndex[i])); 2039 if (result) 2040 return result; 2041 i++; 2042 } 2043 2044 return result; 2045 } 2046 2047 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr, 2048 uint32_t vclock, uint8_t *current_vclk_did) 2049 { 2050 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 2051 2052 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2053 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2054 vclock, ÷rs), 2055 "Failed to get VCLK clock settings from VBIOS!", 2056 return -EINVAL); 2057 2058 *current_vclk_did = (uint8_t)dividers.ulDid; 2059 2060 return 0; 2061 } 2062 2063 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr, 2064 uint32_t dclock, uint8_t *current_dclk_did) 2065 { 2066 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 2067 2068 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2069 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2070 dclock, ÷rs), 2071 "Failed to get DCLK clock settings from VBIOS!", 2072 return -EINVAL); 2073 2074 *current_dclk_did = (uint8_t)dividers.ulDid; 2075 2076 return 0; 2077 } 2078 2079 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr) 2080 { 2081 struct vega10_hwmgr *data = hwmgr->backend; 2082 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2083 struct vega10_single_dpm_table *vclk_dpm_table = 2084 &(data->dpm_table.vclk_table); 2085 struct vega10_single_dpm_table *dclk_dpm_table = 2086 &(data->dpm_table.dclk_table); 2087 struct phm_ppt_v2_information *table_info = 2088 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2089 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = 2090 table_info->mm_dep_table; 2091 int result = -EINVAL; 2092 uint32_t i, j; 2093 2094 for (i = 0; i < vclk_dpm_table->count; i++) { 2095 result = vega10_populate_single_vclock_level(hwmgr, 2096 vclk_dpm_table->dpm_levels[i].value, 2097 &(pp_table->VclkDid[i])); 2098 if (result) 2099 return result; 2100 } 2101 2102 j = i - 1; 2103 while (i < NUM_UVD_DPM_LEVELS) { 2104 result = vega10_populate_single_vclock_level(hwmgr, 2105 vclk_dpm_table->dpm_levels[j].value, 2106 &(pp_table->VclkDid[i])); 2107 if (result) 2108 return result; 2109 i++; 2110 } 2111 2112 for (i = 0; i < dclk_dpm_table->count; i++) { 2113 result = vega10_populate_single_dclock_level(hwmgr, 2114 dclk_dpm_table->dpm_levels[i].value, 2115 &(pp_table->DclkDid[i])); 2116 if (result) 2117 return result; 2118 } 2119 2120 j = i - 1; 2121 while (i < NUM_UVD_DPM_LEVELS) { 2122 result = vega10_populate_single_dclock_level(hwmgr, 2123 dclk_dpm_table->dpm_levels[j].value, 2124 &(pp_table->DclkDid[i])); 2125 if (result) 2126 return result; 2127 i++; 2128 } 2129 2130 for (i = 0; i < dep_table->count; i++) { 2131 if (dep_table->entries[i].vclk == 2132 vclk_dpm_table->dpm_levels[i].value && 2133 dep_table->entries[i].dclk == 2134 dclk_dpm_table->dpm_levels[i].value) 2135 pp_table->UvdDpmVoltageIndex[i] = 2136 dep_table->entries[i].vddcInd; 2137 else 2138 return -1; 2139 } 2140 2141 j = i - 1; 2142 while (i < NUM_UVD_DPM_LEVELS) { 2143 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd; 2144 i++; 2145 } 2146 2147 return 0; 2148 } 2149 2150 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr) 2151 { 2152 struct vega10_hwmgr *data = hwmgr->backend; 2153 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2154 struct phm_ppt_v2_information *table_info = 2155 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2156 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 2157 table_info->vdd_dep_on_sclk; 2158 uint32_t i; 2159 2160 for (i = 0; i < dep_table->count; i++) { 2161 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable; 2162 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset 2163 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 2164 } 2165 2166 return 0; 2167 } 2168 2169 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 2170 { 2171 struct vega10_hwmgr *data = hwmgr->backend; 2172 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2173 struct phm_ppt_v2_information *table_info = 2174 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2175 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 2176 table_info->vdd_dep_on_sclk; 2177 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; 2178 int result = 0; 2179 uint32_t i; 2180 2181 pp_table->MinVoltageVid = (uint8_t)0xff; 2182 pp_table->MaxVoltageVid = (uint8_t)0; 2183 2184 if (data->smu_features[GNLD_AVFS].supported) { 2185 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); 2186 if (!result) { 2187 pp_table->MinVoltageVid = (uint8_t) 2188 convert_to_vid((uint16_t)(avfs_params.ulMinVddc)); 2189 pp_table->MaxVoltageVid = (uint8_t) 2190 convert_to_vid((uint16_t)(avfs_params.ulMaxVddc)); 2191 2192 pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0); 2193 pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1); 2194 pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2); 2195 pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); 2196 pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean); 2197 pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); 2198 pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor); 2199 2200 pp_table->BtcGbVdroopTableCksOff.a0 = 2201 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0); 2202 pp_table->BtcGbVdroopTableCksOff.a0_shift = 20; 2203 pp_table->BtcGbVdroopTableCksOff.a1 = 2204 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1); 2205 pp_table->BtcGbVdroopTableCksOff.a1_shift = 20; 2206 pp_table->BtcGbVdroopTableCksOff.a2 = 2207 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2); 2208 pp_table->BtcGbVdroopTableCksOff.a2_shift = 20; 2209 2210 pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson; 2211 pp_table->BtcGbVdroopTableCksOn.a0 = 2212 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0); 2213 pp_table->BtcGbVdroopTableCksOn.a0_shift = 20; 2214 pp_table->BtcGbVdroopTableCksOn.a1 = 2215 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1); 2216 pp_table->BtcGbVdroopTableCksOn.a1_shift = 20; 2217 pp_table->BtcGbVdroopTableCksOn.a2 = 2218 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2); 2219 pp_table->BtcGbVdroopTableCksOn.a2_shift = 20; 2220 2221 pp_table->AvfsGbCksOn.m1 = 2222 cpu_to_le32(avfs_params.ulGbFuseTableCksonM1); 2223 pp_table->AvfsGbCksOn.m2 = 2224 cpu_to_le32(avfs_params.ulGbFuseTableCksonM2); 2225 pp_table->AvfsGbCksOn.b = 2226 cpu_to_le32(avfs_params.ulGbFuseTableCksonB); 2227 pp_table->AvfsGbCksOn.m1_shift = 24; 2228 pp_table->AvfsGbCksOn.m2_shift = 12; 2229 pp_table->AvfsGbCksOn.b_shift = 0; 2230 2231 pp_table->OverrideAvfsGbCksOn = 2232 avfs_params.ucEnableGbFuseTableCkson; 2233 pp_table->AvfsGbCksOff.m1 = 2234 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1); 2235 pp_table->AvfsGbCksOff.m2 = 2236 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2); 2237 pp_table->AvfsGbCksOff.b = 2238 cpu_to_le32(avfs_params.ulGbFuseTableCksoffB); 2239 pp_table->AvfsGbCksOff.m1_shift = 24; 2240 pp_table->AvfsGbCksOff.m2_shift = 12; 2241 pp_table->AvfsGbCksOff.b_shift = 0; 2242 2243 for (i = 0; i < dep_table->count; i++) 2244 pp_table->StaticVoltageOffsetVid[i] = 2245 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset)); 2246 2247 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2248 data->disp_clk_quad_eqn_a) && 2249 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2250 data->disp_clk_quad_eqn_b)) { 2251 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = 2252 (int32_t)data->disp_clk_quad_eqn_a; 2253 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = 2254 (int32_t)data->disp_clk_quad_eqn_b; 2255 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = 2256 (int32_t)data->disp_clk_quad_eqn_c; 2257 } else { 2258 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = 2259 (int32_t)avfs_params.ulDispclk2GfxclkM1; 2260 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = 2261 (int32_t)avfs_params.ulDispclk2GfxclkM2; 2262 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = 2263 (int32_t)avfs_params.ulDispclk2GfxclkB; 2264 } 2265 2266 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24; 2267 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12; 2268 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12; 2269 2270 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2271 data->dcef_clk_quad_eqn_a) && 2272 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2273 data->dcef_clk_quad_eqn_b)) { 2274 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = 2275 (int32_t)data->dcef_clk_quad_eqn_a; 2276 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = 2277 (int32_t)data->dcef_clk_quad_eqn_b; 2278 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = 2279 (int32_t)data->dcef_clk_quad_eqn_c; 2280 } else { 2281 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = 2282 (int32_t)avfs_params.ulDcefclk2GfxclkM1; 2283 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = 2284 (int32_t)avfs_params.ulDcefclk2GfxclkM2; 2285 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = 2286 (int32_t)avfs_params.ulDcefclk2GfxclkB; 2287 } 2288 2289 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24; 2290 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12; 2291 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12; 2292 2293 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2294 data->pixel_clk_quad_eqn_a) && 2295 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2296 data->pixel_clk_quad_eqn_b)) { 2297 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = 2298 (int32_t)data->pixel_clk_quad_eqn_a; 2299 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = 2300 (int32_t)data->pixel_clk_quad_eqn_b; 2301 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = 2302 (int32_t)data->pixel_clk_quad_eqn_c; 2303 } else { 2304 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = 2305 (int32_t)avfs_params.ulPixelclk2GfxclkM1; 2306 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = 2307 (int32_t)avfs_params.ulPixelclk2GfxclkM2; 2308 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = 2309 (int32_t)avfs_params.ulPixelclk2GfxclkB; 2310 } 2311 2312 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24; 2313 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12; 2314 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12; 2315 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2316 data->phy_clk_quad_eqn_a) && 2317 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2318 data->phy_clk_quad_eqn_b)) { 2319 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = 2320 (int32_t)data->phy_clk_quad_eqn_a; 2321 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = 2322 (int32_t)data->phy_clk_quad_eqn_b; 2323 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = 2324 (int32_t)data->phy_clk_quad_eqn_c; 2325 } else { 2326 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = 2327 (int32_t)avfs_params.ulPhyclk2GfxclkM1; 2328 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = 2329 (int32_t)avfs_params.ulPhyclk2GfxclkM2; 2330 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = 2331 (int32_t)avfs_params.ulPhyclk2GfxclkB; 2332 } 2333 2334 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24; 2335 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12; 2336 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12; 2337 2338 pp_table->AcgBtcGbVdroopTable.a0 = avfs_params.ulAcgGbVdroopTableA0; 2339 pp_table->AcgBtcGbVdroopTable.a0_shift = 20; 2340 pp_table->AcgBtcGbVdroopTable.a1 = avfs_params.ulAcgGbVdroopTableA1; 2341 pp_table->AcgBtcGbVdroopTable.a1_shift = 20; 2342 pp_table->AcgBtcGbVdroopTable.a2 = avfs_params.ulAcgGbVdroopTableA2; 2343 pp_table->AcgBtcGbVdroopTable.a2_shift = 20; 2344 2345 pp_table->AcgAvfsGb.m1 = avfs_params.ulAcgGbFuseTableM1; 2346 pp_table->AcgAvfsGb.m2 = avfs_params.ulAcgGbFuseTableM2; 2347 pp_table->AcgAvfsGb.b = avfs_params.ulAcgGbFuseTableB; 2348 pp_table->AcgAvfsGb.m1_shift = 24; 2349 pp_table->AcgAvfsGb.m2_shift = 12; 2350 pp_table->AcgAvfsGb.b_shift = 0; 2351 2352 } else { 2353 data->smu_features[GNLD_AVFS].supported = false; 2354 } 2355 } 2356 2357 return 0; 2358 } 2359 2360 static int vega10_acg_enable(struct pp_hwmgr *hwmgr) 2361 { 2362 struct vega10_hwmgr *data = hwmgr->backend; 2363 uint32_t agc_btc_response; 2364 int ret; 2365 2366 if (data->smu_features[GNLD_ACG].supported) { 2367 if (0 == vega10_enable_smc_features(hwmgr, true, 2368 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap)) 2369 data->smu_features[GNLD_DPM_PREFETCHER].enabled = true; 2370 2371 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL); 2372 if (ret) 2373 return ret; 2374 2375 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response); 2376 if (ret) 2377 agc_btc_response = 0; 2378 2379 if (1 == agc_btc_response) { 2380 if (1 == data->acg_loop_state) 2381 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL); 2382 else if (2 == data->acg_loop_state) 2383 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL); 2384 if (0 == vega10_enable_smc_features(hwmgr, true, 2385 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2386 data->smu_features[GNLD_ACG].enabled = true; 2387 } else { 2388 pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n"); 2389 data->smu_features[GNLD_ACG].enabled = false; 2390 } 2391 } 2392 2393 return 0; 2394 } 2395 2396 static int vega10_acg_disable(struct pp_hwmgr *hwmgr) 2397 { 2398 struct vega10_hwmgr *data = hwmgr->backend; 2399 2400 if (data->smu_features[GNLD_ACG].supported && 2401 data->smu_features[GNLD_ACG].enabled) 2402 if (!vega10_enable_smc_features(hwmgr, false, 2403 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2404 data->smu_features[GNLD_ACG].enabled = false; 2405 2406 return 0; 2407 } 2408 2409 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) 2410 { 2411 struct vega10_hwmgr *data = hwmgr->backend; 2412 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2413 struct pp_atomfwctrl_gpio_parameters gpio_params = {0}; 2414 int result; 2415 2416 result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params); 2417 if (!result) { 2418 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) && 2419 data->registry_data.regulator_hot_gpio_support) { 2420 pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio; 2421 pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity; 2422 pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio; 2423 pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity; 2424 } else { 2425 pp_table->VR0HotGpio = 0; 2426 pp_table->VR0HotPolarity = 0; 2427 pp_table->VR1HotGpio = 0; 2428 pp_table->VR1HotPolarity = 0; 2429 } 2430 2431 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) && 2432 data->registry_data.ac_dc_switch_gpio_support) { 2433 pp_table->AcDcGpio = gpio_params.ucAcDcGpio; 2434 pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity; 2435 } else { 2436 pp_table->AcDcGpio = 0; 2437 pp_table->AcDcPolarity = 0; 2438 } 2439 } 2440 2441 return result; 2442 } 2443 2444 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) 2445 { 2446 struct vega10_hwmgr *data = hwmgr->backend; 2447 2448 if (data->smu_features[GNLD_AVFS].supported) { 2449 /* Already enabled or disabled */ 2450 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled)) 2451 return 0; 2452 2453 if (enable) { 2454 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2455 true, 2456 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2457 "[avfs_control] Attempt to Enable AVFS feature Failed!", 2458 return -1); 2459 data->smu_features[GNLD_AVFS].enabled = true; 2460 } else { 2461 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2462 false, 2463 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2464 "[avfs_control] Attempt to Disable AVFS feature Failed!", 2465 return -1); 2466 data->smu_features[GNLD_AVFS].enabled = false; 2467 } 2468 } 2469 2470 return 0; 2471 } 2472 2473 static int vega10_update_avfs(struct pp_hwmgr *hwmgr) 2474 { 2475 struct vega10_hwmgr *data = hwmgr->backend; 2476 2477 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 2478 vega10_avfs_enable(hwmgr, false); 2479 } else if (data->need_update_dpm_table) { 2480 vega10_avfs_enable(hwmgr, false); 2481 vega10_avfs_enable(hwmgr, true); 2482 } else { 2483 vega10_avfs_enable(hwmgr, true); 2484 } 2485 2486 return 0; 2487 } 2488 2489 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) 2490 { 2491 int result = 0; 2492 2493 uint64_t serial_number = 0; 2494 uint32_t top32, bottom32; 2495 struct phm_fuses_default fuse; 2496 2497 struct vega10_hwmgr *data = hwmgr->backend; 2498 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); 2499 2500 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 2501 if (result) 2502 return result; 2503 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 2504 if (result) 2505 return result; 2506 serial_number = ((uint64_t)bottom32 << 32) | top32; 2507 2508 if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) { 2509 avfs_fuse_table->VFT0_b = fuse.VFT0_b; 2510 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1; 2511 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2; 2512 avfs_fuse_table->VFT1_b = fuse.VFT1_b; 2513 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1; 2514 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2; 2515 avfs_fuse_table->VFT2_b = fuse.VFT2_b; 2516 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; 2517 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; 2518 result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table, 2519 AVFSFUSETABLE, false); 2520 PP_ASSERT_WITH_CODE(!result, 2521 "Failed to upload FuseOVerride!", 2522 ); 2523 } 2524 2525 return result; 2526 } 2527 2528 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr) 2529 { 2530 struct vega10_hwmgr *data = hwmgr->backend; 2531 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 2532 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 2533 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 2534 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; 2535 uint32_t i; 2536 2537 dep_table = table_info->vdd_dep_on_mclk; 2538 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk); 2539 2540 for (i = 0; i < dep_table->count; i++) { 2541 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 2542 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; 2543 return; 2544 } 2545 } 2546 2547 dep_table = table_info->vdd_dep_on_sclk; 2548 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk); 2549 for (i = 0; i < dep_table->count; i++) { 2550 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 2551 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; 2552 return; 2553 } 2554 } 2555 } 2556 2557 /** 2558 * vega10_init_smc_table - Initializes the SMC table and uploads it 2559 * 2560 * @hwmgr: the address of the powerplay hardware manager. 2561 * return: always 0 2562 */ 2563 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) 2564 { 2565 int result; 2566 struct vega10_hwmgr *data = hwmgr->backend; 2567 struct phm_ppt_v2_information *table_info = 2568 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2569 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2570 struct pp_atomfwctrl_voltage_table voltage_table; 2571 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 2572 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 2573 2574 result = vega10_setup_default_dpm_tables(hwmgr); 2575 PP_ASSERT_WITH_CODE(!result, 2576 "Failed to setup default DPM tables!", 2577 return result); 2578 2579 if (!hwmgr->not_vf) 2580 return 0; 2581 2582 /* initialize ODN table */ 2583 if (hwmgr->od_enabled) { 2584 if (odn_table->max_vddc) { 2585 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; 2586 vega10_check_dpm_table_updated(hwmgr); 2587 } else { 2588 vega10_odn_initial_default_setting(hwmgr); 2589 } 2590 } 2591 2592 result = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC, 2593 VOLTAGE_OBJ_SVID2, &voltage_table); 2594 PP_ASSERT_WITH_CODE(!result, 2595 "Failed to get voltage table!", 2596 return result); 2597 pp_table->MaxVidStep = voltage_table.max_vid_step; 2598 2599 pp_table->GfxDpmVoltageMode = 2600 (uint8_t)(table_info->uc_gfx_dpm_voltage_mode); 2601 pp_table->SocDpmVoltageMode = 2602 (uint8_t)(table_info->uc_soc_dpm_voltage_mode); 2603 pp_table->UclkDpmVoltageMode = 2604 (uint8_t)(table_info->uc_uclk_dpm_voltage_mode); 2605 pp_table->UvdDpmVoltageMode = 2606 (uint8_t)(table_info->uc_uvd_dpm_voltage_mode); 2607 pp_table->VceDpmVoltageMode = 2608 (uint8_t)(table_info->uc_vce_dpm_voltage_mode); 2609 pp_table->Mp0DpmVoltageMode = 2610 (uint8_t)(table_info->uc_mp0_dpm_voltage_mode); 2611 2612 pp_table->DisplayDpmVoltageMode = 2613 (uint8_t)(table_info->uc_dcef_dpm_voltage_mode); 2614 2615 data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable; 2616 data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable; 2617 2618 if (data->registry_data.ulv_support && 2619 table_info->us_ulv_voltage_offset) { 2620 result = vega10_populate_ulv_state(hwmgr); 2621 PP_ASSERT_WITH_CODE(!result, 2622 "Failed to initialize ULV state!", 2623 return result); 2624 } 2625 2626 result = vega10_populate_smc_link_levels(hwmgr); 2627 PP_ASSERT_WITH_CODE(!result, 2628 "Failed to initialize Link Level!", 2629 return result); 2630 2631 result = vega10_override_pcie_parameters(hwmgr); 2632 PP_ASSERT_WITH_CODE(!result, 2633 "Failed to override pcie parameters!", 2634 return result); 2635 2636 result = vega10_populate_all_graphic_levels(hwmgr); 2637 PP_ASSERT_WITH_CODE(!result, 2638 "Failed to initialize Graphics Level!", 2639 return result); 2640 2641 result = vega10_populate_all_memory_levels(hwmgr); 2642 PP_ASSERT_WITH_CODE(!result, 2643 "Failed to initialize Memory Level!", 2644 return result); 2645 2646 vega10_populate_vddc_soc_levels(hwmgr); 2647 2648 result = vega10_populate_all_display_clock_levels(hwmgr); 2649 PP_ASSERT_WITH_CODE(!result, 2650 "Failed to initialize Display Level!", 2651 return result); 2652 2653 result = vega10_populate_smc_vce_levels(hwmgr); 2654 PP_ASSERT_WITH_CODE(!result, 2655 "Failed to initialize VCE Level!", 2656 return result); 2657 2658 result = vega10_populate_smc_uvd_levels(hwmgr); 2659 PP_ASSERT_WITH_CODE(!result, 2660 "Failed to initialize UVD Level!", 2661 return result); 2662 2663 if (data->registry_data.clock_stretcher_support) { 2664 result = vega10_populate_clock_stretcher_table(hwmgr); 2665 PP_ASSERT_WITH_CODE(!result, 2666 "Failed to populate Clock Stretcher Table!", 2667 return result); 2668 } 2669 2670 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 2671 if (!result) { 2672 data->vbios_boot_state.vddc = boot_up_values.usVddc; 2673 data->vbios_boot_state.vddci = boot_up_values.usVddci; 2674 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 2675 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 2676 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 2677 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, 2678 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk); 2679 2680 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, 2681 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk); 2682 2683 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 2684 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 2685 if (0 != boot_up_values.usVddc) { 2686 smum_send_msg_to_smc_with_parameter(hwmgr, 2687 PPSMC_MSG_SetFloorSocVoltage, 2688 (boot_up_values.usVddc * 4), 2689 NULL); 2690 data->vbios_boot_state.bsoc_vddc_lock = true; 2691 } else { 2692 data->vbios_boot_state.bsoc_vddc_lock = false; 2693 } 2694 smum_send_msg_to_smc_with_parameter(hwmgr, 2695 PPSMC_MSG_SetMinDeepSleepDcefclk, 2696 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 2697 NULL); 2698 } 2699 2700 result = vega10_populate_avfs_parameters(hwmgr); 2701 PP_ASSERT_WITH_CODE(!result, 2702 "Failed to initialize AVFS Parameters!", 2703 return result); 2704 2705 result = vega10_populate_gpio_parameters(hwmgr); 2706 PP_ASSERT_WITH_CODE(!result, 2707 "Failed to initialize GPIO Parameters!", 2708 return result); 2709 2710 pp_table->GfxclkAverageAlpha = (uint8_t) 2711 (data->gfxclk_average_alpha); 2712 pp_table->SocclkAverageAlpha = (uint8_t) 2713 (data->socclk_average_alpha); 2714 pp_table->UclkAverageAlpha = (uint8_t) 2715 (data->uclk_average_alpha); 2716 pp_table->GfxActivityAverageAlpha = (uint8_t) 2717 (data->gfx_activity_average_alpha); 2718 2719 vega10_populate_and_upload_avfs_fuse_override(hwmgr); 2720 2721 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); 2722 2723 PP_ASSERT_WITH_CODE(!result, 2724 "Failed to upload PPtable!", return result); 2725 2726 result = vega10_avfs_enable(hwmgr, true); 2727 PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", 2728 return result); 2729 vega10_acg_enable(hwmgr); 2730 2731 return 0; 2732 } 2733 2734 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) 2735 { 2736 struct vega10_hwmgr *data = hwmgr->backend; 2737 2738 if (data->smu_features[GNLD_THERMAL].supported) { 2739 if (data->smu_features[GNLD_THERMAL].enabled) 2740 pr_info("THERMAL Feature Already enabled!"); 2741 2742 PP_ASSERT_WITH_CODE( 2743 !vega10_enable_smc_features(hwmgr, 2744 true, 2745 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2746 "Enable THERMAL Feature Failed!", 2747 return -1); 2748 data->smu_features[GNLD_THERMAL].enabled = true; 2749 } 2750 2751 return 0; 2752 } 2753 2754 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) 2755 { 2756 struct vega10_hwmgr *data = hwmgr->backend; 2757 2758 if (data->smu_features[GNLD_THERMAL].supported) { 2759 if (!data->smu_features[GNLD_THERMAL].enabled) 2760 pr_info("THERMAL Feature Already disabled!"); 2761 2762 PP_ASSERT_WITH_CODE( 2763 !vega10_enable_smc_features(hwmgr, 2764 false, 2765 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2766 "disable THERMAL Feature Failed!", 2767 return -1); 2768 data->smu_features[GNLD_THERMAL].enabled = false; 2769 } 2770 2771 return 0; 2772 } 2773 2774 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) 2775 { 2776 struct vega10_hwmgr *data = hwmgr->backend; 2777 2778 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { 2779 if (data->smu_features[GNLD_VR0HOT].supported) { 2780 PP_ASSERT_WITH_CODE( 2781 !vega10_enable_smc_features(hwmgr, 2782 true, 2783 data->smu_features[GNLD_VR0HOT].smu_feature_bitmap), 2784 "Attempt to Enable VR0 Hot feature Failed!", 2785 return -1); 2786 data->smu_features[GNLD_VR0HOT].enabled = true; 2787 } else { 2788 if (data->smu_features[GNLD_VR1HOT].supported) { 2789 PP_ASSERT_WITH_CODE( 2790 !vega10_enable_smc_features(hwmgr, 2791 true, 2792 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap), 2793 "Attempt to Enable VR0 Hot feature Failed!", 2794 return -1); 2795 data->smu_features[GNLD_VR1HOT].enabled = true; 2796 } 2797 } 2798 } 2799 return 0; 2800 } 2801 2802 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) 2803 { 2804 struct vega10_hwmgr *data = hwmgr->backend; 2805 2806 if (data->registry_data.ulv_support) { 2807 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2808 true, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2809 "Enable ULV Feature Failed!", 2810 return -1); 2811 data->smu_features[GNLD_ULV].enabled = true; 2812 } 2813 2814 return 0; 2815 } 2816 2817 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) 2818 { 2819 struct vega10_hwmgr *data = hwmgr->backend; 2820 2821 if (data->registry_data.ulv_support) { 2822 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2823 false, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2824 "disable ULV Feature Failed!", 2825 return -EINVAL); 2826 data->smu_features[GNLD_ULV].enabled = false; 2827 } 2828 2829 return 0; 2830 } 2831 2832 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2833 { 2834 struct vega10_hwmgr *data = hwmgr->backend; 2835 2836 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2837 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2838 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2839 "Attempt to Enable DS_GFXCLK Feature Failed!", 2840 return -EINVAL); 2841 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 2842 } 2843 2844 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2845 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2846 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2847 "Attempt to Enable DS_SOCCLK Feature Failed!", 2848 return -EINVAL); 2849 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 2850 } 2851 2852 if (data->smu_features[GNLD_DS_LCLK].supported) { 2853 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2854 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2855 "Attempt to Enable DS_LCLK Feature Failed!", 2856 return -EINVAL); 2857 data->smu_features[GNLD_DS_LCLK].enabled = true; 2858 } 2859 2860 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2861 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2862 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2863 "Attempt to Enable DS_DCEFCLK Feature Failed!", 2864 return -EINVAL); 2865 data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 2866 } 2867 2868 return 0; 2869 } 2870 2871 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2872 { 2873 struct vega10_hwmgr *data = hwmgr->backend; 2874 2875 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2876 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2877 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2878 "Attempt to disable DS_GFXCLK Feature Failed!", 2879 return -EINVAL); 2880 data->smu_features[GNLD_DS_GFXCLK].enabled = false; 2881 } 2882 2883 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2884 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2885 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2886 "Attempt to disable DS_ Feature Failed!", 2887 return -EINVAL); 2888 data->smu_features[GNLD_DS_SOCCLK].enabled = false; 2889 } 2890 2891 if (data->smu_features[GNLD_DS_LCLK].supported) { 2892 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2893 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2894 "Attempt to disable DS_LCLK Feature Failed!", 2895 return -EINVAL); 2896 data->smu_features[GNLD_DS_LCLK].enabled = false; 2897 } 2898 2899 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2900 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2901 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2902 "Attempt to disable DS_DCEFCLK Feature Failed!", 2903 return -EINVAL); 2904 data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 2905 } 2906 2907 return 0; 2908 } 2909 2910 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) 2911 { 2912 struct vega10_hwmgr *data = hwmgr->backend; 2913 uint32_t i, feature_mask = 0; 2914 2915 if (!hwmgr->not_vf) 2916 return 0; 2917 2918 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2919 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2920 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2921 "Attempt to disable LED DPM feature failed!", return -EINVAL); 2922 data->smu_features[GNLD_LED_DISPLAY].enabled = false; 2923 } 2924 2925 for (i = 0; i < GNLD_DPM_MAX; i++) { 2926 if (data->smu_features[i].smu_feature_bitmap & bitmap) { 2927 if (data->smu_features[i].supported) { 2928 if (data->smu_features[i].enabled) { 2929 feature_mask |= data->smu_features[i]. 2930 smu_feature_bitmap; 2931 data->smu_features[i].enabled = false; 2932 } 2933 } 2934 } 2935 } 2936 2937 vega10_enable_smc_features(hwmgr, false, feature_mask); 2938 2939 return 0; 2940 } 2941 2942 /** 2943 * vega10_start_dpm - Tell SMC to enabled the supported DPMs. 2944 * 2945 * @hwmgr: the address of the powerplay hardware manager. 2946 * @bitmap: bitmap for the features to enabled. 2947 * return: 0 on at least one DPM is successfully enabled. 2948 */ 2949 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) 2950 { 2951 struct vega10_hwmgr *data = hwmgr->backend; 2952 uint32_t i, feature_mask = 0; 2953 2954 for (i = 0; i < GNLD_DPM_MAX; i++) { 2955 if (data->smu_features[i].smu_feature_bitmap & bitmap) { 2956 if (data->smu_features[i].supported) { 2957 if (!data->smu_features[i].enabled) { 2958 feature_mask |= data->smu_features[i]. 2959 smu_feature_bitmap; 2960 data->smu_features[i].enabled = true; 2961 } 2962 } 2963 } 2964 } 2965 2966 if (vega10_enable_smc_features(hwmgr, 2967 true, feature_mask)) { 2968 for (i = 0; i < GNLD_DPM_MAX; i++) { 2969 if (data->smu_features[i].smu_feature_bitmap & 2970 feature_mask) 2971 data->smu_features[i].enabled = false; 2972 } 2973 } 2974 2975 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2976 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2977 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2978 "Attempt to Enable LED DPM feature Failed!", return -EINVAL); 2979 data->smu_features[GNLD_LED_DISPLAY].enabled = true; 2980 } 2981 2982 if (data->vbios_boot_state.bsoc_vddc_lock) { 2983 smum_send_msg_to_smc_with_parameter(hwmgr, 2984 PPSMC_MSG_SetFloorSocVoltage, 0, 2985 NULL); 2986 data->vbios_boot_state.bsoc_vddc_lock = false; 2987 } 2988 2989 if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { 2990 if (data->smu_features[GNLD_ACDC].supported) { 2991 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2992 true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), 2993 "Attempt to Enable DS_GFXCLK Feature Failed!", 2994 return -1); 2995 data->smu_features[GNLD_ACDC].enabled = true; 2996 } 2997 } 2998 2999 if (data->registry_data.pcie_dpm_key_disabled) { 3000 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3001 false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap), 3002 "Attempt to Disable Link DPM feature Failed!", return -EINVAL); 3003 data->smu_features[GNLD_DPM_LINK].enabled = false; 3004 data->smu_features[GNLD_DPM_LINK].supported = false; 3005 } 3006 3007 return 0; 3008 } 3009 3010 3011 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable) 3012 { 3013 struct vega10_hwmgr *data = hwmgr->backend; 3014 3015 if (data->smu_features[GNLD_PCC_LIMIT].supported) { 3016 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled) 3017 pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled"); 3018 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3019 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap), 3020 "Attempt to Enable PCC Limit feature Failed!", 3021 return -EINVAL); 3022 data->smu_features[GNLD_PCC_LIMIT].enabled = enable; 3023 } 3024 3025 return 0; 3026 } 3027 3028 static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 3029 { 3030 struct phm_ppt_v2_information *table_info = 3031 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3032 3033 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 3034 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 3035 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; 3036 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; 3037 } else { 3038 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3039 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk; 3040 } 3041 3042 hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk; 3043 hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk; 3044 3045 /* make sure the output is in Mhz */ 3046 hwmgr->pstate_sclk /= 100; 3047 hwmgr->pstate_mclk /= 100; 3048 hwmgr->pstate_sclk_peak /= 100; 3049 hwmgr->pstate_mclk_peak /= 100; 3050 } 3051 3052 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 3053 { 3054 struct vega10_hwmgr *data = hwmgr->backend; 3055 int tmp_result, result = 0; 3056 3057 if (hwmgr->not_vf) { 3058 vega10_enable_disable_PCC_limit_feature(hwmgr, true); 3059 3060 smum_send_msg_to_smc_with_parameter(hwmgr, 3061 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry, 3062 NULL); 3063 3064 tmp_result = vega10_construct_voltage_tables(hwmgr); 3065 PP_ASSERT_WITH_CODE(!tmp_result, 3066 "Failed to construct voltage tables!", 3067 result = tmp_result); 3068 } 3069 3070 if (hwmgr->not_vf || hwmgr->pp_one_vf) { 3071 tmp_result = vega10_init_smc_table(hwmgr); 3072 PP_ASSERT_WITH_CODE(!tmp_result, 3073 "Failed to initialize SMC table!", 3074 result = tmp_result); 3075 } 3076 3077 if (hwmgr->not_vf) { 3078 if (PP_CAP(PHM_PlatformCaps_ThermalController)) { 3079 tmp_result = vega10_enable_thermal_protection(hwmgr); 3080 PP_ASSERT_WITH_CODE(!tmp_result, 3081 "Failed to enable thermal protection!", 3082 result = tmp_result); 3083 } 3084 3085 tmp_result = vega10_enable_vrhot_feature(hwmgr); 3086 PP_ASSERT_WITH_CODE(!tmp_result, 3087 "Failed to enable VR hot feature!", 3088 result = tmp_result); 3089 3090 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); 3091 PP_ASSERT_WITH_CODE(!tmp_result, 3092 "Failed to enable deep sleep master switch!", 3093 result = tmp_result); 3094 } 3095 3096 if (hwmgr->not_vf) { 3097 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES); 3098 PP_ASSERT_WITH_CODE(!tmp_result, 3099 "Failed to start DPM!", result = tmp_result); 3100 } 3101 3102 if (hwmgr->not_vf) { 3103 /* enable didt, do not abort if failed didt */ 3104 tmp_result = vega10_enable_didt_config(hwmgr); 3105 PP_ASSERT(!tmp_result, 3106 "Failed to enable didt config!"); 3107 } 3108 3109 tmp_result = vega10_enable_power_containment(hwmgr); 3110 PP_ASSERT_WITH_CODE(!tmp_result, 3111 "Failed to enable power containment!", 3112 result = tmp_result); 3113 3114 if (hwmgr->not_vf) { 3115 tmp_result = vega10_power_control_set_level(hwmgr); 3116 PP_ASSERT_WITH_CODE(!tmp_result, 3117 "Failed to power control set level!", 3118 result = tmp_result); 3119 3120 tmp_result = vega10_enable_ulv(hwmgr); 3121 PP_ASSERT_WITH_CODE(!tmp_result, 3122 "Failed to enable ULV!", 3123 result = tmp_result); 3124 } 3125 3126 vega10_populate_umdpstate_clocks(hwmgr); 3127 3128 return result; 3129 } 3130 3131 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr) 3132 { 3133 return sizeof(struct vega10_power_state); 3134 } 3135 3136 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, 3137 void *state, struct pp_power_state *power_state, 3138 void *pp_table, uint32_t classification_flag) 3139 { 3140 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2; 3141 struct vega10_power_state *vega10_ps = 3142 cast_phw_vega10_power_state(&(power_state->hardware)); 3143 struct vega10_performance_level *performance_level; 3144 ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state; 3145 ATOM_Vega10_POWERPLAYTABLE *powerplay_table = 3146 (ATOM_Vega10_POWERPLAYTABLE *)pp_table; 3147 ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table = 3148 (ATOM_Vega10_SOCCLK_Dependency_Table *) 3149 (((unsigned long)powerplay_table) + 3150 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset)); 3151 ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = 3152 (ATOM_Vega10_GFXCLK_Dependency_Table *) 3153 (((unsigned long)powerplay_table) + 3154 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); 3155 ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table = 3156 (ATOM_Vega10_MCLK_Dependency_Table *) 3157 (((unsigned long)powerplay_table) + 3158 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 3159 3160 3161 /* The following fields are not initialized here: 3162 * id orderedList allStatesList 3163 */ 3164 power_state->classification.ui_label = 3165 (le16_to_cpu(state_entry->usClassification) & 3166 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> 3167 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; 3168 power_state->classification.flags = classification_flag; 3169 /* NOTE: There is a classification2 flag in BIOS 3170 * that is not being used right now 3171 */ 3172 power_state->classification.temporary_state = false; 3173 power_state->classification.to_be_deleted = false; 3174 3175 power_state->validation.disallowOnDC = 3176 ((le32_to_cpu(state_entry->ulCapsAndSettings) & 3177 ATOM_Vega10_DISALLOW_ON_DC) != 0); 3178 3179 power_state->display.disableFrameModulation = false; 3180 power_state->display.limitRefreshrate = false; 3181 power_state->display.enableVariBright = 3182 ((le32_to_cpu(state_entry->ulCapsAndSettings) & 3183 ATOM_Vega10_ENABLE_VARIBRIGHT) != 0); 3184 3185 power_state->validation.supportedPowerLevels = 0; 3186 power_state->uvd_clocks.VCLK = 0; 3187 power_state->uvd_clocks.DCLK = 0; 3188 power_state->temperatures.min = 0; 3189 power_state->temperatures.max = 0; 3190 3191 performance_level = &(vega10_ps->performance_levels 3192 [vega10_ps->performance_level_count++]); 3193 3194 PP_ASSERT_WITH_CODE( 3195 (vega10_ps->performance_level_count < 3196 NUM_GFXCLK_DPM_LEVELS), 3197 "Performance levels exceeds SMC limit!", 3198 return -1); 3199 3200 PP_ASSERT_WITH_CODE( 3201 (vega10_ps->performance_level_count < 3202 hwmgr->platform_descriptor. 3203 hardwareActivityPerformanceLevels), 3204 "Performance levels exceeds Driver limit!", 3205 return -1); 3206 3207 /* Performance levels are arranged from low to high. */ 3208 performance_level->soc_clock = socclk_dep_table->entries 3209 [state_entry->ucSocClockIndexLow].ulClk; 3210 performance_level->gfx_clock = gfxclk_dep_table->entries 3211 [state_entry->ucGfxClockIndexLow].ulClk; 3212 performance_level->mem_clock = mclk_dep_table->entries 3213 [state_entry->ucMemClockIndexLow].ulMemClk; 3214 3215 performance_level = &(vega10_ps->performance_levels 3216 [vega10_ps->performance_level_count++]); 3217 performance_level->soc_clock = socclk_dep_table->entries 3218 [state_entry->ucSocClockIndexHigh].ulClk; 3219 if (gfxclk_dep_table->ucRevId == 0) { 3220 /* under vega10 pp one vf mode, the gfx clk dpm need be lower 3221 * to level-4 due to the limited 110w-power 3222 */ 3223 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) 3224 performance_level->gfx_clock = 3225 gfxclk_dep_table->entries[4].ulClk; 3226 else 3227 performance_level->gfx_clock = gfxclk_dep_table->entries 3228 [state_entry->ucGfxClockIndexHigh].ulClk; 3229 } else if (gfxclk_dep_table->ucRevId == 1) { 3230 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries; 3231 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) 3232 performance_level->gfx_clock = patom_record_V2[4].ulClk; 3233 else 3234 performance_level->gfx_clock = 3235 patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk; 3236 } 3237 3238 performance_level->mem_clock = mclk_dep_table->entries 3239 [state_entry->ucMemClockIndexHigh].ulMemClk; 3240 return 0; 3241 } 3242 3243 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr, 3244 unsigned long entry_index, struct pp_power_state *state) 3245 { 3246 int result; 3247 struct vega10_power_state *vega10_ps; 3248 3249 state->hardware.magic = PhwVega10_Magic; 3250 3251 vega10_ps = cast_phw_vega10_power_state(&state->hardware); 3252 3253 result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state, 3254 vega10_get_pp_table_entry_callback_func); 3255 if (result) 3256 return result; 3257 3258 /* 3259 * This is the earliest time we have all the dependency table 3260 * and the VBIOS boot state 3261 */ 3262 /* set DC compatible flag if this state supports DC */ 3263 if (!state->validation.disallowOnDC) 3264 vega10_ps->dc_compatible = true; 3265 3266 vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3267 vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3268 3269 return 0; 3270 } 3271 3272 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr, 3273 struct pp_hw_power_state *hw_ps) 3274 { 3275 return 0; 3276 } 3277 3278 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 3279 struct pp_power_state *request_ps, 3280 const struct pp_power_state *current_ps) 3281 { 3282 struct amdgpu_device *adev = hwmgr->adev; 3283 struct vega10_power_state *vega10_ps; 3284 uint32_t sclk; 3285 uint32_t mclk; 3286 struct PP_Clocks minimum_clocks = {0}; 3287 bool disable_mclk_switching; 3288 bool disable_mclk_switching_for_frame_lock; 3289 bool disable_mclk_switching_for_vr; 3290 bool force_mclk_high; 3291 const struct phm_clock_and_voltage_limits *max_limits; 3292 uint32_t i; 3293 struct vega10_hwmgr *data = hwmgr->backend; 3294 struct phm_ppt_v2_information *table_info = 3295 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3296 int32_t count; 3297 uint32_t stable_pstate_sclk_dpm_percentage; 3298 uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; 3299 uint32_t latency; 3300 3301 vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware); 3302 if (!vega10_ps) 3303 return -EINVAL; 3304 3305 data->battery_state = (PP_StateUILabel_Battery == 3306 request_ps->classification.ui_label); 3307 3308 if (vega10_ps->performance_level_count != 2) 3309 pr_info("VI should always have 2 performance levels"); 3310 3311 max_limits = adev->pm.ac_power ? 3312 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : 3313 &(hwmgr->dyn_state.max_clock_voltage_on_dc); 3314 3315 /* Cap clock DPM tables at DC MAX if it is in DC. */ 3316 if (!adev->pm.ac_power) { 3317 for (i = 0; i < vega10_ps->performance_level_count; i++) { 3318 if (vega10_ps->performance_levels[i].mem_clock > 3319 max_limits->mclk) 3320 vega10_ps->performance_levels[i].mem_clock = 3321 max_limits->mclk; 3322 if (vega10_ps->performance_levels[i].gfx_clock > 3323 max_limits->sclk) 3324 vega10_ps->performance_levels[i].gfx_clock = 3325 max_limits->sclk; 3326 } 3327 } 3328 3329 /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ 3330 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; 3331 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 3332 3333 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3334 stable_pstate_sclk_dpm_percentage = 3335 data->registry_data.stable_pstate_sclk_dpm_percentage; 3336 PP_ASSERT_WITH_CODE( 3337 data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && 3338 data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, 3339 "percent sclk value must range from 1% to 100%, setting default value", 3340 stable_pstate_sclk_dpm_percentage = 75); 3341 3342 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); 3343 stable_pstate_sclk = (max_limits->sclk * 3344 stable_pstate_sclk_dpm_percentage) / 100; 3345 3346 for (count = table_info->vdd_dep_on_sclk->count - 1; 3347 count >= 0; count--) { 3348 if (stable_pstate_sclk >= 3349 table_info->vdd_dep_on_sclk->entries[count].clk) { 3350 stable_pstate_sclk = 3351 table_info->vdd_dep_on_sclk->entries[count].clk; 3352 break; 3353 } 3354 } 3355 3356 if (count < 0) 3357 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3358 3359 stable_pstate_mclk = max_limits->mclk; 3360 3361 minimum_clocks.engineClock = stable_pstate_sclk; 3362 minimum_clocks.memoryClock = stable_pstate_mclk; 3363 } 3364 3365 disable_mclk_switching_for_frame_lock = 3366 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 3367 disable_mclk_switching_for_vr = 3368 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); 3369 force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); 3370 3371 if (hwmgr->display_config->num_display == 0) 3372 disable_mclk_switching = false; 3373 else 3374 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 3375 !hwmgr->display_config->multi_monitor_in_sync) || 3376 disable_mclk_switching_for_frame_lock || 3377 disable_mclk_switching_for_vr || 3378 force_mclk_high; 3379 3380 sclk = vega10_ps->performance_levels[0].gfx_clock; 3381 mclk = vega10_ps->performance_levels[0].mem_clock; 3382 3383 if (sclk < minimum_clocks.engineClock) 3384 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? 3385 max_limits->sclk : minimum_clocks.engineClock; 3386 3387 if (mclk < minimum_clocks.memoryClock) 3388 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? 3389 max_limits->mclk : minimum_clocks.memoryClock; 3390 3391 vega10_ps->performance_levels[0].gfx_clock = sclk; 3392 vega10_ps->performance_levels[0].mem_clock = mclk; 3393 3394 if (vega10_ps->performance_levels[1].gfx_clock < 3395 vega10_ps->performance_levels[0].gfx_clock) 3396 vega10_ps->performance_levels[0].gfx_clock = 3397 vega10_ps->performance_levels[1].gfx_clock; 3398 3399 if (disable_mclk_switching) { 3400 /* Set Mclk the max of level 0 and level 1 */ 3401 if (mclk < vega10_ps->performance_levels[1].mem_clock) 3402 mclk = vega10_ps->performance_levels[1].mem_clock; 3403 3404 /* Find the lowest MCLK frequency that is within 3405 * the tolerable latency defined in DAL 3406 */ 3407 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3408 for (i = 0; i < data->mclk_latency_table.count; i++) { 3409 if ((data->mclk_latency_table.entries[i].latency <= latency) && 3410 (data->mclk_latency_table.entries[i].frequency >= 3411 vega10_ps->performance_levels[0].mem_clock) && 3412 (data->mclk_latency_table.entries[i].frequency <= 3413 vega10_ps->performance_levels[1].mem_clock)) 3414 mclk = data->mclk_latency_table.entries[i].frequency; 3415 } 3416 vega10_ps->performance_levels[0].mem_clock = mclk; 3417 } else { 3418 if (vega10_ps->performance_levels[1].mem_clock < 3419 vega10_ps->performance_levels[0].mem_clock) 3420 vega10_ps->performance_levels[0].mem_clock = 3421 vega10_ps->performance_levels[1].mem_clock; 3422 } 3423 3424 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3425 for (i = 0; i < vega10_ps->performance_level_count; i++) { 3426 vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk; 3427 vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk; 3428 } 3429 } 3430 3431 return 0; 3432 } 3433 3434 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) 3435 { 3436 struct vega10_hwmgr *data = hwmgr->backend; 3437 const struct phm_set_power_state_input *states = 3438 (const struct phm_set_power_state_input *)input; 3439 const struct vega10_power_state *vega10_ps = 3440 cast_const_phw_vega10_power_state(states->pnew_state); 3441 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 3442 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 3443 uint32_t sclk, mclk; 3444 uint32_t i; 3445 3446 if (vega10_ps == NULL) 3447 return -EINVAL; 3448 sclk = vega10_ps->performance_levels 3449 [vega10_ps->performance_level_count - 1].gfx_clock; 3450 mclk = vega10_ps->performance_levels 3451 [vega10_ps->performance_level_count - 1].mem_clock; 3452 3453 for (i = 0; i < sclk_table->count; i++) { 3454 if (sclk == sclk_table->dpm_levels[i].value) 3455 break; 3456 } 3457 3458 if (i >= sclk_table->count) { 3459 if (sclk > sclk_table->dpm_levels[i-1].value) { 3460 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3461 sclk_table->dpm_levels[i-1].value = sclk; 3462 } 3463 } 3464 3465 for (i = 0; i < mclk_table->count; i++) { 3466 if (mclk == mclk_table->dpm_levels[i].value) 3467 break; 3468 } 3469 3470 if (i >= mclk_table->count) { 3471 if (mclk > mclk_table->dpm_levels[i-1].value) { 3472 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3473 mclk_table->dpm_levels[i-1].value = mclk; 3474 } 3475 } 3476 3477 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 3478 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; 3479 3480 return 0; 3481 } 3482 3483 static int vega10_populate_and_upload_sclk_mclk_dpm_levels( 3484 struct pp_hwmgr *hwmgr, const void *input) 3485 { 3486 int result = 0; 3487 struct vega10_hwmgr *data = hwmgr->backend; 3488 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3489 struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table; 3490 struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk; 3491 int count; 3492 3493 if (!data->need_update_dpm_table) 3494 return 0; 3495 3496 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 3497 for (count = 0; count < dpm_table->gfx_table.count; count++) 3498 dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; 3499 } 3500 3501 odn_clk_table = &odn_table->vdd_dep_on_mclk; 3502 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 3503 for (count = 0; count < dpm_table->mem_table.count; count++) 3504 dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; 3505 } 3506 3507 if (data->need_update_dpm_table & 3508 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { 3509 result = vega10_populate_all_graphic_levels(hwmgr); 3510 PP_ASSERT_WITH_CODE((0 == result), 3511 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", 3512 return result); 3513 } 3514 3515 if (data->need_update_dpm_table & 3516 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3517 result = vega10_populate_all_memory_levels(hwmgr); 3518 PP_ASSERT_WITH_CODE((0 == result), 3519 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", 3520 return result); 3521 } 3522 3523 vega10_populate_vddc_soc_levels(hwmgr); 3524 3525 return result; 3526 } 3527 3528 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, 3529 struct vega10_single_dpm_table *dpm_table, 3530 uint32_t low_limit, uint32_t high_limit) 3531 { 3532 uint32_t i; 3533 3534 for (i = 0; i < dpm_table->count; i++) { 3535 if ((dpm_table->dpm_levels[i].value < low_limit) || 3536 (dpm_table->dpm_levels[i].value > high_limit)) 3537 dpm_table->dpm_levels[i].enabled = false; 3538 else 3539 dpm_table->dpm_levels[i].enabled = true; 3540 } 3541 return 0; 3542 } 3543 3544 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, 3545 struct vega10_single_dpm_table *dpm_table, 3546 uint32_t low_limit, uint32_t high_limit, 3547 uint32_t disable_dpm_mask) 3548 { 3549 uint32_t i; 3550 3551 for (i = 0; i < dpm_table->count; i++) { 3552 if ((dpm_table->dpm_levels[i].value < low_limit) || 3553 (dpm_table->dpm_levels[i].value > high_limit)) 3554 dpm_table->dpm_levels[i].enabled = false; 3555 else if (!((1 << i) & disable_dpm_mask)) 3556 dpm_table->dpm_levels[i].enabled = false; 3557 else 3558 dpm_table->dpm_levels[i].enabled = true; 3559 } 3560 return 0; 3561 } 3562 3563 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr, 3564 const struct vega10_power_state *vega10_ps) 3565 { 3566 struct vega10_hwmgr *data = hwmgr->backend; 3567 uint32_t high_limit_count; 3568 3569 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1), 3570 "power state did not have any performance level", 3571 return -1); 3572 3573 high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1; 3574 3575 vega10_trim_single_dpm_states(hwmgr, 3576 &(data->dpm_table.soc_table), 3577 vega10_ps->performance_levels[0].soc_clock, 3578 vega10_ps->performance_levels[high_limit_count].soc_clock); 3579 3580 vega10_trim_single_dpm_states_with_mask(hwmgr, 3581 &(data->dpm_table.gfx_table), 3582 vega10_ps->performance_levels[0].gfx_clock, 3583 vega10_ps->performance_levels[high_limit_count].gfx_clock, 3584 data->disable_dpm_mask); 3585 3586 vega10_trim_single_dpm_states(hwmgr, 3587 &(data->dpm_table.mem_table), 3588 vega10_ps->performance_levels[0].mem_clock, 3589 vega10_ps->performance_levels[high_limit_count].mem_clock); 3590 3591 return 0; 3592 } 3593 3594 static uint32_t vega10_find_lowest_dpm_level( 3595 struct vega10_single_dpm_table *table) 3596 { 3597 uint32_t i; 3598 3599 for (i = 0; i < table->count; i++) { 3600 if (table->dpm_levels[i].enabled) 3601 break; 3602 } 3603 3604 return i; 3605 } 3606 3607 static uint32_t vega10_find_highest_dpm_level( 3608 struct vega10_single_dpm_table *table) 3609 { 3610 uint32_t i = 0; 3611 3612 if (table->count <= MAX_REGULAR_DPM_NUMBER) { 3613 for (i = table->count; i > 0; i--) { 3614 if (table->dpm_levels[i - 1].enabled) 3615 return i - 1; 3616 } 3617 } else { 3618 pr_info("DPM Table Has Too Many Entries!"); 3619 return MAX_REGULAR_DPM_NUMBER - 1; 3620 } 3621 3622 return i; 3623 } 3624 3625 static void vega10_apply_dal_minimum_voltage_request( 3626 struct pp_hwmgr *hwmgr) 3627 { 3628 return; 3629 } 3630 3631 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) 3632 { 3633 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk; 3634 struct phm_ppt_v2_information *table_info = 3635 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3636 3637 vdd_dep_table_on_mclk = table_info->vdd_dep_on_mclk; 3638 3639 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; 3640 } 3641 3642 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) 3643 { 3644 struct vega10_hwmgr *data = hwmgr->backend; 3645 uint32_t socclk_idx; 3646 3647 vega10_apply_dal_minimum_voltage_request(hwmgr); 3648 3649 if (!data->registry_data.sclk_dpm_key_disabled) { 3650 if (data->smc_state_table.gfx_boot_level != 3651 data->dpm_table.gfx_table.dpm_state.soft_min_level) { 3652 smum_send_msg_to_smc_with_parameter(hwmgr, 3653 PPSMC_MSG_SetSoftMinGfxclkByIndex, 3654 data->smc_state_table.gfx_boot_level, 3655 NULL); 3656 3657 data->dpm_table.gfx_table.dpm_state.soft_min_level = 3658 data->smc_state_table.gfx_boot_level; 3659 } 3660 } 3661 3662 if (!data->registry_data.mclk_dpm_key_disabled) { 3663 if (data->smc_state_table.mem_boot_level != 3664 data->dpm_table.mem_table.dpm_state.soft_min_level) { 3665 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) 3666 && hwmgr->not_vf) { 3667 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); 3668 smum_send_msg_to_smc_with_parameter(hwmgr, 3669 PPSMC_MSG_SetSoftMinSocclkByIndex, 3670 socclk_idx, 3671 NULL); 3672 } else { 3673 smum_send_msg_to_smc_with_parameter(hwmgr, 3674 PPSMC_MSG_SetSoftMinUclkByIndex, 3675 data->smc_state_table.mem_boot_level, 3676 NULL); 3677 } 3678 data->dpm_table.mem_table.dpm_state.soft_min_level = 3679 data->smc_state_table.mem_boot_level; 3680 } 3681 } 3682 3683 if (!hwmgr->not_vf) 3684 return 0; 3685 3686 if (!data->registry_data.socclk_dpm_key_disabled) { 3687 if (data->smc_state_table.soc_boot_level != 3688 data->dpm_table.soc_table.dpm_state.soft_min_level) { 3689 smum_send_msg_to_smc_with_parameter(hwmgr, 3690 PPSMC_MSG_SetSoftMinSocclkByIndex, 3691 data->smc_state_table.soc_boot_level, 3692 NULL); 3693 data->dpm_table.soc_table.dpm_state.soft_min_level = 3694 data->smc_state_table.soc_boot_level; 3695 } 3696 } 3697 3698 return 0; 3699 } 3700 3701 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 3702 { 3703 struct vega10_hwmgr *data = hwmgr->backend; 3704 3705 vega10_apply_dal_minimum_voltage_request(hwmgr); 3706 3707 if (!data->registry_data.sclk_dpm_key_disabled) { 3708 if (data->smc_state_table.gfx_max_level != 3709 data->dpm_table.gfx_table.dpm_state.soft_max_level) { 3710 smum_send_msg_to_smc_with_parameter(hwmgr, 3711 PPSMC_MSG_SetSoftMaxGfxclkByIndex, 3712 data->smc_state_table.gfx_max_level, 3713 NULL); 3714 data->dpm_table.gfx_table.dpm_state.soft_max_level = 3715 data->smc_state_table.gfx_max_level; 3716 } 3717 } 3718 3719 if (!data->registry_data.mclk_dpm_key_disabled) { 3720 if (data->smc_state_table.mem_max_level != 3721 data->dpm_table.mem_table.dpm_state.soft_max_level) { 3722 smum_send_msg_to_smc_with_parameter(hwmgr, 3723 PPSMC_MSG_SetSoftMaxUclkByIndex, 3724 data->smc_state_table.mem_max_level, 3725 NULL); 3726 data->dpm_table.mem_table.dpm_state.soft_max_level = 3727 data->smc_state_table.mem_max_level; 3728 } 3729 } 3730 3731 if (!hwmgr->not_vf) 3732 return 0; 3733 3734 if (!data->registry_data.socclk_dpm_key_disabled) { 3735 if (data->smc_state_table.soc_max_level != 3736 data->dpm_table.soc_table.dpm_state.soft_max_level) { 3737 smum_send_msg_to_smc_with_parameter(hwmgr, 3738 PPSMC_MSG_SetSoftMaxSocclkByIndex, 3739 data->smc_state_table.soc_max_level, 3740 NULL); 3741 data->dpm_table.soc_table.dpm_state.soft_max_level = 3742 data->smc_state_table.soc_max_level; 3743 } 3744 } 3745 3746 return 0; 3747 } 3748 3749 static int vega10_generate_dpm_level_enable_mask( 3750 struct pp_hwmgr *hwmgr, const void *input) 3751 { 3752 struct vega10_hwmgr *data = hwmgr->backend; 3753 const struct phm_set_power_state_input *states = 3754 (const struct phm_set_power_state_input *)input; 3755 const struct vega10_power_state *vega10_ps = 3756 cast_const_phw_vega10_power_state(states->pnew_state); 3757 int i; 3758 3759 if (vega10_ps == NULL) 3760 return -EINVAL; 3761 3762 PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps), 3763 "Attempt to Trim DPM States Failed!", 3764 return -1); 3765 3766 data->smc_state_table.gfx_boot_level = 3767 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 3768 data->smc_state_table.gfx_max_level = 3769 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 3770 data->smc_state_table.mem_boot_level = 3771 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 3772 data->smc_state_table.mem_max_level = 3773 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 3774 data->smc_state_table.soc_boot_level = 3775 vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 3776 data->smc_state_table.soc_max_level = 3777 vega10_find_highest_dpm_level(&(data->dpm_table.soc_table)); 3778 3779 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 3780 "Attempt to upload DPM Bootup Levels Failed!", 3781 return -1); 3782 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 3783 "Attempt to upload DPM Max Levels Failed!", 3784 return -1); 3785 for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++) 3786 data->dpm_table.gfx_table.dpm_levels[i].enabled = true; 3787 3788 3789 for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++) 3790 data->dpm_table.mem_table.dpm_levels[i].enabled = true; 3791 3792 for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++) 3793 data->dpm_table.soc_table.dpm_levels[i].enabled = true; 3794 3795 return 0; 3796 } 3797 3798 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 3799 { 3800 struct vega10_hwmgr *data = hwmgr->backend; 3801 3802 if (data->smu_features[GNLD_DPM_VCE].supported) { 3803 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3804 enable, 3805 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 3806 "Attempt to Enable/Disable DPM VCE Failed!", 3807 return -1); 3808 data->smu_features[GNLD_DPM_VCE].enabled = enable; 3809 } 3810 3811 return 0; 3812 } 3813 3814 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) 3815 { 3816 struct vega10_hwmgr *data = hwmgr->backend; 3817 uint32_t low_sclk_interrupt_threshold = 0; 3818 3819 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && 3820 (data->low_sclk_interrupt_threshold != 0)) { 3821 low_sclk_interrupt_threshold = 3822 data->low_sclk_interrupt_threshold; 3823 3824 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold = 3825 cpu_to_le32(low_sclk_interrupt_threshold); 3826 3827 /* This message will also enable SmcToHost Interrupt */ 3828 smum_send_msg_to_smc_with_parameter(hwmgr, 3829 PPSMC_MSG_SetLowGfxclkInterruptThreshold, 3830 (uint32_t)low_sclk_interrupt_threshold, 3831 NULL); 3832 } 3833 3834 return 0; 3835 } 3836 3837 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, 3838 const void *input) 3839 { 3840 int tmp_result, result = 0; 3841 struct vega10_hwmgr *data = hwmgr->backend; 3842 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 3843 3844 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); 3845 PP_ASSERT_WITH_CODE(!tmp_result, 3846 "Failed to find DPM states clocks in DPM table!", 3847 result = tmp_result); 3848 3849 tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); 3850 PP_ASSERT_WITH_CODE(!tmp_result, 3851 "Failed to populate and upload SCLK MCLK DPM levels!", 3852 result = tmp_result); 3853 3854 tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input); 3855 PP_ASSERT_WITH_CODE(!tmp_result, 3856 "Failed to generate DPM level enabled mask!", 3857 result = tmp_result); 3858 3859 tmp_result = vega10_update_sclk_threshold(hwmgr); 3860 PP_ASSERT_WITH_CODE(!tmp_result, 3861 "Failed to update SCLK threshold!", 3862 result = tmp_result); 3863 3864 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); 3865 PP_ASSERT_WITH_CODE(!result, 3866 "Failed to upload PPtable!", return result); 3867 3868 /* 3869 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. 3870 * That effectively disables AVFS feature. 3871 */ 3872 if(hwmgr->hardcode_pp_table != NULL) 3873 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 3874 3875 vega10_update_avfs(hwmgr); 3876 3877 /* 3878 * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC. 3879 * That will help to keep AVFS disabled. 3880 */ 3881 data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; 3882 3883 return 0; 3884 } 3885 3886 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 3887 { 3888 struct pp_power_state *ps; 3889 struct vega10_power_state *vega10_ps; 3890 3891 if (hwmgr == NULL) 3892 return -EINVAL; 3893 3894 ps = hwmgr->request_ps; 3895 3896 if (ps == NULL) 3897 return -EINVAL; 3898 3899 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3900 3901 if (low) 3902 return vega10_ps->performance_levels[0].gfx_clock; 3903 else 3904 return vega10_ps->performance_levels 3905 [vega10_ps->performance_level_count - 1].gfx_clock; 3906 } 3907 3908 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 3909 { 3910 struct pp_power_state *ps; 3911 struct vega10_power_state *vega10_ps; 3912 3913 if (hwmgr == NULL) 3914 return -EINVAL; 3915 3916 ps = hwmgr->request_ps; 3917 3918 if (ps == NULL) 3919 return -EINVAL; 3920 3921 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3922 3923 if (low) 3924 return vega10_ps->performance_levels[0].mem_clock; 3925 else 3926 return vega10_ps->performance_levels 3927 [vega10_ps->performance_level_count-1].mem_clock; 3928 } 3929 3930 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, 3931 uint32_t *query) 3932 { 3933 uint32_t value; 3934 int ret; 3935 3936 if (!query) 3937 return -EINVAL; 3938 3939 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value); 3940 if (ret) 3941 return ret; 3942 3943 /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */ 3944 *query = value << 8; 3945 3946 return 0; 3947 } 3948 3949 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 3950 void *value, int *size) 3951 { 3952 struct amdgpu_device *adev = hwmgr->adev; 3953 uint32_t sclk_mhz, mclk_idx, activity_percent = 0; 3954 struct vega10_hwmgr *data = hwmgr->backend; 3955 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3956 int ret = 0; 3957 uint32_t val_vid; 3958 3959 switch (idx) { 3960 case AMDGPU_PP_SENSOR_GFX_SCLK: 3961 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz); 3962 if (ret) 3963 break; 3964 3965 *((uint32_t *)value) = sclk_mhz * 100; 3966 break; 3967 case AMDGPU_PP_SENSOR_GFX_MCLK: 3968 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx); 3969 if (ret) 3970 break; 3971 if (mclk_idx < dpm_table->mem_table.count) { 3972 *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; 3973 *size = 4; 3974 } else { 3975 ret = -EINVAL; 3976 } 3977 break; 3978 case AMDGPU_PP_SENSOR_GPU_LOAD: 3979 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0, 3980 &activity_percent); 3981 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 3982 *size = 4; 3983 break; 3984 case AMDGPU_PP_SENSOR_GPU_TEMP: 3985 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); 3986 *size = 4; 3987 break; 3988 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 3989 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value); 3990 *((uint32_t *)value) = *((uint32_t *)value) * 3991 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 3992 *size = 4; 3993 break; 3994 case AMDGPU_PP_SENSOR_MEM_TEMP: 3995 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value); 3996 *((uint32_t *)value) = *((uint32_t *)value) * 3997 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 3998 *size = 4; 3999 break; 4000 case AMDGPU_PP_SENSOR_UVD_POWER: 4001 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 4002 *size = 4; 4003 break; 4004 case AMDGPU_PP_SENSOR_VCE_POWER: 4005 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 4006 *size = 4; 4007 break; 4008 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 4009 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value); 4010 break; 4011 case AMDGPU_PP_SENSOR_VDDGFX: 4012 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & 4013 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >> 4014 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT; 4015 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid); 4016 return 0; 4017 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 4018 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value); 4019 if (!ret) 4020 *size = 8; 4021 break; 4022 default: 4023 ret = -EOPNOTSUPP; 4024 break; 4025 } 4026 4027 return ret; 4028 } 4029 4030 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, 4031 bool has_disp) 4032 { 4033 smum_send_msg_to_smc_with_parameter(hwmgr, 4034 PPSMC_MSG_SetUclkFastSwitch, 4035 has_disp ? 1 : 0, 4036 NULL); 4037 } 4038 4039 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 4040 struct pp_display_clock_request *clock_req) 4041 { 4042 int result = 0; 4043 enum amd_pp_clock_type clk_type = clock_req->clock_type; 4044 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 4045 DSPCLK_e clk_select = 0; 4046 uint32_t clk_request = 0; 4047 4048 switch (clk_type) { 4049 case amd_pp_dcef_clock: 4050 clk_select = DSPCLK_DCEFCLK; 4051 break; 4052 case amd_pp_disp_clock: 4053 clk_select = DSPCLK_DISPCLK; 4054 break; 4055 case amd_pp_pixel_clock: 4056 clk_select = DSPCLK_PIXCLK; 4057 break; 4058 case amd_pp_phy_clock: 4059 clk_select = DSPCLK_PHYCLK; 4060 break; 4061 default: 4062 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 4063 result = -1; 4064 break; 4065 } 4066 4067 if (!result) { 4068 clk_request = (clk_freq << 16) | clk_select; 4069 smum_send_msg_to_smc_with_parameter(hwmgr, 4070 PPSMC_MSG_RequestDisplayClockByFreq, 4071 clk_request, 4072 NULL); 4073 } 4074 4075 return result; 4076 } 4077 4078 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, 4079 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, 4080 uint32_t frequency) 4081 { 4082 uint8_t count; 4083 uint8_t i; 4084 4085 if (mclk_table == NULL || mclk_table->count == 0) 4086 return 0; 4087 4088 count = (uint8_t)(mclk_table->count); 4089 4090 for(i = 0; i < count; i++) { 4091 if(mclk_table->entries[i].clk >= frequency) 4092 return i; 4093 } 4094 4095 return i-1; 4096 } 4097 4098 static int vega10_notify_smc_display_config_after_ps_adjustment( 4099 struct pp_hwmgr *hwmgr) 4100 { 4101 struct vega10_hwmgr *data = hwmgr->backend; 4102 struct vega10_single_dpm_table *dpm_table = 4103 &data->dpm_table.dcef_table; 4104 struct phm_ppt_v2_information *table_info = 4105 (struct phm_ppt_v2_information *)hwmgr->pptable; 4106 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; 4107 uint32_t idx; 4108 struct PP_Clocks min_clocks = {0}; 4109 uint32_t i; 4110 struct pp_display_clock_request clock_req; 4111 4112 if ((hwmgr->display_config->num_display > 1) && 4113 !hwmgr->display_config->multi_monitor_in_sync && 4114 !hwmgr->display_config->nb_pstate_switch_disable) 4115 vega10_notify_smc_display_change(hwmgr, false); 4116 else 4117 vega10_notify_smc_display_change(hwmgr, true); 4118 4119 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 4120 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 4121 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 4122 4123 for (i = 0; i < dpm_table->count; i++) { 4124 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) 4125 break; 4126 } 4127 4128 if (i < dpm_table->count) { 4129 clock_req.clock_type = amd_pp_dcef_clock; 4130 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10; 4131 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { 4132 smum_send_msg_to_smc_with_parameter( 4133 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 4134 min_clocks.dcefClockInSR / 100, 4135 NULL); 4136 } else { 4137 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 4138 } 4139 } else { 4140 pr_debug("Cannot find requested DCEFCLK!"); 4141 } 4142 4143 if (min_clocks.memoryClock != 0) { 4144 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); 4145 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx, 4146 NULL); 4147 data->dpm_table.mem_table.dpm_state.soft_min_level= idx; 4148 } 4149 4150 return 0; 4151 } 4152 4153 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr) 4154 { 4155 struct vega10_hwmgr *data = hwmgr->backend; 4156 4157 data->smc_state_table.gfx_boot_level = 4158 data->smc_state_table.gfx_max_level = 4159 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 4160 data->smc_state_table.mem_boot_level = 4161 data->smc_state_table.mem_max_level = 4162 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 4163 4164 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4165 "Failed to upload boot level to highest!", 4166 return -1); 4167 4168 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4169 "Failed to upload dpm max level to highest!", 4170 return -1); 4171 4172 return 0; 4173 } 4174 4175 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr) 4176 { 4177 struct vega10_hwmgr *data = hwmgr->backend; 4178 4179 data->smc_state_table.gfx_boot_level = 4180 data->smc_state_table.gfx_max_level = 4181 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 4182 data->smc_state_table.mem_boot_level = 4183 data->smc_state_table.mem_max_level = 4184 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 4185 4186 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4187 "Failed to upload boot level to highest!", 4188 return -1); 4189 4190 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4191 "Failed to upload dpm max level to highest!", 4192 return -1); 4193 4194 return 0; 4195 4196 } 4197 4198 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 4199 { 4200 struct vega10_hwmgr *data = hwmgr->backend; 4201 4202 data->smc_state_table.gfx_boot_level = 4203 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 4204 data->smc_state_table.gfx_max_level = 4205 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 4206 data->smc_state_table.mem_boot_level = 4207 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 4208 data->smc_state_table.mem_max_level = 4209 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 4210 4211 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4212 "Failed to upload DPM Bootup Levels!", 4213 return -1); 4214 4215 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4216 "Failed to upload DPM Max Levels!", 4217 return -1); 4218 return 0; 4219 } 4220 4221 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 4222 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 4223 { 4224 struct phm_ppt_v2_information *table_info = 4225 (struct phm_ppt_v2_information *)(hwmgr->pptable); 4226 4227 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 4228 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL && 4229 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 4230 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; 4231 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; 4232 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; 4233 } 4234 4235 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 4236 *sclk_mask = 0; 4237 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 4238 *mclk_mask = 0; 4239 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 4240 /* under vega10 pp one vf mode, the gfx clk dpm need be lower 4241 * to level-4 due to the limited power 4242 */ 4243 if (hwmgr->pp_one_vf) 4244 *sclk_mask = 4; 4245 else 4246 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 4247 *soc_mask = table_info->vdd_dep_on_socclk->count - 1; 4248 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; 4249 } 4250 4251 return 0; 4252 } 4253 4254 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 4255 { 4256 if (!hwmgr->not_vf) 4257 return; 4258 4259 switch (mode) { 4260 case AMD_FAN_CTRL_NONE: 4261 vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 4262 break; 4263 case AMD_FAN_CTRL_MANUAL: 4264 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 4265 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 4266 break; 4267 case AMD_FAN_CTRL_AUTO: 4268 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 4269 vega10_fan_ctrl_start_smc_fan_control(hwmgr); 4270 break; 4271 default: 4272 break; 4273 } 4274 } 4275 4276 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, 4277 enum pp_clock_type type, uint32_t mask) 4278 { 4279 struct vega10_hwmgr *data = hwmgr->backend; 4280 4281 switch (type) { 4282 case PP_SCLK: 4283 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; 4284 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; 4285 4286 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4287 "Failed to upload boot level to lowest!", 4288 return -EINVAL); 4289 4290 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4291 "Failed to upload dpm max level to highest!", 4292 return -EINVAL); 4293 break; 4294 4295 case PP_MCLK: 4296 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; 4297 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; 4298 4299 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4300 "Failed to upload boot level to lowest!", 4301 return -EINVAL); 4302 4303 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4304 "Failed to upload dpm max level to highest!", 4305 return -EINVAL); 4306 4307 break; 4308 4309 case PP_SOCCLK: 4310 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; 4311 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; 4312 4313 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4314 "Failed to upload boot level to lowest!", 4315 return -EINVAL); 4316 4317 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4318 "Failed to upload dpm max level to highest!", 4319 return -EINVAL); 4320 4321 break; 4322 4323 case PP_DCEFCLK: 4324 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n"); 4325 break; 4326 4327 case PP_PCIE: 4328 default: 4329 break; 4330 } 4331 4332 return 0; 4333 } 4334 4335 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 4336 enum amd_dpm_forced_level level) 4337 { 4338 int ret = 0; 4339 uint32_t sclk_mask = 0; 4340 uint32_t mclk_mask = 0; 4341 uint32_t soc_mask = 0; 4342 4343 switch (level) { 4344 case AMD_DPM_FORCED_LEVEL_HIGH: 4345 ret = vega10_force_dpm_highest(hwmgr); 4346 break; 4347 case AMD_DPM_FORCED_LEVEL_LOW: 4348 ret = vega10_force_dpm_lowest(hwmgr); 4349 break; 4350 case AMD_DPM_FORCED_LEVEL_AUTO: 4351 ret = vega10_unforce_dpm_levels(hwmgr); 4352 break; 4353 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 4354 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 4355 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 4356 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 4357 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 4358 if (ret) 4359 return ret; 4360 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 4361 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 4362 break; 4363 case AMD_DPM_FORCED_LEVEL_MANUAL: 4364 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 4365 default: 4366 break; 4367 } 4368 4369 if (!hwmgr->not_vf) 4370 return ret; 4371 4372 if (!ret) { 4373 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 4374 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE); 4375 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 4376 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO); 4377 } 4378 4379 return ret; 4380 } 4381 4382 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) 4383 { 4384 struct vega10_hwmgr *data = hwmgr->backend; 4385 4386 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 4387 return AMD_FAN_CTRL_MANUAL; 4388 else 4389 return AMD_FAN_CTRL_AUTO; 4390 } 4391 4392 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr, 4393 struct amd_pp_simple_clock_info *info) 4394 { 4395 struct phm_ppt_v2_information *table_info = 4396 (struct phm_ppt_v2_information *)hwmgr->pptable; 4397 struct phm_clock_and_voltage_limits *max_limits = 4398 &table_info->max_clock_voltage_on_ac; 4399 4400 info->engine_max_clock = max_limits->sclk; 4401 info->memory_max_clock = max_limits->mclk; 4402 4403 return 0; 4404 } 4405 4406 static void vega10_get_sclks(struct pp_hwmgr *hwmgr, 4407 struct pp_clock_levels_with_latency *clocks) 4408 { 4409 struct phm_ppt_v2_information *table_info = 4410 (struct phm_ppt_v2_information *)hwmgr->pptable; 4411 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4412 table_info->vdd_dep_on_sclk; 4413 uint32_t i; 4414 4415 clocks->num_levels = 0; 4416 for (i = 0; i < dep_table->count; i++) { 4417 if (dep_table->entries[i].clk) { 4418 clocks->data[clocks->num_levels].clocks_in_khz = 4419 dep_table->entries[i].clk * 10; 4420 clocks->num_levels++; 4421 } 4422 } 4423 4424 } 4425 4426 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, 4427 struct pp_clock_levels_with_latency *clocks) 4428 { 4429 struct phm_ppt_v2_information *table_info = 4430 (struct phm_ppt_v2_information *)hwmgr->pptable; 4431 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4432 table_info->vdd_dep_on_mclk; 4433 struct vega10_hwmgr *data = hwmgr->backend; 4434 uint32_t j = 0; 4435 uint32_t i; 4436 4437 for (i = 0; i < dep_table->count; i++) { 4438 if (dep_table->entries[i].clk) { 4439 4440 clocks->data[j].clocks_in_khz = 4441 dep_table->entries[i].clk * 10; 4442 data->mclk_latency_table.entries[j].frequency = 4443 dep_table->entries[i].clk; 4444 clocks->data[j].latency_in_us = 4445 data->mclk_latency_table.entries[j].latency = 25; 4446 j++; 4447 } 4448 } 4449 clocks->num_levels = data->mclk_latency_table.count = j; 4450 } 4451 4452 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr, 4453 struct pp_clock_levels_with_latency *clocks) 4454 { 4455 struct phm_ppt_v2_information *table_info = 4456 (struct phm_ppt_v2_information *)hwmgr->pptable; 4457 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4458 table_info->vdd_dep_on_dcefclk; 4459 uint32_t i; 4460 4461 for (i = 0; i < dep_table->count; i++) { 4462 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4463 clocks->data[i].latency_in_us = 0; 4464 clocks->num_levels++; 4465 } 4466 } 4467 4468 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr, 4469 struct pp_clock_levels_with_latency *clocks) 4470 { 4471 struct phm_ppt_v2_information *table_info = 4472 (struct phm_ppt_v2_information *)hwmgr->pptable; 4473 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4474 table_info->vdd_dep_on_socclk; 4475 uint32_t i; 4476 4477 for (i = 0; i < dep_table->count; i++) { 4478 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4479 clocks->data[i].latency_in_us = 0; 4480 clocks->num_levels++; 4481 } 4482 } 4483 4484 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 4485 enum amd_pp_clock_type type, 4486 struct pp_clock_levels_with_latency *clocks) 4487 { 4488 switch (type) { 4489 case amd_pp_sys_clock: 4490 vega10_get_sclks(hwmgr, clocks); 4491 break; 4492 case amd_pp_mem_clock: 4493 vega10_get_memclocks(hwmgr, clocks); 4494 break; 4495 case amd_pp_dcef_clock: 4496 vega10_get_dcefclocks(hwmgr, clocks); 4497 break; 4498 case amd_pp_soc_clock: 4499 vega10_get_socclocks(hwmgr, clocks); 4500 break; 4501 default: 4502 return -1; 4503 } 4504 4505 return 0; 4506 } 4507 4508 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 4509 enum amd_pp_clock_type type, 4510 struct pp_clock_levels_with_voltage *clocks) 4511 { 4512 struct phm_ppt_v2_information *table_info = 4513 (struct phm_ppt_v2_information *)hwmgr->pptable; 4514 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 4515 uint32_t i; 4516 4517 switch (type) { 4518 case amd_pp_mem_clock: 4519 dep_table = table_info->vdd_dep_on_mclk; 4520 break; 4521 case amd_pp_dcef_clock: 4522 dep_table = table_info->vdd_dep_on_dcefclk; 4523 break; 4524 case amd_pp_disp_clock: 4525 dep_table = table_info->vdd_dep_on_dispclk; 4526 break; 4527 case amd_pp_pixel_clock: 4528 dep_table = table_info->vdd_dep_on_pixclk; 4529 break; 4530 case amd_pp_phy_clock: 4531 dep_table = table_info->vdd_dep_on_phyclk; 4532 break; 4533 default: 4534 return -1; 4535 } 4536 4537 for (i = 0; i < dep_table->count; i++) { 4538 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4539 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table-> 4540 entries[dep_table->entries[i].vddInd].us_vdd); 4541 clocks->num_levels++; 4542 } 4543 4544 if (i < dep_table->count) 4545 return -1; 4546 4547 return 0; 4548 } 4549 4550 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 4551 void *clock_range) 4552 { 4553 struct vega10_hwmgr *data = hwmgr->backend; 4554 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range; 4555 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 4556 4557 if (!data->registry_data.disable_water_mark) { 4558 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 4559 data->water_marks_bitmap = WaterMarksExist; 4560 } 4561 4562 return 0; 4563 } 4564 4565 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 4566 { 4567 static const char *ppfeature_name[] = { 4568 "DPM_PREFETCHER", 4569 "GFXCLK_DPM", 4570 "UCLK_DPM", 4571 "SOCCLK_DPM", 4572 "UVD_DPM", 4573 "VCE_DPM", 4574 "ULV", 4575 "MP0CLK_DPM", 4576 "LINK_DPM", 4577 "DCEFCLK_DPM", 4578 "AVFS", 4579 "GFXCLK_DS", 4580 "SOCCLK_DS", 4581 "LCLK_DS", 4582 "PPT", 4583 "TDC", 4584 "THERMAL", 4585 "GFX_PER_CU_CG", 4586 "RM", 4587 "DCEFCLK_DS", 4588 "ACDC", 4589 "VR0HOT", 4590 "VR1HOT", 4591 "FW_CTF", 4592 "LED_DISPLAY", 4593 "FAN_CONTROL", 4594 "FAST_PPT", 4595 "DIDT", 4596 "ACG", 4597 "PCC_LIMIT"}; 4598 static const char *output_title[] = { 4599 "FEATURES", 4600 "BITMASK", 4601 "ENABLEMENT"}; 4602 uint64_t features_enabled; 4603 int i; 4604 int ret = 0; 4605 int size = 0; 4606 4607 phm_get_sysfs_buf(&buf, &size); 4608 4609 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); 4610 PP_ASSERT_WITH_CODE(!ret, 4611 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 4612 return ret); 4613 4614 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled); 4615 size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n", 4616 output_title[0], 4617 output_title[1], 4618 output_title[2]); 4619 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 4620 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n", 4621 ppfeature_name[i], 4622 1ULL << i, 4623 (features_enabled & (1ULL << i)) ? "Y" : "N"); 4624 } 4625 4626 return size; 4627 } 4628 4629 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 4630 { 4631 uint64_t features_enabled; 4632 uint64_t features_to_enable; 4633 uint64_t features_to_disable; 4634 int ret = 0; 4635 4636 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 4637 return -EINVAL; 4638 4639 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); 4640 if (ret) 4641 return ret; 4642 4643 features_to_disable = 4644 features_enabled & ~new_ppfeature_masks; 4645 features_to_enable = 4646 ~features_enabled & new_ppfeature_masks; 4647 4648 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 4649 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 4650 4651 if (features_to_disable) { 4652 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable); 4653 if (ret) 4654 return ret; 4655 } 4656 4657 if (features_to_enable) { 4658 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable); 4659 if (ret) 4660 return ret; 4661 } 4662 4663 return 0; 4664 } 4665 4666 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 4667 { 4668 struct amdgpu_device *adev = hwmgr->adev; 4669 4670 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 4671 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 4672 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 4673 } 4674 4675 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 4676 { 4677 struct amdgpu_device *adev = hwmgr->adev; 4678 4679 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 4680 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 4681 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 4682 } 4683 4684 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr, 4685 enum pp_clock_type type, char *buf, int *offset) 4686 { 4687 struct vega10_hwmgr *data = hwmgr->backend; 4688 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4689 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4690 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); 4691 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); 4692 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; 4693 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 4694 PPTable_t *pptable = &(data->smc_state_table.pp_table); 4695 4696 uint32_t i, now, count = 0; 4697 int ret = 0; 4698 4699 switch (type) { 4700 case PP_SCLK: 4701 if (data->registry_data.sclk_dpm_key_disabled) 4702 return -EOPNOTSUPP; 4703 4704 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); 4705 if (unlikely(ret != 0)) 4706 return ret; 4707 4708 if (hwmgr->pp_one_vf && 4709 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) 4710 count = 5; 4711 else 4712 count = sclk_table->count; 4713 for (i = 0; i < count; i++) 4714 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4715 i, sclk_table->dpm_levels[i].value / 100, 4716 (i == now) ? "*" : ""); 4717 break; 4718 case PP_MCLK: 4719 if (data->registry_data.mclk_dpm_key_disabled) 4720 return -EOPNOTSUPP; 4721 4722 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); 4723 if (unlikely(ret != 0)) 4724 return ret; 4725 4726 for (i = 0; i < mclk_table->count; i++) 4727 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4728 i, mclk_table->dpm_levels[i].value / 100, 4729 (i == now) ? "*" : ""); 4730 break; 4731 case PP_SOCCLK: 4732 if (data->registry_data.socclk_dpm_key_disabled) 4733 return -EOPNOTSUPP; 4734 4735 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); 4736 if (unlikely(ret != 0)) 4737 return ret; 4738 4739 for (i = 0; i < soc_table->count; i++) 4740 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4741 i, soc_table->dpm_levels[i].value / 100, 4742 (i == now) ? "*" : ""); 4743 break; 4744 case PP_DCEFCLK: 4745 if (data->registry_data.dcefclk_dpm_key_disabled) 4746 return -EOPNOTSUPP; 4747 4748 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 4749 PPSMC_MSG_GetClockFreqMHz, 4750 CLK_DCEFCLK, &now); 4751 if (unlikely(ret != 0)) 4752 return ret; 4753 4754 for (i = 0; i < dcef_table->count; i++) 4755 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4756 i, dcef_table->dpm_levels[i].value / 100, 4757 (dcef_table->dpm_levels[i].value / 100 == now) ? 4758 "*" : ""); 4759 break; 4760 case PP_PCIE: 4761 current_gen_speed = 4762 vega10_get_current_pcie_link_speed_level(hwmgr); 4763 current_lane_width = 4764 vega10_get_current_pcie_link_width_level(hwmgr); 4765 for (i = 0; i < NUM_LINK_LEVELS; i++) { 4766 gen_speed = pptable->PcieGenSpeed[i]; 4767 lane_width = pptable->PcieLaneCount[i]; 4768 4769 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i, 4770 (gen_speed == 0) ? "2.5GT/s," : 4771 (gen_speed == 1) ? "5.0GT/s," : 4772 (gen_speed == 2) ? "8.0GT/s," : 4773 (gen_speed == 3) ? "16.0GT/s," : "", 4774 (lane_width == 1) ? "x1" : 4775 (lane_width == 2) ? "x2" : 4776 (lane_width == 3) ? "x4" : 4777 (lane_width == 4) ? "x8" : 4778 (lane_width == 5) ? "x12" : 4779 (lane_width == 6) ? "x16" : "", 4780 (current_gen_speed == gen_speed) && 4781 (current_lane_width == lane_width) ? 4782 "*" : ""); 4783 } 4784 break; 4785 4786 case OD_SCLK: 4787 if (!hwmgr->od_enabled) 4788 return -EOPNOTSUPP; 4789 4790 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK"); 4791 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 4792 for (i = 0; i < podn_vdd_dep->count; i++) 4793 *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n", 4794 i, podn_vdd_dep->entries[i].clk / 100, 4795 podn_vdd_dep->entries[i].vddc); 4796 break; 4797 case OD_MCLK: 4798 if (!hwmgr->od_enabled) 4799 return -EOPNOTSUPP; 4800 4801 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK"); 4802 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 4803 for (i = 0; i < podn_vdd_dep->count; i++) 4804 *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n", 4805 i, podn_vdd_dep->entries[i].clk/100, 4806 podn_vdd_dep->entries[i].vddc); 4807 break; 4808 case OD_RANGE: 4809 if (!hwmgr->od_enabled) 4810 return -EOPNOTSUPP; 4811 4812 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 4813 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n", 4814 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, 4815 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4816 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n", 4817 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, 4818 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4819 *offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n", 4820 data->odn_dpm_table.min_vddc, 4821 data->odn_dpm_table.max_vddc); 4822 break; 4823 default: 4824 ret = -ENOENT; 4825 break; 4826 } 4827 return ret; 4828 } 4829 4830 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, 4831 enum pp_clock_type type, char *buf) 4832 { 4833 struct vega10_hwmgr *data = hwmgr->backend; 4834 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4835 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4836 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); 4837 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); 4838 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; 4839 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 4840 PPTable_t *pptable = &(data->smc_state_table.pp_table); 4841 4842 int i, ret, now, size = 0, count = 0; 4843 4844 switch (type) { 4845 case PP_SCLK: 4846 if (data->registry_data.sclk_dpm_key_disabled) 4847 break; 4848 4849 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); 4850 if (ret) 4851 break; 4852 4853 if (hwmgr->pp_one_vf && 4854 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) 4855 count = 5; 4856 else 4857 count = sclk_table->count; 4858 for (i = 0; i < count; i++) 4859 size += sprintf(buf + size, "%d: %uMhz %s\n", 4860 i, sclk_table->dpm_levels[i].value / 100, 4861 (i == now) ? "*" : ""); 4862 break; 4863 case PP_MCLK: 4864 if (data->registry_data.mclk_dpm_key_disabled) 4865 break; 4866 4867 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); 4868 if (ret) 4869 break; 4870 4871 for (i = 0; i < mclk_table->count; i++) 4872 size += sprintf(buf + size, "%d: %uMhz %s\n", 4873 i, mclk_table->dpm_levels[i].value / 100, 4874 (i == now) ? "*" : ""); 4875 break; 4876 case PP_SOCCLK: 4877 if (data->registry_data.socclk_dpm_key_disabled) 4878 break; 4879 4880 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); 4881 if (ret) 4882 break; 4883 4884 for (i = 0; i < soc_table->count; i++) 4885 size += sprintf(buf + size, "%d: %uMhz %s\n", 4886 i, soc_table->dpm_levels[i].value / 100, 4887 (i == now) ? "*" : ""); 4888 break; 4889 case PP_DCEFCLK: 4890 if (data->registry_data.dcefclk_dpm_key_disabled) 4891 break; 4892 4893 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 4894 PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now); 4895 if (ret) 4896 break; 4897 4898 for (i = 0; i < dcef_table->count; i++) 4899 size += sprintf(buf + size, "%d: %uMhz %s\n", 4900 i, dcef_table->dpm_levels[i].value / 100, 4901 (dcef_table->dpm_levels[i].value / 100 == now) ? 4902 "*" : ""); 4903 break; 4904 case PP_PCIE: 4905 current_gen_speed = 4906 vega10_get_current_pcie_link_speed_level(hwmgr); 4907 current_lane_width = 4908 vega10_get_current_pcie_link_width_level(hwmgr); 4909 for (i = 0; i < NUM_LINK_LEVELS; i++) { 4910 gen_speed = pptable->PcieGenSpeed[i]; 4911 lane_width = pptable->PcieLaneCount[i]; 4912 4913 size += sprintf(buf + size, "%d: %s %s %s\n", i, 4914 (gen_speed == 0) ? "2.5GT/s," : 4915 (gen_speed == 1) ? "5.0GT/s," : 4916 (gen_speed == 2) ? "8.0GT/s," : 4917 (gen_speed == 3) ? "16.0GT/s," : "", 4918 (lane_width == 1) ? "x1" : 4919 (lane_width == 2) ? "x2" : 4920 (lane_width == 3) ? "x4" : 4921 (lane_width == 4) ? "x8" : 4922 (lane_width == 5) ? "x12" : 4923 (lane_width == 6) ? "x16" : "", 4924 (current_gen_speed == gen_speed) && 4925 (current_lane_width == lane_width) ? 4926 "*" : ""); 4927 } 4928 break; 4929 4930 case OD_SCLK: 4931 if (hwmgr->od_enabled) { 4932 size += sprintf(buf + size, "%s:\n", "OD_SCLK"); 4933 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 4934 for (i = 0; i < podn_vdd_dep->count; i++) 4935 size += sprintf(buf + size, "%d: %10uMhz %10umV\n", 4936 i, podn_vdd_dep->entries[i].clk / 100, 4937 podn_vdd_dep->entries[i].vddc); 4938 } 4939 break; 4940 case OD_MCLK: 4941 if (hwmgr->od_enabled) { 4942 size += sprintf(buf + size, "%s:\n", "OD_MCLK"); 4943 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 4944 for (i = 0; i < podn_vdd_dep->count; i++) 4945 size += sprintf(buf + size, "%d: %10uMhz %10umV\n", 4946 i, podn_vdd_dep->entries[i].clk/100, 4947 podn_vdd_dep->entries[i].vddc); 4948 } 4949 break; 4950 case OD_RANGE: 4951 if (hwmgr->od_enabled) { 4952 size += sprintf(buf + size, "%s:\n", "OD_RANGE"); 4953 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", 4954 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, 4955 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4956 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", 4957 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, 4958 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4959 size += sprintf(buf + size, "VDDC: %7umV %11umV\n", 4960 data->odn_dpm_table.min_vddc, 4961 data->odn_dpm_table.max_vddc); 4962 } 4963 break; 4964 default: 4965 break; 4966 } 4967 return size; 4968 } 4969 4970 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 4971 { 4972 struct vega10_hwmgr *data = hwmgr->backend; 4973 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 4974 int result = 0; 4975 4976 if ((data->water_marks_bitmap & WaterMarksExist) && 4977 !(data->water_marks_bitmap & WaterMarksLoaded)) { 4978 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); 4979 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL); 4980 data->water_marks_bitmap |= WaterMarksLoaded; 4981 } 4982 4983 if (data->water_marks_bitmap & WaterMarksLoaded) { 4984 smum_send_msg_to_smc_with_parameter(hwmgr, 4985 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, 4986 NULL); 4987 } 4988 4989 return result; 4990 } 4991 4992 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 4993 { 4994 struct vega10_hwmgr *data = hwmgr->backend; 4995 4996 if (data->smu_features[GNLD_DPM_UVD].supported) { 4997 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 4998 enable, 4999 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 5000 "Attempt to Enable/Disable DPM UVD Failed!", 5001 return -1); 5002 data->smu_features[GNLD_DPM_UVD].enabled = enable; 5003 } 5004 return 0; 5005 } 5006 5007 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 5008 { 5009 struct vega10_hwmgr *data = hwmgr->backend; 5010 5011 data->vce_power_gated = bgate; 5012 vega10_enable_disable_vce_dpm(hwmgr, !bgate); 5013 } 5014 5015 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 5016 { 5017 struct vega10_hwmgr *data = hwmgr->backend; 5018 5019 data->uvd_power_gated = bgate; 5020 vega10_enable_disable_uvd_dpm(hwmgr, !bgate); 5021 } 5022 5023 static inline bool vega10_are_power_levels_equal( 5024 const struct vega10_performance_level *pl1, 5025 const struct vega10_performance_level *pl2) 5026 { 5027 return ((pl1->soc_clock == pl2->soc_clock) && 5028 (pl1->gfx_clock == pl2->gfx_clock) && 5029 (pl1->mem_clock == pl2->mem_clock)); 5030 } 5031 5032 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr, 5033 const struct pp_hw_power_state *pstate1, 5034 const struct pp_hw_power_state *pstate2, bool *equal) 5035 { 5036 const struct vega10_power_state *vega10_psa; 5037 const struct vega10_power_state *vega10_psb; 5038 int i; 5039 5040 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 5041 return -EINVAL; 5042 5043 vega10_psa = cast_const_phw_vega10_power_state(pstate1); 5044 vega10_psb = cast_const_phw_vega10_power_state(pstate2); 5045 if (vega10_psa == NULL || vega10_psb == NULL) 5046 return -EINVAL; 5047 5048 /* If the two states don't even have the same number of performance levels 5049 * they cannot be the same state. 5050 */ 5051 if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) { 5052 *equal = false; 5053 return 0; 5054 } 5055 5056 for (i = 0; i < vega10_psa->performance_level_count; i++) { 5057 if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]), 5058 &(vega10_psb->performance_levels[i]))) { 5059 /* If we have found even one performance level pair 5060 * that is different the states are different. 5061 */ 5062 *equal = false; 5063 return 0; 5064 } 5065 } 5066 5067 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 5068 *equal = ((vega10_psa->uvd_clks.vclk == vega10_psb->uvd_clks.vclk) && 5069 (vega10_psa->uvd_clks.dclk == vega10_psb->uvd_clks.dclk)); 5070 *equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) && 5071 (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk)); 5072 *equal &= (vega10_psa->sclk_threshold == vega10_psb->sclk_threshold); 5073 5074 return 0; 5075 } 5076 5077 static bool 5078 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 5079 { 5080 struct vega10_hwmgr *data = hwmgr->backend; 5081 bool is_update_required = false; 5082 5083 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 5084 is_update_required = true; 5085 5086 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) { 5087 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) 5088 is_update_required = true; 5089 } 5090 5091 return is_update_required; 5092 } 5093 5094 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 5095 { 5096 int tmp_result, result = 0; 5097 5098 if (!hwmgr->not_vf) 5099 return 0; 5100 5101 if (PP_CAP(PHM_PlatformCaps_ThermalController)) 5102 vega10_disable_thermal_protection(hwmgr); 5103 5104 tmp_result = vega10_disable_power_containment(hwmgr); 5105 PP_ASSERT_WITH_CODE((tmp_result == 0), 5106 "Failed to disable power containment!", result = tmp_result); 5107 5108 tmp_result = vega10_disable_didt_config(hwmgr); 5109 PP_ASSERT_WITH_CODE((tmp_result == 0), 5110 "Failed to disable didt config!", result = tmp_result); 5111 5112 tmp_result = vega10_avfs_enable(hwmgr, false); 5113 PP_ASSERT_WITH_CODE((tmp_result == 0), 5114 "Failed to disable AVFS!", result = tmp_result); 5115 5116 tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); 5117 PP_ASSERT_WITH_CODE((tmp_result == 0), 5118 "Failed to stop DPM!", result = tmp_result); 5119 5120 tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); 5121 PP_ASSERT_WITH_CODE((tmp_result == 0), 5122 "Failed to disable deep sleep!", result = tmp_result); 5123 5124 tmp_result = vega10_disable_ulv(hwmgr); 5125 PP_ASSERT_WITH_CODE((tmp_result == 0), 5126 "Failed to disable ulv!", result = tmp_result); 5127 5128 tmp_result = vega10_acg_disable(hwmgr); 5129 PP_ASSERT_WITH_CODE((tmp_result == 0), 5130 "Failed to disable acg!", result = tmp_result); 5131 5132 vega10_enable_disable_PCC_limit_feature(hwmgr, false); 5133 return result; 5134 } 5135 5136 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) 5137 { 5138 struct vega10_hwmgr *data = hwmgr->backend; 5139 int result; 5140 5141 result = vega10_disable_dpm_tasks(hwmgr); 5142 PP_ASSERT_WITH_CODE((0 == result), 5143 "[disable_dpm_tasks] Failed to disable DPM!", 5144 ); 5145 data->water_marks_bitmap &= ~(WaterMarksLoaded); 5146 5147 return result; 5148 } 5149 5150 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) 5151 { 5152 struct vega10_hwmgr *data = hwmgr->backend; 5153 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 5154 struct vega10_single_dpm_table *golden_sclk_table = 5155 &(data->golden_dpm_table.gfx_table); 5156 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 5157 int golden_value = golden_sclk_table->dpm_levels 5158 [golden_sclk_table->count - 1].value; 5159 5160 value -= golden_value; 5161 value = DIV_ROUND_UP(value * 100, golden_value); 5162 5163 return value; 5164 } 5165 5166 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5167 { 5168 struct vega10_hwmgr *data = hwmgr->backend; 5169 struct vega10_single_dpm_table *golden_sclk_table = 5170 &(data->golden_dpm_table.gfx_table); 5171 struct pp_power_state *ps; 5172 struct vega10_power_state *vega10_ps; 5173 5174 ps = hwmgr->request_ps; 5175 5176 if (ps == NULL) 5177 return -EINVAL; 5178 5179 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5180 if (vega10_ps == NULL) 5181 return -EINVAL; 5182 5183 vega10_ps->performance_levels 5184 [vega10_ps->performance_level_count - 1].gfx_clock = 5185 golden_sclk_table->dpm_levels 5186 [golden_sclk_table->count - 1].value * 5187 value / 100 + 5188 golden_sclk_table->dpm_levels 5189 [golden_sclk_table->count - 1].value; 5190 5191 if (vega10_ps->performance_levels 5192 [vega10_ps->performance_level_count - 1].gfx_clock > 5193 hwmgr->platform_descriptor.overdriveLimit.engineClock) { 5194 vega10_ps->performance_levels 5195 [vega10_ps->performance_level_count - 1].gfx_clock = 5196 hwmgr->platform_descriptor.overdriveLimit.engineClock; 5197 pr_warn("max sclk supported by vbios is %d\n", 5198 hwmgr->platform_descriptor.overdriveLimit.engineClock); 5199 } 5200 return 0; 5201 } 5202 5203 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) 5204 { 5205 struct vega10_hwmgr *data = hwmgr->backend; 5206 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 5207 struct vega10_single_dpm_table *golden_mclk_table = 5208 &(data->golden_dpm_table.mem_table); 5209 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 5210 int golden_value = golden_mclk_table->dpm_levels 5211 [golden_mclk_table->count - 1].value; 5212 5213 value -= golden_value; 5214 value = DIV_ROUND_UP(value * 100, golden_value); 5215 5216 return value; 5217 } 5218 5219 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5220 { 5221 struct vega10_hwmgr *data = hwmgr->backend; 5222 struct vega10_single_dpm_table *golden_mclk_table = 5223 &(data->golden_dpm_table.mem_table); 5224 struct pp_power_state *ps; 5225 struct vega10_power_state *vega10_ps; 5226 5227 ps = hwmgr->request_ps; 5228 5229 if (ps == NULL) 5230 return -EINVAL; 5231 5232 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5233 if (vega10_ps == NULL) 5234 return -EINVAL; 5235 5236 vega10_ps->performance_levels 5237 [vega10_ps->performance_level_count - 1].mem_clock = 5238 golden_mclk_table->dpm_levels 5239 [golden_mclk_table->count - 1].value * 5240 value / 100 + 5241 golden_mclk_table->dpm_levels 5242 [golden_mclk_table->count - 1].value; 5243 5244 if (vega10_ps->performance_levels 5245 [vega10_ps->performance_level_count - 1].mem_clock > 5246 hwmgr->platform_descriptor.overdriveLimit.memoryClock) { 5247 vega10_ps->performance_levels 5248 [vega10_ps->performance_level_count - 1].mem_clock = 5249 hwmgr->platform_descriptor.overdriveLimit.memoryClock; 5250 pr_warn("max mclk supported by vbios is %d\n", 5251 hwmgr->platform_descriptor.overdriveLimit.memoryClock); 5252 } 5253 5254 return 0; 5255 } 5256 5257 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 5258 uint32_t virtual_addr_low, 5259 uint32_t virtual_addr_hi, 5260 uint32_t mc_addr_low, 5261 uint32_t mc_addr_hi, 5262 uint32_t size) 5263 { 5264 smum_send_msg_to_smc_with_parameter(hwmgr, 5265 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 5266 virtual_addr_hi, 5267 NULL); 5268 smum_send_msg_to_smc_with_parameter(hwmgr, 5269 PPSMC_MSG_SetSystemVirtualDramAddrLow, 5270 virtual_addr_low, 5271 NULL); 5272 smum_send_msg_to_smc_with_parameter(hwmgr, 5273 PPSMC_MSG_DramLogSetDramAddrHigh, 5274 mc_addr_hi, 5275 NULL); 5276 5277 smum_send_msg_to_smc_with_parameter(hwmgr, 5278 PPSMC_MSG_DramLogSetDramAddrLow, 5279 mc_addr_low, 5280 NULL); 5281 5282 smum_send_msg_to_smc_with_parameter(hwmgr, 5283 PPSMC_MSG_DramLogSetDramSize, 5284 size, 5285 NULL); 5286 return 0; 5287 } 5288 5289 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 5290 struct PP_TemperatureRange *thermal_data) 5291 { 5292 struct vega10_hwmgr *data = hwmgr->backend; 5293 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 5294 struct phm_ppt_v2_information *pp_table_info = 5295 (struct phm_ppt_v2_information *)(hwmgr->pptable); 5296 struct phm_tdp_table *tdp_table = pp_table_info->tdp_table; 5297 5298 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 5299 5300 thermal_data->max = pp_table->TedgeLimit * 5301 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5302 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 5303 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5304 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 5305 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5306 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 5307 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5308 thermal_data->mem_crit_max = pp_table->ThbmLimit * 5309 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5310 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 5311 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5312 5313 if (tdp_table->usSoftwareShutdownTemp > pp_table->ThotspotLimit && 5314 tdp_table->usSoftwareShutdownTemp < VEGA10_THERMAL_MAXIMUM_ALERT_TEMP) 5315 thermal_data->sw_ctf_threshold = tdp_table->usSoftwareShutdownTemp; 5316 else 5317 thermal_data->sw_ctf_threshold = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP; 5318 thermal_data->sw_ctf_threshold *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5319 5320 return 0; 5321 } 5322 5323 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 5324 { 5325 struct vega10_hwmgr *data = hwmgr->backend; 5326 uint32_t i, size = 0; 5327 static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,}, 5328 {70, 60, 1, 3,}, 5329 {90, 60, 0, 0,}, 5330 {70, 60, 0, 0,}, 5331 {70, 90, 0, 0,}, 5332 {30, 60, 0, 6,}, 5333 }; 5334 static const char *title[6] = {"NUM", 5335 "MODE_NAME", 5336 "BUSY_SET_POINT", 5337 "FPS", 5338 "USE_RLC_BUSY", 5339 "MIN_ACTIVE_LEVEL"}; 5340 5341 if (!buf) 5342 return -EINVAL; 5343 5344 phm_get_sysfs_buf(&buf, &size); 5345 5346 size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0], 5347 title[1], title[2], title[3], title[4], title[5]); 5348 5349 for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++) 5350 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", 5351 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 5352 profile_mode_setting[i][0], profile_mode_setting[i][1], 5353 profile_mode_setting[i][2], profile_mode_setting[i][3]); 5354 5355 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i, 5356 amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 5357 data->custom_profile_mode[0], data->custom_profile_mode[1], 5358 data->custom_profile_mode[2], data->custom_profile_mode[3]); 5359 return size; 5360 } 5361 5362 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr) 5363 { 5364 struct amdgpu_device *adev = hwmgr->adev; 5365 5366 return (adev->pdev->device == 0x6860); 5367 } 5368 5369 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 5370 { 5371 struct vega10_hwmgr *data = hwmgr->backend; 5372 uint8_t busy_set_point; 5373 uint8_t FPS; 5374 uint8_t use_rlc_busy; 5375 uint8_t min_active_level; 5376 uint32_t power_profile_mode = input[size]; 5377 5378 if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 5379 if (size != 0 && size != 4) 5380 return -EINVAL; 5381 5382 /* If size = 0 and the CUSTOM profile has been set already 5383 * then just apply the profile. The copy stored in the hwmgr 5384 * is zeroed out on init 5385 */ 5386 if (size == 0) { 5387 if (data->custom_profile_mode[0] != 0) 5388 goto out; 5389 else 5390 return -EINVAL; 5391 } 5392 5393 data->custom_profile_mode[0] = busy_set_point = input[0]; 5394 data->custom_profile_mode[1] = FPS = input[1]; 5395 data->custom_profile_mode[2] = use_rlc_busy = input[2]; 5396 data->custom_profile_mode[3] = min_active_level = input[3]; 5397 smum_send_msg_to_smc_with_parameter(hwmgr, 5398 PPSMC_MSG_SetCustomGfxDpmParameters, 5399 busy_set_point | FPS<<8 | 5400 use_rlc_busy << 16 | min_active_level<<24, 5401 NULL); 5402 } 5403 5404 out: 5405 if (vega10_get_power_profile_mode_quirks(hwmgr)) 5406 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 5407 1 << power_profile_mode, 5408 NULL); 5409 else 5410 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 5411 (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), 5412 NULL); 5413 5414 hwmgr->power_profile_mode = power_profile_mode; 5415 5416 return 0; 5417 } 5418 5419 5420 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, 5421 enum PP_OD_DPM_TABLE_COMMAND type, 5422 uint32_t clk, 5423 uint32_t voltage) 5424 { 5425 struct vega10_hwmgr *data = hwmgr->backend; 5426 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 5427 struct vega10_single_dpm_table *golden_table; 5428 5429 if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) { 5430 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc); 5431 return false; 5432 } 5433 5434 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5435 golden_table = &(data->golden_dpm_table.gfx_table); 5436 if (golden_table->dpm_levels[0].value > clk || 5437 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { 5438 pr_info("OD engine clock is out of range [%d - %d] MHz\n", 5439 golden_table->dpm_levels[0].value/100, 5440 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5441 return false; 5442 } 5443 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5444 golden_table = &(data->golden_dpm_table.mem_table); 5445 if (golden_table->dpm_levels[0].value > clk || 5446 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { 5447 pr_info("OD memory clock is out of range [%d - %d] MHz\n", 5448 golden_table->dpm_levels[0].value/100, 5449 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5450 return false; 5451 } 5452 } else { 5453 return false; 5454 } 5455 5456 return true; 5457 } 5458 5459 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr) 5460 { 5461 struct vega10_hwmgr *data = hwmgr->backend; 5462 struct pp_power_state *ps = hwmgr->request_ps; 5463 struct vega10_power_state *vega10_ps; 5464 struct vega10_single_dpm_table *gfx_dpm_table = 5465 &data->dpm_table.gfx_table; 5466 struct vega10_single_dpm_table *soc_dpm_table = 5467 &data->dpm_table.soc_table; 5468 struct vega10_single_dpm_table *mem_dpm_table = 5469 &data->dpm_table.mem_table; 5470 int max_level; 5471 5472 if (!ps) 5473 return; 5474 5475 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5476 if (vega10_ps == NULL) 5477 return; 5478 5479 max_level = vega10_ps->performance_level_count - 1; 5480 5481 if (vega10_ps->performance_levels[max_level].gfx_clock != 5482 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) 5483 vega10_ps->performance_levels[max_level].gfx_clock = 5484 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; 5485 5486 if (vega10_ps->performance_levels[max_level].soc_clock != 5487 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) 5488 vega10_ps->performance_levels[max_level].soc_clock = 5489 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; 5490 5491 if (vega10_ps->performance_levels[max_level].mem_clock != 5492 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) 5493 vega10_ps->performance_levels[max_level].mem_clock = 5494 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; 5495 5496 if (!hwmgr->ps) 5497 return; 5498 5499 ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1)); 5500 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5501 if (vega10_ps == NULL) 5502 return; 5503 5504 max_level = vega10_ps->performance_level_count - 1; 5505 5506 if (vega10_ps->performance_levels[max_level].gfx_clock != 5507 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) 5508 vega10_ps->performance_levels[max_level].gfx_clock = 5509 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; 5510 5511 if (vega10_ps->performance_levels[max_level].soc_clock != 5512 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) 5513 vega10_ps->performance_levels[max_level].soc_clock = 5514 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; 5515 5516 if (vega10_ps->performance_levels[max_level].mem_clock != 5517 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) 5518 vega10_ps->performance_levels[max_level].mem_clock = 5519 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; 5520 } 5521 5522 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr, 5523 enum PP_OD_DPM_TABLE_COMMAND type) 5524 { 5525 struct vega10_hwmgr *data = hwmgr->backend; 5526 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 5527 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk; 5528 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; 5529 5530 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk = 5531 &data->odn_dpm_table.vdd_dep_on_socclk; 5532 struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table; 5533 5534 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep; 5535 uint8_t i, j; 5536 5537 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5538 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 5539 for (i = 0; i < podn_vdd_dep->count; i++) 5540 od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc; 5541 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5542 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 5543 for (i = 0; i < dpm_table->count; i++) { 5544 for (j = 0; j < od_vddc_lookup_table->count; j++) { 5545 if (od_vddc_lookup_table->entries[j].us_vdd > 5546 podn_vdd_dep->entries[i].vddc) 5547 break; 5548 } 5549 if (j == od_vddc_lookup_table->count) { 5550 j = od_vddc_lookup_table->count - 1; 5551 od_vddc_lookup_table->entries[j].us_vdd = 5552 podn_vdd_dep->entries[i].vddc; 5553 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 5554 } 5555 podn_vdd_dep->entries[i].vddInd = j; 5556 } 5557 dpm_table = &data->dpm_table.soc_table; 5558 for (i = 0; i < dep_table->count; i++) { 5559 if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd && 5560 dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) { 5561 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5562 for (; (i < dep_table->count) && 5563 (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) { 5564 podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk; 5565 dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk; 5566 } 5567 break; 5568 } else { 5569 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk; 5570 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc; 5571 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd; 5572 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk; 5573 } 5574 } 5575 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk < 5576 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) { 5577 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5578 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = 5579 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; 5580 dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = 5581 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; 5582 } 5583 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd < 5584 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) { 5585 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5586 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = 5587 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd; 5588 } 5589 } 5590 vega10_odn_update_power_state(hwmgr); 5591 } 5592 5593 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 5594 enum PP_OD_DPM_TABLE_COMMAND type, 5595 long *input, uint32_t size) 5596 { 5597 struct vega10_hwmgr *data = hwmgr->backend; 5598 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table; 5599 struct vega10_single_dpm_table *dpm_table; 5600 5601 uint32_t input_clk; 5602 uint32_t input_vol; 5603 uint32_t input_level; 5604 uint32_t i; 5605 5606 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 5607 return -EINVAL); 5608 5609 if (!hwmgr->od_enabled) { 5610 pr_info("OverDrive feature not enabled\n"); 5611 return -EINVAL; 5612 } 5613 5614 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { 5615 dpm_table = &data->dpm_table.gfx_table; 5616 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk; 5617 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 5618 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { 5619 dpm_table = &data->dpm_table.mem_table; 5620 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk; 5621 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 5622 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { 5623 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table)); 5624 vega10_odn_initial_default_setting(hwmgr); 5625 vega10_odn_update_power_state(hwmgr); 5626 /* force to update all clock tables */ 5627 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK | 5628 DPMTABLE_UPDATE_MCLK | 5629 DPMTABLE_UPDATE_SOCCLK; 5630 return 0; 5631 } else if (PP_OD_COMMIT_DPM_TABLE == type) { 5632 vega10_check_dpm_table_updated(hwmgr); 5633 return 0; 5634 } else { 5635 return -EINVAL; 5636 } 5637 5638 for (i = 0; i < size; i += 3) { 5639 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) { 5640 pr_info("invalid clock voltage input\n"); 5641 return 0; 5642 } 5643 input_level = input[i]; 5644 input_clk = input[i+1] * 100; 5645 input_vol = input[i+2]; 5646 5647 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { 5648 dpm_table->dpm_levels[input_level].value = input_clk; 5649 podn_vdd_dep_table->entries[input_level].clk = input_clk; 5650 podn_vdd_dep_table->entries[input_level].vddc = input_vol; 5651 } else { 5652 return -EINVAL; 5653 } 5654 } 5655 vega10_odn_update_soc_table(hwmgr, type); 5656 return 0; 5657 } 5658 5659 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr, 5660 enum pp_mp1_state mp1_state) 5661 { 5662 uint16_t msg; 5663 int ret; 5664 5665 switch (mp1_state) { 5666 case PP_MP1_STATE_UNLOAD: 5667 msg = PPSMC_MSG_PrepareMp1ForUnload; 5668 break; 5669 case PP_MP1_STATE_SHUTDOWN: 5670 case PP_MP1_STATE_RESET: 5671 case PP_MP1_STATE_NONE: 5672 default: 5673 return 0; 5674 } 5675 5676 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 5677 "[PrepareMp1] Failed!", 5678 return ret); 5679 5680 return 0; 5681 } 5682 5683 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 5684 PHM_PerformanceLevelDesignation designation, uint32_t index, 5685 PHM_PerformanceLevel *level) 5686 { 5687 const struct vega10_power_state *vega10_ps; 5688 uint32_t i; 5689 5690 if (level == NULL || hwmgr == NULL || state == NULL) 5691 return -EINVAL; 5692 5693 vega10_ps = cast_const_phw_vega10_power_state(state); 5694 if (vega10_ps == NULL) 5695 return -EINVAL; 5696 5697 i = index > vega10_ps->performance_level_count - 1 ? 5698 vega10_ps->performance_level_count - 1 : index; 5699 5700 level->coreClock = vega10_ps->performance_levels[i].gfx_clock; 5701 level->memory_clock = vega10_ps->performance_levels[i].mem_clock; 5702 5703 return 0; 5704 } 5705 5706 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable) 5707 { 5708 struct vega10_hwmgr *data = hwmgr->backend; 5709 uint32_t feature_mask = 0; 5710 5711 if (disable) { 5712 feature_mask |= data->smu_features[GNLD_ULV].enabled ? 5713 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; 5714 feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ? 5715 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; 5716 feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ? 5717 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; 5718 feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ? 5719 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; 5720 feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ? 5721 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; 5722 } else { 5723 feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ? 5724 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; 5725 feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ? 5726 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; 5727 feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ? 5728 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; 5729 feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ? 5730 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; 5731 feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ? 5732 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; 5733 } 5734 5735 if (feature_mask) 5736 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 5737 !disable, feature_mask), 5738 "enable/disable power features for compute performance Failed!", 5739 return -EINVAL); 5740 5741 if (disable) { 5742 data->smu_features[GNLD_ULV].enabled = false; 5743 data->smu_features[GNLD_DS_GFXCLK].enabled = false; 5744 data->smu_features[GNLD_DS_SOCCLK].enabled = false; 5745 data->smu_features[GNLD_DS_LCLK].enabled = false; 5746 data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 5747 } else { 5748 data->smu_features[GNLD_ULV].enabled = true; 5749 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 5750 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 5751 data->smu_features[GNLD_DS_LCLK].enabled = true; 5752 data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 5753 } 5754 5755 return 0; 5756 5757 } 5758 5759 static const struct pp_hwmgr_func vega10_hwmgr_funcs = { 5760 .backend_init = vega10_hwmgr_backend_init, 5761 .backend_fini = vega10_hwmgr_backend_fini, 5762 .asic_setup = vega10_setup_asic_task, 5763 .dynamic_state_management_enable = vega10_enable_dpm_tasks, 5764 .dynamic_state_management_disable = vega10_disable_dpm_tasks, 5765 .get_num_of_pp_table_entries = 5766 vega10_get_number_of_powerplay_table_entries, 5767 .get_power_state_size = vega10_get_power_state_size, 5768 .get_pp_table_entry = vega10_get_pp_table_entry, 5769 .patch_boot_state = vega10_patch_boot_state, 5770 .apply_state_adjust_rules = vega10_apply_state_adjust_rules, 5771 .power_state_set = vega10_set_power_state_tasks, 5772 .get_sclk = vega10_dpm_get_sclk, 5773 .get_mclk = vega10_dpm_get_mclk, 5774 .notify_smc_display_config_after_ps_adjustment = 5775 vega10_notify_smc_display_config_after_ps_adjustment, 5776 .force_dpm_level = vega10_dpm_force_dpm_level, 5777 .stop_thermal_controller = vega10_thermal_stop_thermal_controller, 5778 .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info, 5779 .get_fan_speed_pwm = vega10_fan_ctrl_get_fan_speed_pwm, 5780 .set_fan_speed_pwm = vega10_fan_ctrl_set_fan_speed_pwm, 5781 .reset_fan_speed_to_default = 5782 vega10_fan_ctrl_reset_fan_speed_to_default, 5783 .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm, 5784 .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm, 5785 .uninitialize_thermal_controller = 5786 vega10_thermal_ctrl_uninitialize_thermal_controller, 5787 .set_fan_control_mode = vega10_set_fan_control_mode, 5788 .get_fan_control_mode = vega10_get_fan_control_mode, 5789 .read_sensor = vega10_read_sensor, 5790 .get_dal_power_level = vega10_get_dal_power_level, 5791 .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency, 5792 .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage, 5793 .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges, 5794 .display_clock_voltage_request = vega10_display_clock_voltage_request, 5795 .force_clock_level = vega10_force_clock_level, 5796 .emit_clock_levels = vega10_emit_clock_levels, 5797 .print_clock_levels = vega10_print_clock_levels, 5798 .display_config_changed = vega10_display_configuration_changed_task, 5799 .powergate_uvd = vega10_power_gate_uvd, 5800 .powergate_vce = vega10_power_gate_vce, 5801 .check_states_equal = vega10_check_states_equal, 5802 .check_smc_update_required_for_display_configuration = 5803 vega10_check_smc_update_required_for_display_configuration, 5804 .power_off_asic = vega10_power_off_asic, 5805 .disable_smc_firmware_ctf = vega10_thermal_disable_alert, 5806 .get_sclk_od = vega10_get_sclk_od, 5807 .set_sclk_od = vega10_set_sclk_od, 5808 .get_mclk_od = vega10_get_mclk_od, 5809 .set_mclk_od = vega10_set_mclk_od, 5810 .avfs_control = vega10_avfs_enable, 5811 .notify_cac_buffer_info = vega10_notify_cac_buffer_info, 5812 .get_thermal_temperature_range = vega10_get_thermal_temperature_range, 5813 .register_irq_handlers = smu9_register_irq_handlers, 5814 .start_thermal_controller = vega10_start_thermal_controller, 5815 .get_power_profile_mode = vega10_get_power_profile_mode, 5816 .set_power_profile_mode = vega10_set_power_profile_mode, 5817 .set_power_limit = vega10_set_power_limit, 5818 .odn_edit_dpm_table = vega10_odn_edit_dpm_table, 5819 .get_performance_level = vega10_get_performance_level, 5820 .get_bamaco_support = smu9_get_bamaco_support, 5821 .get_asic_baco_state = smu9_baco_get_state, 5822 .set_asic_baco_state = vega10_baco_set_state, 5823 .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost, 5824 .get_ppfeature_status = vega10_get_ppfeature_status, 5825 .set_ppfeature_status = vega10_set_ppfeature_status, 5826 .set_mp1_state = vega10_set_mp1_state, 5827 .disable_power_features_for_compute_performance = 5828 vega10_disable_power_features_for_compute_performance, 5829 }; 5830 5831 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) 5832 { 5833 struct amdgpu_device *adev = hwmgr->adev; 5834 5835 hwmgr->hwmgr_func = &vega10_hwmgr_funcs; 5836 hwmgr->pptable_func = &vega10_pptable_funcs; 5837 if (amdgpu_passthrough(adev)) 5838 return vega10_baco_set_cap(hwmgr); 5839 5840 return 0; 5841 } 5842