1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _SMU7_HWMGR_H 25 #define _SMU7_HWMGR_H 26 27 #include "hwmgr.h" 28 #include "ppatomctrl.h" 29 30 #define SMU7_MAX_HARDWARE_POWERLEVELS 2 31 32 #define SMU7_VOLTAGE_CONTROL_NONE 0x0 33 #define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1 34 #define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2 35 #define SMU7_VOLTAGE_CONTROL_MERGED 0x3 36 37 enum gpu_pt_config_reg_type { 38 GPU_CONFIGREG_MMR = 0, 39 GPU_CONFIGREG_SMC_IND, 40 GPU_CONFIGREG_DIDT_IND, 41 GPU_CONFIGREG_GC_CAC_IND, 42 GPU_CONFIGREG_CACHE, 43 GPU_CONFIGREG_MAX 44 }; 45 46 struct gpu_pt_config_reg { 47 uint32_t offset; 48 uint32_t mask; 49 uint32_t shift; 50 uint32_t value; 51 enum gpu_pt_config_reg_type type; 52 }; 53 54 struct smu7_performance_level { 55 uint32_t memory_clock; 56 uint32_t engine_clock; 57 uint16_t pcie_gen; 58 uint16_t pcie_lane; 59 }; 60 61 struct smu7_thermal_temperature_setting { 62 long temperature_low; 63 long temperature_high; 64 long temperature_shutdown; 65 }; 66 67 struct smu7_uvd_clocks { 68 uint32_t vclk; 69 uint32_t dclk; 70 }; 71 72 struct smu7_vce_clocks { 73 uint32_t evclk; 74 uint32_t ecclk; 75 }; 76 77 struct smu7_power_state { 78 uint32_t magic; 79 struct smu7_uvd_clocks uvd_clks; 80 struct smu7_vce_clocks vce_clks; 81 uint32_t sam_clk; 82 uint16_t performance_level_count; 83 bool dc_compatible; 84 uint32_t sclk_threshold; 85 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; 86 }; 87 88 struct smu7_dpm_level { 89 bool enabled; 90 uint32_t value; 91 uint32_t param1; 92 }; 93 94 #define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5 95 #define MAX_REGULAR_DPM_NUMBER 8 96 #define SMU7_MINIMUM_ENGINE_CLOCK 2500 97 98 struct smu7_single_dpm_table { 99 uint32_t count; 100 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 101 }; 102 103 struct smu7_dpm_table { 104 struct smu7_single_dpm_table sclk_table; 105 struct smu7_single_dpm_table mclk_table; 106 struct smu7_single_dpm_table pcie_speed_table; 107 struct smu7_single_dpm_table vddc_table; 108 struct smu7_single_dpm_table vddci_table; 109 struct smu7_single_dpm_table mvdd_table; 110 }; 111 112 struct smu7_clock_registers { 113 uint32_t vCG_SPLL_FUNC_CNTL; 114 uint32_t vCG_SPLL_FUNC_CNTL_2; 115 uint32_t vCG_SPLL_FUNC_CNTL_3; 116 uint32_t vCG_SPLL_FUNC_CNTL_4; 117 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 118 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 119 uint32_t vDLL_CNTL; 120 uint32_t vMCLK_PWRMGT_CNTL; 121 uint32_t vMPLL_AD_FUNC_CNTL; 122 uint32_t vMPLL_DQ_FUNC_CNTL; 123 uint32_t vMPLL_FUNC_CNTL; 124 uint32_t vMPLL_FUNC_CNTL_1; 125 uint32_t vMPLL_FUNC_CNTL_2; 126 uint32_t vMPLL_SS1; 127 uint32_t vMPLL_SS2; 128 }; 129 130 #define DISABLE_MC_LOADMICROCODE 1 131 #define DISABLE_MC_CFGPROGRAMMING 2 132 133 struct smu7_voltage_smio_registers { 134 uint32_t vS0_VID_LOWER_SMIO_CNTL; 135 }; 136 137 #define SMU7_MAX_LEAKAGE_COUNT 8 138 139 struct smu7_leakage_voltage { 140 uint16_t count; 141 uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT]; 142 uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT]; 143 }; 144 145 struct smu7_vbios_boot_state { 146 uint16_t mvdd_bootup_value; 147 uint16_t vddc_bootup_value; 148 uint16_t vddci_bootup_value; 149 uint16_t vddgfx_bootup_value; 150 uint32_t sclk_bootup_value; 151 uint32_t mclk_bootup_value; 152 uint16_t pcie_gen_bootup_value; 153 uint16_t pcie_lane_bootup_value; 154 }; 155 156 struct smu7_display_timing { 157 uint32_t min_clock_in_sr; 158 uint32_t num_existing_displays; 159 uint32_t vrefresh; 160 }; 161 162 struct smu7_dpmlevel_enable_mask { 163 uint32_t uvd_dpm_enable_mask; 164 uint32_t vce_dpm_enable_mask; 165 uint32_t acp_dpm_enable_mask; 166 uint32_t samu_dpm_enable_mask; 167 uint32_t sclk_dpm_enable_mask; 168 uint32_t mclk_dpm_enable_mask; 169 uint32_t pcie_dpm_enable_mask; 170 }; 171 172 struct smu7_pcie_perf_range { 173 uint16_t max; 174 uint16_t min; 175 }; 176 177 struct smu7_odn_clock_voltage_dependency_table { 178 uint32_t count; 179 phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 180 }; 181 182 struct smu7_odn_dpm_table { 183 struct phm_odn_clock_levels odn_core_clock_dpm_levels; 184 struct phm_odn_clock_levels odn_memory_clock_dpm_levels; 185 struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; 186 struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; 187 uint32_t odn_mclk_min_limit; 188 uint32_t min_vddc; 189 uint32_t max_vddc; 190 }; 191 192 struct profile_mode_setting { 193 uint8_t bupdate_sclk; 194 uint8_t sclk_up_hyst; 195 uint8_t sclk_down_hyst; 196 uint16_t sclk_activity; 197 uint8_t bupdate_mclk; 198 uint8_t mclk_up_hyst; 199 uint8_t mclk_down_hyst; 200 uint16_t mclk_activity; 201 }; 202 203 struct smu7_mclk_latency_entries { 204 uint32_t frequency; 205 uint32_t latency; 206 }; 207 208 struct smu7_mclk_latency_table { 209 uint32_t count; 210 struct smu7_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 211 }; 212 213 struct smu7_hwmgr { 214 struct smu7_dpm_table dpm_table; 215 struct smu7_dpm_table golden_dpm_table; 216 struct smu7_odn_dpm_table odn_dpm_table; 217 struct smu7_mclk_latency_table mclk_latency_table; 218 219 uint32_t voting_rights_clients[8]; 220 uint32_t static_screen_threshold_unit; 221 uint32_t static_screen_threshold; 222 uint32_t voltage_control; 223 uint32_t vdd_gfx_control; 224 uint32_t vddc_vddgfx_delta; 225 uint32_t active_auto_throttle_sources; 226 227 struct smu7_clock_registers clock_registers; 228 229 bool is_memory_gddr5; 230 uint16_t acpi_vddc; 231 bool pspp_notify_required; 232 uint16_t force_pcie_gen; 233 uint16_t acpi_pcie_gen; 234 uint32_t pcie_gen_cap; 235 uint32_t pcie_lane_cap; 236 uint32_t pcie_spc_cap; 237 struct smu7_leakage_voltage vddc_leakage; 238 struct smu7_leakage_voltage vddci_leakage; 239 struct smu7_leakage_voltage vddcgfx_leakage; 240 241 uint32_t mvdd_control; 242 uint32_t vddc_mask_low; 243 uint32_t mvdd_mask_low; 244 uint16_t max_vddc_in_pptable; 245 uint16_t min_vddc_in_pptable; 246 uint16_t max_vddci_in_pptable; 247 uint16_t min_vddci_in_pptable; 248 bool is_uvd_enabled; 249 struct smu7_vbios_boot_state vbios_boot_state; 250 251 bool pcie_performance_request; 252 bool battery_state; 253 bool mclk_ignore_signal; 254 bool is_tlu_enabled; 255 bool disable_handshake; 256 bool smc_voltage_control_enabled; 257 bool vbi_time_out_support; 258 259 uint32_t soft_regs_start; 260 /* ---- Stuff originally coming from Evergreen ---- */ 261 uint32_t vddci_control; 262 struct pp_atomctrl_voltage_table vddc_voltage_table; 263 struct pp_atomctrl_voltage_table vddci_voltage_table; 264 struct pp_atomctrl_voltage_table mvdd_voltage_table; 265 struct pp_atomctrl_voltage_table vddgfx_voltage_table; 266 267 uint32_t mgcg_cgtt_local2; 268 uint32_t mgcg_cgtt_local3; 269 uint32_t gpio_debug; 270 uint32_t mc_micro_code_feature; 271 uint32_t highest_mclk; 272 uint16_t acpi_vddci; 273 uint8_t mvdd_high_index; 274 uint8_t mvdd_low_index; 275 bool dll_default_on; 276 bool performance_request_registered; 277 278 /* ---- Low Power Features ---- */ 279 bool ulv_supported; 280 281 /* ---- CAC Stuff ---- */ 282 uint32_t cac_table_start; 283 bool cac_configuration_required; 284 bool driver_calculate_cac_leakage; 285 bool cac_enabled; 286 287 /* ---- DPM2 Parameters ---- */ 288 uint32_t power_containment_features; 289 bool enable_dte_feature; 290 bool enable_tdc_limit_feature; 291 bool enable_pkg_pwr_tracking_feature; 292 bool disable_uvd_power_tune_feature; 293 294 295 uint32_t dte_tj_offset; 296 uint32_t fast_watermark_threshold; 297 298 /* ---- Phase Shedding ---- */ 299 uint8_t vddc_phase_shed_control; 300 301 /* ---- DI/DT ---- */ 302 struct smu7_display_timing display_timing; 303 304 /* ---- Thermal Temperature Setting ---- */ 305 struct smu7_thermal_temperature_setting thermal_temp_setting; 306 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; 307 uint32_t need_update_smu7_dpm_table; 308 uint32_t sclk_dpm_key_disabled; 309 uint32_t mclk_dpm_key_disabled; 310 uint32_t pcie_dpm_key_disabled; 311 uint32_t min_engine_clocks; 312 struct smu7_pcie_perf_range pcie_gen_performance; 313 struct smu7_pcie_perf_range pcie_lane_performance; 314 struct smu7_pcie_perf_range pcie_gen_power_saving; 315 struct smu7_pcie_perf_range pcie_lane_power_saving; 316 bool use_pcie_performance_levels; 317 bool use_pcie_power_saving_levels; 318 uint32_t mclk_dpm0_activity_target; 319 uint32_t low_sclk_interrupt_threshold; 320 uint32_t last_mclk_dpm_enable_mask; 321 bool uvd_enabled; 322 323 /* ---- Power Gating States ---- */ 324 bool uvd_power_gated; 325 bool vce_power_gated; 326 bool need_long_memory_training; 327 328 /* Application power optimization parameters */ 329 bool update_up_hyst; 330 bool update_down_hyst; 331 uint32_t down_hyst; 332 uint32_t up_hyst; 333 uint32_t disable_dpm_mask; 334 bool apply_optimized_settings; 335 336 uint32_t avfs_vdroop_override_setting; 337 bool apply_avfs_cks_off_voltage; 338 uint32_t frame_time_x2; 339 uint32_t last_sent_vbi_timeout; 340 uint16_t mem_latency_high; 341 uint16_t mem_latency_low; 342 uint32_t vr_config; 343 struct profile_mode_setting current_profile_setting; 344 345 uint32_t ro_range_minimum; 346 uint32_t ro_range_maximum; 347 348 bool disable_edc_leakage_controller; 349 AtomCtrl_HiLoLeakageOffsetTable edc_hilo_leakage_offset_from_vbios; 350 AtomCtrl_EDCLeakgeTable edc_leakage_table; 351 }; 352 353 /* To convert to Q8.8 format for firmware */ 354 #define SMU7_Q88_FORMAT_CONVERSION_UNIT 256 355 356 enum SMU7_I2CLineID { 357 SMU7_I2CLineID_DDC1 = 0x90, 358 SMU7_I2CLineID_DDC2 = 0x91, 359 SMU7_I2CLineID_DDC3 = 0x92, 360 SMU7_I2CLineID_DDC4 = 0x93, 361 SMU7_I2CLineID_DDC5 = 0x94, 362 SMU7_I2CLineID_DDC6 = 0x95, 363 SMU7_I2CLineID_SCLSDA = 0x96, 364 SMU7_I2CLineID_DDCVGA = 0x97 365 }; 366 367 #define SMU7_I2C_DDC1DATA 0 368 #define SMU7_I2C_DDC1CLK 1 369 #define SMU7_I2C_DDC2DATA 2 370 #define SMU7_I2C_DDC2CLK 3 371 #define SMU7_I2C_DDC3DATA 4 372 #define SMU7_I2C_DDC3CLK 5 373 #define SMU7_I2C_SDA 40 374 #define SMU7_I2C_SCL 41 375 #define SMU7_I2C_DDC4DATA 65 376 #define SMU7_I2C_DDC4CLK 66 377 #define SMU7_I2C_DDC5DATA 0x48 378 #define SMU7_I2C_DDC5CLK 0x49 379 #define SMU7_I2C_DDC6DATA 0x4a 380 #define SMU7_I2C_DDC6CLK 0x4b 381 #define SMU7_I2C_DDCVGADATA 0x4c 382 #define SMU7_I2C_DDCVGACLK 0x4d 383 384 #define SMU7_UNUSED_GPIO_PIN 0x7F 385 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 386 uint32_t clock_insr); 387 #endif 388 389