1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/slab.h> 28 #include <asm/div64.h> 29 #if IS_ENABLED(CONFIG_X86_64) 30 #include <asm/intel-family.h> 31 #endif 32 #include <drm/amdgpu_drm.h> 33 #include "ppatomctrl.h" 34 #include "atombios.h" 35 #include "pptable_v1_0.h" 36 #include "pppcielanes.h" 37 #include "amd_pcie_helpers.h" 38 #include "hardwaremanager.h" 39 #include "process_pptables_v1_0.h" 40 #include "cgs_common.h" 41 42 #include "smu7_common.h" 43 44 #include "hwmgr.h" 45 #include "smu7_hwmgr.h" 46 #include "smu_ucode_xfer_vi.h" 47 #include "smu7_powertune.h" 48 #include "smu7_dyn_defaults.h" 49 #include "smu7_thermal.h" 50 #include "smu7_clockpowergating.h" 51 #include "processpptables.h" 52 #include "pp_thermal.h" 53 #include "smu7_baco.h" 54 #include "smu7_smumgr.h" 55 #include "polaris10_smumgr.h" 56 57 #include "ivsrcid/ivsrcid_vislands30.h" 58 59 #define MC_CG_ARB_FREQ_F0 0x0a 60 #define MC_CG_ARB_FREQ_F1 0x0b 61 #define MC_CG_ARB_FREQ_F2 0x0c 62 #define MC_CG_ARB_FREQ_F3 0x0d 63 64 #define MC_CG_SEQ_DRAMCONF_S0 0x05 65 #define MC_CG_SEQ_DRAMCONF_S1 0x06 66 #define MC_CG_SEQ_YCLK_SUSPEND 0x04 67 #define MC_CG_SEQ_YCLK_RESUME 0x0a 68 69 #define SMC_CG_IND_START 0xc0030000 70 #define SMC_CG_IND_END 0xc0040000 71 72 #define MEM_FREQ_LOW_LATENCY 25000 73 #define MEM_FREQ_HIGH_LATENCY 80000 74 75 #define MEM_LATENCY_HIGH 45 76 #define MEM_LATENCY_LOW 35 77 #define MEM_LATENCY_ERR 0xFFFF 78 79 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 80 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 81 #define MC_SEQ_MISC0_GDDR5_VALUE 5 82 83 #define PCIE_BUS_CLK 10000 84 #define TCLK (PCIE_BUS_CLK / 10) 85 86 static struct profile_mode_setting smu7_profiling[7] = 87 {{0, 0, 0, 0, 0, 0, 0, 0}, 88 {1, 0, 100, 30, 1, 0, 100, 10}, 89 {1, 10, 0, 30, 0, 0, 0, 0}, 90 {0, 0, 0, 0, 1, 10, 16, 31}, 91 {1, 0, 11, 50, 1, 0, 100, 10}, 92 {1, 0, 5, 30, 0, 0, 0, 0}, 93 {0, 0, 0, 0, 0, 0, 0, 0}, 94 }; 95 96 #define PPSMC_MSG_SetVBITimeout_VEGAM ((uint16_t) 0x310) 97 98 #define ixPWR_SVI2_PLANE1_LOAD 0xC0200280 99 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK 0x00000020L 100 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK 0x00000040L 101 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT 0x00000005 102 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT 0x00000006 103 104 #define STRAP_EVV_REVISION_MSB 2211 105 #define STRAP_EVV_REVISION_LSB 2208 106 107 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ 108 enum DPM_EVENT_SRC { 109 DPM_EVENT_SRC_ANALOG = 0, 110 DPM_EVENT_SRC_EXTERNAL = 1, 111 DPM_EVENT_SRC_DIGITAL = 2, 112 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 113 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 114 }; 115 116 #define ixDIDT_SQ_EDC_CTRL 0x0013 117 #define ixDIDT_SQ_EDC_THRESHOLD 0x0014 118 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 119 #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 120 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 121 #define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 122 123 #define ixDIDT_TD_EDC_CTRL 0x0053 124 #define ixDIDT_TD_EDC_THRESHOLD 0x0054 125 #define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 126 #define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 127 #define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 128 #define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 129 130 #define ixDIDT_TCP_EDC_CTRL 0x0073 131 #define ixDIDT_TCP_EDC_THRESHOLD 0x0074 132 #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 133 #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 134 #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 135 #define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 136 137 #define ixDIDT_DB_EDC_CTRL 0x0033 138 #define ixDIDT_DB_EDC_THRESHOLD 0x0034 139 #define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 140 #define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 141 #define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 142 #define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 143 144 uint32_t DIDTEDCConfig_P12[] = { 145 ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 146 ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 147 ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 148 ixDIDT_SQ_EDC_STALL_PATTERN_7, 149 ixDIDT_SQ_EDC_THRESHOLD, 150 ixDIDT_SQ_EDC_CTRL, 151 ixDIDT_TD_EDC_STALL_PATTERN_1_2, 152 ixDIDT_TD_EDC_STALL_PATTERN_3_4, 153 ixDIDT_TD_EDC_STALL_PATTERN_5_6, 154 ixDIDT_TD_EDC_STALL_PATTERN_7, 155 ixDIDT_TD_EDC_THRESHOLD, 156 ixDIDT_TD_EDC_CTRL, 157 ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 158 ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 159 ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 160 ixDIDT_TCP_EDC_STALL_PATTERN_7, 161 ixDIDT_TCP_EDC_THRESHOLD, 162 ixDIDT_TCP_EDC_CTRL, 163 ixDIDT_DB_EDC_STALL_PATTERN_1_2, 164 ixDIDT_DB_EDC_STALL_PATTERN_3_4, 165 ixDIDT_DB_EDC_STALL_PATTERN_5_6, 166 ixDIDT_DB_EDC_STALL_PATTERN_7, 167 ixDIDT_DB_EDC_THRESHOLD, 168 ixDIDT_DB_EDC_CTRL, 169 0xFFFFFFFF // End of list 170 }; 171 172 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic); 173 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 174 enum pp_clock_type type, uint32_t mask); 175 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr); 176 177 static struct smu7_power_state *cast_phw_smu7_power_state( 178 struct pp_hw_power_state *hw_ps) 179 { 180 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), 181 "Invalid Powerstate Type!", 182 return NULL); 183 184 return (struct smu7_power_state *)hw_ps; 185 } 186 187 static const struct smu7_power_state *cast_const_phw_smu7_power_state( 188 const struct pp_hw_power_state *hw_ps) 189 { 190 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), 191 "Invalid Powerstate Type!", 192 return NULL); 193 194 return (const struct smu7_power_state *)hw_ps; 195 } 196 197 /** 198 * smu7_get_mc_microcode_version - Find the MC microcode version and store it in the HwMgr struct 199 * 200 * @hwmgr: the address of the powerplay hardware manager. 201 * Return: always 0 202 */ 203 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) 204 { 205 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); 206 207 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); 208 209 return 0; 210 } 211 212 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) 213 { 214 uint32_t speedCntl = 0; 215 216 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ 217 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, 218 ixPCIE_LC_SPEED_CNTL); 219 return((uint16_t)PHM_GET_FIELD(speedCntl, 220 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); 221 } 222 223 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) 224 { 225 uint32_t link_width; 226 227 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ 228 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 229 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); 230 231 PP_ASSERT_WITH_CODE((7 >= link_width), 232 "Invalid PCIe lane width!", return 0); 233 234 return decode_pcie_lane_width(link_width); 235 } 236 237 /** 238 * smu7_enable_smc_voltage_controller - Enable voltage control 239 * 240 * @hwmgr: the address of the powerplay hardware manager. 241 * Return: always PP_Result_OK 242 */ 243 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) 244 { 245 if (hwmgr->chip_id >= CHIP_POLARIS10 && 246 hwmgr->chip_id <= CHIP_VEGAM) { 247 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 248 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0); 249 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 250 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0); 251 } 252 253 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) 254 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL); 255 256 return 0; 257 } 258 259 /** 260 * smu7_voltage_control - Checks if we want to support voltage control 261 * 262 * @hwmgr: the address of the powerplay hardware manager. 263 */ 264 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr) 265 { 266 const struct smu7_hwmgr *data = 267 (const struct smu7_hwmgr *)(hwmgr->backend); 268 269 return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control); 270 } 271 272 /** 273 * smu7_enable_voltage_control - Enable voltage control 274 * 275 * @hwmgr: the address of the powerplay hardware manager. 276 * Return: always 0 277 */ 278 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr) 279 { 280 /* enable voltage control */ 281 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 282 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); 283 284 return 0; 285 } 286 287 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table, 288 struct phm_clock_voltage_dependency_table *voltage_dependency_table 289 ) 290 { 291 uint32_t i; 292 293 PP_ASSERT_WITH_CODE((NULL != voltage_table), 294 "Voltage Dependency Table empty.", return -EINVAL;); 295 296 voltage_table->mask_low = 0; 297 voltage_table->phase_delay = 0; 298 voltage_table->count = voltage_dependency_table->count; 299 300 for (i = 0; i < voltage_dependency_table->count; i++) { 301 voltage_table->entries[i].value = 302 voltage_dependency_table->entries[i].v; 303 voltage_table->entries[i].smio_low = 0; 304 } 305 306 return 0; 307 } 308 309 310 /** 311 * smu7_construct_voltage_tables - Create Voltage Tables. 312 * 313 * @hwmgr: the address of the powerplay hardware manager. 314 * Return: always 0 315 */ 316 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) 317 { 318 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 319 struct phm_ppt_v1_information *table_info = 320 (struct phm_ppt_v1_information *)hwmgr->pptable; 321 int result = 0; 322 uint32_t tmp; 323 324 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 325 result = atomctrl_get_voltage_table_v3(hwmgr, 326 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, 327 &(data->mvdd_voltage_table)); 328 PP_ASSERT_WITH_CODE((0 == result), 329 "Failed to retrieve MVDD table.", 330 return result); 331 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { 332 if (hwmgr->pp_table_version == PP_TABLE_V1) 333 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), 334 table_info->vdd_dep_on_mclk); 335 else if (hwmgr->pp_table_version == PP_TABLE_V0) 336 result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table), 337 hwmgr->dyn_state.mvdd_dependency_on_mclk); 338 339 PP_ASSERT_WITH_CODE((0 == result), 340 "Failed to retrieve SVI2 MVDD table from dependency table.", 341 return result;); 342 } 343 344 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 345 result = atomctrl_get_voltage_table_v3(hwmgr, 346 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, 347 &(data->vddci_voltage_table)); 348 PP_ASSERT_WITH_CODE((0 == result), 349 "Failed to retrieve VDDCI table.", 350 return result); 351 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { 352 if (hwmgr->pp_table_version == PP_TABLE_V1) 353 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), 354 table_info->vdd_dep_on_mclk); 355 else if (hwmgr->pp_table_version == PP_TABLE_V0) 356 result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table), 357 hwmgr->dyn_state.vddci_dependency_on_mclk); 358 PP_ASSERT_WITH_CODE((0 == result), 359 "Failed to retrieve SVI2 VDDCI table from dependency table.", 360 return result); 361 } 362 363 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { 364 /* VDDGFX has only SVI2 voltage control */ 365 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table), 366 table_info->vddgfx_lookup_table); 367 PP_ASSERT_WITH_CODE((0 == result), 368 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;); 369 } 370 371 372 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) { 373 result = atomctrl_get_voltage_table_v3(hwmgr, 374 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT, 375 &data->vddc_voltage_table); 376 PP_ASSERT_WITH_CODE((0 == result), 377 "Failed to retrieve VDDC table.", return result;); 378 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 379 380 if (hwmgr->pp_table_version == PP_TABLE_V0) 381 result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table, 382 hwmgr->dyn_state.vddc_dependency_on_mclk); 383 else if (hwmgr->pp_table_version == PP_TABLE_V1) 384 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), 385 table_info->vddc_lookup_table); 386 387 PP_ASSERT_WITH_CODE((0 == result), 388 "Failed to retrieve SVI2 VDDC table from dependency table.", return result;); 389 } 390 391 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC); 392 PP_ASSERT_WITH_CODE( 393 (data->vddc_voltage_table.count <= tmp), 394 "Too many voltage values for VDDC. Trimming to fit state table.", 395 phm_trim_voltage_table_to_fit_state_table(tmp, 396 &(data->vddc_voltage_table))); 397 398 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); 399 PP_ASSERT_WITH_CODE( 400 (data->vddgfx_voltage_table.count <= tmp), 401 "Too many voltage values for VDDC. Trimming to fit state table.", 402 phm_trim_voltage_table_to_fit_state_table(tmp, 403 &(data->vddgfx_voltage_table))); 404 405 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI); 406 PP_ASSERT_WITH_CODE( 407 (data->vddci_voltage_table.count <= tmp), 408 "Too many voltage values for VDDCI. Trimming to fit state table.", 409 phm_trim_voltage_table_to_fit_state_table(tmp, 410 &(data->vddci_voltage_table))); 411 412 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD); 413 PP_ASSERT_WITH_CODE( 414 (data->mvdd_voltage_table.count <= tmp), 415 "Too many voltage values for MVDD. Trimming to fit state table.", 416 phm_trim_voltage_table_to_fit_state_table(tmp, 417 &(data->mvdd_voltage_table))); 418 419 return 0; 420 } 421 422 /** 423 * smu7_program_static_screen_threshold_parameters - Programs static screed detection parameters 424 * 425 * @hwmgr: the address of the powerplay hardware manager. 426 * Return: always 0 427 */ 428 static int smu7_program_static_screen_threshold_parameters( 429 struct pp_hwmgr *hwmgr) 430 { 431 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 432 433 /* Set static screen threshold unit */ 434 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 435 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, 436 data->static_screen_threshold_unit); 437 /* Set static screen threshold */ 438 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 439 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, 440 data->static_screen_threshold); 441 442 return 0; 443 } 444 445 /** 446 * smu7_enable_display_gap - Setup display gap for glitch free memory clock switching. 447 * 448 * @hwmgr: the address of the powerplay hardware manager. 449 * Return: always 0 450 */ 451 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr) 452 { 453 uint32_t display_gap = 454 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 455 ixCG_DISPLAY_GAP_CNTL); 456 457 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, 458 DISP_GAP, DISPLAY_GAP_IGNORE); 459 460 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, 461 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); 462 463 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 464 ixCG_DISPLAY_GAP_CNTL, display_gap); 465 466 return 0; 467 } 468 469 /** 470 * smu7_program_voting_clients - Programs activity state transition voting clients 471 * 472 * @hwmgr: the address of the powerplay hardware manager. 473 * Return: always 0 474 */ 475 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) 476 { 477 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 478 int i; 479 480 /* Clear reset for voting clients before enabling DPM */ 481 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 482 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); 483 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 484 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); 485 486 for (i = 0; i < 8; i++) 487 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 488 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 489 data->voting_rights_clients[i]); 490 return 0; 491 } 492 493 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) 494 { 495 int i; 496 497 /* Reset voting clients before disabling DPM */ 498 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 499 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); 500 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 501 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); 502 503 for (i = 0; i < 8; i++) 504 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 505 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0); 506 507 return 0; 508 } 509 510 /* Copy one arb setting to another and then switch the active set. 511 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. 512 */ 513 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, 514 uint32_t arb_src, uint32_t arb_dest) 515 { 516 uint32_t mc_arb_dram_timing; 517 uint32_t mc_arb_dram_timing2; 518 uint32_t burst_time; 519 uint32_t mc_cg_config; 520 521 switch (arb_src) { 522 case MC_CG_ARB_FREQ_F0: 523 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); 524 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); 525 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); 526 break; 527 case MC_CG_ARB_FREQ_F1: 528 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); 529 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); 530 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 switch (arb_dest) { 537 case MC_CG_ARB_FREQ_F0: 538 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); 539 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 540 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); 541 break; 542 case MC_CG_ARB_FREQ_F1: 543 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 544 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 545 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); 546 break; 547 default: 548 return -EINVAL; 549 } 550 551 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); 552 mc_cg_config |= 0x0000000F; 553 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); 554 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); 555 556 return 0; 557 } 558 559 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) 560 { 561 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL); 562 } 563 564 /** 565 * smu7_initial_switch_from_arbf0_to_f1 - Initial switch from ARB F0->F1 566 * 567 * @hwmgr: the address of the powerplay hardware manager. 568 * Return: always 0 569 * This function is to be called from the SetPowerState table. 570 */ 571 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) 572 { 573 return smu7_copy_and_switch_arb_sets(hwmgr, 574 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 575 } 576 577 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) 578 { 579 uint32_t tmp; 580 581 tmp = (cgs_read_ind_register(hwmgr->device, 582 CGS_IND_REG__SMC, ixSMC_SCRATCH9) & 583 0x0000ff00) >> 8; 584 585 if (tmp == MC_CG_ARB_FREQ_F0) 586 return 0; 587 588 return smu7_copy_and_switch_arb_sets(hwmgr, 589 tmp, MC_CG_ARB_FREQ_F0); 590 } 591 592 static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr) 593 { 594 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 595 uint16_t pcie_gen = 0; 596 597 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 && 598 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4) 599 pcie_gen = 3; 600 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 && 601 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) 602 pcie_gen = 2; 603 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 && 604 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2) 605 pcie_gen = 1; 606 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 && 607 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1) 608 pcie_gen = 0; 609 610 return pcie_gen; 611 } 612 613 static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr) 614 { 615 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 616 uint16_t pcie_width = 0; 617 618 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 619 pcie_width = 16; 620 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 621 pcie_width = 12; 622 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 623 pcie_width = 8; 624 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 625 pcie_width = 4; 626 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 627 pcie_width = 2; 628 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 629 pcie_width = 1; 630 631 return pcie_width; 632 } 633 634 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 635 { 636 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 637 638 struct phm_ppt_v1_information *table_info = 639 (struct phm_ppt_v1_information *)(hwmgr->pptable); 640 struct phm_ppt_v1_pcie_table *pcie_table = NULL; 641 642 uint32_t i, max_entry; 643 uint32_t tmp; 644 645 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || 646 data->use_pcie_power_saving_levels), "No pcie performance levels!", 647 return -EINVAL); 648 649 if (table_info != NULL) 650 pcie_table = table_info->pcie_table; 651 652 if (data->use_pcie_performance_levels && 653 !data->use_pcie_power_saving_levels) { 654 data->pcie_gen_power_saving = data->pcie_gen_performance; 655 data->pcie_lane_power_saving = data->pcie_lane_performance; 656 } else if (!data->use_pcie_performance_levels && 657 data->use_pcie_power_saving_levels) { 658 data->pcie_gen_performance = data->pcie_gen_power_saving; 659 data->pcie_lane_performance = data->pcie_lane_power_saving; 660 } 661 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK); 662 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, 663 tmp, 664 MAX_REGULAR_DPM_NUMBER); 665 666 if (pcie_table != NULL) { 667 /* max_entry is used to make sure we reserve one PCIE level 668 * for boot level (fix for A+A PSPP issue). 669 * If PCIE table from PPTable have ULV entry + 8 entries, 670 * then ignore the last entry.*/ 671 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count; 672 for (i = 1; i < max_entry; i++) { 673 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, 674 get_pcie_gen_support(data->pcie_gen_cap, 675 pcie_table->entries[i].gen_speed), 676 get_pcie_lane_support(data->pcie_lane_cap, 677 pcie_table->entries[i].lane_width)); 678 } 679 data->dpm_table.pcie_speed_table.count = max_entry - 1; 680 smum_update_smc_table(hwmgr, SMU_BIF_TABLE); 681 } else { 682 /* Hardcode Pcie Table */ 683 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, 684 get_pcie_gen_support(data->pcie_gen_cap, 685 PP_Min_PCIEGen), 686 get_pcie_lane_support(data->pcie_lane_cap, 687 PP_Max_PCIELane)); 688 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, 689 get_pcie_gen_support(data->pcie_gen_cap, 690 PP_Min_PCIEGen), 691 get_pcie_lane_support(data->pcie_lane_cap, 692 PP_Max_PCIELane)); 693 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, 694 get_pcie_gen_support(data->pcie_gen_cap, 695 PP_Max_PCIEGen), 696 get_pcie_lane_support(data->pcie_lane_cap, 697 PP_Max_PCIELane)); 698 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, 699 get_pcie_gen_support(data->pcie_gen_cap, 700 PP_Max_PCIEGen), 701 get_pcie_lane_support(data->pcie_lane_cap, 702 PP_Max_PCIELane)); 703 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, 704 get_pcie_gen_support(data->pcie_gen_cap, 705 PP_Max_PCIEGen), 706 get_pcie_lane_support(data->pcie_lane_cap, 707 PP_Max_PCIELane)); 708 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, 709 get_pcie_gen_support(data->pcie_gen_cap, 710 PP_Max_PCIEGen), 711 get_pcie_lane_support(data->pcie_lane_cap, 712 PP_Max_PCIELane)); 713 714 data->dpm_table.pcie_speed_table.count = 6; 715 } 716 /* Populate last level for boot PCIE level, but do not increment count. */ 717 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 718 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) 719 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i, 720 get_pcie_gen_support(data->pcie_gen_cap, 721 PP_Max_PCIEGen), 722 data->vbios_boot_state.pcie_lane_bootup_value); 723 } else { 724 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 725 data->dpm_table.pcie_speed_table.count, 726 get_pcie_gen_support(data->pcie_gen_cap, 727 PP_Min_PCIEGen), 728 get_pcie_lane_support(data->pcie_lane_cap, 729 PP_Max_PCIELane)); 730 731 if (data->pcie_dpm_key_disabled) 732 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 733 data->dpm_table.pcie_speed_table.count, 734 smu7_override_pcie_speed(hwmgr), smu7_override_pcie_width(hwmgr)); 735 } 736 return 0; 737 } 738 739 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) 740 { 741 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 742 743 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); 744 745 phm_reset_single_dpm_table( 746 &data->dpm_table.sclk_table, 747 smum_get_mac_definition(hwmgr, 748 SMU_MAX_LEVELS_GRAPHICS), 749 MAX_REGULAR_DPM_NUMBER); 750 phm_reset_single_dpm_table( 751 &data->dpm_table.mclk_table, 752 smum_get_mac_definition(hwmgr, 753 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); 754 755 phm_reset_single_dpm_table( 756 &data->dpm_table.vddc_table, 757 smum_get_mac_definition(hwmgr, 758 SMU_MAX_LEVELS_VDDC), 759 MAX_REGULAR_DPM_NUMBER); 760 phm_reset_single_dpm_table( 761 &data->dpm_table.vddci_table, 762 smum_get_mac_definition(hwmgr, 763 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); 764 765 phm_reset_single_dpm_table( 766 &data->dpm_table.mvdd_table, 767 smum_get_mac_definition(hwmgr, 768 SMU_MAX_LEVELS_MVDD), 769 MAX_REGULAR_DPM_NUMBER); 770 return 0; 771 } 772 /* 773 * This function is to initialize all DPM state tables 774 * for SMU7 based on the dependency table. 775 * Dynamic state patching function will then trim these 776 * state tables to the allowed range based 777 * on the power policy or external client requests, 778 * such as UVD request, etc. 779 */ 780 781 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) 782 { 783 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 784 struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table = 785 hwmgr->dyn_state.vddc_dependency_on_sclk; 786 struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table = 787 hwmgr->dyn_state.vddc_dependency_on_mclk; 788 struct phm_cac_leakage_table *std_voltage_table = 789 hwmgr->dyn_state.cac_leakage_table; 790 uint32_t i; 791 792 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, 793 "SCLK dependency table is missing. This table is mandatory", return -EINVAL); 794 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, 795 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); 796 797 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, 798 "MCLK dependency table is missing. This table is mandatory", return -EINVAL); 799 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, 800 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); 801 802 803 /* Initialize Sclk DPM table based on allow Sclk values*/ 804 data->dpm_table.sclk_table.count = 0; 805 806 for (i = 0; i < allowed_vdd_sclk_table->count; i++) { 807 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != 808 allowed_vdd_sclk_table->entries[i].clk) { 809 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 810 allowed_vdd_sclk_table->entries[i].clk; 811 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; 812 data->dpm_table.sclk_table.count++; 813 } 814 } 815 816 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, 817 "MCLK dependency table is missing. This table is mandatory", return -EINVAL); 818 /* Initialize Mclk DPM table based on allow Mclk values */ 819 data->dpm_table.mclk_table.count = 0; 820 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 821 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != 822 allowed_vdd_mclk_table->entries[i].clk) { 823 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 824 allowed_vdd_mclk_table->entries[i].clk; 825 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; 826 data->dpm_table.mclk_table.count++; 827 } 828 } 829 830 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */ 831 for (i = 0; i < allowed_vdd_sclk_table->count; i++) { 832 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 833 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; 834 /* param1 is for corresponding std voltage */ 835 data->dpm_table.vddc_table.dpm_levels[i].enabled = true; 836 } 837 838 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count; 839 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; 840 841 if (NULL != allowed_vdd_mclk_table) { 842 /* Initialize Vddci DPM table based on allow Mclk values */ 843 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 844 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 845 data->dpm_table.vddci_table.dpm_levels[i].enabled = true; 846 } 847 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count; 848 } 849 850 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; 851 852 if (NULL != allowed_vdd_mclk_table) { 853 /* 854 * Initialize MVDD DPM table based on allow Mclk 855 * values 856 */ 857 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 858 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 859 data->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 860 } 861 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count; 862 } 863 864 return 0; 865 } 866 867 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr) 868 { 869 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 870 struct phm_ppt_v1_information *table_info = 871 (struct phm_ppt_v1_information *)(hwmgr->pptable); 872 uint32_t i; 873 874 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 875 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 876 877 if (table_info == NULL) 878 return -EINVAL; 879 880 dep_sclk_table = table_info->vdd_dep_on_sclk; 881 dep_mclk_table = table_info->vdd_dep_on_mclk; 882 883 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, 884 "SCLK dependency table is missing.", 885 return -EINVAL); 886 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, 887 "SCLK dependency table count is 0.", 888 return -EINVAL); 889 890 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, 891 "MCLK dependency table is missing.", 892 return -EINVAL); 893 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, 894 "MCLK dependency table count is 0", 895 return -EINVAL); 896 897 /* Initialize Sclk DPM table based on allow Sclk values */ 898 data->dpm_table.sclk_table.count = 0; 899 for (i = 0; i < dep_sclk_table->count; i++) { 900 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != 901 dep_sclk_table->entries[i].clk) { 902 903 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 904 dep_sclk_table->entries[i].clk; 905 906 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 907 (i == 0) ? true : false; 908 data->dpm_table.sclk_table.count++; 909 } 910 } 911 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) 912 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; 913 /* Initialize Mclk DPM table based on allow Mclk values */ 914 data->dpm_table.mclk_table.count = 0; 915 for (i = 0; i < dep_mclk_table->count; i++) { 916 if (i == 0 || data->dpm_table.mclk_table.dpm_levels 917 [data->dpm_table.mclk_table.count - 1].value != 918 dep_mclk_table->entries[i].clk) { 919 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 920 dep_mclk_table->entries[i].clk; 921 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 922 (i == 0) ? true : false; 923 data->dpm_table.mclk_table.count++; 924 } 925 } 926 927 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) 928 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk; 929 return 0; 930 } 931 932 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr) 933 { 934 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 935 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 936 struct phm_ppt_v1_information *table_info = 937 (struct phm_ppt_v1_information *)(hwmgr->pptable); 938 uint32_t i; 939 940 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 941 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 942 struct phm_odn_performance_level *entries; 943 944 if (table_info == NULL) 945 return -EINVAL; 946 947 dep_sclk_table = table_info->vdd_dep_on_sclk; 948 dep_mclk_table = table_info->vdd_dep_on_mclk; 949 950 odn_table->odn_core_clock_dpm_levels.num_of_pl = 951 data->golden_dpm_table.sclk_table.count; 952 entries = odn_table->odn_core_clock_dpm_levels.entries; 953 for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) { 954 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value; 955 entries[i].enabled = true; 956 entries[i].vddc = dep_sclk_table->entries[i].vddc; 957 } 958 959 smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table, 960 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk)); 961 962 odn_table->odn_memory_clock_dpm_levels.num_of_pl = 963 data->golden_dpm_table.mclk_table.count; 964 entries = odn_table->odn_memory_clock_dpm_levels.entries; 965 for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) { 966 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value; 967 entries[i].enabled = true; 968 entries[i].vddc = dep_mclk_table->entries[i].vddc; 969 } 970 971 smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table, 972 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk)); 973 974 return 0; 975 } 976 977 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr) 978 { 979 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 980 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 981 struct phm_ppt_v1_information *table_info = 982 (struct phm_ppt_v1_information *)(hwmgr->pptable); 983 uint32_t min_vddc = 0; 984 uint32_t max_vddc = 0; 985 986 if (!table_info) 987 return; 988 989 dep_sclk_table = table_info->vdd_dep_on_sclk; 990 991 atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc); 992 993 if (min_vddc == 0 || min_vddc > 2000 994 || min_vddc > dep_sclk_table->entries[0].vddc) 995 min_vddc = dep_sclk_table->entries[0].vddc; 996 997 if (max_vddc == 0 || max_vddc > 2000 998 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc) 999 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc; 1000 1001 data->odn_dpm_table.min_vddc = min_vddc; 1002 data->odn_dpm_table.max_vddc = max_vddc; 1003 } 1004 1005 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) 1006 { 1007 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1008 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 1009 struct phm_ppt_v1_information *table_info = 1010 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1011 uint32_t i; 1012 1013 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 1014 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; 1015 1016 if (table_info == NULL) 1017 return; 1018 1019 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { 1020 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock != 1021 data->dpm_table.sclk_table.dpm_levels[i].value) { 1022 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 1023 break; 1024 } 1025 } 1026 1027 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { 1028 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock != 1029 data->dpm_table.mclk_table.dpm_levels[i].value) { 1030 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 1031 break; 1032 } 1033 } 1034 1035 dep_table = table_info->vdd_dep_on_mclk; 1036 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk); 1037 1038 for (i = 0; i < dep_table->count; i++) { 1039 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 1040 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; 1041 return; 1042 } 1043 } 1044 1045 dep_table = table_info->vdd_dep_on_sclk; 1046 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); 1047 for (i = 0; i < dep_table->count; i++) { 1048 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 1049 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; 1050 return; 1051 } 1052 } 1053 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 1054 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; 1055 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; 1056 } 1057 } 1058 1059 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 1060 { 1061 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1062 1063 smu7_reset_dpm_tables(hwmgr); 1064 1065 if (hwmgr->pp_table_version == PP_TABLE_V1) 1066 smu7_setup_dpm_tables_v1(hwmgr); 1067 else if (hwmgr->pp_table_version == PP_TABLE_V0) 1068 smu7_setup_dpm_tables_v0(hwmgr); 1069 1070 smu7_setup_default_pcie_table(hwmgr); 1071 1072 /* save a copy of the default DPM table */ 1073 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 1074 sizeof(struct smu7_dpm_table)); 1075 1076 /* initialize ODN table */ 1077 if (hwmgr->od_enabled) { 1078 if (data->odn_dpm_table.max_vddc) { 1079 smu7_check_dpm_table_updated(hwmgr); 1080 } else { 1081 smu7_setup_voltage_range_from_vbios(hwmgr); 1082 smu7_odn_initial_default_setting(hwmgr); 1083 } 1084 } 1085 return 0; 1086 } 1087 1088 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) 1089 { 1090 1091 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1092 PHM_PlatformCaps_RegulatorHot)) 1093 return smum_send_msg_to_smc(hwmgr, 1094 PPSMC_MSG_EnableVRHotGPIOInterrupt, 1095 NULL); 1096 1097 return 0; 1098 } 1099 1100 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr) 1101 { 1102 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1103 SCLK_PWRMGT_OFF, 0); 1104 return 0; 1105 } 1106 1107 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) 1108 { 1109 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1110 1111 if (data->ulv_supported) 1112 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL); 1113 1114 return 0; 1115 } 1116 1117 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) 1118 { 1119 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1120 1121 if (data->ulv_supported) 1122 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL); 1123 1124 return 0; 1125 } 1126 1127 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 1128 { 1129 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1130 PHM_PlatformCaps_SclkDeepSleep)) { 1131 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL)) 1132 PP_ASSERT_WITH_CODE(false, 1133 "Attempt to enable Master Deep Sleep switch failed!", 1134 return -EINVAL); 1135 } else { 1136 if (smum_send_msg_to_smc(hwmgr, 1137 PPSMC_MSG_MASTER_DeepSleep_OFF, 1138 NULL)) { 1139 PP_ASSERT_WITH_CODE(false, 1140 "Attempt to disable Master Deep Sleep switch failed!", 1141 return -EINVAL); 1142 } 1143 } 1144 1145 return 0; 1146 } 1147 1148 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 1149 { 1150 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1151 PHM_PlatformCaps_SclkDeepSleep)) { 1152 if (smum_send_msg_to_smc(hwmgr, 1153 PPSMC_MSG_MASTER_DeepSleep_OFF, 1154 NULL)) { 1155 PP_ASSERT_WITH_CODE(false, 1156 "Attempt to disable Master Deep Sleep switch failed!", 1157 return -EINVAL); 1158 } 1159 } 1160 1161 return 0; 1162 } 1163 1164 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr) 1165 { 1166 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1167 uint32_t soft_register_value = 0; 1168 uint32_t handshake_disables_offset = data->soft_regs_start 1169 + smum_get_offsetof(hwmgr, 1170 SMU_SoftRegisters, HandshakeDisables); 1171 1172 soft_register_value = cgs_read_ind_register(hwmgr->device, 1173 CGS_IND_REG__SMC, handshake_disables_offset); 1174 soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE; 1175 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1176 handshake_disables_offset, soft_register_value); 1177 return 0; 1178 } 1179 1180 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) 1181 { 1182 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1183 uint32_t soft_register_value = 0; 1184 uint32_t handshake_disables_offset = data->soft_regs_start 1185 + smum_get_offsetof(hwmgr, 1186 SMU_SoftRegisters, HandshakeDisables); 1187 1188 soft_register_value = cgs_read_ind_register(hwmgr->device, 1189 CGS_IND_REG__SMC, handshake_disables_offset); 1190 soft_register_value |= smum_get_mac_definition(hwmgr, 1191 SMU_UVD_MCLK_HANDSHAKE_DISABLE); 1192 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1193 handshake_disables_offset, soft_register_value); 1194 return 0; 1195 } 1196 1197 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 1198 { 1199 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1200 1201 /* enable SCLK dpm */ 1202 if (!data->sclk_dpm_key_disabled) { 1203 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1204 hwmgr->chip_id <= CHIP_VEGAM) 1205 smu7_disable_sclk_vce_handshake(hwmgr); 1206 1207 PP_ASSERT_WITH_CODE( 1208 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)), 1209 "Failed to enable SCLK DPM during DPM Start Function!", 1210 return -EINVAL); 1211 } 1212 1213 /* enable MCLK dpm */ 1214 if (0 == data->mclk_dpm_key_disabled) { 1215 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) 1216 smu7_disable_handshake_uvd(hwmgr); 1217 1218 PP_ASSERT_WITH_CODE( 1219 (0 == smum_send_msg_to_smc(hwmgr, 1220 PPSMC_MSG_MCLKDPM_Enable, 1221 NULL)), 1222 "Failed to enable MCLK DPM during DPM Start Function!", 1223 return -EINVAL); 1224 1225 if ((hwmgr->chip_family == AMDGPU_FAMILY_CI) || 1226 (hwmgr->chip_id == CHIP_POLARIS10) || 1227 (hwmgr->chip_id == CHIP_POLARIS11) || 1228 (hwmgr->chip_id == CHIP_POLARIS12) || 1229 (hwmgr->chip_id == CHIP_TONGA) || 1230 (hwmgr->chip_id == CHIP_TOPAZ)) 1231 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); 1232 1233 1234 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 1235 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5); 1236 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5); 1237 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005); 1238 udelay(10); 1239 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005); 1240 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005); 1241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005); 1242 } else { 1243 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); 1244 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); 1245 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); 1246 udelay(10); 1247 if (hwmgr->chip_id == CHIP_VEGAM) { 1248 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009); 1249 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009); 1250 } else { 1251 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); 1252 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); 1253 } 1254 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); 1255 } 1256 } 1257 1258 return 0; 1259 } 1260 1261 static int smu7_start_dpm(struct pp_hwmgr *hwmgr) 1262 { 1263 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1264 1265 /*enable general power management */ 1266 1267 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1268 GLOBAL_PWRMGT_EN, 1); 1269 1270 /* enable sclk deep sleep */ 1271 1272 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1273 DYNAMIC_PM_EN, 1); 1274 1275 /* prepare for PCIE DPM */ 1276 1277 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1278 data->soft_regs_start + 1279 smum_get_offsetof(hwmgr, SMU_SoftRegisters, 1280 VoltageChangeTimeout), 0x1000); 1281 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 1282 SWRST_COMMAND_1, RESETLC, 0x0); 1283 1284 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) 1285 cgs_write_register(hwmgr->device, 0x1488, 1286 (cgs_read_register(hwmgr->device, 0x1488) & ~0x1)); 1287 1288 if (smu7_enable_sclk_mclk_dpm(hwmgr)) { 1289 pr_err("Failed to enable Sclk DPM and Mclk DPM!"); 1290 return -EINVAL; 1291 } 1292 1293 /* enable PCIE dpm */ 1294 if (0 == data->pcie_dpm_key_disabled) { 1295 PP_ASSERT_WITH_CODE( 1296 (0 == smum_send_msg_to_smc(hwmgr, 1297 PPSMC_MSG_PCIeDPM_Enable, 1298 NULL)), 1299 "Failed to enable pcie DPM during DPM Start Function!", 1300 return -EINVAL); 1301 } else { 1302 PP_ASSERT_WITH_CODE( 1303 (0 == smum_send_msg_to_smc(hwmgr, 1304 PPSMC_MSG_PCIeDPM_Disable, 1305 NULL)), 1306 "Failed to disable pcie DPM during DPM Start Function!", 1307 return -EINVAL); 1308 } 1309 1310 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1311 PHM_PlatformCaps_Falcon_QuickTransition)) { 1312 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr, 1313 PPSMC_MSG_EnableACDCGPIOInterrupt, 1314 NULL)), 1315 "Failed to enable AC DC GPIO Interrupt!", 1316 ); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 1323 { 1324 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1325 1326 /* disable SCLK dpm */ 1327 if (!data->sclk_dpm_key_disabled) { 1328 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1329 "Trying to disable SCLK DPM when DPM is disabled", 1330 return 0); 1331 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL); 1332 } 1333 1334 /* disable MCLK dpm */ 1335 if (!data->mclk_dpm_key_disabled) { 1336 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1337 "Trying to disable MCLK DPM when DPM is disabled", 1338 return 0); 1339 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) 1346 { 1347 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1348 1349 /* disable general power management */ 1350 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1351 GLOBAL_PWRMGT_EN, 0); 1352 /* disable sclk deep sleep */ 1353 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1354 DYNAMIC_PM_EN, 0); 1355 1356 /* disable PCIE dpm */ 1357 if (!data->pcie_dpm_key_disabled) { 1358 PP_ASSERT_WITH_CODE( 1359 (smum_send_msg_to_smc(hwmgr, 1360 PPSMC_MSG_PCIeDPM_Disable, 1361 NULL) == 0), 1362 "Failed to disable pcie DPM during DPM Stop Function!", 1363 return -EINVAL); 1364 } 1365 1366 smu7_disable_sclk_mclk_dpm(hwmgr); 1367 1368 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1369 "Trying to disable voltage DPM when DPM is disabled", 1370 return 0); 1371 1372 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL); 1373 1374 return 0; 1375 } 1376 1377 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) 1378 { 1379 bool protection; 1380 enum DPM_EVENT_SRC src; 1381 1382 switch (sources) { 1383 default: 1384 pr_err("Unknown throttling event sources."); 1385 fallthrough; 1386 case 0: 1387 protection = false; 1388 /* src is unused */ 1389 break; 1390 case (1 << PHM_AutoThrottleSource_Thermal): 1391 protection = true; 1392 src = DPM_EVENT_SRC_DIGITAL; 1393 break; 1394 case (1 << PHM_AutoThrottleSource_External): 1395 protection = true; 1396 src = DPM_EVENT_SRC_EXTERNAL; 1397 break; 1398 case (1 << PHM_AutoThrottleSource_External) | 1399 (1 << PHM_AutoThrottleSource_Thermal): 1400 protection = true; 1401 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; 1402 break; 1403 } 1404 /* Order matters - don't enable thermal protection for the wrong source. */ 1405 if (protection) { 1406 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, 1407 DPM_EVENT_SRC, src); 1408 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1409 THERMAL_PROTECTION_DIS, 1410 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1411 PHM_PlatformCaps_ThermalController)); 1412 } else 1413 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1414 THERMAL_PROTECTION_DIS, 1); 1415 } 1416 1417 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, 1418 PHM_AutoThrottleSource source) 1419 { 1420 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1421 1422 if (!(data->active_auto_throttle_sources & (1 << source))) { 1423 data->active_auto_throttle_sources |= 1 << source; 1424 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); 1425 } 1426 return 0; 1427 } 1428 1429 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) 1430 { 1431 return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); 1432 } 1433 1434 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr, 1435 PHM_AutoThrottleSource source) 1436 { 1437 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1438 1439 if (data->active_auto_throttle_sources & (1 << source)) { 1440 data->active_auto_throttle_sources &= ~(1 << source); 1441 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); 1442 } 1443 return 0; 1444 } 1445 1446 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) 1447 { 1448 return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); 1449 } 1450 1451 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) 1452 { 1453 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1454 data->pcie_performance_request = true; 1455 1456 return 0; 1457 } 1458 1459 static int smu7_program_edc_didt_registers(struct pp_hwmgr *hwmgr, 1460 uint32_t *cac_config_regs, 1461 AtomCtrl_EDCLeakgeTable *edc_leakage_table) 1462 { 1463 uint32_t data, i = 0; 1464 1465 while (cac_config_regs[i] != 0xFFFFFFFF) { 1466 data = edc_leakage_table->DIDT_REG[i]; 1467 cgs_write_ind_register(hwmgr->device, 1468 CGS_IND_REG__DIDT, 1469 cac_config_regs[i], 1470 data); 1471 i++; 1472 } 1473 1474 return 0; 1475 } 1476 1477 static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr) 1478 { 1479 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1480 int ret = 0; 1481 1482 if (!data->disable_edc_leakage_controller && 1483 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset && 1484 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) { 1485 ret = smu7_program_edc_didt_registers(hwmgr, 1486 DIDTEDCConfig_P12, 1487 &data->edc_leakage_table); 1488 if (ret) 1489 return ret; 1490 1491 ret = smum_send_msg_to_smc(hwmgr, 1492 (PPSMC_Msg)PPSMC_MSG_EnableEDCController, 1493 NULL); 1494 } else { 1495 ret = smum_send_msg_to_smc(hwmgr, 1496 (PPSMC_Msg)PPSMC_MSG_DisableEDCController, 1497 NULL); 1498 } 1499 1500 return ret; 1501 } 1502 1503 static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1504 { 1505 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1506 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; 1507 int32_t tmp_sclk, count, percentage; 1508 1509 if (golden_dpm_table->mclk_table.count == 1) { 1510 percentage = 70; 1511 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[0].value; 1512 } else { 1513 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / 1514 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 1515 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; 1516 } 1517 1518 tmp_sclk = hwmgr->pstate_mclk * percentage / 100; 1519 1520 if (hwmgr->pp_table_version == PP_TABLE_V0) { 1521 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk = 1522 hwmgr->dyn_state.vddc_dependency_on_sclk; 1523 1524 for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) { 1525 if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) { 1526 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk; 1527 break; 1528 } 1529 } 1530 if (count < 0) 1531 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk; 1532 1533 hwmgr->pstate_sclk_peak = 1534 vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk; 1535 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 1536 struct phm_ppt_v1_information *table_info = 1537 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1538 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk = 1539 table_info->vdd_dep_on_sclk; 1540 1541 for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) { 1542 if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) { 1543 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk; 1544 break; 1545 } 1546 } 1547 if (count < 0) 1548 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk; 1549 1550 hwmgr->pstate_sclk_peak = 1551 vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk; 1552 } 1553 1554 hwmgr->pstate_mclk_peak = 1555 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 1556 1557 /* make sure the output is in Mhz */ 1558 hwmgr->pstate_sclk /= 100; 1559 hwmgr->pstate_mclk /= 100; 1560 hwmgr->pstate_sclk_peak /= 100; 1561 hwmgr->pstate_mclk_peak /= 100; 1562 } 1563 1564 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1565 { 1566 int tmp_result = 0; 1567 int result = 0; 1568 1569 if (smu7_voltage_control(hwmgr)) { 1570 tmp_result = smu7_enable_voltage_control(hwmgr); 1571 PP_ASSERT_WITH_CODE(tmp_result == 0, 1572 "Failed to enable voltage control!", 1573 result = tmp_result); 1574 1575 tmp_result = smu7_construct_voltage_tables(hwmgr); 1576 PP_ASSERT_WITH_CODE((0 == tmp_result), 1577 "Failed to construct voltage tables!", 1578 result = tmp_result); 1579 } 1580 smum_initialize_mc_reg_table(hwmgr); 1581 1582 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1583 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) 1584 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1585 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); 1586 1587 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1588 PHM_PlatformCaps_ThermalController)) 1589 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1590 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); 1591 1592 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr); 1593 PP_ASSERT_WITH_CODE((0 == tmp_result), 1594 "Failed to program static screen threshold parameters!", 1595 result = tmp_result); 1596 1597 tmp_result = smu7_enable_display_gap(hwmgr); 1598 PP_ASSERT_WITH_CODE((0 == tmp_result), 1599 "Failed to enable display gap!", result = tmp_result); 1600 1601 tmp_result = smu7_program_voting_clients(hwmgr); 1602 PP_ASSERT_WITH_CODE((0 == tmp_result), 1603 "Failed to program voting clients!", result = tmp_result); 1604 1605 tmp_result = smum_process_firmware_header(hwmgr); 1606 PP_ASSERT_WITH_CODE((0 == tmp_result), 1607 "Failed to process firmware header!", result = tmp_result); 1608 1609 if (hwmgr->chip_id != CHIP_VEGAM) { 1610 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr); 1611 PP_ASSERT_WITH_CODE((0 == tmp_result), 1612 "Failed to initialize switch from ArbF0 to F1!", 1613 result = tmp_result); 1614 } 1615 1616 result = smu7_setup_default_dpm_tables(hwmgr); 1617 PP_ASSERT_WITH_CODE(0 == result, 1618 "Failed to setup default DPM tables!", return result); 1619 1620 tmp_result = smum_init_smc_table(hwmgr); 1621 PP_ASSERT_WITH_CODE((0 == tmp_result), 1622 "Failed to initialize SMC table!", result = tmp_result); 1623 1624 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr); 1625 PP_ASSERT_WITH_CODE((0 == tmp_result), 1626 "Failed to enable VR hot GPIO interrupt!", result = tmp_result); 1627 1628 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1629 hwmgr->chip_id <= CHIP_VEGAM) { 1630 tmp_result = smu7_notify_has_display(hwmgr); 1631 PP_ASSERT_WITH_CODE((0 == tmp_result), 1632 "Failed to enable display setting!", result = tmp_result); 1633 } else { 1634 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL); 1635 } 1636 1637 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1638 hwmgr->chip_id <= CHIP_VEGAM) { 1639 tmp_result = smu7_populate_edc_leakage_registers(hwmgr); 1640 PP_ASSERT_WITH_CODE((0 == tmp_result), 1641 "Failed to populate edc leakage registers!", result = tmp_result); 1642 } 1643 1644 tmp_result = smu7_enable_sclk_control(hwmgr); 1645 PP_ASSERT_WITH_CODE((0 == tmp_result), 1646 "Failed to enable SCLK control!", result = tmp_result); 1647 1648 tmp_result = smu7_enable_smc_voltage_controller(hwmgr); 1649 PP_ASSERT_WITH_CODE((0 == tmp_result), 1650 "Failed to enable voltage control!", result = tmp_result); 1651 1652 tmp_result = smu7_enable_ulv(hwmgr); 1653 PP_ASSERT_WITH_CODE((0 == tmp_result), 1654 "Failed to enable ULV!", result = tmp_result); 1655 1656 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr); 1657 PP_ASSERT_WITH_CODE((0 == tmp_result), 1658 "Failed to enable deep sleep master switch!", result = tmp_result); 1659 1660 tmp_result = smu7_enable_didt_config(hwmgr); 1661 PP_ASSERT_WITH_CODE((tmp_result == 0), 1662 "Failed to enable deep sleep master switch!", result = tmp_result); 1663 1664 tmp_result = smu7_start_dpm(hwmgr); 1665 PP_ASSERT_WITH_CODE((0 == tmp_result), 1666 "Failed to start DPM!", result = tmp_result); 1667 1668 tmp_result = smu7_enable_smc_cac(hwmgr); 1669 PP_ASSERT_WITH_CODE((0 == tmp_result), 1670 "Failed to enable SMC CAC!", result = tmp_result); 1671 1672 tmp_result = smu7_enable_power_containment(hwmgr); 1673 PP_ASSERT_WITH_CODE((0 == tmp_result), 1674 "Failed to enable power containment!", result = tmp_result); 1675 1676 tmp_result = smu7_power_control_set_level(hwmgr); 1677 PP_ASSERT_WITH_CODE((0 == tmp_result), 1678 "Failed to power control set level!", result = tmp_result); 1679 1680 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr); 1681 PP_ASSERT_WITH_CODE((0 == tmp_result), 1682 "Failed to enable thermal auto throttle!", result = tmp_result); 1683 1684 tmp_result = smu7_pcie_performance_request(hwmgr); 1685 PP_ASSERT_WITH_CODE((0 == tmp_result), 1686 "pcie performance request failed!", result = tmp_result); 1687 1688 smu7_populate_umdpstate_clocks(hwmgr); 1689 1690 return 0; 1691 } 1692 1693 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) 1694 { 1695 if (!hwmgr->avfs_supported) 1696 return 0; 1697 1698 if (enable) { 1699 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 1700 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { 1701 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 1702 hwmgr, PPSMC_MSG_EnableAvfs, NULL), 1703 "Failed to enable AVFS!", 1704 return -EINVAL); 1705 } 1706 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 1707 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { 1708 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 1709 hwmgr, PPSMC_MSG_DisableAvfs, NULL), 1710 "Failed to disable AVFS!", 1711 return -EINVAL); 1712 } 1713 1714 return 0; 1715 } 1716 1717 static int smu7_update_avfs(struct pp_hwmgr *hwmgr) 1718 { 1719 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1720 1721 if (!hwmgr->avfs_supported) 1722 return 0; 1723 1724 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 1725 smu7_avfs_control(hwmgr, false); 1726 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 1727 smu7_avfs_control(hwmgr, false); 1728 smu7_avfs_control(hwmgr, true); 1729 } else { 1730 smu7_avfs_control(hwmgr, true); 1731 } 1732 1733 return 0; 1734 } 1735 1736 static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 1737 { 1738 int tmp_result, result = 0; 1739 1740 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1741 PHM_PlatformCaps_ThermalController)) 1742 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1743 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1); 1744 1745 tmp_result = smu7_disable_power_containment(hwmgr); 1746 PP_ASSERT_WITH_CODE((tmp_result == 0), 1747 "Failed to disable power containment!", result = tmp_result); 1748 1749 tmp_result = smu7_disable_smc_cac(hwmgr); 1750 PP_ASSERT_WITH_CODE((tmp_result == 0), 1751 "Failed to disable SMC CAC!", result = tmp_result); 1752 1753 tmp_result = smu7_disable_didt_config(hwmgr); 1754 PP_ASSERT_WITH_CODE((tmp_result == 0), 1755 "Failed to disable DIDT!", result = tmp_result); 1756 1757 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1758 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0); 1759 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1760 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0); 1761 1762 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr); 1763 PP_ASSERT_WITH_CODE((tmp_result == 0), 1764 "Failed to disable thermal auto throttle!", result = tmp_result); 1765 1766 tmp_result = smu7_avfs_control(hwmgr, false); 1767 PP_ASSERT_WITH_CODE((tmp_result == 0), 1768 "Failed to disable AVFS!", result = tmp_result); 1769 1770 tmp_result = smu7_stop_dpm(hwmgr); 1771 PP_ASSERT_WITH_CODE((tmp_result == 0), 1772 "Failed to stop DPM!", result = tmp_result); 1773 1774 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr); 1775 PP_ASSERT_WITH_CODE((tmp_result == 0), 1776 "Failed to disable deep sleep master switch!", result = tmp_result); 1777 1778 tmp_result = smu7_disable_ulv(hwmgr); 1779 PP_ASSERT_WITH_CODE((tmp_result == 0), 1780 "Failed to disable ULV!", result = tmp_result); 1781 1782 tmp_result = smu7_clear_voting_clients(hwmgr); 1783 PP_ASSERT_WITH_CODE((tmp_result == 0), 1784 "Failed to clear voting clients!", result = tmp_result); 1785 1786 tmp_result = smu7_reset_to_default(hwmgr); 1787 PP_ASSERT_WITH_CODE((tmp_result == 0), 1788 "Failed to reset to default!", result = tmp_result); 1789 1790 tmp_result = smum_stop_smc(hwmgr); 1791 PP_ASSERT_WITH_CODE((tmp_result == 0), 1792 "Failed to stop smc!", result = tmp_result); 1793 1794 tmp_result = smu7_force_switch_to_arbf0(hwmgr); 1795 PP_ASSERT_WITH_CODE((tmp_result == 0), 1796 "Failed to force to switch arbf0!", result = tmp_result); 1797 1798 return result; 1799 } 1800 1801 static bool intel_core_rkl_chk(void) 1802 { 1803 #if IS_ENABLED(CONFIG_X86_64) 1804 struct cpuinfo_x86 *c = &cpu_data(0); 1805 1806 return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE); 1807 #else 1808 return false; 1809 #endif 1810 } 1811 1812 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 1813 { 1814 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1815 struct phm_ppt_v1_information *table_info = 1816 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1817 struct amdgpu_device *adev = hwmgr->adev; 1818 uint8_t tmp1, tmp2; 1819 uint16_t tmp3 = 0; 1820 1821 data->dll_default_on = false; 1822 data->mclk_dpm0_activity_target = 0xa; 1823 data->vddc_vddgfx_delta = 300; 1824 data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT; 1825 data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT; 1826 data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0; 1827 data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1; 1828 data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2; 1829 data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3; 1830 data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4; 1831 data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5; 1832 data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6; 1833 data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7; 1834 1835 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 1836 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 1837 data->pcie_dpm_key_disabled = 1838 intel_core_rkl_chk() || !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 1839 /* need to set voltage control types before EVV patching */ 1840 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE; 1841 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE; 1842 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE; 1843 data->enable_tdc_limit_feature = true; 1844 data->enable_pkg_pwr_tracking_feature = true; 1845 data->force_pcie_gen = PP_PCIEGenInvalid; 1846 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; 1847 data->current_profile_setting.bupdate_sclk = 1; 1848 data->current_profile_setting.sclk_up_hyst = 0; 1849 data->current_profile_setting.sclk_down_hyst = 100; 1850 data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT; 1851 data->current_profile_setting.bupdate_mclk = 1; 1852 if (hwmgr->chip_id >= CHIP_POLARIS10) { 1853 if (adev->gmc.vram_width == 256) { 1854 data->current_profile_setting.mclk_up_hyst = 10; 1855 data->current_profile_setting.mclk_down_hyst = 60; 1856 data->current_profile_setting.mclk_activity = 25; 1857 } else if (adev->gmc.vram_width == 128) { 1858 data->current_profile_setting.mclk_up_hyst = 5; 1859 data->current_profile_setting.mclk_down_hyst = 16; 1860 data->current_profile_setting.mclk_activity = 20; 1861 } else if (adev->gmc.vram_width == 64) { 1862 data->current_profile_setting.mclk_up_hyst = 3; 1863 data->current_profile_setting.mclk_down_hyst = 16; 1864 data->current_profile_setting.mclk_activity = 20; 1865 } 1866 } else { 1867 data->current_profile_setting.mclk_up_hyst = 0; 1868 data->current_profile_setting.mclk_down_hyst = 100; 1869 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT; 1870 } 1871 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1872 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1873 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1874 1875 if (hwmgr->chip_id == CHIP_HAWAII) { 1876 data->thermal_temp_setting.temperature_low = 94500; 1877 data->thermal_temp_setting.temperature_high = 95000; 1878 data->thermal_temp_setting.temperature_shutdown = 104000; 1879 } else { 1880 data->thermal_temp_setting.temperature_low = 99500; 1881 data->thermal_temp_setting.temperature_high = 100000; 1882 data->thermal_temp_setting.temperature_shutdown = 104000; 1883 } 1884 1885 data->fast_watermark_threshold = 100; 1886 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1887 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 1888 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1889 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1890 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 1891 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1892 1893 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1894 PHM_PlatformCaps_ControlVDDGFX)) { 1895 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1896 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { 1897 data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1898 } 1899 } 1900 1901 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1902 PHM_PlatformCaps_EnableMVDDControl)) { 1903 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1904 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 1905 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1906 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1907 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 1908 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1909 } 1910 1911 if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) 1912 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1913 PHM_PlatformCaps_ControlVDDGFX); 1914 1915 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1916 PHM_PlatformCaps_ControlVDDCI)) { 1917 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1918 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 1919 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1920 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1921 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 1922 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1923 } 1924 1925 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) 1926 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1927 PHM_PlatformCaps_EnableMVDDControl); 1928 1929 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) 1930 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1931 PHM_PlatformCaps_ControlVDDCI); 1932 1933 data->vddc_phase_shed_control = 1; 1934 if ((hwmgr->chip_id == CHIP_POLARIS12) || 1935 ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) || 1936 ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 1937 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) || 1938 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) { 1939 if (data->voltage_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 1940 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2, 1941 &tmp3); 1942 tmp3 = (tmp3 >> 5) & 0x3; 1943 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3; 1944 } 1945 } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 1946 data->vddc_phase_shed_control = 1; 1947 } 1948 1949 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) 1950 && (table_info->cac_dtp_table->usClockStretchAmount != 0)) 1951 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1952 PHM_PlatformCaps_ClockStretcher); 1953 1954 data->pcie_gen_performance.max = PP_PCIEGen1; 1955 data->pcie_gen_performance.min = PP_PCIEGen3; 1956 data->pcie_gen_power_saving.max = PP_PCIEGen1; 1957 data->pcie_gen_power_saving.min = PP_PCIEGen3; 1958 data->pcie_lane_performance.max = 0; 1959 data->pcie_lane_performance.min = 16; 1960 data->pcie_lane_power_saving.max = 0; 1961 data->pcie_lane_power_saving.min = 16; 1962 1963 1964 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 1965 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1966 PHM_PlatformCaps_UVDPowerGating); 1967 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 1968 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1969 PHM_PlatformCaps_VCEPowerGating); 1970 1971 data->disable_edc_leakage_controller = true; 1972 if (((adev->asic_type == CHIP_POLARIS10) && hwmgr->is_kicker) || 1973 ((adev->asic_type == CHIP_POLARIS11) && hwmgr->is_kicker) || 1974 (adev->asic_type == CHIP_POLARIS12) || 1975 (adev->asic_type == CHIP_VEGAM)) 1976 data->disable_edc_leakage_controller = false; 1977 1978 if (!atomctrl_is_asic_internal_ss_supported(hwmgr)) { 1979 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1980 PHM_PlatformCaps_MemorySpreadSpectrumSupport); 1981 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1982 PHM_PlatformCaps_EngineSpreadSpectrumSupport); 1983 } 1984 1985 if ((adev->pdev->device == 0x699F) && 1986 (adev->pdev->revision == 0xCF)) { 1987 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1988 PHM_PlatformCaps_PowerContainment); 1989 data->enable_tdc_limit_feature = false; 1990 data->enable_pkg_pwr_tracking_feature = false; 1991 data->disable_edc_leakage_controller = true; 1992 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1993 PHM_PlatformCaps_ClockStretcher); 1994 } 1995 } 1996 1997 static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr) 1998 { 1999 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2000 struct amdgpu_device *adev = hwmgr->adev; 2001 uint32_t asicrev1, evv_revision, max = 0, min = 0; 2002 2003 atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB, STRAP_EVV_REVISION_MSB, 2004 &evv_revision); 2005 2006 atomctrl_read_efuse(hwmgr, 568, 579, &asicrev1); 2007 2008 if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) || 2009 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) { 2010 min = 1200; 2011 max = 2500; 2012 } else if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 2013 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) { 2014 min = 900; 2015 max= 2100; 2016 } else if (hwmgr->chip_id == CHIP_POLARIS10) { 2017 if (adev->pdev->subsystem_vendor == 0x106B) { 2018 min = 1000; 2019 max = 2300; 2020 } else { 2021 if (evv_revision == 0) { 2022 min = 1000; 2023 max = 2300; 2024 } else if (evv_revision == 1) { 2025 if (asicrev1 == 326) { 2026 min = 1200; 2027 max = 2500; 2028 /* TODO: PATCH RO in VBIOS */ 2029 } else { 2030 min = 1200; 2031 max = 2000; 2032 } 2033 } else if (evv_revision == 2) { 2034 min = 1200; 2035 max = 2500; 2036 } 2037 } 2038 } else { 2039 min = 1100; 2040 max = 2100; 2041 } 2042 2043 data->ro_range_minimum = min; 2044 data->ro_range_maximum = max; 2045 2046 /* TODO: PATCH RO in VBIOS here */ 2047 2048 return 0; 2049 } 2050 2051 /** 2052 * smu7_get_evv_voltages - Get Leakage VDDC based on leakage ID. 2053 * 2054 * @hwmgr: the address of the powerplay hardware manager. 2055 * Return: always 0 2056 */ 2057 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) 2058 { 2059 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2060 uint16_t vv_id; 2061 uint16_t vddc = 0; 2062 uint16_t vddgfx = 0; 2063 uint16_t i, j; 2064 uint32_t sclk = 0; 2065 struct phm_ppt_v1_information *table_info = 2066 (struct phm_ppt_v1_information *)hwmgr->pptable; 2067 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; 2068 2069 if (hwmgr->chip_id == CHIP_POLARIS10 || 2070 hwmgr->chip_id == CHIP_POLARIS11 || 2071 hwmgr->chip_id == CHIP_POLARIS12) 2072 smu7_calculate_ro_range(hwmgr); 2073 2074 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 2075 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 2076 2077 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2078 if ((hwmgr->pp_table_version == PP_TABLE_V1) 2079 && !phm_get_sclk_for_voltage_evv(hwmgr, 2080 table_info->vddgfx_lookup_table, vv_id, &sclk)) { 2081 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2082 PHM_PlatformCaps_ClockStretcher)) { 2083 sclk_table = table_info->vdd_dep_on_sclk; 2084 2085 for (j = 1; j < sclk_table->count; j++) { 2086 if (sclk_table->entries[j].clk == sclk && 2087 sclk_table->entries[j].cks_enable == 0) { 2088 sclk += 5000; 2089 break; 2090 } 2091 } 2092 } 2093 if (0 == atomctrl_get_voltage_evv_on_sclk 2094 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, 2095 vv_id, &vddgfx)) { 2096 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ 2097 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL); 2098 2099 /* the voltage should not be zero nor equal to leakage ID */ 2100 if (vddgfx != 0 && vddgfx != vv_id) { 2101 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; 2102 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id; 2103 data->vddcgfx_leakage.count++; 2104 } 2105 } else { 2106 pr_info("Error retrieving EVV voltage value!\n"); 2107 } 2108 } 2109 } else { 2110 if ((hwmgr->pp_table_version == PP_TABLE_V0) 2111 || !phm_get_sclk_for_voltage_evv(hwmgr, 2112 table_info->vddc_lookup_table, vv_id, &sclk)) { 2113 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2114 PHM_PlatformCaps_ClockStretcher)) { 2115 if (table_info == NULL) 2116 return -EINVAL; 2117 sclk_table = table_info->vdd_dep_on_sclk; 2118 2119 for (j = 1; j < sclk_table->count; j++) { 2120 if (sclk_table->entries[j].clk == sclk && 2121 sclk_table->entries[j].cks_enable == 0) { 2122 sclk += 5000; 2123 break; 2124 } 2125 } 2126 } 2127 2128 if (phm_get_voltage_evv_on_sclk(hwmgr, 2129 VOLTAGE_TYPE_VDDC, 2130 sclk, vv_id, &vddc) == 0) { 2131 if (vddc >= 2000 || vddc == 0) 2132 return -EINVAL; 2133 } else { 2134 pr_debug("failed to retrieving EVV voltage!\n"); 2135 continue; 2136 } 2137 2138 /* the voltage should not be zero nor equal to leakage ID */ 2139 if (vddc != 0 && vddc != vv_id) { 2140 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc); 2141 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; 2142 data->vddc_leakage.count++; 2143 } 2144 } 2145 } 2146 } 2147 2148 return 0; 2149 } 2150 2151 /** 2152 * smu7_patch_ppt_v1_with_vdd_leakage - Change virtual leakage voltage to actual value. 2153 * 2154 * @hwmgr: the address of the powerplay hardware manager. 2155 * @voltage: pointer to changing voltage 2156 * @leakage_table: pointer to leakage table 2157 */ 2158 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr, 2159 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table) 2160 { 2161 uint32_t index; 2162 2163 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 2164 for (index = 0; index < leakage_table->count; index++) { 2165 /* if this voltage matches a leakage voltage ID */ 2166 /* patch with actual leakage voltage */ 2167 if (leakage_table->leakage_id[index] == *voltage) { 2168 *voltage = leakage_table->actual_voltage[index]; 2169 break; 2170 } 2171 } 2172 2173 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 2174 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 2175 } 2176 2177 /** 2178 * smu7_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. 2179 * 2180 * @hwmgr: the address of the powerplay hardware manager. 2181 * @lookup_table: pointer to voltage lookup table 2182 * @leakage_table: pointer to leakage table 2183 * Return: always 0 2184 */ 2185 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, 2186 phm_ppt_v1_voltage_lookup_table *lookup_table, 2187 struct smu7_leakage_voltage *leakage_table) 2188 { 2189 uint32_t i; 2190 2191 for (i = 0; i < lookup_table->count; i++) 2192 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, 2193 &lookup_table->entries[i].us_vdd, leakage_table); 2194 2195 return 0; 2196 } 2197 2198 static int smu7_patch_clock_voltage_limits_with_vddc_leakage( 2199 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table, 2200 uint16_t *vddc) 2201 { 2202 struct phm_ppt_v1_information *table_info = 2203 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2204 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); 2205 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = 2206 table_info->max_clock_voltage_on_dc.vddc; 2207 return 0; 2208 } 2209 2210 static int smu7_patch_voltage_dependency_tables_with_lookup_table( 2211 struct pp_hwmgr *hwmgr) 2212 { 2213 uint8_t entry_id; 2214 uint8_t voltage_id; 2215 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2216 struct phm_ppt_v1_information *table_info = 2217 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2218 2219 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 2220 table_info->vdd_dep_on_sclk; 2221 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = 2222 table_info->vdd_dep_on_mclk; 2223 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 2224 table_info->mm_dep_table; 2225 2226 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2227 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2228 voltage_id = sclk_table->entries[entry_id].vddInd; 2229 sclk_table->entries[entry_id].vddgfx = 2230 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd; 2231 } 2232 } else { 2233 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2234 voltage_id = sclk_table->entries[entry_id].vddInd; 2235 sclk_table->entries[entry_id].vddc = 2236 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2237 } 2238 } 2239 2240 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 2241 voltage_id = mclk_table->entries[entry_id].vddInd; 2242 mclk_table->entries[entry_id].vddc = 2243 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2244 } 2245 2246 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { 2247 voltage_id = mm_table->entries[entry_id].vddcInd; 2248 mm_table->entries[entry_id].vddc = 2249 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2250 } 2251 2252 return 0; 2253 2254 } 2255 2256 static int phm_add_voltage(struct pp_hwmgr *hwmgr, 2257 phm_ppt_v1_voltage_lookup_table *look_up_table, 2258 phm_ppt_v1_voltage_lookup_record *record) 2259 { 2260 uint32_t i; 2261 2262 PP_ASSERT_WITH_CODE((NULL != look_up_table), 2263 "Lookup Table empty.", return -EINVAL); 2264 PP_ASSERT_WITH_CODE((0 != look_up_table->count), 2265 "Lookup Table empty.", return -EINVAL); 2266 2267 i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); 2268 PP_ASSERT_WITH_CODE((i >= look_up_table->count), 2269 "Lookup Table is full.", return -EINVAL); 2270 2271 /* This is to avoid entering duplicate calculated records. */ 2272 for (i = 0; i < look_up_table->count; i++) { 2273 if (look_up_table->entries[i].us_vdd == record->us_vdd) { 2274 if (look_up_table->entries[i].us_calculated == 1) 2275 return 0; 2276 break; 2277 } 2278 } 2279 2280 look_up_table->entries[i].us_calculated = 1; 2281 look_up_table->entries[i].us_vdd = record->us_vdd; 2282 look_up_table->entries[i].us_cac_low = record->us_cac_low; 2283 look_up_table->entries[i].us_cac_mid = record->us_cac_mid; 2284 look_up_table->entries[i].us_cac_high = record->us_cac_high; 2285 /* Only increment the count when we're appending, not replacing duplicate entry. */ 2286 if (i == look_up_table->count) 2287 look_up_table->count++; 2288 2289 return 0; 2290 } 2291 2292 2293 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) 2294 { 2295 uint8_t entry_id; 2296 struct phm_ppt_v1_voltage_lookup_record v_record; 2297 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2298 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 2299 2300 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; 2301 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; 2302 2303 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2304 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2305 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15)) 2306 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + 2307 sclk_table->entries[entry_id].vdd_offset - 0xFFFF; 2308 else 2309 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + 2310 sclk_table->entries[entry_id].vdd_offset; 2311 2312 sclk_table->entries[entry_id].vddc = 2313 v_record.us_cac_low = v_record.us_cac_mid = 2314 v_record.us_cac_high = v_record.us_vdd; 2315 2316 phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); 2317 } 2318 2319 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 2320 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15)) 2321 v_record.us_vdd = mclk_table->entries[entry_id].vddc + 2322 mclk_table->entries[entry_id].vdd_offset - 0xFFFF; 2323 else 2324 v_record.us_vdd = mclk_table->entries[entry_id].vddc + 2325 mclk_table->entries[entry_id].vdd_offset; 2326 2327 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low = 2328 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; 2329 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); 2330 } 2331 } 2332 return 0; 2333 } 2334 2335 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) 2336 { 2337 uint8_t entry_id; 2338 struct phm_ppt_v1_voltage_lookup_record v_record; 2339 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2340 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 2341 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; 2342 2343 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2344 for (entry_id = 0; entry_id < mm_table->count; entry_id++) { 2345 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15)) 2346 v_record.us_vdd = mm_table->entries[entry_id].vddc + 2347 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF; 2348 else 2349 v_record.us_vdd = mm_table->entries[entry_id].vddc + 2350 mm_table->entries[entry_id].vddgfx_offset; 2351 2352 /* Add the calculated VDDGFX to the VDDGFX lookup table */ 2353 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low = 2354 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; 2355 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); 2356 } 2357 } 2358 return 0; 2359 } 2360 2361 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, 2362 struct phm_ppt_v1_voltage_lookup_table *lookup_table) 2363 { 2364 uint32_t table_size, i, j; 2365 table_size = lookup_table->count; 2366 2367 PP_ASSERT_WITH_CODE(0 != lookup_table->count, 2368 "Lookup table is empty", return -EINVAL); 2369 2370 /* Sorting voltages */ 2371 for (i = 0; i < table_size - 1; i++) { 2372 for (j = i + 1; j > 0; j--) { 2373 if (lookup_table->entries[j].us_vdd < 2374 lookup_table->entries[j - 1].us_vdd) { 2375 swap(lookup_table->entries[j - 1], 2376 lookup_table->entries[j]); 2377 } 2378 } 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr) 2385 { 2386 int result = 0; 2387 int tmp_result; 2388 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2389 struct phm_ppt_v1_information *table_info = 2390 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2391 2392 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2393 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, 2394 table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage)); 2395 if (tmp_result != 0) 2396 result = tmp_result; 2397 2398 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, 2399 &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage)); 2400 } else { 2401 2402 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, 2403 table_info->vddc_lookup_table, &(data->vddc_leakage)); 2404 if (tmp_result) 2405 result = tmp_result; 2406 2407 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, 2408 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); 2409 if (tmp_result) 2410 result = tmp_result; 2411 } 2412 2413 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr); 2414 if (tmp_result) 2415 result = tmp_result; 2416 2417 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr); 2418 if (tmp_result) 2419 result = tmp_result; 2420 2421 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr); 2422 if (tmp_result) 2423 result = tmp_result; 2424 2425 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table); 2426 if (tmp_result) 2427 result = tmp_result; 2428 2429 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); 2430 if (tmp_result) 2431 result = tmp_result; 2432 2433 return result; 2434 } 2435 2436 static int smu7_find_highest_vddc(struct pp_hwmgr *hwmgr) 2437 { 2438 struct phm_ppt_v1_information *table_info = 2439 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2440 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 2441 table_info->vdd_dep_on_sclk; 2442 struct phm_ppt_v1_voltage_lookup_table *lookup_table = 2443 table_info->vddc_lookup_table; 2444 uint16_t highest_voltage; 2445 uint32_t i; 2446 2447 highest_voltage = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 2448 2449 for (i = 0; i < lookup_table->count; i++) { 2450 if (lookup_table->entries[i].us_vdd < ATOM_VIRTUAL_VOLTAGE_ID0 && 2451 lookup_table->entries[i].us_vdd > highest_voltage) 2452 highest_voltage = lookup_table->entries[i].us_vdd; 2453 } 2454 2455 return highest_voltage; 2456 } 2457 2458 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr) 2459 { 2460 struct phm_ppt_v1_information *table_info = 2461 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2462 2463 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 2464 table_info->vdd_dep_on_sclk; 2465 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = 2466 table_info->vdd_dep_on_mclk; 2467 2468 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, 2469 "VDD dependency on SCLK table is missing.", 2470 return -EINVAL); 2471 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, 2472 "VDD dependency on SCLK table has to have is missing.", 2473 return -EINVAL); 2474 2475 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, 2476 "VDD dependency on MCLK table is missing", 2477 return -EINVAL); 2478 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 2479 "VDD dependency on MCLK table has to have is missing.", 2480 return -EINVAL); 2481 2482 table_info->max_clock_voltage_on_ac.sclk = 2483 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; 2484 table_info->max_clock_voltage_on_ac.mclk = 2485 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 2486 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) 2487 table_info->max_clock_voltage_on_ac.vddc = 2488 smu7_find_highest_vddc(hwmgr); 2489 else 2490 table_info->max_clock_voltage_on_ac.vddc = 2491 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 2492 table_info->max_clock_voltage_on_ac.vddci = 2493 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; 2494 2495 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; 2496 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; 2497 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc; 2498 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci; 2499 2500 return 0; 2501 } 2502 2503 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) 2504 { 2505 struct phm_ppt_v1_information *table_info = 2506 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2507 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 2508 struct phm_ppt_v1_voltage_lookup_table *lookup_table; 2509 uint32_t i; 2510 uint32_t hw_revision, sub_vendor_id, sub_sys_id; 2511 struct amdgpu_device *adev = hwmgr->adev; 2512 2513 if (table_info != NULL) { 2514 dep_mclk_table = table_info->vdd_dep_on_mclk; 2515 lookup_table = table_info->vddc_lookup_table; 2516 } else 2517 return 0; 2518 2519 hw_revision = adev->pdev->revision; 2520 sub_sys_id = adev->pdev->subsystem_device; 2521 sub_vendor_id = adev->pdev->subsystem_vendor; 2522 2523 if (adev->pdev->device == 0x67DF && hw_revision == 0xC7 && 2524 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) || 2525 (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) || 2526 (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) { 2527 2528 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 2529 CGS_IND_REG__SMC, 2530 PWR_CKS_CNTL, 2531 CKS_STRETCH_AMOUNT, 2532 0x3); 2533 2534 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000) 2535 return 0; 2536 2537 for (i = 0; i < lookup_table->count; i++) { 2538 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) { 2539 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i; 2540 return 0; 2541 } 2542 } 2543 } 2544 return 0; 2545 } 2546 2547 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) 2548 { 2549 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; 2550 uint32_t temp_reg; 2551 struct phm_ppt_v1_information *table_info = 2552 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2553 2554 2555 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { 2556 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); 2557 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { 2558 case 0: 2559 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); 2560 break; 2561 case 1: 2562 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); 2563 break; 2564 case 2: 2565 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); 2566 break; 2567 case 3: 2568 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); 2569 break; 2570 case 4: 2571 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); 2572 break; 2573 default: 2574 break; 2575 } 2576 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); 2577 } 2578 2579 if (table_info == NULL) 2580 return 0; 2581 2582 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 && 2583 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) { 2584 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit = 2585 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; 2586 2587 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit = 2588 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; 2589 2590 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1; 2591 2592 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100; 2593 2594 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit = 2595 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; 2596 2597 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1; 2598 2599 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ? 2600 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0; 2601 2602 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp; 2603 table_info->cac_dtp_table->usOperatingTempStep = 1; 2604 table_info->cac_dtp_table->usOperatingTempHyst = 1; 2605 2606 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = 2607 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; 2608 2609 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = 2610 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM; 2611 2612 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit = 2613 table_info->cac_dtp_table->usOperatingTempMinLimit; 2614 2615 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit = 2616 table_info->cac_dtp_table->usOperatingTempMaxLimit; 2617 2618 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = 2619 table_info->cac_dtp_table->usDefaultTargetOperatingTemp; 2620 2621 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep = 2622 table_info->cac_dtp_table->usOperatingTempStep; 2623 2624 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = 2625 table_info->cac_dtp_table->usTargetOperatingTemp; 2626 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK) 2627 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2628 PHM_PlatformCaps_ODFuzzyFanControlSupport); 2629 } 2630 2631 return 0; 2632 } 2633 2634 /** 2635 * smu7_patch_ppt_v0_with_vdd_leakage - Change virtual leakage voltage to actual value. 2636 * 2637 * @hwmgr: the address of the powerplay hardware manager. 2638 * @voltage: pointer to changing voltage 2639 * @leakage_table: pointer to leakage table 2640 */ 2641 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr, 2642 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table) 2643 { 2644 uint32_t index; 2645 2646 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 2647 for (index = 0; index < leakage_table->count; index++) { 2648 /* if this voltage matches a leakage voltage ID */ 2649 /* patch with actual leakage voltage */ 2650 if (leakage_table->leakage_id[index] == *voltage) { 2651 *voltage = leakage_table->actual_voltage[index]; 2652 break; 2653 } 2654 } 2655 2656 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 2657 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 2658 } 2659 2660 2661 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr, 2662 struct phm_clock_voltage_dependency_table *tab) 2663 { 2664 uint16_t i; 2665 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2666 2667 if (tab) 2668 for (i = 0; i < tab->count; i++) 2669 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2670 &data->vddc_leakage); 2671 2672 return 0; 2673 } 2674 2675 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr, 2676 struct phm_clock_voltage_dependency_table *tab) 2677 { 2678 uint16_t i; 2679 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2680 2681 if (tab) 2682 for (i = 0; i < tab->count; i++) 2683 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2684 &data->vddci_leakage); 2685 2686 return 0; 2687 } 2688 2689 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr, 2690 struct phm_vce_clock_voltage_dependency_table *tab) 2691 { 2692 uint16_t i; 2693 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2694 2695 if (tab) 2696 for (i = 0; i < tab->count; i++) 2697 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2698 &data->vddc_leakage); 2699 2700 return 0; 2701 } 2702 2703 2704 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr, 2705 struct phm_uvd_clock_voltage_dependency_table *tab) 2706 { 2707 uint16_t i; 2708 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2709 2710 if (tab) 2711 for (i = 0; i < tab->count; i++) 2712 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2713 &data->vddc_leakage); 2714 2715 return 0; 2716 } 2717 2718 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr, 2719 struct phm_phase_shedding_limits_table *tab) 2720 { 2721 uint16_t i; 2722 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2723 2724 if (tab) 2725 for (i = 0; i < tab->count; i++) 2726 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage, 2727 &data->vddc_leakage); 2728 2729 return 0; 2730 } 2731 2732 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr, 2733 struct phm_samu_clock_voltage_dependency_table *tab) 2734 { 2735 uint16_t i; 2736 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2737 2738 if (tab) 2739 for (i = 0; i < tab->count; i++) 2740 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2741 &data->vddc_leakage); 2742 2743 return 0; 2744 } 2745 2746 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr, 2747 struct phm_acp_clock_voltage_dependency_table *tab) 2748 { 2749 uint16_t i; 2750 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2751 2752 if (tab) 2753 for (i = 0; i < tab->count; i++) 2754 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2755 &data->vddc_leakage); 2756 2757 return 0; 2758 } 2759 2760 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, 2761 struct phm_clock_and_voltage_limits *tab) 2762 { 2763 uint32_t vddc, vddci; 2764 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2765 2766 if (tab) { 2767 vddc = tab->vddc; 2768 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, 2769 &data->vddc_leakage); 2770 tab->vddc = vddc; 2771 vddci = tab->vddci; 2772 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, 2773 &data->vddci_leakage); 2774 tab->vddci = vddci; 2775 } 2776 2777 return 0; 2778 } 2779 2780 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab) 2781 { 2782 uint32_t i; 2783 uint32_t vddc; 2784 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2785 2786 if (tab) { 2787 for (i = 0; i < tab->count; i++) { 2788 vddc = (uint32_t)(tab->entries[i].Vddc); 2789 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage); 2790 tab->entries[i].Vddc = (uint16_t)vddc; 2791 } 2792 } 2793 2794 return 0; 2795 } 2796 2797 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr) 2798 { 2799 int tmp; 2800 2801 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); 2802 if (tmp) 2803 return -EINVAL; 2804 2805 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); 2806 if (tmp) 2807 return -EINVAL; 2808 2809 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 2810 if (tmp) 2811 return -EINVAL; 2812 2813 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); 2814 if (tmp) 2815 return -EINVAL; 2816 2817 tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table); 2818 if (tmp) 2819 return -EINVAL; 2820 2821 tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table); 2822 if (tmp) 2823 return -EINVAL; 2824 2825 tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table); 2826 if (tmp) 2827 return -EINVAL; 2828 2829 tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table); 2830 if (tmp) 2831 return -EINVAL; 2832 2833 tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table); 2834 if (tmp) 2835 return -EINVAL; 2836 2837 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac); 2838 if (tmp) 2839 return -EINVAL; 2840 2841 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); 2842 if (tmp) 2843 return -EINVAL; 2844 2845 tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table); 2846 if (tmp) 2847 return -EINVAL; 2848 2849 return 0; 2850 } 2851 2852 2853 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) 2854 { 2855 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2856 2857 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 2858 struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 2859 struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk; 2860 2861 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, 2862 "VDDC dependency on SCLK table is missing. This table is mandatory", 2863 return -EINVAL); 2864 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, 2865 "VDDC dependency on SCLK table has to have is missing. This table is mandatory", 2866 return -EINVAL); 2867 2868 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL, 2869 "VDDC dependency on MCLK table is missing. This table is mandatory", 2870 return -EINVAL); 2871 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1, 2872 "VDD dependency on MCLK table has to have is missing. This table is mandatory", 2873 return -EINVAL); 2874 2875 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v; 2876 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 2877 2878 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = 2879 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 2880 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = 2881 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk; 2882 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = 2883 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 2884 2885 if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) { 2886 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v; 2887 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 2888 } 2889 2890 if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1) 2891 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v; 2892 2893 return 0; 2894 } 2895 2896 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 2897 { 2898 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 2899 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 2900 kfree(hwmgr->backend); 2901 hwmgr->backend = NULL; 2902 2903 return 0; 2904 } 2905 2906 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr) 2907 { 2908 uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id; 2909 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2910 int i; 2911 2912 if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) { 2913 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 2914 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 2915 if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci, 2916 virtual_voltage_id, 2917 efuse_voltage_id) == 0) { 2918 if (vddc != 0 && vddc != virtual_voltage_id) { 2919 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; 2920 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; 2921 data->vddc_leakage.count++; 2922 } 2923 if (vddci != 0 && vddci != virtual_voltage_id) { 2924 data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci; 2925 data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id; 2926 data->vddci_leakage.count++; 2927 } 2928 } 2929 } 2930 } 2931 return 0; 2932 } 2933 2934 #define LEAKAGE_ID_MSB 463 2935 #define LEAKAGE_ID_LSB 454 2936 2937 static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr) 2938 { 2939 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2940 uint32_t efuse; 2941 uint16_t offset; 2942 int ret = 0; 2943 2944 if (data->disable_edc_leakage_controller) 2945 return 0; 2946 2947 ret = atomctrl_get_edc_hilo_leakage_offset_table(hwmgr, 2948 &data->edc_hilo_leakage_offset_from_vbios); 2949 if (ret) 2950 return ret; 2951 2952 if (data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset && 2953 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) { 2954 atomctrl_read_efuse(hwmgr, LEAKAGE_ID_LSB, LEAKAGE_ID_MSB, &efuse); 2955 if (efuse < data->edc_hilo_leakage_offset_from_vbios.usHiLoLeakageThreshold) 2956 offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset; 2957 else 2958 offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset; 2959 2960 ret = atomctrl_get_edc_leakage_table(hwmgr, 2961 &data->edc_leakage_table, 2962 offset); 2963 if (ret) 2964 return ret; 2965 } 2966 2967 return ret; 2968 } 2969 2970 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 2971 { 2972 struct smu7_hwmgr *data; 2973 int result = 0; 2974 2975 data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL); 2976 if (data == NULL) 2977 return -ENOMEM; 2978 2979 hwmgr->backend = data; 2980 smu7_patch_voltage_workaround(hwmgr); 2981 smu7_init_dpm_defaults(hwmgr); 2982 2983 /* Get leakage voltage based on leakage ID. */ 2984 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2985 PHM_PlatformCaps_EVV)) { 2986 result = smu7_get_evv_voltages(hwmgr); 2987 if (result) { 2988 pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); 2989 return -EINVAL; 2990 } 2991 } else { 2992 smu7_get_elb_voltages(hwmgr); 2993 } 2994 2995 if (hwmgr->pp_table_version == PP_TABLE_V1) { 2996 smu7_complete_dependency_tables(hwmgr); 2997 smu7_set_private_data_based_on_pptable_v1(hwmgr); 2998 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 2999 smu7_patch_dependency_tables_with_leakage(hwmgr); 3000 smu7_set_private_data_based_on_pptable_v0(hwmgr); 3001 } 3002 3003 /* Initalize Dynamic State Adjustment Rule Settings */ 3004 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); 3005 3006 if (0 == result) { 3007 struct amdgpu_device *adev = hwmgr->adev; 3008 3009 data->is_tlu_enabled = false; 3010 3011 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 3012 SMU7_MAX_HARDWARE_POWERLEVELS; 3013 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 3014 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 3015 3016 data->pcie_gen_cap = adev->pm.pcie_gen_mask; 3017 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 3018 data->pcie_spc_cap = 20; 3019 else 3020 data->pcie_spc_cap = 16; 3021 data->pcie_lane_cap = adev->pm.pcie_mlw_mask; 3022 3023 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 3024 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 3025 hwmgr->platform_descriptor.clockStep.engineClock = 500; 3026 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 3027 smu7_thermal_parameter_init(hwmgr); 3028 } else { 3029 /* Ignore return value in here, we are cleaning up a mess. */ 3030 smu7_hwmgr_backend_fini(hwmgr); 3031 } 3032 3033 result = smu7_update_edc_leakage_table(hwmgr); 3034 if (result) 3035 return result; 3036 3037 return 0; 3038 } 3039 3040 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) 3041 { 3042 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3043 uint32_t level, tmp; 3044 3045 if (!data->pcie_dpm_key_disabled) { 3046 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3047 level = 0; 3048 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; 3049 while (tmp >>= 1) 3050 level++; 3051 3052 if (level) 3053 smum_send_msg_to_smc_with_parameter(hwmgr, 3054 PPSMC_MSG_PCIeDPM_ForceLevel, level, 3055 NULL); 3056 } 3057 } 3058 3059 if (!data->sclk_dpm_key_disabled) { 3060 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3061 level = 0; 3062 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; 3063 while (tmp >>= 1) 3064 level++; 3065 3066 if (level) 3067 smum_send_msg_to_smc_with_parameter(hwmgr, 3068 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3069 (1 << level), 3070 NULL); 3071 } 3072 } 3073 3074 if (!data->mclk_dpm_key_disabled) { 3075 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3076 level = 0; 3077 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; 3078 while (tmp >>= 1) 3079 level++; 3080 3081 if (level) 3082 smum_send_msg_to_smc_with_parameter(hwmgr, 3083 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3084 (1 << level), 3085 NULL); 3086 } 3087 } 3088 3089 return 0; 3090 } 3091 3092 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) 3093 { 3094 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3095 3096 if (hwmgr->pp_table_version == PP_TABLE_V1) 3097 phm_apply_dal_min_voltage_request(hwmgr); 3098 /* TO DO for v0 iceland and Ci*/ 3099 3100 if (!data->sclk_dpm_key_disabled) { 3101 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) 3102 smum_send_msg_to_smc_with_parameter(hwmgr, 3103 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3104 data->dpm_level_enable_mask.sclk_dpm_enable_mask, 3105 NULL); 3106 } 3107 3108 if (!data->mclk_dpm_key_disabled) { 3109 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) 3110 smum_send_msg_to_smc_with_parameter(hwmgr, 3111 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3112 data->dpm_level_enable_mask.mclk_dpm_enable_mask, 3113 NULL); 3114 } 3115 3116 return 0; 3117 } 3118 3119 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 3120 { 3121 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3122 3123 if (!smum_is_dpm_running(hwmgr)) 3124 return -EINVAL; 3125 3126 if (!data->pcie_dpm_key_disabled) { 3127 smum_send_msg_to_smc(hwmgr, 3128 PPSMC_MSG_PCIeDPM_UnForceLevel, 3129 NULL); 3130 } 3131 3132 return smu7_upload_dpm_level_enable_mask(hwmgr); 3133 } 3134 3135 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) 3136 { 3137 struct smu7_hwmgr *data = 3138 (struct smu7_hwmgr *)(hwmgr->backend); 3139 uint32_t level; 3140 3141 if (!data->sclk_dpm_key_disabled) 3142 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3143 level = phm_get_lowest_enabled_level(hwmgr, 3144 data->dpm_level_enable_mask.sclk_dpm_enable_mask); 3145 smum_send_msg_to_smc_with_parameter(hwmgr, 3146 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3147 (1 << level), 3148 NULL); 3149 3150 } 3151 3152 if (!data->mclk_dpm_key_disabled) { 3153 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3154 level = phm_get_lowest_enabled_level(hwmgr, 3155 data->dpm_level_enable_mask.mclk_dpm_enable_mask); 3156 smum_send_msg_to_smc_with_parameter(hwmgr, 3157 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3158 (1 << level), 3159 NULL); 3160 } 3161 } 3162 3163 if (!data->pcie_dpm_key_disabled) { 3164 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3165 level = phm_get_lowest_enabled_level(hwmgr, 3166 data->dpm_level_enable_mask.pcie_dpm_enable_mask); 3167 smum_send_msg_to_smc_with_parameter(hwmgr, 3168 PPSMC_MSG_PCIeDPM_ForceLevel, 3169 (level), 3170 NULL); 3171 } 3172 } 3173 3174 return 0; 3175 } 3176 3177 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 3178 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) 3179 { 3180 uint32_t percentage; 3181 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3182 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; 3183 int32_t tmp_mclk; 3184 int32_t tmp_sclk; 3185 int32_t count; 3186 3187 if (golden_dpm_table->mclk_table.count < 1) 3188 return -EINVAL; 3189 3190 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / 3191 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 3192 3193 if (golden_dpm_table->mclk_table.count == 1) { 3194 percentage = 70; 3195 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 3196 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 3197 } else { 3198 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; 3199 *mclk_mask = golden_dpm_table->mclk_table.count - 2; 3200 } 3201 3202 tmp_sclk = tmp_mclk * percentage / 100; 3203 3204 if (hwmgr->pp_table_version == PP_TABLE_V0) { 3205 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 3206 count >= 0; count--) { 3207 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { 3208 *sclk_mask = count; 3209 break; 3210 } 3211 } 3212 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 3213 *sclk_mask = 0; 3214 3215 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3216 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 3217 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 3218 struct phm_ppt_v1_information *table_info = 3219 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3220 3221 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { 3222 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) { 3223 *sclk_mask = count; 3224 break; 3225 } 3226 } 3227 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 3228 *sclk_mask = 0; 3229 3230 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3231 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 3232 } 3233 3234 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) 3235 *mclk_mask = 0; 3236 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3237 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 3238 3239 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1; 3240 3241 return 0; 3242 } 3243 3244 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, 3245 enum amd_dpm_forced_level level) 3246 { 3247 int ret = 0; 3248 uint32_t sclk_mask = 0; 3249 uint32_t mclk_mask = 0; 3250 uint32_t pcie_mask = 0; 3251 3252 switch (level) { 3253 case AMD_DPM_FORCED_LEVEL_HIGH: 3254 ret = smu7_force_dpm_highest(hwmgr); 3255 break; 3256 case AMD_DPM_FORCED_LEVEL_LOW: 3257 ret = smu7_force_dpm_lowest(hwmgr); 3258 break; 3259 case AMD_DPM_FORCED_LEVEL_AUTO: 3260 ret = smu7_unforce_dpm_levels(hwmgr); 3261 break; 3262 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 3263 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 3264 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 3265 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 3266 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); 3267 if (ret) 3268 return ret; 3269 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 3270 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 3271 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); 3272 break; 3273 case AMD_DPM_FORCED_LEVEL_MANUAL: 3274 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 3275 default: 3276 break; 3277 } 3278 3279 if (!ret) { 3280 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3281 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 3282 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3283 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); 3284 } 3285 return ret; 3286 } 3287 3288 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) 3289 { 3290 return sizeof(struct smu7_power_state); 3291 } 3292 3293 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr, 3294 uint32_t vblank_time_us) 3295 { 3296 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3297 uint32_t switch_limit_us; 3298 3299 switch (hwmgr->chip_id) { 3300 case CHIP_POLARIS10: 3301 case CHIP_POLARIS11: 3302 case CHIP_POLARIS12: 3303 if (hwmgr->is_kicker || (hwmgr->chip_id == CHIP_POLARIS12)) 3304 switch_limit_us = data->is_memory_gddr5 ? 450 : 150; 3305 else 3306 switch_limit_us = data->is_memory_gddr5 ? 200 : 150; 3307 break; 3308 case CHIP_VEGAM: 3309 switch_limit_us = 30; 3310 break; 3311 default: 3312 switch_limit_us = data->is_memory_gddr5 ? 450 : 150; 3313 break; 3314 } 3315 3316 if (vblank_time_us < switch_limit_us) 3317 return true; 3318 else 3319 return false; 3320 } 3321 3322 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 3323 struct pp_power_state *request_ps, 3324 const struct pp_power_state *current_ps) 3325 { 3326 struct amdgpu_device *adev = hwmgr->adev; 3327 struct smu7_power_state *smu7_ps = 3328 cast_phw_smu7_power_state(&request_ps->hardware); 3329 uint32_t sclk; 3330 uint32_t mclk; 3331 struct PP_Clocks minimum_clocks = {0}; 3332 bool disable_mclk_switching; 3333 bool disable_mclk_switching_for_frame_lock; 3334 bool disable_mclk_switching_for_display; 3335 const struct phm_clock_and_voltage_limits *max_limits; 3336 uint32_t i; 3337 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3338 struct phm_ppt_v1_information *table_info = 3339 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3340 int32_t count; 3341 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; 3342 uint32_t latency; 3343 bool latency_allowed = false; 3344 3345 data->battery_state = (PP_StateUILabel_Battery == 3346 request_ps->classification.ui_label); 3347 data->mclk_ignore_signal = false; 3348 3349 max_limits = adev->pm.ac_power ? 3350 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : 3351 &(hwmgr->dyn_state.max_clock_voltage_on_dc); 3352 3353 /* Cap clock DPM tables at DC MAX if it is in DC. */ 3354 if (!adev->pm.ac_power) { 3355 for (i = 0; i < smu7_ps->performance_level_count; i++) { 3356 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) 3357 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; 3358 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) 3359 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; 3360 } 3361 } 3362 3363 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; 3364 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 3365 3366 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3367 PHM_PlatformCaps_StablePState)) { 3368 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); 3369 stable_pstate_sclk = (max_limits->sclk * 75) / 100; 3370 3371 for (count = table_info->vdd_dep_on_sclk->count - 1; 3372 count >= 0; count--) { 3373 if (stable_pstate_sclk >= 3374 table_info->vdd_dep_on_sclk->entries[count].clk) { 3375 stable_pstate_sclk = 3376 table_info->vdd_dep_on_sclk->entries[count].clk; 3377 break; 3378 } 3379 } 3380 3381 if (count < 0) 3382 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3383 3384 stable_pstate_mclk = max_limits->mclk; 3385 3386 minimum_clocks.engineClock = stable_pstate_sclk; 3387 minimum_clocks.memoryClock = stable_pstate_mclk; 3388 } 3389 3390 disable_mclk_switching_for_frame_lock = phm_cap_enabled( 3391 hwmgr->platform_descriptor.platformCaps, 3392 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 3393 3394 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && 3395 !hwmgr->display_config->multi_monitor_in_sync) || 3396 (hwmgr->display_config->num_display && 3397 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); 3398 3399 disable_mclk_switching = disable_mclk_switching_for_frame_lock || 3400 disable_mclk_switching_for_display; 3401 3402 if (hwmgr->display_config->num_display == 0) { 3403 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) 3404 data->mclk_ignore_signal = true; 3405 else 3406 disable_mclk_switching = false; 3407 } 3408 3409 sclk = smu7_ps->performance_levels[0].engine_clock; 3410 mclk = smu7_ps->performance_levels[0].memory_clock; 3411 3412 if (disable_mclk_switching && 3413 (!(hwmgr->chip_id >= CHIP_POLARIS10 && 3414 hwmgr->chip_id <= CHIP_VEGAM))) 3415 mclk = smu7_ps->performance_levels 3416 [smu7_ps->performance_level_count - 1].memory_clock; 3417 3418 if (sclk < minimum_clocks.engineClock) 3419 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? 3420 max_limits->sclk : minimum_clocks.engineClock; 3421 3422 if (mclk < minimum_clocks.memoryClock) 3423 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? 3424 max_limits->mclk : minimum_clocks.memoryClock; 3425 3426 smu7_ps->performance_levels[0].engine_clock = sclk; 3427 smu7_ps->performance_levels[0].memory_clock = mclk; 3428 3429 smu7_ps->performance_levels[1].engine_clock = 3430 (smu7_ps->performance_levels[1].engine_clock >= 3431 smu7_ps->performance_levels[0].engine_clock) ? 3432 smu7_ps->performance_levels[1].engine_clock : 3433 smu7_ps->performance_levels[0].engine_clock; 3434 3435 if (disable_mclk_switching) { 3436 if (mclk < smu7_ps->performance_levels[1].memory_clock) 3437 mclk = smu7_ps->performance_levels[1].memory_clock; 3438 3439 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) { 3440 if (disable_mclk_switching_for_display) { 3441 /* Find the lowest MCLK frequency that is within 3442 * the tolerable latency defined in DAL 3443 */ 3444 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3445 for (i = 0; i < data->mclk_latency_table.count; i++) { 3446 if (data->mclk_latency_table.entries[i].latency <= latency) { 3447 latency_allowed = true; 3448 3449 if ((data->mclk_latency_table.entries[i].frequency >= 3450 smu7_ps->performance_levels[0].memory_clock) && 3451 (data->mclk_latency_table.entries[i].frequency <= 3452 smu7_ps->performance_levels[1].memory_clock)) { 3453 mclk = data->mclk_latency_table.entries[i].frequency; 3454 break; 3455 } 3456 } 3457 } 3458 if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) { 3459 data->mclk_ignore_signal = true; 3460 } else { 3461 data->mclk_ignore_signal = false; 3462 } 3463 } 3464 3465 if (disable_mclk_switching_for_frame_lock) 3466 mclk = smu7_ps->performance_levels[1].memory_clock; 3467 } 3468 3469 smu7_ps->performance_levels[0].memory_clock = mclk; 3470 3471 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 3472 hwmgr->chip_id <= CHIP_VEGAM)) 3473 smu7_ps->performance_levels[1].memory_clock = mclk; 3474 } else { 3475 if (smu7_ps->performance_levels[1].memory_clock < 3476 smu7_ps->performance_levels[0].memory_clock) 3477 smu7_ps->performance_levels[1].memory_clock = 3478 smu7_ps->performance_levels[0].memory_clock; 3479 } 3480 3481 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3482 PHM_PlatformCaps_StablePState)) { 3483 for (i = 0; i < smu7_ps->performance_level_count; i++) { 3484 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk; 3485 smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk; 3486 smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; 3487 smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; 3488 } 3489 } 3490 return 0; 3491 } 3492 3493 3494 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 3495 { 3496 struct pp_power_state *ps; 3497 struct smu7_power_state *smu7_ps; 3498 3499 if (hwmgr == NULL) 3500 return -EINVAL; 3501 3502 ps = hwmgr->request_ps; 3503 3504 if (ps == NULL) 3505 return -EINVAL; 3506 3507 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3508 3509 if (low) 3510 return smu7_ps->performance_levels[0].memory_clock; 3511 else 3512 return smu7_ps->performance_levels 3513 [smu7_ps->performance_level_count-1].memory_clock; 3514 } 3515 3516 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 3517 { 3518 struct pp_power_state *ps; 3519 struct smu7_power_state *smu7_ps; 3520 3521 if (hwmgr == NULL) 3522 return -EINVAL; 3523 3524 ps = hwmgr->request_ps; 3525 3526 if (ps == NULL) 3527 return -EINVAL; 3528 3529 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3530 3531 if (low) 3532 return smu7_ps->performance_levels[0].engine_clock; 3533 else 3534 return smu7_ps->performance_levels 3535 [smu7_ps->performance_level_count-1].engine_clock; 3536 } 3537 3538 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, 3539 struct pp_hw_power_state *hw_ps) 3540 { 3541 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3542 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps; 3543 ATOM_FIRMWARE_INFO_V2_2 *fw_info; 3544 uint16_t size; 3545 uint8_t frev, crev; 3546 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 3547 3548 /* First retrieve the Boot clocks and VDDC from the firmware info table. 3549 * We assume here that fw_info is unchanged if this call fails. 3550 */ 3551 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index, 3552 &size, &frev, &crev); 3553 if (!fw_info) 3554 /* During a test, there is no firmware info table. */ 3555 return 0; 3556 3557 /* Patch the state. */ 3558 data->vbios_boot_state.sclk_bootup_value = 3559 le32_to_cpu(fw_info->ulDefaultEngineClock); 3560 data->vbios_boot_state.mclk_bootup_value = 3561 le32_to_cpu(fw_info->ulDefaultMemoryClock); 3562 data->vbios_boot_state.mvdd_bootup_value = 3563 le16_to_cpu(fw_info->usBootUpMVDDCVoltage); 3564 data->vbios_boot_state.vddc_bootup_value = 3565 le16_to_cpu(fw_info->usBootUpVDDCVoltage); 3566 data->vbios_boot_state.vddci_bootup_value = 3567 le16_to_cpu(fw_info->usBootUpVDDCIVoltage); 3568 data->vbios_boot_state.pcie_gen_bootup_value = 3569 smu7_get_current_pcie_speed(hwmgr); 3570 3571 data->vbios_boot_state.pcie_lane_bootup_value = 3572 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr); 3573 3574 /* set boot power state */ 3575 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; 3576 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; 3577 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; 3578 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; 3579 3580 return 0; 3581 } 3582 3583 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) 3584 { 3585 int result; 3586 unsigned long ret = 0; 3587 3588 if (hwmgr->pp_table_version == PP_TABLE_V0) { 3589 result = pp_tables_get_num_of_entries(hwmgr, &ret); 3590 return result ? 0 : ret; 3591 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 3592 result = get_number_of_powerplay_table_entries_v1_0(hwmgr); 3593 return result; 3594 } 3595 return 0; 3596 } 3597 3598 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, 3599 void *state, struct pp_power_state *power_state, 3600 void *pp_table, uint32_t classification_flag) 3601 { 3602 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3603 struct smu7_power_state *smu7_power_state = 3604 (struct smu7_power_state *)(&(power_state->hardware)); 3605 struct smu7_performance_level *performance_level; 3606 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; 3607 ATOM_Tonga_POWERPLAYTABLE *powerplay_table = 3608 (ATOM_Tonga_POWERPLAYTABLE *)pp_table; 3609 PPTable_Generic_SubTable_Header *sclk_dep_table = 3610 (PPTable_Generic_SubTable_Header *) 3611 (((unsigned long)powerplay_table) + 3612 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); 3613 3614 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = 3615 (ATOM_Tonga_MCLK_Dependency_Table *) 3616 (((unsigned long)powerplay_table) + 3617 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 3618 3619 /* The following fields are not initialized here: id orderedList allStatesList */ 3620 power_state->classification.ui_label = 3621 (le16_to_cpu(state_entry->usClassification) & 3622 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> 3623 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; 3624 power_state->classification.flags = classification_flag; 3625 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ 3626 3627 power_state->classification.temporary_state = false; 3628 power_state->classification.to_be_deleted = false; 3629 3630 power_state->validation.disallowOnDC = 3631 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & 3632 ATOM_Tonga_DISALLOW_ON_DC)); 3633 3634 power_state->pcie.lanes = 0; 3635 3636 power_state->display.disableFrameModulation = false; 3637 power_state->display.limitRefreshrate = false; 3638 power_state->display.enableVariBright = 3639 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & 3640 ATOM_Tonga_ENABLE_VARIBRIGHT)); 3641 3642 power_state->validation.supportedPowerLevels = 0; 3643 power_state->uvd_clocks.VCLK = 0; 3644 power_state->uvd_clocks.DCLK = 0; 3645 power_state->temperatures.min = 0; 3646 power_state->temperatures.max = 0; 3647 3648 performance_level = &(smu7_power_state->performance_levels 3649 [smu7_power_state->performance_level_count++]); 3650 3651 PP_ASSERT_WITH_CODE( 3652 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), 3653 "Performance levels exceeds SMC limit!", 3654 return -EINVAL); 3655 3656 PP_ASSERT_WITH_CODE( 3657 (smu7_power_state->performance_level_count < 3658 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3659 "Performance levels exceeds Driver limit!", 3660 return -EINVAL); 3661 3662 /* Performance levels are arranged from low to high. */ 3663 performance_level->memory_clock = mclk_dep_table->entries 3664 [state_entry->ucMemoryClockIndexLow].ulMclk; 3665 if (sclk_dep_table->ucRevId == 0) 3666 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries 3667 [state_entry->ucEngineClockIndexLow].ulSclk; 3668 else if (sclk_dep_table->ucRevId == 1) 3669 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries 3670 [state_entry->ucEngineClockIndexLow].ulSclk; 3671 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3672 state_entry->ucPCIEGenLow); 3673 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3674 state_entry->ucPCIELaneLow); 3675 3676 performance_level = &(smu7_power_state->performance_levels 3677 [smu7_power_state->performance_level_count++]); 3678 performance_level->memory_clock = mclk_dep_table->entries 3679 [state_entry->ucMemoryClockIndexHigh].ulMclk; 3680 3681 if (sclk_dep_table->ucRevId == 0) 3682 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries 3683 [state_entry->ucEngineClockIndexHigh].ulSclk; 3684 else if (sclk_dep_table->ucRevId == 1) 3685 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries 3686 [state_entry->ucEngineClockIndexHigh].ulSclk; 3687 3688 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3689 state_entry->ucPCIEGenHigh); 3690 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3691 state_entry->ucPCIELaneHigh); 3692 3693 return 0; 3694 } 3695 3696 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr, 3697 unsigned long entry_index, struct pp_power_state *state) 3698 { 3699 int result; 3700 struct smu7_power_state *ps; 3701 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3702 struct phm_ppt_v1_information *table_info = 3703 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3704 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 3705 table_info->vdd_dep_on_mclk; 3706 3707 state->hardware.magic = PHM_VIslands_Magic; 3708 3709 ps = (struct smu7_power_state *)(&state->hardware); 3710 3711 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state, 3712 smu7_get_pp_table_entry_callback_func_v1); 3713 3714 /* This is the earliest time we have all the dependency table and the VBIOS boot state 3715 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state 3716 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state 3717 */ 3718 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { 3719 if (dep_mclk_table->entries[0].clk != 3720 data->vbios_boot_state.mclk_bootup_value) 3721 pr_debug("Single MCLK entry VDDCI/MCLK dependency table " 3722 "does not match VBIOS boot MCLK level"); 3723 if (dep_mclk_table->entries[0].vddci != 3724 data->vbios_boot_state.vddci_bootup_value) 3725 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " 3726 "does not match VBIOS boot VDDCI level"); 3727 } 3728 3729 /* set DC compatible flag if this state supports DC */ 3730 if (!state->validation.disallowOnDC) 3731 ps->dc_compatible = true; 3732 3733 if (state->classification.flags & PP_StateClassificationFlag_ACPI) 3734 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; 3735 3736 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3737 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3738 3739 if (!result) { 3740 uint32_t i; 3741 3742 switch (state->classification.ui_label) { 3743 case PP_StateUILabel_Performance: 3744 data->use_pcie_performance_levels = true; 3745 for (i = 0; i < ps->performance_level_count; i++) { 3746 if (data->pcie_gen_performance.max < 3747 ps->performance_levels[i].pcie_gen) 3748 data->pcie_gen_performance.max = 3749 ps->performance_levels[i].pcie_gen; 3750 3751 if (data->pcie_gen_performance.min > 3752 ps->performance_levels[i].pcie_gen) 3753 data->pcie_gen_performance.min = 3754 ps->performance_levels[i].pcie_gen; 3755 3756 if (data->pcie_lane_performance.max < 3757 ps->performance_levels[i].pcie_lane) 3758 data->pcie_lane_performance.max = 3759 ps->performance_levels[i].pcie_lane; 3760 if (data->pcie_lane_performance.min > 3761 ps->performance_levels[i].pcie_lane) 3762 data->pcie_lane_performance.min = 3763 ps->performance_levels[i].pcie_lane; 3764 } 3765 break; 3766 case PP_StateUILabel_Battery: 3767 data->use_pcie_power_saving_levels = true; 3768 3769 for (i = 0; i < ps->performance_level_count; i++) { 3770 if (data->pcie_gen_power_saving.max < 3771 ps->performance_levels[i].pcie_gen) 3772 data->pcie_gen_power_saving.max = 3773 ps->performance_levels[i].pcie_gen; 3774 3775 if (data->pcie_gen_power_saving.min > 3776 ps->performance_levels[i].pcie_gen) 3777 data->pcie_gen_power_saving.min = 3778 ps->performance_levels[i].pcie_gen; 3779 3780 if (data->pcie_lane_power_saving.max < 3781 ps->performance_levels[i].pcie_lane) 3782 data->pcie_lane_power_saving.max = 3783 ps->performance_levels[i].pcie_lane; 3784 3785 if (data->pcie_lane_power_saving.min > 3786 ps->performance_levels[i].pcie_lane) 3787 data->pcie_lane_power_saving.min = 3788 ps->performance_levels[i].pcie_lane; 3789 } 3790 break; 3791 default: 3792 break; 3793 } 3794 } 3795 return 0; 3796 } 3797 3798 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, 3799 struct pp_hw_power_state *power_state, 3800 unsigned int index, const void *clock_info) 3801 { 3802 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3803 struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state); 3804 const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info; 3805 struct smu7_performance_level *performance_level; 3806 uint32_t engine_clock, memory_clock; 3807 uint16_t pcie_gen_from_bios; 3808 3809 engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow; 3810 memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow; 3811 3812 if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk) 3813 data->highest_mclk = memory_clock; 3814 3815 PP_ASSERT_WITH_CODE( 3816 (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), 3817 "Performance levels exceeds SMC limit!", 3818 return -EINVAL); 3819 3820 PP_ASSERT_WITH_CODE( 3821 (ps->performance_level_count < 3822 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3823 "Performance levels exceeds Driver limit, Skip!", 3824 return 0); 3825 3826 performance_level = &(ps->performance_levels 3827 [ps->performance_level_count++]); 3828 3829 /* Performance levels are arranged from low to high. */ 3830 performance_level->memory_clock = memory_clock; 3831 performance_level->engine_clock = engine_clock; 3832 3833 pcie_gen_from_bios = visland_clk_info->ucPCIEGen; 3834 3835 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios); 3836 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane); 3837 3838 return 0; 3839 } 3840 3841 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr, 3842 unsigned long entry_index, struct pp_power_state *state) 3843 { 3844 int result; 3845 struct smu7_power_state *ps; 3846 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3847 struct phm_clock_voltage_dependency_table *dep_mclk_table = 3848 hwmgr->dyn_state.vddci_dependency_on_mclk; 3849 3850 memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state)); 3851 3852 state->hardware.magic = PHM_VIslands_Magic; 3853 3854 ps = (struct smu7_power_state *)(&state->hardware); 3855 3856 result = pp_tables_get_entry(hwmgr, entry_index, state, 3857 smu7_get_pp_table_entry_callback_func_v0); 3858 3859 /* 3860 * This is the earliest time we have all the dependency table 3861 * and the VBIOS boot state as 3862 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot 3863 * state if there is only one VDDCI/MCLK level, check if it's 3864 * the same as VBIOS boot state 3865 */ 3866 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { 3867 if (dep_mclk_table->entries[0].clk != 3868 data->vbios_boot_state.mclk_bootup_value) 3869 pr_debug("Single MCLK entry VDDCI/MCLK dependency table " 3870 "does not match VBIOS boot MCLK level"); 3871 if (dep_mclk_table->entries[0].v != 3872 data->vbios_boot_state.vddci_bootup_value) 3873 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " 3874 "does not match VBIOS boot VDDCI level"); 3875 } 3876 3877 /* set DC compatible flag if this state supports DC */ 3878 if (!state->validation.disallowOnDC) 3879 ps->dc_compatible = true; 3880 3881 if (state->classification.flags & PP_StateClassificationFlag_ACPI) 3882 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; 3883 3884 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3885 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3886 3887 if (!result) { 3888 uint32_t i; 3889 3890 switch (state->classification.ui_label) { 3891 case PP_StateUILabel_Performance: 3892 data->use_pcie_performance_levels = true; 3893 3894 for (i = 0; i < ps->performance_level_count; i++) { 3895 if (data->pcie_gen_performance.max < 3896 ps->performance_levels[i].pcie_gen) 3897 data->pcie_gen_performance.max = 3898 ps->performance_levels[i].pcie_gen; 3899 3900 if (data->pcie_gen_performance.min > 3901 ps->performance_levels[i].pcie_gen) 3902 data->pcie_gen_performance.min = 3903 ps->performance_levels[i].pcie_gen; 3904 3905 if (data->pcie_lane_performance.max < 3906 ps->performance_levels[i].pcie_lane) 3907 data->pcie_lane_performance.max = 3908 ps->performance_levels[i].pcie_lane; 3909 3910 if (data->pcie_lane_performance.min > 3911 ps->performance_levels[i].pcie_lane) 3912 data->pcie_lane_performance.min = 3913 ps->performance_levels[i].pcie_lane; 3914 } 3915 break; 3916 case PP_StateUILabel_Battery: 3917 data->use_pcie_power_saving_levels = true; 3918 3919 for (i = 0; i < ps->performance_level_count; i++) { 3920 if (data->pcie_gen_power_saving.max < 3921 ps->performance_levels[i].pcie_gen) 3922 data->pcie_gen_power_saving.max = 3923 ps->performance_levels[i].pcie_gen; 3924 3925 if (data->pcie_gen_power_saving.min > 3926 ps->performance_levels[i].pcie_gen) 3927 data->pcie_gen_power_saving.min = 3928 ps->performance_levels[i].pcie_gen; 3929 3930 if (data->pcie_lane_power_saving.max < 3931 ps->performance_levels[i].pcie_lane) 3932 data->pcie_lane_power_saving.max = 3933 ps->performance_levels[i].pcie_lane; 3934 3935 if (data->pcie_lane_power_saving.min > 3936 ps->performance_levels[i].pcie_lane) 3937 data->pcie_lane_power_saving.min = 3938 ps->performance_levels[i].pcie_lane; 3939 } 3940 break; 3941 default: 3942 break; 3943 } 3944 } 3945 return 0; 3946 } 3947 3948 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, 3949 unsigned long entry_index, struct pp_power_state *state) 3950 { 3951 if (hwmgr->pp_table_version == PP_TABLE_V0) 3952 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state); 3953 else if (hwmgr->pp_table_version == PP_TABLE_V1) 3954 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state); 3955 3956 return 0; 3957 } 3958 3959 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query) 3960 { 3961 struct amdgpu_device *adev = hwmgr->adev; 3962 int i; 3963 u32 tmp = 0; 3964 3965 if (!query) 3966 return -EINVAL; 3967 3968 /* 3969 * PPSMC_MSG_GetCurrPkgPwr is not supported on: 3970 * - Hawaii 3971 * - Bonaire 3972 * - Fiji 3973 * - Tonga 3974 */ 3975 if ((adev->asic_type != CHIP_HAWAII) && 3976 (adev->asic_type != CHIP_BONAIRE) && 3977 (adev->asic_type != CHIP_FIJI) && 3978 (adev->asic_type != CHIP_TONGA)) { 3979 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp); 3980 *query = tmp; 3981 3982 if (tmp != 0) 3983 return 0; 3984 } 3985 3986 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL); 3987 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 3988 ixSMU_PM_STATUS_95, 0); 3989 3990 for (i = 0; i < 10; i++) { 3991 msleep(500); 3992 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL); 3993 tmp = cgs_read_ind_register(hwmgr->device, 3994 CGS_IND_REG__SMC, 3995 ixSMU_PM_STATUS_95); 3996 if (tmp != 0) 3997 break; 3998 } 3999 *query = tmp; 4000 4001 return 0; 4002 } 4003 4004 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, 4005 void *value, int *size) 4006 { 4007 uint32_t sclk, mclk, activity_percent; 4008 uint32_t offset, val_vid; 4009 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4010 4011 /* size must be at least 4 bytes for all sensors */ 4012 if (*size < 4) 4013 return -EINVAL; 4014 4015 switch (idx) { 4016 case AMDGPU_PP_SENSOR_GFX_SCLK: 4017 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &sclk); 4018 *((uint32_t *)value) = sclk; 4019 *size = 4; 4020 return 0; 4021 case AMDGPU_PP_SENSOR_GFX_MCLK: 4022 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &mclk); 4023 *((uint32_t *)value) = mclk; 4024 *size = 4; 4025 return 0; 4026 case AMDGPU_PP_SENSOR_GPU_LOAD: 4027 case AMDGPU_PP_SENSOR_MEM_LOAD: 4028 offset = data->soft_regs_start + smum_get_offsetof(hwmgr, 4029 SMU_SoftRegisters, 4030 (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ? 4031 AverageGraphicsActivity: 4032 AverageMemoryActivity); 4033 4034 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); 4035 activity_percent += 0x80; 4036 activity_percent >>= 8; 4037 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 4038 *size = 4; 4039 return 0; 4040 case AMDGPU_PP_SENSOR_GPU_TEMP: 4041 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr); 4042 *size = 4; 4043 return 0; 4044 case AMDGPU_PP_SENSOR_UVD_POWER: 4045 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 4046 *size = 4; 4047 return 0; 4048 case AMDGPU_PP_SENSOR_VCE_POWER: 4049 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 4050 *size = 4; 4051 return 0; 4052 case AMDGPU_PP_SENSOR_GPU_POWER: 4053 return smu7_get_gpu_power(hwmgr, (uint32_t *)value); 4054 case AMDGPU_PP_SENSOR_VDDGFX: 4055 if ((data->vr_config & VRCONF_VDDGFX_MASK) == 4056 (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT)) 4057 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, 4058 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID); 4059 else 4060 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, 4061 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID); 4062 4063 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid); 4064 return 0; 4065 default: 4066 return -EOPNOTSUPP; 4067 } 4068 } 4069 4070 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) 4071 { 4072 const struct phm_set_power_state_input *states = 4073 (const struct phm_set_power_state_input *)input; 4074 const struct smu7_power_state *smu7_ps = 4075 cast_const_phw_smu7_power_state(states->pnew_state); 4076 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4077 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4078 uint32_t sclk = smu7_ps->performance_levels 4079 [smu7_ps->performance_level_count - 1].engine_clock; 4080 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4081 uint32_t mclk = smu7_ps->performance_levels 4082 [smu7_ps->performance_level_count - 1].memory_clock; 4083 struct PP_Clocks min_clocks = {0}; 4084 uint32_t i; 4085 4086 for (i = 0; i < sclk_table->count; i++) { 4087 if (sclk == sclk_table->dpm_levels[i].value) 4088 break; 4089 } 4090 4091 if (i >= sclk_table->count) { 4092 if (sclk > sclk_table->dpm_levels[i-1].value) { 4093 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 4094 sclk_table->dpm_levels[i-1].value = sclk; 4095 } 4096 } else { 4097 /* TODO: Check SCLK in DAL's minimum clocks 4098 * in case DeepSleep divider update is required. 4099 */ 4100 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && 4101 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || 4102 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) 4103 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 4104 } 4105 4106 for (i = 0; i < mclk_table->count; i++) { 4107 if (mclk == mclk_table->dpm_levels[i].value) 4108 break; 4109 } 4110 4111 if (i >= mclk_table->count) { 4112 if (mclk > mclk_table->dpm_levels[i-1].value) { 4113 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 4114 mclk_table->dpm_levels[i-1].value = mclk; 4115 } 4116 } 4117 4118 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 4119 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 4120 4121 return 0; 4122 } 4123 4124 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr, 4125 const struct smu7_power_state *smu7_ps) 4126 { 4127 uint32_t i; 4128 uint32_t sclk, max_sclk = 0; 4129 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4130 struct smu7_dpm_table *dpm_table = &data->dpm_table; 4131 4132 for (i = 0; i < smu7_ps->performance_level_count; i++) { 4133 sclk = smu7_ps->performance_levels[i].engine_clock; 4134 if (max_sclk < sclk) 4135 max_sclk = sclk; 4136 } 4137 4138 for (i = 0; i < dpm_table->sclk_table.count; i++) { 4139 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) 4140 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? 4141 dpm_table->pcie_speed_table.dpm_levels 4142 [dpm_table->pcie_speed_table.count - 1].value : 4143 dpm_table->pcie_speed_table.dpm_levels[i].value); 4144 } 4145 4146 return 0; 4147 } 4148 4149 static int smu7_request_link_speed_change_before_state_change( 4150 struct pp_hwmgr *hwmgr, const void *input) 4151 { 4152 const struct phm_set_power_state_input *states = 4153 (const struct phm_set_power_state_input *)input; 4154 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4155 const struct smu7_power_state *smu7_nps = 4156 cast_const_phw_smu7_power_state(states->pnew_state); 4157 const struct smu7_power_state *polaris10_cps = 4158 cast_const_phw_smu7_power_state(states->pcurrent_state); 4159 4160 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps); 4161 uint16_t current_link_speed; 4162 4163 if (data->force_pcie_gen == PP_PCIEGenInvalid) 4164 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps); 4165 else 4166 current_link_speed = data->force_pcie_gen; 4167 4168 data->force_pcie_gen = PP_PCIEGenInvalid; 4169 data->pspp_notify_required = false; 4170 4171 if (target_link_speed > current_link_speed) { 4172 switch (target_link_speed) { 4173 #ifdef CONFIG_ACPI 4174 case PP_PCIEGen3: 4175 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false)) 4176 break; 4177 data->force_pcie_gen = PP_PCIEGen2; 4178 if (current_link_speed == PP_PCIEGen2) 4179 break; 4180 fallthrough; 4181 case PP_PCIEGen2: 4182 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false)) 4183 break; 4184 fallthrough; 4185 #endif 4186 default: 4187 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr); 4188 break; 4189 } 4190 } else { 4191 if (target_link_speed < current_link_speed) 4192 data->pspp_notify_required = true; 4193 } 4194 4195 return 0; 4196 } 4197 4198 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 4199 { 4200 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4201 4202 if (0 == data->need_update_smu7_dpm_table) 4203 return 0; 4204 4205 if ((0 == data->sclk_dpm_key_disabled) && 4206 (data->need_update_smu7_dpm_table & 4207 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 4208 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4209 "Trying to freeze SCLK DPM when DPM is disabled", 4210 ); 4211 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4212 PPSMC_MSG_SCLKDPM_FreezeLevel, 4213 NULL), 4214 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", 4215 return -EINVAL); 4216 } 4217 4218 if ((0 == data->mclk_dpm_key_disabled) && 4219 !data->mclk_ignore_signal && 4220 (data->need_update_smu7_dpm_table & 4221 DPMTABLE_OD_UPDATE_MCLK)) { 4222 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4223 "Trying to freeze MCLK DPM when DPM is disabled", 4224 ); 4225 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4226 PPSMC_MSG_MCLKDPM_FreezeLevel, 4227 NULL), 4228 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", 4229 return -EINVAL); 4230 } 4231 4232 return 0; 4233 } 4234 4235 static int smu7_populate_and_upload_sclk_mclk_dpm_levels( 4236 struct pp_hwmgr *hwmgr, const void *input) 4237 { 4238 int result = 0; 4239 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4240 struct smu7_dpm_table *dpm_table = &data->dpm_table; 4241 uint32_t count; 4242 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 4243 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); 4244 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); 4245 4246 if (0 == data->need_update_smu7_dpm_table) 4247 return 0; 4248 4249 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 4250 for (count = 0; count < dpm_table->sclk_table.count; count++) { 4251 dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled; 4252 dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock; 4253 } 4254 } 4255 4256 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 4257 for (count = 0; count < dpm_table->mclk_table.count; count++) { 4258 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; 4259 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; 4260 } 4261 } 4262 4263 if (data->need_update_smu7_dpm_table & 4264 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 4265 result = smum_populate_all_graphic_levels(hwmgr); 4266 PP_ASSERT_WITH_CODE((0 == result), 4267 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", 4268 return result); 4269 } 4270 4271 if (data->need_update_smu7_dpm_table & 4272 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 4273 /*populate MCLK dpm table to SMU7 */ 4274 result = smum_populate_all_memory_levels(hwmgr); 4275 PP_ASSERT_WITH_CODE((0 == result), 4276 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", 4277 return result); 4278 } 4279 4280 return result; 4281 } 4282 4283 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, 4284 struct smu7_single_dpm_table *dpm_table, 4285 uint32_t low_limit, uint32_t high_limit) 4286 { 4287 uint32_t i; 4288 4289 /* force the trim if mclk_switching is disabled to prevent flicker */ 4290 bool force_trim = (low_limit == high_limit); 4291 for (i = 0; i < dpm_table->count; i++) { 4292 /*skip the trim if od is enabled*/ 4293 if ((!hwmgr->od_enabled || force_trim) 4294 && (dpm_table->dpm_levels[i].value < low_limit 4295 || dpm_table->dpm_levels[i].value > high_limit)) 4296 dpm_table->dpm_levels[i].enabled = false; 4297 else 4298 dpm_table->dpm_levels[i].enabled = true; 4299 } 4300 4301 return 0; 4302 } 4303 4304 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr, 4305 const struct smu7_power_state *smu7_ps) 4306 { 4307 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4308 uint32_t high_limit_count; 4309 4310 PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1), 4311 "power state did not have any performance level", 4312 return -EINVAL); 4313 4314 high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1; 4315 4316 smu7_trim_single_dpm_states(hwmgr, 4317 &(data->dpm_table.sclk_table), 4318 smu7_ps->performance_levels[0].engine_clock, 4319 smu7_ps->performance_levels[high_limit_count].engine_clock); 4320 4321 smu7_trim_single_dpm_states(hwmgr, 4322 &(data->dpm_table.mclk_table), 4323 smu7_ps->performance_levels[0].memory_clock, 4324 smu7_ps->performance_levels[high_limit_count].memory_clock); 4325 4326 return 0; 4327 } 4328 4329 static int smu7_generate_dpm_level_enable_mask( 4330 struct pp_hwmgr *hwmgr, const void *input) 4331 { 4332 int result = 0; 4333 const struct phm_set_power_state_input *states = 4334 (const struct phm_set_power_state_input *)input; 4335 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4336 const struct smu7_power_state *smu7_ps = 4337 cast_const_phw_smu7_power_state(states->pnew_state); 4338 4339 4340 result = smu7_trim_dpm_states(hwmgr, smu7_ps); 4341 if (result) 4342 return result; 4343 4344 data->dpm_level_enable_mask.sclk_dpm_enable_mask = 4345 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); 4346 data->dpm_level_enable_mask.mclk_dpm_enable_mask = 4347 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); 4348 data->dpm_level_enable_mask.pcie_dpm_enable_mask = 4349 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); 4350 4351 return 0; 4352 } 4353 4354 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 4355 { 4356 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4357 4358 if (0 == data->need_update_smu7_dpm_table) 4359 return 0; 4360 4361 if ((0 == data->sclk_dpm_key_disabled) && 4362 (data->need_update_smu7_dpm_table & 4363 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 4364 4365 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4366 "Trying to Unfreeze SCLK DPM when DPM is disabled", 4367 ); 4368 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4369 PPSMC_MSG_SCLKDPM_UnfreezeLevel, 4370 NULL), 4371 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", 4372 return -EINVAL); 4373 } 4374 4375 if ((0 == data->mclk_dpm_key_disabled) && 4376 !data->mclk_ignore_signal && 4377 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 4378 4379 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4380 "Trying to Unfreeze MCLK DPM when DPM is disabled", 4381 ); 4382 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4383 PPSMC_MSG_MCLKDPM_UnfreezeLevel, 4384 NULL), 4385 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", 4386 return -EINVAL); 4387 } 4388 4389 data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; 4390 4391 return 0; 4392 } 4393 4394 static int smu7_notify_link_speed_change_after_state_change( 4395 struct pp_hwmgr *hwmgr, const void *input) 4396 { 4397 const struct phm_set_power_state_input *states = 4398 (const struct phm_set_power_state_input *)input; 4399 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4400 const struct smu7_power_state *smu7_ps = 4401 cast_const_phw_smu7_power_state(states->pnew_state); 4402 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps); 4403 uint8_t request; 4404 4405 if (data->pspp_notify_required) { 4406 if (target_link_speed == PP_PCIEGen3) 4407 request = PCIE_PERF_REQ_GEN3; 4408 else if (target_link_speed == PP_PCIEGen2) 4409 request = PCIE_PERF_REQ_GEN2; 4410 else 4411 request = PCIE_PERF_REQ_GEN1; 4412 4413 if (request == PCIE_PERF_REQ_GEN1 && 4414 smu7_get_current_pcie_speed(hwmgr) > 0) 4415 return 0; 4416 4417 #ifdef CONFIG_ACPI 4418 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) { 4419 if (PP_PCIEGen2 == target_link_speed) 4420 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!"); 4421 else 4422 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!"); 4423 } 4424 #endif 4425 } 4426 4427 return 0; 4428 } 4429 4430 static int smu7_notify_no_display(struct pp_hwmgr *hwmgr) 4431 { 4432 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL) == 0) ? 0 : -EINVAL; 4433 } 4434 4435 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr) 4436 { 4437 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4438 4439 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { 4440 if (hwmgr->chip_id == CHIP_VEGAM) 4441 smum_send_msg_to_smc_with_parameter(hwmgr, 4442 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2, 4443 NULL); 4444 else 4445 smum_send_msg_to_smc_with_parameter(hwmgr, 4446 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2, 4447 NULL); 4448 data->last_sent_vbi_timeout = data->frame_time_x2; 4449 } 4450 4451 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ? 0 : -EINVAL; 4452 } 4453 4454 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) 4455 { 4456 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4457 int result = 0; 4458 4459 if (data->mclk_ignore_signal) 4460 result = smu7_notify_no_display(hwmgr); 4461 else 4462 result = smu7_notify_has_display(hwmgr); 4463 4464 return result; 4465 } 4466 4467 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) 4468 { 4469 int tmp_result, result = 0; 4470 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4471 4472 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input); 4473 PP_ASSERT_WITH_CODE((0 == tmp_result), 4474 "Failed to find DPM states clocks in DPM table!", 4475 result = tmp_result); 4476 4477 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 4478 PHM_PlatformCaps_PCIEPerformanceRequest)) { 4479 tmp_result = 4480 smu7_request_link_speed_change_before_state_change(hwmgr, input); 4481 PP_ASSERT_WITH_CODE((0 == tmp_result), 4482 "Failed to request link speed change before state change!", 4483 result = tmp_result); 4484 } 4485 4486 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr); 4487 PP_ASSERT_WITH_CODE((0 == tmp_result), 4488 "Failed to freeze SCLK MCLK DPM!", result = tmp_result); 4489 4490 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); 4491 PP_ASSERT_WITH_CODE((0 == tmp_result), 4492 "Failed to populate and upload SCLK MCLK DPM levels!", 4493 result = tmp_result); 4494 4495 /* 4496 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. 4497 * That effectively disables AVFS feature. 4498 */ 4499 if (hwmgr->hardcode_pp_table != NULL) 4500 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 4501 4502 tmp_result = smu7_update_avfs(hwmgr); 4503 PP_ASSERT_WITH_CODE((0 == tmp_result), 4504 "Failed to update avfs voltages!", 4505 result = tmp_result); 4506 4507 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input); 4508 PP_ASSERT_WITH_CODE((0 == tmp_result), 4509 "Failed to generate DPM level enabled mask!", 4510 result = tmp_result); 4511 4512 tmp_result = smum_update_sclk_threshold(hwmgr); 4513 PP_ASSERT_WITH_CODE((0 == tmp_result), 4514 "Failed to update SCLK threshold!", 4515 result = tmp_result); 4516 4517 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr); 4518 PP_ASSERT_WITH_CODE((0 == tmp_result), 4519 "Failed to unfreeze SCLK MCLK DPM!", 4520 result = tmp_result); 4521 4522 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr); 4523 PP_ASSERT_WITH_CODE((0 == tmp_result), 4524 "Failed to upload DPM level enabled mask!", 4525 result = tmp_result); 4526 4527 tmp_result = smu7_notify_smc_display(hwmgr); 4528 PP_ASSERT_WITH_CODE((0 == tmp_result), 4529 "Failed to notify smc display settings!", 4530 result = tmp_result); 4531 4532 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 4533 PHM_PlatformCaps_PCIEPerformanceRequest)) { 4534 tmp_result = 4535 smu7_notify_link_speed_change_after_state_change(hwmgr, input); 4536 PP_ASSERT_WITH_CODE((0 == tmp_result), 4537 "Failed to notify link speed change after state change!", 4538 result = tmp_result); 4539 } 4540 data->apply_optimized_settings = false; 4541 return result; 4542 } 4543 4544 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) 4545 { 4546 hwmgr->thermal_controller. 4547 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; 4548 4549 return smum_send_msg_to_smc_with_parameter(hwmgr, 4550 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm, 4551 NULL); 4552 } 4553 4554 static int 4555 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) 4556 { 4557 return 0; 4558 } 4559 4560 /** 4561 * smu7_program_display_gap - Programs the display gap 4562 * 4563 * @hwmgr: the address of the powerplay hardware manager. 4564 * Return: always OK 4565 */ 4566 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) 4567 { 4568 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4569 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); 4570 uint32_t display_gap2; 4571 uint32_t pre_vbi_time_in_us; 4572 uint32_t frame_time_in_us; 4573 uint32_t ref_clock, refresh_rate; 4574 4575 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); 4576 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); 4577 4578 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 4579 refresh_rate = hwmgr->display_config->vrefresh; 4580 4581 if (0 == refresh_rate) 4582 refresh_rate = 60; 4583 4584 frame_time_in_us = 1000000 / refresh_rate; 4585 4586 pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time; 4587 4588 data->frame_time_x2 = frame_time_in_us * 2 / 100; 4589 4590 if (data->frame_time_x2 < 280) { 4591 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2); 4592 data->frame_time_x2 = 280; 4593 } 4594 4595 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); 4596 4597 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); 4598 4599 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4600 data->soft_regs_start + smum_get_offsetof(hwmgr, 4601 SMU_SoftRegisters, 4602 PreVBlankGap), 0x64); 4603 4604 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4605 data->soft_regs_start + smum_get_offsetof(hwmgr, 4606 SMU_SoftRegisters, 4607 VBlankTimeout), 4608 (frame_time_in_us - pre_vbi_time_in_us)); 4609 4610 return 0; 4611 } 4612 4613 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 4614 { 4615 return smu7_program_display_gap(hwmgr); 4616 } 4617 4618 /** 4619 * smu7_set_max_fan_rpm_output - Set maximum target operating fan output RPM 4620 * 4621 * @hwmgr: the address of the powerplay hardware manager. 4622 * @us_max_fan_rpm: max operating fan RPM value. 4623 * Return: The response that came from the SMC. 4624 */ 4625 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) 4626 { 4627 hwmgr->thermal_controller. 4628 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; 4629 4630 return smum_send_msg_to_smc_with_parameter(hwmgr, 4631 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm, 4632 NULL); 4633 } 4634 4635 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = { 4636 .process = phm_irq_process, 4637 }; 4638 4639 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr) 4640 { 4641 struct amdgpu_irq_src *source = 4642 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL); 4643 4644 if (!source) 4645 return -ENOMEM; 4646 4647 source->funcs = &smu7_irq_funcs; 4648 4649 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4650 AMDGPU_IRQ_CLIENTID_LEGACY, 4651 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH, 4652 source); 4653 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4654 AMDGPU_IRQ_CLIENTID_LEGACY, 4655 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW, 4656 source); 4657 4658 /* Register CTF(GPIO_19) interrupt */ 4659 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4660 AMDGPU_IRQ_CLIENTID_LEGACY, 4661 VISLANDS30_IV_SRCID_GPIO_19, 4662 source); 4663 4664 return 0; 4665 } 4666 4667 static bool 4668 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 4669 { 4670 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4671 bool is_update_required = false; 4672 4673 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 4674 is_update_required = true; 4675 4676 if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh) 4677 is_update_required = true; 4678 4679 if (hwmgr->chip_id >= CHIP_POLARIS10 && 4680 hwmgr->chip_id <= CHIP_VEGAM && 4681 data->last_sent_vbi_timeout != data->frame_time_x2) 4682 is_update_required = true; 4683 4684 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { 4685 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr && 4686 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK || 4687 hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) 4688 is_update_required = true; 4689 } 4690 return is_update_required; 4691 } 4692 4693 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1, 4694 const struct smu7_performance_level *pl2) 4695 { 4696 return ((pl1->memory_clock == pl2->memory_clock) && 4697 (pl1->engine_clock == pl2->engine_clock) && 4698 (pl1->pcie_gen == pl2->pcie_gen) && 4699 (pl1->pcie_lane == pl2->pcie_lane)); 4700 } 4701 4702 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr, 4703 const struct pp_hw_power_state *pstate1, 4704 const struct pp_hw_power_state *pstate2, bool *equal) 4705 { 4706 const struct smu7_power_state *psa; 4707 const struct smu7_power_state *psb; 4708 int i; 4709 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4710 4711 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 4712 return -EINVAL; 4713 4714 psa = cast_const_phw_smu7_power_state(pstate1); 4715 psb = cast_const_phw_smu7_power_state(pstate2); 4716 /* If the two states don't even have the same number of performance levels they cannot be the same state. */ 4717 if (psa->performance_level_count != psb->performance_level_count) { 4718 *equal = false; 4719 return 0; 4720 } 4721 4722 for (i = 0; i < psa->performance_level_count; i++) { 4723 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { 4724 /* If we have found even one performance level pair that is different the states are different. */ 4725 *equal = false; 4726 return 0; 4727 } 4728 } 4729 4730 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 4731 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); 4732 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); 4733 *equal &= (psa->sclk_threshold == psb->sclk_threshold); 4734 /* For OD call, set value based on flag */ 4735 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | 4736 DPMTABLE_OD_UPDATE_MCLK | 4737 DPMTABLE_OD_UPDATE_VDDC)); 4738 4739 return 0; 4740 } 4741 4742 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr) 4743 { 4744 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4745 4746 uint32_t tmp; 4747 4748 /* Read MC indirect register offset 0x9F bits [3:0] to see 4749 * if VBIOS has already loaded a full version of MC ucode 4750 * or not. 4751 */ 4752 4753 smu7_get_mc_microcode_version(hwmgr); 4754 4755 data->need_long_memory_training = false; 4756 4757 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 4758 ixMC_IO_DEBUG_UP_13); 4759 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); 4760 4761 if (tmp & (1 << 23)) { 4762 data->mem_latency_high = MEM_LATENCY_HIGH; 4763 data->mem_latency_low = MEM_LATENCY_LOW; 4764 if ((hwmgr->chip_id == CHIP_POLARIS10) || 4765 (hwmgr->chip_id == CHIP_POLARIS11) || 4766 (hwmgr->chip_id == CHIP_POLARIS12)) 4767 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL); 4768 } else { 4769 data->mem_latency_high = 330; 4770 data->mem_latency_low = 330; 4771 if ((hwmgr->chip_id == CHIP_POLARIS10) || 4772 (hwmgr->chip_id == CHIP_POLARIS11) || 4773 (hwmgr->chip_id == CHIP_POLARIS12)) 4774 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL); 4775 } 4776 4777 return 0; 4778 } 4779 4780 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr) 4781 { 4782 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4783 4784 data->clock_registers.vCG_SPLL_FUNC_CNTL = 4785 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); 4786 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = 4787 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); 4788 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = 4789 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); 4790 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = 4791 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); 4792 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = 4793 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); 4794 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = 4795 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); 4796 data->clock_registers.vDLL_CNTL = 4797 cgs_read_register(hwmgr->device, mmDLL_CNTL); 4798 data->clock_registers.vMCLK_PWRMGT_CNTL = 4799 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); 4800 data->clock_registers.vMPLL_AD_FUNC_CNTL = 4801 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); 4802 data->clock_registers.vMPLL_DQ_FUNC_CNTL = 4803 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); 4804 data->clock_registers.vMPLL_FUNC_CNTL = 4805 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); 4806 data->clock_registers.vMPLL_FUNC_CNTL_1 = 4807 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); 4808 data->clock_registers.vMPLL_FUNC_CNTL_2 = 4809 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); 4810 data->clock_registers.vMPLL_SS1 = 4811 cgs_read_register(hwmgr->device, mmMPLL_SS1); 4812 data->clock_registers.vMPLL_SS2 = 4813 cgs_read_register(hwmgr->device, mmMPLL_SS2); 4814 return 0; 4815 4816 } 4817 4818 /** 4819 * smu7_get_memory_type - Find out if memory is GDDR5. 4820 * 4821 * @hwmgr: the address of the powerplay hardware manager. 4822 * Return: always 0 4823 */ 4824 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr) 4825 { 4826 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4827 struct amdgpu_device *adev = hwmgr->adev; 4828 4829 data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5); 4830 4831 return 0; 4832 } 4833 4834 /** 4835 * smu7_enable_acpi_power_management - Enables Dynamic Power Management by SMC 4836 * 4837 * @hwmgr: the address of the powerplay hardware manager. 4838 * Return: always 0 4839 */ 4840 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr) 4841 { 4842 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 4843 GENERAL_PWRMGT, STATIC_PM_EN, 1); 4844 4845 return 0; 4846 } 4847 4848 /** 4849 * smu7_init_power_gate_state - Initialize PowerGating States for different engines 4850 * 4851 * @hwmgr: the address of the powerplay hardware manager. 4852 * Return: always 0 4853 */ 4854 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr) 4855 { 4856 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4857 4858 data->uvd_power_gated = false; 4859 data->vce_power_gated = false; 4860 4861 return 0; 4862 } 4863 4864 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr) 4865 { 4866 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4867 4868 data->low_sclk_interrupt_threshold = 0; 4869 return 0; 4870 } 4871 4872 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) 4873 { 4874 int tmp_result, result = 0; 4875 4876 smu7_check_mc_firmware(hwmgr); 4877 4878 tmp_result = smu7_read_clock_registers(hwmgr); 4879 PP_ASSERT_WITH_CODE((0 == tmp_result), 4880 "Failed to read clock registers!", result = tmp_result); 4881 4882 tmp_result = smu7_get_memory_type(hwmgr); 4883 PP_ASSERT_WITH_CODE((0 == tmp_result), 4884 "Failed to get memory type!", result = tmp_result); 4885 4886 tmp_result = smu7_enable_acpi_power_management(hwmgr); 4887 PP_ASSERT_WITH_CODE((0 == tmp_result), 4888 "Failed to enable ACPI power management!", result = tmp_result); 4889 4890 tmp_result = smu7_init_power_gate_state(hwmgr); 4891 PP_ASSERT_WITH_CODE((0 == tmp_result), 4892 "Failed to init power gate state!", result = tmp_result); 4893 4894 tmp_result = smu7_get_mc_microcode_version(hwmgr); 4895 PP_ASSERT_WITH_CODE((0 == tmp_result), 4896 "Failed to get MC microcode version!", result = tmp_result); 4897 4898 tmp_result = smu7_init_sclk_threshold(hwmgr); 4899 PP_ASSERT_WITH_CODE((0 == tmp_result), 4900 "Failed to init sclk threshold!", result = tmp_result); 4901 4902 return result; 4903 } 4904 4905 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 4906 enum pp_clock_type type, uint32_t mask) 4907 { 4908 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4909 4910 if (mask == 0) 4911 return -EINVAL; 4912 4913 switch (type) { 4914 case PP_SCLK: 4915 if (!data->sclk_dpm_key_disabled) 4916 smum_send_msg_to_smc_with_parameter(hwmgr, 4917 PPSMC_MSG_SCLKDPM_SetEnabledMask, 4918 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask, 4919 NULL); 4920 break; 4921 case PP_MCLK: 4922 if (!data->mclk_dpm_key_disabled) 4923 smum_send_msg_to_smc_with_parameter(hwmgr, 4924 PPSMC_MSG_MCLKDPM_SetEnabledMask, 4925 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask, 4926 NULL); 4927 break; 4928 case PP_PCIE: 4929 { 4930 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; 4931 4932 if (!data->pcie_dpm_key_disabled) { 4933 if (fls(tmp) != ffs(tmp)) 4934 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel, 4935 NULL); 4936 else 4937 smum_send_msg_to_smc_with_parameter(hwmgr, 4938 PPSMC_MSG_PCIeDPM_ForceLevel, 4939 fls(tmp) - 1, 4940 NULL); 4941 } 4942 break; 4943 } 4944 default: 4945 break; 4946 } 4947 4948 return 0; 4949 } 4950 4951 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, 4952 enum pp_clock_type type, char *buf) 4953 { 4954 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4955 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4956 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4957 struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); 4958 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 4959 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); 4960 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); 4961 int size = 0; 4962 uint32_t i, now, clock, pcie_speed; 4963 4964 switch (type) { 4965 case PP_SCLK: 4966 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock); 4967 4968 for (i = 0; i < sclk_table->count; i++) { 4969 if (clock > sclk_table->dpm_levels[i].value) 4970 continue; 4971 break; 4972 } 4973 now = i; 4974 4975 for (i = 0; i < sclk_table->count; i++) 4976 size += sprintf(buf + size, "%d: %uMhz %s\n", 4977 i, sclk_table->dpm_levels[i].value / 100, 4978 (i == now) ? "*" : ""); 4979 break; 4980 case PP_MCLK: 4981 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock); 4982 4983 for (i = 0; i < mclk_table->count; i++) { 4984 if (clock > mclk_table->dpm_levels[i].value) 4985 continue; 4986 break; 4987 } 4988 now = i; 4989 4990 for (i = 0; i < mclk_table->count; i++) 4991 size += sprintf(buf + size, "%d: %uMhz %s\n", 4992 i, mclk_table->dpm_levels[i].value / 100, 4993 (i == now) ? "*" : ""); 4994 break; 4995 case PP_PCIE: 4996 pcie_speed = smu7_get_current_pcie_speed(hwmgr); 4997 for (i = 0; i < pcie_table->count; i++) { 4998 if (pcie_speed != pcie_table->dpm_levels[i].value) 4999 continue; 5000 break; 5001 } 5002 now = i; 5003 5004 for (i = 0; i < pcie_table->count; i++) 5005 size += sprintf(buf + size, "%d: %s %s\n", i, 5006 (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" : 5007 (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : 5008 (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", 5009 (i == now) ? "*" : ""); 5010 break; 5011 case OD_SCLK: 5012 if (hwmgr->od_enabled) { 5013 size += sprintf(buf + size, "%s:\n", "OD_SCLK"); 5014 for (i = 0; i < odn_sclk_table->num_of_pl; i++) 5015 size += sprintf(buf + size, "%d: %10uMHz %10umV\n", 5016 i, odn_sclk_table->entries[i].clock/100, 5017 odn_sclk_table->entries[i].vddc); 5018 } 5019 break; 5020 case OD_MCLK: 5021 if (hwmgr->od_enabled) { 5022 size += sprintf(buf + size, "%s:\n", "OD_MCLK"); 5023 for (i = 0; i < odn_mclk_table->num_of_pl; i++) 5024 size += sprintf(buf + size, "%d: %10uMHz %10umV\n", 5025 i, odn_mclk_table->entries[i].clock/100, 5026 odn_mclk_table->entries[i].vddc); 5027 } 5028 break; 5029 case OD_RANGE: 5030 if (hwmgr->od_enabled) { 5031 size += sprintf(buf + size, "%s:\n", "OD_RANGE"); 5032 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", 5033 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, 5034 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5035 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", 5036 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, 5037 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5038 size += sprintf(buf + size, "VDDC: %7umV %11umV\n", 5039 data->odn_dpm_table.min_vddc, 5040 data->odn_dpm_table.max_vddc); 5041 } 5042 break; 5043 default: 5044 break; 5045 } 5046 return size; 5047 } 5048 5049 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 5050 { 5051 switch (mode) { 5052 case AMD_FAN_CTRL_NONE: 5053 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 5054 break; 5055 case AMD_FAN_CTRL_MANUAL: 5056 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 5057 PHM_PlatformCaps_MicrocodeFanControl)) 5058 smu7_fan_ctrl_stop_smc_fan_control(hwmgr); 5059 break; 5060 case AMD_FAN_CTRL_AUTO: 5061 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode)) 5062 smu7_fan_ctrl_start_smc_fan_control(hwmgr); 5063 break; 5064 default: 5065 break; 5066 } 5067 } 5068 5069 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) 5070 { 5071 return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL; 5072 } 5073 5074 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr) 5075 { 5076 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5077 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 5078 struct smu7_single_dpm_table *golden_sclk_table = 5079 &(data->golden_dpm_table.sclk_table); 5080 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 5081 int golden_value = golden_sclk_table->dpm_levels 5082 [golden_sclk_table->count - 1].value; 5083 5084 value -= golden_value; 5085 value = DIV_ROUND_UP(value * 100, golden_value); 5086 5087 return value; 5088 } 5089 5090 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5091 { 5092 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5093 struct smu7_single_dpm_table *golden_sclk_table = 5094 &(data->golden_dpm_table.sclk_table); 5095 struct pp_power_state *ps; 5096 struct smu7_power_state *smu7_ps; 5097 5098 if (value > 20) 5099 value = 20; 5100 5101 ps = hwmgr->request_ps; 5102 5103 if (ps == NULL) 5104 return -EINVAL; 5105 5106 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 5107 5108 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock = 5109 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * 5110 value / 100 + 5111 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; 5112 5113 return 0; 5114 } 5115 5116 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr) 5117 { 5118 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5119 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 5120 struct smu7_single_dpm_table *golden_mclk_table = 5121 &(data->golden_dpm_table.mclk_table); 5122 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 5123 int golden_value = golden_mclk_table->dpm_levels 5124 [golden_mclk_table->count - 1].value; 5125 5126 value -= golden_value; 5127 value = DIV_ROUND_UP(value * 100, golden_value); 5128 5129 return value; 5130 } 5131 5132 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5133 { 5134 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5135 struct smu7_single_dpm_table *golden_mclk_table = 5136 &(data->golden_dpm_table.mclk_table); 5137 struct pp_power_state *ps; 5138 struct smu7_power_state *smu7_ps; 5139 5140 if (value > 20) 5141 value = 20; 5142 5143 ps = hwmgr->request_ps; 5144 5145 if (ps == NULL) 5146 return -EINVAL; 5147 5148 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 5149 5150 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock = 5151 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * 5152 value / 100 + 5153 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; 5154 5155 return 0; 5156 } 5157 5158 5159 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 5160 { 5161 struct phm_ppt_v1_information *table_info = 5162 (struct phm_ppt_v1_information *)hwmgr->pptable; 5163 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; 5164 struct phm_clock_voltage_dependency_table *sclk_table; 5165 int i; 5166 5167 if (hwmgr->pp_table_version == PP_TABLE_V1) { 5168 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) 5169 return -EINVAL; 5170 dep_sclk_table = table_info->vdd_dep_on_sclk; 5171 for (i = 0; i < dep_sclk_table->count; i++) 5172 clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; 5173 clocks->count = dep_sclk_table->count; 5174 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 5175 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 5176 for (i = 0; i < sclk_table->count; i++) 5177 clocks->clock[i] = sclk_table->entries[i].clk * 10; 5178 clocks->count = sclk_table->count; 5179 } 5180 5181 return 0; 5182 } 5183 5184 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk) 5185 { 5186 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5187 5188 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY) 5189 return data->mem_latency_high; 5190 else if (clk >= MEM_FREQ_HIGH_LATENCY) 5191 return data->mem_latency_low; 5192 else 5193 return MEM_LATENCY_ERR; 5194 } 5195 5196 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 5197 { 5198 struct phm_ppt_v1_information *table_info = 5199 (struct phm_ppt_v1_information *)hwmgr->pptable; 5200 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 5201 int i; 5202 struct phm_clock_voltage_dependency_table *mclk_table; 5203 5204 if (hwmgr->pp_table_version == PP_TABLE_V1) { 5205 if (table_info == NULL) 5206 return -EINVAL; 5207 dep_mclk_table = table_info->vdd_dep_on_mclk; 5208 for (i = 0; i < dep_mclk_table->count; i++) { 5209 clocks->clock[i] = dep_mclk_table->entries[i].clk * 10; 5210 clocks->latency[i] = smu7_get_mem_latency(hwmgr, 5211 dep_mclk_table->entries[i].clk); 5212 } 5213 clocks->count = dep_mclk_table->count; 5214 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 5215 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 5216 for (i = 0; i < mclk_table->count; i++) 5217 clocks->clock[i] = mclk_table->entries[i].clk * 10; 5218 clocks->count = mclk_table->count; 5219 } 5220 return 0; 5221 } 5222 5223 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, 5224 struct amd_pp_clocks *clocks) 5225 { 5226 switch (type) { 5227 case amd_pp_sys_clock: 5228 smu7_get_sclks(hwmgr, clocks); 5229 break; 5230 case amd_pp_mem_clock: 5231 smu7_get_mclks(hwmgr, clocks); 5232 break; 5233 default: 5234 return -EINVAL; 5235 } 5236 5237 return 0; 5238 } 5239 5240 static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr, 5241 struct pp_clock_levels_with_latency *clocks) 5242 { 5243 struct phm_ppt_v1_information *table_info = 5244 (struct phm_ppt_v1_information *)hwmgr->pptable; 5245 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = 5246 table_info->vdd_dep_on_sclk; 5247 int i; 5248 5249 clocks->num_levels = 0; 5250 for (i = 0; i < dep_sclk_table->count; i++) { 5251 if (dep_sclk_table->entries[i].clk) { 5252 clocks->data[clocks->num_levels].clocks_in_khz = 5253 dep_sclk_table->entries[i].clk * 10; 5254 clocks->num_levels++; 5255 } 5256 } 5257 5258 return 0; 5259 } 5260 5261 static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr, 5262 struct pp_clock_levels_with_latency *clocks) 5263 { 5264 struct phm_ppt_v1_information *table_info = 5265 (struct phm_ppt_v1_information *)hwmgr->pptable; 5266 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 5267 table_info->vdd_dep_on_mclk; 5268 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5269 int i; 5270 5271 clocks->num_levels = 0; 5272 data->mclk_latency_table.count = 0; 5273 for (i = 0; i < dep_mclk_table->count; i++) { 5274 if (dep_mclk_table->entries[i].clk) { 5275 clocks->data[clocks->num_levels].clocks_in_khz = 5276 dep_mclk_table->entries[i].clk * 10; 5277 data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency = 5278 dep_mclk_table->entries[i].clk; 5279 clocks->data[clocks->num_levels].latency_in_us = 5280 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency = 5281 smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk); 5282 clocks->num_levels++; 5283 data->mclk_latency_table.count++; 5284 } 5285 } 5286 5287 return 0; 5288 } 5289 5290 static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 5291 enum amd_pp_clock_type type, 5292 struct pp_clock_levels_with_latency *clocks) 5293 { 5294 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 5295 hwmgr->chip_id <= CHIP_VEGAM)) 5296 return -EINVAL; 5297 5298 switch (type) { 5299 case amd_pp_sys_clock: 5300 smu7_get_sclks_with_latency(hwmgr, clocks); 5301 break; 5302 case amd_pp_mem_clock: 5303 smu7_get_mclks_with_latency(hwmgr, clocks); 5304 break; 5305 default: 5306 return -EINVAL; 5307 } 5308 5309 return 0; 5310 } 5311 5312 static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 5313 void *clock_range) 5314 { 5315 struct phm_ppt_v1_information *table_info = 5316 (struct phm_ppt_v1_information *)hwmgr->pptable; 5317 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 5318 table_info->vdd_dep_on_mclk; 5319 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = 5320 table_info->vdd_dep_on_sclk; 5321 struct polaris10_smumgr *smu_data = 5322 (struct polaris10_smumgr *)(hwmgr->smu_backend); 5323 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 5324 struct dm_pp_wm_sets_with_clock_ranges *watermarks = 5325 (struct dm_pp_wm_sets_with_clock_ranges *)clock_range; 5326 uint32_t i, j, k; 5327 bool valid_entry; 5328 5329 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 5330 hwmgr->chip_id <= CHIP_VEGAM)) 5331 return -EINVAL; 5332 5333 for (i = 0; i < dep_mclk_table->count; i++) { 5334 for (j = 0; j < dep_sclk_table->count; j++) { 5335 valid_entry = false; 5336 for (k = 0; k < watermarks->num_wm_sets; k++) { 5337 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && 5338 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && 5339 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && 5340 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { 5341 valid_entry = true; 5342 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id; 5343 break; 5344 } 5345 } 5346 PP_ASSERT_WITH_CODE(valid_entry, 5347 "Clock is not in range of specified clock range for watermark from DAL! Using highest water mark set.", 5348 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id); 5349 } 5350 } 5351 5352 return smu7_copy_bytes_to_smc(hwmgr, 5353 smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, DisplayWatermark), 5354 (uint8_t *)table->DisplayWatermark, 5355 sizeof(uint8_t) * SMU74_MAX_LEVELS_MEMORY * SMU74_MAX_LEVELS_GRAPHICS, 5356 SMC_RAM_END); 5357 } 5358 5359 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 5360 uint32_t virtual_addr_low, 5361 uint32_t virtual_addr_hi, 5362 uint32_t mc_addr_low, 5363 uint32_t mc_addr_hi, 5364 uint32_t size) 5365 { 5366 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5367 5368 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5369 data->soft_regs_start + 5370 smum_get_offsetof(hwmgr, 5371 SMU_SoftRegisters, DRAM_LOG_ADDR_H), 5372 mc_addr_hi); 5373 5374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5375 data->soft_regs_start + 5376 smum_get_offsetof(hwmgr, 5377 SMU_SoftRegisters, DRAM_LOG_ADDR_L), 5378 mc_addr_low); 5379 5380 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5381 data->soft_regs_start + 5382 smum_get_offsetof(hwmgr, 5383 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H), 5384 virtual_addr_hi); 5385 5386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5387 data->soft_regs_start + 5388 smum_get_offsetof(hwmgr, 5389 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L), 5390 virtual_addr_low); 5391 5392 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5393 data->soft_regs_start + 5394 smum_get_offsetof(hwmgr, 5395 SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE), 5396 size); 5397 return 0; 5398 } 5399 5400 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr, 5401 struct amd_pp_simple_clock_info *clocks) 5402 { 5403 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5404 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 5405 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 5406 5407 if (clocks == NULL) 5408 return -EINVAL; 5409 5410 clocks->memory_max_clock = mclk_table->count > 1 ? 5411 mclk_table->dpm_levels[mclk_table->count-1].value : 5412 mclk_table->dpm_levels[0].value; 5413 clocks->engine_max_clock = sclk_table->count > 1 ? 5414 sclk_table->dpm_levels[sclk_table->count-1].value : 5415 sclk_table->dpm_levels[0].value; 5416 return 0; 5417 } 5418 5419 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 5420 struct PP_TemperatureRange *thermal_data) 5421 { 5422 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5423 struct phm_ppt_v1_information *table_info = 5424 (struct phm_ppt_v1_information *)hwmgr->pptable; 5425 5426 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange)); 5427 5428 if (hwmgr->pp_table_version == PP_TABLE_V1) 5429 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp * 5430 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5431 else if (hwmgr->pp_table_version == PP_TABLE_V0) 5432 thermal_data->max = data->thermal_temp_setting.temperature_shutdown * 5433 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5434 5435 return 0; 5436 } 5437 5438 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, 5439 enum PP_OD_DPM_TABLE_COMMAND type, 5440 uint32_t clk, 5441 uint32_t voltage) 5442 { 5443 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5444 5445 if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) { 5446 pr_info("OD voltage is out of range [%d - %d] mV\n", 5447 data->odn_dpm_table.min_vddc, 5448 data->odn_dpm_table.max_vddc); 5449 return false; 5450 } 5451 5452 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5453 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk || 5454 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { 5455 pr_info("OD engine clock is out of range [%d - %d] MHz\n", 5456 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, 5457 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5458 return false; 5459 } 5460 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5461 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk || 5462 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { 5463 pr_info("OD memory clock is out of range [%d - %d] MHz\n", 5464 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, 5465 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5466 return false; 5467 } 5468 } else { 5469 return false; 5470 } 5471 5472 return true; 5473 } 5474 5475 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 5476 enum PP_OD_DPM_TABLE_COMMAND type, 5477 long *input, uint32_t size) 5478 { 5479 uint32_t i; 5480 struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL; 5481 struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL; 5482 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5483 5484 uint32_t input_clk; 5485 uint32_t input_vol; 5486 uint32_t input_level; 5487 5488 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 5489 return -EINVAL); 5490 5491 if (!hwmgr->od_enabled) { 5492 pr_info("OverDrive feature not enabled\n"); 5493 return -EINVAL; 5494 } 5495 5496 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { 5497 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels; 5498 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk; 5499 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), 5500 "Failed to get ODN SCLK and Voltage tables", 5501 return -EINVAL); 5502 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { 5503 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels; 5504 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk; 5505 5506 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), 5507 "Failed to get ODN MCLK and Voltage tables", 5508 return -EINVAL); 5509 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { 5510 smu7_odn_initial_default_setting(hwmgr); 5511 return 0; 5512 } else if (PP_OD_COMMIT_DPM_TABLE == type) { 5513 smu7_check_dpm_table_updated(hwmgr); 5514 return 0; 5515 } else { 5516 return -EINVAL; 5517 } 5518 5519 for (i = 0; i < size; i += 3) { 5520 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) { 5521 pr_info("invalid clock voltage input \n"); 5522 return 0; 5523 } 5524 input_level = input[i]; 5525 input_clk = input[i+1] * 100; 5526 input_vol = input[i+2]; 5527 5528 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { 5529 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; 5530 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; 5531 podn_dpm_table_in_backend->entries[input_level].vddc = input_vol; 5532 podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol; 5533 podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol; 5534 } else { 5535 return -EINVAL; 5536 } 5537 } 5538 5539 return 0; 5540 } 5541 5542 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 5543 { 5544 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5545 uint32_t i, size = 0; 5546 uint32_t len; 5547 5548 static const char *title[8] = {"NUM", 5549 "MODE_NAME", 5550 "SCLK_UP_HYST", 5551 "SCLK_DOWN_HYST", 5552 "SCLK_ACTIVE_LEVEL", 5553 "MCLK_UP_HYST", 5554 "MCLK_DOWN_HYST", 5555 "MCLK_ACTIVE_LEVEL"}; 5556 5557 if (!buf) 5558 return -EINVAL; 5559 5560 phm_get_sysfs_buf(&buf, &size); 5561 5562 size += sysfs_emit_at(buf, size, "%s %16s %16s %16s %16s %16s %16s %16s\n", 5563 title[0], title[1], title[2], title[3], 5564 title[4], title[5], title[6], title[7]); 5565 5566 len = ARRAY_SIZE(smu7_profiling); 5567 5568 for (i = 0; i < len; i++) { 5569 if (i == hwmgr->power_profile_mode) { 5570 size += sysfs_emit_at(buf, size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n", 5571 i, amdgpu_pp_profile_name[i], "*", 5572 data->current_profile_setting.sclk_up_hyst, 5573 data->current_profile_setting.sclk_down_hyst, 5574 data->current_profile_setting.sclk_activity, 5575 data->current_profile_setting.mclk_up_hyst, 5576 data->current_profile_setting.mclk_down_hyst, 5577 data->current_profile_setting.mclk_activity); 5578 continue; 5579 } 5580 if (smu7_profiling[i].bupdate_sclk) 5581 size += sysfs_emit_at(buf, size, "%3d %16s: %8d %16d %16d ", 5582 i, amdgpu_pp_profile_name[i], smu7_profiling[i].sclk_up_hyst, 5583 smu7_profiling[i].sclk_down_hyst, 5584 smu7_profiling[i].sclk_activity); 5585 else 5586 size += sysfs_emit_at(buf, size, "%3d %16s: %8s %16s %16s ", 5587 i, amdgpu_pp_profile_name[i], "-", "-", "-"); 5588 5589 if (smu7_profiling[i].bupdate_mclk) 5590 size += sysfs_emit_at(buf, size, "%16d %16d %16d\n", 5591 smu7_profiling[i].mclk_up_hyst, 5592 smu7_profiling[i].mclk_down_hyst, 5593 smu7_profiling[i].mclk_activity); 5594 else 5595 size += sysfs_emit_at(buf, size, "%16s %16s %16s\n", 5596 "-", "-", "-"); 5597 } 5598 5599 return size; 5600 } 5601 5602 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr, 5603 enum PP_SMC_POWER_PROFILE requst) 5604 { 5605 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5606 uint32_t tmp, level; 5607 5608 if (requst == PP_SMC_POWER_PROFILE_COMPUTE) { 5609 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 5610 level = 0; 5611 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; 5612 while (tmp >>= 1) 5613 level++; 5614 if (level > 0) 5615 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); 5616 } 5617 } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) { 5618 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); 5619 } 5620 } 5621 5622 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 5623 { 5624 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5625 struct profile_mode_setting tmp; 5626 enum PP_SMC_POWER_PROFILE mode; 5627 5628 if (input == NULL) 5629 return -EINVAL; 5630 5631 mode = input[size]; 5632 switch (mode) { 5633 case PP_SMC_POWER_PROFILE_CUSTOM: 5634 if (size < 8 && size != 0) 5635 return -EINVAL; 5636 /* If only CUSTOM is passed in, use the saved values. Check 5637 * that we actually have a CUSTOM profile by ensuring that 5638 * the "use sclk" or the "use mclk" bits are set 5639 */ 5640 tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM]; 5641 if (size == 0) { 5642 if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0) 5643 return -EINVAL; 5644 } else { 5645 tmp.bupdate_sclk = input[0]; 5646 tmp.sclk_up_hyst = input[1]; 5647 tmp.sclk_down_hyst = input[2]; 5648 tmp.sclk_activity = input[3]; 5649 tmp.bupdate_mclk = input[4]; 5650 tmp.mclk_up_hyst = input[5]; 5651 tmp.mclk_down_hyst = input[6]; 5652 tmp.mclk_activity = input[7]; 5653 smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp; 5654 } 5655 if (!smum_update_dpm_settings(hwmgr, &tmp)) { 5656 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting)); 5657 hwmgr->power_profile_mode = mode; 5658 } 5659 break; 5660 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 5661 case PP_SMC_POWER_PROFILE_POWERSAVING: 5662 case PP_SMC_POWER_PROFILE_VIDEO: 5663 case PP_SMC_POWER_PROFILE_VR: 5664 case PP_SMC_POWER_PROFILE_COMPUTE: 5665 if (mode == hwmgr->power_profile_mode) 5666 return 0; 5667 5668 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting)); 5669 if (!smum_update_dpm_settings(hwmgr, &tmp)) { 5670 if (tmp.bupdate_sclk) { 5671 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk; 5672 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst; 5673 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst; 5674 data->current_profile_setting.sclk_activity = tmp.sclk_activity; 5675 } 5676 if (tmp.bupdate_mclk) { 5677 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk; 5678 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst; 5679 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst; 5680 data->current_profile_setting.mclk_activity = tmp.mclk_activity; 5681 } 5682 smu7_patch_compute_profile_mode(hwmgr, mode); 5683 hwmgr->power_profile_mode = mode; 5684 } 5685 break; 5686 default: 5687 return -EINVAL; 5688 } 5689 5690 return 0; 5691 } 5692 5693 static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 5694 PHM_PerformanceLevelDesignation designation, uint32_t index, 5695 PHM_PerformanceLevel *level) 5696 { 5697 const struct smu7_power_state *ps; 5698 uint32_t i; 5699 5700 if (level == NULL || hwmgr == NULL || state == NULL) 5701 return -EINVAL; 5702 5703 ps = cast_const_phw_smu7_power_state(state); 5704 5705 i = index > ps->performance_level_count - 1 ? 5706 ps->performance_level_count - 1 : index; 5707 5708 level->coreClock = ps->performance_levels[i].engine_clock; 5709 level->memory_clock = ps->performance_levels[i].memory_clock; 5710 5711 return 0; 5712 } 5713 5714 static int smu7_power_off_asic(struct pp_hwmgr *hwmgr) 5715 { 5716 int result; 5717 5718 result = smu7_disable_dpm_tasks(hwmgr); 5719 PP_ASSERT_WITH_CODE((0 == result), 5720 "[disable_dpm_tasks] Failed to disable DPM!", 5721 ); 5722 5723 return result; 5724 } 5725 5726 static const struct pp_hwmgr_func smu7_hwmgr_funcs = { 5727 .backend_init = &smu7_hwmgr_backend_init, 5728 .backend_fini = &smu7_hwmgr_backend_fini, 5729 .asic_setup = &smu7_setup_asic_task, 5730 .dynamic_state_management_enable = &smu7_enable_dpm_tasks, 5731 .apply_state_adjust_rules = smu7_apply_state_adjust_rules, 5732 .force_dpm_level = &smu7_force_dpm_level, 5733 .power_state_set = smu7_set_power_state_tasks, 5734 .get_power_state_size = smu7_get_power_state_size, 5735 .get_mclk = smu7_dpm_get_mclk, 5736 .get_sclk = smu7_dpm_get_sclk, 5737 .patch_boot_state = smu7_dpm_patch_boot_state, 5738 .get_pp_table_entry = smu7_get_pp_table_entry, 5739 .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries, 5740 .powerdown_uvd = smu7_powerdown_uvd, 5741 .powergate_uvd = smu7_powergate_uvd, 5742 .powergate_vce = smu7_powergate_vce, 5743 .disable_clock_power_gating = smu7_disable_clock_power_gating, 5744 .update_clock_gatings = smu7_update_clock_gatings, 5745 .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment, 5746 .display_config_changed = smu7_display_configuration_changed_task, 5747 .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output, 5748 .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output, 5749 .stop_thermal_controller = smu7_thermal_stop_thermal_controller, 5750 .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info, 5751 .get_fan_speed_pwm = smu7_fan_ctrl_get_fan_speed_pwm, 5752 .set_fan_speed_pwm = smu7_fan_ctrl_set_fan_speed_pwm, 5753 .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default, 5754 .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm, 5755 .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm, 5756 .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller, 5757 .register_irq_handlers = smu7_register_irq_handlers, 5758 .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration, 5759 .check_states_equal = smu7_check_states_equal, 5760 .set_fan_control_mode = smu7_set_fan_control_mode, 5761 .get_fan_control_mode = smu7_get_fan_control_mode, 5762 .force_clock_level = smu7_force_clock_level, 5763 .print_clock_levels = smu7_print_clock_levels, 5764 .powergate_gfx = smu7_powergate_gfx, 5765 .get_sclk_od = smu7_get_sclk_od, 5766 .set_sclk_od = smu7_set_sclk_od, 5767 .get_mclk_od = smu7_get_mclk_od, 5768 .set_mclk_od = smu7_set_mclk_od, 5769 .get_clock_by_type = smu7_get_clock_by_type, 5770 .get_clock_by_type_with_latency = smu7_get_clock_by_type_with_latency, 5771 .set_watermarks_for_clocks_ranges = smu7_set_watermarks_for_clocks_ranges, 5772 .read_sensor = smu7_read_sensor, 5773 .dynamic_state_management_disable = smu7_disable_dpm_tasks, 5774 .avfs_control = smu7_avfs_control, 5775 .disable_smc_firmware_ctf = smu7_thermal_disable_alert, 5776 .start_thermal_controller = smu7_start_thermal_controller, 5777 .notify_cac_buffer_info = smu7_notify_cac_buffer_info, 5778 .get_max_high_clocks = smu7_get_max_high_clocks, 5779 .get_thermal_temperature_range = smu7_get_thermal_temperature_range, 5780 .odn_edit_dpm_table = smu7_odn_edit_dpm_table, 5781 .set_power_limit = smu7_set_power_limit, 5782 .get_power_profile_mode = smu7_get_power_profile_mode, 5783 .set_power_profile_mode = smu7_set_power_profile_mode, 5784 .get_performance_level = smu7_get_performance_level, 5785 .get_asic_baco_capability = smu7_baco_get_capability, 5786 .get_asic_baco_state = smu7_baco_get_state, 5787 .set_asic_baco_state = smu7_baco_set_state, 5788 .power_off_asic = smu7_power_off_asic, 5789 }; 5790 5791 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 5792 uint32_t clock_insr) 5793 { 5794 uint8_t i; 5795 uint32_t temp; 5796 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK); 5797 5798 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0); 5799 for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 5800 temp = clock >> i; 5801 5802 if (temp >= min || i == 0) 5803 break; 5804 } 5805 return i; 5806 } 5807 5808 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr) 5809 { 5810 hwmgr->hwmgr_func = &smu7_hwmgr_funcs; 5811 if (hwmgr->pp_table_version == PP_TABLE_V0) 5812 hwmgr->pptable_func = &pptable_funcs; 5813 else if (hwmgr->pp_table_version == PP_TABLE_V1) 5814 hwmgr->pptable_func = &pptable_v1_0_funcs; 5815 5816 return 0; 5817 } 5818