1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU10_HWMGR_H 25 #define SMU10_HWMGR_H 26 27 #include "hwmgr.h" 28 #include "smu10_inc.h" 29 #include "smu10_driver_if.h" 30 #include "rv_ppsmc.h" 31 32 33 #define SMU10_MAX_HARDWARE_POWERLEVELS 8 34 #define SMU10_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15 35 36 #define DPMFlags_SCLK_Enabled 0x00000001 37 #define DPMFlags_UVD_Enabled 0x00000002 38 #define DPMFlags_VCE_Enabled 0x00000004 39 #define DPMFlags_ACP_Enabled 0x00000008 40 #define DPMFlags_ForceHighestValid 0x40000000 41 42 /* Do not change the following, it is also defined in SMU8.h */ 43 #define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 44 #define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000 45 #define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x01000000 46 #define SMU_EnabledFeatureScoreboard_VceDpmOn 0x02000000 47 48 #define SMU_PHYID_SHIFT 8 49 50 #define SMU10_PCIE_POWERGATING_TARGET_GFX 0 51 #define SMU10_PCIE_POWERGATING_TARGET_DDI 1 52 #define SMU10_PCIE_POWERGATING_TARGET_PLLCASCADE 2 53 #define SMU10_PCIE_POWERGATING_TARGET_PHY 3 54 55 enum VQ_TYPE { 56 CLOCK_TYPE_DCLK = 0L, 57 CLOCK_TYPE_ECLK, 58 CLOCK_TYPE_SCLK, 59 CLOCK_TYPE_CCLK, 60 VQ_GFX_CU 61 }; 62 63 #define SUSTAINABLE_SCLK_MASK 0x00ffffff 64 #define SUSTAINABLE_SCLK_SHIFT 0 65 #define SUSTAINABLE_CU_MASK 0xff000000 66 #define SUSTAINABLE_CU_SHIFT 24 67 68 struct smu10_dpm_entry { 69 uint32_t soft_min_clk; 70 uint32_t hard_min_clk; 71 uint32_t soft_max_clk; 72 uint32_t hard_max_clk; 73 }; 74 75 struct smu10_power_level { 76 uint32_t engine_clock; 77 uint8_t vddc_index; 78 uint8_t ds_divider_index; 79 uint8_t ss_divider_index; 80 uint8_t allow_gnb_slow; 81 uint8_t force_nbp_state; 82 uint8_t display_wm; 83 uint8_t vce_wm; 84 uint8_t num_simd_to_powerdown; 85 uint8_t hysteresis_up; 86 uint8_t rsv[3]; 87 }; 88 89 /*used for the nbpsFlags field in smu10_power state*/ 90 #define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0) 91 #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1) 92 #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2) 93 94 #define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0) 95 96 struct smu10_uvd_clocks { 97 uint32_t vclk; 98 uint32_t dclk; 99 uint32_t vclk_low_divider; 100 uint32_t vclk_high_divider; 101 uint32_t dclk_low_divider; 102 uint32_t dclk_high_divider; 103 }; 104 105 struct pp_disable_nbpslo_flags { 106 union { 107 struct { 108 uint32_t entry : 1; 109 uint32_t display : 1; 110 uint32_t driver: 1; 111 uint32_t vce : 1; 112 uint32_t uvd : 1; 113 uint32_t acp : 1; 114 uint32_t reserved: 26; 115 } bits; 116 uint32_t u32All; 117 }; 118 }; 119 120 121 enum smu10_pstate_previous_action { 122 DO_NOTHING = 1, 123 FORCE_HIGH, 124 CANCEL_FORCE_HIGH 125 }; 126 127 struct smu10_power_state { 128 unsigned int magic; 129 uint32_t level; 130 struct smu10_uvd_clocks uvd_clocks; 131 uint32_t evclk; 132 uint32_t ecclk; 133 uint32_t samclk; 134 uint32_t acpclk; 135 bool need_dfs_bypass; 136 137 uint32_t nbps_flags; 138 uint32_t bapm_flags; 139 uint8_t dpm0_pg_nbps_low; 140 uint8_t dpm0_pg_nbps_high; 141 uint8_t dpm_x_nbps_low; 142 uint8_t dpm_x_nbps_high; 143 144 enum smu10_pstate_previous_action action; 145 146 struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS]; 147 struct pp_disable_nbpslo_flags nbpslo_flags; 148 }; 149 150 #define SMU10_NUM_NBPSTATES 4 151 #define SMU10_NUM_NBPMEMORYCLOCK 2 152 153 154 struct smu10_display_phy_info_entry { 155 uint8_t phy_present; 156 uint8_t active_lane_mapping; 157 uint8_t display_config_type; 158 uint8_t active_num_of_lanes; 159 }; 160 161 #define SMU10_MAX_DISPLAYPHY_IDS 10 162 163 struct smu10_display_phy_info { 164 bool display_phy_access_initialized; 165 struct smu10_display_phy_info_entry entries[SMU10_MAX_DISPLAYPHY_IDS]; 166 }; 167 168 #define MAX_DISPLAY_CLOCK_LEVEL 8 169 170 struct smu10_system_info{ 171 uint8_t htc_tmp_lmt; 172 uint8_t htc_hyst_lmt; 173 }; 174 175 #define MAX_REGULAR_DPM_NUMBER 8 176 177 struct smu10_mclk_latency_entries { 178 uint32_t frequency; 179 uint32_t latency; 180 }; 181 182 struct smu10_mclk_latency_table { 183 uint32_t count; 184 struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 185 }; 186 187 struct smu10_clock_voltage_dependency_record { 188 uint32_t clk; 189 uint32_t vol; 190 }; 191 192 193 struct smu10_voltage_dependency_table { 194 uint32_t count; 195 struct smu10_clock_voltage_dependency_record entries[] __counted_by(count); 196 }; 197 198 struct smu10_clock_voltage_information { 199 struct smu10_voltage_dependency_table *vdd_dep_on_dcefclk; 200 struct smu10_voltage_dependency_table *vdd_dep_on_socclk; 201 struct smu10_voltage_dependency_table *vdd_dep_on_fclk; 202 struct smu10_voltage_dependency_table *vdd_dep_on_mclk; 203 struct smu10_voltage_dependency_table *vdd_dep_on_dispclk; 204 struct smu10_voltage_dependency_table *vdd_dep_on_dppclk; 205 struct smu10_voltage_dependency_table *vdd_dep_on_phyclk; 206 }; 207 208 struct smu10_hwmgr { 209 uint32_t disable_driver_thermal_policy; 210 uint32_t thermal_auto_throttling_treshold; 211 struct smu10_system_info sys_info; 212 struct smu10_mclk_latency_table mclk_latency_table; 213 214 uint32_t ddi_power_gating_disabled; 215 216 struct smu10_display_phy_info_entry display_phy_info; 217 uint32_t dce_slow_sclk_threshold; 218 219 bool disp_clk_bypass; 220 bool disp_clk_bypass_pending; 221 uint32_t bapm_enabled; 222 223 bool video_start; 224 bool battery_state; 225 226 uint32_t is_nb_dpm_enabled; 227 uint32_t is_voltage_island_enabled; 228 uint32_t disable_smu_acp_s3_handshake; 229 uint32_t disable_notify_smu_vpu_recovery; 230 bool in_vpu_recovery; 231 bool pg_acp_init; 232 uint8_t disp_config; 233 234 /* PowerTune */ 235 uint32_t power_containment_features; 236 bool cac_enabled; 237 bool disable_uvd_power_tune_feature; 238 bool enable_bapm_feature; 239 bool enable_tdc_limit_feature; 240 241 242 /* SMC SRAM Address of firmware header tables */ 243 uint32_t sram_end; 244 uint32_t dpm_table_start; 245 uint32_t soft_regs_start; 246 247 /* start of SMU7_Fusion_DpmTable */ 248 249 uint8_t uvd_level_count; 250 uint8_t vce_level_count; 251 uint8_t acp_level_count; 252 uint8_t samu_level_count; 253 254 uint32_t fps_high_threshold; 255 uint32_t fps_low_threshold; 256 257 uint32_t dpm_flags; 258 struct smu10_dpm_entry sclk_dpm; 259 struct smu10_dpm_entry uvd_dpm; 260 struct smu10_dpm_entry vce_dpm; 261 struct smu10_dpm_entry acp_dpm; 262 bool acp_power_up_no_dsp; 263 264 uint32_t max_sclk_level; 265 uint32_t num_of_clk_entries; 266 267 /* CPU Power State */ 268 uint32_t separation_time; 269 bool cc6_disable; 270 bool pstate_disable; 271 bool cc6_setting_changed; 272 273 uint32_t ulTotalActiveCUs; 274 275 bool isp_tileA_power_gated; 276 bool isp_tileB_power_gated; 277 uint32_t isp_actual_hard_min_freq; 278 uint32_t soc_actual_hard_min_freq; 279 uint32_t dcf_actual_hard_min_freq; 280 281 uint32_t f_actual_hard_min_freq; 282 uint32_t fabric_actual_soft_min_freq; 283 uint32_t vclk_soft_min; 284 uint32_t dclk_soft_min; 285 uint32_t gfx_actual_soft_min_freq; 286 uint32_t gfx_actual_soft_max_freq; 287 uint32_t gfx_min_freq_limit; 288 uint32_t gfx_max_freq_limit; /* in 10Khz*/ 289 290 bool vcn_power_gated; 291 bool vcn_dpg_mode; 292 293 bool gfx_off_controled_by_driver; 294 bool water_marks_exist; 295 Watermarks_t water_marks_table; 296 struct smu10_clock_voltage_information clock_vol_info; 297 DpmClocks_t clock_table; 298 299 uint32_t active_process_mask; 300 bool need_min_deep_sleep_dcefclk; 301 uint32_t deep_sleep_dcefclk; 302 uint32_t num_active_display; 303 304 bool fine_grain_enabled; 305 }; 306 307 struct pp_hwmgr; 308 309 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr); 310 311 /* UMD PState SMU10 Msg Parameters in MHz */ 312 #define SMU10_UMD_PSTATE_GFXCLK 700 313 #define SMU10_UMD_PSTATE_SOCCLK 626 314 #define SMU10_UMD_PSTATE_FCLK 933 315 #define SMU10_UMD_PSTATE_VCE 0x03C00320 316 #define SMU10_UMD_PSTATE_PROFILE_VCE 0x02AD0229 317 318 #define SMU10_UMD_PSTATE_PEAK_SOCCLK 757 319 #define SMU10_UMD_PSTATE_PEAK_FCLK 1200 320 321 #define SMU10_UMD_PSTATE_MIN_FCLK 400 322 #define SMU10_UMD_PSTATE_MIN_SOCCLK 200 323 #define SMU10_UMD_PSTATE_MIN_VCE 0x0190012C 324 325 #endif 326