1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2015 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan *
22e098bc96SEvan Quan */
23e098bc96SEvan Quan #include "pp_debug.h"
24e098bc96SEvan Quan #include <linux/errno.h>
25e098bc96SEvan Quan #include "hwmgr.h"
26e098bc96SEvan Quan #include "hardwaremanager.h"
27e098bc96SEvan Quan #include "power_state.h"
28e098bc96SEvan Quan
29e098bc96SEvan Quan
30e098bc96SEvan Quan #define TEMP_RANGE_MIN (0)
31e098bc96SEvan Quan #define TEMP_RANGE_MAX (80 * 1000)
32e098bc96SEvan Quan
33e098bc96SEvan Quan #define PHM_FUNC_CHECK(hw) \
34e098bc96SEvan Quan do { \
35e098bc96SEvan Quan if ((hw) == NULL || (hw)->hwmgr_func == NULL) \
36e098bc96SEvan Quan return -EINVAL; \
37e098bc96SEvan Quan } while (0)
38e098bc96SEvan Quan
phm_setup_asic(struct pp_hwmgr * hwmgr)39e098bc96SEvan Quan int phm_setup_asic(struct pp_hwmgr *hwmgr)
40e098bc96SEvan Quan {
41e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
42e098bc96SEvan Quan
43e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->asic_setup)
44e098bc96SEvan Quan return hwmgr->hwmgr_func->asic_setup(hwmgr);
45e098bc96SEvan Quan
46e098bc96SEvan Quan return 0;
47e098bc96SEvan Quan }
48e098bc96SEvan Quan
phm_power_down_asic(struct pp_hwmgr * hwmgr)49e098bc96SEvan Quan int phm_power_down_asic(struct pp_hwmgr *hwmgr)
50e098bc96SEvan Quan {
51e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
52e098bc96SEvan Quan
53e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->power_off_asic)
54e098bc96SEvan Quan return hwmgr->hwmgr_func->power_off_asic(hwmgr);
55e098bc96SEvan Quan
56e098bc96SEvan Quan return 0;
57e098bc96SEvan Quan }
58e098bc96SEvan Quan
phm_set_power_state(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * pcurrent_state,const struct pp_hw_power_state * pnew_power_state)59e098bc96SEvan Quan int phm_set_power_state(struct pp_hwmgr *hwmgr,
60e098bc96SEvan Quan const struct pp_hw_power_state *pcurrent_state,
61e098bc96SEvan Quan const struct pp_hw_power_state *pnew_power_state)
62e098bc96SEvan Quan {
63e098bc96SEvan Quan struct phm_set_power_state_input states;
64e098bc96SEvan Quan
65e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
66e098bc96SEvan Quan
67e098bc96SEvan Quan states.pcurrent_state = pcurrent_state;
68e098bc96SEvan Quan states.pnew_state = pnew_power_state;
69e098bc96SEvan Quan
70e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->power_state_set)
71e098bc96SEvan Quan return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
72e098bc96SEvan Quan
73e098bc96SEvan Quan return 0;
74e098bc96SEvan Quan }
75e098bc96SEvan Quan
phm_enable_dynamic_state_management(struct pp_hwmgr * hwmgr)76e098bc96SEvan Quan int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
77e098bc96SEvan Quan {
78e098bc96SEvan Quan struct amdgpu_device *adev = NULL;
79e098bc96SEvan Quan int ret = -EINVAL;
80e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
81e098bc96SEvan Quan adev = hwmgr->adev;
82e098bc96SEvan Quan
83e098bc96SEvan Quan /* Skip for suspend/resume case */
84e098bc96SEvan Quan if (!hwmgr->pp_one_vf && smum_is_dpm_running(hwmgr)
85e0172928SXiaojian Du && !amdgpu_passthrough(adev) && adev->in_suspend
86e0172928SXiaojian Du && adev->asic_type != CHIP_RAVEN) {
87e098bc96SEvan Quan pr_info("dpm has been enabled\n");
88e098bc96SEvan Quan return 0;
89e098bc96SEvan Quan }
90e098bc96SEvan Quan
91e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
92e098bc96SEvan Quan ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
93e098bc96SEvan Quan
94e098bc96SEvan Quan return ret;
95e098bc96SEvan Quan }
96e098bc96SEvan Quan
phm_disable_dynamic_state_management(struct pp_hwmgr * hwmgr)97e098bc96SEvan Quan int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
98e098bc96SEvan Quan {
99e098bc96SEvan Quan int ret = -EINVAL;
100e098bc96SEvan Quan
101e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
102e098bc96SEvan Quan
103e098bc96SEvan Quan if (!hwmgr->not_vf)
104e098bc96SEvan Quan return 0;
105e098bc96SEvan Quan
106e098bc96SEvan Quan if (!smum_is_dpm_running(hwmgr)) {
107e098bc96SEvan Quan pr_info("dpm has been disabled\n");
108e098bc96SEvan Quan return 0;
109e098bc96SEvan Quan }
110e098bc96SEvan Quan
111e098bc96SEvan Quan if (hwmgr->hwmgr_func->dynamic_state_management_disable)
112e098bc96SEvan Quan ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
113e098bc96SEvan Quan
114e098bc96SEvan Quan return ret;
115e098bc96SEvan Quan }
116e098bc96SEvan Quan
phm_force_dpm_levels(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level)117e098bc96SEvan Quan int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
118e098bc96SEvan Quan {
119e098bc96SEvan Quan int ret = 0;
120e098bc96SEvan Quan
121e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
122e098bc96SEvan Quan
123e098bc96SEvan Quan if (hwmgr->hwmgr_func->force_dpm_level != NULL)
124e098bc96SEvan Quan ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
125e098bc96SEvan Quan
126e098bc96SEvan Quan return ret;
127e098bc96SEvan Quan }
128e098bc96SEvan Quan
phm_apply_state_adjust_rules(struct pp_hwmgr * hwmgr,struct pp_power_state * adjusted_ps,const struct pp_power_state * current_ps)129e098bc96SEvan Quan int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
130e098bc96SEvan Quan struct pp_power_state *adjusted_ps,
131e098bc96SEvan Quan const struct pp_power_state *current_ps)
132e098bc96SEvan Quan {
133e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
134e098bc96SEvan Quan
135e098bc96SEvan Quan if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
136e098bc96SEvan Quan return hwmgr->hwmgr_func->apply_state_adjust_rules(
137e098bc96SEvan Quan hwmgr,
138e098bc96SEvan Quan adjusted_ps,
139e098bc96SEvan Quan current_ps);
140e098bc96SEvan Quan return 0;
141e098bc96SEvan Quan }
142e098bc96SEvan Quan
phm_apply_clock_adjust_rules(struct pp_hwmgr * hwmgr)143e098bc96SEvan Quan int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr)
144e098bc96SEvan Quan {
145e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
146e098bc96SEvan Quan
147e098bc96SEvan Quan if (hwmgr->hwmgr_func->apply_clocks_adjust_rules != NULL)
148e098bc96SEvan Quan return hwmgr->hwmgr_func->apply_clocks_adjust_rules(hwmgr);
149e098bc96SEvan Quan return 0;
150e098bc96SEvan Quan }
151e098bc96SEvan Quan
phm_powerdown_uvd(struct pp_hwmgr * hwmgr)152e098bc96SEvan Quan int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
153e098bc96SEvan Quan {
154e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
155e098bc96SEvan Quan
156e098bc96SEvan Quan if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
157e098bc96SEvan Quan return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
158e098bc96SEvan Quan return 0;
159e098bc96SEvan Quan }
160e098bc96SEvan Quan
161e098bc96SEvan Quan
phm_disable_clock_power_gatings(struct pp_hwmgr * hwmgr)162e098bc96SEvan Quan int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
163e098bc96SEvan Quan {
164e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
165e098bc96SEvan Quan
166e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
167e098bc96SEvan Quan return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
168e098bc96SEvan Quan
169e098bc96SEvan Quan return 0;
170e098bc96SEvan Quan }
171e098bc96SEvan Quan
phm_pre_display_configuration_changed(struct pp_hwmgr * hwmgr)172e098bc96SEvan Quan int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr)
173e098bc96SEvan Quan {
174e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
175e098bc96SEvan Quan
176e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->pre_display_config_changed)
177e098bc96SEvan Quan hwmgr->hwmgr_func->pre_display_config_changed(hwmgr);
178e098bc96SEvan Quan
179e098bc96SEvan Quan return 0;
180e098bc96SEvan Quan
181e098bc96SEvan Quan }
182e098bc96SEvan Quan
phm_display_configuration_changed(struct pp_hwmgr * hwmgr)183e098bc96SEvan Quan int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
184e098bc96SEvan Quan {
185e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
186e098bc96SEvan Quan
187e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->display_config_changed)
188e098bc96SEvan Quan hwmgr->hwmgr_func->display_config_changed(hwmgr);
189e098bc96SEvan Quan
190e098bc96SEvan Quan return 0;
191e098bc96SEvan Quan }
192e098bc96SEvan Quan
phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr * hwmgr)193e098bc96SEvan Quan int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
194e098bc96SEvan Quan {
195e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
196e098bc96SEvan Quan
197e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
198e098bc96SEvan Quan hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
199e098bc96SEvan Quan
200e098bc96SEvan Quan return 0;
201e098bc96SEvan Quan }
202e098bc96SEvan Quan
phm_stop_thermal_controller(struct pp_hwmgr * hwmgr)203e098bc96SEvan Quan int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
204e098bc96SEvan Quan {
205e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
206e098bc96SEvan Quan
207e098bc96SEvan Quan if (!hwmgr->not_vf)
208e098bc96SEvan Quan return 0;
209e098bc96SEvan Quan
210e098bc96SEvan Quan if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
211e098bc96SEvan Quan return -EINVAL;
212e098bc96SEvan Quan
213e098bc96SEvan Quan return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
214e098bc96SEvan Quan }
215e098bc96SEvan Quan
phm_register_irq_handlers(struct pp_hwmgr * hwmgr)216e098bc96SEvan Quan int phm_register_irq_handlers(struct pp_hwmgr *hwmgr)
217e098bc96SEvan Quan {
218e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
219e098bc96SEvan Quan
220e098bc96SEvan Quan if (hwmgr->hwmgr_func->register_irq_handlers != NULL)
221e098bc96SEvan Quan return hwmgr->hwmgr_func->register_irq_handlers(hwmgr);
222e098bc96SEvan Quan
223e098bc96SEvan Quan return 0;
224e098bc96SEvan Quan }
225e098bc96SEvan Quan
226e098bc96SEvan Quan /**
227b4643c50SLee Jones * phm_start_thermal_controller - Initializes the thermal controller subsystem.
228e098bc96SEvan Quan *
229b4643c50SLee Jones * @hwmgr: the address of the powerplay hardware manager.
230b4643c50SLee Jones * Exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
231e098bc96SEvan Quan */
phm_start_thermal_controller(struct pp_hwmgr * hwmgr)232e098bc96SEvan Quan int phm_start_thermal_controller(struct pp_hwmgr *hwmgr)
233e098bc96SEvan Quan {
234e098bc96SEvan Quan int ret = 0;
235e098bc96SEvan Quan struct PP_TemperatureRange range = {
236e098bc96SEvan Quan TEMP_RANGE_MIN,
237e098bc96SEvan Quan TEMP_RANGE_MAX,
238e098bc96SEvan Quan TEMP_RANGE_MAX,
239e098bc96SEvan Quan TEMP_RANGE_MIN,
240e098bc96SEvan Quan TEMP_RANGE_MAX,
241e098bc96SEvan Quan TEMP_RANGE_MAX,
242e098bc96SEvan Quan TEMP_RANGE_MIN,
243e098bc96SEvan Quan TEMP_RANGE_MAX,
244*064329c5SEvan Quan TEMP_RANGE_MAX,
245*064329c5SEvan Quan 0};
246e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
247e098bc96SEvan Quan
248e098bc96SEvan Quan if (!hwmgr->not_vf)
249e098bc96SEvan Quan return 0;
250e098bc96SEvan Quan
251e098bc96SEvan Quan if (hwmgr->hwmgr_func->get_thermal_temperature_range)
252e098bc96SEvan Quan hwmgr->hwmgr_func->get_thermal_temperature_range(
253e098bc96SEvan Quan hwmgr, &range);
254e098bc96SEvan Quan
255e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
256e098bc96SEvan Quan PHM_PlatformCaps_ThermalController)
257e098bc96SEvan Quan && hwmgr->hwmgr_func->start_thermal_controller != NULL)
258e098bc96SEvan Quan ret = hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
259e098bc96SEvan Quan
260e098bc96SEvan Quan adev->pm.dpm.thermal.min_temp = range.min;
261e098bc96SEvan Quan adev->pm.dpm.thermal.max_temp = range.max;
262e098bc96SEvan Quan adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
263e098bc96SEvan Quan adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
264e098bc96SEvan Quan adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
265e098bc96SEvan Quan adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
266e098bc96SEvan Quan adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
267e098bc96SEvan Quan adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
268e098bc96SEvan Quan adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
269*064329c5SEvan Quan adev->pm.dpm.thermal.sw_ctf_threshold = range.sw_ctf_threshold;
270e098bc96SEvan Quan
271e098bc96SEvan Quan return ret;
272e098bc96SEvan Quan }
273e098bc96SEvan Quan
274e098bc96SEvan Quan
phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr * hwmgr)275e098bc96SEvan Quan bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
276e098bc96SEvan Quan {
2776c4d1f43SEvan Quan if (hwmgr == NULL ||
2786c4d1f43SEvan Quan hwmgr->hwmgr_func == NULL)
2796c4d1f43SEvan Quan return false;
2806c4d1f43SEvan Quan
281e098bc96SEvan Quan if (hwmgr->pp_one_vf)
282e098bc96SEvan Quan return false;
283e098bc96SEvan Quan
284e098bc96SEvan Quan if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
285e098bc96SEvan Quan return false;
286e098bc96SEvan Quan
287e098bc96SEvan Quan return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
288e098bc96SEvan Quan }
289e098bc96SEvan Quan
290e098bc96SEvan Quan
phm_check_states_equal(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * pstate1,const struct pp_hw_power_state * pstate2,bool * equal)291e098bc96SEvan Quan int phm_check_states_equal(struct pp_hwmgr *hwmgr,
292e098bc96SEvan Quan const struct pp_hw_power_state *pstate1,
293e098bc96SEvan Quan const struct pp_hw_power_state *pstate2,
294e098bc96SEvan Quan bool *equal)
295e098bc96SEvan Quan {
296e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
297e098bc96SEvan Quan
298e098bc96SEvan Quan if (hwmgr->hwmgr_func->check_states_equal == NULL)
299e098bc96SEvan Quan return -EINVAL;
300e098bc96SEvan Quan
301e098bc96SEvan Quan return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
302e098bc96SEvan Quan }
303e098bc96SEvan Quan
phm_store_dal_configuration_data(struct pp_hwmgr * hwmgr,const struct amd_pp_display_configuration * display_config)304e098bc96SEvan Quan int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
305e098bc96SEvan Quan const struct amd_pp_display_configuration *display_config)
306e098bc96SEvan Quan {
307e098bc96SEvan Quan int index = 0;
308e098bc96SEvan Quan int number_of_active_display = 0;
309e098bc96SEvan Quan
310e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
311e098bc96SEvan Quan
312e098bc96SEvan Quan if (display_config == NULL)
313e098bc96SEvan Quan return -EINVAL;
314e098bc96SEvan Quan
315e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk)
316e098bc96SEvan Quan hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
317e098bc96SEvan Quan
318e098bc96SEvan Quan for (index = 0; index < display_config->num_path_including_non_display; index++) {
319e098bc96SEvan Quan if (display_config->displays[index].controller_id != 0)
320e098bc96SEvan Quan number_of_active_display++;
321e098bc96SEvan Quan }
322e098bc96SEvan Quan
323e098bc96SEvan Quan if (NULL != hwmgr->hwmgr_func->set_active_display_count)
324e098bc96SEvan Quan hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display);
325e098bc96SEvan Quan
326e098bc96SEvan Quan if (hwmgr->hwmgr_func->store_cc6_data == NULL)
327e098bc96SEvan Quan return -EINVAL;
328e098bc96SEvan Quan
329e098bc96SEvan Quan /* TODO: pass other display configuration in the future */
330e098bc96SEvan Quan
331e098bc96SEvan Quan if (hwmgr->hwmgr_func->store_cc6_data)
332e098bc96SEvan Quan hwmgr->hwmgr_func->store_cc6_data(hwmgr,
333e098bc96SEvan Quan display_config->cpu_pstate_separation_time,
334e098bc96SEvan Quan display_config->cpu_cc6_disable,
335e098bc96SEvan Quan display_config->cpu_pstate_disable,
336e098bc96SEvan Quan display_config->nb_pstate_switch_disable);
337e098bc96SEvan Quan
338e098bc96SEvan Quan return 0;
339e098bc96SEvan Quan }
340e098bc96SEvan Quan
phm_get_dal_power_level(struct pp_hwmgr * hwmgr,struct amd_pp_simple_clock_info * info)341e098bc96SEvan Quan int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
342e098bc96SEvan Quan struct amd_pp_simple_clock_info *info)
343e098bc96SEvan Quan {
344e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
345e098bc96SEvan Quan
346e098bc96SEvan Quan if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
347e098bc96SEvan Quan return -EINVAL;
348e098bc96SEvan Quan return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
349e098bc96SEvan Quan }
350e098bc96SEvan Quan
phm_set_cpu_power_state(struct pp_hwmgr * hwmgr)351e098bc96SEvan Quan int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
352e098bc96SEvan Quan {
353e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
354e098bc96SEvan Quan
355e098bc96SEvan Quan if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
356e098bc96SEvan Quan return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
357e098bc96SEvan Quan
358e098bc96SEvan Quan return 0;
359e098bc96SEvan Quan }
360e098bc96SEvan Quan
361e098bc96SEvan Quan
phm_get_performance_level(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,PHM_PerformanceLevelDesignation designation,uint32_t index,PHM_PerformanceLevel * level)362e098bc96SEvan Quan int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
363e098bc96SEvan Quan PHM_PerformanceLevelDesignation designation, uint32_t index,
364e098bc96SEvan Quan PHM_PerformanceLevel *level)
365e098bc96SEvan Quan {
366e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
367e098bc96SEvan Quan if (hwmgr->hwmgr_func->get_performance_level == NULL)
368e098bc96SEvan Quan return -EINVAL;
369e098bc96SEvan Quan
370e098bc96SEvan Quan return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
371e098bc96SEvan Quan
372e098bc96SEvan Quan
373e098bc96SEvan Quan }
374e098bc96SEvan Quan
375e098bc96SEvan Quan
376e098bc96SEvan Quan /**
377b4643c50SLee Jones * phm_get_clock_info
378e098bc96SEvan Quan *
379b4643c50SLee Jones * @hwmgr: the address of the powerplay hardware manager.
380b4643c50SLee Jones * @state: the address of the Power State structure.
381b4643c50SLee Jones * @pclock_info: the address of PP_ClockInfo structure where the result will be returned.
382b4643c50SLee Jones * @designation: PHM performance level designation
383b4643c50SLee Jones * Exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
384e098bc96SEvan Quan */
phm_get_clock_info(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,struct pp_clock_info * pclock_info,PHM_PerformanceLevelDesignation designation)385e098bc96SEvan Quan int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
386e098bc96SEvan Quan PHM_PerformanceLevelDesignation designation)
387e098bc96SEvan Quan {
388e098bc96SEvan Quan int result;
389e098bc96SEvan Quan PHM_PerformanceLevel performance_level = {0};
390e098bc96SEvan Quan
391e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
392e098bc96SEvan Quan
393e098bc96SEvan Quan PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
394e098bc96SEvan Quan PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
395e098bc96SEvan Quan
396e098bc96SEvan Quan result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
397e098bc96SEvan Quan
398e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
399e098bc96SEvan Quan
400e098bc96SEvan Quan
401e098bc96SEvan Quan pclock_info->min_mem_clk = performance_level.memory_clock;
402e098bc96SEvan Quan pclock_info->min_eng_clk = performance_level.coreClock;
403e098bc96SEvan Quan pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
404e098bc96SEvan Quan
405e098bc96SEvan Quan
406e098bc96SEvan Quan result = phm_get_performance_level(hwmgr, state, designation,
407e098bc96SEvan Quan (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
408e098bc96SEvan Quan
409e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
410e098bc96SEvan Quan
411e098bc96SEvan Quan pclock_info->max_mem_clk = performance_level.memory_clock;
412e098bc96SEvan Quan pclock_info->max_eng_clk = performance_level.coreClock;
413e098bc96SEvan Quan pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
414e098bc96SEvan Quan
415e098bc96SEvan Quan return 0;
416e098bc96SEvan Quan }
417e098bc96SEvan Quan
phm_get_current_shallow_sleep_clocks(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,struct pp_clock_info * clock_info)418e098bc96SEvan Quan int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
419e098bc96SEvan Quan {
420e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
421e098bc96SEvan Quan
422e098bc96SEvan Quan if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
423e098bc96SEvan Quan return -EINVAL;
424e098bc96SEvan Quan
425e098bc96SEvan Quan return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
426e098bc96SEvan Quan
427e098bc96SEvan Quan }
428e098bc96SEvan Quan
phm_get_clock_by_type(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct amd_pp_clocks * clocks)429e098bc96SEvan Quan int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
430e098bc96SEvan Quan {
431e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
432e098bc96SEvan Quan
433e098bc96SEvan Quan if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
434e098bc96SEvan Quan return -EINVAL;
435e098bc96SEvan Quan
436e098bc96SEvan Quan return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
437e098bc96SEvan Quan
438e098bc96SEvan Quan }
439e098bc96SEvan Quan
phm_get_clock_by_type_with_latency(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)440e098bc96SEvan Quan int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
441e098bc96SEvan Quan enum amd_pp_clock_type type,
442e098bc96SEvan Quan struct pp_clock_levels_with_latency *clocks)
443e098bc96SEvan Quan {
444e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
445e098bc96SEvan Quan
446e098bc96SEvan Quan if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
447e098bc96SEvan Quan return -EINVAL;
448e098bc96SEvan Quan
449e098bc96SEvan Quan return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);
450e098bc96SEvan Quan
451e098bc96SEvan Quan }
452e098bc96SEvan Quan
phm_get_clock_by_type_with_voltage(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_voltage * clocks)453e098bc96SEvan Quan int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
454e098bc96SEvan Quan enum amd_pp_clock_type type,
455e098bc96SEvan Quan struct pp_clock_levels_with_voltage *clocks)
456e098bc96SEvan Quan {
457e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
458e098bc96SEvan Quan
459e098bc96SEvan Quan if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
460e098bc96SEvan Quan return -EINVAL;
461e098bc96SEvan Quan
462e098bc96SEvan Quan return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);
463e098bc96SEvan Quan
464e098bc96SEvan Quan }
465e098bc96SEvan Quan
phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr * hwmgr,void * clock_ranges)466e098bc96SEvan Quan int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
467e098bc96SEvan Quan void *clock_ranges)
468e098bc96SEvan Quan {
469e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
470e098bc96SEvan Quan
471e098bc96SEvan Quan if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges)
472e098bc96SEvan Quan return -EINVAL;
473e098bc96SEvan Quan
474e098bc96SEvan Quan return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
475e098bc96SEvan Quan clock_ranges);
476e098bc96SEvan Quan }
477e098bc96SEvan Quan
phm_display_clock_voltage_request(struct pp_hwmgr * hwmgr,struct pp_display_clock_request * clock)478e098bc96SEvan Quan int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
479e098bc96SEvan Quan struct pp_display_clock_request *clock)
480e098bc96SEvan Quan {
481e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
482e098bc96SEvan Quan
483e098bc96SEvan Quan if (!hwmgr->hwmgr_func->display_clock_voltage_request)
484e098bc96SEvan Quan return -EINVAL;
485e098bc96SEvan Quan
486e098bc96SEvan Quan return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);
487e098bc96SEvan Quan }
488e098bc96SEvan Quan
phm_get_max_high_clocks(struct pp_hwmgr * hwmgr,struct amd_pp_simple_clock_info * clocks)489e098bc96SEvan Quan int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
490e098bc96SEvan Quan {
491e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
492e098bc96SEvan Quan
493e098bc96SEvan Quan if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
494e098bc96SEvan Quan return -EINVAL;
495e098bc96SEvan Quan
496e098bc96SEvan Quan return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
497e098bc96SEvan Quan }
498e098bc96SEvan Quan
phm_disable_smc_firmware_ctf(struct pp_hwmgr * hwmgr)499e098bc96SEvan Quan int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr)
500e098bc96SEvan Quan {
501e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
502e098bc96SEvan Quan
503e098bc96SEvan Quan if (!hwmgr->not_vf)
504e098bc96SEvan Quan return 0;
505e098bc96SEvan Quan
506e098bc96SEvan Quan if (hwmgr->hwmgr_func->disable_smc_firmware_ctf == NULL)
507e098bc96SEvan Quan return -EINVAL;
508e098bc96SEvan Quan
509e098bc96SEvan Quan return hwmgr->hwmgr_func->disable_smc_firmware_ctf(hwmgr);
510e098bc96SEvan Quan }
511e098bc96SEvan Quan
phm_set_active_display_count(struct pp_hwmgr * hwmgr,uint32_t count)512e098bc96SEvan Quan int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
513e098bc96SEvan Quan {
514e098bc96SEvan Quan PHM_FUNC_CHECK(hwmgr);
515e098bc96SEvan Quan
516e098bc96SEvan Quan if (!hwmgr->hwmgr_func->set_active_display_count)
517e098bc96SEvan Quan return -EINVAL;
518e098bc96SEvan Quan
519e098bc96SEvan Quan return hwmgr->hwmgr_func->set_active_display_count(hwmgr, count);
520e098bc96SEvan Quan }
521