1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/types.h> 24 #include <linux/kernel.h> 25 #include <linux/gfp.h> 26 #include <linux/slab.h> 27 #include <linux/firmware.h> 28 #include <linux/reboot.h> 29 #include "amd_shared.h" 30 #include "power_state.h" 31 #include "amdgpu.h" 32 #include "hwmgr.h" 33 #include "amdgpu_dpm_internal.h" 34 35 static const struct amd_pm_funcs pp_dpm_funcs; 36 37 static int amd_powerplay_create(struct amdgpu_device *adev) 38 { 39 struct pp_hwmgr *hwmgr; 40 41 if (adev == NULL) 42 return -EINVAL; 43 44 hwmgr = kzalloc_obj(struct pp_hwmgr); 45 if (hwmgr == NULL) 46 return -ENOMEM; 47 48 hwmgr->adev = adev; 49 hwmgr->not_vf = !amdgpu_sriov_vf(adev); 50 hwmgr->device = amdgpu_cgs_create_device(adev); 51 if (!hwmgr->device) { 52 kfree(hwmgr); 53 return -ENOMEM; 54 } 55 56 mutex_init(&hwmgr->msg_lock); 57 hwmgr->chip_family = adev->family; 58 hwmgr->chip_id = adev->asic_type; 59 hwmgr->feature_mask = adev->pm.pp_feature; 60 hwmgr->display_config = &adev->pm.pm_display_cfg; 61 adev->powerplay.pp_handle = hwmgr; 62 adev->powerplay.pp_funcs = &pp_dpm_funcs; 63 return 0; 64 } 65 66 67 static void amd_powerplay_destroy(struct amdgpu_device *adev) 68 { 69 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 70 71 mutex_destroy(&hwmgr->msg_lock); 72 73 kfree(hwmgr->hardcode_pp_table); 74 hwmgr->hardcode_pp_table = NULL; 75 76 kfree(hwmgr); 77 hwmgr = NULL; 78 } 79 80 static int pp_early_init(struct amdgpu_ip_block *ip_block) 81 { 82 int ret; 83 struct amdgpu_device *adev = ip_block->adev; 84 ret = amd_powerplay_create(adev); 85 86 if (ret != 0) 87 return ret; 88 89 ret = hwmgr_early_init(adev->powerplay.pp_handle); 90 if (ret) 91 return -EINVAL; 92 93 return 0; 94 } 95 96 static void pp_swctf_delayed_work_handler(struct work_struct *work) 97 { 98 struct pp_hwmgr *hwmgr = 99 container_of(work, struct pp_hwmgr, swctf_delayed_work.work); 100 struct amdgpu_device *adev = hwmgr->adev; 101 struct amdgpu_dpm_thermal *range = 102 &adev->pm.dpm.thermal; 103 uint32_t gpu_temperature, size = sizeof(gpu_temperature); 104 int ret; 105 106 /* 107 * If the hotspot/edge temperature is confirmed as below SW CTF setting point 108 * after the delay enforced, nothing will be done. 109 * Otherwise, a graceful shutdown will be performed to prevent further damage. 110 */ 111 if (range->sw_ctf_threshold && 112 hwmgr->hwmgr_func->read_sensor) { 113 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, 114 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 115 &gpu_temperature, 116 &size); 117 /* 118 * For some legacy ASICs, hotspot temperature retrieving might be not 119 * supported. Check the edge temperature instead then. 120 */ 121 if (ret == -EOPNOTSUPP) 122 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, 123 AMDGPU_PP_SENSOR_EDGE_TEMP, 124 &gpu_temperature, 125 &size); 126 if (!ret && gpu_temperature / 1000 < range->sw_ctf_threshold) 127 return; 128 } 129 130 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 131 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 132 orderly_poweroff(true); 133 } 134 135 static int pp_sw_init(struct amdgpu_ip_block *ip_block) 136 { 137 struct amdgpu_device *adev = ip_block->adev; 138 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 139 int ret = 0; 140 141 ret = hwmgr_sw_init(hwmgr); 142 143 pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully"); 144 145 if (!ret) 146 INIT_DELAYED_WORK(&hwmgr->swctf_delayed_work, 147 pp_swctf_delayed_work_handler); 148 149 return ret; 150 } 151 152 static int pp_sw_fini(struct amdgpu_ip_block *ip_block) 153 { 154 struct amdgpu_device *adev = ip_block->adev; 155 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 156 157 hwmgr_sw_fini(hwmgr); 158 159 amdgpu_ucode_release(&adev->pm.fw); 160 161 return 0; 162 } 163 164 static int pp_hw_init(struct amdgpu_ip_block *ip_block) 165 { 166 int ret = 0; 167 struct amdgpu_device *adev = ip_block->adev; 168 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 169 170 ret = hwmgr_hw_init(hwmgr); 171 172 if (ret) 173 pr_err("powerplay hw init failed\n"); 174 175 return ret; 176 } 177 178 static int pp_hw_fini(struct amdgpu_ip_block *ip_block) 179 { 180 struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle; 181 182 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); 183 184 hwmgr_hw_fini(hwmgr); 185 186 return 0; 187 } 188 189 static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) 190 { 191 int r = -EINVAL; 192 void *cpu_ptr = NULL; 193 uint64_t gpu_addr; 194 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 195 196 if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size, 197 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 198 &adev->pm.smu_prv_buffer, 199 &gpu_addr, 200 &cpu_ptr)) { 201 drm_err(adev_to_drm(adev), "failed to create smu prv buffer\n"); 202 return; 203 } 204 205 if (hwmgr->hwmgr_func->notify_cac_buffer_info) 206 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, 207 lower_32_bits((unsigned long)cpu_ptr), 208 upper_32_bits((unsigned long)cpu_ptr), 209 lower_32_bits(gpu_addr), 210 upper_32_bits(gpu_addr), 211 adev->pm.smu_prv_buffer_size); 212 213 if (r) { 214 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); 215 adev->pm.smu_prv_buffer = NULL; 216 drm_err(adev_to_drm(adev), "failed to notify SMU buffer address\n"); 217 } 218 } 219 220 static int pp_late_init(struct amdgpu_ip_block *ip_block) 221 { 222 struct amdgpu_device *adev = ip_block->adev; 223 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 224 225 if (hwmgr && hwmgr->pm_en) 226 hwmgr_handle_task(hwmgr, 227 AMD_PP_TASK_COMPLETE_INIT, NULL); 228 if (adev->pm.smu_prv_buffer_size != 0) 229 pp_reserve_vram_for_smu(adev); 230 231 return 0; 232 } 233 234 static void pp_late_fini(struct amdgpu_ip_block *ip_block) 235 { 236 struct amdgpu_device *adev = ip_block->adev; 237 238 if (adev->pm.smu_prv_buffer) 239 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); 240 amd_powerplay_destroy(adev); 241 } 242 243 244 static bool pp_is_idle(struct amdgpu_ip_block *ip_block) 245 { 246 return false; 247 } 248 249 static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block, 250 enum amd_powergating_state state) 251 { 252 return 0; 253 } 254 255 static int pp_suspend(struct amdgpu_ip_block *ip_block) 256 { 257 struct amdgpu_device *adev = ip_block->adev; 258 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 259 260 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); 261 262 return hwmgr_suspend(hwmgr); 263 } 264 265 static int pp_resume(struct amdgpu_ip_block *ip_block) 266 { 267 struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle; 268 269 return hwmgr_resume(hwmgr); 270 } 271 272 static int pp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 273 enum amd_clockgating_state state) 274 { 275 return 0; 276 } 277 278 static const struct amd_ip_funcs pp_ip_funcs = { 279 .name = "powerplay", 280 .early_init = pp_early_init, 281 .late_init = pp_late_init, 282 .sw_init = pp_sw_init, 283 .sw_fini = pp_sw_fini, 284 .hw_init = pp_hw_init, 285 .hw_fini = pp_hw_fini, 286 .late_fini = pp_late_fini, 287 .suspend = pp_suspend, 288 .resume = pp_resume, 289 .is_idle = pp_is_idle, 290 .set_clockgating_state = pp_set_clockgating_state, 291 .set_powergating_state = pp_set_powergating_state, 292 }; 293 294 const struct amdgpu_ip_block_version pp_smu_ip_block = 295 { 296 .type = AMD_IP_BLOCK_TYPE_SMC, 297 .major = 1, 298 .minor = 0, 299 .rev = 0, 300 .funcs = &pp_ip_funcs, 301 }; 302 303 /* This interface only be supported On Vi, 304 * because only smu7/8 can help to load gfx/sdma fw, 305 * smu need to be enabled before load other ip's fw. 306 * so call start smu to load smu7 fw and other ip's fw 307 */ 308 static int pp_dpm_load_fw(void *handle) 309 { 310 struct pp_hwmgr *hwmgr = handle; 311 312 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu) 313 return -EINVAL; 314 315 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { 316 pr_err("fw load failed\n"); 317 return -EINVAL; 318 } 319 320 return 0; 321 } 322 323 static int pp_dpm_fw_loading_complete(void *handle) 324 { 325 return 0; 326 } 327 328 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) 329 { 330 struct pp_hwmgr *hwmgr = handle; 331 332 if (!hwmgr || !hwmgr->pm_en) 333 return -EINVAL; 334 335 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { 336 pr_info_ratelimited("%s was not implemented.\n", __func__); 337 return 0; 338 } 339 340 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); 341 } 342 343 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, 344 enum amd_dpm_forced_level *level) 345 { 346 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 347 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 348 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 349 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 350 351 if (!(hwmgr->dpm_level & profile_mode_mask)) { 352 /* enter umd pstate, save current level, disable gfx cg*/ 353 if (*level & profile_mode_mask) { 354 hwmgr->saved_dpm_level = hwmgr->dpm_level; 355 hwmgr->en_umd_pstate = true; 356 } 357 } else { 358 /* exit umd pstate, restore level, enable gfx cg*/ 359 if (!(*level & profile_mode_mask)) { 360 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 361 *level = hwmgr->saved_dpm_level; 362 hwmgr->en_umd_pstate = false; 363 } 364 } 365 } 366 367 static int pp_dpm_force_performance_level(void *handle, 368 enum amd_dpm_forced_level level) 369 { 370 struct pp_hwmgr *hwmgr = handle; 371 372 if (!hwmgr || !hwmgr->pm_en) 373 return -EINVAL; 374 375 if (level == hwmgr->dpm_level) 376 return 0; 377 378 pp_dpm_en_umd_pstate(hwmgr, &level); 379 hwmgr->request_dpm_level = level; 380 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 381 382 return 0; 383 } 384 385 static enum amd_dpm_forced_level pp_dpm_get_performance_level( 386 void *handle) 387 { 388 struct pp_hwmgr *hwmgr = handle; 389 390 if (!hwmgr || !hwmgr->pm_en) 391 return -EINVAL; 392 393 return hwmgr->dpm_level; 394 } 395 396 static uint32_t pp_dpm_get_sclk(void *handle, bool low) 397 { 398 struct pp_hwmgr *hwmgr = handle; 399 400 if (!hwmgr || !hwmgr->pm_en) 401 return 0; 402 403 if (hwmgr->hwmgr_func->get_sclk == NULL) { 404 pr_info_ratelimited("%s was not implemented.\n", __func__); 405 return 0; 406 } 407 return hwmgr->hwmgr_func->get_sclk(hwmgr, low); 408 } 409 410 static uint32_t pp_dpm_get_mclk(void *handle, bool low) 411 { 412 struct pp_hwmgr *hwmgr = handle; 413 414 if (!hwmgr || !hwmgr->pm_en) 415 return 0; 416 417 if (hwmgr->hwmgr_func->get_mclk == NULL) { 418 pr_info_ratelimited("%s was not implemented.\n", __func__); 419 return 0; 420 } 421 return hwmgr->hwmgr_func->get_mclk(hwmgr, low); 422 } 423 424 static void pp_dpm_powergate_vce(void *handle, bool gate) 425 { 426 struct pp_hwmgr *hwmgr = handle; 427 428 if (!hwmgr || !hwmgr->pm_en) 429 return; 430 431 if (hwmgr->hwmgr_func->powergate_vce == NULL) { 432 pr_info_ratelimited("%s was not implemented.\n", __func__); 433 return; 434 } 435 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); 436 } 437 438 static void pp_dpm_powergate_uvd(void *handle, bool gate) 439 { 440 struct pp_hwmgr *hwmgr = handle; 441 442 if (!hwmgr || !hwmgr->pm_en) 443 return; 444 445 if (hwmgr->hwmgr_func->powergate_uvd == NULL) { 446 pr_info_ratelimited("%s was not implemented.\n", __func__); 447 return; 448 } 449 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); 450 } 451 452 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, 453 enum amd_pm_state_type *user_state) 454 { 455 struct pp_hwmgr *hwmgr = handle; 456 457 if (!hwmgr || !hwmgr->pm_en) 458 return -EINVAL; 459 460 return hwmgr_handle_task(hwmgr, task_id, user_state); 461 } 462 463 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) 464 { 465 struct pp_hwmgr *hwmgr = handle; 466 struct pp_power_state *state; 467 enum amd_pm_state_type pm_type; 468 469 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps) 470 return -EINVAL; 471 472 state = hwmgr->current_ps; 473 474 switch (state->classification.ui_label) { 475 case PP_StateUILabel_Battery: 476 pm_type = POWER_STATE_TYPE_BATTERY; 477 break; 478 case PP_StateUILabel_Balanced: 479 pm_type = POWER_STATE_TYPE_BALANCED; 480 break; 481 case PP_StateUILabel_Performance: 482 pm_type = POWER_STATE_TYPE_PERFORMANCE; 483 break; 484 default: 485 if (state->classification.flags & PP_StateClassificationFlag_Boot) 486 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 487 else 488 pm_type = POWER_STATE_TYPE_DEFAULT; 489 break; 490 } 491 492 return pm_type; 493 } 494 495 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) 496 { 497 struct pp_hwmgr *hwmgr = handle; 498 499 if (!hwmgr || !hwmgr->pm_en) 500 return -EOPNOTSUPP; 501 502 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) 503 return -EOPNOTSUPP; 504 505 if (mode == U32_MAX) 506 return -EINVAL; 507 508 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); 509 510 return 0; 511 } 512 513 static int pp_dpm_get_fan_control_mode(void *handle, uint32_t *fan_mode) 514 { 515 struct pp_hwmgr *hwmgr = handle; 516 517 if (!hwmgr || !hwmgr->pm_en) 518 return -EOPNOTSUPP; 519 520 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) 521 return -EOPNOTSUPP; 522 523 if (!fan_mode) 524 return -EINVAL; 525 526 *fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); 527 return 0; 528 } 529 530 static int pp_dpm_set_fan_speed_pwm(void *handle, uint32_t speed) 531 { 532 struct pp_hwmgr *hwmgr = handle; 533 534 if (!hwmgr || !hwmgr->pm_en) 535 return -EOPNOTSUPP; 536 537 if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL) 538 return -EOPNOTSUPP; 539 540 if (speed == U32_MAX) 541 return -EINVAL; 542 543 return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed); 544 } 545 546 static int pp_dpm_get_fan_speed_pwm(void *handle, uint32_t *speed) 547 { 548 struct pp_hwmgr *hwmgr = handle; 549 550 if (!hwmgr || !hwmgr->pm_en) 551 return -EOPNOTSUPP; 552 553 if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL) 554 return -EOPNOTSUPP; 555 556 if (!speed) 557 return -EINVAL; 558 559 return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed); 560 } 561 562 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) 563 { 564 struct pp_hwmgr *hwmgr = handle; 565 566 if (!hwmgr || !hwmgr->pm_en) 567 return -EOPNOTSUPP; 568 569 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) 570 return -EOPNOTSUPP; 571 572 if (!rpm) 573 return -EINVAL; 574 575 return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); 576 } 577 578 static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm) 579 { 580 struct pp_hwmgr *hwmgr = handle; 581 582 if (!hwmgr || !hwmgr->pm_en) 583 return -EOPNOTSUPP; 584 585 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) 586 return -EOPNOTSUPP; 587 588 if (rpm == U32_MAX) 589 return -EINVAL; 590 591 return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm); 592 } 593 594 static int pp_dpm_get_pp_num_states(void *handle, 595 struct pp_states_info *data) 596 { 597 struct pp_hwmgr *hwmgr = handle; 598 int i; 599 600 memset(data, 0, sizeof(*data)); 601 602 if (!hwmgr || !hwmgr->pm_en || !hwmgr->ps) 603 return -EINVAL; 604 605 data->nums = hwmgr->num_ps; 606 607 for (i = 0; i < hwmgr->num_ps; i++) { 608 struct pp_power_state *state = (struct pp_power_state *) 609 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); 610 switch (state->classification.ui_label) { 611 case PP_StateUILabel_Battery: 612 data->states[i] = POWER_STATE_TYPE_BATTERY; 613 break; 614 case PP_StateUILabel_Balanced: 615 data->states[i] = POWER_STATE_TYPE_BALANCED; 616 break; 617 case PP_StateUILabel_Performance: 618 data->states[i] = POWER_STATE_TYPE_PERFORMANCE; 619 break; 620 default: 621 if (state->classification.flags & PP_StateClassificationFlag_Boot) 622 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT; 623 else 624 data->states[i] = POWER_STATE_TYPE_DEFAULT; 625 } 626 } 627 return 0; 628 } 629 630 static int pp_dpm_get_pp_table(void *handle, char **table) 631 { 632 struct pp_hwmgr *hwmgr = handle; 633 634 if (!hwmgr || !hwmgr->pm_en || !table) 635 return -EINVAL; 636 637 if (!hwmgr->soft_pp_table) 638 return -EOPNOTSUPP; 639 640 *table = (char *)hwmgr->soft_pp_table; 641 return hwmgr->soft_pp_table_size; 642 } 643 644 static int amd_powerplay_reset(void *handle) 645 { 646 struct pp_hwmgr *hwmgr = handle; 647 int ret; 648 649 ret = hwmgr_hw_fini(hwmgr); 650 if (ret) 651 return ret; 652 653 ret = hwmgr_hw_init(hwmgr); 654 if (ret) 655 return ret; 656 657 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL); 658 } 659 660 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) 661 { 662 struct pp_hwmgr *hwmgr = handle; 663 void *hardcode_pp_table; 664 int ret = -ENOMEM; 665 666 if (!hwmgr || !hwmgr->pm_en || !buf || !size || size > U32_MAX) 667 return -EINVAL; 668 669 hardcode_pp_table = kmemdup(buf, size, GFP_KERNEL); 670 if (!hardcode_pp_table) 671 return ret; 672 673 kfree(hwmgr->hardcode_pp_table); 674 hwmgr->hardcode_pp_table = hardcode_pp_table; 675 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table; 676 hwmgr->soft_pp_table_size = size; 677 678 ret = amd_powerplay_reset(handle); 679 if (ret) 680 return ret; 681 682 if (hwmgr->hwmgr_func->avfs_control) 683 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false); 684 685 return ret; 686 } 687 688 static int pp_dpm_force_clock_level(void *handle, 689 enum pp_clock_type type, uint32_t mask) 690 { 691 struct pp_hwmgr *hwmgr = handle; 692 693 if (!hwmgr || !hwmgr->pm_en) 694 return -EINVAL; 695 696 if (hwmgr->hwmgr_func->force_clock_level == NULL) { 697 pr_info_ratelimited("%s was not implemented.\n", __func__); 698 return 0; 699 } 700 701 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 702 pr_debug("force clock level is for dpm manual mode only.\n"); 703 return -EINVAL; 704 } 705 706 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); 707 } 708 709 static int pp_dpm_emit_clock_levels(void *handle, 710 enum pp_clock_type type, 711 char *buf, 712 int *offset) 713 { 714 struct pp_hwmgr *hwmgr = handle; 715 716 if (!hwmgr || !hwmgr->pm_en) 717 return -EOPNOTSUPP; 718 719 if (!hwmgr->hwmgr_func->emit_clock_levels) 720 return -ENOENT; 721 722 return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset); 723 } 724 725 static int pp_dpm_get_sclk_od(void *handle) 726 { 727 struct pp_hwmgr *hwmgr = handle; 728 729 if (!hwmgr || !hwmgr->pm_en) 730 return -EINVAL; 731 732 if (hwmgr->hwmgr_func->get_sclk_od == NULL) { 733 pr_info_ratelimited("%s was not implemented.\n", __func__); 734 return 0; 735 } 736 return hwmgr->hwmgr_func->get_sclk_od(hwmgr); 737 } 738 739 static int pp_dpm_set_sclk_od(void *handle, uint32_t value) 740 { 741 struct pp_hwmgr *hwmgr = handle; 742 743 if (!hwmgr || !hwmgr->pm_en) 744 return -EINVAL; 745 746 if (hwmgr->hwmgr_func->set_sclk_od == NULL) { 747 pr_info_ratelimited("%s was not implemented.\n", __func__); 748 return 0; 749 } 750 751 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value); 752 } 753 754 static int pp_dpm_get_mclk_od(void *handle) 755 { 756 struct pp_hwmgr *hwmgr = handle; 757 758 if (!hwmgr || !hwmgr->pm_en) 759 return -EINVAL; 760 761 if (hwmgr->hwmgr_func->get_mclk_od == NULL) { 762 pr_info_ratelimited("%s was not implemented.\n", __func__); 763 return 0; 764 } 765 return hwmgr->hwmgr_func->get_mclk_od(hwmgr); 766 } 767 768 static int pp_dpm_set_mclk_od(void *handle, uint32_t value) 769 { 770 struct pp_hwmgr *hwmgr = handle; 771 772 if (!hwmgr || !hwmgr->pm_en) 773 return -EINVAL; 774 775 if (hwmgr->hwmgr_func->set_mclk_od == NULL) { 776 pr_info_ratelimited("%s was not implemented.\n", __func__); 777 return 0; 778 } 779 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); 780 } 781 782 static int pp_dpm_read_sensor(void *handle, int idx, 783 void *value, int *size) 784 { 785 struct pp_hwmgr *hwmgr = handle; 786 787 if (!hwmgr || !hwmgr->pm_en || !value) 788 return -EINVAL; 789 790 switch (idx) { 791 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 792 *((uint32_t *)value) = hwmgr->pstate_sclk * 100; 793 return 0; 794 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 795 *((uint32_t *)value) = hwmgr->pstate_mclk * 100; 796 return 0; 797 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 798 *((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100; 799 return 0; 800 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 801 *((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100; 802 return 0; 803 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 804 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM; 805 return 0; 806 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 807 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM; 808 return 0; 809 default: 810 return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size); 811 } 812 } 813 814 static struct amd_vce_state* 815 pp_dpm_get_vce_clock_state(void *handle, unsigned idx) 816 { 817 struct pp_hwmgr *hwmgr = handle; 818 819 if (!hwmgr || !hwmgr->pm_en) 820 return NULL; 821 822 if (idx < hwmgr->num_vce_state_tables) 823 return &hwmgr->vce_states[idx]; 824 return NULL; 825 } 826 827 static int pp_get_power_profile_mode(void *handle, char *buf) 828 { 829 struct pp_hwmgr *hwmgr = handle; 830 831 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode) 832 return -EOPNOTSUPP; 833 if (!buf) 834 return -EINVAL; 835 836 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf); 837 } 838 839 static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size) 840 { 841 struct pp_hwmgr *hwmgr = handle; 842 843 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode) 844 return -EOPNOTSUPP; 845 846 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 847 pr_debug("power profile setting is for manual dpm mode only.\n"); 848 return -EINVAL; 849 } 850 851 return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); 852 } 853 854 static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size) 855 { 856 struct pp_hwmgr *hwmgr = handle; 857 858 if (!hwmgr || !hwmgr->pm_en) 859 return -EINVAL; 860 861 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL) 862 return 0; 863 864 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size); 865 } 866 867 static int pp_odn_edit_dpm_table(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 868 long *input, uint32_t size) 869 { 870 struct pp_hwmgr *hwmgr = handle; 871 872 if (!hwmgr || !hwmgr->pm_en) 873 return -EINVAL; 874 875 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { 876 pr_info_ratelimited("%s was not implemented.\n", __func__); 877 return 0; 878 } 879 880 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size); 881 } 882 883 static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state) 884 { 885 struct pp_hwmgr *hwmgr = handle; 886 887 if (!hwmgr) 888 return -EINVAL; 889 890 if (!hwmgr->pm_en) 891 return 0; 892 893 if (hwmgr->hwmgr_func->set_mp1_state) 894 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state); 895 896 return 0; 897 } 898 899 static int pp_dpm_switch_power_profile(void *handle, 900 enum PP_SMC_POWER_PROFILE type, bool en) 901 { 902 struct pp_hwmgr *hwmgr = handle; 903 long workload[1]; 904 uint32_t index; 905 906 if (!hwmgr || !hwmgr->pm_en) 907 return -EINVAL; 908 909 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { 910 pr_info_ratelimited("%s was not implemented.\n", __func__); 911 return -EINVAL; 912 } 913 914 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 915 return -EINVAL; 916 917 if (!en) { 918 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]); 919 index = fls(hwmgr->workload_mask); 920 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0; 921 workload[0] = hwmgr->workload_setting[index]; 922 } else { 923 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]); 924 index = fls(hwmgr->workload_mask); 925 index = index <= Workload_Policy_Max ? index - 1 : 0; 926 workload[0] = hwmgr->workload_setting[index]; 927 } 928 929 if (type == PP_SMC_POWER_PROFILE_COMPUTE && 930 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) { 931 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) 932 return -EINVAL; 933 } 934 935 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 936 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0); 937 938 return 0; 939 } 940 941 static int pp_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 942 { 943 struct pp_hwmgr *hwmgr = handle; 944 uint32_t max_power_limit; 945 946 if (!hwmgr || !hwmgr->pm_en) 947 return -EINVAL; 948 949 if (hwmgr->hwmgr_func->set_power_limit == NULL) { 950 pr_info_ratelimited("%s was not implemented.\n", __func__); 951 return -EINVAL; 952 } 953 954 if (limit == 0) 955 limit = hwmgr->default_power_limit; 956 957 max_power_limit = hwmgr->default_power_limit; 958 if (hwmgr->od_enabled) { 959 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); 960 max_power_limit /= 100; 961 } 962 963 if (limit > max_power_limit) 964 return -EINVAL; 965 966 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit); 967 hwmgr->power_limit = limit; 968 return 0; 969 } 970 971 static int pp_get_power_limit(void *handle, uint32_t *limit, 972 enum pp_power_limit_level pp_limit_level, 973 enum pp_power_type power_type) 974 { 975 struct pp_hwmgr *hwmgr = handle; 976 int ret = 0; 977 978 if (!hwmgr || !hwmgr->pm_en || !limit) 979 return -EINVAL; 980 981 if (power_type != PP_PWR_TYPE_SUSTAINED) 982 return -EOPNOTSUPP; 983 984 switch (pp_limit_level) { 985 case PP_PWR_LIMIT_CURRENT: 986 *limit = hwmgr->power_limit; 987 break; 988 case PP_PWR_LIMIT_DEFAULT: 989 *limit = hwmgr->default_power_limit; 990 break; 991 case PP_PWR_LIMIT_MAX: 992 *limit = hwmgr->default_power_limit; 993 if (hwmgr->od_enabled) { 994 *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); 995 *limit /= 100; 996 } 997 break; 998 case PP_PWR_LIMIT_MIN: 999 *limit = 0; 1000 break; 1001 default: 1002 ret = -EOPNOTSUPP; 1003 break; 1004 } 1005 1006 return ret; 1007 } 1008 1009 static int pp_display_configuration_change(void *handle, 1010 const struct amd_pp_display_configuration *display_config) 1011 { 1012 struct pp_hwmgr *hwmgr = handle; 1013 1014 if (!hwmgr || !hwmgr->pm_en) 1015 return -EINVAL; 1016 1017 phm_store_dal_configuration_data(hwmgr, display_config); 1018 return 0; 1019 } 1020 1021 static int pp_get_current_clocks(void *handle, 1022 struct amd_pp_clock_info *clocks) 1023 { 1024 struct pp_clock_info hw_clocks; 1025 struct pp_hwmgr *hwmgr = handle; 1026 int ret = 0; 1027 1028 if (!hwmgr || !hwmgr->pm_en) 1029 return -EINVAL; 1030 1031 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1032 PHM_PlatformCaps_PowerContainment)) 1033 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, 1034 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment); 1035 else 1036 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, 1037 &hw_clocks, PHM_PerformanceLevelDesignation_Activity); 1038 1039 if (ret) { 1040 drm_err(adev_to_drm(hwmgr->adev), 1041 "Error in phm_get_clock_info\n"); 1042 return -EINVAL; 1043 } 1044 1045 clocks->min_engine_clock = hw_clocks.min_eng_clk; 1046 clocks->max_engine_clock = hw_clocks.max_eng_clk; 1047 clocks->min_memory_clock = hw_clocks.min_mem_clk; 1048 clocks->max_memory_clock = hw_clocks.max_mem_clk; 1049 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; 1050 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; 1051 1052 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1053 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1054 1055 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { 1056 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1057 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1058 } 1059 return 0; 1060 } 1061 1062 static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) 1063 { 1064 struct pp_hwmgr *hwmgr = handle; 1065 1066 if (!hwmgr || !hwmgr->pm_en) 1067 return -EINVAL; 1068 1069 if (clocks == NULL) 1070 return -EINVAL; 1071 1072 return phm_get_clock_by_type(hwmgr, type, clocks); 1073 } 1074 1075 static int pp_get_clock_by_type_with_latency(void *handle, 1076 enum amd_pp_clock_type type, 1077 struct pp_clock_levels_with_latency *clocks) 1078 { 1079 struct pp_hwmgr *hwmgr = handle; 1080 1081 if (!hwmgr || !hwmgr->pm_en || !clocks) 1082 return -EINVAL; 1083 1084 return phm_get_clock_by_type_with_latency(hwmgr, type, clocks); 1085 } 1086 1087 static int pp_get_clock_by_type_with_voltage(void *handle, 1088 enum amd_pp_clock_type type, 1089 struct pp_clock_levels_with_voltage *clocks) 1090 { 1091 struct pp_hwmgr *hwmgr = handle; 1092 1093 if (!hwmgr || !hwmgr->pm_en || !clocks) 1094 return -EINVAL; 1095 1096 return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks); 1097 } 1098 1099 static int pp_set_watermarks_for_clocks_ranges(void *handle, 1100 void *clock_ranges) 1101 { 1102 struct pp_hwmgr *hwmgr = handle; 1103 1104 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) 1105 return -EINVAL; 1106 1107 return phm_set_watermarks_for_clocks_ranges(hwmgr, 1108 clock_ranges); 1109 } 1110 1111 static int pp_display_clock_voltage_request(void *handle, 1112 struct pp_display_clock_request *clock) 1113 { 1114 struct pp_hwmgr *hwmgr = handle; 1115 1116 if (!hwmgr || !hwmgr->pm_en || !clock) 1117 return -EINVAL; 1118 1119 return phm_display_clock_voltage_request(hwmgr, clock); 1120 } 1121 1122 static int pp_get_display_mode_validation_clocks(void *handle, 1123 struct amd_pp_simple_clock_info *clocks) 1124 { 1125 struct pp_hwmgr *hwmgr = handle; 1126 int ret = 0; 1127 1128 if (!hwmgr || !hwmgr->pm_en || !clocks) 1129 return -EINVAL; 1130 1131 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) 1132 ret = phm_get_max_high_clocks(hwmgr, clocks); 1133 1134 return ret; 1135 } 1136 1137 static int pp_dpm_powergate_mmhub(void *handle) 1138 { 1139 struct pp_hwmgr *hwmgr = handle; 1140 1141 if (!hwmgr || !hwmgr->pm_en) 1142 return -EINVAL; 1143 1144 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) { 1145 pr_info_ratelimited("%s was not implemented.\n", __func__); 1146 return 0; 1147 } 1148 1149 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr); 1150 } 1151 1152 static int pp_dpm_powergate_gfx(void *handle, bool gate) 1153 { 1154 struct pp_hwmgr *hwmgr = handle; 1155 1156 if (!hwmgr || !hwmgr->pm_en) 1157 return 0; 1158 1159 if (hwmgr->hwmgr_func->powergate_gfx == NULL) { 1160 pr_info_ratelimited("%s was not implemented.\n", __func__); 1161 return 0; 1162 } 1163 1164 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); 1165 } 1166 1167 static void pp_dpm_powergate_acp(void *handle, bool gate) 1168 { 1169 struct pp_hwmgr *hwmgr = handle; 1170 1171 if (!hwmgr || !hwmgr->pm_en) 1172 return; 1173 1174 if (hwmgr->hwmgr_func->powergate_acp == NULL) { 1175 pr_info_ratelimited("%s was not implemented.\n", __func__); 1176 return; 1177 } 1178 1179 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate); 1180 } 1181 1182 static void pp_dpm_powergate_sdma(void *handle, bool gate) 1183 { 1184 struct pp_hwmgr *hwmgr = handle; 1185 1186 if (!hwmgr) 1187 return; 1188 1189 if (hwmgr->hwmgr_func->powergate_sdma == NULL) { 1190 pr_info_ratelimited("%s was not implemented.\n", __func__); 1191 return; 1192 } 1193 1194 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate); 1195 } 1196 1197 static int pp_set_powergating_by_smu(void *handle, 1198 uint32_t block_type, 1199 bool gate, 1200 int inst) 1201 { 1202 int ret = 0; 1203 1204 switch (block_type) { 1205 case AMD_IP_BLOCK_TYPE_UVD: 1206 case AMD_IP_BLOCK_TYPE_VCN: 1207 pp_dpm_powergate_uvd(handle, gate); 1208 break; 1209 case AMD_IP_BLOCK_TYPE_VCE: 1210 pp_dpm_powergate_vce(handle, gate); 1211 break; 1212 case AMD_IP_BLOCK_TYPE_GMC: 1213 /* 1214 * For now, this is only used on PICASSO. 1215 * And only "gate" operation is supported. 1216 */ 1217 if (gate) 1218 pp_dpm_powergate_mmhub(handle); 1219 break; 1220 case AMD_IP_BLOCK_TYPE_GFX: 1221 ret = pp_dpm_powergate_gfx(handle, gate); 1222 break; 1223 case AMD_IP_BLOCK_TYPE_ACP: 1224 pp_dpm_powergate_acp(handle, gate); 1225 break; 1226 case AMD_IP_BLOCK_TYPE_SDMA: 1227 pp_dpm_powergate_sdma(handle, gate); 1228 break; 1229 default: 1230 break; 1231 } 1232 return ret; 1233 } 1234 1235 static int pp_notify_smu_enable_pwe(void *handle) 1236 { 1237 struct pp_hwmgr *hwmgr = handle; 1238 1239 if (!hwmgr || !hwmgr->pm_en) 1240 return -EINVAL; 1241 1242 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) { 1243 pr_info_ratelimited("%s was not implemented.\n", __func__); 1244 return -EINVAL; 1245 } 1246 1247 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr); 1248 1249 return 0; 1250 } 1251 1252 static int pp_enable_mgpu_fan_boost(void *handle) 1253 { 1254 struct pp_hwmgr *hwmgr = handle; 1255 1256 if (!hwmgr) 1257 return -EINVAL; 1258 1259 if (!hwmgr->pm_en || 1260 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL) 1261 return 0; 1262 1263 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr); 1264 1265 return 0; 1266 } 1267 1268 static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock) 1269 { 1270 struct pp_hwmgr *hwmgr = handle; 1271 1272 if (!hwmgr || !hwmgr->pm_en) 1273 return -EINVAL; 1274 1275 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) { 1276 pr_debug("%s was not implemented.\n", __func__); 1277 return -EINVAL; 1278 } 1279 1280 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock); 1281 1282 return 0; 1283 } 1284 1285 static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock) 1286 { 1287 struct pp_hwmgr *hwmgr = handle; 1288 1289 if (!hwmgr || !hwmgr->pm_en) 1290 return -EINVAL; 1291 1292 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) { 1293 pr_debug("%s was not implemented.\n", __func__); 1294 return -EINVAL; 1295 } 1296 1297 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock); 1298 1299 return 0; 1300 } 1301 1302 static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock) 1303 { 1304 struct pp_hwmgr *hwmgr = handle; 1305 1306 if (!hwmgr || !hwmgr->pm_en) 1307 return -EINVAL; 1308 1309 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) { 1310 pr_debug("%s was not implemented.\n", __func__); 1311 return -EINVAL; 1312 } 1313 1314 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); 1315 1316 return 0; 1317 } 1318 1319 static int pp_set_active_display_count(void *handle, uint32_t count) 1320 { 1321 struct pp_hwmgr *hwmgr = handle; 1322 1323 if (!hwmgr || !hwmgr->pm_en) 1324 return -EINVAL; 1325 1326 return phm_set_active_display_count(hwmgr, count); 1327 } 1328 1329 static int pp_get_asic_baco_capability(void *handle) 1330 { 1331 struct pp_hwmgr *hwmgr = handle; 1332 1333 if (!hwmgr) 1334 return false; 1335 1336 if (!(hwmgr->not_vf && amdgpu_dpm) || 1337 !hwmgr->hwmgr_func->get_bamaco_support) 1338 return false; 1339 1340 return hwmgr->hwmgr_func->get_bamaco_support(hwmgr); 1341 } 1342 1343 static int pp_get_asic_baco_state(void *handle, int *state) 1344 { 1345 struct pp_hwmgr *hwmgr = handle; 1346 1347 if (!hwmgr) 1348 return -EINVAL; 1349 1350 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state) 1351 return 0; 1352 1353 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state); 1354 1355 return 0; 1356 } 1357 1358 static int pp_set_asic_baco_state(void *handle, int state) 1359 { 1360 struct pp_hwmgr *hwmgr = handle; 1361 1362 if (!hwmgr) 1363 return -EINVAL; 1364 1365 if (!(hwmgr->not_vf && amdgpu_dpm) || 1366 !hwmgr->hwmgr_func->set_asic_baco_state) 1367 return 0; 1368 1369 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state); 1370 1371 return 0; 1372 } 1373 1374 static int pp_get_ppfeature_status(void *handle, char *buf) 1375 { 1376 struct pp_hwmgr *hwmgr = handle; 1377 1378 if (!hwmgr || !hwmgr->pm_en || !buf) 1379 return -EINVAL; 1380 1381 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) { 1382 pr_info_ratelimited("%s was not implemented.\n", __func__); 1383 return -EINVAL; 1384 } 1385 1386 return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf); 1387 } 1388 1389 static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks) 1390 { 1391 struct pp_hwmgr *hwmgr = handle; 1392 1393 if (!hwmgr || !hwmgr->pm_en) 1394 return -EINVAL; 1395 1396 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) { 1397 pr_info_ratelimited("%s was not implemented.\n", __func__); 1398 return -EINVAL; 1399 } 1400 1401 return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks); 1402 } 1403 1404 static int pp_asic_reset_mode_2(void *handle) 1405 { 1406 struct pp_hwmgr *hwmgr = handle; 1407 1408 if (!hwmgr || !hwmgr->pm_en) 1409 return -EINVAL; 1410 1411 if (hwmgr->hwmgr_func->asic_reset == NULL) { 1412 pr_info_ratelimited("%s was not implemented.\n", __func__); 1413 return -EINVAL; 1414 } 1415 1416 return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2); 1417 } 1418 1419 static int pp_smu_i2c_bus_access(void *handle, bool acquire) 1420 { 1421 struct pp_hwmgr *hwmgr = handle; 1422 1423 if (!hwmgr || !hwmgr->pm_en) 1424 return -EINVAL; 1425 1426 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) { 1427 pr_info_ratelimited("%s was not implemented.\n", __func__); 1428 return -EINVAL; 1429 } 1430 1431 return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire); 1432 } 1433 1434 static int pp_set_df_cstate(void *handle, enum pp_df_cstate state) 1435 { 1436 struct pp_hwmgr *hwmgr = handle; 1437 1438 if (!hwmgr) 1439 return -EINVAL; 1440 1441 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate) 1442 return 0; 1443 1444 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state); 1445 1446 return 0; 1447 } 1448 1449 static int pp_set_xgmi_pstate(void *handle, uint32_t pstate) 1450 { 1451 struct pp_hwmgr *hwmgr = handle; 1452 1453 if (!hwmgr) 1454 return -EINVAL; 1455 1456 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate) 1457 return 0; 1458 1459 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate); 1460 1461 return 0; 1462 } 1463 1464 static ssize_t pp_get_gpu_metrics(void *handle, void **table) 1465 { 1466 struct pp_hwmgr *hwmgr = handle; 1467 1468 if (!hwmgr) 1469 return -EINVAL; 1470 1471 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics) 1472 return -EOPNOTSUPP; 1473 1474 return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table); 1475 } 1476 1477 static int pp_gfx_state_change_set(void *handle, uint32_t state) 1478 { 1479 struct pp_hwmgr *hwmgr = handle; 1480 1481 if (!hwmgr || !hwmgr->pm_en) 1482 return -EINVAL; 1483 1484 if (hwmgr->hwmgr_func->gfx_state_change == NULL) { 1485 pr_info_ratelimited("%s was not implemented.\n", __func__); 1486 return -EINVAL; 1487 } 1488 1489 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state); 1490 return 0; 1491 } 1492 1493 static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size) 1494 { 1495 struct pp_hwmgr *hwmgr = handle; 1496 struct amdgpu_device *adev = hwmgr->adev; 1497 int err; 1498 1499 if (!addr || !size) 1500 return -EINVAL; 1501 1502 *addr = NULL; 1503 *size = 0; 1504 if (adev->pm.smu_prv_buffer) { 1505 err = amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr); 1506 if (err) 1507 return err; 1508 *size = adev->pm.smu_prv_buffer_size; 1509 } 1510 1511 return 0; 1512 } 1513 1514 static void pp_pm_compute_clocks(void *handle) 1515 { 1516 struct pp_hwmgr *hwmgr = handle; 1517 struct amdgpu_device *adev = hwmgr->adev; 1518 1519 if (!adev->dc_enabled) { 1520 amdgpu_dpm_get_display_cfg(adev); 1521 pp_display_configuration_change(handle, 1522 &adev->pm.pm_display_cfg); 1523 } 1524 1525 pp_dpm_dispatch_tasks(handle, 1526 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 1527 NULL); 1528 } 1529 1530 static void pp_dpm_notify_ac_dc(void *handle) 1531 { 1532 struct pp_hwmgr *hwmgr = handle; 1533 1534 if (!hwmgr || !hwmgr->pm_en) 1535 return; 1536 1537 if (hwmgr->hwmgr_func->notify_ac_dc) 1538 hwmgr->hwmgr_func->notify_ac_dc(hwmgr); 1539 } 1540 1541 static const struct amd_pm_funcs pp_dpm_funcs = { 1542 .load_firmware = pp_dpm_load_fw, 1543 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, 1544 .force_performance_level = pp_dpm_force_performance_level, 1545 .get_performance_level = pp_dpm_get_performance_level, 1546 .get_current_power_state = pp_dpm_get_current_power_state, 1547 .dispatch_tasks = pp_dpm_dispatch_tasks, 1548 .set_fan_control_mode = pp_dpm_set_fan_control_mode, 1549 .get_fan_control_mode = pp_dpm_get_fan_control_mode, 1550 .set_fan_speed_pwm = pp_dpm_set_fan_speed_pwm, 1551 .get_fan_speed_pwm = pp_dpm_get_fan_speed_pwm, 1552 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, 1553 .set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm, 1554 .get_pp_num_states = pp_dpm_get_pp_num_states, 1555 .get_pp_table = pp_dpm_get_pp_table, 1556 .set_pp_table = pp_dpm_set_pp_table, 1557 .force_clock_level = pp_dpm_force_clock_level, 1558 .emit_clock_levels = pp_dpm_emit_clock_levels, 1559 .get_sclk_od = pp_dpm_get_sclk_od, 1560 .set_sclk_od = pp_dpm_set_sclk_od, 1561 .get_mclk_od = pp_dpm_get_mclk_od, 1562 .set_mclk_od = pp_dpm_set_mclk_od, 1563 .read_sensor = pp_dpm_read_sensor, 1564 .get_vce_clock_state = pp_dpm_get_vce_clock_state, 1565 .switch_power_profile = pp_dpm_switch_power_profile, 1566 .set_clockgating_by_smu = pp_set_clockgating_by_smu, 1567 .set_powergating_by_smu = pp_set_powergating_by_smu, 1568 .get_power_profile_mode = pp_get_power_profile_mode, 1569 .set_power_profile_mode = pp_set_power_profile_mode, 1570 .set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol, 1571 .odn_edit_dpm_table = pp_odn_edit_dpm_table, 1572 .set_mp1_state = pp_dpm_set_mp1_state, 1573 .set_power_limit = pp_set_power_limit, 1574 .get_power_limit = pp_get_power_limit, 1575 /* export to DC */ 1576 .get_sclk = pp_dpm_get_sclk, 1577 .get_mclk = pp_dpm_get_mclk, 1578 .display_configuration_change = pp_display_configuration_change, 1579 .get_current_clocks = pp_get_current_clocks, 1580 .get_clock_by_type = pp_get_clock_by_type, 1581 .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency, 1582 .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage, 1583 .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges, 1584 .display_clock_voltage_request = pp_display_clock_voltage_request, 1585 .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks, 1586 .notify_smu_enable_pwe = pp_notify_smu_enable_pwe, 1587 .enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost, 1588 .set_active_display_count = pp_set_active_display_count, 1589 .set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk, 1590 .set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq, 1591 .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq, 1592 .get_asic_baco_capability = pp_get_asic_baco_capability, 1593 .get_asic_baco_state = pp_get_asic_baco_state, 1594 .set_asic_baco_state = pp_set_asic_baco_state, 1595 .get_ppfeature_status = pp_get_ppfeature_status, 1596 .set_ppfeature_status = pp_set_ppfeature_status, 1597 .asic_reset_mode_2 = pp_asic_reset_mode_2, 1598 .smu_i2c_bus_access = pp_smu_i2c_bus_access, 1599 .set_df_cstate = pp_set_df_cstate, 1600 .set_xgmi_pstate = pp_set_xgmi_pstate, 1601 .get_gpu_metrics = pp_get_gpu_metrics, 1602 .gfx_state_change_set = pp_gfx_state_change_set, 1603 .get_smu_prv_buf_details = pp_get_prv_buffer_details, 1604 .pm_compute_clocks = pp_pm_compute_clocks, 1605 .notify_ac_dc = pp_dpm_notify_ac_dc, 1606 }; 1607