1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/types.h> 24 #include <linux/kernel.h> 25 #include <linux/gfp.h> 26 #include <linux/slab.h> 27 #include <linux/firmware.h> 28 #include <linux/reboot.h> 29 #include "amd_shared.h" 30 #include "power_state.h" 31 #include "amdgpu.h" 32 #include "hwmgr.h" 33 #include "amdgpu_dpm_internal.h" 34 35 static const struct amd_pm_funcs pp_dpm_funcs; 36 37 static int amd_powerplay_create(struct amdgpu_device *adev) 38 { 39 struct pp_hwmgr *hwmgr; 40 41 if (adev == NULL) 42 return -EINVAL; 43 44 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL); 45 if (hwmgr == NULL) 46 return -ENOMEM; 47 48 hwmgr->adev = adev; 49 hwmgr->not_vf = !amdgpu_sriov_vf(adev); 50 hwmgr->device = amdgpu_cgs_create_device(adev); 51 if (!hwmgr->device) { 52 kfree(hwmgr); 53 return -ENOMEM; 54 } 55 56 mutex_init(&hwmgr->msg_lock); 57 hwmgr->chip_family = adev->family; 58 hwmgr->chip_id = adev->asic_type; 59 hwmgr->feature_mask = adev->pm.pp_feature; 60 hwmgr->display_config = &adev->pm.pm_display_cfg; 61 adev->powerplay.pp_handle = hwmgr; 62 adev->powerplay.pp_funcs = &pp_dpm_funcs; 63 return 0; 64 } 65 66 67 static void amd_powerplay_destroy(struct amdgpu_device *adev) 68 { 69 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 70 71 mutex_destroy(&hwmgr->msg_lock); 72 73 kfree(hwmgr->hardcode_pp_table); 74 hwmgr->hardcode_pp_table = NULL; 75 76 kfree(hwmgr); 77 hwmgr = NULL; 78 } 79 80 static int pp_early_init(struct amdgpu_ip_block *ip_block) 81 { 82 int ret; 83 struct amdgpu_device *adev = ip_block->adev; 84 ret = amd_powerplay_create(adev); 85 86 if (ret != 0) 87 return ret; 88 89 ret = hwmgr_early_init(adev->powerplay.pp_handle); 90 if (ret) 91 return -EINVAL; 92 93 return 0; 94 } 95 96 static void pp_swctf_delayed_work_handler(struct work_struct *work) 97 { 98 struct pp_hwmgr *hwmgr = 99 container_of(work, struct pp_hwmgr, swctf_delayed_work.work); 100 struct amdgpu_device *adev = hwmgr->adev; 101 struct amdgpu_dpm_thermal *range = 102 &adev->pm.dpm.thermal; 103 uint32_t gpu_temperature, size = sizeof(gpu_temperature); 104 int ret; 105 106 /* 107 * If the hotspot/edge temperature is confirmed as below SW CTF setting point 108 * after the delay enforced, nothing will be done. 109 * Otherwise, a graceful shutdown will be performed to prevent further damage. 110 */ 111 if (range->sw_ctf_threshold && 112 hwmgr->hwmgr_func->read_sensor) { 113 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, 114 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 115 &gpu_temperature, 116 &size); 117 /* 118 * For some legacy ASICs, hotspot temperature retrieving might be not 119 * supported. Check the edge temperature instead then. 120 */ 121 if (ret == -EOPNOTSUPP) 122 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, 123 AMDGPU_PP_SENSOR_EDGE_TEMP, 124 &gpu_temperature, 125 &size); 126 if (!ret && gpu_temperature / 1000 < range->sw_ctf_threshold) 127 return; 128 } 129 130 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 131 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 132 orderly_poweroff(true); 133 } 134 135 static int pp_sw_init(struct amdgpu_ip_block *ip_block) 136 { 137 struct amdgpu_device *adev = ip_block->adev; 138 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 139 int ret = 0; 140 141 ret = hwmgr_sw_init(hwmgr); 142 143 pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully"); 144 145 if (!ret) 146 INIT_DELAYED_WORK(&hwmgr->swctf_delayed_work, 147 pp_swctf_delayed_work_handler); 148 149 return ret; 150 } 151 152 static int pp_sw_fini(struct amdgpu_ip_block *ip_block) 153 { 154 struct amdgpu_device *adev = ip_block->adev; 155 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 156 157 hwmgr_sw_fini(hwmgr); 158 159 amdgpu_ucode_release(&adev->pm.fw); 160 161 return 0; 162 } 163 164 static int pp_hw_init(struct amdgpu_ip_block *ip_block) 165 { 166 int ret = 0; 167 struct amdgpu_device *adev = ip_block->adev; 168 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 169 170 ret = hwmgr_hw_init(hwmgr); 171 172 if (ret) 173 pr_err("powerplay hw init failed\n"); 174 175 return ret; 176 } 177 178 static int pp_hw_fini(struct amdgpu_ip_block *ip_block) 179 { 180 struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle; 181 182 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); 183 184 hwmgr_hw_fini(hwmgr); 185 186 return 0; 187 } 188 189 static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) 190 { 191 int r = -EINVAL; 192 void *cpu_ptr = NULL; 193 uint64_t gpu_addr; 194 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 195 196 if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size, 197 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 198 &adev->pm.smu_prv_buffer, 199 &gpu_addr, 200 &cpu_ptr)) { 201 DRM_ERROR("amdgpu: failed to create smu prv buffer\n"); 202 return; 203 } 204 205 if (hwmgr->hwmgr_func->notify_cac_buffer_info) 206 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, 207 lower_32_bits((unsigned long)cpu_ptr), 208 upper_32_bits((unsigned long)cpu_ptr), 209 lower_32_bits(gpu_addr), 210 upper_32_bits(gpu_addr), 211 adev->pm.smu_prv_buffer_size); 212 213 if (r) { 214 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); 215 adev->pm.smu_prv_buffer = NULL; 216 DRM_ERROR("amdgpu: failed to notify SMU buffer address\n"); 217 } 218 } 219 220 static int pp_late_init(struct amdgpu_ip_block *ip_block) 221 { 222 struct amdgpu_device *adev = ip_block->adev; 223 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 224 225 if (hwmgr && hwmgr->pm_en) 226 hwmgr_handle_task(hwmgr, 227 AMD_PP_TASK_COMPLETE_INIT, NULL); 228 if (adev->pm.smu_prv_buffer_size != 0) 229 pp_reserve_vram_for_smu(adev); 230 231 return 0; 232 } 233 234 static void pp_late_fini(struct amdgpu_ip_block *ip_block) 235 { 236 struct amdgpu_device *adev = ip_block->adev; 237 238 if (adev->pm.smu_prv_buffer) 239 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); 240 amd_powerplay_destroy(adev); 241 } 242 243 244 static bool pp_is_idle(struct amdgpu_ip_block *ip_block) 245 { 246 return false; 247 } 248 249 static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block, 250 enum amd_powergating_state state) 251 { 252 return 0; 253 } 254 255 static int pp_suspend(struct amdgpu_ip_block *ip_block) 256 { 257 struct amdgpu_device *adev = ip_block->adev; 258 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 259 260 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); 261 262 return hwmgr_suspend(hwmgr); 263 } 264 265 static int pp_resume(struct amdgpu_ip_block *ip_block) 266 { 267 struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle; 268 269 return hwmgr_resume(hwmgr); 270 } 271 272 static int pp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 273 enum amd_clockgating_state state) 274 { 275 return 0; 276 } 277 278 static const struct amd_ip_funcs pp_ip_funcs = { 279 .name = "powerplay", 280 .early_init = pp_early_init, 281 .late_init = pp_late_init, 282 .sw_init = pp_sw_init, 283 .sw_fini = pp_sw_fini, 284 .hw_init = pp_hw_init, 285 .hw_fini = pp_hw_fini, 286 .late_fini = pp_late_fini, 287 .suspend = pp_suspend, 288 .resume = pp_resume, 289 .is_idle = pp_is_idle, 290 .set_clockgating_state = pp_set_clockgating_state, 291 .set_powergating_state = pp_set_powergating_state, 292 }; 293 294 const struct amdgpu_ip_block_version pp_smu_ip_block = 295 { 296 .type = AMD_IP_BLOCK_TYPE_SMC, 297 .major = 1, 298 .minor = 0, 299 .rev = 0, 300 .funcs = &pp_ip_funcs, 301 }; 302 303 /* This interface only be supported On Vi, 304 * because only smu7/8 can help to load gfx/sdma fw, 305 * smu need to be enabled before load other ip's fw. 306 * so call start smu to load smu7 fw and other ip's fw 307 */ 308 static int pp_dpm_load_fw(void *handle) 309 { 310 struct pp_hwmgr *hwmgr = handle; 311 312 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu) 313 return -EINVAL; 314 315 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { 316 pr_err("fw load failed\n"); 317 return -EINVAL; 318 } 319 320 return 0; 321 } 322 323 static int pp_dpm_fw_loading_complete(void *handle) 324 { 325 return 0; 326 } 327 328 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) 329 { 330 struct pp_hwmgr *hwmgr = handle; 331 332 if (!hwmgr || !hwmgr->pm_en) 333 return -EINVAL; 334 335 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { 336 pr_info_ratelimited("%s was not implemented.\n", __func__); 337 return 0; 338 } 339 340 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); 341 } 342 343 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, 344 enum amd_dpm_forced_level *level) 345 { 346 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 347 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 348 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 349 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 350 351 if (!(hwmgr->dpm_level & profile_mode_mask)) { 352 /* enter umd pstate, save current level, disable gfx cg*/ 353 if (*level & profile_mode_mask) { 354 hwmgr->saved_dpm_level = hwmgr->dpm_level; 355 hwmgr->en_umd_pstate = true; 356 } 357 } else { 358 /* exit umd pstate, restore level, enable gfx cg*/ 359 if (!(*level & profile_mode_mask)) { 360 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 361 *level = hwmgr->saved_dpm_level; 362 hwmgr->en_umd_pstate = false; 363 } 364 } 365 } 366 367 static int pp_dpm_force_performance_level(void *handle, 368 enum amd_dpm_forced_level level) 369 { 370 struct pp_hwmgr *hwmgr = handle; 371 372 if (!hwmgr || !hwmgr->pm_en) 373 return -EINVAL; 374 375 if (level == hwmgr->dpm_level) 376 return 0; 377 378 pp_dpm_en_umd_pstate(hwmgr, &level); 379 hwmgr->request_dpm_level = level; 380 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 381 382 return 0; 383 } 384 385 static enum amd_dpm_forced_level pp_dpm_get_performance_level( 386 void *handle) 387 { 388 struct pp_hwmgr *hwmgr = handle; 389 390 if (!hwmgr || !hwmgr->pm_en) 391 return -EINVAL; 392 393 return hwmgr->dpm_level; 394 } 395 396 static uint32_t pp_dpm_get_sclk(void *handle, bool low) 397 { 398 struct pp_hwmgr *hwmgr = handle; 399 400 if (!hwmgr || !hwmgr->pm_en) 401 return 0; 402 403 if (hwmgr->hwmgr_func->get_sclk == NULL) { 404 pr_info_ratelimited("%s was not implemented.\n", __func__); 405 return 0; 406 } 407 return hwmgr->hwmgr_func->get_sclk(hwmgr, low); 408 } 409 410 static uint32_t pp_dpm_get_mclk(void *handle, bool low) 411 { 412 struct pp_hwmgr *hwmgr = handle; 413 414 if (!hwmgr || !hwmgr->pm_en) 415 return 0; 416 417 if (hwmgr->hwmgr_func->get_mclk == NULL) { 418 pr_info_ratelimited("%s was not implemented.\n", __func__); 419 return 0; 420 } 421 return hwmgr->hwmgr_func->get_mclk(hwmgr, low); 422 } 423 424 static void pp_dpm_powergate_vce(void *handle, bool gate) 425 { 426 struct pp_hwmgr *hwmgr = handle; 427 428 if (!hwmgr || !hwmgr->pm_en) 429 return; 430 431 if (hwmgr->hwmgr_func->powergate_vce == NULL) { 432 pr_info_ratelimited("%s was not implemented.\n", __func__); 433 return; 434 } 435 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); 436 } 437 438 static void pp_dpm_powergate_uvd(void *handle, bool gate) 439 { 440 struct pp_hwmgr *hwmgr = handle; 441 442 if (!hwmgr || !hwmgr->pm_en) 443 return; 444 445 if (hwmgr->hwmgr_func->powergate_uvd == NULL) { 446 pr_info_ratelimited("%s was not implemented.\n", __func__); 447 return; 448 } 449 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); 450 } 451 452 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, 453 enum amd_pm_state_type *user_state) 454 { 455 struct pp_hwmgr *hwmgr = handle; 456 457 if (!hwmgr || !hwmgr->pm_en) 458 return -EINVAL; 459 460 return hwmgr_handle_task(hwmgr, task_id, user_state); 461 } 462 463 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) 464 { 465 struct pp_hwmgr *hwmgr = handle; 466 struct pp_power_state *state; 467 enum amd_pm_state_type pm_type; 468 469 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps) 470 return -EINVAL; 471 472 state = hwmgr->current_ps; 473 474 switch (state->classification.ui_label) { 475 case PP_StateUILabel_Battery: 476 pm_type = POWER_STATE_TYPE_BATTERY; 477 break; 478 case PP_StateUILabel_Balanced: 479 pm_type = POWER_STATE_TYPE_BALANCED; 480 break; 481 case PP_StateUILabel_Performance: 482 pm_type = POWER_STATE_TYPE_PERFORMANCE; 483 break; 484 default: 485 if (state->classification.flags & PP_StateClassificationFlag_Boot) 486 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 487 else 488 pm_type = POWER_STATE_TYPE_DEFAULT; 489 break; 490 } 491 492 return pm_type; 493 } 494 495 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) 496 { 497 struct pp_hwmgr *hwmgr = handle; 498 499 if (!hwmgr || !hwmgr->pm_en) 500 return -EOPNOTSUPP; 501 502 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) 503 return -EOPNOTSUPP; 504 505 if (mode == U32_MAX) 506 return -EINVAL; 507 508 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); 509 510 return 0; 511 } 512 513 static int pp_dpm_get_fan_control_mode(void *handle, uint32_t *fan_mode) 514 { 515 struct pp_hwmgr *hwmgr = handle; 516 517 if (!hwmgr || !hwmgr->pm_en) 518 return -EOPNOTSUPP; 519 520 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) 521 return -EOPNOTSUPP; 522 523 if (!fan_mode) 524 return -EINVAL; 525 526 *fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); 527 return 0; 528 } 529 530 static int pp_dpm_set_fan_speed_pwm(void *handle, uint32_t speed) 531 { 532 struct pp_hwmgr *hwmgr = handle; 533 534 if (!hwmgr || !hwmgr->pm_en) 535 return -EOPNOTSUPP; 536 537 if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL) 538 return -EOPNOTSUPP; 539 540 if (speed == U32_MAX) 541 return -EINVAL; 542 543 return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed); 544 } 545 546 static int pp_dpm_get_fan_speed_pwm(void *handle, uint32_t *speed) 547 { 548 struct pp_hwmgr *hwmgr = handle; 549 550 if (!hwmgr || !hwmgr->pm_en) 551 return -EOPNOTSUPP; 552 553 if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL) 554 return -EOPNOTSUPP; 555 556 if (!speed) 557 return -EINVAL; 558 559 return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed); 560 } 561 562 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) 563 { 564 struct pp_hwmgr *hwmgr = handle; 565 566 if (!hwmgr || !hwmgr->pm_en) 567 return -EOPNOTSUPP; 568 569 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) 570 return -EOPNOTSUPP; 571 572 if (!rpm) 573 return -EINVAL; 574 575 return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); 576 } 577 578 static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm) 579 { 580 struct pp_hwmgr *hwmgr = handle; 581 582 if (!hwmgr || !hwmgr->pm_en) 583 return -EOPNOTSUPP; 584 585 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) 586 return -EOPNOTSUPP; 587 588 if (rpm == U32_MAX) 589 return -EINVAL; 590 591 return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm); 592 } 593 594 static int pp_dpm_get_pp_num_states(void *handle, 595 struct pp_states_info *data) 596 { 597 struct pp_hwmgr *hwmgr = handle; 598 int i; 599 600 memset(data, 0, sizeof(*data)); 601 602 if (!hwmgr || !hwmgr->pm_en || !hwmgr->ps) 603 return -EINVAL; 604 605 data->nums = hwmgr->num_ps; 606 607 for (i = 0; i < hwmgr->num_ps; i++) { 608 struct pp_power_state *state = (struct pp_power_state *) 609 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); 610 switch (state->classification.ui_label) { 611 case PP_StateUILabel_Battery: 612 data->states[i] = POWER_STATE_TYPE_BATTERY; 613 break; 614 case PP_StateUILabel_Balanced: 615 data->states[i] = POWER_STATE_TYPE_BALANCED; 616 break; 617 case PP_StateUILabel_Performance: 618 data->states[i] = POWER_STATE_TYPE_PERFORMANCE; 619 break; 620 default: 621 if (state->classification.flags & PP_StateClassificationFlag_Boot) 622 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT; 623 else 624 data->states[i] = POWER_STATE_TYPE_DEFAULT; 625 } 626 } 627 return 0; 628 } 629 630 static int pp_dpm_get_pp_table(void *handle, char **table) 631 { 632 struct pp_hwmgr *hwmgr = handle; 633 634 if (!hwmgr || !hwmgr->pm_en || !table) 635 return -EINVAL; 636 637 if (!hwmgr->soft_pp_table) 638 return -EOPNOTSUPP; 639 640 *table = (char *)hwmgr->soft_pp_table; 641 return hwmgr->soft_pp_table_size; 642 } 643 644 static int amd_powerplay_reset(void *handle) 645 { 646 struct pp_hwmgr *hwmgr = handle; 647 int ret; 648 649 ret = hwmgr_hw_fini(hwmgr); 650 if (ret) 651 return ret; 652 653 ret = hwmgr_hw_init(hwmgr); 654 if (ret) 655 return ret; 656 657 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL); 658 } 659 660 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) 661 { 662 struct pp_hwmgr *hwmgr = handle; 663 int ret = -ENOMEM; 664 665 if (!hwmgr || !hwmgr->pm_en) 666 return -EINVAL; 667 668 if (!hwmgr->hardcode_pp_table) { 669 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table, 670 hwmgr->soft_pp_table_size, 671 GFP_KERNEL); 672 if (!hwmgr->hardcode_pp_table) 673 return ret; 674 } 675 676 memcpy(hwmgr->hardcode_pp_table, buf, size); 677 678 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table; 679 680 ret = amd_powerplay_reset(handle); 681 if (ret) 682 return ret; 683 684 if (hwmgr->hwmgr_func->avfs_control) 685 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false); 686 687 return ret; 688 } 689 690 static int pp_dpm_force_clock_level(void *handle, 691 enum pp_clock_type type, uint32_t mask) 692 { 693 struct pp_hwmgr *hwmgr = handle; 694 695 if (!hwmgr || !hwmgr->pm_en) 696 return -EINVAL; 697 698 if (hwmgr->hwmgr_func->force_clock_level == NULL) { 699 pr_info_ratelimited("%s was not implemented.\n", __func__); 700 return 0; 701 } 702 703 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 704 pr_debug("force clock level is for dpm manual mode only.\n"); 705 return -EINVAL; 706 } 707 708 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); 709 } 710 711 static int pp_dpm_emit_clock_levels(void *handle, 712 enum pp_clock_type type, 713 char *buf, 714 int *offset) 715 { 716 struct pp_hwmgr *hwmgr = handle; 717 718 if (!hwmgr || !hwmgr->pm_en) 719 return -EOPNOTSUPP; 720 721 if (!hwmgr->hwmgr_func->emit_clock_levels) 722 return -ENOENT; 723 724 return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset); 725 } 726 727 static int pp_dpm_get_sclk_od(void *handle) 728 { 729 struct pp_hwmgr *hwmgr = handle; 730 731 if (!hwmgr || !hwmgr->pm_en) 732 return -EINVAL; 733 734 if (hwmgr->hwmgr_func->get_sclk_od == NULL) { 735 pr_info_ratelimited("%s was not implemented.\n", __func__); 736 return 0; 737 } 738 return hwmgr->hwmgr_func->get_sclk_od(hwmgr); 739 } 740 741 static int pp_dpm_set_sclk_od(void *handle, uint32_t value) 742 { 743 struct pp_hwmgr *hwmgr = handle; 744 745 if (!hwmgr || !hwmgr->pm_en) 746 return -EINVAL; 747 748 if (hwmgr->hwmgr_func->set_sclk_od == NULL) { 749 pr_info_ratelimited("%s was not implemented.\n", __func__); 750 return 0; 751 } 752 753 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value); 754 } 755 756 static int pp_dpm_get_mclk_od(void *handle) 757 { 758 struct pp_hwmgr *hwmgr = handle; 759 760 if (!hwmgr || !hwmgr->pm_en) 761 return -EINVAL; 762 763 if (hwmgr->hwmgr_func->get_mclk_od == NULL) { 764 pr_info_ratelimited("%s was not implemented.\n", __func__); 765 return 0; 766 } 767 return hwmgr->hwmgr_func->get_mclk_od(hwmgr); 768 } 769 770 static int pp_dpm_set_mclk_od(void *handle, uint32_t value) 771 { 772 struct pp_hwmgr *hwmgr = handle; 773 774 if (!hwmgr || !hwmgr->pm_en) 775 return -EINVAL; 776 777 if (hwmgr->hwmgr_func->set_mclk_od == NULL) { 778 pr_info_ratelimited("%s was not implemented.\n", __func__); 779 return 0; 780 } 781 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); 782 } 783 784 static int pp_dpm_read_sensor(void *handle, int idx, 785 void *value, int *size) 786 { 787 struct pp_hwmgr *hwmgr = handle; 788 789 if (!hwmgr || !hwmgr->pm_en || !value) 790 return -EINVAL; 791 792 switch (idx) { 793 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 794 *((uint32_t *)value) = hwmgr->pstate_sclk * 100; 795 return 0; 796 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 797 *((uint32_t *)value) = hwmgr->pstate_mclk * 100; 798 return 0; 799 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 800 *((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100; 801 return 0; 802 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 803 *((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100; 804 return 0; 805 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 806 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM; 807 return 0; 808 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 809 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM; 810 return 0; 811 default: 812 return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size); 813 } 814 } 815 816 static struct amd_vce_state* 817 pp_dpm_get_vce_clock_state(void *handle, unsigned idx) 818 { 819 struct pp_hwmgr *hwmgr = handle; 820 821 if (!hwmgr || !hwmgr->pm_en) 822 return NULL; 823 824 if (idx < hwmgr->num_vce_state_tables) 825 return &hwmgr->vce_states[idx]; 826 return NULL; 827 } 828 829 static int pp_get_power_profile_mode(void *handle, char *buf) 830 { 831 struct pp_hwmgr *hwmgr = handle; 832 833 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode) 834 return -EOPNOTSUPP; 835 if (!buf) 836 return -EINVAL; 837 838 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf); 839 } 840 841 static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size) 842 { 843 struct pp_hwmgr *hwmgr = handle; 844 845 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode) 846 return -EOPNOTSUPP; 847 848 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 849 pr_debug("power profile setting is for manual dpm mode only.\n"); 850 return -EINVAL; 851 } 852 853 return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); 854 } 855 856 static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size) 857 { 858 struct pp_hwmgr *hwmgr = handle; 859 860 if (!hwmgr || !hwmgr->pm_en) 861 return -EINVAL; 862 863 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL) 864 return 0; 865 866 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size); 867 } 868 869 static int pp_odn_edit_dpm_table(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 870 long *input, uint32_t size) 871 { 872 struct pp_hwmgr *hwmgr = handle; 873 874 if (!hwmgr || !hwmgr->pm_en) 875 return -EINVAL; 876 877 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { 878 pr_info_ratelimited("%s was not implemented.\n", __func__); 879 return 0; 880 } 881 882 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size); 883 } 884 885 static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state) 886 { 887 struct pp_hwmgr *hwmgr = handle; 888 889 if (!hwmgr) 890 return -EINVAL; 891 892 if (!hwmgr->pm_en) 893 return 0; 894 895 if (hwmgr->hwmgr_func->set_mp1_state) 896 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state); 897 898 return 0; 899 } 900 901 static int pp_dpm_switch_power_profile(void *handle, 902 enum PP_SMC_POWER_PROFILE type, bool en) 903 { 904 struct pp_hwmgr *hwmgr = handle; 905 long workload[1]; 906 uint32_t index; 907 908 if (!hwmgr || !hwmgr->pm_en) 909 return -EINVAL; 910 911 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { 912 pr_info_ratelimited("%s was not implemented.\n", __func__); 913 return -EINVAL; 914 } 915 916 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 917 return -EINVAL; 918 919 if (!en) { 920 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]); 921 index = fls(hwmgr->workload_mask); 922 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0; 923 workload[0] = hwmgr->workload_setting[index]; 924 } else { 925 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]); 926 index = fls(hwmgr->workload_mask); 927 index = index <= Workload_Policy_Max ? index - 1 : 0; 928 workload[0] = hwmgr->workload_setting[index]; 929 } 930 931 if (type == PP_SMC_POWER_PROFILE_COMPUTE && 932 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) { 933 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) 934 return -EINVAL; 935 } 936 937 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 938 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0); 939 940 return 0; 941 } 942 943 static int pp_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 944 { 945 struct pp_hwmgr *hwmgr = handle; 946 uint32_t max_power_limit; 947 948 if (!hwmgr || !hwmgr->pm_en) 949 return -EINVAL; 950 951 if (hwmgr->hwmgr_func->set_power_limit == NULL) { 952 pr_info_ratelimited("%s was not implemented.\n", __func__); 953 return -EINVAL; 954 } 955 956 if (limit == 0) 957 limit = hwmgr->default_power_limit; 958 959 max_power_limit = hwmgr->default_power_limit; 960 if (hwmgr->od_enabled) { 961 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); 962 max_power_limit /= 100; 963 } 964 965 if (limit > max_power_limit) 966 return -EINVAL; 967 968 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit); 969 hwmgr->power_limit = limit; 970 return 0; 971 } 972 973 static int pp_get_power_limit(void *handle, uint32_t *limit, 974 enum pp_power_limit_level pp_limit_level, 975 enum pp_power_type power_type) 976 { 977 struct pp_hwmgr *hwmgr = handle; 978 int ret = 0; 979 980 if (!hwmgr || !hwmgr->pm_en || !limit) 981 return -EINVAL; 982 983 if (power_type != PP_PWR_TYPE_SUSTAINED) 984 return -EOPNOTSUPP; 985 986 switch (pp_limit_level) { 987 case PP_PWR_LIMIT_CURRENT: 988 *limit = hwmgr->power_limit; 989 break; 990 case PP_PWR_LIMIT_DEFAULT: 991 *limit = hwmgr->default_power_limit; 992 break; 993 case PP_PWR_LIMIT_MAX: 994 *limit = hwmgr->default_power_limit; 995 if (hwmgr->od_enabled) { 996 *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); 997 *limit /= 100; 998 } 999 break; 1000 case PP_PWR_LIMIT_MIN: 1001 *limit = 0; 1002 break; 1003 default: 1004 ret = -EOPNOTSUPP; 1005 break; 1006 } 1007 1008 return ret; 1009 } 1010 1011 static int pp_display_configuration_change(void *handle, 1012 const struct amd_pp_display_configuration *display_config) 1013 { 1014 struct pp_hwmgr *hwmgr = handle; 1015 1016 if (!hwmgr || !hwmgr->pm_en) 1017 return -EINVAL; 1018 1019 phm_store_dal_configuration_data(hwmgr, display_config); 1020 return 0; 1021 } 1022 1023 static int pp_get_display_power_level(void *handle, 1024 struct amd_pp_simple_clock_info *output) 1025 { 1026 struct pp_hwmgr *hwmgr = handle; 1027 1028 if (!hwmgr || !hwmgr->pm_en || !output) 1029 return -EINVAL; 1030 1031 return phm_get_dal_power_level(hwmgr, output); 1032 } 1033 1034 static int pp_get_current_clocks(void *handle, 1035 struct amd_pp_clock_info *clocks) 1036 { 1037 struct amd_pp_simple_clock_info simple_clocks = { 0 }; 1038 struct pp_clock_info hw_clocks; 1039 struct pp_hwmgr *hwmgr = handle; 1040 int ret = 0; 1041 1042 if (!hwmgr || !hwmgr->pm_en) 1043 return -EINVAL; 1044 1045 phm_get_dal_power_level(hwmgr, &simple_clocks); 1046 1047 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1048 PHM_PlatformCaps_PowerContainment)) 1049 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, 1050 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment); 1051 else 1052 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, 1053 &hw_clocks, PHM_PerformanceLevelDesignation_Activity); 1054 1055 if (ret) { 1056 pr_debug("Error in phm_get_clock_info \n"); 1057 return -EINVAL; 1058 } 1059 1060 clocks->min_engine_clock = hw_clocks.min_eng_clk; 1061 clocks->max_engine_clock = hw_clocks.max_eng_clk; 1062 clocks->min_memory_clock = hw_clocks.min_mem_clk; 1063 clocks->max_memory_clock = hw_clocks.max_mem_clk; 1064 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; 1065 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; 1066 1067 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1068 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1069 1070 if (simple_clocks.level == 0) 1071 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7; 1072 else 1073 clocks->max_clocks_state = simple_clocks.level; 1074 1075 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { 1076 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1077 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1078 } 1079 return 0; 1080 } 1081 1082 static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) 1083 { 1084 struct pp_hwmgr *hwmgr = handle; 1085 1086 if (!hwmgr || !hwmgr->pm_en) 1087 return -EINVAL; 1088 1089 if (clocks == NULL) 1090 return -EINVAL; 1091 1092 return phm_get_clock_by_type(hwmgr, type, clocks); 1093 } 1094 1095 static int pp_get_clock_by_type_with_latency(void *handle, 1096 enum amd_pp_clock_type type, 1097 struct pp_clock_levels_with_latency *clocks) 1098 { 1099 struct pp_hwmgr *hwmgr = handle; 1100 1101 if (!hwmgr || !hwmgr->pm_en || !clocks) 1102 return -EINVAL; 1103 1104 return phm_get_clock_by_type_with_latency(hwmgr, type, clocks); 1105 } 1106 1107 static int pp_get_clock_by_type_with_voltage(void *handle, 1108 enum amd_pp_clock_type type, 1109 struct pp_clock_levels_with_voltage *clocks) 1110 { 1111 struct pp_hwmgr *hwmgr = handle; 1112 1113 if (!hwmgr || !hwmgr->pm_en || !clocks) 1114 return -EINVAL; 1115 1116 return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks); 1117 } 1118 1119 static int pp_set_watermarks_for_clocks_ranges(void *handle, 1120 void *clock_ranges) 1121 { 1122 struct pp_hwmgr *hwmgr = handle; 1123 1124 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) 1125 return -EINVAL; 1126 1127 return phm_set_watermarks_for_clocks_ranges(hwmgr, 1128 clock_ranges); 1129 } 1130 1131 static int pp_display_clock_voltage_request(void *handle, 1132 struct pp_display_clock_request *clock) 1133 { 1134 struct pp_hwmgr *hwmgr = handle; 1135 1136 if (!hwmgr || !hwmgr->pm_en || !clock) 1137 return -EINVAL; 1138 1139 return phm_display_clock_voltage_request(hwmgr, clock); 1140 } 1141 1142 static int pp_get_display_mode_validation_clocks(void *handle, 1143 struct amd_pp_simple_clock_info *clocks) 1144 { 1145 struct pp_hwmgr *hwmgr = handle; 1146 int ret = 0; 1147 1148 if (!hwmgr || !hwmgr->pm_en || !clocks) 1149 return -EINVAL; 1150 1151 clocks->level = PP_DAL_POWERLEVEL_7; 1152 1153 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) 1154 ret = phm_get_max_high_clocks(hwmgr, clocks); 1155 1156 return ret; 1157 } 1158 1159 static int pp_dpm_powergate_mmhub(void *handle) 1160 { 1161 struct pp_hwmgr *hwmgr = handle; 1162 1163 if (!hwmgr || !hwmgr->pm_en) 1164 return -EINVAL; 1165 1166 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) { 1167 pr_info_ratelimited("%s was not implemented.\n", __func__); 1168 return 0; 1169 } 1170 1171 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr); 1172 } 1173 1174 static int pp_dpm_powergate_gfx(void *handle, bool gate) 1175 { 1176 struct pp_hwmgr *hwmgr = handle; 1177 1178 if (!hwmgr || !hwmgr->pm_en) 1179 return 0; 1180 1181 if (hwmgr->hwmgr_func->powergate_gfx == NULL) { 1182 pr_info_ratelimited("%s was not implemented.\n", __func__); 1183 return 0; 1184 } 1185 1186 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); 1187 } 1188 1189 static void pp_dpm_powergate_acp(void *handle, bool gate) 1190 { 1191 struct pp_hwmgr *hwmgr = handle; 1192 1193 if (!hwmgr || !hwmgr->pm_en) 1194 return; 1195 1196 if (hwmgr->hwmgr_func->powergate_acp == NULL) { 1197 pr_info_ratelimited("%s was not implemented.\n", __func__); 1198 return; 1199 } 1200 1201 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate); 1202 } 1203 1204 static void pp_dpm_powergate_sdma(void *handle, bool gate) 1205 { 1206 struct pp_hwmgr *hwmgr = handle; 1207 1208 if (!hwmgr) 1209 return; 1210 1211 if (hwmgr->hwmgr_func->powergate_sdma == NULL) { 1212 pr_info_ratelimited("%s was not implemented.\n", __func__); 1213 return; 1214 } 1215 1216 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate); 1217 } 1218 1219 static int pp_set_powergating_by_smu(void *handle, 1220 uint32_t block_type, 1221 bool gate, 1222 int inst) 1223 { 1224 int ret = 0; 1225 1226 switch (block_type) { 1227 case AMD_IP_BLOCK_TYPE_UVD: 1228 case AMD_IP_BLOCK_TYPE_VCN: 1229 pp_dpm_powergate_uvd(handle, gate); 1230 break; 1231 case AMD_IP_BLOCK_TYPE_VCE: 1232 pp_dpm_powergate_vce(handle, gate); 1233 break; 1234 case AMD_IP_BLOCK_TYPE_GMC: 1235 /* 1236 * For now, this is only used on PICASSO. 1237 * And only "gate" operation is supported. 1238 */ 1239 if (gate) 1240 pp_dpm_powergate_mmhub(handle); 1241 break; 1242 case AMD_IP_BLOCK_TYPE_GFX: 1243 ret = pp_dpm_powergate_gfx(handle, gate); 1244 break; 1245 case AMD_IP_BLOCK_TYPE_ACP: 1246 pp_dpm_powergate_acp(handle, gate); 1247 break; 1248 case AMD_IP_BLOCK_TYPE_SDMA: 1249 pp_dpm_powergate_sdma(handle, gate); 1250 break; 1251 default: 1252 break; 1253 } 1254 return ret; 1255 } 1256 1257 static int pp_notify_smu_enable_pwe(void *handle) 1258 { 1259 struct pp_hwmgr *hwmgr = handle; 1260 1261 if (!hwmgr || !hwmgr->pm_en) 1262 return -EINVAL; 1263 1264 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) { 1265 pr_info_ratelimited("%s was not implemented.\n", __func__); 1266 return -EINVAL; 1267 } 1268 1269 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr); 1270 1271 return 0; 1272 } 1273 1274 static int pp_enable_mgpu_fan_boost(void *handle) 1275 { 1276 struct pp_hwmgr *hwmgr = handle; 1277 1278 if (!hwmgr) 1279 return -EINVAL; 1280 1281 if (!hwmgr->pm_en || 1282 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL) 1283 return 0; 1284 1285 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr); 1286 1287 return 0; 1288 } 1289 1290 static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock) 1291 { 1292 struct pp_hwmgr *hwmgr = handle; 1293 1294 if (!hwmgr || !hwmgr->pm_en) 1295 return -EINVAL; 1296 1297 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) { 1298 pr_debug("%s was not implemented.\n", __func__); 1299 return -EINVAL; 1300 } 1301 1302 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock); 1303 1304 return 0; 1305 } 1306 1307 static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock) 1308 { 1309 struct pp_hwmgr *hwmgr = handle; 1310 1311 if (!hwmgr || !hwmgr->pm_en) 1312 return -EINVAL; 1313 1314 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) { 1315 pr_debug("%s was not implemented.\n", __func__); 1316 return -EINVAL; 1317 } 1318 1319 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock); 1320 1321 return 0; 1322 } 1323 1324 static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock) 1325 { 1326 struct pp_hwmgr *hwmgr = handle; 1327 1328 if (!hwmgr || !hwmgr->pm_en) 1329 return -EINVAL; 1330 1331 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) { 1332 pr_debug("%s was not implemented.\n", __func__); 1333 return -EINVAL; 1334 } 1335 1336 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); 1337 1338 return 0; 1339 } 1340 1341 static int pp_set_active_display_count(void *handle, uint32_t count) 1342 { 1343 struct pp_hwmgr *hwmgr = handle; 1344 1345 if (!hwmgr || !hwmgr->pm_en) 1346 return -EINVAL; 1347 1348 return phm_set_active_display_count(hwmgr, count); 1349 } 1350 1351 static int pp_get_asic_baco_capability(void *handle) 1352 { 1353 struct pp_hwmgr *hwmgr = handle; 1354 1355 if (!hwmgr) 1356 return false; 1357 1358 if (!(hwmgr->not_vf && amdgpu_dpm) || 1359 !hwmgr->hwmgr_func->get_bamaco_support) 1360 return false; 1361 1362 return hwmgr->hwmgr_func->get_bamaco_support(hwmgr); 1363 } 1364 1365 static int pp_get_asic_baco_state(void *handle, int *state) 1366 { 1367 struct pp_hwmgr *hwmgr = handle; 1368 1369 if (!hwmgr) 1370 return -EINVAL; 1371 1372 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state) 1373 return 0; 1374 1375 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state); 1376 1377 return 0; 1378 } 1379 1380 static int pp_set_asic_baco_state(void *handle, int state) 1381 { 1382 struct pp_hwmgr *hwmgr = handle; 1383 1384 if (!hwmgr) 1385 return -EINVAL; 1386 1387 if (!(hwmgr->not_vf && amdgpu_dpm) || 1388 !hwmgr->hwmgr_func->set_asic_baco_state) 1389 return 0; 1390 1391 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state); 1392 1393 return 0; 1394 } 1395 1396 static int pp_get_ppfeature_status(void *handle, char *buf) 1397 { 1398 struct pp_hwmgr *hwmgr = handle; 1399 1400 if (!hwmgr || !hwmgr->pm_en || !buf) 1401 return -EINVAL; 1402 1403 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) { 1404 pr_info_ratelimited("%s was not implemented.\n", __func__); 1405 return -EINVAL; 1406 } 1407 1408 return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf); 1409 } 1410 1411 static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks) 1412 { 1413 struct pp_hwmgr *hwmgr = handle; 1414 1415 if (!hwmgr || !hwmgr->pm_en) 1416 return -EINVAL; 1417 1418 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) { 1419 pr_info_ratelimited("%s was not implemented.\n", __func__); 1420 return -EINVAL; 1421 } 1422 1423 return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks); 1424 } 1425 1426 static int pp_asic_reset_mode_2(void *handle) 1427 { 1428 struct pp_hwmgr *hwmgr = handle; 1429 1430 if (!hwmgr || !hwmgr->pm_en) 1431 return -EINVAL; 1432 1433 if (hwmgr->hwmgr_func->asic_reset == NULL) { 1434 pr_info_ratelimited("%s was not implemented.\n", __func__); 1435 return -EINVAL; 1436 } 1437 1438 return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2); 1439 } 1440 1441 static int pp_smu_i2c_bus_access(void *handle, bool acquire) 1442 { 1443 struct pp_hwmgr *hwmgr = handle; 1444 1445 if (!hwmgr || !hwmgr->pm_en) 1446 return -EINVAL; 1447 1448 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) { 1449 pr_info_ratelimited("%s was not implemented.\n", __func__); 1450 return -EINVAL; 1451 } 1452 1453 return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire); 1454 } 1455 1456 static int pp_set_df_cstate(void *handle, enum pp_df_cstate state) 1457 { 1458 struct pp_hwmgr *hwmgr = handle; 1459 1460 if (!hwmgr) 1461 return -EINVAL; 1462 1463 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate) 1464 return 0; 1465 1466 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state); 1467 1468 return 0; 1469 } 1470 1471 static int pp_set_xgmi_pstate(void *handle, uint32_t pstate) 1472 { 1473 struct pp_hwmgr *hwmgr = handle; 1474 1475 if (!hwmgr) 1476 return -EINVAL; 1477 1478 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate) 1479 return 0; 1480 1481 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate); 1482 1483 return 0; 1484 } 1485 1486 static ssize_t pp_get_gpu_metrics(void *handle, void **table) 1487 { 1488 struct pp_hwmgr *hwmgr = handle; 1489 1490 if (!hwmgr) 1491 return -EINVAL; 1492 1493 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics) 1494 return -EOPNOTSUPP; 1495 1496 return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table); 1497 } 1498 1499 static int pp_gfx_state_change_set(void *handle, uint32_t state) 1500 { 1501 struct pp_hwmgr *hwmgr = handle; 1502 1503 if (!hwmgr || !hwmgr->pm_en) 1504 return -EINVAL; 1505 1506 if (hwmgr->hwmgr_func->gfx_state_change == NULL) { 1507 pr_info_ratelimited("%s was not implemented.\n", __func__); 1508 return -EINVAL; 1509 } 1510 1511 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state); 1512 return 0; 1513 } 1514 1515 static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size) 1516 { 1517 struct pp_hwmgr *hwmgr = handle; 1518 struct amdgpu_device *adev = hwmgr->adev; 1519 int err; 1520 1521 if (!addr || !size) 1522 return -EINVAL; 1523 1524 *addr = NULL; 1525 *size = 0; 1526 if (adev->pm.smu_prv_buffer) { 1527 err = amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr); 1528 if (err) 1529 return err; 1530 *size = adev->pm.smu_prv_buffer_size; 1531 } 1532 1533 return 0; 1534 } 1535 1536 static void pp_pm_compute_clocks(void *handle) 1537 { 1538 struct pp_hwmgr *hwmgr = handle; 1539 struct amdgpu_device *adev = hwmgr->adev; 1540 1541 if (!adev->dc_enabled) { 1542 amdgpu_dpm_get_display_cfg(adev); 1543 pp_display_configuration_change(handle, 1544 &adev->pm.pm_display_cfg); 1545 } 1546 1547 pp_dpm_dispatch_tasks(handle, 1548 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 1549 NULL); 1550 } 1551 1552 static const struct amd_pm_funcs pp_dpm_funcs = { 1553 .load_firmware = pp_dpm_load_fw, 1554 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, 1555 .force_performance_level = pp_dpm_force_performance_level, 1556 .get_performance_level = pp_dpm_get_performance_level, 1557 .get_current_power_state = pp_dpm_get_current_power_state, 1558 .dispatch_tasks = pp_dpm_dispatch_tasks, 1559 .set_fan_control_mode = pp_dpm_set_fan_control_mode, 1560 .get_fan_control_mode = pp_dpm_get_fan_control_mode, 1561 .set_fan_speed_pwm = pp_dpm_set_fan_speed_pwm, 1562 .get_fan_speed_pwm = pp_dpm_get_fan_speed_pwm, 1563 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, 1564 .set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm, 1565 .get_pp_num_states = pp_dpm_get_pp_num_states, 1566 .get_pp_table = pp_dpm_get_pp_table, 1567 .set_pp_table = pp_dpm_set_pp_table, 1568 .force_clock_level = pp_dpm_force_clock_level, 1569 .emit_clock_levels = pp_dpm_emit_clock_levels, 1570 .get_sclk_od = pp_dpm_get_sclk_od, 1571 .set_sclk_od = pp_dpm_set_sclk_od, 1572 .get_mclk_od = pp_dpm_get_mclk_od, 1573 .set_mclk_od = pp_dpm_set_mclk_od, 1574 .read_sensor = pp_dpm_read_sensor, 1575 .get_vce_clock_state = pp_dpm_get_vce_clock_state, 1576 .switch_power_profile = pp_dpm_switch_power_profile, 1577 .set_clockgating_by_smu = pp_set_clockgating_by_smu, 1578 .set_powergating_by_smu = pp_set_powergating_by_smu, 1579 .get_power_profile_mode = pp_get_power_profile_mode, 1580 .set_power_profile_mode = pp_set_power_profile_mode, 1581 .set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol, 1582 .odn_edit_dpm_table = pp_odn_edit_dpm_table, 1583 .set_mp1_state = pp_dpm_set_mp1_state, 1584 .set_power_limit = pp_set_power_limit, 1585 .get_power_limit = pp_get_power_limit, 1586 /* export to DC */ 1587 .get_sclk = pp_dpm_get_sclk, 1588 .get_mclk = pp_dpm_get_mclk, 1589 .display_configuration_change = pp_display_configuration_change, 1590 .get_display_power_level = pp_get_display_power_level, 1591 .get_current_clocks = pp_get_current_clocks, 1592 .get_clock_by_type = pp_get_clock_by_type, 1593 .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency, 1594 .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage, 1595 .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges, 1596 .display_clock_voltage_request = pp_display_clock_voltage_request, 1597 .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks, 1598 .notify_smu_enable_pwe = pp_notify_smu_enable_pwe, 1599 .enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost, 1600 .set_active_display_count = pp_set_active_display_count, 1601 .set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk, 1602 .set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq, 1603 .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq, 1604 .get_asic_baco_capability = pp_get_asic_baco_capability, 1605 .get_asic_baco_state = pp_get_asic_baco_state, 1606 .set_asic_baco_state = pp_set_asic_baco_state, 1607 .get_ppfeature_status = pp_get_ppfeature_status, 1608 .set_ppfeature_status = pp_set_ppfeature_status, 1609 .asic_reset_mode_2 = pp_asic_reset_mode_2, 1610 .smu_i2c_bus_access = pp_smu_i2c_bus_access, 1611 .set_df_cstate = pp_set_df_cstate, 1612 .set_xgmi_pstate = pp_set_xgmi_pstate, 1613 .get_gpu_metrics = pp_get_gpu_metrics, 1614 .gfx_state_change_set = pp_gfx_state_change_set, 1615 .get_smu_prv_buf_details = pp_get_prv_buffer_details, 1616 .pm_compute_clocks = pp_pm_compute_clocks, 1617 }; 1618