1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "amdgpu.h" 28 #include "sid.h" 29 #include "ppsmc.h" 30 #include "amdgpu_ucode.h" 31 #include "sislands_smc.h" 32 33 #include "smu/smu_6_0_d.h" 34 #include "smu/smu_6_0_sh_mask.h" 35 36 #include "gca/gfx_6_0_d.h" 37 #include "gca/gfx_6_0_sh_mask.h" 38 39 static int si_set_smc_sram_address(struct amdgpu_device *adev, 40 u32 smc_address, u32 limit) 41 { 42 if (smc_address & 3) 43 return -EINVAL; 44 if ((smc_address + 3) > limit) 45 return -EINVAL; 46 47 WREG32(mmSMC_IND_INDEX_0, smc_address); 48 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); 49 50 return 0; 51 } 52 53 int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, 54 u32 smc_start_address, 55 const u8 *src, u32 byte_count, u32 limit) 56 { 57 unsigned long flags; 58 int ret = 0; 59 u32 data, original_data, addr, extra_shift; 60 61 if (smc_start_address & 3) 62 return -EINVAL; 63 if ((smc_start_address + byte_count) > limit) 64 return -EINVAL; 65 66 addr = smc_start_address; 67 68 spin_lock_irqsave(&adev->smc_idx_lock, flags); 69 while (byte_count >= 4) { 70 /* SMC address space is BE */ 71 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 72 73 ret = si_set_smc_sram_address(adev, addr, limit); 74 if (ret) 75 goto done; 76 77 WREG32(mmSMC_IND_DATA_0, data); 78 79 src += 4; 80 byte_count -= 4; 81 addr += 4; 82 } 83 84 /* RMW for the final bytes */ 85 if (byte_count > 0) { 86 data = 0; 87 88 ret = si_set_smc_sram_address(adev, addr, limit); 89 if (ret) 90 goto done; 91 92 original_data = RREG32(mmSMC_IND_DATA_0); 93 extra_shift = 8 * (4 - byte_count); 94 95 while (byte_count > 0) { 96 /* SMC address space is BE */ 97 data = (data << 8) + *src++; 98 byte_count--; 99 } 100 101 data <<= extra_shift; 102 data |= (original_data & ~((~0UL) << extra_shift)); 103 104 ret = si_set_smc_sram_address(adev, addr, limit); 105 if (ret) 106 goto done; 107 108 WREG32(mmSMC_IND_DATA_0, data); 109 } 110 111 done: 112 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 113 114 return ret; 115 } 116 117 void amdgpu_si_start_smc(struct amdgpu_device *adev) 118 { 119 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 120 121 tmp &= ~RST_REG; 122 123 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 124 } 125 126 void amdgpu_si_reset_smc(struct amdgpu_device *adev) 127 { 128 u32 tmp; 129 130 RREG32(mmCB_CGTT_SCLK_CTRL); 131 RREG32(mmCB_CGTT_SCLK_CTRL); 132 RREG32(mmCB_CGTT_SCLK_CTRL); 133 RREG32(mmCB_CGTT_SCLK_CTRL); 134 135 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) | 136 RST_REG; 137 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 138 } 139 140 int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev) 141 { 142 static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 }; 143 144 return amdgpu_si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1); 145 } 146 147 void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable) 148 { 149 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 150 151 if (enable) 152 tmp &= ~CK_DISABLE; 153 else 154 tmp |= CK_DISABLE; 155 156 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 157 } 158 159 bool amdgpu_si_is_smc_running(struct amdgpu_device *adev) 160 { 161 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 162 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 163 164 if (!(rst & RST_REG) && !(clk & CK_DISABLE)) 165 return true; 166 167 return false; 168 } 169 170 PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, 171 PPSMC_Msg msg) 172 { 173 u32 tmp; 174 int i; 175 int usec_timeout; 176 177 /* SMC seems to process some messages exceptionally slowly. */ 178 switch (msg) { 179 case PPSMC_MSG_NoForcedLevel: 180 case PPSMC_MSG_SetEnabledLevels: 181 case PPSMC_MSG_SetForcedLevels: 182 case PPSMC_MSG_DisableULV: 183 case PPSMC_MSG_SwitchToSwState: 184 usec_timeout = 1000000; /* 1 sec */ 185 break; 186 default: 187 usec_timeout = 200000; /* 200 ms */ 188 break; 189 } 190 191 if (!amdgpu_si_is_smc_running(adev)) 192 return PPSMC_Result_Failed; 193 194 WREG32(mmSMC_MESSAGE_0, msg); 195 196 for (i = 0; i < usec_timeout; i++) { 197 tmp = RREG32(mmSMC_RESP_0); 198 if (tmp != 0) 199 break; 200 udelay(1); 201 } 202 203 tmp = RREG32(mmSMC_RESP_0); 204 if (tmp == 0) { 205 drm_warn(adev_to_drm(adev), 206 "%s timeout on message: %x (SMC_SCRATCH0: %x)\n", 207 __func__, msg, RREG32(mmSMC_SCRATCH0)); 208 } 209 210 return (PPSMC_Result)tmp; 211 } 212 213 PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev) 214 { 215 u32 tmp; 216 int i; 217 218 if (!amdgpu_si_is_smc_running(adev)) 219 return PPSMC_Result_OK; 220 221 for (i = 0; i < adev->usec_timeout; i++) { 222 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 223 if ((tmp & CKEN) == 0) 224 break; 225 udelay(1); 226 } 227 228 return PPSMC_Result_OK; 229 } 230 231 int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) 232 { 233 const struct smc_firmware_header_v1_0 *hdr; 234 unsigned long flags; 235 u32 ucode_start_address; 236 u32 ucode_size; 237 const u8 *src; 238 u32 data; 239 240 if (!adev->pm.fw) 241 return -EINVAL; 242 243 hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data; 244 245 amdgpu_ucode_print_smc_hdr(&hdr->header); 246 247 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 248 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); 249 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 250 src = (const u8 *) 251 (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 252 if (ucode_size & 3) 253 return -EINVAL; 254 255 spin_lock_irqsave(&adev->smc_idx_lock, flags); 256 WREG32(mmSMC_IND_INDEX_0, ucode_start_address); 257 WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); 258 while (ucode_size >= 4) { 259 /* SMC address space is BE */ 260 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 261 262 WREG32(mmSMC_IND_DATA_0, data); 263 264 src += 4; 265 ucode_size -= 4; 266 } 267 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); 268 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 269 270 return 0; 271 } 272 273 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 274 u32 *value, u32 limit) 275 { 276 unsigned long flags; 277 int ret; 278 279 spin_lock_irqsave(&adev->smc_idx_lock, flags); 280 ret = si_set_smc_sram_address(adev, smc_address, limit); 281 if (ret == 0) 282 *value = RREG32(mmSMC_IND_DATA_0); 283 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 284 285 return ret; 286 } 287 288 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 289 u32 value, u32 limit) 290 { 291 unsigned long flags; 292 int ret; 293 294 spin_lock_irqsave(&adev->smc_idx_lock, flags); 295 ret = si_set_smc_sram_address(adev, smc_address, limit); 296 if (ret == 0) 297 WREG32(mmSMC_IND_DATA_0, value); 298 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 299 300 return ret; 301 } 302