1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SI_DPM_H__ 24 #define __SI_DPM_H__ 25 26 #include "amdgpu_atombios.h" 27 #include "sislands_smc.h" 28 29 #define MC_CG_CONFIG 0x96f 30 #define MC_ARB_CG 0x9fa 31 #define CG_ARB_REQ(x) ((x) << 0) 32 #define CG_ARB_REQ_MASK (0xff << 0) 33 34 #define MC_ARB_DRAM_TIMING_1 0x9fc 35 #define MC_ARB_DRAM_TIMING_2 0x9fd 36 #define MC_ARB_DRAM_TIMING_3 0x9fe 37 #define MC_ARB_DRAM_TIMING2_1 0x9ff 38 #define MC_ARB_DRAM_TIMING2_2 0xa00 39 #define MC_ARB_DRAM_TIMING2_3 0xa01 40 41 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 42 #define RV770_ASI_DFLT 1000 43 #define CYPRESS_HASI_DFLT 400000 44 #define PCIE_PERF_REQ_PECI_GEN1 2 45 #define PCIE_PERF_REQ_PECI_GEN2 3 46 #define PCIE_PERF_REQ_PECI_GEN3 4 47 #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 48 #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 49 50 #define SMC_STROBE_RATIO 0x0F 51 #define SMC_STROBE_ENABLE 0x10 52 53 #define SMC_MC_EDC_RD_FLAG 0x01 54 #define SMC_MC_EDC_WR_FLAG 0x02 55 #define SMC_MC_RTT_ENABLE 0x04 56 #define SMC_MC_STUTTER_EN 0x08 57 58 #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0 59 #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1 60 #define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2 61 #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3 62 63 #define SISLANDS_LEAKAGE_INDEX0 0xff01 64 #define SISLANDS_MAX_LEAKAGE_COUNT 4 65 66 #define SISLANDS_MAX_HARDWARE_POWERLEVELS 5 67 #define SISLANDS_INITIAL_STATE_ARB_INDEX 0 68 #define SISLANDS_ACPI_STATE_ARB_INDEX 1 69 #define SISLANDS_ULV_STATE_ARB_INDEX 2 70 #define SISLANDS_DRIVER_STATE_ARB_INDEX 3 71 72 #define SISLANDS_DPM2_MAX_PULSE_SKIP 256 73 74 #define SISLANDS_DPM2_NEAR_TDP_DEC 10 75 #define SISLANDS_DPM2_ABOVE_SAFE_INC 5 76 #define SISLANDS_DPM2_BELOW_SAFE_INC 20 77 78 #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80 79 80 #define SISLANDS_DPM2_MAXPS_PERCENT_H 99 81 #define SISLANDS_DPM2_MAXPS_PERCENT_M 99 82 83 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 84 #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12 85 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 86 #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E 87 #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF 88 89 #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10 90 91 #define SISLANDS_VRC_DFLT 0xC000B3 92 #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687 93 #define SISLANDS_CGULVPARAMETER_DFLT 0x00040035 94 #define SISLANDS_CGULVCONTROL_DFLT 0x1f007550 95 96 #define SI_ASI_DFLT 10000 97 #define SI_BSP_DFLT 0x41EB 98 #define SI_BSU_DFLT 0x2 99 #define SI_AH_DFLT 5 100 #define SI_RLP_DFLT 25 101 #define SI_RMP_DFLT 65 102 #define SI_LHP_DFLT 40 103 #define SI_LMP_DFLT 15 104 #define SI_TD_DFLT 0 105 #define SI_UTC_DFLT_00 0x24 106 #define SI_UTC_DFLT_01 0x22 107 #define SI_UTC_DFLT_02 0x22 108 #define SI_UTC_DFLT_03 0x22 109 #define SI_UTC_DFLT_04 0x22 110 #define SI_UTC_DFLT_05 0x22 111 #define SI_UTC_DFLT_06 0x22 112 #define SI_UTC_DFLT_07 0x22 113 #define SI_UTC_DFLT_08 0x22 114 #define SI_UTC_DFLT_09 0x22 115 #define SI_UTC_DFLT_10 0x22 116 #define SI_UTC_DFLT_11 0x22 117 #define SI_UTC_DFLT_12 0x22 118 #define SI_UTC_DFLT_13 0x22 119 #define SI_UTC_DFLT_14 0x22 120 #define SI_DTC_DFLT_00 0x24 121 #define SI_DTC_DFLT_01 0x22 122 #define SI_DTC_DFLT_02 0x22 123 #define SI_DTC_DFLT_03 0x22 124 #define SI_DTC_DFLT_04 0x22 125 #define SI_DTC_DFLT_05 0x22 126 #define SI_DTC_DFLT_06 0x22 127 #define SI_DTC_DFLT_07 0x22 128 #define SI_DTC_DFLT_08 0x22 129 #define SI_DTC_DFLT_09 0x22 130 #define SI_DTC_DFLT_10 0x22 131 #define SI_DTC_DFLT_11 0x22 132 #define SI_DTC_DFLT_12 0x22 133 #define SI_DTC_DFLT_13 0x22 134 #define SI_DTC_DFLT_14 0x22 135 #define SI_VRC_DFLT 0x0000C003 136 #define SI_VOLTAGERESPONSETIME_DFLT 1000 137 #define SI_BACKBIASRESPONSETIME_DFLT 1000 138 #define SI_VRU_DFLT 0x3 139 #define SI_SPLLSTEPTIME_DFLT 0x1000 140 #define SI_SPLLSTEPUNIT_DFLT 0x3 141 #define SI_TPU_DFLT 0 142 #define SI_TPC_DFLT 0x200 143 #define SI_SSTU_DFLT 0 144 #define SI_SST_DFLT 0x00C8 145 #define SI_GICST_DFLT 0x200 146 #define SI_FCT_DFLT 0x0400 147 #define SI_FCTU_DFLT 0 148 #define SI_CTXCGTT3DRPHC_DFLT 0x20 149 #define SI_CTXCGTT3DRSDC_DFLT 0x40 150 #define SI_VDDC3DOORPHC_DFLT 0x100 151 #define SI_VDDC3DOORSDC_DFLT 0x7 152 #define SI_VDDC3DOORSU_DFLT 0 153 #define SI_MPLLLOCKTIME_DFLT 100 154 #define SI_MPLLRESETTIME_DFLT 150 155 #define SI_VCOSTEPPCT_DFLT 20 156 #define SI_ENDINGVCOSTEPPCT_DFLT 5 157 #define SI_REFERENCEDIVIDER_DFLT 4 158 159 #define SI_PM_NUMBER_OF_TC 15 160 #define SI_PM_NUMBER_OF_SCLKS 20 161 #define SI_PM_NUMBER_OF_MCLKS 4 162 #define SI_PM_NUMBER_OF_VOLTAGE_LEVELS 4 163 #define SI_PM_NUMBER_OF_ACTIVITY_LEVELS 3 164 165 /* XXX are these ok? */ 166 #define SI_TEMP_RANGE_MIN (90 * 1000) 167 #define SI_TEMP_RANGE_MAX (120 * 1000) 168 169 #define FDO_PWM_MODE_STATIC 1 170 #define FDO_PWM_MODE_STATIC_RPM 5 171 172 enum ni_dc_cac_level 173 { 174 NISLANDS_DCCAC_LEVEL_0 = 0, 175 NISLANDS_DCCAC_LEVEL_1, 176 NISLANDS_DCCAC_LEVEL_2, 177 NISLANDS_DCCAC_LEVEL_3, 178 NISLANDS_DCCAC_LEVEL_4, 179 NISLANDS_DCCAC_LEVEL_5, 180 NISLANDS_DCCAC_LEVEL_6, 181 NISLANDS_DCCAC_LEVEL_7, 182 NISLANDS_DCCAC_MAX_LEVELS 183 }; 184 185 enum si_cac_config_reg_type 186 { 187 SISLANDS_CACCONFIG_MMR = 0, 188 SISLANDS_CACCONFIG_CGIND, 189 SISLANDS_CACCONFIG_MAX 190 }; 191 192 extern const struct amdgpu_ip_block_version si_smu_ip_block; 193 194 struct ni_leakage_coeffients 195 { 196 u32 at; 197 u32 bt; 198 u32 av; 199 u32 bv; 200 s32 t_slope; 201 s32 t_intercept; 202 u32 t_ref; 203 }; 204 205 struct SMC_NIslands_MCRegisterAddress 206 { 207 uint16_t s0; 208 uint16_t s1; 209 }; 210 211 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; 212 213 struct rv7xx_power_info { 214 /* flags */ 215 bool voltage_control; /* vddc */ 216 bool mvdd_control; 217 bool sclk_ss; 218 bool mclk_ss; 219 bool dynamic_ss; 220 bool thermal_protection; 221 /* voltage */ 222 u32 mvdd_split_frequency; 223 u16 max_vddc; 224 u16 max_vddc_in_table; 225 u16 min_vddc_in_table; 226 /* stored values */ 227 u16 acpi_vddc; 228 u32 ref_div; 229 u32 active_auto_throttle_sources; 230 u32 mclk_stutter_mode_threshold; 231 u32 mclk_strobe_mode_threshold; 232 u32 mclk_edc_enable_threshold; 233 u32 bsp; 234 u32 bsu; 235 u32 pbsp; 236 u32 pbsu; 237 u32 dsp; 238 u32 psp; 239 u32 asi; 240 u32 pasi; 241 u32 vrc; 242 }; 243 244 enum si_pcie_gen { 245 SI_PCIE_GEN1 = 0, 246 SI_PCIE_GEN2 = 1, 247 SI_PCIE_GEN3 = 2, 248 SI_PCIE_GEN_INVALID = 0xffff 249 }; 250 251 struct rv7xx_pl { 252 u32 sclk; 253 u32 mclk; 254 u16 vddc; 255 u16 vddci; /* eg+ only */ 256 u32 flags; 257 enum si_pcie_gen pcie_gen; /* si+ only */ 258 }; 259 260 struct si_ps { 261 u16 performance_level_count; 262 bool dc_compatible; 263 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 264 }; 265 266 struct evergreen_power_info { 267 /* must be first! */ 268 struct rv7xx_power_info rv7xx; 269 /* flags */ 270 bool vddci_control; 271 bool dynamic_ac_timing; 272 bool abm; 273 bool mcls; 274 bool pcie_performance_request; 275 bool sclk_deep_sleep; 276 bool smu_uvd_hs; 277 bool uvd_enabled; 278 /* stored values */ 279 u16 acpi_vddci; 280 u32 mclk_edc_wr_enable_threshold; 281 struct atom_voltage_table vddc_voltage_table; 282 struct atom_voltage_table vddci_voltage_table; 283 struct amdgpu_ps current_rps; 284 struct amdgpu_ps requested_rps; 285 }; 286 287 struct ni_power_info { 288 /* must be first! */ 289 struct evergreen_power_info eg; 290 u32 mclk_rtt_mode_threshold; 291 /* flags */ 292 bool support_cac_long_term_average; 293 bool cac_enabled; 294 bool cac_configuration_required; 295 bool driver_calculate_cac_leakage; 296 bool enable_power_containment; 297 bool enable_cac; 298 bool enable_sq_ramping; 299 struct si_ps current_ps; 300 struct si_ps requested_ps; 301 }; 302 303 struct si_cac_config_reg 304 { 305 u32 offset; 306 u32 mask; 307 u32 shift; 308 u32 value; 309 enum si_cac_config_reg_type type; 310 }; 311 312 struct si_powertune_data 313 { 314 u32 cac_window; 315 u32 l2_lta_window_size_default; 316 u8 lts_truncate_default; 317 u8 shift_n_default; 318 u8 operating_temp; 319 struct ni_leakage_coeffients leakage_coefficients; 320 u32 fixed_kt; 321 u32 lkge_lut_v0_percent; 322 u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS]; 323 bool enable_powertune_by_default; 324 }; 325 326 struct si_dyn_powertune_data 327 { 328 u32 cac_leakage; 329 s32 leakage_minimum_temperature; 330 u32 wintime; 331 u32 l2_lta_window_size; 332 u8 lts_truncate; 333 u8 shift_n; 334 u8 dc_pwr_value; 335 bool disable_uvd_powertune; 336 }; 337 338 struct si_dte_data 339 { 340 u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 341 u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 342 u32 k; 343 u32 t0; 344 u32 max_t; 345 u8 window_size; 346 u8 temp_select; 347 u8 dte_mode; 348 u8 tdep_count; 349 u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 350 u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 351 u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 352 u32 t_threshold; 353 bool enable_dte_by_default; 354 }; 355 356 struct si_clock_registers { 357 u32 cg_spll_func_cntl; 358 u32 cg_spll_func_cntl_2; 359 u32 cg_spll_func_cntl_3; 360 u32 cg_spll_func_cntl_4; 361 u32 cg_spll_spread_spectrum; 362 u32 cg_spll_spread_spectrum_2; 363 u32 dll_cntl; 364 u32 mclk_pwrmgt_cntl; 365 u32 mpll_ad_func_cntl; 366 u32 mpll_dq_func_cntl; 367 u32 mpll_func_cntl; 368 u32 mpll_func_cntl_1; 369 u32 mpll_func_cntl_2; 370 u32 mpll_ss1; 371 u32 mpll_ss2; 372 }; 373 374 struct si_mc_reg_entry { 375 u32 mclk_max; 376 u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 377 }; 378 379 struct si_mc_reg_table { 380 u8 last; 381 u8 num_entries; 382 u16 valid_flag; 383 struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 384 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 385 }; 386 387 struct si_leakage_voltage_entry 388 { 389 u16 voltage; 390 u16 leakage_index; 391 }; 392 393 struct si_leakage_voltage 394 { 395 u16 count; 396 struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT]; 397 }; 398 399 struct si_ulv_param { 400 bool supported; 401 u32 cg_ulv_control; 402 u32 cg_ulv_parameter; 403 u32 volt_change_delay; 404 struct rv7xx_pl pl; 405 bool one_pcie_lane_in_ulv; 406 }; 407 408 struct si_power_info { 409 /* must be first! */ 410 struct ni_power_info ni; 411 struct si_clock_registers clock_registers; 412 struct si_mc_reg_table mc_reg_table; 413 struct atom_voltage_table mvdd_voltage_table; 414 struct atom_voltage_table vddc_phase_shed_table; 415 struct si_leakage_voltage leakage_voltage; 416 u16 mvdd_bootup_value; 417 struct si_ulv_param ulv; 418 u32 max_cu; 419 /* pcie gen */ 420 enum si_pcie_gen force_pcie_gen; 421 enum si_pcie_gen boot_pcie_gen; 422 enum si_pcie_gen acpi_pcie_gen; 423 u32 sys_pcie_mask; 424 /* flags */ 425 bool enable_dte; 426 bool enable_ppm; 427 bool vddc_phase_shed_control; 428 bool pspp_notify_required; 429 bool sclk_deep_sleep_above_low; 430 bool voltage_control_svi2; 431 bool vddci_control_svi2; 432 /* smc offsets */ 433 u32 sram_end; 434 u32 state_table_start; 435 u32 soft_regs_start; 436 u32 mc_reg_table_start; 437 u32 arb_table_start; 438 u32 cac_table_start; 439 u32 dte_table_start; 440 u32 spll_table_start; 441 u32 papm_cfg_table_start; 442 u32 fan_table_start; 443 /* CAC stuff */ 444 const struct si_cac_config_reg *cac_weights; 445 const struct si_cac_config_reg *lcac_config; 446 const struct si_cac_config_reg *cac_override; 447 const struct si_powertune_data *powertune_data; 448 struct si_dyn_powertune_data dyn_powertune_data; 449 /* DTE stuff */ 450 struct si_dte_data dte_data; 451 /* scratch structs */ 452 SMC_SIslands_MCRegisters smc_mc_reg_table; 453 SISLANDS_SMC_STATETABLE smc_statetable; 454 PP_SIslands_PAPMParameters papm_parm; 455 /* SVI2 */ 456 u8 svd_gpio_id; 457 u8 svc_gpio_id; 458 /* fan control */ 459 bool fan_ctrl_is_in_default_mode; 460 u32 t_min; 461 u32 fan_ctrl_default_mode; 462 bool fan_is_controlled_by_smc; 463 }; 464 465 #endif 466