1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "amdgpu_atombios.h" 31 #include "amdgpu_dpm_internal.h" 32 #include "amd_pcie.h" 33 #include "atom.h" 34 #include "gfx_v6_0.h" 35 #include "r600_dpm.h" 36 #include "sid.h" 37 #include "si_dpm.h" 38 #include "../include/pptable.h" 39 #include <linux/math64.h> 40 #include <linux/seq_file.h> 41 #include <linux/firmware.h> 42 #include <legacy_dpm.h> 43 44 #include "bif/bif_3_0_d.h" 45 #include "bif/bif_3_0_sh_mask.h" 46 47 #include "dce/dce_6_0_d.h" 48 #include "dce/dce_6_0_sh_mask.h" 49 50 #include "gca/gfx_6_0_d.h" 51 #include "gca/gfx_6_0_sh_mask.h" 52 53 #include"gmc/gmc_6_0_d.h" 54 #include"gmc/gmc_6_0_sh_mask.h" 55 56 #include "smu/smu_6_0_d.h" 57 #include "smu/smu_6_0_sh_mask.h" 58 59 #define MC_CG_ARB_FREQ_F0 0x0a 60 #define MC_CG_ARB_FREQ_F1 0x0b 61 #define MC_CG_ARB_FREQ_F2 0x0c 62 #define MC_CG_ARB_FREQ_F3 0x0d 63 64 #define SMC_RAM_END 0x20000 65 66 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 67 68 69 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ 70 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 71 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 72 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 73 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 74 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 75 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 76 77 #define BIOS_SCRATCH_4 0x5cd 78 79 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin"); 80 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin"); 81 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin"); 82 MODULE_FIRMWARE("amdgpu/verde_smc.bin"); 83 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin"); 84 MODULE_FIRMWARE("amdgpu/oland_smc.bin"); 85 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin"); 86 MODULE_FIRMWARE("amdgpu/hainan_smc.bin"); 87 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin"); 88 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin"); 89 90 static const struct amd_pm_funcs si_dpm_funcs; 91 92 union power_info { 93 struct _ATOM_POWERPLAY_INFO info; 94 struct _ATOM_POWERPLAY_INFO_V2 info_2; 95 struct _ATOM_POWERPLAY_INFO_V3 info_3; 96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; 100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; 101 }; 102 103 union fan_info { 104 struct _ATOM_PPLIB_FANTABLE fan; 105 struct _ATOM_PPLIB_FANTABLE2 fan2; 106 struct _ATOM_PPLIB_FANTABLE3 fan3; 107 }; 108 109 union pplib_clock_info { 110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 114 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 115 }; 116 117 enum si_dpm_auto_throttle_src { 118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL, 119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL 120 }; 121 122 enum si_dpm_event_src { 123 SI_DPM_EVENT_SRC_ANALOG = 0, 124 SI_DPM_EVENT_SRC_EXTERNAL = 1, 125 SI_DPM_EVENT_SRC_DIGITAL = 2, 126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 128 }; 129 130 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] = 131 { 132 R600_UTC_DFLT_00, 133 R600_UTC_DFLT_01, 134 R600_UTC_DFLT_02, 135 R600_UTC_DFLT_03, 136 R600_UTC_DFLT_04, 137 R600_UTC_DFLT_05, 138 R600_UTC_DFLT_06, 139 R600_UTC_DFLT_07, 140 R600_UTC_DFLT_08, 141 R600_UTC_DFLT_09, 142 R600_UTC_DFLT_10, 143 R600_UTC_DFLT_11, 144 R600_UTC_DFLT_12, 145 R600_UTC_DFLT_13, 146 R600_UTC_DFLT_14, 147 }; 148 149 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = 150 { 151 R600_DTC_DFLT_00, 152 R600_DTC_DFLT_01, 153 R600_DTC_DFLT_02, 154 R600_DTC_DFLT_03, 155 R600_DTC_DFLT_04, 156 R600_DTC_DFLT_05, 157 R600_DTC_DFLT_06, 158 R600_DTC_DFLT_07, 159 R600_DTC_DFLT_08, 160 R600_DTC_DFLT_09, 161 R600_DTC_DFLT_10, 162 R600_DTC_DFLT_11, 163 R600_DTC_DFLT_12, 164 R600_DTC_DFLT_13, 165 R600_DTC_DFLT_14, 166 }; 167 168 static const struct si_cac_config_reg cac_weights_tahiti[] = 169 { 170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 230 { 0xFFFFFFFF } 231 }; 232 233 static const struct si_cac_config_reg lcac_tahiti[] = 234 { 235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 321 { 0xFFFFFFFF } 322 323 }; 324 325 static const struct si_cac_config_reg cac_override_tahiti[] = 326 { 327 { 0xFFFFFFFF } 328 }; 329 330 static const struct si_powertune_data powertune_data_tahiti = 331 { 332 ((1 << 16) | 27027), 333 6, 334 0, 335 4, 336 95, 337 { 338 0UL, 339 0UL, 340 4521550UL, 341 309631529UL, 342 -1270850L, 343 4513710L, 344 40 345 }, 346 595000000UL, 347 12, 348 { 349 0, 350 0, 351 0, 352 0, 353 0, 354 0, 355 0, 356 0 357 }, 358 true 359 }; 360 361 static const struct si_dte_data dte_data_tahiti = 362 { 363 { 1159409, 0, 0, 0, 0 }, 364 { 777, 0, 0, 0, 0 }, 365 2, 366 54000, 367 127000, 368 25, 369 2, 370 10, 371 13, 372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 375 85, 376 false 377 }; 378 379 static const struct si_dte_data dte_data_tahiti_pro = 380 { 381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 382 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 383 5, 384 45000, 385 100, 386 0xA, 387 1, 388 0, 389 0x10, 390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 393 90, 394 true 395 }; 396 397 static const struct si_dte_data dte_data_new_zealand = 398 { 399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 401 0x5, 402 0xAFC8, 403 0x69, 404 0x32, 405 1, 406 0, 407 0x10, 408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 411 85, 412 true 413 }; 414 415 static const struct si_dte_data dte_data_aruba_pro = 416 { 417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 418 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 419 5, 420 45000, 421 100, 422 0xA, 423 1, 424 0, 425 0x10, 426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 429 90, 430 true 431 }; 432 433 static const struct si_dte_data dte_data_malta = 434 { 435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 436 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 437 5, 438 45000, 439 100, 440 0xA, 441 1, 442 0, 443 0x10, 444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 447 90, 448 true 449 }; 450 451 static const struct si_cac_config_reg cac_weights_pitcairn[] = 452 { 453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 513 { 0xFFFFFFFF } 514 }; 515 516 static const struct si_cac_config_reg lcac_pitcairn[] = 517 { 518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 604 { 0xFFFFFFFF } 605 }; 606 607 static const struct si_cac_config_reg cac_override_pitcairn[] = 608 { 609 { 0xFFFFFFFF } 610 }; 611 612 static const struct si_powertune_data powertune_data_pitcairn = 613 { 614 ((1 << 16) | 27027), 615 5, 616 0, 617 6, 618 100, 619 { 620 51600000UL, 621 1800000UL, 622 7194395UL, 623 309631529UL, 624 -1270850L, 625 4513710L, 626 100 627 }, 628 117830498UL, 629 12, 630 { 631 0, 632 0, 633 0, 634 0, 635 0, 636 0, 637 0, 638 0 639 }, 640 true 641 }; 642 643 static const struct si_dte_data dte_data_pitcairn = 644 { 645 { 0, 0, 0, 0, 0 }, 646 { 0, 0, 0, 0, 0 }, 647 0, 648 0, 649 0, 650 0, 651 0, 652 0, 653 0, 654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 657 0, 658 false 659 }; 660 661 static const struct si_dte_data dte_data_curacao_xt = 662 { 663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 664 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 665 5, 666 45000, 667 100, 668 0xA, 669 1, 670 0, 671 0x10, 672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 675 90, 676 true 677 }; 678 679 static const struct si_dte_data dte_data_curacao_pro = 680 { 681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 682 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 683 5, 684 45000, 685 100, 686 0xA, 687 1, 688 0, 689 0x10, 690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 693 90, 694 true 695 }; 696 697 static const struct si_dte_data dte_data_neptune_xt = 698 { 699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 700 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 701 5, 702 45000, 703 100, 704 0xA, 705 1, 706 0, 707 0x10, 708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 711 90, 712 true 713 }; 714 715 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 716 { 717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 777 { 0xFFFFFFFF } 778 }; 779 780 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 781 { 782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 842 { 0xFFFFFFFF } 843 }; 844 845 static const struct si_cac_config_reg cac_weights_heathrow[] = 846 { 847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 907 { 0xFFFFFFFF } 908 }; 909 910 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 911 { 912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 972 { 0xFFFFFFFF } 973 }; 974 975 static const struct si_cac_config_reg cac_weights_cape_verde[] = 976 { 977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1037 { 0xFFFFFFFF } 1038 }; 1039 1040 static const struct si_cac_config_reg lcac_cape_verde[] = 1041 { 1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1096 { 0xFFFFFFFF } 1097 }; 1098 1099 static const struct si_cac_config_reg cac_override_cape_verde[] = 1100 { 1101 { 0xFFFFFFFF } 1102 }; 1103 1104 static const struct si_powertune_data powertune_data_cape_verde = 1105 { 1106 ((1 << 16) | 0x6993), 1107 5, 1108 0, 1109 7, 1110 105, 1111 { 1112 0UL, 1113 0UL, 1114 7194395UL, 1115 309631529UL, 1116 -1270850L, 1117 4513710L, 1118 100 1119 }, 1120 117830498UL, 1121 12, 1122 { 1123 0, 1124 0, 1125 0, 1126 0, 1127 0, 1128 0, 1129 0, 1130 0 1131 }, 1132 true 1133 }; 1134 1135 static const struct si_dte_data dte_data_cape_verde = 1136 { 1137 { 0, 0, 0, 0, 0 }, 1138 { 0, 0, 0, 0, 0 }, 1139 0, 1140 0, 1141 0, 1142 0, 1143 0, 1144 0, 1145 0, 1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1149 0, 1150 false 1151 }; 1152 1153 static const struct si_dte_data dte_data_venus_xtx = 1154 { 1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1157 5, 1158 55000, 1159 0x69, 1160 0xA, 1161 1, 1162 0, 1163 0x3, 1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1167 90, 1168 true 1169 }; 1170 1171 static const struct si_dte_data dte_data_venus_xt = 1172 { 1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1175 5, 1176 55000, 1177 0x69, 1178 0xA, 1179 1, 1180 0, 1181 0x3, 1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1185 90, 1186 true 1187 }; 1188 1189 static const struct si_dte_data dte_data_venus_pro = 1190 { 1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1193 5, 1194 55000, 1195 0x69, 1196 0xA, 1197 1, 1198 0, 1199 0x3, 1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1203 90, 1204 true 1205 }; 1206 1207 static const struct si_cac_config_reg cac_weights_oland[] = 1208 { 1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1269 { 0xFFFFFFFF } 1270 }; 1271 1272 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1273 { 1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1334 { 0xFFFFFFFF } 1335 }; 1336 1337 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1338 { 1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1399 { 0xFFFFFFFF } 1400 }; 1401 1402 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1403 { 1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1464 { 0xFFFFFFFF } 1465 }; 1466 1467 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1468 { 1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1529 { 0xFFFFFFFF } 1530 }; 1531 1532 static const struct si_cac_config_reg lcac_oland[] = 1533 { 1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1576 { 0xFFFFFFFF } 1577 }; 1578 1579 static const struct si_cac_config_reg lcac_mars_pro[] = 1580 { 1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1623 { 0xFFFFFFFF } 1624 }; 1625 1626 static const struct si_cac_config_reg cac_override_oland[] = 1627 { 1628 { 0xFFFFFFFF } 1629 }; 1630 1631 static const struct si_powertune_data powertune_data_oland = 1632 { 1633 ((1 << 16) | 0x6993), 1634 5, 1635 0, 1636 7, 1637 105, 1638 { 1639 0UL, 1640 0UL, 1641 7194395UL, 1642 309631529UL, 1643 -1270850L, 1644 4513710L, 1645 100 1646 }, 1647 117830498UL, 1648 12, 1649 { 1650 0, 1651 0, 1652 0, 1653 0, 1654 0, 1655 0, 1656 0, 1657 0 1658 }, 1659 true 1660 }; 1661 1662 static const struct si_powertune_data powertune_data_mars_pro = 1663 { 1664 ((1 << 16) | 0x6993), 1665 5, 1666 0, 1667 7, 1668 105, 1669 { 1670 0UL, 1671 0UL, 1672 7194395UL, 1673 309631529UL, 1674 -1270850L, 1675 4513710L, 1676 100 1677 }, 1678 117830498UL, 1679 12, 1680 { 1681 0, 1682 0, 1683 0, 1684 0, 1685 0, 1686 0, 1687 0, 1688 0 1689 }, 1690 true 1691 }; 1692 1693 static const struct si_dte_data dte_data_oland = 1694 { 1695 { 0, 0, 0, 0, 0 }, 1696 { 0, 0, 0, 0, 0 }, 1697 0, 1698 0, 1699 0, 1700 0, 1701 0, 1702 0, 1703 0, 1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1707 0, 1708 false 1709 }; 1710 1711 static const struct si_dte_data dte_data_mars_pro = 1712 { 1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1714 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1715 5, 1716 55000, 1717 105, 1718 0xA, 1719 1, 1720 0, 1721 0x10, 1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1725 90, 1726 true 1727 }; 1728 1729 static const struct si_dte_data dte_data_sun_xt = 1730 { 1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1732 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1733 5, 1734 55000, 1735 105, 1736 0xA, 1737 1, 1738 0, 1739 0x10, 1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1743 90, 1744 true 1745 }; 1746 1747 1748 static const struct si_cac_config_reg cac_weights_hainan[] = 1749 { 1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1810 { 0xFFFFFFFF } 1811 }; 1812 1813 static const struct si_powertune_data powertune_data_hainan = 1814 { 1815 ((1 << 16) | 0x6993), 1816 5, 1817 0, 1818 9, 1819 105, 1820 { 1821 0UL, 1822 0UL, 1823 7194395UL, 1824 309631529UL, 1825 -1270850L, 1826 4513710L, 1827 100 1828 }, 1829 117830498UL, 1830 12, 1831 { 1832 0, 1833 0, 1834 0, 1835 0, 1836 0, 1837 0, 1838 0, 1839 0 1840 }, 1841 true 1842 }; 1843 1844 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev); 1845 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev); 1846 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev); 1847 static struct si_ps *si_get_ps(struct amdgpu_ps *rps); 1848 1849 static int si_populate_voltage_value(struct amdgpu_device *adev, 1850 const struct atom_voltage_table *table, 1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1852 static int si_get_std_voltage_value(struct amdgpu_device *adev, 1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1854 u16 *std_voltage); 1855 static int si_write_smc_soft_register(struct amdgpu_device *adev, 1856 u16 reg_offset, u32 value); 1857 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 1858 struct rv7xx_pl *pl, 1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1860 static int si_calculate_sclk_params(struct amdgpu_device *adev, 1861 u32 engine_clock, 1862 SISLANDS_SMC_SCLK_VALUE *sclk); 1863 1864 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); 1865 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); 1866 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); 1867 1868 static struct si_power_info *si_get_pi(struct amdgpu_device *adev) 1869 { 1870 struct si_power_info *pi = adev->pm.dpm.priv; 1871 return pi; 1872 } 1873 1874 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1875 u16 v, s32 t, u32 ileakage, u32 *leakage) 1876 { 1877 s64 kt, kv, leakage_w, i_leakage, vddc; 1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1879 s64 tmp; 1880 1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1882 vddc = div64_s64(drm_int2fixp(v), 1000); 1883 temperature = div64_s64(drm_int2fixp(t), 1000); 1884 1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1889 t_ref = drm_int2fixp(coeff->t_ref); 1890 1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1895 1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1897 1898 *leakage = drm_fixp2int(leakage_w * 1000); 1899 } 1900 1901 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, 1902 const struct ni_leakage_coeffients *coeff, 1903 u16 v, 1904 s32 t, 1905 u32 i_leakage, 1906 u32 *leakage) 1907 { 1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1909 } 1910 1911 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1912 const u32 fixed_kt, u16 v, 1913 u32 ileakage, u32 *leakage) 1914 { 1915 s64 kt, kv, leakage_w, i_leakage, vddc; 1916 1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1918 vddc = div64_s64(drm_int2fixp(v), 1000); 1919 1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1923 1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1925 1926 *leakage = drm_fixp2int(leakage_w * 1000); 1927 } 1928 1929 static void si_calculate_leakage_for_v(struct amdgpu_device *adev, 1930 const struct ni_leakage_coeffients *coeff, 1931 const u32 fixed_kt, 1932 u16 v, 1933 u32 i_leakage, 1934 u32 *leakage) 1935 { 1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1937 } 1938 1939 1940 static void si_update_dte_from_pl2(struct amdgpu_device *adev, 1941 struct si_dte_data *dte_data) 1942 { 1943 u32 p_limit1 = adev->pm.dpm.tdp_limit; 1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; 1945 u32 k = dte_data->k; 1946 u32 t_max = dte_data->max_t; 1947 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1948 u32 t_0 = dte_data->t0; 1949 u32 i; 1950 1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1952 dte_data->tdep_count = 3; 1953 1954 for (i = 0; i < k; i++) { 1955 dte_data->r[i] = 1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1957 (p_limit2 * (u32)100); 1958 } 1959 1960 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1961 1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1963 dte_data->tdep_r[i] = dte_data->r[4]; 1964 } 1965 } else { 1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1967 } 1968 } 1969 1970 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev) 1971 { 1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv; 1973 1974 return pi; 1975 } 1976 1977 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev) 1978 { 1979 struct ni_power_info *pi = adev->pm.dpm.priv; 1980 1981 return pi; 1982 } 1983 1984 static struct si_ps *si_get_ps(struct amdgpu_ps *aps) 1985 { 1986 struct si_ps *ps = aps->ps_priv; 1987 1988 return ps; 1989 } 1990 1991 static void si_initialize_powertune_defaults(struct amdgpu_device *adev) 1992 { 1993 struct ni_power_info *ni_pi = ni_get_pi(adev); 1994 struct si_power_info *si_pi = si_get_pi(adev); 1995 bool update_dte_from_pl2 = false; 1996 1997 if (adev->asic_type == CHIP_TAHITI) { 1998 si_pi->cac_weights = cac_weights_tahiti; 1999 si_pi->lcac_config = lcac_tahiti; 2000 si_pi->cac_override = cac_override_tahiti; 2001 si_pi->powertune_data = &powertune_data_tahiti; 2002 si_pi->dte_data = dte_data_tahiti; 2003 2004 switch (adev->pdev->device) { 2005 case 0x6798: 2006 si_pi->dte_data.enable_dte_by_default = true; 2007 break; 2008 case 0x6799: 2009 si_pi->dte_data = dte_data_new_zealand; 2010 break; 2011 case 0x6790: 2012 case 0x6791: 2013 case 0x6792: 2014 case 0x679E: 2015 si_pi->dte_data = dte_data_aruba_pro; 2016 update_dte_from_pl2 = true; 2017 break; 2018 case 0x679B: 2019 si_pi->dte_data = dte_data_malta; 2020 update_dte_from_pl2 = true; 2021 break; 2022 case 0x679A: 2023 si_pi->dte_data = dte_data_tahiti_pro; 2024 update_dte_from_pl2 = true; 2025 break; 2026 default: 2027 if (si_pi->dte_data.enable_dte_by_default == true) 2028 DRM_ERROR("DTE is not enabled!\n"); 2029 break; 2030 } 2031 } else if (adev->asic_type == CHIP_PITCAIRN) { 2032 si_pi->cac_weights = cac_weights_pitcairn; 2033 si_pi->lcac_config = lcac_pitcairn; 2034 si_pi->cac_override = cac_override_pitcairn; 2035 si_pi->powertune_data = &powertune_data_pitcairn; 2036 2037 switch (adev->pdev->device) { 2038 case 0x6810: 2039 case 0x6818: 2040 si_pi->dte_data = dte_data_curacao_xt; 2041 update_dte_from_pl2 = true; 2042 break; 2043 case 0x6819: 2044 case 0x6811: 2045 si_pi->dte_data = dte_data_curacao_pro; 2046 update_dte_from_pl2 = true; 2047 break; 2048 case 0x6800: 2049 case 0x6806: 2050 si_pi->dte_data = dte_data_neptune_xt; 2051 update_dte_from_pl2 = true; 2052 break; 2053 default: 2054 si_pi->dte_data = dte_data_pitcairn; 2055 break; 2056 } 2057 } else if (adev->asic_type == CHIP_VERDE) { 2058 si_pi->lcac_config = lcac_cape_verde; 2059 si_pi->cac_override = cac_override_cape_verde; 2060 si_pi->powertune_data = &powertune_data_cape_verde; 2061 2062 switch (adev->pdev->device) { 2063 case 0x683B: 2064 case 0x683F: 2065 case 0x6829: 2066 case 0x6835: 2067 si_pi->cac_weights = cac_weights_cape_verde_pro; 2068 si_pi->dte_data = dte_data_cape_verde; 2069 break; 2070 case 0x682C: 2071 si_pi->cac_weights = cac_weights_cape_verde_pro; 2072 si_pi->dte_data = dte_data_sun_xt; 2073 update_dte_from_pl2 = true; 2074 break; 2075 case 0x6825: 2076 case 0x6827: 2077 si_pi->cac_weights = cac_weights_heathrow; 2078 si_pi->dte_data = dte_data_cape_verde; 2079 break; 2080 case 0x6824: 2081 case 0x682D: 2082 si_pi->cac_weights = cac_weights_chelsea_xt; 2083 si_pi->dte_data = dte_data_cape_verde; 2084 break; 2085 case 0x682F: 2086 si_pi->cac_weights = cac_weights_chelsea_pro; 2087 si_pi->dte_data = dte_data_cape_verde; 2088 break; 2089 case 0x6820: 2090 si_pi->cac_weights = cac_weights_heathrow; 2091 si_pi->dte_data = dte_data_venus_xtx; 2092 break; 2093 case 0x6821: 2094 si_pi->cac_weights = cac_weights_heathrow; 2095 si_pi->dte_data = dte_data_venus_xt; 2096 break; 2097 case 0x6823: 2098 case 0x682B: 2099 case 0x6822: 2100 case 0x682A: 2101 si_pi->cac_weights = cac_weights_chelsea_pro; 2102 si_pi->dte_data = dte_data_venus_pro; 2103 break; 2104 default: 2105 si_pi->cac_weights = cac_weights_cape_verde; 2106 si_pi->dte_data = dte_data_cape_verde; 2107 break; 2108 } 2109 } else if (adev->asic_type == CHIP_OLAND) { 2110 si_pi->lcac_config = lcac_mars_pro; 2111 si_pi->cac_override = cac_override_oland; 2112 si_pi->powertune_data = &powertune_data_mars_pro; 2113 si_pi->dte_data = dte_data_mars_pro; 2114 2115 switch (adev->pdev->device) { 2116 case 0x6601: 2117 case 0x6621: 2118 case 0x6603: 2119 case 0x6605: 2120 si_pi->cac_weights = cac_weights_mars_pro; 2121 update_dte_from_pl2 = true; 2122 break; 2123 case 0x6600: 2124 case 0x6606: 2125 case 0x6620: 2126 case 0x6604: 2127 si_pi->cac_weights = cac_weights_mars_xt; 2128 update_dte_from_pl2 = true; 2129 break; 2130 case 0x6611: 2131 case 0x6613: 2132 case 0x6608: 2133 si_pi->cac_weights = cac_weights_oland_pro; 2134 update_dte_from_pl2 = true; 2135 break; 2136 case 0x6610: 2137 si_pi->cac_weights = cac_weights_oland_xt; 2138 update_dte_from_pl2 = true; 2139 break; 2140 default: 2141 si_pi->cac_weights = cac_weights_oland; 2142 si_pi->lcac_config = lcac_oland; 2143 si_pi->cac_override = cac_override_oland; 2144 si_pi->powertune_data = &powertune_data_oland; 2145 si_pi->dte_data = dte_data_oland; 2146 break; 2147 } 2148 } else if (adev->asic_type == CHIP_HAINAN) { 2149 si_pi->cac_weights = cac_weights_hainan; 2150 si_pi->lcac_config = lcac_oland; 2151 si_pi->cac_override = cac_override_oland; 2152 si_pi->powertune_data = &powertune_data_hainan; 2153 si_pi->dte_data = dte_data_sun_xt; 2154 update_dte_from_pl2 = true; 2155 } else { 2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2157 return; 2158 } 2159 2160 ni_pi->enable_power_containment = false; 2161 ni_pi->enable_cac = false; 2162 ni_pi->enable_sq_ramping = false; 2163 si_pi->enable_dte = false; 2164 2165 if (si_pi->powertune_data->enable_powertune_by_default) { 2166 ni_pi->enable_power_containment = true; 2167 ni_pi->enable_cac = true; 2168 if (si_pi->dte_data.enable_dte_by_default) { 2169 si_pi->enable_dte = true; 2170 if (update_dte_from_pl2) 2171 si_update_dte_from_pl2(adev, &si_pi->dte_data); 2172 2173 } 2174 ni_pi->enable_sq_ramping = true; 2175 } 2176 2177 ni_pi->driver_calculate_cac_leakage = true; 2178 ni_pi->cac_configuration_required = true; 2179 2180 if (ni_pi->cac_configuration_required) { 2181 ni_pi->support_cac_long_term_average = true; 2182 si_pi->dyn_powertune_data.l2_lta_window_size = 2183 si_pi->powertune_data->l2_lta_window_size_default; 2184 si_pi->dyn_powertune_data.lts_truncate = 2185 si_pi->powertune_data->lts_truncate_default; 2186 } else { 2187 ni_pi->support_cac_long_term_average = false; 2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2189 si_pi->dyn_powertune_data.lts_truncate = 0; 2190 } 2191 2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2193 } 2194 2195 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) 2196 { 2197 return 1; 2198 } 2199 2200 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev) 2201 { 2202 u32 xclk; 2203 u32 wintime; 2204 u32 cac_window; 2205 u32 cac_window_size; 2206 2207 xclk = amdgpu_asic_get_xclk(adev); 2208 2209 if (xclk == 0) 2210 return 0; 2211 2212 cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK; 2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2214 2215 wintime = (cac_window_size * 100) / xclk; 2216 2217 return wintime; 2218 } 2219 2220 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2221 { 2222 return power_in_watts; 2223 } 2224 2225 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, 2226 bool adjust_polarity, 2227 u32 tdp_adjustment, 2228 u32 *tdp_limit, 2229 u32 *near_tdp_limit) 2230 { 2231 u32 adjustment_delta, max_tdp_limit; 2232 2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) 2234 return -EINVAL; 2235 2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; 2237 2238 if (adjust_polarity) { 2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); 2241 } else { 2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; 2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) 2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2246 else 2247 *near_tdp_limit = 0; 2248 } 2249 2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2251 return -EINVAL; 2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2253 return -EINVAL; 2254 2255 return 0; 2256 } 2257 2258 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, 2259 struct amdgpu_ps *amdgpu_state) 2260 { 2261 struct ni_power_info *ni_pi = ni_get_pi(adev); 2262 struct si_power_info *si_pi = si_get_pi(adev); 2263 2264 if (ni_pi->enable_power_containment) { 2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2266 PP_SIslands_PAPMParameters *papm_parm; 2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; 2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2269 u32 tdp_limit; 2270 u32 near_tdp_limit; 2271 int ret; 2272 2273 if (scaling_factor == 0) 2274 return -EINVAL; 2275 2276 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2277 2278 ret = si_calculate_adjusted_tdp_limits(adev, 2279 false, /* ??? */ 2280 adev->pm.dpm.tdp_adjustment, 2281 &tdp_limit, 2282 &near_tdp_limit); 2283 if (ret) 2284 return ret; 2285 2286 smc_table->dpm2Params.TDPLimit = 2287 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2288 smc_table->dpm2Params.NearTDPLimit = 2289 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2290 smc_table->dpm2Params.SafePowerLimit = 2291 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2292 2293 ret = amdgpu_si_copy_bytes_to_smc(adev, 2294 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2295 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2296 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2297 sizeof(u32) * 3, 2298 si_pi->sram_end); 2299 if (ret) 2300 return ret; 2301 2302 if (si_pi->enable_ppm) { 2303 papm_parm = &si_pi->papm_parm; 2304 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2305 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2306 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2307 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2308 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2309 papm_parm->PlatformPowerLimit = 0xffffffff; 2310 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2311 2312 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2313 (u8 *)papm_parm, 2314 sizeof(PP_SIslands_PAPMParameters), 2315 si_pi->sram_end); 2316 if (ret) 2317 return ret; 2318 } 2319 } 2320 return 0; 2321 } 2322 2323 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, 2324 struct amdgpu_ps *amdgpu_state) 2325 { 2326 struct ni_power_info *ni_pi = ni_get_pi(adev); 2327 struct si_power_info *si_pi = si_get_pi(adev); 2328 2329 if (ni_pi->enable_power_containment) { 2330 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2331 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2332 int ret; 2333 2334 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2335 2336 smc_table->dpm2Params.NearTDPLimit = 2337 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2338 smc_table->dpm2Params.SafePowerLimit = 2339 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2340 2341 ret = amdgpu_si_copy_bytes_to_smc(adev, 2342 (si_pi->state_table_start + 2343 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2344 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2345 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2346 sizeof(u32) * 2, 2347 si_pi->sram_end); 2348 if (ret) 2349 return ret; 2350 } 2351 2352 return 0; 2353 } 2354 2355 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, 2356 const u16 prev_std_vddc, 2357 const u16 curr_std_vddc) 2358 { 2359 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2360 u64 prev_vddc = (u64)prev_std_vddc; 2361 u64 curr_vddc = (u64)curr_std_vddc; 2362 u64 pwr_efficiency_ratio, n, d; 2363 2364 if ((prev_vddc == 0) || (curr_vddc == 0)) 2365 return 0; 2366 2367 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2368 d = prev_vddc * prev_vddc; 2369 pwr_efficiency_ratio = div64_u64(n, d); 2370 2371 if (pwr_efficiency_ratio > (u64)0xFFFF) 2372 return 0; 2373 2374 return (u16)pwr_efficiency_ratio; 2375 } 2376 2377 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev, 2378 struct amdgpu_ps *amdgpu_state) 2379 { 2380 struct si_power_info *si_pi = si_get_pi(adev); 2381 2382 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2383 amdgpu_state->vclk && amdgpu_state->dclk) 2384 return true; 2385 2386 return false; 2387 } 2388 2389 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev) 2390 { 2391 struct evergreen_power_info *pi = adev->pm.dpm.priv; 2392 2393 return pi; 2394 } 2395 2396 static int si_populate_power_containment_values(struct amdgpu_device *adev, 2397 struct amdgpu_ps *amdgpu_state, 2398 SISLANDS_SMC_SWSTATE *smc_state) 2399 { 2400 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 2401 struct ni_power_info *ni_pi = ni_get_pi(adev); 2402 struct si_ps *state = si_get_ps(amdgpu_state); 2403 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2404 u32 prev_sclk; 2405 u32 max_sclk; 2406 u32 min_sclk; 2407 u16 prev_std_vddc; 2408 u16 curr_std_vddc; 2409 int i; 2410 u16 pwr_efficiency_ratio; 2411 u8 max_ps_percent; 2412 bool disable_uvd_power_tune; 2413 int ret; 2414 2415 if (ni_pi->enable_power_containment == false) 2416 return 0; 2417 2418 if (state->performance_level_count == 0) 2419 return -EINVAL; 2420 2421 if (smc_state->levelCount != state->performance_level_count) 2422 return -EINVAL; 2423 2424 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state); 2425 2426 smc_state->levels[0].dpm2.MaxPS = 0; 2427 smc_state->levels[0].dpm2.NearTDPDec = 0; 2428 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2429 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2430 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2431 2432 for (i = 1; i < state->performance_level_count; i++) { 2433 prev_sclk = state->performance_levels[i-1].sclk; 2434 max_sclk = state->performance_levels[i].sclk; 2435 if (i == 1) 2436 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2437 else 2438 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2439 2440 if (prev_sclk > max_sclk) 2441 return -EINVAL; 2442 2443 if ((max_ps_percent == 0) || 2444 (prev_sclk == max_sclk) || 2445 disable_uvd_power_tune) 2446 min_sclk = max_sclk; 2447 else if (i == 1) 2448 min_sclk = prev_sclk; 2449 else 2450 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2451 2452 if (min_sclk < state->performance_levels[0].sclk) 2453 min_sclk = state->performance_levels[0].sclk; 2454 2455 if (min_sclk == 0) 2456 return -EINVAL; 2457 2458 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2459 state->performance_levels[i-1].vddc, &vddc); 2460 if (ret) 2461 return ret; 2462 2463 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc); 2464 if (ret) 2465 return ret; 2466 2467 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2468 state->performance_levels[i].vddc, &vddc); 2469 if (ret) 2470 return ret; 2471 2472 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc); 2473 if (ret) 2474 return ret; 2475 2476 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev, 2477 prev_std_vddc, curr_std_vddc); 2478 2479 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2480 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2481 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2482 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2483 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2484 } 2485 2486 return 0; 2487 } 2488 2489 static int si_populate_sq_ramping_values(struct amdgpu_device *adev, 2490 struct amdgpu_ps *amdgpu_state, 2491 SISLANDS_SMC_SWSTATE *smc_state) 2492 { 2493 struct ni_power_info *ni_pi = ni_get_pi(adev); 2494 struct si_ps *state = si_get_ps(amdgpu_state); 2495 u32 sq_power_throttle, sq_power_throttle2; 2496 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2497 int i; 2498 2499 if (state->performance_level_count == 0) 2500 return -EINVAL; 2501 2502 if (smc_state->levelCount != state->performance_level_count) 2503 return -EINVAL; 2504 2505 if (adev->pm.dpm.sq_ramping_threshold == 0) 2506 return -EINVAL; 2507 2508 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (SQ_POWER_THROTTLE__MAX_POWER_MASK >> SQ_POWER_THROTTLE__MAX_POWER__SHIFT)) 2509 enable_sq_ramping = false; 2510 2511 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (SQ_POWER_THROTTLE__MIN_POWER_MASK >> SQ_POWER_THROTTLE__MIN_POWER__SHIFT)) 2512 enable_sq_ramping = false; 2513 2514 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK >> SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT)) 2515 enable_sq_ramping = false; 2516 2517 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK >> SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT)) 2518 enable_sq_ramping = false; 2519 2520 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK >> SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT)) 2521 enable_sq_ramping = false; 2522 2523 for (i = 0; i < state->performance_level_count; i++) { 2524 sq_power_throttle = 0; 2525 sq_power_throttle2 = 0; 2526 2527 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && 2528 enable_sq_ramping) { 2529 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER << SQ_POWER_THROTTLE__MAX_POWER__SHIFT; 2530 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MIN_POWER << SQ_POWER_THROTTLE__MIN_POWER__SHIFT; 2531 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA << SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT; 2532 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_STI_SIZE << SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT; 2533 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_LTI_RATIO << SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT; 2534 } else { 2535 sq_power_throttle |= SQ_POWER_THROTTLE__MAX_POWER_MASK | 2536 SQ_POWER_THROTTLE__MIN_POWER_MASK; 2537 sq_power_throttle2 |= SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | 2538 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | 2539 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 2540 } 2541 2542 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2543 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2544 } 2545 2546 return 0; 2547 } 2548 2549 static int si_enable_power_containment(struct amdgpu_device *adev, 2550 struct amdgpu_ps *amdgpu_new_state, 2551 bool enable) 2552 { 2553 struct ni_power_info *ni_pi = ni_get_pi(adev); 2554 PPSMC_Result smc_result; 2555 int ret = 0; 2556 2557 if (ni_pi->enable_power_containment) { 2558 if (enable) { 2559 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2560 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2561 if (smc_result != PPSMC_Result_OK) { 2562 ret = -EINVAL; 2563 ni_pi->pc_enabled = false; 2564 } else { 2565 ni_pi->pc_enabled = true; 2566 } 2567 } 2568 } else { 2569 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2570 if (smc_result != PPSMC_Result_OK) 2571 ret = -EINVAL; 2572 ni_pi->pc_enabled = false; 2573 } 2574 } 2575 2576 return ret; 2577 } 2578 2579 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) 2580 { 2581 struct si_power_info *si_pi = si_get_pi(adev); 2582 int ret = 0; 2583 struct si_dte_data *dte_data = &si_pi->dte_data; 2584 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2585 u32 table_size; 2586 u8 tdep_count; 2587 u32 i; 2588 2589 if (dte_data == NULL) 2590 si_pi->enable_dte = false; 2591 2592 if (si_pi->enable_dte == false) 2593 return 0; 2594 2595 if (dte_data->k <= 0) 2596 return -EINVAL; 2597 2598 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2599 if (dte_tables == NULL) { 2600 si_pi->enable_dte = false; 2601 return -ENOMEM; 2602 } 2603 2604 table_size = dte_data->k; 2605 2606 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2607 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2608 2609 tdep_count = dte_data->tdep_count; 2610 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2611 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2612 2613 dte_tables->K = cpu_to_be32(table_size); 2614 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2615 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2616 dte_tables->WindowSize = dte_data->window_size; 2617 dte_tables->temp_select = dte_data->temp_select; 2618 dte_tables->DTE_mode = dte_data->dte_mode; 2619 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2620 2621 if (tdep_count > 0) 2622 table_size--; 2623 2624 for (i = 0; i < table_size; i++) { 2625 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2626 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2627 } 2628 2629 dte_tables->Tdep_count = tdep_count; 2630 2631 for (i = 0; i < (u32)tdep_count; i++) { 2632 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2633 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2634 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2635 } 2636 2637 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, 2638 (u8 *)dte_tables, 2639 sizeof(Smc_SIslands_DTE_Configuration), 2640 si_pi->sram_end); 2641 kfree(dte_tables); 2642 2643 return ret; 2644 } 2645 2646 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, 2647 u16 *max, u16 *min) 2648 { 2649 struct si_power_info *si_pi = si_get_pi(adev); 2650 struct amdgpu_cac_leakage_table *table = 2651 &adev->pm.dpm.dyn_state.cac_leakage_table; 2652 u32 i; 2653 u32 v0_loadline; 2654 2655 if (table == NULL) 2656 return -EINVAL; 2657 2658 *max = 0; 2659 *min = 0xFFFF; 2660 2661 for (i = 0; i < table->count; i++) { 2662 if (table->entries[i].vddc > *max) 2663 *max = table->entries[i].vddc; 2664 if (table->entries[i].vddc < *min) 2665 *min = table->entries[i].vddc; 2666 } 2667 2668 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2669 return -EINVAL; 2670 2671 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2672 2673 if (v0_loadline > 0xFFFFUL) 2674 return -EINVAL; 2675 2676 *min = (u16)v0_loadline; 2677 2678 if ((*min > *max) || (*max == 0) || (*min == 0)) 2679 return -EINVAL; 2680 2681 return 0; 2682 } 2683 2684 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2685 { 2686 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2687 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2688 } 2689 2690 static int si_init_dte_leakage_table(struct amdgpu_device *adev, 2691 PP_SIslands_CacConfig *cac_tables, 2692 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2693 u16 t0, u16 t_step) 2694 { 2695 struct si_power_info *si_pi = si_get_pi(adev); 2696 u32 leakage; 2697 unsigned int i, j; 2698 s32 t; 2699 u32 smc_leakage; 2700 u32 scaling_factor; 2701 u16 voltage; 2702 2703 scaling_factor = si_get_smc_power_scaling_factor(adev); 2704 2705 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2706 t = (1000 * (i * t_step + t0)); 2707 2708 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2709 voltage = vddc_max - (vddc_step * j); 2710 2711 si_calculate_leakage_for_v_and_t(adev, 2712 &si_pi->powertune_data->leakage_coefficients, 2713 voltage, 2714 t, 2715 si_pi->dyn_powertune_data.cac_leakage, 2716 &leakage); 2717 2718 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2719 2720 if (smc_leakage > 0xFFFF) 2721 smc_leakage = 0xFFFF; 2722 2723 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2724 cpu_to_be16((u16)smc_leakage); 2725 } 2726 } 2727 return 0; 2728 } 2729 2730 static int si_init_simplified_leakage_table(struct amdgpu_device *adev, 2731 PP_SIslands_CacConfig *cac_tables, 2732 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2733 { 2734 struct si_power_info *si_pi = si_get_pi(adev); 2735 u32 leakage; 2736 unsigned int i, j; 2737 u32 smc_leakage; 2738 u32 scaling_factor; 2739 u16 voltage; 2740 2741 scaling_factor = si_get_smc_power_scaling_factor(adev); 2742 2743 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2744 voltage = vddc_max - (vddc_step * j); 2745 2746 si_calculate_leakage_for_v(adev, 2747 &si_pi->powertune_data->leakage_coefficients, 2748 si_pi->powertune_data->fixed_kt, 2749 voltage, 2750 si_pi->dyn_powertune_data.cac_leakage, 2751 &leakage); 2752 2753 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2754 2755 if (smc_leakage > 0xFFFF) 2756 smc_leakage = 0xFFFF; 2757 2758 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2759 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2760 cpu_to_be16((u16)smc_leakage); 2761 } 2762 return 0; 2763 } 2764 2765 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) 2766 { 2767 struct ni_power_info *ni_pi = ni_get_pi(adev); 2768 struct si_power_info *si_pi = si_get_pi(adev); 2769 PP_SIslands_CacConfig *cac_tables = NULL; 2770 u16 vddc_max, vddc_min, vddc_step; 2771 u16 t0, t_step; 2772 u32 load_line_slope, reg; 2773 int ret = 0; 2774 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100; 2775 2776 if (ni_pi->enable_cac == false) 2777 return 0; 2778 2779 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2780 if (!cac_tables) 2781 return -ENOMEM; 2782 2783 reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK; 2784 reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT); 2785 WREG32(mmCG_CAC_CTRL, reg); 2786 2787 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; 2788 si_pi->dyn_powertune_data.dc_pwr_value = 2789 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2790 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); 2791 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2792 2793 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2794 2795 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min); 2796 if (ret) 2797 goto done_free; 2798 2799 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2800 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2801 t_step = 4; 2802 t0 = 60; 2803 2804 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2805 ret = si_init_dte_leakage_table(adev, cac_tables, 2806 vddc_max, vddc_min, vddc_step, 2807 t0, t_step); 2808 else 2809 ret = si_init_simplified_leakage_table(adev, cac_tables, 2810 vddc_max, vddc_min, vddc_step); 2811 if (ret) 2812 goto done_free; 2813 2814 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2815 2816 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2817 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2818 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2819 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2820 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2821 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2822 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2823 cac_tables->calculation_repeats = cpu_to_be32(2); 2824 cac_tables->dc_cac = cpu_to_be32(0); 2825 cac_tables->log2_PG_LKG_SCALE = 12; 2826 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2827 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2828 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2829 2830 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, 2831 (u8 *)cac_tables, 2832 sizeof(PP_SIslands_CacConfig), 2833 si_pi->sram_end); 2834 2835 if (ret) 2836 goto done_free; 2837 2838 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2839 2840 done_free: 2841 if (ret) { 2842 ni_pi->enable_cac = false; 2843 ni_pi->enable_power_containment = false; 2844 } 2845 2846 kfree(cac_tables); 2847 2848 return ret; 2849 } 2850 2851 static int si_program_cac_config_registers(struct amdgpu_device *adev, 2852 const struct si_cac_config_reg *cac_config_regs) 2853 { 2854 const struct si_cac_config_reg *config_regs = cac_config_regs; 2855 u32 data = 0, offset; 2856 2857 if (!config_regs) 2858 return -EINVAL; 2859 2860 while (config_regs->offset != 0xFFFFFFFF) { 2861 switch (config_regs->type) { 2862 case SISLANDS_CACCONFIG_CGIND: 2863 offset = SMC_CG_IND_START + config_regs->offset; 2864 if (offset < SMC_CG_IND_END) 2865 data = RREG32_SMC(offset); 2866 break; 2867 default: 2868 data = RREG32(config_regs->offset); 2869 break; 2870 } 2871 2872 data &= ~config_regs->mask; 2873 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2874 2875 switch (config_regs->type) { 2876 case SISLANDS_CACCONFIG_CGIND: 2877 offset = SMC_CG_IND_START + config_regs->offset; 2878 if (offset < SMC_CG_IND_END) 2879 WREG32_SMC(offset, data); 2880 break; 2881 default: 2882 WREG32(config_regs->offset, data); 2883 break; 2884 } 2885 config_regs++; 2886 } 2887 return 0; 2888 } 2889 2890 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev) 2891 { 2892 struct ni_power_info *ni_pi = ni_get_pi(adev); 2893 struct si_power_info *si_pi = si_get_pi(adev); 2894 int ret; 2895 2896 if ((ni_pi->enable_cac == false) || 2897 (ni_pi->cac_configuration_required == false)) 2898 return 0; 2899 2900 ret = si_program_cac_config_registers(adev, si_pi->lcac_config); 2901 if (ret) 2902 return ret; 2903 ret = si_program_cac_config_registers(adev, si_pi->cac_override); 2904 if (ret) 2905 return ret; 2906 ret = si_program_cac_config_registers(adev, si_pi->cac_weights); 2907 if (ret) 2908 return ret; 2909 2910 return 0; 2911 } 2912 2913 static int si_enable_smc_cac(struct amdgpu_device *adev, 2914 struct amdgpu_ps *amdgpu_new_state, 2915 bool enable) 2916 { 2917 struct ni_power_info *ni_pi = ni_get_pi(adev); 2918 struct si_power_info *si_pi = si_get_pi(adev); 2919 PPSMC_Result smc_result; 2920 int ret = 0; 2921 2922 if (ni_pi->enable_cac) { 2923 if (enable) { 2924 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2925 if (ni_pi->support_cac_long_term_average) { 2926 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2927 if (smc_result != PPSMC_Result_OK) 2928 ni_pi->support_cac_long_term_average = false; 2929 } 2930 2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2932 if (smc_result != PPSMC_Result_OK) { 2933 ret = -EINVAL; 2934 ni_pi->cac_enabled = false; 2935 } else { 2936 ni_pi->cac_enabled = true; 2937 } 2938 2939 if (si_pi->enable_dte) { 2940 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2941 if (smc_result != PPSMC_Result_OK) 2942 ret = -EINVAL; 2943 } 2944 } 2945 } else if (ni_pi->cac_enabled) { 2946 if (si_pi->enable_dte) 2947 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2948 2949 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2950 2951 ni_pi->cac_enabled = false; 2952 2953 if (ni_pi->support_cac_long_term_average) 2954 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2955 } 2956 } 2957 return ret; 2958 } 2959 2960 static int si_init_smc_spll_table(struct amdgpu_device *adev) 2961 { 2962 struct ni_power_info *ni_pi = ni_get_pi(adev); 2963 struct si_power_info *si_pi = si_get_pi(adev); 2964 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2965 SISLANDS_SMC_SCLK_VALUE sclk_params; 2966 u32 fb_div, p_div; 2967 u32 clk_s, clk_v; 2968 u32 sclk = 0; 2969 int ret = 0; 2970 u32 tmp; 2971 int i; 2972 2973 if (si_pi->spll_table_start == 0) 2974 return -EINVAL; 2975 2976 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2977 if (spll_table == NULL) 2978 return -ENOMEM; 2979 2980 for (i = 0; i < 256; i++) { 2981 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); 2982 if (ret) 2983 break; 2984 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK) >> CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT; 2985 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT; 2986 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK) >> CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT; 2987 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK) >> CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT; 2988 2989 fb_div &= ~0x00001FFF; 2990 fb_div >>= 1; 2991 clk_v >>= 6; 2992 2993 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2994 ret = -EINVAL; 2995 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2996 ret = -EINVAL; 2997 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2998 ret = -EINVAL; 2999 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 3000 ret = -EINVAL; 3001 3002 if (ret) 3003 break; 3004 3005 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 3006 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 3007 spll_table->freq[i] = cpu_to_be32(tmp); 3008 3009 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 3010 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 3011 spll_table->ss[i] = cpu_to_be32(tmp); 3012 3013 sclk += 512; 3014 } 3015 3016 3017 if (!ret) 3018 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 3019 (u8 *)spll_table, 3020 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 3021 si_pi->sram_end); 3022 3023 if (ret) 3024 ni_pi->enable_power_containment = false; 3025 3026 kfree(spll_table); 3027 3028 return ret; 3029 } 3030 3031 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, 3032 u16 vce_voltage) 3033 { 3034 u16 highest_leakage = 0; 3035 struct si_power_info *si_pi = si_get_pi(adev); 3036 int i; 3037 3038 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 3039 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 3040 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 3041 } 3042 3043 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 3044 return highest_leakage; 3045 3046 return vce_voltage; 3047 } 3048 3049 static int si_get_vce_clock_voltage(struct amdgpu_device *adev, 3050 u32 evclk, u32 ecclk, u16 *voltage) 3051 { 3052 u32 i; 3053 int ret = -EINVAL; 3054 struct amdgpu_vce_clock_voltage_dependency_table *table = 3055 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3056 3057 if (((evclk == 0) && (ecclk == 0)) || 3058 (table && (table->count == 0))) { 3059 *voltage = 0; 3060 return 0; 3061 } 3062 3063 for (i = 0; i < table->count; i++) { 3064 if ((evclk <= table->entries[i].evclk) && 3065 (ecclk <= table->entries[i].ecclk)) { 3066 *voltage = table->entries[i].v; 3067 ret = 0; 3068 break; 3069 } 3070 } 3071 3072 /* if no match return the highest voltage */ 3073 if (ret) 3074 *voltage = table->entries[table->count - 1].v; 3075 3076 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage); 3077 3078 return ret; 3079 } 3080 3081 static bool si_dpm_vblank_too_short(void *handle) 3082 { 3083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3084 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); 3085 /* we never hit the non-gddr5 limit so disable it */ 3086 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; 3087 3088 if (vblank_time < switch_limit) 3089 return true; 3090 else 3091 return false; 3092 3093 } 3094 3095 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, 3096 u32 arb_freq_src, u32 arb_freq_dest) 3097 { 3098 u32 mc_arb_dram_timing; 3099 u32 mc_arb_dram_timing2; 3100 u32 burst_time; 3101 u32 mc_cg_config; 3102 3103 switch (arb_freq_src) { 3104 case MC_CG_ARB_FREQ_F0: 3105 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 3106 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 3107 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; 3108 break; 3109 case MC_CG_ARB_FREQ_F1: 3110 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); 3111 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 3112 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; 3113 break; 3114 case MC_CG_ARB_FREQ_F2: 3115 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); 3116 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 3117 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; 3118 break; 3119 case MC_CG_ARB_FREQ_F3: 3120 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); 3121 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 3122 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; 3123 break; 3124 default: 3125 return -EINVAL; 3126 } 3127 3128 switch (arb_freq_dest) { 3129 case MC_CG_ARB_FREQ_F0: 3130 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); 3131 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 3132 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); 3133 break; 3134 case MC_CG_ARB_FREQ_F1: 3135 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 3136 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 3137 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); 3138 break; 3139 case MC_CG_ARB_FREQ_F2: 3140 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); 3141 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); 3142 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); 3143 break; 3144 case MC_CG_ARB_FREQ_F3: 3145 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); 3146 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); 3147 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); 3148 break; 3149 default: 3150 return -EINVAL; 3151 } 3152 3153 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; 3154 WREG32(MC_CG_CONFIG, mc_cg_config); 3155 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); 3156 3157 return 0; 3158 } 3159 3160 static void ni_update_current_ps(struct amdgpu_device *adev, 3161 struct amdgpu_ps *rps) 3162 { 3163 struct si_ps *new_ps = si_get_ps(rps); 3164 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3165 struct ni_power_info *ni_pi = ni_get_pi(adev); 3166 3167 eg_pi->current_rps = *rps; 3168 ni_pi->current_ps = *new_ps; 3169 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; 3170 adev->pm.dpm.current_ps = &eg_pi->current_rps; 3171 } 3172 3173 static void ni_update_requested_ps(struct amdgpu_device *adev, 3174 struct amdgpu_ps *rps) 3175 { 3176 struct si_ps *new_ps = si_get_ps(rps); 3177 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3178 struct ni_power_info *ni_pi = ni_get_pi(adev); 3179 3180 eg_pi->requested_rps = *rps; 3181 ni_pi->requested_ps = *new_ps; 3182 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; 3183 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; 3184 } 3185 3186 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, 3187 struct amdgpu_ps *new_ps, 3188 struct amdgpu_ps *old_ps) 3189 { 3190 struct si_ps *new_state = si_get_ps(new_ps); 3191 struct si_ps *current_state = si_get_ps(old_ps); 3192 3193 if ((new_ps->vclk == old_ps->vclk) && 3194 (new_ps->dclk == old_ps->dclk)) 3195 return; 3196 3197 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= 3198 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3199 return; 3200 3201 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3202 } 3203 3204 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, 3205 struct amdgpu_ps *new_ps, 3206 struct amdgpu_ps *old_ps) 3207 { 3208 struct si_ps *new_state = si_get_ps(new_ps); 3209 struct si_ps *current_state = si_get_ps(old_ps); 3210 3211 if ((new_ps->vclk == old_ps->vclk) && 3212 (new_ps->dclk == old_ps->dclk)) 3213 return; 3214 3215 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < 3216 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3217 return; 3218 3219 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3220 } 3221 3222 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) 3223 { 3224 unsigned int i; 3225 3226 for (i = 0; i < table->count; i++) 3227 if (voltage <= table->entries[i].value) 3228 return table->entries[i].value; 3229 3230 return table->entries[table->count - 1].value; 3231 } 3232 3233 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, 3234 u32 max_clock, u32 requested_clock) 3235 { 3236 unsigned int i; 3237 3238 if ((clocks == NULL) || (clocks->count == 0)) 3239 return (requested_clock < max_clock) ? requested_clock : max_clock; 3240 3241 for (i = 0; i < clocks->count; i++) { 3242 if (clocks->values[i] >= requested_clock) 3243 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; 3244 } 3245 3246 return (clocks->values[clocks->count - 1] < max_clock) ? 3247 clocks->values[clocks->count - 1] : max_clock; 3248 } 3249 3250 static u32 btc_get_valid_mclk(struct amdgpu_device *adev, 3251 u32 max_mclk, u32 requested_mclk) 3252 { 3253 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, 3254 max_mclk, requested_mclk); 3255 } 3256 3257 static u32 btc_get_valid_sclk(struct amdgpu_device *adev, 3258 u32 max_sclk, u32 requested_sclk) 3259 { 3260 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, 3261 max_sclk, requested_sclk); 3262 } 3263 3264 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table, 3265 u32 *max_clock) 3266 { 3267 u32 i, clock = 0; 3268 3269 if ((table == NULL) || (table->count == 0)) { 3270 *max_clock = clock; 3271 return; 3272 } 3273 3274 for (i = 0; i < table->count; i++) { 3275 if (clock < table->entries[i].clk) 3276 clock = table->entries[i].clk; 3277 } 3278 *max_clock = clock; 3279 } 3280 3281 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table, 3282 u32 clock, u16 max_voltage, u16 *voltage) 3283 { 3284 u32 i; 3285 3286 if ((table == NULL) || (table->count == 0)) 3287 return; 3288 3289 for (i= 0; i < table->count; i++) { 3290 if (clock <= table->entries[i].clk) { 3291 if (*voltage < table->entries[i].v) 3292 *voltage = (u16)((table->entries[i].v < max_voltage) ? 3293 table->entries[i].v : max_voltage); 3294 return; 3295 } 3296 } 3297 3298 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage; 3299 } 3300 3301 static void btc_adjust_clock_combinations(struct amdgpu_device *adev, 3302 const struct amdgpu_clock_and_voltage_limits *max_limits, 3303 struct rv7xx_pl *pl) 3304 { 3305 3306 if ((pl->mclk == 0) || (pl->sclk == 0)) 3307 return; 3308 3309 if (pl->mclk == pl->sclk) 3310 return; 3311 3312 if (pl->mclk > pl->sclk) { 3313 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) 3314 pl->sclk = btc_get_valid_sclk(adev, 3315 max_limits->sclk, 3316 (pl->mclk + 3317 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / 3318 adev->pm.dpm.dyn_state.mclk_sclk_ratio); 3319 } else { 3320 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) 3321 pl->mclk = btc_get_valid_mclk(adev, 3322 max_limits->mclk, 3323 pl->sclk - 3324 adev->pm.dpm.dyn_state.sclk_mclk_delta); 3325 } 3326 } 3327 3328 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, 3329 u16 max_vddc, u16 max_vddci, 3330 u16 *vddc, u16 *vddci) 3331 { 3332 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3333 u16 new_voltage; 3334 3335 if ((0 == *vddc) || (0 == *vddci)) 3336 return; 3337 3338 if (*vddc > *vddci) { 3339 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3340 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, 3341 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3342 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; 3343 } 3344 } else { 3345 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3346 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, 3347 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3348 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; 3349 } 3350 } 3351 } 3352 3353 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 3354 u32 *p, u32 *u) 3355 { 3356 u32 b_c = 0; 3357 u32 i_c; 3358 u32 tmp; 3359 3360 i_c = (i * r_c) / 100; 3361 tmp = i_c >> p_b; 3362 3363 while (tmp) { 3364 b_c++; 3365 tmp >>= 1; 3366 } 3367 3368 *u = (b_c + 1) / 2; 3369 *p = i_c / (1 << (2 * (*u))); 3370 } 3371 3372 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) 3373 { 3374 u32 k, a, ah, al; 3375 u32 t1; 3376 3377 if ((fl == 0) || (fh == 0) || (fl > fh)) 3378 return -EINVAL; 3379 3380 k = (100 * fh) / fl; 3381 t1 = (t * (k - 100)); 3382 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); 3383 a = (a + 5) / 10; 3384 ah = ((a * t) + 5000) / 10000; 3385 al = a - ah; 3386 3387 *th = t - ah; 3388 *tl = t + al; 3389 3390 return 0; 3391 } 3392 3393 static bool r600_is_uvd_state(u32 class, u32 class2) 3394 { 3395 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 3396 return true; 3397 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 3398 return true; 3399 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 3400 return true; 3401 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 3402 return true; 3403 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 3404 return true; 3405 return false; 3406 } 3407 3408 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev) 3409 { 3410 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); 3411 } 3412 3413 static void rv770_get_max_vddc(struct amdgpu_device *adev) 3414 { 3415 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3416 u16 vddc; 3417 3418 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc)) 3419 pi->max_vddc = 0; 3420 else 3421 pi->max_vddc = vddc; 3422 } 3423 3424 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) 3425 { 3426 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3427 struct amdgpu_atom_ss ss; 3428 3429 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3430 ASIC_INTERNAL_ENGINE_SS, 0); 3431 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3432 ASIC_INTERNAL_MEMORY_SS, 0); 3433 3434 if (pi->sclk_ss || pi->mclk_ss) 3435 pi->dynamic_ss = true; 3436 else 3437 pi->dynamic_ss = false; 3438 } 3439 3440 3441 static void si_apply_state_adjust_rules(struct amdgpu_device *adev, 3442 struct amdgpu_ps *rps) 3443 { 3444 struct si_ps *ps = si_get_ps(rps); 3445 struct amdgpu_clock_and_voltage_limits *max_limits; 3446 bool disable_mclk_switching = false; 3447 bool disable_sclk_switching = false; 3448 u32 mclk, sclk; 3449 u16 vddc, vddci, min_vce_voltage = 0; 3450 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 3451 u32 max_sclk = 0, max_mclk = 0; 3452 int i; 3453 3454 if (adev->asic_type == CHIP_HAINAN) { 3455 if ((adev->pdev->revision == 0x81) || 3456 (adev->pdev->revision == 0xC3) || 3457 (adev->pdev->device == 0x6664) || 3458 (adev->pdev->device == 0x6665) || 3459 (adev->pdev->device == 0x6667)) { 3460 max_sclk = 75000; 3461 } 3462 if ((adev->pdev->revision == 0xC3) || 3463 (adev->pdev->device == 0x6665)) { 3464 max_sclk = 60000; 3465 max_mclk = 80000; 3466 } 3467 } else if (adev->asic_type == CHIP_OLAND) { 3468 if ((adev->pdev->revision == 0xC7) || 3469 (adev->pdev->revision == 0x80) || 3470 (adev->pdev->revision == 0x81) || 3471 (adev->pdev->revision == 0x83) || 3472 (adev->pdev->revision == 0x87) || 3473 (adev->pdev->device == 0x6604) || 3474 (adev->pdev->device == 0x6605)) { 3475 max_sclk = 75000; 3476 } 3477 } 3478 3479 if (rps->vce_active) { 3480 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 3481 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; 3482 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, 3483 &min_vce_voltage); 3484 } else { 3485 rps->evclk = 0; 3486 rps->ecclk = 0; 3487 } 3488 3489 if ((adev->pm.dpm.new_active_crtc_count > 1) || 3490 si_dpm_vblank_too_short(adev)) 3491 disable_mclk_switching = true; 3492 3493 if (rps->vclk || rps->dclk) { 3494 disable_mclk_switching = true; 3495 disable_sclk_switching = true; 3496 } 3497 3498 if (adev->pm.ac_power) 3499 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3500 else 3501 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3502 3503 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3504 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3505 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3506 } 3507 if (adev->pm.ac_power == false) { 3508 for (i = 0; i < ps->performance_level_count; i++) { 3509 if (ps->performance_levels[i].mclk > max_limits->mclk) 3510 ps->performance_levels[i].mclk = max_limits->mclk; 3511 if (ps->performance_levels[i].sclk > max_limits->sclk) 3512 ps->performance_levels[i].sclk = max_limits->sclk; 3513 if (ps->performance_levels[i].vddc > max_limits->vddc) 3514 ps->performance_levels[i].vddc = max_limits->vddc; 3515 if (ps->performance_levels[i].vddci > max_limits->vddci) 3516 ps->performance_levels[i].vddci = max_limits->vddci; 3517 } 3518 } 3519 3520 /* limit clocks to max supported clocks based on voltage dependency tables */ 3521 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3522 &max_sclk_vddc); 3523 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3524 &max_mclk_vddci); 3525 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3526 &max_mclk_vddc); 3527 3528 for (i = 0; i < ps->performance_level_count; i++) { 3529 if (max_sclk_vddc) { 3530 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3531 ps->performance_levels[i].sclk = max_sclk_vddc; 3532 } 3533 if (max_mclk_vddci) { 3534 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3535 ps->performance_levels[i].mclk = max_mclk_vddci; 3536 } 3537 if (max_mclk_vddc) { 3538 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3539 ps->performance_levels[i].mclk = max_mclk_vddc; 3540 } 3541 if (max_mclk) { 3542 if (ps->performance_levels[i].mclk > max_mclk) 3543 ps->performance_levels[i].mclk = max_mclk; 3544 } 3545 if (max_sclk) { 3546 if (ps->performance_levels[i].sclk > max_sclk) 3547 ps->performance_levels[i].sclk = max_sclk; 3548 } 3549 } 3550 3551 /* XXX validate the min clocks required for display */ 3552 3553 if (disable_mclk_switching) { 3554 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3555 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3556 } else { 3557 mclk = ps->performance_levels[0].mclk; 3558 vddci = ps->performance_levels[0].vddci; 3559 } 3560 3561 if (disable_sclk_switching) { 3562 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3563 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3564 } else { 3565 sclk = ps->performance_levels[0].sclk; 3566 vddc = ps->performance_levels[0].vddc; 3567 } 3568 3569 if (rps->vce_active) { 3570 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) 3571 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; 3572 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) 3573 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; 3574 } 3575 3576 /* adjusted low state */ 3577 ps->performance_levels[0].sclk = sclk; 3578 ps->performance_levels[0].mclk = mclk; 3579 ps->performance_levels[0].vddc = vddc; 3580 ps->performance_levels[0].vddci = vddci; 3581 3582 if (disable_sclk_switching) { 3583 sclk = ps->performance_levels[0].sclk; 3584 for (i = 1; i < ps->performance_level_count; i++) { 3585 if (sclk < ps->performance_levels[i].sclk) 3586 sclk = ps->performance_levels[i].sclk; 3587 } 3588 for (i = 0; i < ps->performance_level_count; i++) { 3589 ps->performance_levels[i].sclk = sclk; 3590 ps->performance_levels[i].vddc = vddc; 3591 } 3592 } else { 3593 for (i = 1; i < ps->performance_level_count; i++) { 3594 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3595 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3596 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3597 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3598 } 3599 } 3600 3601 if (disable_mclk_switching) { 3602 mclk = ps->performance_levels[0].mclk; 3603 for (i = 1; i < ps->performance_level_count; i++) { 3604 if (mclk < ps->performance_levels[i].mclk) 3605 mclk = ps->performance_levels[i].mclk; 3606 } 3607 for (i = 0; i < ps->performance_level_count; i++) { 3608 ps->performance_levels[i].mclk = mclk; 3609 ps->performance_levels[i].vddci = vddci; 3610 } 3611 } else { 3612 for (i = 1; i < ps->performance_level_count; i++) { 3613 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3614 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3615 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3616 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3617 } 3618 } 3619 3620 for (i = 0; i < ps->performance_level_count; i++) 3621 btc_adjust_clock_combinations(adev, max_limits, 3622 &ps->performance_levels[i]); 3623 3624 for (i = 0; i < ps->performance_level_count; i++) { 3625 if (ps->performance_levels[i].vddc < min_vce_voltage) 3626 ps->performance_levels[i].vddc = min_vce_voltage; 3627 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3628 ps->performance_levels[i].sclk, 3629 max_limits->vddc, &ps->performance_levels[i].vddc); 3630 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3631 ps->performance_levels[i].mclk, 3632 max_limits->vddci, &ps->performance_levels[i].vddci); 3633 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3634 ps->performance_levels[i].mclk, 3635 max_limits->vddc, &ps->performance_levels[i].vddc); 3636 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3637 adev->clock.current_dispclk, 3638 max_limits->vddc, &ps->performance_levels[i].vddc); 3639 } 3640 3641 for (i = 0; i < ps->performance_level_count; i++) { 3642 btc_apply_voltage_delta_rules(adev, 3643 max_limits->vddc, max_limits->vddci, 3644 &ps->performance_levels[i].vddc, 3645 &ps->performance_levels[i].vddci); 3646 } 3647 3648 ps->dc_compatible = true; 3649 for (i = 0; i < ps->performance_level_count; i++) { 3650 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3651 ps->dc_compatible = false; 3652 } 3653 } 3654 3655 #if 0 3656 static int si_read_smc_soft_register(struct amdgpu_device *adev, 3657 u16 reg_offset, u32 *value) 3658 { 3659 struct si_power_info *si_pi = si_get_pi(adev); 3660 3661 return amdgpu_si_read_smc_sram_dword(adev, 3662 si_pi->soft_regs_start + reg_offset, value, 3663 si_pi->sram_end); 3664 } 3665 #endif 3666 3667 static int si_write_smc_soft_register(struct amdgpu_device *adev, 3668 u16 reg_offset, u32 value) 3669 { 3670 struct si_power_info *si_pi = si_get_pi(adev); 3671 3672 return amdgpu_si_write_smc_sram_dword(adev, 3673 si_pi->soft_regs_start + reg_offset, 3674 value, si_pi->sram_end); 3675 } 3676 3677 static bool si_is_special_1gb_platform(struct amdgpu_device *adev) 3678 { 3679 bool ret = false; 3680 u32 tmp, width, row, column, bank, density; 3681 bool is_memory_gddr5, is_special; 3682 3683 tmp = RREG32(MC_SEQ_MISC0); 3684 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3685 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3686 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3687 3688 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3689 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3690 3691 tmp = RREG32(mmMC_ARB_RAMCFG); 3692 row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10; 3693 column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8; 3694 bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2; 3695 3696 density = (1 << (row + column - 20 + bank)) * width; 3697 3698 if ((adev->pdev->device == 0x6819) && 3699 is_memory_gddr5 && is_special && (density == 0x400)) 3700 ret = true; 3701 3702 return ret; 3703 } 3704 3705 static void si_get_leakage_vddc(struct amdgpu_device *adev) 3706 { 3707 struct si_power_info *si_pi = si_get_pi(adev); 3708 u16 vddc, count = 0; 3709 int i, ret; 3710 3711 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3712 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3713 3714 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3715 si_pi->leakage_voltage.entries[count].voltage = vddc; 3716 si_pi->leakage_voltage.entries[count].leakage_index = 3717 SISLANDS_LEAKAGE_INDEX0 + i; 3718 count++; 3719 } 3720 } 3721 si_pi->leakage_voltage.count = count; 3722 } 3723 3724 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, 3725 u32 index, u16 *leakage_voltage) 3726 { 3727 struct si_power_info *si_pi = si_get_pi(adev); 3728 int i; 3729 3730 if (leakage_voltage == NULL) 3731 return -EINVAL; 3732 3733 if ((index & 0xff00) != 0xff00) 3734 return -EINVAL; 3735 3736 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3737 return -EINVAL; 3738 3739 if (index < SISLANDS_LEAKAGE_INDEX0) 3740 return -EINVAL; 3741 3742 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3743 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3744 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3745 return 0; 3746 } 3747 } 3748 return -EAGAIN; 3749 } 3750 3751 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) 3752 { 3753 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3754 bool want_thermal_protection; 3755 enum si_dpm_event_src dpm_event_src; 3756 3757 switch (sources) { 3758 case 0: 3759 default: 3760 want_thermal_protection = false; 3761 break; 3762 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL): 3763 want_thermal_protection = true; 3764 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL; 3765 break; 3766 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3767 want_thermal_protection = true; 3768 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL; 3769 break; 3770 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3771 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3772 want_thermal_protection = true; 3773 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3774 break; 3775 } 3776 3777 if (want_thermal_protection) { 3778 WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK); 3779 if (pi->thermal_protection) 3780 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 3781 } else { 3782 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 3783 } 3784 } 3785 3786 static void si_enable_auto_throttle_source(struct amdgpu_device *adev, 3787 enum si_dpm_auto_throttle_src source, 3788 bool enable) 3789 { 3790 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3791 3792 if (enable) { 3793 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3794 pi->active_auto_throttle_sources |= 1 << source; 3795 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3796 } 3797 } else { 3798 if (pi->active_auto_throttle_sources & (1 << source)) { 3799 pi->active_auto_throttle_sources &= ~(1 << source); 3800 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3801 } 3802 } 3803 } 3804 3805 static void si_start_dpm(struct amdgpu_device *adev) 3806 { 3807 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK); 3808 } 3809 3810 static void si_stop_dpm(struct amdgpu_device *adev) 3811 { 3812 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK); 3813 } 3814 3815 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable) 3816 { 3817 if (enable) 3818 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK); 3819 else 3820 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK); 3821 3822 } 3823 3824 #if 0 3825 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, 3826 u32 thermal_level) 3827 { 3828 PPSMC_Result ret; 3829 3830 if (thermal_level == 0) { 3831 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3832 if (ret == PPSMC_Result_OK) 3833 return 0; 3834 else 3835 return -EINVAL; 3836 } 3837 return 0; 3838 } 3839 3840 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) 3841 { 3842 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3843 } 3844 #endif 3845 3846 #if 0 3847 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) 3848 { 3849 if (ac_power) 3850 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3851 0 : -EINVAL; 3852 3853 return 0; 3854 } 3855 #endif 3856 3857 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, 3858 PPSMC_Msg msg, u32 parameter) 3859 { 3860 WREG32(mmSMC_SCRATCH0, parameter); 3861 return amdgpu_si_send_msg_to_smc(adev, msg); 3862 } 3863 3864 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) 3865 { 3866 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3867 return -EINVAL; 3868 3869 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3870 0 : -EINVAL; 3871 } 3872 3873 static int si_dpm_force_performance_level(void *handle, 3874 enum amd_dpm_forced_level level) 3875 { 3876 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3877 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; 3878 struct si_ps *ps = si_get_ps(rps); 3879 u32 levels = ps->performance_level_count; 3880 3881 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 3882 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3883 return -EINVAL; 3884 3885 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3886 return -EINVAL; 3887 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { 3888 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3889 return -EINVAL; 3890 3891 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3892 return -EINVAL; 3893 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { 3894 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3895 return -EINVAL; 3896 3897 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3898 return -EINVAL; 3899 } 3900 3901 adev->pm.dpm.forced_level = level; 3902 3903 return 0; 3904 } 3905 3906 #if 0 3907 static int si_set_boot_state(struct amdgpu_device *adev) 3908 { 3909 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3910 0 : -EINVAL; 3911 } 3912 #endif 3913 3914 static int si_set_sw_state(struct amdgpu_device *adev) 3915 { 3916 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3917 0 : -EINVAL; 3918 } 3919 3920 static int si_halt_smc(struct amdgpu_device *adev) 3921 { 3922 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3923 return -EINVAL; 3924 3925 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3926 0 : -EINVAL; 3927 } 3928 3929 static int si_resume_smc(struct amdgpu_device *adev) 3930 { 3931 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3932 return -EINVAL; 3933 3934 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3935 0 : -EINVAL; 3936 } 3937 3938 static void si_dpm_start_smc(struct amdgpu_device *adev) 3939 { 3940 amdgpu_si_program_jump_on_start(adev); 3941 amdgpu_si_start_smc(adev); 3942 amdgpu_si_smc_clock(adev, true); 3943 } 3944 3945 static void si_dpm_stop_smc(struct amdgpu_device *adev) 3946 { 3947 amdgpu_si_reset_smc(adev); 3948 amdgpu_si_smc_clock(adev, false); 3949 } 3950 3951 static int si_process_firmware_header(struct amdgpu_device *adev) 3952 { 3953 struct si_power_info *si_pi = si_get_pi(adev); 3954 u32 tmp; 3955 int ret; 3956 3957 ret = amdgpu_si_read_smc_sram_dword(adev, 3958 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3959 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3960 &tmp, si_pi->sram_end); 3961 if (ret) 3962 return ret; 3963 3964 si_pi->state_table_start = tmp; 3965 3966 ret = amdgpu_si_read_smc_sram_dword(adev, 3967 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3968 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3969 &tmp, si_pi->sram_end); 3970 if (ret) 3971 return ret; 3972 3973 si_pi->soft_regs_start = tmp; 3974 3975 ret = amdgpu_si_read_smc_sram_dword(adev, 3976 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3977 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3978 &tmp, si_pi->sram_end); 3979 if (ret) 3980 return ret; 3981 3982 si_pi->mc_reg_table_start = tmp; 3983 3984 ret = amdgpu_si_read_smc_sram_dword(adev, 3985 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3986 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3987 &tmp, si_pi->sram_end); 3988 if (ret) 3989 return ret; 3990 3991 si_pi->fan_table_start = tmp; 3992 3993 ret = amdgpu_si_read_smc_sram_dword(adev, 3994 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3995 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3996 &tmp, si_pi->sram_end); 3997 if (ret) 3998 return ret; 3999 4000 si_pi->arb_table_start = tmp; 4001 4002 ret = amdgpu_si_read_smc_sram_dword(adev, 4003 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4004 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4005 &tmp, si_pi->sram_end); 4006 if (ret) 4007 return ret; 4008 4009 si_pi->cac_table_start = tmp; 4010 4011 ret = amdgpu_si_read_smc_sram_dword(adev, 4012 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4013 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4014 &tmp, si_pi->sram_end); 4015 if (ret) 4016 return ret; 4017 4018 si_pi->dte_table_start = tmp; 4019 4020 ret = amdgpu_si_read_smc_sram_dword(adev, 4021 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4022 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4023 &tmp, si_pi->sram_end); 4024 if (ret) 4025 return ret; 4026 4027 si_pi->spll_table_start = tmp; 4028 4029 ret = amdgpu_si_read_smc_sram_dword(adev, 4030 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4031 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4032 &tmp, si_pi->sram_end); 4033 if (ret) 4034 return ret; 4035 4036 si_pi->papm_cfg_table_start = tmp; 4037 4038 return ret; 4039 } 4040 4041 static void si_read_clock_registers(struct amdgpu_device *adev) 4042 { 4043 struct si_power_info *si_pi = si_get_pi(adev); 4044 4045 si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL); 4046 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2); 4047 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3); 4048 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4); 4049 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM); 4050 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2); 4051 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 4052 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 4053 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 4054 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 4055 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 4056 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 4057 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 4058 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 4059 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 4060 } 4061 4062 static void si_enable_thermal_protection(struct amdgpu_device *adev, 4063 bool enable) 4064 { 4065 if (enable) 4066 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 4067 else 4068 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 4069 } 4070 4071 static void si_enable_acpi_power_management(struct amdgpu_device *adev) 4072 { 4073 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK); 4074 } 4075 4076 #if 0 4077 static int si_enter_ulp_state(struct amdgpu_device *adev) 4078 { 4079 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 4080 4081 udelay(25000); 4082 4083 return 0; 4084 } 4085 4086 static int si_exit_ulp_state(struct amdgpu_device *adev) 4087 { 4088 int i; 4089 4090 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 4091 4092 udelay(7000); 4093 4094 for (i = 0; i < adev->usec_timeout; i++) { 4095 if (RREG32(SMC_RESP_0) == 1) 4096 break; 4097 udelay(1000); 4098 } 4099 4100 return 0; 4101 } 4102 #endif 4103 4104 static int si_notify_smc_display_change(struct amdgpu_device *adev, 4105 bool has_display) 4106 { 4107 PPSMC_Msg msg = has_display ? 4108 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 4109 4110 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4111 0 : -EINVAL; 4112 } 4113 4114 static void si_program_response_times(struct amdgpu_device *adev) 4115 { 4116 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 4117 u32 vddc_dly, acpi_dly, vbi_dly; 4118 u32 reference_clock; 4119 4120 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 4121 4122 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; 4123 4124 if (voltage_response_time == 0) 4125 voltage_response_time = 1000; 4126 4127 acpi_delay_time = 15000; 4128 vbi_time_out = 100000; 4129 4130 reference_clock = amdgpu_asic_get_xclk(adev); 4131 4132 vddc_dly = (voltage_response_time * reference_clock) / 100; 4133 acpi_dly = (acpi_delay_time * reference_clock) / 100; 4134 vbi_dly = (vbi_time_out * reference_clock) / 100; 4135 4136 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 4137 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 4138 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 4139 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 4140 } 4141 4142 static void si_program_ds_registers(struct amdgpu_device *adev) 4143 { 4144 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4145 u32 tmp; 4146 4147 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */ 4148 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0) 4149 tmp = 0x10; 4150 else 4151 tmp = 0x1; 4152 4153 if (eg_pi->sclk_deep_sleep) { 4154 WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK); 4155 WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK, 4156 ~CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK); 4157 } 4158 } 4159 4160 static void si_program_display_gap(struct amdgpu_device *adev) 4161 { 4162 u32 tmp, pipe; 4163 int i; 4164 4165 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); 4166 if (adev->pm.dpm.new_active_crtc_count > 0) 4167 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; 4168 else 4169 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; 4170 4171 if (adev->pm.dpm.new_active_crtc_count > 1) 4172 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; 4173 else 4174 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; 4175 4176 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp); 4177 4178 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 4179 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 4180 4181 if ((adev->pm.dpm.new_active_crtc_count > 0) && 4182 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 4183 /* find the first active crtc */ 4184 for (i = 0; i < adev->mode_info.num_crtc; i++) { 4185 if (adev->pm.dpm.new_active_crtcs & (1 << i)) 4186 break; 4187 } 4188 if (i == adev->mode_info.num_crtc) 4189 pipe = 0; 4190 else 4191 pipe = i; 4192 4193 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 4194 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 4195 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 4196 } 4197 4198 /* Setting this to false forces the performance state to low if the crtcs are disabled. 4199 * This can be a problem on PowerXpress systems or if you want to use the card 4200 * for offscreen rendering or compute if there are no crtcs enabled. 4201 */ 4202 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); 4203 } 4204 4205 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) 4206 { 4207 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4208 4209 if (enable) { 4210 if (pi->sclk_ss) 4211 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK); 4212 } else { 4213 WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK); 4214 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK); 4215 } 4216 } 4217 4218 static void si_setup_bsp(struct amdgpu_device *adev) 4219 { 4220 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4221 u32 xclk = amdgpu_asic_get_xclk(adev); 4222 4223 r600_calculate_u_and_p(pi->asi, 4224 xclk, 4225 16, 4226 &pi->bsp, 4227 &pi->bsu); 4228 4229 r600_calculate_u_and_p(pi->pasi, 4230 xclk, 4231 16, 4232 &pi->pbsp, 4233 &pi->pbsu); 4234 4235 4236 pi->dsp = (pi->bsp << CG_BSP__BSP__SHIFT) | (pi->bsu << CG_BSP__BSU__SHIFT); 4237 pi->psp = (pi->pbsp << CG_BSP__BSP__SHIFT) | (pi->pbsu << CG_BSP__BSU__SHIFT); 4238 4239 WREG32(mmCG_BSP, pi->dsp); 4240 } 4241 4242 static void si_program_git(struct amdgpu_device *adev) 4243 { 4244 WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK); 4245 } 4246 4247 static void si_program_tp(struct amdgpu_device *adev) 4248 { 4249 int i; 4250 enum r600_td td = R600_TD_DFLT; 4251 4252 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 4253 WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT)); 4254 4255 if (td == R600_TD_AUTO) 4256 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK); 4257 else 4258 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK); 4259 4260 if (td == R600_TD_UP) 4261 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK); 4262 4263 if (td == R600_TD_DOWN) 4264 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK); 4265 } 4266 4267 static void si_program_tpp(struct amdgpu_device *adev) 4268 { 4269 WREG32(mmCG_TPC, R600_TPC_DFLT); 4270 } 4271 4272 static void si_program_sstp(struct amdgpu_device *adev) 4273 { 4274 WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT)); 4275 } 4276 4277 static void si_enable_display_gap(struct amdgpu_device *adev) 4278 { 4279 u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL); 4280 4281 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); 4282 tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT | 4283 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT); 4284 4285 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK); 4286 tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT | 4287 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT); 4288 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp); 4289 } 4290 4291 static void si_program_vc(struct amdgpu_device *adev) 4292 { 4293 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4294 4295 WREG32(mmCG_FTV, pi->vrc); 4296 } 4297 4298 static void si_clear_vc(struct amdgpu_device *adev) 4299 { 4300 WREG32(mmCG_FTV, 0); 4301 } 4302 4303 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 4304 { 4305 u8 mc_para_index; 4306 4307 if (memory_clock < 10000) 4308 mc_para_index = 0; 4309 else if (memory_clock >= 80000) 4310 mc_para_index = 0x0f; 4311 else 4312 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 4313 return mc_para_index; 4314 } 4315 4316 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 4317 { 4318 u8 mc_para_index; 4319 4320 if (strobe_mode) { 4321 if (memory_clock < 12500) 4322 mc_para_index = 0x00; 4323 else if (memory_clock > 47500) 4324 mc_para_index = 0x0f; 4325 else 4326 mc_para_index = (u8)((memory_clock - 10000) / 2500); 4327 } else { 4328 if (memory_clock < 65000) 4329 mc_para_index = 0x00; 4330 else if (memory_clock > 135000) 4331 mc_para_index = 0x0f; 4332 else 4333 mc_para_index = (u8)((memory_clock - 60000) / 5000); 4334 } 4335 return mc_para_index; 4336 } 4337 4338 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) 4339 { 4340 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4341 bool strobe_mode = false; 4342 u8 result = 0; 4343 4344 if (mclk <= pi->mclk_strobe_mode_threshold) 4345 strobe_mode = true; 4346 4347 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 4348 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 4349 else 4350 result = si_get_ddr3_mclk_frequency_ratio(mclk); 4351 4352 if (strobe_mode) 4353 result |= SISLANDS_SMC_STROBE_ENABLE; 4354 4355 return result; 4356 } 4357 4358 static int si_upload_firmware(struct amdgpu_device *adev) 4359 { 4360 struct si_power_info *si_pi = si_get_pi(adev); 4361 4362 amdgpu_si_reset_smc(adev); 4363 amdgpu_si_smc_clock(adev, false); 4364 4365 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); 4366 } 4367 4368 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, 4369 const struct atom_voltage_table *table, 4370 const struct amdgpu_phase_shedding_limits_table *limits) 4371 { 4372 u32 data, num_bits, num_levels; 4373 4374 if ((table == NULL) || (limits == NULL)) 4375 return false; 4376 4377 data = table->mask_low; 4378 4379 num_bits = hweight32(data); 4380 4381 if (num_bits == 0) 4382 return false; 4383 4384 num_levels = (1 << num_bits); 4385 4386 if (table->count != num_levels) 4387 return false; 4388 4389 if (limits->count != (num_levels - 1)) 4390 return false; 4391 4392 return true; 4393 } 4394 4395 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, 4396 u32 max_voltage_steps, 4397 struct atom_voltage_table *voltage_table) 4398 { 4399 unsigned int i, diff; 4400 4401 if (voltage_table->count <= max_voltage_steps) 4402 return; 4403 4404 diff = voltage_table->count - max_voltage_steps; 4405 4406 for (i= 0; i < max_voltage_steps; i++) 4407 voltage_table->entries[i] = voltage_table->entries[i + diff]; 4408 4409 voltage_table->count = max_voltage_steps; 4410 } 4411 4412 static int si_get_svi2_voltage_table(struct amdgpu_device *adev, 4413 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, 4414 struct atom_voltage_table *voltage_table) 4415 { 4416 u32 i; 4417 4418 if (voltage_dependency_table == NULL) 4419 return -EINVAL; 4420 4421 voltage_table->mask_low = 0; 4422 voltage_table->phase_delay = 0; 4423 4424 voltage_table->count = voltage_dependency_table->count; 4425 for (i = 0; i < voltage_table->count; i++) { 4426 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 4427 voltage_table->entries[i].smio_low = 0; 4428 } 4429 4430 return 0; 4431 } 4432 4433 static int si_construct_voltage_tables(struct amdgpu_device *adev) 4434 { 4435 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4436 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4437 struct si_power_info *si_pi = si_get_pi(adev); 4438 int ret; 4439 4440 if (pi->voltage_control) { 4441 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4442 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 4443 if (ret) 4444 return ret; 4445 4446 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4447 si_trim_voltage_table_to_fit_state_table(adev, 4448 SISLANDS_MAX_NO_VREG_STEPS, 4449 &eg_pi->vddc_voltage_table); 4450 } else if (si_pi->voltage_control_svi2) { 4451 ret = si_get_svi2_voltage_table(adev, 4452 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4453 &eg_pi->vddc_voltage_table); 4454 if (ret) 4455 return ret; 4456 } else { 4457 return -EINVAL; 4458 } 4459 4460 if (eg_pi->vddci_control) { 4461 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, 4462 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4463 if (ret) 4464 return ret; 4465 4466 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4467 si_trim_voltage_table_to_fit_state_table(adev, 4468 SISLANDS_MAX_NO_VREG_STEPS, 4469 &eg_pi->vddci_voltage_table); 4470 } 4471 if (si_pi->vddci_control_svi2) { 4472 ret = si_get_svi2_voltage_table(adev, 4473 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4474 &eg_pi->vddci_voltage_table); 4475 if (ret) 4476 return ret; 4477 } 4478 4479 if (pi->mvdd_control) { 4480 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, 4481 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4482 4483 if (ret) { 4484 pi->mvdd_control = false; 4485 return ret; 4486 } 4487 4488 if (si_pi->mvdd_voltage_table.count == 0) { 4489 pi->mvdd_control = false; 4490 return -EINVAL; 4491 } 4492 4493 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4494 si_trim_voltage_table_to_fit_state_table(adev, 4495 SISLANDS_MAX_NO_VREG_STEPS, 4496 &si_pi->mvdd_voltage_table); 4497 } 4498 4499 if (si_pi->vddc_phase_shed_control) { 4500 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4501 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4502 if (ret) 4503 si_pi->vddc_phase_shed_control = false; 4504 4505 if ((si_pi->vddc_phase_shed_table.count == 0) || 4506 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4507 si_pi->vddc_phase_shed_control = false; 4508 } 4509 4510 return 0; 4511 } 4512 4513 static void si_populate_smc_voltage_table(struct amdgpu_device *adev, 4514 const struct atom_voltage_table *voltage_table, 4515 SISLANDS_SMC_STATETABLE *table) 4516 { 4517 unsigned int i; 4518 4519 for (i = 0; i < voltage_table->count; i++) 4520 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4521 } 4522 4523 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev, 4524 SISLANDS_SMC_STATETABLE *table) 4525 { 4526 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4527 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4528 struct si_power_info *si_pi = si_get_pi(adev); 4529 u8 i; 4530 4531 if (si_pi->voltage_control_svi2) { 4532 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4533 si_pi->svc_gpio_id); 4534 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4535 si_pi->svd_gpio_id); 4536 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4537 2); 4538 } else { 4539 if (eg_pi->vddc_voltage_table.count) { 4540 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); 4541 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4542 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4543 4544 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4545 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4546 table->maxVDDCIndexInPPTable = i; 4547 break; 4548 } 4549 } 4550 } 4551 4552 if (eg_pi->vddci_voltage_table.count) { 4553 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); 4554 4555 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4556 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4557 } 4558 4559 4560 if (si_pi->mvdd_voltage_table.count) { 4561 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); 4562 4563 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4564 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4565 } 4566 4567 if (si_pi->vddc_phase_shed_control) { 4568 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, 4569 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4570 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); 4571 4572 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4573 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4574 4575 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4576 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4577 } else { 4578 si_pi->vddc_phase_shed_control = false; 4579 } 4580 } 4581 } 4582 4583 return 0; 4584 } 4585 4586 static int si_populate_voltage_value(struct amdgpu_device *adev, 4587 const struct atom_voltage_table *table, 4588 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4589 { 4590 unsigned int i; 4591 4592 for (i = 0; i < table->count; i++) { 4593 if (value <= table->entries[i].value) { 4594 voltage->index = (u8)i; 4595 voltage->value = cpu_to_be16(table->entries[i].value); 4596 break; 4597 } 4598 } 4599 4600 if (i >= table->count) 4601 return -EINVAL; 4602 4603 return 0; 4604 } 4605 4606 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, 4607 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4608 { 4609 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4610 struct si_power_info *si_pi = si_get_pi(adev); 4611 4612 if (pi->mvdd_control) { 4613 if (mclk <= pi->mvdd_split_frequency) 4614 voltage->index = 0; 4615 else 4616 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4617 4618 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4619 } 4620 return 0; 4621 } 4622 4623 static int si_get_std_voltage_value(struct amdgpu_device *adev, 4624 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4625 u16 *std_voltage) 4626 { 4627 u16 v_index; 4628 bool voltage_found = false; 4629 *std_voltage = be16_to_cpu(voltage->value); 4630 4631 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4632 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4633 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4634 return -EINVAL; 4635 4636 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4637 if (be16_to_cpu(voltage->value) == 4638 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4639 voltage_found = true; 4640 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4641 *std_voltage = 4642 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4643 else 4644 *std_voltage = 4645 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4646 break; 4647 } 4648 } 4649 4650 if (!voltage_found) { 4651 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4652 if (be16_to_cpu(voltage->value) <= 4653 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4654 voltage_found = true; 4655 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4656 *std_voltage = 4657 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4658 else 4659 *std_voltage = 4660 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4661 break; 4662 } 4663 } 4664 } 4665 } else { 4666 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4667 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4668 } 4669 } 4670 4671 return 0; 4672 } 4673 4674 static int si_populate_std_voltage_value(struct amdgpu_device *adev, 4675 u16 value, u8 index, 4676 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4677 { 4678 voltage->index = index; 4679 voltage->value = cpu_to_be16(value); 4680 4681 return 0; 4682 } 4683 4684 static int si_populate_phase_shedding_value(struct amdgpu_device *adev, 4685 const struct amdgpu_phase_shedding_limits_table *limits, 4686 u16 voltage, u32 sclk, u32 mclk, 4687 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4688 { 4689 unsigned int i; 4690 4691 for (i = 0; i < limits->count; i++) { 4692 if ((voltage <= limits->entries[i].voltage) && 4693 (sclk <= limits->entries[i].sclk) && 4694 (mclk <= limits->entries[i].mclk)) 4695 break; 4696 } 4697 4698 smc_voltage->phase_settings = (u8)i; 4699 4700 return 0; 4701 } 4702 4703 static int si_init_arb_table_index(struct amdgpu_device *adev) 4704 { 4705 struct si_power_info *si_pi = si_get_pi(adev); 4706 u32 tmp; 4707 int ret; 4708 4709 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4710 &tmp, si_pi->sram_end); 4711 if (ret) 4712 return ret; 4713 4714 tmp &= 0x00FFFFFF; 4715 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4716 4717 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, 4718 tmp, si_pi->sram_end); 4719 } 4720 4721 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) 4722 { 4723 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4724 } 4725 4726 static int si_reset_to_default(struct amdgpu_device *adev) 4727 { 4728 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4729 0 : -EINVAL; 4730 } 4731 4732 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) 4733 { 4734 struct si_power_info *si_pi = si_get_pi(adev); 4735 u32 tmp; 4736 int ret; 4737 4738 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4739 &tmp, si_pi->sram_end); 4740 if (ret) 4741 return ret; 4742 4743 tmp = (tmp >> 24) & 0xff; 4744 4745 if (tmp == MC_CG_ARB_FREQ_F0) 4746 return 0; 4747 4748 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); 4749 } 4750 4751 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, 4752 u32 engine_clock) 4753 { 4754 u32 dram_rows; 4755 u32 dram_refresh_rate; 4756 u32 mc_arb_rfsh_rate; 4757 u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT; 4758 4759 if (tmp >= 4) 4760 dram_rows = 16384; 4761 else 4762 dram_rows = 1 << (tmp + 10); 4763 4764 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4765 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4766 4767 return mc_arb_rfsh_rate; 4768 } 4769 4770 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, 4771 struct rv7xx_pl *pl, 4772 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4773 { 4774 u32 dram_timing; 4775 u32 dram_timing2; 4776 u32 burst_time; 4777 int ret; 4778 4779 arb_regs->mc_arb_rfsh_rate = 4780 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); 4781 4782 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk, 4783 pl->mclk); 4784 if (ret) 4785 return ret; 4786 4787 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4788 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4789 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4790 4791 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4792 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4793 arb_regs->mc_arb_burst_time = (u8)burst_time; 4794 4795 return 0; 4796 } 4797 4798 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, 4799 struct amdgpu_ps *amdgpu_state, 4800 unsigned int first_arb_set) 4801 { 4802 struct si_power_info *si_pi = si_get_pi(adev); 4803 struct si_ps *state = si_get_ps(amdgpu_state); 4804 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4805 int i, ret = 0; 4806 4807 for (i = 0; i < state->performance_level_count; i++) { 4808 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4809 if (ret) 4810 break; 4811 ret = amdgpu_si_copy_bytes_to_smc(adev, 4812 si_pi->arb_table_start + 4813 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4814 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4815 (u8 *)&arb_regs, 4816 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4817 si_pi->sram_end); 4818 if (ret) 4819 break; 4820 } 4821 4822 return ret; 4823 } 4824 4825 static int si_program_memory_timing_parameters(struct amdgpu_device *adev, 4826 struct amdgpu_ps *amdgpu_new_state) 4827 { 4828 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state, 4829 SISLANDS_DRIVER_STATE_ARB_INDEX); 4830 } 4831 4832 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev, 4833 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4834 { 4835 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4836 struct si_power_info *si_pi = si_get_pi(adev); 4837 4838 if (pi->mvdd_control) 4839 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, 4840 si_pi->mvdd_bootup_value, voltage); 4841 4842 return 0; 4843 } 4844 4845 static int si_populate_smc_initial_state(struct amdgpu_device *adev, 4846 struct amdgpu_ps *amdgpu_initial_state, 4847 SISLANDS_SMC_STATETABLE *table) 4848 { 4849 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); 4850 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4851 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4852 struct si_power_info *si_pi = si_get_pi(adev); 4853 u32 reg; 4854 int ret; 4855 4856 table->initialState.level.mclk.vDLL_CNTL = 4857 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4858 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = 4859 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4860 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = 4861 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4862 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = 4863 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4864 table->initialState.level.mclk.vMPLL_FUNC_CNTL = 4865 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4866 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = 4867 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4868 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = 4869 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4870 table->initialState.level.mclk.vMPLL_SS = 4871 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4872 table->initialState.level.mclk.vMPLL_SS2 = 4873 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4874 4875 table->initialState.level.mclk.mclk_value = 4876 cpu_to_be32(initial_state->performance_levels[0].mclk); 4877 4878 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = 4879 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4880 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 4881 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4882 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 4883 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4884 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 4885 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4886 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = 4887 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4888 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4889 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4890 4891 table->initialState.level.sclk.sclk_value = 4892 cpu_to_be32(initial_state->performance_levels[0].sclk); 4893 4894 table->initialState.level.arbRefreshState = 4895 SISLANDS_INITIAL_STATE_ARB_INDEX; 4896 4897 table->initialState.level.ACIndex = 0; 4898 4899 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 4900 initial_state->performance_levels[0].vddc, 4901 &table->initialState.level.vddc); 4902 4903 if (!ret) { 4904 u16 std_vddc; 4905 4906 ret = si_get_std_voltage_value(adev, 4907 &table->initialState.level.vddc, 4908 &std_vddc); 4909 if (!ret) 4910 si_populate_std_voltage_value(adev, std_vddc, 4911 table->initialState.level.vddc.index, 4912 &table->initialState.level.std_vddc); 4913 } 4914 4915 if (eg_pi->vddci_control) 4916 si_populate_voltage_value(adev, 4917 &eg_pi->vddci_voltage_table, 4918 initial_state->performance_levels[0].vddci, 4919 &table->initialState.level.vddci); 4920 4921 if (si_pi->vddc_phase_shed_control) 4922 si_populate_phase_shedding_value(adev, 4923 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 4924 initial_state->performance_levels[0].vddc, 4925 initial_state->performance_levels[0].sclk, 4926 initial_state->performance_levels[0].mclk, 4927 &table->initialState.level.vddc); 4928 4929 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd); 4930 4931 reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT; 4932 table->initialState.level.aT = cpu_to_be32(reg); 4933 table->initialState.level.bSP = cpu_to_be32(pi->dsp); 4934 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; 4935 4936 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 4937 table->initialState.level.strobeMode = 4938 si_get_strobe_mode_settings(adev, 4939 initial_state->performance_levels[0].mclk); 4940 4941 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4942 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4943 else 4944 table->initialState.level.mcFlags = 0; 4945 } 4946 4947 table->initialState.levelCount = 1; 4948 4949 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4950 4951 table->initialState.level.dpm2.MaxPS = 0; 4952 table->initialState.level.dpm2.NearTDPDec = 0; 4953 table->initialState.level.dpm2.AboveSafeInc = 0; 4954 table->initialState.level.dpm2.BelowSafeInc = 0; 4955 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; 4956 4957 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | 4958 SQ_POWER_THROTTLE__MAX_POWER_MASK; 4959 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); 4960 4961 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | 4962 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | 4963 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 4964 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 4965 4966 return 0; 4967 } 4968 4969 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev, 4970 u32 sys_mask, 4971 enum si_pcie_gen asic_gen, 4972 enum si_pcie_gen default_gen) 4973 { 4974 switch (asic_gen) { 4975 case SI_PCIE_GEN1: 4976 return SI_PCIE_GEN1; 4977 case SI_PCIE_GEN2: 4978 return SI_PCIE_GEN2; 4979 case SI_PCIE_GEN3: 4980 return SI_PCIE_GEN3; 4981 default: 4982 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) && 4983 (default_gen == SI_PCIE_GEN3)) 4984 return SI_PCIE_GEN3; 4985 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) && 4986 (default_gen == SI_PCIE_GEN2)) 4987 return SI_PCIE_GEN2; 4988 else 4989 return SI_PCIE_GEN1; 4990 } 4991 return SI_PCIE_GEN1; 4992 } 4993 4994 static int si_populate_smc_acpi_state(struct amdgpu_device *adev, 4995 SISLANDS_SMC_STATETABLE *table) 4996 { 4997 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4998 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4999 struct si_power_info *si_pi = si_get_pi(adev); 5000 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5001 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5002 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5003 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5004 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5005 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5006 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5007 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5008 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5009 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5010 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5011 u32 reg; 5012 int ret; 5013 5014 table->ACPIState = table->initialState; 5015 5016 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 5017 5018 if (pi->acpi_vddc) { 5019 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5020 pi->acpi_vddc, &table->ACPIState.level.vddc); 5021 if (!ret) { 5022 u16 std_vddc; 5023 5024 ret = si_get_std_voltage_value(adev, 5025 &table->ACPIState.level.vddc, &std_vddc); 5026 if (!ret) 5027 si_populate_std_voltage_value(adev, std_vddc, 5028 table->ACPIState.level.vddc.index, 5029 &table->ACPIState.level.std_vddc); 5030 } 5031 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; 5032 5033 if (si_pi->vddc_phase_shed_control) { 5034 si_populate_phase_shedding_value(adev, 5035 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5036 pi->acpi_vddc, 5037 0, 5038 0, 5039 &table->ACPIState.level.vddc); 5040 } 5041 } else { 5042 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5043 pi->min_vddc_in_table, &table->ACPIState.level.vddc); 5044 if (!ret) { 5045 u16 std_vddc; 5046 5047 ret = si_get_std_voltage_value(adev, 5048 &table->ACPIState.level.vddc, &std_vddc); 5049 5050 if (!ret) 5051 si_populate_std_voltage_value(adev, std_vddc, 5052 table->ACPIState.level.vddc.index, 5053 &table->ACPIState.level.std_vddc); 5054 } 5055 table->ACPIState.level.gen2PCIE = 5056 (u8)si_gen_pcie_gen_support(adev, 5057 si_pi->sys_pcie_mask, 5058 si_pi->boot_pcie_gen, 5059 SI_PCIE_GEN1); 5060 5061 if (si_pi->vddc_phase_shed_control) 5062 si_populate_phase_shedding_value(adev, 5063 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5064 pi->min_vddc_in_table, 5065 0, 5066 0, 5067 &table->ACPIState.level.vddc); 5068 } 5069 5070 if (pi->acpi_vddc) { 5071 if (eg_pi->acpi_vddci) 5072 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5073 eg_pi->acpi_vddci, 5074 &table->ACPIState.level.vddci); 5075 } 5076 5077 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 5078 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5079 5080 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 5081 5082 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; 5083 spll_func_cntl_2 |= 4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT; 5084 5085 table->ACPIState.level.mclk.vDLL_CNTL = 5086 cpu_to_be32(dll_cntl); 5087 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = 5088 cpu_to_be32(mclk_pwrmgt_cntl); 5089 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = 5090 cpu_to_be32(mpll_ad_func_cntl); 5091 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = 5092 cpu_to_be32(mpll_dq_func_cntl); 5093 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = 5094 cpu_to_be32(mpll_func_cntl); 5095 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = 5096 cpu_to_be32(mpll_func_cntl_1); 5097 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = 5098 cpu_to_be32(mpll_func_cntl_2); 5099 table->ACPIState.level.mclk.vMPLL_SS = 5100 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 5101 table->ACPIState.level.mclk.vMPLL_SS2 = 5102 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 5103 5104 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = 5105 cpu_to_be32(spll_func_cntl); 5106 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 5107 cpu_to_be32(spll_func_cntl_2); 5108 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 5109 cpu_to_be32(spll_func_cntl_3); 5110 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 5111 cpu_to_be32(spll_func_cntl_4); 5112 5113 table->ACPIState.level.mclk.mclk_value = 0; 5114 table->ACPIState.level.sclk.sclk_value = 0; 5115 5116 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd); 5117 5118 if (eg_pi->dynamic_ac_timing) 5119 table->ACPIState.level.ACIndex = 0; 5120 5121 table->ACPIState.level.dpm2.MaxPS = 0; 5122 table->ACPIState.level.dpm2.NearTDPDec = 0; 5123 table->ACPIState.level.dpm2.AboveSafeInc = 0; 5124 table->ACPIState.level.dpm2.BelowSafeInc = 0; 5125 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; 5126 5127 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK; 5128 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); 5129 5130 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 5131 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 5132 5133 return 0; 5134 } 5135 5136 static int si_populate_ulv_state(struct amdgpu_device *adev, 5137 struct SISLANDS_SMC_SWSTATE_SINGLE *state) 5138 { 5139 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5140 struct si_power_info *si_pi = si_get_pi(adev); 5141 struct si_ulv_param *ulv = &si_pi->ulv; 5142 u32 sclk_in_sr = 1350; /* ??? */ 5143 int ret; 5144 5145 ret = si_convert_power_level_to_smc(adev, &ulv->pl, 5146 &state->level); 5147 if (!ret) { 5148 if (eg_pi->sclk_deep_sleep) { 5149 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5150 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5151 else 5152 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5153 } 5154 if (ulv->one_pcie_lane_in_ulv) 5155 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 5156 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 5157 state->level.ACIndex = 1; 5158 state->level.std_vddc = state->level.vddc; 5159 state->levelCount = 1; 5160 5161 state->flags |= PPSMC_SWSTATE_FLAG_DC; 5162 } 5163 5164 return ret; 5165 } 5166 5167 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) 5168 { 5169 struct si_power_info *si_pi = si_get_pi(adev); 5170 struct si_ulv_param *ulv = &si_pi->ulv; 5171 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 5172 int ret; 5173 5174 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, 5175 &arb_regs); 5176 if (ret) 5177 return ret; 5178 5179 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 5180 ulv->volt_change_delay); 5181 5182 ret = amdgpu_si_copy_bytes_to_smc(adev, 5183 si_pi->arb_table_start + 5184 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5185 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5186 (u8 *)&arb_regs, 5187 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5188 si_pi->sram_end); 5189 5190 return ret; 5191 } 5192 5193 static void si_get_mvdd_configuration(struct amdgpu_device *adev) 5194 { 5195 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5196 5197 pi->mvdd_split_frequency = 30000; 5198 } 5199 5200 static int si_init_smc_table(struct amdgpu_device *adev) 5201 { 5202 struct si_power_info *si_pi = si_get_pi(adev); 5203 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; 5204 const struct si_ulv_param *ulv = &si_pi->ulv; 5205 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 5206 int ret; 5207 u32 lane_width; 5208 u32 vr_hot_gpio; 5209 5210 si_populate_smc_voltage_tables(adev, table); 5211 5212 switch (adev->pm.int_thermal_type) { 5213 case THERMAL_TYPE_SI: 5214 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 5215 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 5216 break; 5217 case THERMAL_TYPE_NONE: 5218 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 5219 break; 5220 default: 5221 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 5222 break; 5223 } 5224 5225 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 5226 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 5227 5228 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 5229 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819)) 5230 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 5231 } 5232 5233 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 5234 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 5235 5236 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5237 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 5238 5239 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 5240 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 5241 5242 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 5243 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 5244 vr_hot_gpio = adev->pm.dpm.backbias_response_time; 5245 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 5246 vr_hot_gpio); 5247 } 5248 5249 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table); 5250 if (ret) 5251 return ret; 5252 5253 ret = si_populate_smc_acpi_state(adev, table); 5254 if (ret) 5255 return ret; 5256 5257 table->driverState.flags = table->initialState.flags; 5258 table->driverState.levelCount = table->initialState.levelCount; 5259 table->driverState.levels[0] = table->initialState.level; 5260 5261 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state, 5262 SISLANDS_INITIAL_STATE_ARB_INDEX); 5263 if (ret) 5264 return ret; 5265 5266 if (ulv->supported && ulv->pl.vddc) { 5267 ret = si_populate_ulv_state(adev, &table->ULVState); 5268 if (ret) 5269 return ret; 5270 5271 ret = si_program_ulv_memory_timing_parameters(adev); 5272 if (ret) 5273 return ret; 5274 5275 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control); 5276 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter); 5277 5278 lane_width = amdgpu_get_pcie_lanes(adev); 5279 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5280 } else { 5281 table->ULVState = table->initialState; 5282 } 5283 5284 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5285 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5286 si_pi->sram_end); 5287 } 5288 5289 static int si_calculate_sclk_params(struct amdgpu_device *adev, 5290 u32 engine_clock, 5291 SISLANDS_SMC_SCLK_VALUE *sclk) 5292 { 5293 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5294 struct si_power_info *si_pi = si_get_pi(adev); 5295 struct atom_clock_dividers dividers; 5296 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5297 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5298 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5299 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5300 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 5301 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 5302 u64 tmp; 5303 u32 reference_clock = adev->clock.spll.reference_freq; 5304 u32 reference_divider; 5305 u32 fbdiv; 5306 int ret; 5307 5308 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 5309 engine_clock, false, ÷rs); 5310 if (ret) 5311 return ret; 5312 5313 reference_divider = 1 + dividers.ref_div; 5314 5315 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 5316 do_div(tmp, reference_clock); 5317 fbdiv = (u32) tmp; 5318 5319 spll_func_cntl &= ~(CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK | CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK); 5320 spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT; 5321 spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT; 5322 5323 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; 5324 spll_func_cntl_2 |= 2 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT; 5325 5326 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK; 5327 spll_func_cntl_3 |= fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT; 5328 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK; 5329 5330 if (pi->sclk_ss) { 5331 struct amdgpu_atom_ss ss; 5332 u32 vco_freq = engine_clock * dividers.post_div; 5333 5334 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5335 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 5336 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 5337 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 5338 5339 cg_spll_spread_spectrum &= ~CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK; 5340 cg_spll_spread_spectrum |= clk_s << CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT; 5341 cg_spll_spread_spectrum |= CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK; 5342 5343 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK; 5344 cg_spll_spread_spectrum_2 |= clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT; 5345 } 5346 } 5347 5348 sclk->sclk_value = engine_clock; 5349 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 5350 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 5351 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 5352 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 5353 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 5354 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 5355 5356 return 0; 5357 } 5358 5359 static int si_populate_sclk_value(struct amdgpu_device *adev, 5360 u32 engine_clock, 5361 SISLANDS_SMC_SCLK_VALUE *sclk) 5362 { 5363 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 5364 int ret; 5365 5366 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); 5367 if (!ret) { 5368 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 5369 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 5370 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 5371 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 5372 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 5373 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 5374 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 5375 } 5376 5377 return ret; 5378 } 5379 5380 static int si_populate_mclk_value(struct amdgpu_device *adev, 5381 u32 engine_clock, 5382 u32 memory_clock, 5383 SISLANDS_SMC_MCLK_VALUE *mclk, 5384 bool strobe_mode, 5385 bool dll_state_on) 5386 { 5387 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5388 struct si_power_info *si_pi = si_get_pi(adev); 5389 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5390 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5391 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5392 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5393 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5394 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5395 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5396 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 5397 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 5398 struct atom_mpll_param mpll_param; 5399 int ret; 5400 5401 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); 5402 if (ret) 5403 return ret; 5404 5405 mpll_func_cntl &= ~BWCTRL_MASK; 5406 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 5407 5408 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 5409 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 5410 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 5411 5412 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 5413 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 5414 5415 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5416 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 5417 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 5418 YCLK_POST_DIV(mpll_param.post_div); 5419 } 5420 5421 if (pi->mclk_ss) { 5422 struct amdgpu_atom_ss ss; 5423 u32 freq_nom; 5424 u32 tmp; 5425 u32 reference_clock = adev->clock.mpll.reference_freq; 5426 5427 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5428 freq_nom = memory_clock * 4; 5429 else 5430 freq_nom = memory_clock * 2; 5431 5432 tmp = freq_nom / reference_clock; 5433 tmp = tmp * tmp; 5434 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5435 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 5436 u32 clks = reference_clock * 5 / ss.rate; 5437 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 5438 5439 mpll_ss1 &= ~CLKV_MASK; 5440 mpll_ss1 |= CLKV(clkv); 5441 5442 mpll_ss2 &= ~CLKS_MASK; 5443 mpll_ss2 |= CLKS(clks); 5444 } 5445 } 5446 5447 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 5448 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 5449 5450 if (dll_state_on) 5451 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 5452 else 5453 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5454 5455 mclk->mclk_value = cpu_to_be32(memory_clock); 5456 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 5457 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 5458 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 5459 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 5460 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 5461 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 5462 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 5463 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 5464 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 5465 5466 return 0; 5467 } 5468 5469 static void si_populate_smc_sp(struct amdgpu_device *adev, 5470 struct amdgpu_ps *amdgpu_state, 5471 SISLANDS_SMC_SWSTATE *smc_state) 5472 { 5473 struct si_ps *ps = si_get_ps(amdgpu_state); 5474 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5475 int i; 5476 5477 for (i = 0; i < ps->performance_level_count - 1; i++) 5478 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5479 5480 smc_state->levels[ps->performance_level_count - 1].bSP = 5481 cpu_to_be32(pi->psp); 5482 } 5483 5484 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 5485 struct rv7xx_pl *pl, 5486 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5487 { 5488 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5489 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5490 struct si_power_info *si_pi = si_get_pi(adev); 5491 int ret; 5492 bool dll_state_on; 5493 u16 std_vddc; 5494 5495 if (eg_pi->pcie_performance_request && 5496 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID)) 5497 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5498 else 5499 level->gen2PCIE = (u8)pl->pcie_gen; 5500 5501 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); 5502 if (ret) 5503 return ret; 5504 5505 level->mcFlags = 0; 5506 5507 if (pi->mclk_stutter_mode_threshold && 5508 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5509 !eg_pi->uvd_enabled && 5510 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) && 5511 (adev->pm.dpm.new_active_crtc_count <= 2)) { 5512 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5513 } 5514 5515 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5516 if (pl->mclk > pi->mclk_edc_enable_threshold) 5517 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5518 5519 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5520 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5521 5522 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); 5523 5524 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5525 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5526 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5527 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5528 else 5529 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5530 } else { 5531 dll_state_on = false; 5532 } 5533 } else { 5534 level->strobeMode = si_get_strobe_mode_settings(adev, 5535 pl->mclk); 5536 5537 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5538 } 5539 5540 ret = si_populate_mclk_value(adev, 5541 pl->sclk, 5542 pl->mclk, 5543 &level->mclk, 5544 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5545 if (ret) 5546 return ret; 5547 5548 ret = si_populate_voltage_value(adev, 5549 &eg_pi->vddc_voltage_table, 5550 pl->vddc, &level->vddc); 5551 if (ret) 5552 return ret; 5553 5554 5555 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); 5556 if (ret) 5557 return ret; 5558 5559 ret = si_populate_std_voltage_value(adev, std_vddc, 5560 level->vddc.index, &level->std_vddc); 5561 if (ret) 5562 return ret; 5563 5564 if (eg_pi->vddci_control) { 5565 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5566 pl->vddci, &level->vddci); 5567 if (ret) 5568 return ret; 5569 } 5570 5571 if (si_pi->vddc_phase_shed_control) { 5572 ret = si_populate_phase_shedding_value(adev, 5573 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5574 pl->vddc, 5575 pl->sclk, 5576 pl->mclk, 5577 &level->vddc); 5578 if (ret) 5579 return ret; 5580 } 5581 5582 level->MaxPoweredUpCU = si_pi->max_cu; 5583 5584 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); 5585 5586 return ret; 5587 } 5588 5589 static int si_populate_smc_t(struct amdgpu_device *adev, 5590 struct amdgpu_ps *amdgpu_state, 5591 SISLANDS_SMC_SWSTATE *smc_state) 5592 { 5593 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5594 struct si_ps *state = si_get_ps(amdgpu_state); 5595 u32 a_t; 5596 u32 t_l, t_h; 5597 u32 high_bsp; 5598 int i, ret; 5599 5600 if (state->performance_level_count >= 9) 5601 return -EINVAL; 5602 5603 if (state->performance_level_count < 2) { 5604 a_t = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT; 5605 smc_state->levels[0].aT = cpu_to_be32(a_t); 5606 return 0; 5607 } 5608 5609 smc_state->levels[0].aT = cpu_to_be32(0); 5610 5611 for (i = 0; i <= state->performance_level_count - 2; i++) { 5612 ret = r600_calculate_at( 5613 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5614 100 * R600_AH_DFLT, 5615 state->performance_levels[i + 1].sclk, 5616 state->performance_levels[i].sclk, 5617 &t_l, 5618 &t_h); 5619 5620 if (ret) { 5621 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5622 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5623 } 5624 5625 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_AT__CG_R_MASK; 5626 a_t |= (t_l * pi->bsp / 20000) << CG_AT__CG_R__SHIFT; 5627 smc_state->levels[i].aT = cpu_to_be32(a_t); 5628 5629 high_bsp = (i == state->performance_level_count - 2) ? 5630 pi->pbsp : pi->bsp; 5631 a_t = (0xffff) << CG_AT__CG_R__SHIFT | (t_h * high_bsp / 20000) << CG_AT__CG_L__SHIFT; 5632 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5633 } 5634 5635 return 0; 5636 } 5637 5638 static int si_disable_ulv(struct amdgpu_device *adev) 5639 { 5640 struct si_power_info *si_pi = si_get_pi(adev); 5641 struct si_ulv_param *ulv = &si_pi->ulv; 5642 5643 if (ulv->supported) 5644 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5645 0 : -EINVAL; 5646 5647 return 0; 5648 } 5649 5650 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, 5651 struct amdgpu_ps *amdgpu_state) 5652 { 5653 const struct si_power_info *si_pi = si_get_pi(adev); 5654 const struct si_ulv_param *ulv = &si_pi->ulv; 5655 const struct si_ps *state = si_get_ps(amdgpu_state); 5656 int i; 5657 5658 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5659 return false; 5660 5661 /* XXX validate against display requirements! */ 5662 5663 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5664 if (adev->clock.current_dispclk <= 5665 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5666 if (ulv->pl.vddc < 5667 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5668 return false; 5669 } 5670 } 5671 5672 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) 5673 return false; 5674 5675 return true; 5676 } 5677 5678 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, 5679 struct amdgpu_ps *amdgpu_new_state) 5680 { 5681 const struct si_power_info *si_pi = si_get_pi(adev); 5682 const struct si_ulv_param *ulv = &si_pi->ulv; 5683 5684 if (ulv->supported) { 5685 if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) 5686 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5687 0 : -EINVAL; 5688 } 5689 return 0; 5690 } 5691 5692 static int si_convert_power_state_to_smc(struct amdgpu_device *adev, 5693 struct amdgpu_ps *amdgpu_state, 5694 SISLANDS_SMC_SWSTATE *smc_state) 5695 { 5696 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5697 struct ni_power_info *ni_pi = ni_get_pi(adev); 5698 struct si_power_info *si_pi = si_get_pi(adev); 5699 struct si_ps *state = si_get_ps(amdgpu_state); 5700 int i, ret; 5701 u32 threshold; 5702 u32 sclk_in_sr = 1350; /* ??? */ 5703 5704 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5705 return -EINVAL; 5706 5707 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5708 5709 if (amdgpu_state->vclk && amdgpu_state->dclk) { 5710 eg_pi->uvd_enabled = true; 5711 if (eg_pi->smu_uvd_hs) 5712 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5713 } else { 5714 eg_pi->uvd_enabled = false; 5715 } 5716 5717 if (state->dc_compatible) 5718 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5719 5720 smc_state->levelCount = 0; 5721 for (i = 0; i < state->performance_level_count; i++) { 5722 if (eg_pi->sclk_deep_sleep) { 5723 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5724 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5725 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5726 else 5727 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5728 } 5729 } 5730 5731 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], 5732 &smc_state->levels[i]); 5733 smc_state->levels[i].arbRefreshState = 5734 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5735 5736 if (ret) 5737 return ret; 5738 5739 if (ni_pi->enable_power_containment) 5740 smc_state->levels[i].displayWatermark = 5741 (state->performance_levels[i].sclk < threshold) ? 5742 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5743 else 5744 smc_state->levels[i].displayWatermark = (i < 2) ? 5745 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5746 5747 if (eg_pi->dynamic_ac_timing) 5748 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5749 else 5750 smc_state->levels[i].ACIndex = 0; 5751 5752 smc_state->levelCount++; 5753 } 5754 5755 si_write_smc_soft_register(adev, 5756 SI_SMC_SOFT_REGISTER_watermark_threshold, 5757 threshold / 512); 5758 5759 si_populate_smc_sp(adev, amdgpu_state, smc_state); 5760 5761 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state); 5762 if (ret) 5763 ni_pi->enable_power_containment = false; 5764 5765 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state); 5766 if (ret) 5767 ni_pi->enable_sq_ramping = false; 5768 5769 return si_populate_smc_t(adev, amdgpu_state, smc_state); 5770 } 5771 5772 static int si_upload_sw_state(struct amdgpu_device *adev, 5773 struct amdgpu_ps *amdgpu_new_state) 5774 { 5775 struct si_power_info *si_pi = si_get_pi(adev); 5776 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 5777 int ret; 5778 u32 address = si_pi->state_table_start + 5779 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5780 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5781 size_t state_size = struct_size(smc_state, levels, 5782 new_state->performance_level_count); 5783 memset(smc_state, 0, state_size); 5784 5785 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); 5786 if (ret) 5787 return ret; 5788 5789 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5790 state_size, si_pi->sram_end); 5791 } 5792 5793 static int si_upload_ulv_state(struct amdgpu_device *adev) 5794 { 5795 struct si_power_info *si_pi = si_get_pi(adev); 5796 struct si_ulv_param *ulv = &si_pi->ulv; 5797 int ret = 0; 5798 5799 if (ulv->supported && ulv->pl.vddc) { 5800 u32 address = si_pi->state_table_start + 5801 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5802 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; 5803 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE); 5804 5805 memset(smc_state, 0, state_size); 5806 5807 ret = si_populate_ulv_state(adev, smc_state); 5808 if (!ret) 5809 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5810 state_size, si_pi->sram_end); 5811 } 5812 5813 return ret; 5814 } 5815 5816 static int si_upload_smc_data(struct amdgpu_device *adev) 5817 { 5818 struct amdgpu_crtc *amdgpu_crtc = NULL; 5819 int i; 5820 5821 if (adev->pm.dpm.new_active_crtc_count == 0) 5822 return 0; 5823 5824 for (i = 0; i < adev->mode_info.num_crtc; i++) { 5825 if (adev->pm.dpm.new_active_crtcs & (1 << i)) { 5826 amdgpu_crtc = adev->mode_info.crtcs[i]; 5827 break; 5828 } 5829 } 5830 5831 if (amdgpu_crtc == NULL) 5832 return 0; 5833 5834 if (amdgpu_crtc->line_time <= 0) 5835 return 0; 5836 5837 if (si_write_smc_soft_register(adev, 5838 SI_SMC_SOFT_REGISTER_crtc_index, 5839 amdgpu_crtc->crtc_id) != PPSMC_Result_OK) 5840 return 0; 5841 5842 if (si_write_smc_soft_register(adev, 5843 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5844 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK) 5845 return 0; 5846 5847 if (si_write_smc_soft_register(adev, 5848 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5849 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK) 5850 return 0; 5851 5852 return 0; 5853 } 5854 5855 static int si_set_mc_special_registers(struct amdgpu_device *adev, 5856 struct si_mc_reg_table *table) 5857 { 5858 u8 i, j, k; 5859 u32 temp_reg; 5860 5861 for (i = 0, j = table->last; i < table->last; i++) { 5862 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5863 return -EINVAL; 5864 switch (table->mc_reg_address[i].s1) { 5865 case MC_SEQ_MISC1: 5866 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5867 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; 5868 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; 5869 for (k = 0; k < table->num_entries; k++) 5870 table->mc_reg_table_entry[k].mc_data[j] = 5871 ((temp_reg & 0xffff0000)) | 5872 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5873 j++; 5874 5875 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5876 return -EINVAL; 5877 temp_reg = RREG32(MC_PMG_CMD_MRS); 5878 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; 5879 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; 5880 for (k = 0; k < table->num_entries; k++) { 5881 table->mc_reg_table_entry[k].mc_data[j] = 5882 (temp_reg & 0xffff0000) | 5883 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5884 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) 5885 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5886 } 5887 j++; 5888 5889 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { 5890 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5891 return -EINVAL; 5892 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; 5893 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; 5894 for (k = 0; k < table->num_entries; k++) 5895 table->mc_reg_table_entry[k].mc_data[j] = 5896 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5897 j++; 5898 } 5899 break; 5900 case MC_SEQ_RESERVE_M: 5901 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5902 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; 5903 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; 5904 for(k = 0; k < table->num_entries; k++) 5905 table->mc_reg_table_entry[k].mc_data[j] = 5906 (temp_reg & 0xffff0000) | 5907 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5908 j++; 5909 break; 5910 default: 5911 break; 5912 } 5913 } 5914 5915 table->last = j; 5916 5917 return 0; 5918 } 5919 5920 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5921 { 5922 bool result = true; 5923 switch (in_reg) { 5924 case MC_SEQ_RAS_TIMING: 5925 *out_reg = MC_SEQ_RAS_TIMING_LP; 5926 break; 5927 case MC_SEQ_CAS_TIMING: 5928 *out_reg = MC_SEQ_CAS_TIMING_LP; 5929 break; 5930 case MC_SEQ_MISC_TIMING: 5931 *out_reg = MC_SEQ_MISC_TIMING_LP; 5932 break; 5933 case MC_SEQ_MISC_TIMING2: 5934 *out_reg = MC_SEQ_MISC_TIMING2_LP; 5935 break; 5936 case MC_SEQ_RD_CTL_D0: 5937 *out_reg = MC_SEQ_RD_CTL_D0_LP; 5938 break; 5939 case MC_SEQ_RD_CTL_D1: 5940 *out_reg = MC_SEQ_RD_CTL_D1_LP; 5941 break; 5942 case MC_SEQ_WR_CTL_D0: 5943 *out_reg = MC_SEQ_WR_CTL_D0_LP; 5944 break; 5945 case MC_SEQ_WR_CTL_D1: 5946 *out_reg = MC_SEQ_WR_CTL_D1_LP; 5947 break; 5948 case MC_PMG_CMD_EMRS: 5949 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP; 5950 break; 5951 case MC_PMG_CMD_MRS: 5952 *out_reg = MC_SEQ_PMG_CMD_MRS_LP; 5953 break; 5954 case MC_PMG_CMD_MRS1: 5955 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP; 5956 break; 5957 case MC_SEQ_PMG_TIMING: 5958 *out_reg = MC_SEQ_PMG_TIMING_LP; 5959 break; 5960 case MC_PMG_CMD_MRS2: 5961 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP; 5962 break; 5963 case MC_SEQ_WR_CTL_2: 5964 *out_reg = MC_SEQ_WR_CTL_2_LP; 5965 break; 5966 default: 5967 result = false; 5968 break; 5969 } 5970 5971 return result; 5972 } 5973 5974 static void si_set_valid_flag(struct si_mc_reg_table *table) 5975 { 5976 u8 i, j; 5977 5978 for (i = 0; i < table->last; i++) { 5979 for (j = 1; j < table->num_entries; j++) { 5980 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5981 table->valid_flag |= 1 << i; 5982 break; 5983 } 5984 } 5985 } 5986 } 5987 5988 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5989 { 5990 u32 i; 5991 u16 address; 5992 5993 for (i = 0; i < table->last; i++) 5994 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5995 address : table->mc_reg_address[i].s1; 5996 5997 } 5998 5999 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 6000 struct si_mc_reg_table *si_table) 6001 { 6002 u8 i, j; 6003 6004 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6005 return -EINVAL; 6006 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 6007 return -EINVAL; 6008 6009 for (i = 0; i < table->last; i++) 6010 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 6011 si_table->last = table->last; 6012 6013 for (i = 0; i < table->num_entries; i++) { 6014 si_table->mc_reg_table_entry[i].mclk_max = 6015 table->mc_reg_table_entry[i].mclk_max; 6016 for (j = 0; j < table->last; j++) { 6017 si_table->mc_reg_table_entry[i].mc_data[j] = 6018 table->mc_reg_table_entry[i].mc_data[j]; 6019 } 6020 } 6021 si_table->num_entries = table->num_entries; 6022 6023 return 0; 6024 } 6025 6026 static int si_initialize_mc_reg_table(struct amdgpu_device *adev) 6027 { 6028 struct si_power_info *si_pi = si_get_pi(adev); 6029 struct atom_mc_reg_table *table; 6030 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 6031 u8 module_index = rv770_get_memory_module_index(adev); 6032 int ret; 6033 6034 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 6035 if (!table) 6036 return -ENOMEM; 6037 6038 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 6039 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 6040 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 6041 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 6042 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 6043 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 6044 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 6045 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 6046 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 6047 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 6048 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 6049 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 6050 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 6051 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 6052 6053 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); 6054 if (ret) 6055 goto init_mc_done; 6056 6057 ret = si_copy_vbios_mc_reg_table(table, si_table); 6058 if (ret) 6059 goto init_mc_done; 6060 6061 si_set_s0_mc_reg_index(si_table); 6062 6063 ret = si_set_mc_special_registers(adev, si_table); 6064 if (ret) 6065 goto init_mc_done; 6066 6067 si_set_valid_flag(si_table); 6068 6069 init_mc_done: 6070 kfree(table); 6071 6072 return ret; 6073 6074 } 6075 6076 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev, 6077 SMC_SIslands_MCRegisters *mc_reg_table) 6078 { 6079 struct si_power_info *si_pi = si_get_pi(adev); 6080 u32 i, j; 6081 6082 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 6083 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 6084 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6085 break; 6086 mc_reg_table->address[i].s0 = 6087 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 6088 mc_reg_table->address[i].s1 = 6089 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 6090 i++; 6091 } 6092 } 6093 mc_reg_table->last = (u8)i; 6094 } 6095 6096 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 6097 SMC_SIslands_MCRegisterSet *data, 6098 u32 num_entries, u32 valid_flag) 6099 { 6100 u32 i, j; 6101 6102 for(i = 0, j = 0; j < num_entries; j++) { 6103 if (valid_flag & (1 << j)) { 6104 data->value[i] = cpu_to_be32(entry->mc_data[j]); 6105 i++; 6106 } 6107 } 6108 } 6109 6110 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, 6111 struct rv7xx_pl *pl, 6112 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 6113 { 6114 struct si_power_info *si_pi = si_get_pi(adev); 6115 u32 i = 0; 6116 6117 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 6118 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 6119 break; 6120 } 6121 6122 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 6123 --i; 6124 6125 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 6126 mc_reg_table_data, si_pi->mc_reg_table.last, 6127 si_pi->mc_reg_table.valid_flag); 6128 } 6129 6130 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, 6131 struct amdgpu_ps *amdgpu_state, 6132 SMC_SIslands_MCRegisters *mc_reg_table) 6133 { 6134 struct si_ps *state = si_get_ps(amdgpu_state); 6135 int i; 6136 6137 for (i = 0; i < state->performance_level_count; i++) { 6138 si_convert_mc_reg_table_entry_to_smc(adev, 6139 &state->performance_levels[i], 6140 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 6141 } 6142 } 6143 6144 static int si_populate_mc_reg_table(struct amdgpu_device *adev, 6145 struct amdgpu_ps *amdgpu_boot_state) 6146 { 6147 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state); 6148 struct si_power_info *si_pi = si_get_pi(adev); 6149 struct si_ulv_param *ulv = &si_pi->ulv; 6150 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6151 6152 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6153 6154 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1); 6155 6156 si_populate_mc_reg_addresses(adev, smc_mc_reg_table); 6157 6158 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], 6159 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 6160 6161 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6162 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 6163 si_pi->mc_reg_table.last, 6164 si_pi->mc_reg_table.valid_flag); 6165 6166 if (ulv->supported && ulv->pl.vddc != 0) 6167 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, 6168 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 6169 else 6170 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6171 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 6172 si_pi->mc_reg_table.last, 6173 si_pi->mc_reg_table.valid_flag); 6174 6175 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); 6176 6177 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6178 (u8 *)smc_mc_reg_table, 6179 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6180 } 6181 6182 static int si_upload_mc_reg_table(struct amdgpu_device *adev, 6183 struct amdgpu_ps *amdgpu_new_state) 6184 { 6185 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 6186 struct si_power_info *si_pi = si_get_pi(adev); 6187 u32 address = si_pi->mc_reg_table_start + 6188 offsetof(SMC_SIslands_MCRegisters, 6189 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 6190 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6191 6192 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6193 6194 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); 6195 6196 return amdgpu_si_copy_bytes_to_smc(adev, address, 6197 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6198 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6199 si_pi->sram_end); 6200 } 6201 6202 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) 6203 { 6204 if (enable) 6205 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK); 6206 else 6207 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK); 6208 } 6209 6210 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev, 6211 struct amdgpu_ps *amdgpu_state) 6212 { 6213 struct si_ps *state = si_get_ps(amdgpu_state); 6214 int i; 6215 u16 pcie_speed, max_speed = 0; 6216 6217 for (i = 0; i < state->performance_level_count; i++) { 6218 pcie_speed = state->performance_levels[i].pcie_gen; 6219 if (max_speed < pcie_speed) 6220 max_speed = pcie_speed; 6221 } 6222 return max_speed; 6223 } 6224 6225 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev) 6226 { 6227 u32 speed_cntl; 6228 6229 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL) & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK; 6230 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 6231 6232 return (u16)speed_cntl; 6233 } 6234 6235 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, 6236 struct amdgpu_ps *amdgpu_new_state, 6237 struct amdgpu_ps *amdgpu_current_state) 6238 { 6239 struct si_power_info *si_pi = si_get_pi(adev); 6240 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6241 enum si_pcie_gen current_link_speed; 6242 6243 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID) 6244 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state); 6245 else 6246 current_link_speed = si_pi->force_pcie_gen; 6247 6248 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 6249 si_pi->pspp_notify_required = false; 6250 if (target_link_speed > current_link_speed) { 6251 switch (target_link_speed) { 6252 #if defined(CONFIG_ACPI) 6253 case SI_PCIE_GEN3: 6254 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 6255 break; 6256 si_pi->force_pcie_gen = SI_PCIE_GEN2; 6257 if (current_link_speed == SI_PCIE_GEN2) 6258 break; 6259 fallthrough; 6260 case SI_PCIE_GEN2: 6261 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 6262 break; 6263 fallthrough; 6264 #endif 6265 default: 6266 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); 6267 break; 6268 } 6269 } else { 6270 if (target_link_speed < current_link_speed) 6271 si_pi->pspp_notify_required = true; 6272 } 6273 } 6274 6275 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, 6276 struct amdgpu_ps *amdgpu_new_state, 6277 struct amdgpu_ps *amdgpu_current_state) 6278 { 6279 struct si_power_info *si_pi = si_get_pi(adev); 6280 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6281 u8 request; 6282 6283 if (si_pi->pspp_notify_required) { 6284 if (target_link_speed == SI_PCIE_GEN3) 6285 request = PCIE_PERF_REQ_PECI_GEN3; 6286 else if (target_link_speed == SI_PCIE_GEN2) 6287 request = PCIE_PERF_REQ_PECI_GEN2; 6288 else 6289 request = PCIE_PERF_REQ_PECI_GEN1; 6290 6291 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 6292 (si_get_current_pcie_speed(adev) > 0)) 6293 return; 6294 6295 #if defined(CONFIG_ACPI) 6296 amdgpu_acpi_pcie_performance_request(adev, request, false); 6297 #endif 6298 } 6299 } 6300 6301 #if 0 6302 static int si_ds_request(struct amdgpu_device *adev, 6303 bool ds_status_on, u32 count_write) 6304 { 6305 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6306 6307 if (eg_pi->sclk_deep_sleep) { 6308 if (ds_status_on) 6309 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6310 PPSMC_Result_OK) ? 6311 0 : -EINVAL; 6312 else 6313 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6314 PPSMC_Result_OK) ? 0 : -EINVAL; 6315 } 6316 return 0; 6317 } 6318 #endif 6319 6320 static void si_set_max_cu_value(struct amdgpu_device *adev) 6321 { 6322 struct si_power_info *si_pi = si_get_pi(adev); 6323 6324 if (adev->asic_type == CHIP_VERDE) { 6325 switch (adev->pdev->device) { 6326 case 0x6820: 6327 case 0x6825: 6328 case 0x6821: 6329 case 0x6823: 6330 case 0x6827: 6331 si_pi->max_cu = 10; 6332 break; 6333 case 0x682D: 6334 case 0x6824: 6335 case 0x682F: 6336 case 0x6826: 6337 si_pi->max_cu = 8; 6338 break; 6339 case 0x6828: 6340 case 0x6830: 6341 case 0x6831: 6342 case 0x6838: 6343 case 0x6839: 6344 case 0x683D: 6345 si_pi->max_cu = 10; 6346 break; 6347 case 0x683B: 6348 case 0x683F: 6349 case 0x6829: 6350 si_pi->max_cu = 8; 6351 break; 6352 default: 6353 si_pi->max_cu = 0; 6354 break; 6355 } 6356 } else { 6357 si_pi->max_cu = 0; 6358 } 6359 } 6360 6361 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, 6362 struct amdgpu_clock_voltage_dependency_table *table) 6363 { 6364 u32 i; 6365 int j; 6366 u16 leakage_voltage; 6367 6368 if (table) { 6369 for (i = 0; i < table->count; i++) { 6370 switch (si_get_leakage_voltage_from_leakage_index(adev, 6371 table->entries[i].v, 6372 &leakage_voltage)) { 6373 case 0: 6374 table->entries[i].v = leakage_voltage; 6375 break; 6376 case -EAGAIN: 6377 return -EINVAL; 6378 case -EINVAL: 6379 default: 6380 break; 6381 } 6382 } 6383 6384 for (j = (table->count - 2); j >= 0; j--) { 6385 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 6386 table->entries[j].v : table->entries[j + 1].v; 6387 } 6388 } 6389 return 0; 6390 } 6391 6392 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) 6393 { 6394 int ret = 0; 6395 6396 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6397 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 6398 if (ret) 6399 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n"); 6400 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6401 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 6402 if (ret) 6403 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n"); 6404 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6405 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 6406 if (ret) 6407 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n"); 6408 return ret; 6409 } 6410 6411 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, 6412 struct amdgpu_ps *amdgpu_new_state, 6413 struct amdgpu_ps *amdgpu_current_state) 6414 { 6415 u32 lane_width; 6416 u32 new_lane_width = 6417 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6418 u32 current_lane_width = 6419 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6420 6421 if (new_lane_width != current_lane_width) { 6422 amdgpu_set_pcie_lanes(adev, new_lane_width); 6423 lane_width = amdgpu_get_pcie_lanes(adev); 6424 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 6425 } 6426 } 6427 6428 static void si_dpm_setup_asic(struct amdgpu_device *adev) 6429 { 6430 si_read_clock_registers(adev); 6431 si_enable_acpi_power_management(adev); 6432 } 6433 6434 static int si_thermal_enable_alert(struct amdgpu_device *adev, 6435 bool enable) 6436 { 6437 u32 thermal_int = RREG32(mmCG_THERMAL_INT); 6438 6439 if (enable) { 6440 PPSMC_Result result; 6441 6442 thermal_int &= ~(CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK); 6443 WREG32(mmCG_THERMAL_INT, thermal_int); 6444 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6445 if (result != PPSMC_Result_OK) { 6446 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6447 return -EINVAL; 6448 } 6449 } else { 6450 thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 6451 WREG32(mmCG_THERMAL_INT, thermal_int); 6452 } 6453 6454 return 0; 6455 } 6456 6457 static int si_thermal_set_temperature_range(struct amdgpu_device *adev, 6458 int min_temp, int max_temp) 6459 { 6460 int low_temp = 0 * 1000; 6461 int high_temp = 255 * 1000; 6462 6463 if (low_temp < min_temp) 6464 low_temp = min_temp; 6465 if (high_temp > max_temp) 6466 high_temp = max_temp; 6467 if (high_temp < low_temp) { 6468 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6469 return -EINVAL; 6470 } 6471 6472 WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK); 6473 WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK); 6474 WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK); 6475 6476 adev->pm.dpm.thermal.min_temp = low_temp; 6477 adev->pm.dpm.thermal.max_temp = high_temp; 6478 6479 return 0; 6480 } 6481 6482 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) 6483 { 6484 struct si_power_info *si_pi = si_get_pi(adev); 6485 u32 tmp; 6486 6487 if (si_pi->fan_ctrl_is_in_default_mode) { 6488 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6489 si_pi->fan_ctrl_default_mode = tmp; 6490 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT; 6491 si_pi->t_min = tmp; 6492 si_pi->fan_ctrl_is_in_default_mode = false; 6493 } 6494 6495 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; 6496 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT; 6497 WREG32(mmCG_FDO_CTRL2, tmp); 6498 6499 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6500 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6501 WREG32(mmCG_FDO_CTRL2, tmp); 6502 } 6503 6504 static int si_thermal_setup_fan_table(struct amdgpu_device *adev) 6505 { 6506 struct si_power_info *si_pi = si_get_pi(adev); 6507 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6508 u32 duty100; 6509 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6510 u16 fdo_min, slope1, slope2; 6511 u32 reference_clock, tmp; 6512 int ret; 6513 u64 tmp64; 6514 6515 if (!si_pi->fan_table_start) { 6516 adev->pm.dpm.fan.ucode_fan_control = false; 6517 return 0; 6518 } 6519 6520 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6521 6522 if (duty100 == 0) { 6523 adev->pm.dpm.fan.ucode_fan_control = false; 6524 return 0; 6525 } 6526 6527 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; 6528 do_div(tmp64, 10000); 6529 fdo_min = (u16)tmp64; 6530 6531 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; 6532 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; 6533 6534 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; 6535 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; 6536 6537 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6538 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6539 6540 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); 6541 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); 6542 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); 6543 fan_table.slope1 = cpu_to_be16(slope1); 6544 fan_table.slope2 = cpu_to_be16(slope2); 6545 fan_table.fdo_min = cpu_to_be16(fdo_min); 6546 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); 6547 fan_table.hys_up = cpu_to_be16(1); 6548 fan_table.hys_slope = cpu_to_be16(1); 6549 fan_table.temp_resp_lim = cpu_to_be16(5); 6550 reference_clock = amdgpu_asic_get_xclk(adev); 6551 6552 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * 6553 reference_clock) / 1600); 6554 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6555 6556 tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT; 6557 fan_table.temp_src = (uint8_t)tmp; 6558 6559 ret = amdgpu_si_copy_bytes_to_smc(adev, 6560 si_pi->fan_table_start, 6561 (u8 *)(&fan_table), 6562 sizeof(fan_table), 6563 si_pi->sram_end); 6564 6565 if (ret) { 6566 DRM_ERROR("Failed to load fan table to the SMC."); 6567 adev->pm.dpm.fan.ucode_fan_control = false; 6568 } 6569 6570 return ret; 6571 } 6572 6573 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) 6574 { 6575 struct si_power_info *si_pi = si_get_pi(adev); 6576 PPSMC_Result ret; 6577 6578 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6579 if (ret == PPSMC_Result_OK) { 6580 si_pi->fan_is_controlled_by_smc = true; 6581 return 0; 6582 } else { 6583 return -EINVAL; 6584 } 6585 } 6586 6587 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) 6588 { 6589 struct si_power_info *si_pi = si_get_pi(adev); 6590 PPSMC_Result ret; 6591 6592 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6593 6594 if (ret == PPSMC_Result_OK) { 6595 si_pi->fan_is_controlled_by_smc = false; 6596 return 0; 6597 } else { 6598 return -EINVAL; 6599 } 6600 } 6601 6602 static int si_dpm_get_fan_speed_pwm(void *handle, 6603 u32 *speed) 6604 { 6605 u32 duty, duty100; 6606 u64 tmp64; 6607 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6608 6609 if (!speed) 6610 return -EINVAL; 6611 6612 if (adev->pm.no_fan) 6613 return -ENOENT; 6614 6615 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6616 duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT; 6617 6618 if (duty100 == 0) 6619 return -EINVAL; 6620 6621 tmp64 = (u64)duty * 255; 6622 do_div(tmp64, duty100); 6623 *speed = min_t(u32, tmp64, 255); 6624 6625 return 0; 6626 } 6627 6628 static int si_dpm_set_fan_speed_pwm(void *handle, 6629 u32 speed) 6630 { 6631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6632 struct si_power_info *si_pi = si_get_pi(adev); 6633 u32 tmp; 6634 u32 duty, duty100; 6635 u64 tmp64; 6636 6637 if (adev->pm.no_fan) 6638 return -ENOENT; 6639 6640 if (si_pi->fan_is_controlled_by_smc) 6641 return -EINVAL; 6642 6643 if (speed > 255) 6644 return -EINVAL; 6645 6646 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6647 6648 if (duty100 == 0) 6649 return -EINVAL; 6650 6651 tmp64 = (u64)speed * duty100; 6652 do_div(tmp64, 255); 6653 duty = (u32)tmp64; 6654 6655 tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK; 6656 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT; 6657 WREG32(mmCG_FDO_CTRL0, tmp); 6658 6659 return 0; 6660 } 6661 6662 static int si_dpm_set_fan_control_mode(void *handle, u32 mode) 6663 { 6664 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6665 6666 if (mode == U32_MAX) 6667 return -EINVAL; 6668 6669 if (mode) { 6670 /* stop auto-manage */ 6671 if (adev->pm.dpm.fan.ucode_fan_control) 6672 si_fan_ctrl_stop_smc_fan_control(adev); 6673 si_fan_ctrl_set_static_mode(adev, mode); 6674 } else { 6675 /* restart auto-manage */ 6676 if (adev->pm.dpm.fan.ucode_fan_control) 6677 si_thermal_start_smc_fan_control(adev); 6678 else 6679 si_fan_ctrl_set_default_mode(adev); 6680 } 6681 6682 return 0; 6683 } 6684 6685 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode) 6686 { 6687 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6688 struct si_power_info *si_pi = si_get_pi(adev); 6689 u32 tmp; 6690 6691 if (!fan_mode) 6692 return -EINVAL; 6693 6694 if (si_pi->fan_is_controlled_by_smc) 6695 return 0; 6696 6697 tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6698 *fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT); 6699 6700 return 0; 6701 } 6702 6703 #if 0 6704 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, 6705 u32 *speed) 6706 { 6707 u32 tach_period; 6708 u32 xclk = amdgpu_asic_get_xclk(adev); 6709 6710 if (adev->pm.no_fan) 6711 return -ENOENT; 6712 6713 if (adev->pm.fan_pulses_per_revolution == 0) 6714 return -ENOENT; 6715 6716 tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT; 6717 if (tach_period == 0) 6718 return -ENOENT; 6719 6720 *speed = 60 * xclk * 10000 / tach_period; 6721 6722 return 0; 6723 } 6724 6725 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, 6726 u32 speed) 6727 { 6728 u32 tach_period, tmp; 6729 u32 xclk = amdgpu_asic_get_xclk(adev); 6730 6731 if (adev->pm.no_fan) 6732 return -ENOENT; 6733 6734 if (adev->pm.fan_pulses_per_revolution == 0) 6735 return -ENOENT; 6736 6737 if ((speed < adev->pm.fan_min_rpm) || 6738 (speed > adev->pm.fan_max_rpm)) 6739 return -EINVAL; 6740 6741 if (adev->pm.dpm.fan.ucode_fan_control) 6742 si_fan_ctrl_stop_smc_fan_control(adev); 6743 6744 tach_period = 60 * xclk * 10000 / (8 * speed); 6745 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK; 6746 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT; 6747 WREG32(mmCG_TACH_CTRL, tmp); 6748 6749 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); 6750 6751 return 0; 6752 } 6753 #endif 6754 6755 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) 6756 { 6757 struct si_power_info *si_pi = si_get_pi(adev); 6758 u32 tmp; 6759 6760 if (!si_pi->fan_ctrl_is_in_default_mode) { 6761 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6762 tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6763 WREG32(mmCG_FDO_CTRL2, tmp); 6764 6765 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; 6766 tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT; 6767 WREG32(mmCG_FDO_CTRL2, tmp); 6768 si_pi->fan_ctrl_is_in_default_mode = true; 6769 } 6770 } 6771 6772 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev) 6773 { 6774 if (adev->pm.dpm.fan.ucode_fan_control) { 6775 si_fan_ctrl_start_smc_fan_control(adev); 6776 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); 6777 } 6778 } 6779 6780 static void si_thermal_initialize(struct amdgpu_device *adev) 6781 { 6782 u32 tmp; 6783 6784 if (adev->pm.fan_pulses_per_revolution) { 6785 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK; 6786 tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT; 6787 WREG32(mmCG_TACH_CTRL, tmp); 6788 } 6789 6790 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK; 6791 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT; 6792 WREG32(mmCG_FDO_CTRL2, tmp); 6793 } 6794 6795 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev) 6796 { 6797 int ret; 6798 6799 si_thermal_initialize(adev); 6800 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6801 if (ret) 6802 return ret; 6803 ret = si_thermal_enable_alert(adev, true); 6804 if (ret) 6805 return ret; 6806 if (adev->pm.dpm.fan.ucode_fan_control) { 6807 ret = si_halt_smc(adev); 6808 if (ret) 6809 return ret; 6810 ret = si_thermal_setup_fan_table(adev); 6811 if (ret) 6812 return ret; 6813 ret = si_resume_smc(adev); 6814 if (ret) 6815 return ret; 6816 si_thermal_start_smc_fan_control(adev); 6817 } 6818 6819 return 0; 6820 } 6821 6822 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev) 6823 { 6824 if (!adev->pm.no_fan) { 6825 si_fan_ctrl_set_default_mode(adev); 6826 si_fan_ctrl_stop_smc_fan_control(adev); 6827 } 6828 } 6829 6830 static int si_dpm_enable(struct amdgpu_device *adev) 6831 { 6832 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6833 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6834 struct si_power_info *si_pi = si_get_pi(adev); 6835 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6836 int ret; 6837 6838 if (amdgpu_si_is_smc_running(adev)) 6839 return -EINVAL; 6840 if (pi->voltage_control || si_pi->voltage_control_svi2) 6841 si_enable_voltage_control(adev, true); 6842 if (pi->mvdd_control) 6843 si_get_mvdd_configuration(adev); 6844 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6845 ret = si_construct_voltage_tables(adev); 6846 if (ret) { 6847 DRM_ERROR("si_construct_voltage_tables failed\n"); 6848 return ret; 6849 } 6850 } 6851 if (eg_pi->dynamic_ac_timing) { 6852 ret = si_initialize_mc_reg_table(adev); 6853 if (ret) 6854 eg_pi->dynamic_ac_timing = false; 6855 } 6856 if (pi->dynamic_ss) 6857 si_enable_spread_spectrum(adev, true); 6858 if (pi->thermal_protection) 6859 si_enable_thermal_protection(adev, true); 6860 si_setup_bsp(adev); 6861 si_program_git(adev); 6862 si_program_tp(adev); 6863 si_program_tpp(adev); 6864 si_program_sstp(adev); 6865 si_enable_display_gap(adev); 6866 si_program_vc(adev); 6867 ret = si_upload_firmware(adev); 6868 if (ret) { 6869 DRM_ERROR("si_upload_firmware failed\n"); 6870 return ret; 6871 } 6872 ret = si_process_firmware_header(adev); 6873 if (ret) { 6874 DRM_ERROR("si_process_firmware_header failed\n"); 6875 return ret; 6876 } 6877 ret = si_initial_switch_from_arb_f0_to_f1(adev); 6878 if (ret) { 6879 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6880 return ret; 6881 } 6882 ret = si_init_smc_table(adev); 6883 if (ret) { 6884 DRM_ERROR("si_init_smc_table failed\n"); 6885 return ret; 6886 } 6887 ret = si_init_smc_spll_table(adev); 6888 if (ret) { 6889 DRM_ERROR("si_init_smc_spll_table failed\n"); 6890 return ret; 6891 } 6892 ret = si_init_arb_table_index(adev); 6893 if (ret) { 6894 DRM_ERROR("si_init_arb_table_index failed\n"); 6895 return ret; 6896 } 6897 if (eg_pi->dynamic_ac_timing) { 6898 ret = si_populate_mc_reg_table(adev, boot_ps); 6899 if (ret) { 6900 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6901 return ret; 6902 } 6903 } 6904 ret = si_initialize_smc_cac_tables(adev); 6905 if (ret) { 6906 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6907 return ret; 6908 } 6909 ret = si_initialize_hardware_cac_manager(adev); 6910 if (ret) { 6911 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6912 return ret; 6913 } 6914 ret = si_initialize_smc_dte_tables(adev); 6915 if (ret) { 6916 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6917 return ret; 6918 } 6919 ret = si_populate_smc_tdp_limits(adev, boot_ps); 6920 if (ret) { 6921 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6922 return ret; 6923 } 6924 ret = si_populate_smc_tdp_limits_2(adev, boot_ps); 6925 if (ret) { 6926 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6927 return ret; 6928 } 6929 si_program_response_times(adev); 6930 si_program_ds_registers(adev); 6931 si_dpm_start_smc(adev); 6932 ret = si_notify_smc_display_change(adev, false); 6933 if (ret) { 6934 DRM_ERROR("si_notify_smc_display_change failed\n"); 6935 return ret; 6936 } 6937 si_enable_sclk_control(adev, true); 6938 si_start_dpm(adev); 6939 6940 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6941 si_thermal_start_thermal_controller(adev); 6942 6943 ni_update_current_ps(adev, boot_ps); 6944 6945 return 0; 6946 } 6947 6948 static int si_set_temperature_range(struct amdgpu_device *adev) 6949 { 6950 int ret; 6951 6952 ret = si_thermal_enable_alert(adev, false); 6953 if (ret) 6954 return ret; 6955 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6956 if (ret) 6957 return ret; 6958 ret = si_thermal_enable_alert(adev, true); 6959 if (ret) 6960 return ret; 6961 6962 return ret; 6963 } 6964 6965 static void si_dpm_disable(struct amdgpu_device *adev) 6966 { 6967 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6968 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6969 6970 if (!amdgpu_si_is_smc_running(adev)) 6971 return; 6972 si_thermal_stop_thermal_controller(adev); 6973 si_disable_ulv(adev); 6974 si_clear_vc(adev); 6975 if (pi->thermal_protection) 6976 si_enable_thermal_protection(adev, false); 6977 si_enable_power_containment(adev, boot_ps, false); 6978 si_enable_smc_cac(adev, boot_ps, false); 6979 si_enable_spread_spectrum(adev, false); 6980 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6981 si_stop_dpm(adev); 6982 si_reset_to_default(adev); 6983 si_dpm_stop_smc(adev); 6984 si_force_switch_to_arb_f0(adev); 6985 6986 ni_update_current_ps(adev, boot_ps); 6987 } 6988 6989 static int si_dpm_pre_set_power_state(void *handle) 6990 { 6991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6992 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6993 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 6994 struct amdgpu_ps *new_ps = &requested_ps; 6995 6996 ni_update_requested_ps(adev, new_ps); 6997 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); 6998 6999 return 0; 7000 } 7001 7002 static int si_power_control_set_level(struct amdgpu_device *adev) 7003 { 7004 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; 7005 int ret; 7006 7007 ret = si_restrict_performance_levels_before_switch(adev); 7008 if (ret) 7009 return ret; 7010 ret = si_halt_smc(adev); 7011 if (ret) 7012 return ret; 7013 ret = si_populate_smc_tdp_limits(adev, new_ps); 7014 if (ret) 7015 return ret; 7016 ret = si_populate_smc_tdp_limits_2(adev, new_ps); 7017 if (ret) 7018 return ret; 7019 ret = si_resume_smc(adev); 7020 if (ret) 7021 return ret; 7022 return si_set_sw_state(adev); 7023 } 7024 7025 static void si_set_vce_clock(struct amdgpu_device *adev, 7026 struct amdgpu_ps *new_rps, 7027 struct amdgpu_ps *old_rps) 7028 { 7029 if ((old_rps->evclk != new_rps->evclk) || 7030 (old_rps->ecclk != new_rps->ecclk)) { 7031 /* Turn the clocks on when encoding, off otherwise */ 7032 if (new_rps->evclk || new_rps->ecclk) { 7033 /* Place holder for future VCE1.0 porting to amdgpu 7034 vce_v1_0_enable_mgcg(adev, false, false);*/ 7035 } else { 7036 /* Place holder for future VCE1.0 porting to amdgpu 7037 vce_v1_0_enable_mgcg(adev, true, false); 7038 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/ 7039 } 7040 } 7041 } 7042 7043 static int si_dpm_set_power_state(void *handle) 7044 { 7045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7046 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7047 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7048 struct amdgpu_ps *old_ps = &eg_pi->current_rps; 7049 int ret; 7050 7051 ret = si_disable_ulv(adev); 7052 if (ret) { 7053 DRM_ERROR("si_disable_ulv failed\n"); 7054 return ret; 7055 } 7056 ret = si_restrict_performance_levels_before_switch(adev); 7057 if (ret) { 7058 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 7059 return ret; 7060 } 7061 if (eg_pi->pcie_performance_request) 7062 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps); 7063 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps); 7064 ret = si_enable_power_containment(adev, new_ps, false); 7065 if (ret) { 7066 DRM_ERROR("si_enable_power_containment failed\n"); 7067 return ret; 7068 } 7069 ret = si_enable_smc_cac(adev, new_ps, false); 7070 if (ret) { 7071 DRM_ERROR("si_enable_smc_cac failed\n"); 7072 return ret; 7073 } 7074 ret = si_halt_smc(adev); 7075 if (ret) { 7076 DRM_ERROR("si_halt_smc failed\n"); 7077 return ret; 7078 } 7079 ret = si_upload_sw_state(adev, new_ps); 7080 if (ret) { 7081 DRM_ERROR("si_upload_sw_state failed\n"); 7082 return ret; 7083 } 7084 ret = si_upload_smc_data(adev); 7085 if (ret) { 7086 DRM_ERROR("si_upload_smc_data failed\n"); 7087 return ret; 7088 } 7089 ret = si_upload_ulv_state(adev); 7090 if (ret) { 7091 DRM_ERROR("si_upload_ulv_state failed\n"); 7092 return ret; 7093 } 7094 if (eg_pi->dynamic_ac_timing) { 7095 ret = si_upload_mc_reg_table(adev, new_ps); 7096 if (ret) { 7097 DRM_ERROR("si_upload_mc_reg_table failed\n"); 7098 return ret; 7099 } 7100 } 7101 ret = si_program_memory_timing_parameters(adev, new_ps); 7102 if (ret) { 7103 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 7104 return ret; 7105 } 7106 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps); 7107 7108 ret = si_resume_smc(adev); 7109 if (ret) { 7110 DRM_ERROR("si_resume_smc failed\n"); 7111 return ret; 7112 } 7113 ret = si_set_sw_state(adev); 7114 if (ret) { 7115 DRM_ERROR("si_set_sw_state failed\n"); 7116 return ret; 7117 } 7118 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps); 7119 si_set_vce_clock(adev, new_ps, old_ps); 7120 if (eg_pi->pcie_performance_request) 7121 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); 7122 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps); 7123 if (ret) { 7124 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 7125 return ret; 7126 } 7127 ret = si_enable_smc_cac(adev, new_ps, true); 7128 if (ret) { 7129 DRM_ERROR("si_enable_smc_cac failed\n"); 7130 return ret; 7131 } 7132 ret = si_enable_power_containment(adev, new_ps, true); 7133 if (ret) { 7134 DRM_ERROR("si_enable_power_containment failed\n"); 7135 return ret; 7136 } 7137 7138 ret = si_power_control_set_level(adev); 7139 if (ret) { 7140 DRM_ERROR("si_power_control_set_level failed\n"); 7141 return ret; 7142 } 7143 7144 return 0; 7145 } 7146 7147 static void si_dpm_post_set_power_state(void *handle) 7148 { 7149 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7150 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7151 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7152 7153 ni_update_current_ps(adev, new_ps); 7154 } 7155 7156 #if 0 7157 void si_dpm_reset_asic(struct amdgpu_device *adev) 7158 { 7159 si_restrict_performance_levels_before_switch(adev); 7160 si_disable_ulv(adev); 7161 si_set_boot_state(adev); 7162 } 7163 #endif 7164 7165 static void si_dpm_display_configuration_changed(void *handle) 7166 { 7167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7168 7169 si_program_display_gap(adev); 7170 } 7171 7172 7173 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, 7174 struct amdgpu_ps *rps, 7175 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 7176 u8 table_rev) 7177 { 7178 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 7179 rps->class = le16_to_cpu(non_clock_info->usClassification); 7180 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 7181 7182 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 7183 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 7184 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 7185 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 7186 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 7187 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 7188 } else { 7189 rps->vclk = 0; 7190 rps->dclk = 0; 7191 } 7192 7193 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 7194 adev->pm.dpm.boot_ps = rps; 7195 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 7196 adev->pm.dpm.uvd_ps = rps; 7197 } 7198 7199 static void si_parse_pplib_clock_info(struct amdgpu_device *adev, 7200 struct amdgpu_ps *rps, int index, 7201 union pplib_clock_info *clock_info) 7202 { 7203 struct rv7xx_power_info *pi = rv770_get_pi(adev); 7204 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7205 struct si_power_info *si_pi = si_get_pi(adev); 7206 struct si_ps *ps = si_get_ps(rps); 7207 u16 leakage_voltage; 7208 struct rv7xx_pl *pl = &ps->performance_levels[index]; 7209 int ret; 7210 7211 ps->performance_level_count = index + 1; 7212 7213 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7214 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 7215 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7216 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 7217 7218 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 7219 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 7220 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 7221 pl->pcie_gen = si_gen_pcie_gen_support(adev, 7222 si_pi->sys_pcie_mask, 7223 si_pi->boot_pcie_gen, 7224 clock_info->si.ucPCIEGen); 7225 7226 /* patch up vddc if necessary */ 7227 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, 7228 &leakage_voltage); 7229 if (ret == 0) 7230 pl->vddc = leakage_voltage; 7231 7232 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 7233 pi->acpi_vddc = pl->vddc; 7234 eg_pi->acpi_vddci = pl->vddci; 7235 si_pi->acpi_pcie_gen = pl->pcie_gen; 7236 } 7237 7238 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 7239 index == 0) { 7240 /* XXX disable for A0 tahiti */ 7241 si_pi->ulv.supported = false; 7242 si_pi->ulv.pl = *pl; 7243 si_pi->ulv.one_pcie_lane_in_ulv = false; 7244 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 7245 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 7246 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 7247 } 7248 7249 if (pi->min_vddc_in_table > pl->vddc) 7250 pi->min_vddc_in_table = pl->vddc; 7251 7252 if (pi->max_vddc_in_table < pl->vddc) 7253 pi->max_vddc_in_table = pl->vddc; 7254 7255 /* patch up boot state */ 7256 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 7257 u16 vddc, vddci, mvdd; 7258 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd); 7259 pl->mclk = adev->clock.default_mclk; 7260 pl->sclk = adev->clock.default_sclk; 7261 pl->vddc = vddc; 7262 pl->vddci = vddci; 7263 si_pi->mvdd_bootup_value = mvdd; 7264 } 7265 7266 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 7267 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 7268 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 7269 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 7270 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 7271 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 7272 } 7273 } 7274 7275 union pplib_power_state { 7276 struct _ATOM_PPLIB_STATE v1; 7277 struct _ATOM_PPLIB_STATE_V2 v2; 7278 }; 7279 7280 static int si_parse_power_table(struct amdgpu_device *adev) 7281 { 7282 struct amdgpu_mode_info *mode_info = &adev->mode_info; 7283 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 7284 union pplib_power_state *power_state; 7285 int i, j, k, non_clock_array_index, clock_array_index; 7286 union pplib_clock_info *clock_info; 7287 struct _StateArray *state_array; 7288 struct _ClockInfoArray *clock_info_array; 7289 struct _NonClockInfoArray *non_clock_info_array; 7290 union power_info *power_info; 7291 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 7292 u16 data_offset; 7293 u8 frev, crev; 7294 u8 *power_state_offset; 7295 struct si_ps *ps; 7296 7297 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 7298 &frev, &crev, &data_offset)) 7299 return -EINVAL; 7300 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 7301 7302 amdgpu_add_thermal_controller(adev); 7303 7304 state_array = (struct _StateArray *) 7305 (mode_info->atom_context->bios + data_offset + 7306 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 7307 clock_info_array = (struct _ClockInfoArray *) 7308 (mode_info->atom_context->bios + data_offset + 7309 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 7310 non_clock_info_array = (struct _NonClockInfoArray *) 7311 (mode_info->atom_context->bios + data_offset + 7312 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 7313 7314 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 7315 sizeof(struct amdgpu_ps), 7316 GFP_KERNEL); 7317 if (!adev->pm.dpm.ps) 7318 return -ENOMEM; 7319 power_state_offset = (u8 *)state_array->states; 7320 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { 7321 u8 *idx; 7322 power_state = (union pplib_power_state *)power_state_offset; 7323 non_clock_array_index = power_state->v2.nonClockInfoIndex; 7324 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 7325 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 7326 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL); 7327 if (ps == NULL) 7328 return -ENOMEM; 7329 adev->pm.dpm.ps[i].ps_priv = ps; 7330 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], 7331 non_clock_info, 7332 non_clock_info_array->ucEntrySize); 7333 k = 0; 7334 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 7335 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 7336 clock_array_index = idx[j]; 7337 if (clock_array_index >= clock_info_array->ucNumEntries) 7338 continue; 7339 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 7340 break; 7341 clock_info = (union pplib_clock_info *) 7342 ((u8 *)&clock_info_array->clockInfo[0] + 7343 (clock_array_index * clock_info_array->ucEntrySize)); 7344 si_parse_pplib_clock_info(adev, 7345 &adev->pm.dpm.ps[i], k, 7346 clock_info); 7347 k++; 7348 } 7349 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 7350 adev->pm.dpm.num_ps++; 7351 } 7352 7353 /* fill in the vce power states */ 7354 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 7355 u32 sclk, mclk; 7356 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 7357 clock_info = (union pplib_clock_info *) 7358 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 7359 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7360 sclk |= clock_info->si.ucEngineClockHigh << 16; 7361 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7362 mclk |= clock_info->si.ucMemoryClockHigh << 16; 7363 adev->pm.dpm.vce_states[i].sclk = sclk; 7364 adev->pm.dpm.vce_states[i].mclk = mclk; 7365 } 7366 7367 return 0; 7368 } 7369 7370 static int si_dpm_init(struct amdgpu_device *adev) 7371 { 7372 struct rv7xx_power_info *pi; 7373 struct evergreen_power_info *eg_pi; 7374 struct ni_power_info *ni_pi; 7375 struct si_power_info *si_pi; 7376 struct atom_clock_dividers dividers; 7377 int ret; 7378 7379 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 7380 if (si_pi == NULL) 7381 return -ENOMEM; 7382 adev->pm.dpm.priv = si_pi; 7383 ni_pi = &si_pi->ni; 7384 eg_pi = &ni_pi->eg; 7385 pi = &eg_pi->rv7xx; 7386 7387 si_pi->sys_pcie_mask = 7388 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK; 7389 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 7390 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); 7391 7392 si_set_max_cu_value(adev); 7393 7394 rv770_get_max_vddc(adev); 7395 si_get_leakage_vddc(adev); 7396 si_patch_dependency_tables_based_on_leakage(adev); 7397 7398 pi->acpi_vddc = 0; 7399 eg_pi->acpi_vddci = 0; 7400 pi->min_vddc_in_table = 0; 7401 pi->max_vddc_in_table = 0; 7402 7403 ret = amdgpu_get_platform_caps(adev); 7404 if (ret) 7405 return ret; 7406 7407 ret = amdgpu_parse_extended_power_table(adev); 7408 if (ret) 7409 return ret; 7410 7411 ret = si_parse_power_table(adev); 7412 if (ret) 7413 return ret; 7414 7415 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 7416 kcalloc(4, 7417 sizeof(struct amdgpu_clock_voltage_dependency_entry), 7418 GFP_KERNEL); 7419 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) 7420 return -ENOMEM; 7421 7422 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 7423 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 7424 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 7425 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 7426 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 7427 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 7428 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 7429 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 7430 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 7431 7432 if (adev->pm.dpm.voltage_response_time == 0) 7433 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 7434 if (adev->pm.dpm.backbias_response_time == 0) 7435 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 7436 7437 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 7438 0, false, ÷rs); 7439 if (ret) 7440 pi->ref_div = dividers.ref_div + 1; 7441 else 7442 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7443 7444 eg_pi->smu_uvd_hs = false; 7445 7446 pi->mclk_strobe_mode_threshold = 40000; 7447 if (si_is_special_1gb_platform(adev)) 7448 pi->mclk_stutter_mode_threshold = 0; 7449 else 7450 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7451 pi->mclk_edc_enable_threshold = 40000; 7452 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7453 7454 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7455 7456 pi->voltage_control = 7457 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7458 VOLTAGE_OBJ_GPIO_LUT); 7459 if (!pi->voltage_control) { 7460 si_pi->voltage_control_svi2 = 7461 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7462 VOLTAGE_OBJ_SVID2); 7463 if (si_pi->voltage_control_svi2) 7464 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7465 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7466 } 7467 7468 pi->mvdd_control = 7469 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7470 VOLTAGE_OBJ_GPIO_LUT); 7471 7472 eg_pi->vddci_control = 7473 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7474 VOLTAGE_OBJ_GPIO_LUT); 7475 if (!eg_pi->vddci_control) 7476 si_pi->vddci_control_svi2 = 7477 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7478 VOLTAGE_OBJ_SVID2); 7479 7480 si_pi->vddc_phase_shed_control = 7481 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7482 VOLTAGE_OBJ_PHASE_LUT); 7483 7484 rv770_get_engine_memory_ss(adev); 7485 7486 pi->asi = RV770_ASI_DFLT; 7487 pi->pasi = CYPRESS_HASI_DFLT; 7488 pi->vrc = SISLANDS_VRC_DFLT; 7489 7490 pi->gfx_clock_gating = true; 7491 7492 eg_pi->sclk_deep_sleep = true; 7493 si_pi->sclk_deep_sleep_above_low = false; 7494 7495 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7496 pi->thermal_protection = true; 7497 else 7498 pi->thermal_protection = false; 7499 7500 eg_pi->dynamic_ac_timing = true; 7501 7502 eg_pi->light_sleep = true; 7503 #if defined(CONFIG_ACPI) 7504 eg_pi->pcie_performance_request = 7505 amdgpu_acpi_is_pcie_performance_request_supported(adev); 7506 #else 7507 eg_pi->pcie_performance_request = false; 7508 #endif 7509 7510 si_pi->sram_end = SMC_RAM_END; 7511 7512 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7513 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7514 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7515 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7516 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7517 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7518 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7519 7520 si_initialize_powertune_defaults(adev); 7521 7522 /* make sure dc limits are valid */ 7523 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7524 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7525 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7526 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7527 7528 si_pi->fan_ctrl_is_in_default_mode = true; 7529 7530 return 0; 7531 } 7532 7533 static void si_dpm_fini(struct amdgpu_device *adev) 7534 { 7535 int i; 7536 7537 if (adev->pm.dpm.ps) 7538 for (i = 0; i < adev->pm.dpm.num_ps; i++) 7539 kfree(adev->pm.dpm.ps[i].ps_priv); 7540 kfree(adev->pm.dpm.ps); 7541 kfree(adev->pm.dpm.priv); 7542 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7543 amdgpu_free_extended_power_table(adev); 7544 } 7545 7546 static void si_dpm_debugfs_print_current_performance_level(void *handle, 7547 struct seq_file *m) 7548 { 7549 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7550 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7551 struct amdgpu_ps *rps = &eg_pi->current_rps; 7552 struct si_ps *ps = si_get_ps(rps); 7553 struct rv7xx_pl *pl; 7554 u32 current_index = 7555 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >> 7556 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT; 7557 7558 if (current_index >= ps->performance_level_count) { 7559 seq_printf(m, "invalid dpm profile %d\n", current_index); 7560 } else { 7561 pl = &ps->performance_levels[current_index]; 7562 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7563 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7564 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7565 } 7566 } 7567 7568 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev, 7569 struct amdgpu_irq_src *source, 7570 unsigned type, 7571 enum amdgpu_interrupt_state state) 7572 { 7573 u32 cg_thermal_int; 7574 7575 switch (type) { 7576 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: 7577 switch (state) { 7578 case AMDGPU_IRQ_STATE_DISABLE: 7579 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7580 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK; 7581 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int); 7582 break; 7583 case AMDGPU_IRQ_STATE_ENABLE: 7584 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7585 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK; 7586 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int); 7587 break; 7588 default: 7589 break; 7590 } 7591 break; 7592 7593 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: 7594 switch (state) { 7595 case AMDGPU_IRQ_STATE_DISABLE: 7596 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7597 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 7598 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int); 7599 break; 7600 case AMDGPU_IRQ_STATE_ENABLE: 7601 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7602 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 7603 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int); 7604 break; 7605 default: 7606 break; 7607 } 7608 break; 7609 7610 default: 7611 break; 7612 } 7613 return 0; 7614 } 7615 7616 static int si_dpm_process_interrupt(struct amdgpu_device *adev, 7617 struct amdgpu_irq_src *source, 7618 struct amdgpu_iv_entry *entry) 7619 { 7620 bool queue_thermal = false; 7621 7622 if (entry == NULL) 7623 return -EINVAL; 7624 7625 switch (entry->src_id) { 7626 case 230: /* thermal low to high */ 7627 DRM_DEBUG("IH: thermal low to high\n"); 7628 adev->pm.dpm.thermal.high_to_low = false; 7629 queue_thermal = true; 7630 break; 7631 case 231: /* thermal high to low */ 7632 DRM_DEBUG("IH: thermal high to low\n"); 7633 adev->pm.dpm.thermal.high_to_low = true; 7634 queue_thermal = true; 7635 break; 7636 default: 7637 break; 7638 } 7639 7640 if (queue_thermal) 7641 schedule_work(&adev->pm.dpm.thermal.work); 7642 7643 return 0; 7644 } 7645 7646 static int si_dpm_late_init(struct amdgpu_ip_block *ip_block) 7647 { 7648 int ret; 7649 struct amdgpu_device *adev = ip_block->adev; 7650 7651 if (!adev->pm.dpm_enabled) 7652 return 0; 7653 7654 ret = si_set_temperature_range(adev); 7655 if (ret) 7656 return ret; 7657 #if 0 //TODO ? 7658 si_dpm_powergate_uvd(adev, true); 7659 #endif 7660 return 0; 7661 } 7662 7663 /** 7664 * si_dpm_init_microcode - load ucode images from disk 7665 * 7666 * @adev: amdgpu_device pointer 7667 * 7668 * Use the firmware interface to load the ucode images into 7669 * the driver (not loaded into hw). 7670 * Returns 0 on success, error on failure. 7671 */ 7672 static int si_dpm_init_microcode(struct amdgpu_device *adev) 7673 { 7674 const char *chip_name; 7675 int err; 7676 7677 DRM_DEBUG("\n"); 7678 switch (adev->asic_type) { 7679 case CHIP_TAHITI: 7680 chip_name = "tahiti"; 7681 break; 7682 case CHIP_PITCAIRN: 7683 if ((adev->pdev->revision == 0x81) && 7684 ((adev->pdev->device == 0x6810) || 7685 (adev->pdev->device == 0x6811))) 7686 chip_name = "pitcairn_k"; 7687 else 7688 chip_name = "pitcairn"; 7689 break; 7690 case CHIP_VERDE: 7691 if (((adev->pdev->device == 0x6820) && 7692 ((adev->pdev->revision == 0x81) || 7693 (adev->pdev->revision == 0x83))) || 7694 ((adev->pdev->device == 0x6821) && 7695 ((adev->pdev->revision == 0x83) || 7696 (adev->pdev->revision == 0x87))) || 7697 ((adev->pdev->revision == 0x87) && 7698 ((adev->pdev->device == 0x6823) || 7699 (adev->pdev->device == 0x682b)))) 7700 chip_name = "verde_k"; 7701 else 7702 chip_name = "verde"; 7703 break; 7704 case CHIP_OLAND: 7705 if (((adev->pdev->revision == 0x81) && 7706 ((adev->pdev->device == 0x6600) || 7707 (adev->pdev->device == 0x6604) || 7708 (adev->pdev->device == 0x6605) || 7709 (adev->pdev->device == 0x6610))) || 7710 ((adev->pdev->revision == 0x83) && 7711 (adev->pdev->device == 0x6610))) 7712 chip_name = "oland_k"; 7713 else 7714 chip_name = "oland"; 7715 break; 7716 case CHIP_HAINAN: 7717 if (((adev->pdev->revision == 0x81) && 7718 (adev->pdev->device == 0x6660)) || 7719 ((adev->pdev->revision == 0x83) && 7720 ((adev->pdev->device == 0x6660) || 7721 (adev->pdev->device == 0x6663) || 7722 (adev->pdev->device == 0x6665) || 7723 (adev->pdev->device == 0x6667)))) 7724 chip_name = "hainan_k"; 7725 else if ((adev->pdev->revision == 0xc3) && 7726 (adev->pdev->device == 0x6665)) 7727 chip_name = "banks_k_2"; 7728 else 7729 chip_name = "hainan"; 7730 break; 7731 default: BUG(); 7732 } 7733 7734 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 7735 "amdgpu/%s_smc.bin", chip_name); 7736 if (err) { 7737 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n", 7738 err, chip_name); 7739 amdgpu_ucode_release(&adev->pm.fw); 7740 } 7741 return err; 7742 } 7743 7744 static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block) 7745 { 7746 int ret; 7747 struct amdgpu_device *adev = ip_block->adev; 7748 7749 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); 7750 if (ret) 7751 return ret; 7752 7753 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); 7754 if (ret) 7755 return ret; 7756 7757 /* default to balanced state */ 7758 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 7759 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 7760 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; 7761 adev->pm.default_sclk = adev->clock.default_sclk; 7762 adev->pm.default_mclk = adev->clock.default_mclk; 7763 adev->pm.current_sclk = adev->clock.default_sclk; 7764 adev->pm.current_mclk = adev->clock.default_mclk; 7765 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 7766 7767 if (amdgpu_dpm == 0) 7768 return 0; 7769 7770 ret = si_dpm_init_microcode(adev); 7771 if (ret) 7772 return ret; 7773 7774 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 7775 ret = si_dpm_init(adev); 7776 if (ret) 7777 goto dpm_failed; 7778 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7779 if (amdgpu_dpm == 1) 7780 amdgpu_pm_print_power_states(adev); 7781 DRM_INFO("amdgpu: dpm initialized\n"); 7782 7783 return 0; 7784 7785 dpm_failed: 7786 si_dpm_fini(adev); 7787 DRM_ERROR("amdgpu: dpm initialization failed\n"); 7788 return ret; 7789 } 7790 7791 static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block) 7792 { 7793 struct amdgpu_device *adev = ip_block->adev; 7794 7795 flush_work(&adev->pm.dpm.thermal.work); 7796 7797 si_dpm_fini(adev); 7798 7799 return 0; 7800 } 7801 7802 static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block) 7803 { 7804 int ret; 7805 7806 struct amdgpu_device *adev = ip_block->adev; 7807 7808 if (!amdgpu_dpm) 7809 return 0; 7810 7811 mutex_lock(&adev->pm.mutex); 7812 si_dpm_setup_asic(adev); 7813 ret = si_dpm_enable(adev); 7814 if (ret) 7815 adev->pm.dpm_enabled = false; 7816 else 7817 adev->pm.dpm_enabled = true; 7818 amdgpu_legacy_dpm_compute_clocks(adev); 7819 mutex_unlock(&adev->pm.mutex); 7820 return ret; 7821 } 7822 7823 static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block) 7824 { 7825 struct amdgpu_device *adev = ip_block->adev; 7826 7827 if (adev->pm.dpm_enabled) 7828 si_dpm_disable(adev); 7829 7830 return 0; 7831 } 7832 7833 static int si_dpm_suspend(struct amdgpu_ip_block *ip_block) 7834 { 7835 struct amdgpu_device *adev = ip_block->adev; 7836 7837 cancel_work_sync(&adev->pm.dpm.thermal.work); 7838 7839 if (adev->pm.dpm_enabled) { 7840 mutex_lock(&adev->pm.mutex); 7841 adev->pm.dpm_enabled = false; 7842 /* disable dpm */ 7843 si_dpm_disable(adev); 7844 /* reset the power state */ 7845 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7846 mutex_unlock(&adev->pm.mutex); 7847 } 7848 7849 return 0; 7850 } 7851 7852 static int si_dpm_resume(struct amdgpu_ip_block *ip_block) 7853 { 7854 int ret = 0; 7855 struct amdgpu_device *adev = ip_block->adev; 7856 7857 if (!amdgpu_dpm) 7858 return 0; 7859 7860 if (!adev->pm.dpm_enabled) { 7861 /* asic init will reset to the boot state */ 7862 mutex_lock(&adev->pm.mutex); 7863 si_dpm_setup_asic(adev); 7864 ret = si_dpm_enable(adev); 7865 if (ret) { 7866 adev->pm.dpm_enabled = false; 7867 } else { 7868 adev->pm.dpm_enabled = true; 7869 amdgpu_legacy_dpm_compute_clocks(adev); 7870 } 7871 mutex_unlock(&adev->pm.mutex); 7872 } 7873 7874 return ret; 7875 } 7876 7877 static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block) 7878 { 7879 /* XXX */ 7880 return true; 7881 } 7882 7883 static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) 7884 { 7885 /* XXX */ 7886 return 0; 7887 } 7888 7889 static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 7890 enum amd_clockgating_state state) 7891 { 7892 return 0; 7893 } 7894 7895 static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block, 7896 enum amd_powergating_state state) 7897 { 7898 return 0; 7899 } 7900 7901 /* get temperature in millidegrees */ 7902 static int si_dpm_get_temp(void *handle) 7903 { 7904 u32 temp; 7905 int actual_temp = 0; 7906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7907 7908 temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 7909 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; 7910 7911 if (temp & 0x200) 7912 actual_temp = 255; 7913 else 7914 actual_temp = temp & 0x1ff; 7915 7916 actual_temp = (actual_temp * 1000); 7917 7918 return actual_temp; 7919 } 7920 7921 static u32 si_dpm_get_sclk(void *handle, bool low) 7922 { 7923 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7924 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7925 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7926 7927 if (low) 7928 return requested_state->performance_levels[0].sclk; 7929 else 7930 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 7931 } 7932 7933 static u32 si_dpm_get_mclk(void *handle, bool low) 7934 { 7935 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7936 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7937 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7938 7939 if (low) 7940 return requested_state->performance_levels[0].mclk; 7941 else 7942 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 7943 } 7944 7945 static void si_dpm_print_power_state(void *handle, 7946 void *current_ps) 7947 { 7948 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7949 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; 7950 struct si_ps *ps = si_get_ps(rps); 7951 struct rv7xx_pl *pl; 7952 int i; 7953 7954 amdgpu_dpm_print_class_info(rps->class, rps->class2); 7955 amdgpu_dpm_print_cap_info(rps->caps); 7956 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7957 for (i = 0; i < ps->performance_level_count; i++) { 7958 pl = &ps->performance_levels[i]; 7959 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7960 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7961 } 7962 amdgpu_dpm_print_ps_status(adev, rps); 7963 } 7964 7965 static int si_dpm_early_init(struct amdgpu_ip_block *ip_block) 7966 { 7967 7968 struct amdgpu_device *adev = ip_block->adev; 7969 7970 adev->powerplay.pp_funcs = &si_dpm_funcs; 7971 adev->powerplay.pp_handle = adev; 7972 si_dpm_set_irq_funcs(adev); 7973 return 0; 7974 } 7975 7976 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, 7977 const struct rv7xx_pl *si_cpl2) 7978 { 7979 return ((si_cpl1->mclk == si_cpl2->mclk) && 7980 (si_cpl1->sclk == si_cpl2->sclk) && 7981 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && 7982 (si_cpl1->vddc == si_cpl2->vddc) && 7983 (si_cpl1->vddci == si_cpl2->vddci)); 7984 } 7985 7986 static int si_check_state_equal(void *handle, 7987 void *current_ps, 7988 void *request_ps, 7989 bool *equal) 7990 { 7991 struct si_ps *si_cps; 7992 struct si_ps *si_rps; 7993 int i; 7994 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 7995 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 7996 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7997 7998 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 7999 return -EINVAL; 8000 8001 si_cps = si_get_ps((struct amdgpu_ps *)cps); 8002 si_rps = si_get_ps((struct amdgpu_ps *)rps); 8003 8004 if (si_cps == NULL) { 8005 printk("si_cps is NULL\n"); 8006 *equal = false; 8007 return 0; 8008 } 8009 8010 if (si_cps->performance_level_count != si_rps->performance_level_count) { 8011 *equal = false; 8012 return 0; 8013 } 8014 8015 for (i = 0; i < si_cps->performance_level_count; i++) { 8016 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), 8017 &(si_rps->performance_levels[i]))) { 8018 *equal = false; 8019 return 0; 8020 } 8021 } 8022 8023 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 8024 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); 8025 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); 8026 8027 return 0; 8028 } 8029 8030 static int si_dpm_read_sensor(void *handle, int idx, 8031 void *value, int *size) 8032 { 8033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8034 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 8035 struct amdgpu_ps *rps = &eg_pi->current_rps; 8036 struct si_ps *ps = si_get_ps(rps); 8037 uint32_t sclk, mclk; 8038 u32 pl_index = 8039 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >> 8040 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT; 8041 8042 /* size must be at least 4 bytes for all sensors */ 8043 if (*size < 4) 8044 return -EINVAL; 8045 8046 switch (idx) { 8047 case AMDGPU_PP_SENSOR_GFX_SCLK: 8048 if (pl_index < ps->performance_level_count) { 8049 sclk = ps->performance_levels[pl_index].sclk; 8050 *((uint32_t *)value) = sclk; 8051 *size = 4; 8052 return 0; 8053 } 8054 return -EINVAL; 8055 case AMDGPU_PP_SENSOR_GFX_MCLK: 8056 if (pl_index < ps->performance_level_count) { 8057 mclk = ps->performance_levels[pl_index].mclk; 8058 *((uint32_t *)value) = mclk; 8059 *size = 4; 8060 return 0; 8061 } 8062 return -EINVAL; 8063 case AMDGPU_PP_SENSOR_GPU_TEMP: 8064 *((uint32_t *)value) = si_dpm_get_temp(adev); 8065 *size = 4; 8066 return 0; 8067 default: 8068 return -EOPNOTSUPP; 8069 } 8070 } 8071 8072 static const struct amd_ip_funcs si_dpm_ip_funcs = { 8073 .name = "si_dpm", 8074 .early_init = si_dpm_early_init, 8075 .late_init = si_dpm_late_init, 8076 .sw_init = si_dpm_sw_init, 8077 .sw_fini = si_dpm_sw_fini, 8078 .hw_init = si_dpm_hw_init, 8079 .hw_fini = si_dpm_hw_fini, 8080 .suspend = si_dpm_suspend, 8081 .resume = si_dpm_resume, 8082 .is_idle = si_dpm_is_idle, 8083 .wait_for_idle = si_dpm_wait_for_idle, 8084 .set_clockgating_state = si_dpm_set_clockgating_state, 8085 .set_powergating_state = si_dpm_set_powergating_state, 8086 }; 8087 8088 const struct amdgpu_ip_block_version si_smu_ip_block = 8089 { 8090 .type = AMD_IP_BLOCK_TYPE_SMC, 8091 .major = 6, 8092 .minor = 0, 8093 .rev = 0, 8094 .funcs = &si_dpm_ip_funcs, 8095 }; 8096 8097 static const struct amd_pm_funcs si_dpm_funcs = { 8098 .pre_set_power_state = &si_dpm_pre_set_power_state, 8099 .set_power_state = &si_dpm_set_power_state, 8100 .post_set_power_state = &si_dpm_post_set_power_state, 8101 .display_configuration_changed = &si_dpm_display_configuration_changed, 8102 .get_sclk = &si_dpm_get_sclk, 8103 .get_mclk = &si_dpm_get_mclk, 8104 .print_power_state = &si_dpm_print_power_state, 8105 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 8106 .force_performance_level = &si_dpm_force_performance_level, 8107 .vblank_too_short = &si_dpm_vblank_too_short, 8108 .set_fan_control_mode = &si_dpm_set_fan_control_mode, 8109 .get_fan_control_mode = &si_dpm_get_fan_control_mode, 8110 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm, 8111 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm, 8112 .check_state_equal = &si_check_state_equal, 8113 .get_vce_clock_state = amdgpu_get_vce_clock_state, 8114 .read_sensor = &si_dpm_read_sensor, 8115 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks, 8116 }; 8117 8118 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = { 8119 .set = si_dpm_set_interrupt_state, 8120 .process = si_dpm_process_interrupt, 8121 }; 8122 8123 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) 8124 { 8125 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 8126 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; 8127 } 8128 8129