1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "amdgpu_atombios.h" 31 #include "amdgpu_dpm_internal.h" 32 #include "amd_pcie.h" 33 #include "atom.h" 34 #include "gfx_v6_0.h" 35 #include "r600_dpm.h" 36 #include "sid.h" 37 #include "si_dpm.h" 38 #include "../include/pptable.h" 39 #include <linux/math64.h> 40 #include <linux/seq_file.h> 41 #include <linux/firmware.h> 42 #include <legacy_dpm.h> 43 44 #include "bif/bif_3_0_d.h" 45 #include "bif/bif_3_0_sh_mask.h" 46 47 #include "dce/dce_6_0_d.h" 48 #include "dce/dce_6_0_sh_mask.h" 49 50 #include "gca/gfx_6_0_d.h" 51 #include "gca/gfx_6_0_sh_mask.h" 52 53 #include"gmc/gmc_6_0_d.h" 54 #include"gmc/gmc_6_0_sh_mask.h" 55 56 #include "smu/smu_6_0_d.h" 57 #include "smu/smu_6_0_sh_mask.h" 58 59 #define MC_CG_ARB_FREQ_F0 0x0a 60 #define MC_CG_ARB_FREQ_F1 0x0b 61 #define MC_CG_ARB_FREQ_F2 0x0c 62 #define MC_CG_ARB_FREQ_F3 0x0d 63 64 #define SMC_RAM_END 0x20000 65 66 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 67 68 69 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ 70 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 71 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 72 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 73 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 74 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 75 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 76 77 #define BIOS_SCRATCH_4 0x5cd 78 79 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin"); 80 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin"); 81 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin"); 82 MODULE_FIRMWARE("amdgpu/verde_smc.bin"); 83 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin"); 84 MODULE_FIRMWARE("amdgpu/oland_smc.bin"); 85 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin"); 86 MODULE_FIRMWARE("amdgpu/hainan_smc.bin"); 87 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin"); 88 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin"); 89 90 static const struct amd_pm_funcs si_dpm_funcs; 91 92 union power_info { 93 struct _ATOM_POWERPLAY_INFO info; 94 struct _ATOM_POWERPLAY_INFO_V2 info_2; 95 struct _ATOM_POWERPLAY_INFO_V3 info_3; 96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; 100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; 101 }; 102 103 union fan_info { 104 struct _ATOM_PPLIB_FANTABLE fan; 105 struct _ATOM_PPLIB_FANTABLE2 fan2; 106 struct _ATOM_PPLIB_FANTABLE3 fan3; 107 }; 108 109 union pplib_clock_info { 110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 114 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 115 }; 116 117 enum si_dpm_auto_throttle_src { 118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL, 119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL 120 }; 121 122 enum si_dpm_event_src { 123 SI_DPM_EVENT_SRC_ANALOG = 0, 124 SI_DPM_EVENT_SRC_EXTERNAL = 1, 125 SI_DPM_EVENT_SRC_DIGITAL = 2, 126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 128 }; 129 130 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] = 131 { 132 R600_UTC_DFLT_00, 133 R600_UTC_DFLT_01, 134 R600_UTC_DFLT_02, 135 R600_UTC_DFLT_03, 136 R600_UTC_DFLT_04, 137 R600_UTC_DFLT_05, 138 R600_UTC_DFLT_06, 139 R600_UTC_DFLT_07, 140 R600_UTC_DFLT_08, 141 R600_UTC_DFLT_09, 142 R600_UTC_DFLT_10, 143 R600_UTC_DFLT_11, 144 R600_UTC_DFLT_12, 145 R600_UTC_DFLT_13, 146 R600_UTC_DFLT_14, 147 }; 148 149 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = 150 { 151 R600_DTC_DFLT_00, 152 R600_DTC_DFLT_01, 153 R600_DTC_DFLT_02, 154 R600_DTC_DFLT_03, 155 R600_DTC_DFLT_04, 156 R600_DTC_DFLT_05, 157 R600_DTC_DFLT_06, 158 R600_DTC_DFLT_07, 159 R600_DTC_DFLT_08, 160 R600_DTC_DFLT_09, 161 R600_DTC_DFLT_10, 162 R600_DTC_DFLT_11, 163 R600_DTC_DFLT_12, 164 R600_DTC_DFLT_13, 165 R600_DTC_DFLT_14, 166 }; 167 168 static const struct si_cac_config_reg cac_weights_tahiti[] = 169 { 170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 230 { 0xFFFFFFFF } 231 }; 232 233 static const struct si_cac_config_reg lcac_tahiti[] = 234 { 235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 321 { 0xFFFFFFFF } 322 323 }; 324 325 static const struct si_cac_config_reg cac_override_tahiti[] = 326 { 327 { 0xFFFFFFFF } 328 }; 329 330 static const struct si_powertune_data powertune_data_tahiti = 331 { 332 ((1 << 16) | 27027), 333 6, 334 0, 335 4, 336 95, 337 { 338 0UL, 339 0UL, 340 4521550UL, 341 309631529UL, 342 -1270850L, 343 4513710L, 344 40 345 }, 346 595000000UL, 347 12, 348 { 349 0, 350 0, 351 0, 352 0, 353 0, 354 0, 355 0, 356 0 357 }, 358 true 359 }; 360 361 static const struct si_dte_data dte_data_tahiti = 362 { 363 { 1159409, 0, 0, 0, 0 }, 364 { 777, 0, 0, 0, 0 }, 365 2, 366 54000, 367 127000, 368 25, 369 2, 370 10, 371 13, 372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 375 85, 376 false 377 }; 378 379 static const struct si_dte_data dte_data_tahiti_pro = 380 { 381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 382 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 383 5, 384 45000, 385 100, 386 0xA, 387 1, 388 0, 389 0x10, 390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 393 90, 394 true 395 }; 396 397 static const struct si_dte_data dte_data_new_zealand = 398 { 399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 401 0x5, 402 0xAFC8, 403 0x69, 404 0x32, 405 1, 406 0, 407 0x10, 408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 411 85, 412 true 413 }; 414 415 static const struct si_dte_data dte_data_aruba_pro = 416 { 417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 418 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 419 5, 420 45000, 421 100, 422 0xA, 423 1, 424 0, 425 0x10, 426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 429 90, 430 true 431 }; 432 433 static const struct si_dte_data dte_data_malta = 434 { 435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 436 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 437 5, 438 45000, 439 100, 440 0xA, 441 1, 442 0, 443 0x10, 444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 447 90, 448 true 449 }; 450 451 static const struct si_cac_config_reg cac_weights_pitcairn[] = 452 { 453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 513 { 0xFFFFFFFF } 514 }; 515 516 static const struct si_cac_config_reg lcac_pitcairn[] = 517 { 518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 604 { 0xFFFFFFFF } 605 }; 606 607 static const struct si_cac_config_reg cac_override_pitcairn[] = 608 { 609 { 0xFFFFFFFF } 610 }; 611 612 static const struct si_powertune_data powertune_data_pitcairn = 613 { 614 ((1 << 16) | 27027), 615 5, 616 0, 617 6, 618 100, 619 { 620 51600000UL, 621 1800000UL, 622 7194395UL, 623 309631529UL, 624 -1270850L, 625 4513710L, 626 100 627 }, 628 117830498UL, 629 12, 630 { 631 0, 632 0, 633 0, 634 0, 635 0, 636 0, 637 0, 638 0 639 }, 640 true 641 }; 642 643 static const struct si_dte_data dte_data_pitcairn = 644 { 645 { 0, 0, 0, 0, 0 }, 646 { 0, 0, 0, 0, 0 }, 647 0, 648 0, 649 0, 650 0, 651 0, 652 0, 653 0, 654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 657 0, 658 false 659 }; 660 661 static const struct si_dte_data dte_data_curacao_xt = 662 { 663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 664 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 665 5, 666 45000, 667 100, 668 0xA, 669 1, 670 0, 671 0x10, 672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 675 90, 676 true 677 }; 678 679 static const struct si_dte_data dte_data_curacao_pro = 680 { 681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 682 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 683 5, 684 45000, 685 100, 686 0xA, 687 1, 688 0, 689 0x10, 690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 693 90, 694 true 695 }; 696 697 static const struct si_dte_data dte_data_neptune_xt = 698 { 699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 700 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 701 5, 702 45000, 703 100, 704 0xA, 705 1, 706 0, 707 0x10, 708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 711 90, 712 true 713 }; 714 715 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 716 { 717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 777 { 0xFFFFFFFF } 778 }; 779 780 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 781 { 782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 842 { 0xFFFFFFFF } 843 }; 844 845 static const struct si_cac_config_reg cac_weights_heathrow[] = 846 { 847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 907 { 0xFFFFFFFF } 908 }; 909 910 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 911 { 912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 972 { 0xFFFFFFFF } 973 }; 974 975 static const struct si_cac_config_reg cac_weights_cape_verde[] = 976 { 977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1037 { 0xFFFFFFFF } 1038 }; 1039 1040 static const struct si_cac_config_reg lcac_cape_verde[] = 1041 { 1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1096 { 0xFFFFFFFF } 1097 }; 1098 1099 static const struct si_cac_config_reg cac_override_cape_verde[] = 1100 { 1101 { 0xFFFFFFFF } 1102 }; 1103 1104 static const struct si_powertune_data powertune_data_cape_verde = 1105 { 1106 ((1 << 16) | 0x6993), 1107 5, 1108 0, 1109 7, 1110 105, 1111 { 1112 0UL, 1113 0UL, 1114 7194395UL, 1115 309631529UL, 1116 -1270850L, 1117 4513710L, 1118 100 1119 }, 1120 117830498UL, 1121 12, 1122 { 1123 0, 1124 0, 1125 0, 1126 0, 1127 0, 1128 0, 1129 0, 1130 0 1131 }, 1132 true 1133 }; 1134 1135 static const struct si_dte_data dte_data_cape_verde = 1136 { 1137 { 0, 0, 0, 0, 0 }, 1138 { 0, 0, 0, 0, 0 }, 1139 0, 1140 0, 1141 0, 1142 0, 1143 0, 1144 0, 1145 0, 1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1149 0, 1150 false 1151 }; 1152 1153 static const struct si_dte_data dte_data_venus_xtx = 1154 { 1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1157 5, 1158 55000, 1159 0x69, 1160 0xA, 1161 1, 1162 0, 1163 0x3, 1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1167 90, 1168 true 1169 }; 1170 1171 static const struct si_dte_data dte_data_venus_xt = 1172 { 1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1175 5, 1176 55000, 1177 0x69, 1178 0xA, 1179 1, 1180 0, 1181 0x3, 1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1185 90, 1186 true 1187 }; 1188 1189 static const struct si_dte_data dte_data_venus_pro = 1190 { 1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1193 5, 1194 55000, 1195 0x69, 1196 0xA, 1197 1, 1198 0, 1199 0x3, 1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1203 90, 1204 true 1205 }; 1206 1207 static const struct si_cac_config_reg cac_weights_oland[] = 1208 { 1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1269 { 0xFFFFFFFF } 1270 }; 1271 1272 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1273 { 1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1334 { 0xFFFFFFFF } 1335 }; 1336 1337 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1338 { 1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1399 { 0xFFFFFFFF } 1400 }; 1401 1402 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1403 { 1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1464 { 0xFFFFFFFF } 1465 }; 1466 1467 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1468 { 1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1529 { 0xFFFFFFFF } 1530 }; 1531 1532 static const struct si_cac_config_reg lcac_oland[] = 1533 { 1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1576 { 0xFFFFFFFF } 1577 }; 1578 1579 static const struct si_cac_config_reg lcac_mars_pro[] = 1580 { 1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1623 { 0xFFFFFFFF } 1624 }; 1625 1626 static const struct si_cac_config_reg cac_override_oland[] = 1627 { 1628 { 0xFFFFFFFF } 1629 }; 1630 1631 static const struct si_powertune_data powertune_data_oland = 1632 { 1633 ((1 << 16) | 0x6993), 1634 5, 1635 0, 1636 7, 1637 105, 1638 { 1639 0UL, 1640 0UL, 1641 7194395UL, 1642 309631529UL, 1643 -1270850L, 1644 4513710L, 1645 100 1646 }, 1647 117830498UL, 1648 12, 1649 { 1650 0, 1651 0, 1652 0, 1653 0, 1654 0, 1655 0, 1656 0, 1657 0 1658 }, 1659 true 1660 }; 1661 1662 static const struct si_powertune_data powertune_data_mars_pro = 1663 { 1664 ((1 << 16) | 0x6993), 1665 5, 1666 0, 1667 7, 1668 105, 1669 { 1670 0UL, 1671 0UL, 1672 7194395UL, 1673 309631529UL, 1674 -1270850L, 1675 4513710L, 1676 100 1677 }, 1678 117830498UL, 1679 12, 1680 { 1681 0, 1682 0, 1683 0, 1684 0, 1685 0, 1686 0, 1687 0, 1688 0 1689 }, 1690 true 1691 }; 1692 1693 static const struct si_dte_data dte_data_oland = 1694 { 1695 { 0, 0, 0, 0, 0 }, 1696 { 0, 0, 0, 0, 0 }, 1697 0, 1698 0, 1699 0, 1700 0, 1701 0, 1702 0, 1703 0, 1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1707 0, 1708 false 1709 }; 1710 1711 static const struct si_dte_data dte_data_mars_pro = 1712 { 1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1714 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1715 5, 1716 55000, 1717 105, 1718 0xA, 1719 1, 1720 0, 1721 0x10, 1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1725 90, 1726 true 1727 }; 1728 1729 static const struct si_dte_data dte_data_sun_xt = 1730 { 1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1732 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1733 5, 1734 55000, 1735 105, 1736 0xA, 1737 1, 1738 0, 1739 0x10, 1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1743 90, 1744 true 1745 }; 1746 1747 1748 static const struct si_cac_config_reg cac_weights_hainan[] = 1749 { 1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1810 { 0xFFFFFFFF } 1811 }; 1812 1813 static const struct si_powertune_data powertune_data_hainan = 1814 { 1815 ((1 << 16) | 0x6993), 1816 5, 1817 0, 1818 9, 1819 105, 1820 { 1821 0UL, 1822 0UL, 1823 7194395UL, 1824 309631529UL, 1825 -1270850L, 1826 4513710L, 1827 100 1828 }, 1829 117830498UL, 1830 12, 1831 { 1832 0, 1833 0, 1834 0, 1835 0, 1836 0, 1837 0, 1838 0, 1839 0 1840 }, 1841 true 1842 }; 1843 1844 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev); 1845 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev); 1846 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev); 1847 static struct si_ps *si_get_ps(struct amdgpu_ps *rps); 1848 1849 static int si_populate_voltage_value(struct amdgpu_device *adev, 1850 const struct atom_voltage_table *table, 1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1852 static int si_get_std_voltage_value(struct amdgpu_device *adev, 1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1854 u16 *std_voltage); 1855 static int si_write_smc_soft_register(struct amdgpu_device *adev, 1856 u16 reg_offset, u32 value); 1857 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 1858 struct rv7xx_pl *pl, 1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1860 static int si_calculate_sclk_params(struct amdgpu_device *adev, 1861 u32 engine_clock, 1862 SISLANDS_SMC_SCLK_VALUE *sclk); 1863 1864 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); 1865 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); 1866 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); 1867 1868 static struct si_power_info *si_get_pi(struct amdgpu_device *adev) 1869 { 1870 struct si_power_info *pi = adev->pm.dpm.priv; 1871 return pi; 1872 } 1873 1874 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1875 u16 v, s32 t, u32 ileakage, u32 *leakage) 1876 { 1877 s64 kt, kv, leakage_w, i_leakage, vddc; 1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1879 s64 tmp; 1880 1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1882 vddc = div64_s64(drm_int2fixp(v), 1000); 1883 temperature = div64_s64(drm_int2fixp(t), 1000); 1884 1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1889 t_ref = drm_int2fixp(coeff->t_ref); 1890 1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1895 1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1897 1898 *leakage = drm_fixp2int(leakage_w * 1000); 1899 } 1900 1901 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, 1902 const struct ni_leakage_coeffients *coeff, 1903 u16 v, 1904 s32 t, 1905 u32 i_leakage, 1906 u32 *leakage) 1907 { 1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1909 } 1910 1911 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1912 const u32 fixed_kt, u16 v, 1913 u32 ileakage, u32 *leakage) 1914 { 1915 s64 kt, kv, leakage_w, i_leakage, vddc; 1916 1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1918 vddc = div64_s64(drm_int2fixp(v), 1000); 1919 1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1923 1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1925 1926 *leakage = drm_fixp2int(leakage_w * 1000); 1927 } 1928 1929 static void si_calculate_leakage_for_v(struct amdgpu_device *adev, 1930 const struct ni_leakage_coeffients *coeff, 1931 const u32 fixed_kt, 1932 u16 v, 1933 u32 i_leakage, 1934 u32 *leakage) 1935 { 1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1937 } 1938 1939 1940 static void si_update_dte_from_pl2(struct amdgpu_device *adev, 1941 struct si_dte_data *dte_data) 1942 { 1943 u32 p_limit1 = adev->pm.dpm.tdp_limit; 1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; 1945 u32 k = dte_data->k; 1946 u32 t_max = dte_data->max_t; 1947 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1948 u32 t_0 = dte_data->t0; 1949 u32 i; 1950 1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1952 dte_data->tdep_count = 3; 1953 1954 for (i = 0; i < k; i++) { 1955 dte_data->r[i] = 1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1957 (p_limit2 * (u32)100); 1958 } 1959 1960 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1961 1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1963 dte_data->tdep_r[i] = dte_data->r[4]; 1964 } 1965 } else { 1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1967 } 1968 } 1969 1970 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev) 1971 { 1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv; 1973 1974 return pi; 1975 } 1976 1977 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev) 1978 { 1979 struct ni_power_info *pi = adev->pm.dpm.priv; 1980 1981 return pi; 1982 } 1983 1984 static struct si_ps *si_get_ps(struct amdgpu_ps *aps) 1985 { 1986 struct si_ps *ps = aps->ps_priv; 1987 1988 return ps; 1989 } 1990 1991 static void si_initialize_powertune_defaults(struct amdgpu_device *adev) 1992 { 1993 struct ni_power_info *ni_pi = ni_get_pi(adev); 1994 struct si_power_info *si_pi = si_get_pi(adev); 1995 bool update_dte_from_pl2 = false; 1996 1997 if (adev->asic_type == CHIP_TAHITI) { 1998 si_pi->cac_weights = cac_weights_tahiti; 1999 si_pi->lcac_config = lcac_tahiti; 2000 si_pi->cac_override = cac_override_tahiti; 2001 si_pi->powertune_data = &powertune_data_tahiti; 2002 si_pi->dte_data = dte_data_tahiti; 2003 2004 switch (adev->pdev->device) { 2005 case 0x6798: 2006 si_pi->dte_data.enable_dte_by_default = true; 2007 break; 2008 case 0x6799: 2009 si_pi->dte_data = dte_data_new_zealand; 2010 break; 2011 case 0x6790: 2012 case 0x6791: 2013 case 0x6792: 2014 case 0x679E: 2015 si_pi->dte_data = dte_data_aruba_pro; 2016 update_dte_from_pl2 = true; 2017 break; 2018 case 0x679B: 2019 si_pi->dte_data = dte_data_malta; 2020 update_dte_from_pl2 = true; 2021 break; 2022 case 0x679A: 2023 si_pi->dte_data = dte_data_tahiti_pro; 2024 update_dte_from_pl2 = true; 2025 break; 2026 default: 2027 if (si_pi->dte_data.enable_dte_by_default == true) 2028 DRM_ERROR("DTE is not enabled!\n"); 2029 break; 2030 } 2031 } else if (adev->asic_type == CHIP_PITCAIRN) { 2032 si_pi->cac_weights = cac_weights_pitcairn; 2033 si_pi->lcac_config = lcac_pitcairn; 2034 si_pi->cac_override = cac_override_pitcairn; 2035 si_pi->powertune_data = &powertune_data_pitcairn; 2036 2037 switch (adev->pdev->device) { 2038 case 0x6810: 2039 case 0x6818: 2040 si_pi->dte_data = dte_data_curacao_xt; 2041 update_dte_from_pl2 = true; 2042 break; 2043 case 0x6819: 2044 case 0x6811: 2045 si_pi->dte_data = dte_data_curacao_pro; 2046 update_dte_from_pl2 = true; 2047 break; 2048 case 0x6800: 2049 case 0x6806: 2050 si_pi->dte_data = dte_data_neptune_xt; 2051 update_dte_from_pl2 = true; 2052 break; 2053 default: 2054 si_pi->dte_data = dte_data_pitcairn; 2055 break; 2056 } 2057 } else if (adev->asic_type == CHIP_VERDE) { 2058 si_pi->lcac_config = lcac_cape_verde; 2059 si_pi->cac_override = cac_override_cape_verde; 2060 si_pi->powertune_data = &powertune_data_cape_verde; 2061 2062 switch (adev->pdev->device) { 2063 case 0x683B: 2064 case 0x683F: 2065 case 0x6829: 2066 case 0x6835: 2067 si_pi->cac_weights = cac_weights_cape_verde_pro; 2068 si_pi->dte_data = dte_data_cape_verde; 2069 break; 2070 case 0x682C: 2071 si_pi->cac_weights = cac_weights_cape_verde_pro; 2072 si_pi->dte_data = dte_data_sun_xt; 2073 update_dte_from_pl2 = true; 2074 break; 2075 case 0x6825: 2076 case 0x6827: 2077 si_pi->cac_weights = cac_weights_heathrow; 2078 si_pi->dte_data = dte_data_cape_verde; 2079 break; 2080 case 0x6824: 2081 case 0x682D: 2082 si_pi->cac_weights = cac_weights_chelsea_xt; 2083 si_pi->dte_data = dte_data_cape_verde; 2084 break; 2085 case 0x682F: 2086 si_pi->cac_weights = cac_weights_chelsea_pro; 2087 si_pi->dte_data = dte_data_cape_verde; 2088 break; 2089 case 0x6820: 2090 si_pi->cac_weights = cac_weights_heathrow; 2091 si_pi->dte_data = dte_data_venus_xtx; 2092 break; 2093 case 0x6821: 2094 si_pi->cac_weights = cac_weights_heathrow; 2095 si_pi->dte_data = dte_data_venus_xt; 2096 break; 2097 case 0x6823: 2098 case 0x682B: 2099 case 0x6822: 2100 case 0x682A: 2101 si_pi->cac_weights = cac_weights_chelsea_pro; 2102 si_pi->dte_data = dte_data_venus_pro; 2103 break; 2104 default: 2105 si_pi->cac_weights = cac_weights_cape_verde; 2106 si_pi->dte_data = dte_data_cape_verde; 2107 break; 2108 } 2109 } else if (adev->asic_type == CHIP_OLAND) { 2110 si_pi->lcac_config = lcac_mars_pro; 2111 si_pi->cac_override = cac_override_oland; 2112 si_pi->powertune_data = &powertune_data_mars_pro; 2113 si_pi->dte_data = dte_data_mars_pro; 2114 2115 switch (adev->pdev->device) { 2116 case 0x6601: 2117 case 0x6621: 2118 case 0x6603: 2119 case 0x6605: 2120 si_pi->cac_weights = cac_weights_mars_pro; 2121 update_dte_from_pl2 = true; 2122 break; 2123 case 0x6600: 2124 case 0x6606: 2125 case 0x6620: 2126 case 0x6604: 2127 si_pi->cac_weights = cac_weights_mars_xt; 2128 update_dte_from_pl2 = true; 2129 break; 2130 case 0x6611: 2131 case 0x6613: 2132 case 0x6608: 2133 si_pi->cac_weights = cac_weights_oland_pro; 2134 update_dte_from_pl2 = true; 2135 break; 2136 case 0x6610: 2137 si_pi->cac_weights = cac_weights_oland_xt; 2138 update_dte_from_pl2 = true; 2139 break; 2140 default: 2141 si_pi->cac_weights = cac_weights_oland; 2142 si_pi->lcac_config = lcac_oland; 2143 si_pi->cac_override = cac_override_oland; 2144 si_pi->powertune_data = &powertune_data_oland; 2145 si_pi->dte_data = dte_data_oland; 2146 break; 2147 } 2148 } else if (adev->asic_type == CHIP_HAINAN) { 2149 si_pi->cac_weights = cac_weights_hainan; 2150 si_pi->lcac_config = lcac_oland; 2151 si_pi->cac_override = cac_override_oland; 2152 si_pi->powertune_data = &powertune_data_hainan; 2153 si_pi->dte_data = dte_data_sun_xt; 2154 update_dte_from_pl2 = true; 2155 } else { 2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2157 return; 2158 } 2159 2160 ni_pi->enable_power_containment = false; 2161 ni_pi->enable_cac = false; 2162 ni_pi->enable_sq_ramping = false; 2163 si_pi->enable_dte = false; 2164 2165 if (si_pi->powertune_data->enable_powertune_by_default) { 2166 ni_pi->enable_power_containment = true; 2167 ni_pi->enable_cac = true; 2168 if (si_pi->dte_data.enable_dte_by_default) { 2169 si_pi->enable_dte = true; 2170 if (update_dte_from_pl2) 2171 si_update_dte_from_pl2(adev, &si_pi->dte_data); 2172 2173 } 2174 ni_pi->enable_sq_ramping = true; 2175 } 2176 2177 ni_pi->driver_calculate_cac_leakage = true; 2178 ni_pi->cac_configuration_required = true; 2179 2180 if (ni_pi->cac_configuration_required) { 2181 ni_pi->support_cac_long_term_average = true; 2182 si_pi->dyn_powertune_data.l2_lta_window_size = 2183 si_pi->powertune_data->l2_lta_window_size_default; 2184 si_pi->dyn_powertune_data.lts_truncate = 2185 si_pi->powertune_data->lts_truncate_default; 2186 } else { 2187 ni_pi->support_cac_long_term_average = false; 2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2189 si_pi->dyn_powertune_data.lts_truncate = 0; 2190 } 2191 2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2193 } 2194 2195 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) 2196 { 2197 return 1; 2198 } 2199 2200 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev) 2201 { 2202 u32 xclk; 2203 u32 wintime; 2204 u32 cac_window; 2205 u32 cac_window_size; 2206 2207 xclk = amdgpu_asic_get_xclk(adev); 2208 2209 if (xclk == 0) 2210 return 0; 2211 2212 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2214 2215 wintime = (cac_window_size * 100) / xclk; 2216 2217 return wintime; 2218 } 2219 2220 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2221 { 2222 return power_in_watts; 2223 } 2224 2225 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, 2226 bool adjust_polarity, 2227 u32 tdp_adjustment, 2228 u32 *tdp_limit, 2229 u32 *near_tdp_limit) 2230 { 2231 u32 adjustment_delta, max_tdp_limit; 2232 2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) 2234 return -EINVAL; 2235 2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; 2237 2238 if (adjust_polarity) { 2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); 2241 } else { 2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; 2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) 2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2246 else 2247 *near_tdp_limit = 0; 2248 } 2249 2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2251 return -EINVAL; 2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2253 return -EINVAL; 2254 2255 return 0; 2256 } 2257 2258 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, 2259 struct amdgpu_ps *amdgpu_state) 2260 { 2261 struct ni_power_info *ni_pi = ni_get_pi(adev); 2262 struct si_power_info *si_pi = si_get_pi(adev); 2263 2264 if (ni_pi->enable_power_containment) { 2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2266 PP_SIslands_PAPMParameters *papm_parm; 2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; 2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2269 u32 tdp_limit; 2270 u32 near_tdp_limit; 2271 int ret; 2272 2273 if (scaling_factor == 0) 2274 return -EINVAL; 2275 2276 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2277 2278 ret = si_calculate_adjusted_tdp_limits(adev, 2279 false, /* ??? */ 2280 adev->pm.dpm.tdp_adjustment, 2281 &tdp_limit, 2282 &near_tdp_limit); 2283 if (ret) 2284 return ret; 2285 2286 smc_table->dpm2Params.TDPLimit = 2287 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2288 smc_table->dpm2Params.NearTDPLimit = 2289 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2290 smc_table->dpm2Params.SafePowerLimit = 2291 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2292 2293 ret = amdgpu_si_copy_bytes_to_smc(adev, 2294 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2295 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2296 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2297 sizeof(u32) * 3, 2298 si_pi->sram_end); 2299 if (ret) 2300 return ret; 2301 2302 if (si_pi->enable_ppm) { 2303 papm_parm = &si_pi->papm_parm; 2304 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2305 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2306 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2307 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2308 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2309 papm_parm->PlatformPowerLimit = 0xffffffff; 2310 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2311 2312 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2313 (u8 *)papm_parm, 2314 sizeof(PP_SIslands_PAPMParameters), 2315 si_pi->sram_end); 2316 if (ret) 2317 return ret; 2318 } 2319 } 2320 return 0; 2321 } 2322 2323 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, 2324 struct amdgpu_ps *amdgpu_state) 2325 { 2326 struct ni_power_info *ni_pi = ni_get_pi(adev); 2327 struct si_power_info *si_pi = si_get_pi(adev); 2328 2329 if (ni_pi->enable_power_containment) { 2330 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2331 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2332 int ret; 2333 2334 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2335 2336 smc_table->dpm2Params.NearTDPLimit = 2337 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2338 smc_table->dpm2Params.SafePowerLimit = 2339 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2340 2341 ret = amdgpu_si_copy_bytes_to_smc(adev, 2342 (si_pi->state_table_start + 2343 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2344 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2345 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2346 sizeof(u32) * 2, 2347 si_pi->sram_end); 2348 if (ret) 2349 return ret; 2350 } 2351 2352 return 0; 2353 } 2354 2355 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, 2356 const u16 prev_std_vddc, 2357 const u16 curr_std_vddc) 2358 { 2359 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2360 u64 prev_vddc = (u64)prev_std_vddc; 2361 u64 curr_vddc = (u64)curr_std_vddc; 2362 u64 pwr_efficiency_ratio, n, d; 2363 2364 if ((prev_vddc == 0) || (curr_vddc == 0)) 2365 return 0; 2366 2367 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2368 d = prev_vddc * prev_vddc; 2369 pwr_efficiency_ratio = div64_u64(n, d); 2370 2371 if (pwr_efficiency_ratio > (u64)0xFFFF) 2372 return 0; 2373 2374 return (u16)pwr_efficiency_ratio; 2375 } 2376 2377 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev, 2378 struct amdgpu_ps *amdgpu_state) 2379 { 2380 struct si_power_info *si_pi = si_get_pi(adev); 2381 2382 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2383 amdgpu_state->vclk && amdgpu_state->dclk) 2384 return true; 2385 2386 return false; 2387 } 2388 2389 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev) 2390 { 2391 struct evergreen_power_info *pi = adev->pm.dpm.priv; 2392 2393 return pi; 2394 } 2395 2396 static int si_populate_power_containment_values(struct amdgpu_device *adev, 2397 struct amdgpu_ps *amdgpu_state, 2398 SISLANDS_SMC_SWSTATE *smc_state) 2399 { 2400 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 2401 struct ni_power_info *ni_pi = ni_get_pi(adev); 2402 struct si_ps *state = si_get_ps(amdgpu_state); 2403 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2404 u32 prev_sclk; 2405 u32 max_sclk; 2406 u32 min_sclk; 2407 u16 prev_std_vddc; 2408 u16 curr_std_vddc; 2409 int i; 2410 u16 pwr_efficiency_ratio; 2411 u8 max_ps_percent; 2412 bool disable_uvd_power_tune; 2413 int ret; 2414 2415 if (ni_pi->enable_power_containment == false) 2416 return 0; 2417 2418 if (state->performance_level_count == 0) 2419 return -EINVAL; 2420 2421 if (smc_state->levelCount != state->performance_level_count) 2422 return -EINVAL; 2423 2424 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state); 2425 2426 smc_state->levels[0].dpm2.MaxPS = 0; 2427 smc_state->levels[0].dpm2.NearTDPDec = 0; 2428 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2429 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2430 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2431 2432 for (i = 1; i < state->performance_level_count; i++) { 2433 prev_sclk = state->performance_levels[i-1].sclk; 2434 max_sclk = state->performance_levels[i].sclk; 2435 if (i == 1) 2436 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2437 else 2438 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2439 2440 if (prev_sclk > max_sclk) 2441 return -EINVAL; 2442 2443 if ((max_ps_percent == 0) || 2444 (prev_sclk == max_sclk) || 2445 disable_uvd_power_tune) 2446 min_sclk = max_sclk; 2447 else if (i == 1) 2448 min_sclk = prev_sclk; 2449 else 2450 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2451 2452 if (min_sclk < state->performance_levels[0].sclk) 2453 min_sclk = state->performance_levels[0].sclk; 2454 2455 if (min_sclk == 0) 2456 return -EINVAL; 2457 2458 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2459 state->performance_levels[i-1].vddc, &vddc); 2460 if (ret) 2461 return ret; 2462 2463 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc); 2464 if (ret) 2465 return ret; 2466 2467 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2468 state->performance_levels[i].vddc, &vddc); 2469 if (ret) 2470 return ret; 2471 2472 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc); 2473 if (ret) 2474 return ret; 2475 2476 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev, 2477 prev_std_vddc, curr_std_vddc); 2478 2479 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2480 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2481 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2482 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2483 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2484 } 2485 2486 return 0; 2487 } 2488 2489 static int si_populate_sq_ramping_values(struct amdgpu_device *adev, 2490 struct amdgpu_ps *amdgpu_state, 2491 SISLANDS_SMC_SWSTATE *smc_state) 2492 { 2493 struct ni_power_info *ni_pi = ni_get_pi(adev); 2494 struct si_ps *state = si_get_ps(amdgpu_state); 2495 u32 sq_power_throttle, sq_power_throttle2; 2496 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2497 int i; 2498 2499 if (state->performance_level_count == 0) 2500 return -EINVAL; 2501 2502 if (smc_state->levelCount != state->performance_level_count) 2503 return -EINVAL; 2504 2505 if (adev->pm.dpm.sq_ramping_threshold == 0) 2506 return -EINVAL; 2507 2508 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2509 enable_sq_ramping = false; 2510 2511 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2512 enable_sq_ramping = false; 2513 2514 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2515 enable_sq_ramping = false; 2516 2517 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2518 enable_sq_ramping = false; 2519 2520 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2521 enable_sq_ramping = false; 2522 2523 for (i = 0; i < state->performance_level_count; i++) { 2524 sq_power_throttle = 0; 2525 sq_power_throttle2 = 0; 2526 2527 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && 2528 enable_sq_ramping) { 2529 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2530 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2531 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2532 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2533 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2534 } else { 2535 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2536 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2537 } 2538 2539 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2540 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2541 } 2542 2543 return 0; 2544 } 2545 2546 static int si_enable_power_containment(struct amdgpu_device *adev, 2547 struct amdgpu_ps *amdgpu_new_state, 2548 bool enable) 2549 { 2550 struct ni_power_info *ni_pi = ni_get_pi(adev); 2551 PPSMC_Result smc_result; 2552 int ret = 0; 2553 2554 if (ni_pi->enable_power_containment) { 2555 if (enable) { 2556 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2557 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2558 if (smc_result != PPSMC_Result_OK) { 2559 ret = -EINVAL; 2560 ni_pi->pc_enabled = false; 2561 } else { 2562 ni_pi->pc_enabled = true; 2563 } 2564 } 2565 } else { 2566 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2567 if (smc_result != PPSMC_Result_OK) 2568 ret = -EINVAL; 2569 ni_pi->pc_enabled = false; 2570 } 2571 } 2572 2573 return ret; 2574 } 2575 2576 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) 2577 { 2578 struct si_power_info *si_pi = si_get_pi(adev); 2579 int ret = 0; 2580 struct si_dte_data *dte_data = &si_pi->dte_data; 2581 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2582 u32 table_size; 2583 u8 tdep_count; 2584 u32 i; 2585 2586 if (dte_data == NULL) 2587 si_pi->enable_dte = false; 2588 2589 if (si_pi->enable_dte == false) 2590 return 0; 2591 2592 if (dte_data->k <= 0) 2593 return -EINVAL; 2594 2595 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2596 if (dte_tables == NULL) { 2597 si_pi->enable_dte = false; 2598 return -ENOMEM; 2599 } 2600 2601 table_size = dte_data->k; 2602 2603 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2604 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2605 2606 tdep_count = dte_data->tdep_count; 2607 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2608 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2609 2610 dte_tables->K = cpu_to_be32(table_size); 2611 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2612 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2613 dte_tables->WindowSize = dte_data->window_size; 2614 dte_tables->temp_select = dte_data->temp_select; 2615 dte_tables->DTE_mode = dte_data->dte_mode; 2616 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2617 2618 if (tdep_count > 0) 2619 table_size--; 2620 2621 for (i = 0; i < table_size; i++) { 2622 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2623 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2624 } 2625 2626 dte_tables->Tdep_count = tdep_count; 2627 2628 for (i = 0; i < (u32)tdep_count; i++) { 2629 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2630 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2631 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2632 } 2633 2634 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, 2635 (u8 *)dte_tables, 2636 sizeof(Smc_SIslands_DTE_Configuration), 2637 si_pi->sram_end); 2638 kfree(dte_tables); 2639 2640 return ret; 2641 } 2642 2643 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, 2644 u16 *max, u16 *min) 2645 { 2646 struct si_power_info *si_pi = si_get_pi(adev); 2647 struct amdgpu_cac_leakage_table *table = 2648 &adev->pm.dpm.dyn_state.cac_leakage_table; 2649 u32 i; 2650 u32 v0_loadline; 2651 2652 if (table == NULL) 2653 return -EINVAL; 2654 2655 *max = 0; 2656 *min = 0xFFFF; 2657 2658 for (i = 0; i < table->count; i++) { 2659 if (table->entries[i].vddc > *max) 2660 *max = table->entries[i].vddc; 2661 if (table->entries[i].vddc < *min) 2662 *min = table->entries[i].vddc; 2663 } 2664 2665 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2666 return -EINVAL; 2667 2668 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2669 2670 if (v0_loadline > 0xFFFFUL) 2671 return -EINVAL; 2672 2673 *min = (u16)v0_loadline; 2674 2675 if ((*min > *max) || (*max == 0) || (*min == 0)) 2676 return -EINVAL; 2677 2678 return 0; 2679 } 2680 2681 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2682 { 2683 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2684 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2685 } 2686 2687 static int si_init_dte_leakage_table(struct amdgpu_device *adev, 2688 PP_SIslands_CacConfig *cac_tables, 2689 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2690 u16 t0, u16 t_step) 2691 { 2692 struct si_power_info *si_pi = si_get_pi(adev); 2693 u32 leakage; 2694 unsigned int i, j; 2695 s32 t; 2696 u32 smc_leakage; 2697 u32 scaling_factor; 2698 u16 voltage; 2699 2700 scaling_factor = si_get_smc_power_scaling_factor(adev); 2701 2702 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2703 t = (1000 * (i * t_step + t0)); 2704 2705 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2706 voltage = vddc_max - (vddc_step * j); 2707 2708 si_calculate_leakage_for_v_and_t(adev, 2709 &si_pi->powertune_data->leakage_coefficients, 2710 voltage, 2711 t, 2712 si_pi->dyn_powertune_data.cac_leakage, 2713 &leakage); 2714 2715 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2716 2717 if (smc_leakage > 0xFFFF) 2718 smc_leakage = 0xFFFF; 2719 2720 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2721 cpu_to_be16((u16)smc_leakage); 2722 } 2723 } 2724 return 0; 2725 } 2726 2727 static int si_init_simplified_leakage_table(struct amdgpu_device *adev, 2728 PP_SIslands_CacConfig *cac_tables, 2729 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2730 { 2731 struct si_power_info *si_pi = si_get_pi(adev); 2732 u32 leakage; 2733 unsigned int i, j; 2734 u32 smc_leakage; 2735 u32 scaling_factor; 2736 u16 voltage; 2737 2738 scaling_factor = si_get_smc_power_scaling_factor(adev); 2739 2740 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2741 voltage = vddc_max - (vddc_step * j); 2742 2743 si_calculate_leakage_for_v(adev, 2744 &si_pi->powertune_data->leakage_coefficients, 2745 si_pi->powertune_data->fixed_kt, 2746 voltage, 2747 si_pi->dyn_powertune_data.cac_leakage, 2748 &leakage); 2749 2750 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2751 2752 if (smc_leakage > 0xFFFF) 2753 smc_leakage = 0xFFFF; 2754 2755 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2756 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2757 cpu_to_be16((u16)smc_leakage); 2758 } 2759 return 0; 2760 } 2761 2762 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) 2763 { 2764 struct ni_power_info *ni_pi = ni_get_pi(adev); 2765 struct si_power_info *si_pi = si_get_pi(adev); 2766 PP_SIslands_CacConfig *cac_tables = NULL; 2767 u16 vddc_max, vddc_min, vddc_step; 2768 u16 t0, t_step; 2769 u32 load_line_slope, reg; 2770 int ret = 0; 2771 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100; 2772 2773 if (ni_pi->enable_cac == false) 2774 return 0; 2775 2776 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2777 if (!cac_tables) 2778 return -ENOMEM; 2779 2780 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2781 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2782 WREG32(CG_CAC_CTRL, reg); 2783 2784 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; 2785 si_pi->dyn_powertune_data.dc_pwr_value = 2786 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2787 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); 2788 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2789 2790 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2791 2792 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min); 2793 if (ret) 2794 goto done_free; 2795 2796 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2797 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2798 t_step = 4; 2799 t0 = 60; 2800 2801 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2802 ret = si_init_dte_leakage_table(adev, cac_tables, 2803 vddc_max, vddc_min, vddc_step, 2804 t0, t_step); 2805 else 2806 ret = si_init_simplified_leakage_table(adev, cac_tables, 2807 vddc_max, vddc_min, vddc_step); 2808 if (ret) 2809 goto done_free; 2810 2811 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2812 2813 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2814 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2815 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2816 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2817 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2818 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2819 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2820 cac_tables->calculation_repeats = cpu_to_be32(2); 2821 cac_tables->dc_cac = cpu_to_be32(0); 2822 cac_tables->log2_PG_LKG_SCALE = 12; 2823 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2824 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2825 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2826 2827 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, 2828 (u8 *)cac_tables, 2829 sizeof(PP_SIslands_CacConfig), 2830 si_pi->sram_end); 2831 2832 if (ret) 2833 goto done_free; 2834 2835 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2836 2837 done_free: 2838 if (ret) { 2839 ni_pi->enable_cac = false; 2840 ni_pi->enable_power_containment = false; 2841 } 2842 2843 kfree(cac_tables); 2844 2845 return ret; 2846 } 2847 2848 static int si_program_cac_config_registers(struct amdgpu_device *adev, 2849 const struct si_cac_config_reg *cac_config_regs) 2850 { 2851 const struct si_cac_config_reg *config_regs = cac_config_regs; 2852 u32 data = 0, offset; 2853 2854 if (!config_regs) 2855 return -EINVAL; 2856 2857 while (config_regs->offset != 0xFFFFFFFF) { 2858 switch (config_regs->type) { 2859 case SISLANDS_CACCONFIG_CGIND: 2860 offset = SMC_CG_IND_START + config_regs->offset; 2861 if (offset < SMC_CG_IND_END) 2862 data = RREG32_SMC(offset); 2863 break; 2864 default: 2865 data = RREG32(config_regs->offset); 2866 break; 2867 } 2868 2869 data &= ~config_regs->mask; 2870 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2871 2872 switch (config_regs->type) { 2873 case SISLANDS_CACCONFIG_CGIND: 2874 offset = SMC_CG_IND_START + config_regs->offset; 2875 if (offset < SMC_CG_IND_END) 2876 WREG32_SMC(offset, data); 2877 break; 2878 default: 2879 WREG32(config_regs->offset, data); 2880 break; 2881 } 2882 config_regs++; 2883 } 2884 return 0; 2885 } 2886 2887 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev) 2888 { 2889 struct ni_power_info *ni_pi = ni_get_pi(adev); 2890 struct si_power_info *si_pi = si_get_pi(adev); 2891 int ret; 2892 2893 if ((ni_pi->enable_cac == false) || 2894 (ni_pi->cac_configuration_required == false)) 2895 return 0; 2896 2897 ret = si_program_cac_config_registers(adev, si_pi->lcac_config); 2898 if (ret) 2899 return ret; 2900 ret = si_program_cac_config_registers(adev, si_pi->cac_override); 2901 if (ret) 2902 return ret; 2903 ret = si_program_cac_config_registers(adev, si_pi->cac_weights); 2904 if (ret) 2905 return ret; 2906 2907 return 0; 2908 } 2909 2910 static int si_enable_smc_cac(struct amdgpu_device *adev, 2911 struct amdgpu_ps *amdgpu_new_state, 2912 bool enable) 2913 { 2914 struct ni_power_info *ni_pi = ni_get_pi(adev); 2915 struct si_power_info *si_pi = si_get_pi(adev); 2916 PPSMC_Result smc_result; 2917 int ret = 0; 2918 2919 if (ni_pi->enable_cac) { 2920 if (enable) { 2921 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2922 if (ni_pi->support_cac_long_term_average) { 2923 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2924 if (smc_result != PPSMC_Result_OK) 2925 ni_pi->support_cac_long_term_average = false; 2926 } 2927 2928 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2929 if (smc_result != PPSMC_Result_OK) { 2930 ret = -EINVAL; 2931 ni_pi->cac_enabled = false; 2932 } else { 2933 ni_pi->cac_enabled = true; 2934 } 2935 2936 if (si_pi->enable_dte) { 2937 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2938 if (smc_result != PPSMC_Result_OK) 2939 ret = -EINVAL; 2940 } 2941 } 2942 } else if (ni_pi->cac_enabled) { 2943 if (si_pi->enable_dte) 2944 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2945 2946 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2947 2948 ni_pi->cac_enabled = false; 2949 2950 if (ni_pi->support_cac_long_term_average) 2951 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2952 } 2953 } 2954 return ret; 2955 } 2956 2957 static int si_init_smc_spll_table(struct amdgpu_device *adev) 2958 { 2959 struct ni_power_info *ni_pi = ni_get_pi(adev); 2960 struct si_power_info *si_pi = si_get_pi(adev); 2961 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2962 SISLANDS_SMC_SCLK_VALUE sclk_params; 2963 u32 fb_div, p_div; 2964 u32 clk_s, clk_v; 2965 u32 sclk = 0; 2966 int ret = 0; 2967 u32 tmp; 2968 int i; 2969 2970 if (si_pi->spll_table_start == 0) 2971 return -EINVAL; 2972 2973 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2974 if (spll_table == NULL) 2975 return -ENOMEM; 2976 2977 for (i = 0; i < 256; i++) { 2978 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); 2979 if (ret) 2980 break; 2981 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2982 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2983 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2984 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2985 2986 fb_div &= ~0x00001FFF; 2987 fb_div >>= 1; 2988 clk_v >>= 6; 2989 2990 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2991 ret = -EINVAL; 2992 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2993 ret = -EINVAL; 2994 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2995 ret = -EINVAL; 2996 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2997 ret = -EINVAL; 2998 2999 if (ret) 3000 break; 3001 3002 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 3003 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 3004 spll_table->freq[i] = cpu_to_be32(tmp); 3005 3006 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 3007 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 3008 spll_table->ss[i] = cpu_to_be32(tmp); 3009 3010 sclk += 512; 3011 } 3012 3013 3014 if (!ret) 3015 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 3016 (u8 *)spll_table, 3017 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 3018 si_pi->sram_end); 3019 3020 if (ret) 3021 ni_pi->enable_power_containment = false; 3022 3023 kfree(spll_table); 3024 3025 return ret; 3026 } 3027 3028 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, 3029 u16 vce_voltage) 3030 { 3031 u16 highest_leakage = 0; 3032 struct si_power_info *si_pi = si_get_pi(adev); 3033 int i; 3034 3035 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 3036 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 3037 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 3038 } 3039 3040 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 3041 return highest_leakage; 3042 3043 return vce_voltage; 3044 } 3045 3046 static int si_get_vce_clock_voltage(struct amdgpu_device *adev, 3047 u32 evclk, u32 ecclk, u16 *voltage) 3048 { 3049 u32 i; 3050 int ret = -EINVAL; 3051 struct amdgpu_vce_clock_voltage_dependency_table *table = 3052 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3053 3054 if (((evclk == 0) && (ecclk == 0)) || 3055 (table && (table->count == 0))) { 3056 *voltage = 0; 3057 return 0; 3058 } 3059 3060 for (i = 0; i < table->count; i++) { 3061 if ((evclk <= table->entries[i].evclk) && 3062 (ecclk <= table->entries[i].ecclk)) { 3063 *voltage = table->entries[i].v; 3064 ret = 0; 3065 break; 3066 } 3067 } 3068 3069 /* if no match return the highest voltage */ 3070 if (ret) 3071 *voltage = table->entries[table->count - 1].v; 3072 3073 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage); 3074 3075 return ret; 3076 } 3077 3078 static bool si_dpm_vblank_too_short(void *handle) 3079 { 3080 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3081 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); 3082 /* we never hit the non-gddr5 limit so disable it */ 3083 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; 3084 3085 if (vblank_time < switch_limit) 3086 return true; 3087 else 3088 return false; 3089 3090 } 3091 3092 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, 3093 u32 arb_freq_src, u32 arb_freq_dest) 3094 { 3095 u32 mc_arb_dram_timing; 3096 u32 mc_arb_dram_timing2; 3097 u32 burst_time; 3098 u32 mc_cg_config; 3099 3100 switch (arb_freq_src) { 3101 case MC_CG_ARB_FREQ_F0: 3102 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 3103 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 3104 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; 3105 break; 3106 case MC_CG_ARB_FREQ_F1: 3107 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); 3108 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 3109 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; 3110 break; 3111 case MC_CG_ARB_FREQ_F2: 3112 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); 3113 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 3114 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; 3115 break; 3116 case MC_CG_ARB_FREQ_F3: 3117 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); 3118 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 3119 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; 3120 break; 3121 default: 3122 return -EINVAL; 3123 } 3124 3125 switch (arb_freq_dest) { 3126 case MC_CG_ARB_FREQ_F0: 3127 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); 3128 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 3129 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); 3130 break; 3131 case MC_CG_ARB_FREQ_F1: 3132 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 3133 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 3134 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); 3135 break; 3136 case MC_CG_ARB_FREQ_F2: 3137 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); 3138 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); 3139 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); 3140 break; 3141 case MC_CG_ARB_FREQ_F3: 3142 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); 3143 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); 3144 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); 3145 break; 3146 default: 3147 return -EINVAL; 3148 } 3149 3150 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; 3151 WREG32(MC_CG_CONFIG, mc_cg_config); 3152 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); 3153 3154 return 0; 3155 } 3156 3157 static void ni_update_current_ps(struct amdgpu_device *adev, 3158 struct amdgpu_ps *rps) 3159 { 3160 struct si_ps *new_ps = si_get_ps(rps); 3161 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3162 struct ni_power_info *ni_pi = ni_get_pi(adev); 3163 3164 eg_pi->current_rps = *rps; 3165 ni_pi->current_ps = *new_ps; 3166 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; 3167 adev->pm.dpm.current_ps = &eg_pi->current_rps; 3168 } 3169 3170 static void ni_update_requested_ps(struct amdgpu_device *adev, 3171 struct amdgpu_ps *rps) 3172 { 3173 struct si_ps *new_ps = si_get_ps(rps); 3174 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3175 struct ni_power_info *ni_pi = ni_get_pi(adev); 3176 3177 eg_pi->requested_rps = *rps; 3178 ni_pi->requested_ps = *new_ps; 3179 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; 3180 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; 3181 } 3182 3183 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, 3184 struct amdgpu_ps *new_ps, 3185 struct amdgpu_ps *old_ps) 3186 { 3187 struct si_ps *new_state = si_get_ps(new_ps); 3188 struct si_ps *current_state = si_get_ps(old_ps); 3189 3190 if ((new_ps->vclk == old_ps->vclk) && 3191 (new_ps->dclk == old_ps->dclk)) 3192 return; 3193 3194 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= 3195 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3196 return; 3197 3198 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3199 } 3200 3201 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, 3202 struct amdgpu_ps *new_ps, 3203 struct amdgpu_ps *old_ps) 3204 { 3205 struct si_ps *new_state = si_get_ps(new_ps); 3206 struct si_ps *current_state = si_get_ps(old_ps); 3207 3208 if ((new_ps->vclk == old_ps->vclk) && 3209 (new_ps->dclk == old_ps->dclk)) 3210 return; 3211 3212 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < 3213 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3214 return; 3215 3216 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3217 } 3218 3219 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) 3220 { 3221 unsigned int i; 3222 3223 for (i = 0; i < table->count; i++) 3224 if (voltage <= table->entries[i].value) 3225 return table->entries[i].value; 3226 3227 return table->entries[table->count - 1].value; 3228 } 3229 3230 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, 3231 u32 max_clock, u32 requested_clock) 3232 { 3233 unsigned int i; 3234 3235 if ((clocks == NULL) || (clocks->count == 0)) 3236 return (requested_clock < max_clock) ? requested_clock : max_clock; 3237 3238 for (i = 0; i < clocks->count; i++) { 3239 if (clocks->values[i] >= requested_clock) 3240 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; 3241 } 3242 3243 return (clocks->values[clocks->count - 1] < max_clock) ? 3244 clocks->values[clocks->count - 1] : max_clock; 3245 } 3246 3247 static u32 btc_get_valid_mclk(struct amdgpu_device *adev, 3248 u32 max_mclk, u32 requested_mclk) 3249 { 3250 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, 3251 max_mclk, requested_mclk); 3252 } 3253 3254 static u32 btc_get_valid_sclk(struct amdgpu_device *adev, 3255 u32 max_sclk, u32 requested_sclk) 3256 { 3257 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, 3258 max_sclk, requested_sclk); 3259 } 3260 3261 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table, 3262 u32 *max_clock) 3263 { 3264 u32 i, clock = 0; 3265 3266 if ((table == NULL) || (table->count == 0)) { 3267 *max_clock = clock; 3268 return; 3269 } 3270 3271 for (i = 0; i < table->count; i++) { 3272 if (clock < table->entries[i].clk) 3273 clock = table->entries[i].clk; 3274 } 3275 *max_clock = clock; 3276 } 3277 3278 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table, 3279 u32 clock, u16 max_voltage, u16 *voltage) 3280 { 3281 u32 i; 3282 3283 if ((table == NULL) || (table->count == 0)) 3284 return; 3285 3286 for (i= 0; i < table->count; i++) { 3287 if (clock <= table->entries[i].clk) { 3288 if (*voltage < table->entries[i].v) 3289 *voltage = (u16)((table->entries[i].v < max_voltage) ? 3290 table->entries[i].v : max_voltage); 3291 return; 3292 } 3293 } 3294 3295 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage; 3296 } 3297 3298 static void btc_adjust_clock_combinations(struct amdgpu_device *adev, 3299 const struct amdgpu_clock_and_voltage_limits *max_limits, 3300 struct rv7xx_pl *pl) 3301 { 3302 3303 if ((pl->mclk == 0) || (pl->sclk == 0)) 3304 return; 3305 3306 if (pl->mclk == pl->sclk) 3307 return; 3308 3309 if (pl->mclk > pl->sclk) { 3310 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) 3311 pl->sclk = btc_get_valid_sclk(adev, 3312 max_limits->sclk, 3313 (pl->mclk + 3314 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / 3315 adev->pm.dpm.dyn_state.mclk_sclk_ratio); 3316 } else { 3317 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) 3318 pl->mclk = btc_get_valid_mclk(adev, 3319 max_limits->mclk, 3320 pl->sclk - 3321 adev->pm.dpm.dyn_state.sclk_mclk_delta); 3322 } 3323 } 3324 3325 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, 3326 u16 max_vddc, u16 max_vddci, 3327 u16 *vddc, u16 *vddci) 3328 { 3329 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3330 u16 new_voltage; 3331 3332 if ((0 == *vddc) || (0 == *vddci)) 3333 return; 3334 3335 if (*vddc > *vddci) { 3336 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3337 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, 3338 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3339 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; 3340 } 3341 } else { 3342 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3343 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, 3344 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3345 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; 3346 } 3347 } 3348 } 3349 3350 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 3351 u32 *p, u32 *u) 3352 { 3353 u32 b_c = 0; 3354 u32 i_c; 3355 u32 tmp; 3356 3357 i_c = (i * r_c) / 100; 3358 tmp = i_c >> p_b; 3359 3360 while (tmp) { 3361 b_c++; 3362 tmp >>= 1; 3363 } 3364 3365 *u = (b_c + 1) / 2; 3366 *p = i_c / (1 << (2 * (*u))); 3367 } 3368 3369 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) 3370 { 3371 u32 k, a, ah, al; 3372 u32 t1; 3373 3374 if ((fl == 0) || (fh == 0) || (fl > fh)) 3375 return -EINVAL; 3376 3377 k = (100 * fh) / fl; 3378 t1 = (t * (k - 100)); 3379 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); 3380 a = (a + 5) / 10; 3381 ah = ((a * t) + 5000) / 10000; 3382 al = a - ah; 3383 3384 *th = t - ah; 3385 *tl = t + al; 3386 3387 return 0; 3388 } 3389 3390 static bool r600_is_uvd_state(u32 class, u32 class2) 3391 { 3392 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 3393 return true; 3394 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 3395 return true; 3396 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 3397 return true; 3398 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 3399 return true; 3400 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 3401 return true; 3402 return false; 3403 } 3404 3405 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev) 3406 { 3407 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); 3408 } 3409 3410 static void rv770_get_max_vddc(struct amdgpu_device *adev) 3411 { 3412 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3413 u16 vddc; 3414 3415 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc)) 3416 pi->max_vddc = 0; 3417 else 3418 pi->max_vddc = vddc; 3419 } 3420 3421 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) 3422 { 3423 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3424 struct amdgpu_atom_ss ss; 3425 3426 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3427 ASIC_INTERNAL_ENGINE_SS, 0); 3428 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3429 ASIC_INTERNAL_MEMORY_SS, 0); 3430 3431 if (pi->sclk_ss || pi->mclk_ss) 3432 pi->dynamic_ss = true; 3433 else 3434 pi->dynamic_ss = false; 3435 } 3436 3437 3438 static void si_apply_state_adjust_rules(struct amdgpu_device *adev, 3439 struct amdgpu_ps *rps) 3440 { 3441 struct si_ps *ps = si_get_ps(rps); 3442 struct amdgpu_clock_and_voltage_limits *max_limits; 3443 bool disable_mclk_switching = false; 3444 bool disable_sclk_switching = false; 3445 u32 mclk, sclk; 3446 u16 vddc, vddci, min_vce_voltage = 0; 3447 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 3448 u32 max_sclk = 0, max_mclk = 0; 3449 int i; 3450 3451 if (adev->asic_type == CHIP_HAINAN) { 3452 if ((adev->pdev->revision == 0x81) || 3453 (adev->pdev->revision == 0xC3) || 3454 (adev->pdev->device == 0x6664) || 3455 (adev->pdev->device == 0x6665) || 3456 (adev->pdev->device == 0x6667)) { 3457 max_sclk = 75000; 3458 } 3459 if ((adev->pdev->revision == 0xC3) || 3460 (adev->pdev->device == 0x6665)) { 3461 max_sclk = 60000; 3462 max_mclk = 80000; 3463 } 3464 } else if (adev->asic_type == CHIP_OLAND) { 3465 if ((adev->pdev->revision == 0xC7) || 3466 (adev->pdev->revision == 0x80) || 3467 (adev->pdev->revision == 0x81) || 3468 (adev->pdev->revision == 0x83) || 3469 (adev->pdev->revision == 0x87) || 3470 (adev->pdev->device == 0x6604) || 3471 (adev->pdev->device == 0x6605)) { 3472 max_sclk = 75000; 3473 } 3474 } 3475 3476 if (rps->vce_active) { 3477 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 3478 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; 3479 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, 3480 &min_vce_voltage); 3481 } else { 3482 rps->evclk = 0; 3483 rps->ecclk = 0; 3484 } 3485 3486 if ((adev->pm.dpm.new_active_crtc_count > 1) || 3487 si_dpm_vblank_too_short(adev)) 3488 disable_mclk_switching = true; 3489 3490 if (rps->vclk || rps->dclk) { 3491 disable_mclk_switching = true; 3492 disable_sclk_switching = true; 3493 } 3494 3495 if (adev->pm.ac_power) 3496 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3497 else 3498 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3499 3500 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3501 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3502 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3503 } 3504 if (adev->pm.ac_power == false) { 3505 for (i = 0; i < ps->performance_level_count; i++) { 3506 if (ps->performance_levels[i].mclk > max_limits->mclk) 3507 ps->performance_levels[i].mclk = max_limits->mclk; 3508 if (ps->performance_levels[i].sclk > max_limits->sclk) 3509 ps->performance_levels[i].sclk = max_limits->sclk; 3510 if (ps->performance_levels[i].vddc > max_limits->vddc) 3511 ps->performance_levels[i].vddc = max_limits->vddc; 3512 if (ps->performance_levels[i].vddci > max_limits->vddci) 3513 ps->performance_levels[i].vddci = max_limits->vddci; 3514 } 3515 } 3516 3517 /* limit clocks to max supported clocks based on voltage dependency tables */ 3518 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3519 &max_sclk_vddc); 3520 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3521 &max_mclk_vddci); 3522 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3523 &max_mclk_vddc); 3524 3525 for (i = 0; i < ps->performance_level_count; i++) { 3526 if (max_sclk_vddc) { 3527 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3528 ps->performance_levels[i].sclk = max_sclk_vddc; 3529 } 3530 if (max_mclk_vddci) { 3531 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3532 ps->performance_levels[i].mclk = max_mclk_vddci; 3533 } 3534 if (max_mclk_vddc) { 3535 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3536 ps->performance_levels[i].mclk = max_mclk_vddc; 3537 } 3538 if (max_mclk) { 3539 if (ps->performance_levels[i].mclk > max_mclk) 3540 ps->performance_levels[i].mclk = max_mclk; 3541 } 3542 if (max_sclk) { 3543 if (ps->performance_levels[i].sclk > max_sclk) 3544 ps->performance_levels[i].sclk = max_sclk; 3545 } 3546 } 3547 3548 /* XXX validate the min clocks required for display */ 3549 3550 if (disable_mclk_switching) { 3551 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3552 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3553 } else { 3554 mclk = ps->performance_levels[0].mclk; 3555 vddci = ps->performance_levels[0].vddci; 3556 } 3557 3558 if (disable_sclk_switching) { 3559 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3560 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3561 } else { 3562 sclk = ps->performance_levels[0].sclk; 3563 vddc = ps->performance_levels[0].vddc; 3564 } 3565 3566 if (rps->vce_active) { 3567 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) 3568 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; 3569 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) 3570 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; 3571 } 3572 3573 /* adjusted low state */ 3574 ps->performance_levels[0].sclk = sclk; 3575 ps->performance_levels[0].mclk = mclk; 3576 ps->performance_levels[0].vddc = vddc; 3577 ps->performance_levels[0].vddci = vddci; 3578 3579 if (disable_sclk_switching) { 3580 sclk = ps->performance_levels[0].sclk; 3581 for (i = 1; i < ps->performance_level_count; i++) { 3582 if (sclk < ps->performance_levels[i].sclk) 3583 sclk = ps->performance_levels[i].sclk; 3584 } 3585 for (i = 0; i < ps->performance_level_count; i++) { 3586 ps->performance_levels[i].sclk = sclk; 3587 ps->performance_levels[i].vddc = vddc; 3588 } 3589 } else { 3590 for (i = 1; i < ps->performance_level_count; i++) { 3591 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3592 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3593 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3594 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3595 } 3596 } 3597 3598 if (disable_mclk_switching) { 3599 mclk = ps->performance_levels[0].mclk; 3600 for (i = 1; i < ps->performance_level_count; i++) { 3601 if (mclk < ps->performance_levels[i].mclk) 3602 mclk = ps->performance_levels[i].mclk; 3603 } 3604 for (i = 0; i < ps->performance_level_count; i++) { 3605 ps->performance_levels[i].mclk = mclk; 3606 ps->performance_levels[i].vddci = vddci; 3607 } 3608 } else { 3609 for (i = 1; i < ps->performance_level_count; i++) { 3610 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3611 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3612 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3613 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3614 } 3615 } 3616 3617 for (i = 0; i < ps->performance_level_count; i++) 3618 btc_adjust_clock_combinations(adev, max_limits, 3619 &ps->performance_levels[i]); 3620 3621 for (i = 0; i < ps->performance_level_count; i++) { 3622 if (ps->performance_levels[i].vddc < min_vce_voltage) 3623 ps->performance_levels[i].vddc = min_vce_voltage; 3624 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3625 ps->performance_levels[i].sclk, 3626 max_limits->vddc, &ps->performance_levels[i].vddc); 3627 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3628 ps->performance_levels[i].mclk, 3629 max_limits->vddci, &ps->performance_levels[i].vddci); 3630 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3631 ps->performance_levels[i].mclk, 3632 max_limits->vddc, &ps->performance_levels[i].vddc); 3633 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3634 adev->clock.current_dispclk, 3635 max_limits->vddc, &ps->performance_levels[i].vddc); 3636 } 3637 3638 for (i = 0; i < ps->performance_level_count; i++) { 3639 btc_apply_voltage_delta_rules(adev, 3640 max_limits->vddc, max_limits->vddci, 3641 &ps->performance_levels[i].vddc, 3642 &ps->performance_levels[i].vddci); 3643 } 3644 3645 ps->dc_compatible = true; 3646 for (i = 0; i < ps->performance_level_count; i++) { 3647 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3648 ps->dc_compatible = false; 3649 } 3650 } 3651 3652 #if 0 3653 static int si_read_smc_soft_register(struct amdgpu_device *adev, 3654 u16 reg_offset, u32 *value) 3655 { 3656 struct si_power_info *si_pi = si_get_pi(adev); 3657 3658 return amdgpu_si_read_smc_sram_dword(adev, 3659 si_pi->soft_regs_start + reg_offset, value, 3660 si_pi->sram_end); 3661 } 3662 #endif 3663 3664 static int si_write_smc_soft_register(struct amdgpu_device *adev, 3665 u16 reg_offset, u32 value) 3666 { 3667 struct si_power_info *si_pi = si_get_pi(adev); 3668 3669 return amdgpu_si_write_smc_sram_dword(adev, 3670 si_pi->soft_regs_start + reg_offset, 3671 value, si_pi->sram_end); 3672 } 3673 3674 static bool si_is_special_1gb_platform(struct amdgpu_device *adev) 3675 { 3676 bool ret = false; 3677 u32 tmp, width, row, column, bank, density; 3678 bool is_memory_gddr5, is_special; 3679 3680 tmp = RREG32(MC_SEQ_MISC0); 3681 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3682 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3683 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3684 3685 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3686 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3687 3688 tmp = RREG32(MC_ARB_RAMCFG); 3689 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3690 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3691 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3692 3693 density = (1 << (row + column - 20 + bank)) * width; 3694 3695 if ((adev->pdev->device == 0x6819) && 3696 is_memory_gddr5 && is_special && (density == 0x400)) 3697 ret = true; 3698 3699 return ret; 3700 } 3701 3702 static void si_get_leakage_vddc(struct amdgpu_device *adev) 3703 { 3704 struct si_power_info *si_pi = si_get_pi(adev); 3705 u16 vddc, count = 0; 3706 int i, ret; 3707 3708 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3709 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3710 3711 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3712 si_pi->leakage_voltage.entries[count].voltage = vddc; 3713 si_pi->leakage_voltage.entries[count].leakage_index = 3714 SISLANDS_LEAKAGE_INDEX0 + i; 3715 count++; 3716 } 3717 } 3718 si_pi->leakage_voltage.count = count; 3719 } 3720 3721 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, 3722 u32 index, u16 *leakage_voltage) 3723 { 3724 struct si_power_info *si_pi = si_get_pi(adev); 3725 int i; 3726 3727 if (leakage_voltage == NULL) 3728 return -EINVAL; 3729 3730 if ((index & 0xff00) != 0xff00) 3731 return -EINVAL; 3732 3733 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3734 return -EINVAL; 3735 3736 if (index < SISLANDS_LEAKAGE_INDEX0) 3737 return -EINVAL; 3738 3739 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3740 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3741 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3742 return 0; 3743 } 3744 } 3745 return -EAGAIN; 3746 } 3747 3748 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) 3749 { 3750 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3751 bool want_thermal_protection; 3752 enum si_dpm_event_src dpm_event_src; 3753 3754 switch (sources) { 3755 case 0: 3756 default: 3757 want_thermal_protection = false; 3758 break; 3759 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL): 3760 want_thermal_protection = true; 3761 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL; 3762 break; 3763 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3764 want_thermal_protection = true; 3765 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL; 3766 break; 3767 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3768 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3769 want_thermal_protection = true; 3770 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3771 break; 3772 } 3773 3774 if (want_thermal_protection) { 3775 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3776 if (pi->thermal_protection) 3777 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3778 } else { 3779 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3780 } 3781 } 3782 3783 static void si_enable_auto_throttle_source(struct amdgpu_device *adev, 3784 enum si_dpm_auto_throttle_src source, 3785 bool enable) 3786 { 3787 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3788 3789 if (enable) { 3790 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3791 pi->active_auto_throttle_sources |= 1 << source; 3792 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3793 } 3794 } else { 3795 if (pi->active_auto_throttle_sources & (1 << source)) { 3796 pi->active_auto_throttle_sources &= ~(1 << source); 3797 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3798 } 3799 } 3800 } 3801 3802 static void si_start_dpm(struct amdgpu_device *adev) 3803 { 3804 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3805 } 3806 3807 static void si_stop_dpm(struct amdgpu_device *adev) 3808 { 3809 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3810 } 3811 3812 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable) 3813 { 3814 if (enable) 3815 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3816 else 3817 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3818 3819 } 3820 3821 #if 0 3822 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, 3823 u32 thermal_level) 3824 { 3825 PPSMC_Result ret; 3826 3827 if (thermal_level == 0) { 3828 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3829 if (ret == PPSMC_Result_OK) 3830 return 0; 3831 else 3832 return -EINVAL; 3833 } 3834 return 0; 3835 } 3836 3837 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) 3838 { 3839 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3840 } 3841 #endif 3842 3843 #if 0 3844 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) 3845 { 3846 if (ac_power) 3847 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3848 0 : -EINVAL; 3849 3850 return 0; 3851 } 3852 #endif 3853 3854 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, 3855 PPSMC_Msg msg, u32 parameter) 3856 { 3857 WREG32(SMC_SCRATCH0, parameter); 3858 return amdgpu_si_send_msg_to_smc(adev, msg); 3859 } 3860 3861 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) 3862 { 3863 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3864 return -EINVAL; 3865 3866 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3867 0 : -EINVAL; 3868 } 3869 3870 static int si_dpm_force_performance_level(void *handle, 3871 enum amd_dpm_forced_level level) 3872 { 3873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3874 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; 3875 struct si_ps *ps = si_get_ps(rps); 3876 u32 levels = ps->performance_level_count; 3877 3878 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 3879 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3880 return -EINVAL; 3881 3882 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3883 return -EINVAL; 3884 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { 3885 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3886 return -EINVAL; 3887 3888 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3889 return -EINVAL; 3890 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { 3891 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3892 return -EINVAL; 3893 3894 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3895 return -EINVAL; 3896 } 3897 3898 adev->pm.dpm.forced_level = level; 3899 3900 return 0; 3901 } 3902 3903 #if 0 3904 static int si_set_boot_state(struct amdgpu_device *adev) 3905 { 3906 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3907 0 : -EINVAL; 3908 } 3909 #endif 3910 3911 static int si_set_sw_state(struct amdgpu_device *adev) 3912 { 3913 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3914 0 : -EINVAL; 3915 } 3916 3917 static int si_halt_smc(struct amdgpu_device *adev) 3918 { 3919 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3920 return -EINVAL; 3921 3922 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3923 0 : -EINVAL; 3924 } 3925 3926 static int si_resume_smc(struct amdgpu_device *adev) 3927 { 3928 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3929 return -EINVAL; 3930 3931 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3932 0 : -EINVAL; 3933 } 3934 3935 static void si_dpm_start_smc(struct amdgpu_device *adev) 3936 { 3937 amdgpu_si_program_jump_on_start(adev); 3938 amdgpu_si_start_smc(adev); 3939 amdgpu_si_smc_clock(adev, true); 3940 } 3941 3942 static void si_dpm_stop_smc(struct amdgpu_device *adev) 3943 { 3944 amdgpu_si_reset_smc(adev); 3945 amdgpu_si_smc_clock(adev, false); 3946 } 3947 3948 static int si_process_firmware_header(struct amdgpu_device *adev) 3949 { 3950 struct si_power_info *si_pi = si_get_pi(adev); 3951 u32 tmp; 3952 int ret; 3953 3954 ret = amdgpu_si_read_smc_sram_dword(adev, 3955 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3956 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3957 &tmp, si_pi->sram_end); 3958 if (ret) 3959 return ret; 3960 3961 si_pi->state_table_start = tmp; 3962 3963 ret = amdgpu_si_read_smc_sram_dword(adev, 3964 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3965 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3966 &tmp, si_pi->sram_end); 3967 if (ret) 3968 return ret; 3969 3970 si_pi->soft_regs_start = tmp; 3971 3972 ret = amdgpu_si_read_smc_sram_dword(adev, 3973 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3974 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3975 &tmp, si_pi->sram_end); 3976 if (ret) 3977 return ret; 3978 3979 si_pi->mc_reg_table_start = tmp; 3980 3981 ret = amdgpu_si_read_smc_sram_dword(adev, 3982 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3983 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3984 &tmp, si_pi->sram_end); 3985 if (ret) 3986 return ret; 3987 3988 si_pi->fan_table_start = tmp; 3989 3990 ret = amdgpu_si_read_smc_sram_dword(adev, 3991 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3992 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3993 &tmp, si_pi->sram_end); 3994 if (ret) 3995 return ret; 3996 3997 si_pi->arb_table_start = tmp; 3998 3999 ret = amdgpu_si_read_smc_sram_dword(adev, 4000 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4001 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4002 &tmp, si_pi->sram_end); 4003 if (ret) 4004 return ret; 4005 4006 si_pi->cac_table_start = tmp; 4007 4008 ret = amdgpu_si_read_smc_sram_dword(adev, 4009 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4010 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4011 &tmp, si_pi->sram_end); 4012 if (ret) 4013 return ret; 4014 4015 si_pi->dte_table_start = tmp; 4016 4017 ret = amdgpu_si_read_smc_sram_dword(adev, 4018 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4019 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4020 &tmp, si_pi->sram_end); 4021 if (ret) 4022 return ret; 4023 4024 si_pi->spll_table_start = tmp; 4025 4026 ret = amdgpu_si_read_smc_sram_dword(adev, 4027 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4028 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4029 &tmp, si_pi->sram_end); 4030 if (ret) 4031 return ret; 4032 4033 si_pi->papm_cfg_table_start = tmp; 4034 4035 return ret; 4036 } 4037 4038 static void si_read_clock_registers(struct amdgpu_device *adev) 4039 { 4040 struct si_power_info *si_pi = si_get_pi(adev); 4041 4042 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 4043 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 4044 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 4045 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 4046 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 4047 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 4048 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 4049 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 4050 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 4051 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 4052 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 4053 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 4054 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 4055 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 4056 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 4057 } 4058 4059 static void si_enable_thermal_protection(struct amdgpu_device *adev, 4060 bool enable) 4061 { 4062 if (enable) 4063 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 4064 else 4065 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 4066 } 4067 4068 static void si_enable_acpi_power_management(struct amdgpu_device *adev) 4069 { 4070 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 4071 } 4072 4073 #if 0 4074 static int si_enter_ulp_state(struct amdgpu_device *adev) 4075 { 4076 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 4077 4078 udelay(25000); 4079 4080 return 0; 4081 } 4082 4083 static int si_exit_ulp_state(struct amdgpu_device *adev) 4084 { 4085 int i; 4086 4087 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 4088 4089 udelay(7000); 4090 4091 for (i = 0; i < adev->usec_timeout; i++) { 4092 if (RREG32(SMC_RESP_0) == 1) 4093 break; 4094 udelay(1000); 4095 } 4096 4097 return 0; 4098 } 4099 #endif 4100 4101 static int si_notify_smc_display_change(struct amdgpu_device *adev, 4102 bool has_display) 4103 { 4104 PPSMC_Msg msg = has_display ? 4105 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 4106 4107 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4108 0 : -EINVAL; 4109 } 4110 4111 static void si_program_response_times(struct amdgpu_device *adev) 4112 { 4113 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 4114 u32 vddc_dly, acpi_dly, vbi_dly; 4115 u32 reference_clock; 4116 4117 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 4118 4119 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; 4120 4121 if (voltage_response_time == 0) 4122 voltage_response_time = 1000; 4123 4124 acpi_delay_time = 15000; 4125 vbi_time_out = 100000; 4126 4127 reference_clock = amdgpu_asic_get_xclk(adev); 4128 4129 vddc_dly = (voltage_response_time * reference_clock) / 100; 4130 acpi_dly = (acpi_delay_time * reference_clock) / 100; 4131 vbi_dly = (vbi_time_out * reference_clock) / 100; 4132 4133 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 4134 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 4135 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 4136 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 4137 } 4138 4139 static void si_program_ds_registers(struct amdgpu_device *adev) 4140 { 4141 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4142 u32 tmp; 4143 4144 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */ 4145 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0) 4146 tmp = 0x10; 4147 else 4148 tmp = 0x1; 4149 4150 if (eg_pi->sclk_deep_sleep) { 4151 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 4152 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 4153 ~AUTOSCALE_ON_SS_CLEAR); 4154 } 4155 } 4156 4157 static void si_program_display_gap(struct amdgpu_device *adev) 4158 { 4159 u32 tmp, pipe; 4160 int i; 4161 4162 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 4163 if (adev->pm.dpm.new_active_crtc_count > 0) 4164 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 4165 else 4166 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 4167 4168 if (adev->pm.dpm.new_active_crtc_count > 1) 4169 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 4170 else 4171 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 4172 4173 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 4174 4175 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 4176 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 4177 4178 if ((adev->pm.dpm.new_active_crtc_count > 0) && 4179 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 4180 /* find the first active crtc */ 4181 for (i = 0; i < adev->mode_info.num_crtc; i++) { 4182 if (adev->pm.dpm.new_active_crtcs & (1 << i)) 4183 break; 4184 } 4185 if (i == adev->mode_info.num_crtc) 4186 pipe = 0; 4187 else 4188 pipe = i; 4189 4190 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 4191 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 4192 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 4193 } 4194 4195 /* Setting this to false forces the performance state to low if the crtcs are disabled. 4196 * This can be a problem on PowerXpress systems or if you want to use the card 4197 * for offscreen rendering or compute if there are no crtcs enabled. 4198 */ 4199 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); 4200 } 4201 4202 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) 4203 { 4204 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4205 4206 if (enable) { 4207 if (pi->sclk_ss) 4208 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 4209 } else { 4210 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 4211 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 4212 } 4213 } 4214 4215 static void si_setup_bsp(struct amdgpu_device *adev) 4216 { 4217 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4218 u32 xclk = amdgpu_asic_get_xclk(adev); 4219 4220 r600_calculate_u_and_p(pi->asi, 4221 xclk, 4222 16, 4223 &pi->bsp, 4224 &pi->bsu); 4225 4226 r600_calculate_u_and_p(pi->pasi, 4227 xclk, 4228 16, 4229 &pi->pbsp, 4230 &pi->pbsu); 4231 4232 4233 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 4234 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 4235 4236 WREG32(CG_BSP, pi->dsp); 4237 } 4238 4239 static void si_program_git(struct amdgpu_device *adev) 4240 { 4241 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 4242 } 4243 4244 static void si_program_tp(struct amdgpu_device *adev) 4245 { 4246 int i; 4247 enum r600_td td = R600_TD_DFLT; 4248 4249 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 4250 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 4251 4252 if (td == R600_TD_AUTO) 4253 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 4254 else 4255 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 4256 4257 if (td == R600_TD_UP) 4258 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 4259 4260 if (td == R600_TD_DOWN) 4261 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 4262 } 4263 4264 static void si_program_tpp(struct amdgpu_device *adev) 4265 { 4266 WREG32(CG_TPC, R600_TPC_DFLT); 4267 } 4268 4269 static void si_program_sstp(struct amdgpu_device *adev) 4270 { 4271 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 4272 } 4273 4274 static void si_enable_display_gap(struct amdgpu_device *adev) 4275 { 4276 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 4277 4278 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 4279 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 4280 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 4281 4282 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 4283 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 4284 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 4285 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 4286 } 4287 4288 static void si_program_vc(struct amdgpu_device *adev) 4289 { 4290 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4291 4292 WREG32(CG_FTV, pi->vrc); 4293 } 4294 4295 static void si_clear_vc(struct amdgpu_device *adev) 4296 { 4297 WREG32(CG_FTV, 0); 4298 } 4299 4300 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 4301 { 4302 u8 mc_para_index; 4303 4304 if (memory_clock < 10000) 4305 mc_para_index = 0; 4306 else if (memory_clock >= 80000) 4307 mc_para_index = 0x0f; 4308 else 4309 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 4310 return mc_para_index; 4311 } 4312 4313 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 4314 { 4315 u8 mc_para_index; 4316 4317 if (strobe_mode) { 4318 if (memory_clock < 12500) 4319 mc_para_index = 0x00; 4320 else if (memory_clock > 47500) 4321 mc_para_index = 0x0f; 4322 else 4323 mc_para_index = (u8)((memory_clock - 10000) / 2500); 4324 } else { 4325 if (memory_clock < 65000) 4326 mc_para_index = 0x00; 4327 else if (memory_clock > 135000) 4328 mc_para_index = 0x0f; 4329 else 4330 mc_para_index = (u8)((memory_clock - 60000) / 5000); 4331 } 4332 return mc_para_index; 4333 } 4334 4335 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) 4336 { 4337 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4338 bool strobe_mode = false; 4339 u8 result = 0; 4340 4341 if (mclk <= pi->mclk_strobe_mode_threshold) 4342 strobe_mode = true; 4343 4344 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 4345 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 4346 else 4347 result = si_get_ddr3_mclk_frequency_ratio(mclk); 4348 4349 if (strobe_mode) 4350 result |= SISLANDS_SMC_STROBE_ENABLE; 4351 4352 return result; 4353 } 4354 4355 static int si_upload_firmware(struct amdgpu_device *adev) 4356 { 4357 struct si_power_info *si_pi = si_get_pi(adev); 4358 4359 amdgpu_si_reset_smc(adev); 4360 amdgpu_si_smc_clock(adev, false); 4361 4362 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); 4363 } 4364 4365 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, 4366 const struct atom_voltage_table *table, 4367 const struct amdgpu_phase_shedding_limits_table *limits) 4368 { 4369 u32 data, num_bits, num_levels; 4370 4371 if ((table == NULL) || (limits == NULL)) 4372 return false; 4373 4374 data = table->mask_low; 4375 4376 num_bits = hweight32(data); 4377 4378 if (num_bits == 0) 4379 return false; 4380 4381 num_levels = (1 << num_bits); 4382 4383 if (table->count != num_levels) 4384 return false; 4385 4386 if (limits->count != (num_levels - 1)) 4387 return false; 4388 4389 return true; 4390 } 4391 4392 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, 4393 u32 max_voltage_steps, 4394 struct atom_voltage_table *voltage_table) 4395 { 4396 unsigned int i, diff; 4397 4398 if (voltage_table->count <= max_voltage_steps) 4399 return; 4400 4401 diff = voltage_table->count - max_voltage_steps; 4402 4403 for (i= 0; i < max_voltage_steps; i++) 4404 voltage_table->entries[i] = voltage_table->entries[i + diff]; 4405 4406 voltage_table->count = max_voltage_steps; 4407 } 4408 4409 static int si_get_svi2_voltage_table(struct amdgpu_device *adev, 4410 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, 4411 struct atom_voltage_table *voltage_table) 4412 { 4413 u32 i; 4414 4415 if (voltage_dependency_table == NULL) 4416 return -EINVAL; 4417 4418 voltage_table->mask_low = 0; 4419 voltage_table->phase_delay = 0; 4420 4421 voltage_table->count = voltage_dependency_table->count; 4422 for (i = 0; i < voltage_table->count; i++) { 4423 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 4424 voltage_table->entries[i].smio_low = 0; 4425 } 4426 4427 return 0; 4428 } 4429 4430 static int si_construct_voltage_tables(struct amdgpu_device *adev) 4431 { 4432 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4433 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4434 struct si_power_info *si_pi = si_get_pi(adev); 4435 int ret; 4436 4437 if (pi->voltage_control) { 4438 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4439 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 4440 if (ret) 4441 return ret; 4442 4443 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4444 si_trim_voltage_table_to_fit_state_table(adev, 4445 SISLANDS_MAX_NO_VREG_STEPS, 4446 &eg_pi->vddc_voltage_table); 4447 } else if (si_pi->voltage_control_svi2) { 4448 ret = si_get_svi2_voltage_table(adev, 4449 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4450 &eg_pi->vddc_voltage_table); 4451 if (ret) 4452 return ret; 4453 } else { 4454 return -EINVAL; 4455 } 4456 4457 if (eg_pi->vddci_control) { 4458 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, 4459 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4460 if (ret) 4461 return ret; 4462 4463 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4464 si_trim_voltage_table_to_fit_state_table(adev, 4465 SISLANDS_MAX_NO_VREG_STEPS, 4466 &eg_pi->vddci_voltage_table); 4467 } 4468 if (si_pi->vddci_control_svi2) { 4469 ret = si_get_svi2_voltage_table(adev, 4470 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4471 &eg_pi->vddci_voltage_table); 4472 if (ret) 4473 return ret; 4474 } 4475 4476 if (pi->mvdd_control) { 4477 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, 4478 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4479 4480 if (ret) { 4481 pi->mvdd_control = false; 4482 return ret; 4483 } 4484 4485 if (si_pi->mvdd_voltage_table.count == 0) { 4486 pi->mvdd_control = false; 4487 return -EINVAL; 4488 } 4489 4490 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4491 si_trim_voltage_table_to_fit_state_table(adev, 4492 SISLANDS_MAX_NO_VREG_STEPS, 4493 &si_pi->mvdd_voltage_table); 4494 } 4495 4496 if (si_pi->vddc_phase_shed_control) { 4497 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4498 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4499 if (ret) 4500 si_pi->vddc_phase_shed_control = false; 4501 4502 if ((si_pi->vddc_phase_shed_table.count == 0) || 4503 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4504 si_pi->vddc_phase_shed_control = false; 4505 } 4506 4507 return 0; 4508 } 4509 4510 static void si_populate_smc_voltage_table(struct amdgpu_device *adev, 4511 const struct atom_voltage_table *voltage_table, 4512 SISLANDS_SMC_STATETABLE *table) 4513 { 4514 unsigned int i; 4515 4516 for (i = 0; i < voltage_table->count; i++) 4517 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4518 } 4519 4520 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev, 4521 SISLANDS_SMC_STATETABLE *table) 4522 { 4523 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4524 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4525 struct si_power_info *si_pi = si_get_pi(adev); 4526 u8 i; 4527 4528 if (si_pi->voltage_control_svi2) { 4529 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4530 si_pi->svc_gpio_id); 4531 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4532 si_pi->svd_gpio_id); 4533 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4534 2); 4535 } else { 4536 if (eg_pi->vddc_voltage_table.count) { 4537 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); 4538 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4539 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4540 4541 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4542 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4543 table->maxVDDCIndexInPPTable = i; 4544 break; 4545 } 4546 } 4547 } 4548 4549 if (eg_pi->vddci_voltage_table.count) { 4550 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); 4551 4552 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4553 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4554 } 4555 4556 4557 if (si_pi->mvdd_voltage_table.count) { 4558 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); 4559 4560 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4561 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4562 } 4563 4564 if (si_pi->vddc_phase_shed_control) { 4565 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, 4566 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4567 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); 4568 4569 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4570 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4571 4572 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4573 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4574 } else { 4575 si_pi->vddc_phase_shed_control = false; 4576 } 4577 } 4578 } 4579 4580 return 0; 4581 } 4582 4583 static int si_populate_voltage_value(struct amdgpu_device *adev, 4584 const struct atom_voltage_table *table, 4585 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4586 { 4587 unsigned int i; 4588 4589 for (i = 0; i < table->count; i++) { 4590 if (value <= table->entries[i].value) { 4591 voltage->index = (u8)i; 4592 voltage->value = cpu_to_be16(table->entries[i].value); 4593 break; 4594 } 4595 } 4596 4597 if (i >= table->count) 4598 return -EINVAL; 4599 4600 return 0; 4601 } 4602 4603 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, 4604 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4605 { 4606 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4607 struct si_power_info *si_pi = si_get_pi(adev); 4608 4609 if (pi->mvdd_control) { 4610 if (mclk <= pi->mvdd_split_frequency) 4611 voltage->index = 0; 4612 else 4613 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4614 4615 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4616 } 4617 return 0; 4618 } 4619 4620 static int si_get_std_voltage_value(struct amdgpu_device *adev, 4621 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4622 u16 *std_voltage) 4623 { 4624 u16 v_index; 4625 bool voltage_found = false; 4626 *std_voltage = be16_to_cpu(voltage->value); 4627 4628 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4629 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4630 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4631 return -EINVAL; 4632 4633 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4634 if (be16_to_cpu(voltage->value) == 4635 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4636 voltage_found = true; 4637 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4638 *std_voltage = 4639 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4640 else 4641 *std_voltage = 4642 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4643 break; 4644 } 4645 } 4646 4647 if (!voltage_found) { 4648 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4649 if (be16_to_cpu(voltage->value) <= 4650 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4651 voltage_found = true; 4652 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4653 *std_voltage = 4654 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4655 else 4656 *std_voltage = 4657 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4658 break; 4659 } 4660 } 4661 } 4662 } else { 4663 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4664 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4665 } 4666 } 4667 4668 return 0; 4669 } 4670 4671 static int si_populate_std_voltage_value(struct amdgpu_device *adev, 4672 u16 value, u8 index, 4673 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4674 { 4675 voltage->index = index; 4676 voltage->value = cpu_to_be16(value); 4677 4678 return 0; 4679 } 4680 4681 static int si_populate_phase_shedding_value(struct amdgpu_device *adev, 4682 const struct amdgpu_phase_shedding_limits_table *limits, 4683 u16 voltage, u32 sclk, u32 mclk, 4684 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4685 { 4686 unsigned int i; 4687 4688 for (i = 0; i < limits->count; i++) { 4689 if ((voltage <= limits->entries[i].voltage) && 4690 (sclk <= limits->entries[i].sclk) && 4691 (mclk <= limits->entries[i].mclk)) 4692 break; 4693 } 4694 4695 smc_voltage->phase_settings = (u8)i; 4696 4697 return 0; 4698 } 4699 4700 static int si_init_arb_table_index(struct amdgpu_device *adev) 4701 { 4702 struct si_power_info *si_pi = si_get_pi(adev); 4703 u32 tmp; 4704 int ret; 4705 4706 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4707 &tmp, si_pi->sram_end); 4708 if (ret) 4709 return ret; 4710 4711 tmp &= 0x00FFFFFF; 4712 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4713 4714 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, 4715 tmp, si_pi->sram_end); 4716 } 4717 4718 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) 4719 { 4720 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4721 } 4722 4723 static int si_reset_to_default(struct amdgpu_device *adev) 4724 { 4725 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4726 0 : -EINVAL; 4727 } 4728 4729 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) 4730 { 4731 struct si_power_info *si_pi = si_get_pi(adev); 4732 u32 tmp; 4733 int ret; 4734 4735 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4736 &tmp, si_pi->sram_end); 4737 if (ret) 4738 return ret; 4739 4740 tmp = (tmp >> 24) & 0xff; 4741 4742 if (tmp == MC_CG_ARB_FREQ_F0) 4743 return 0; 4744 4745 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); 4746 } 4747 4748 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, 4749 u32 engine_clock) 4750 { 4751 u32 dram_rows; 4752 u32 dram_refresh_rate; 4753 u32 mc_arb_rfsh_rate; 4754 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4755 4756 if (tmp >= 4) 4757 dram_rows = 16384; 4758 else 4759 dram_rows = 1 << (tmp + 10); 4760 4761 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4762 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4763 4764 return mc_arb_rfsh_rate; 4765 } 4766 4767 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, 4768 struct rv7xx_pl *pl, 4769 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4770 { 4771 u32 dram_timing; 4772 u32 dram_timing2; 4773 u32 burst_time; 4774 int ret; 4775 4776 arb_regs->mc_arb_rfsh_rate = 4777 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); 4778 4779 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk, 4780 pl->mclk); 4781 if (ret) 4782 return ret; 4783 4784 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4785 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4786 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4787 4788 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4789 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4790 arb_regs->mc_arb_burst_time = (u8)burst_time; 4791 4792 return 0; 4793 } 4794 4795 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, 4796 struct amdgpu_ps *amdgpu_state, 4797 unsigned int first_arb_set) 4798 { 4799 struct si_power_info *si_pi = si_get_pi(adev); 4800 struct si_ps *state = si_get_ps(amdgpu_state); 4801 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4802 int i, ret = 0; 4803 4804 for (i = 0; i < state->performance_level_count; i++) { 4805 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4806 if (ret) 4807 break; 4808 ret = amdgpu_si_copy_bytes_to_smc(adev, 4809 si_pi->arb_table_start + 4810 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4811 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4812 (u8 *)&arb_regs, 4813 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4814 si_pi->sram_end); 4815 if (ret) 4816 break; 4817 } 4818 4819 return ret; 4820 } 4821 4822 static int si_program_memory_timing_parameters(struct amdgpu_device *adev, 4823 struct amdgpu_ps *amdgpu_new_state) 4824 { 4825 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state, 4826 SISLANDS_DRIVER_STATE_ARB_INDEX); 4827 } 4828 4829 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev, 4830 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4831 { 4832 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4833 struct si_power_info *si_pi = si_get_pi(adev); 4834 4835 if (pi->mvdd_control) 4836 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, 4837 si_pi->mvdd_bootup_value, voltage); 4838 4839 return 0; 4840 } 4841 4842 static int si_populate_smc_initial_state(struct amdgpu_device *adev, 4843 struct amdgpu_ps *amdgpu_initial_state, 4844 SISLANDS_SMC_STATETABLE *table) 4845 { 4846 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); 4847 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4848 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4849 struct si_power_info *si_pi = si_get_pi(adev); 4850 u32 reg; 4851 int ret; 4852 4853 table->initialState.level.mclk.vDLL_CNTL = 4854 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4855 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = 4856 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4857 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = 4858 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4859 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = 4860 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4861 table->initialState.level.mclk.vMPLL_FUNC_CNTL = 4862 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4863 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = 4864 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4865 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = 4866 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4867 table->initialState.level.mclk.vMPLL_SS = 4868 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4869 table->initialState.level.mclk.vMPLL_SS2 = 4870 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4871 4872 table->initialState.level.mclk.mclk_value = 4873 cpu_to_be32(initial_state->performance_levels[0].mclk); 4874 4875 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = 4876 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4877 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 4878 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4879 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 4880 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4881 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 4882 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4883 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = 4884 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4885 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4886 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4887 4888 table->initialState.level.sclk.sclk_value = 4889 cpu_to_be32(initial_state->performance_levels[0].sclk); 4890 4891 table->initialState.level.arbRefreshState = 4892 SISLANDS_INITIAL_STATE_ARB_INDEX; 4893 4894 table->initialState.level.ACIndex = 0; 4895 4896 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 4897 initial_state->performance_levels[0].vddc, 4898 &table->initialState.level.vddc); 4899 4900 if (!ret) { 4901 u16 std_vddc; 4902 4903 ret = si_get_std_voltage_value(adev, 4904 &table->initialState.level.vddc, 4905 &std_vddc); 4906 if (!ret) 4907 si_populate_std_voltage_value(adev, std_vddc, 4908 table->initialState.level.vddc.index, 4909 &table->initialState.level.std_vddc); 4910 } 4911 4912 if (eg_pi->vddci_control) 4913 si_populate_voltage_value(adev, 4914 &eg_pi->vddci_voltage_table, 4915 initial_state->performance_levels[0].vddci, 4916 &table->initialState.level.vddci); 4917 4918 if (si_pi->vddc_phase_shed_control) 4919 si_populate_phase_shedding_value(adev, 4920 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 4921 initial_state->performance_levels[0].vddc, 4922 initial_state->performance_levels[0].sclk, 4923 initial_state->performance_levels[0].mclk, 4924 &table->initialState.level.vddc); 4925 4926 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd); 4927 4928 reg = CG_R(0xffff) | CG_L(0); 4929 table->initialState.level.aT = cpu_to_be32(reg); 4930 table->initialState.level.bSP = cpu_to_be32(pi->dsp); 4931 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; 4932 4933 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 4934 table->initialState.level.strobeMode = 4935 si_get_strobe_mode_settings(adev, 4936 initial_state->performance_levels[0].mclk); 4937 4938 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4939 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4940 else 4941 table->initialState.level.mcFlags = 0; 4942 } 4943 4944 table->initialState.levelCount = 1; 4945 4946 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4947 4948 table->initialState.level.dpm2.MaxPS = 0; 4949 table->initialState.level.dpm2.NearTDPDec = 0; 4950 table->initialState.level.dpm2.AboveSafeInc = 0; 4951 table->initialState.level.dpm2.BelowSafeInc = 0; 4952 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; 4953 4954 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4955 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); 4956 4957 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4958 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 4959 4960 return 0; 4961 } 4962 4963 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev, 4964 u32 sys_mask, 4965 enum si_pcie_gen asic_gen, 4966 enum si_pcie_gen default_gen) 4967 { 4968 switch (asic_gen) { 4969 case SI_PCIE_GEN1: 4970 return SI_PCIE_GEN1; 4971 case SI_PCIE_GEN2: 4972 return SI_PCIE_GEN2; 4973 case SI_PCIE_GEN3: 4974 return SI_PCIE_GEN3; 4975 default: 4976 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) && 4977 (default_gen == SI_PCIE_GEN3)) 4978 return SI_PCIE_GEN3; 4979 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) && 4980 (default_gen == SI_PCIE_GEN2)) 4981 return SI_PCIE_GEN2; 4982 else 4983 return SI_PCIE_GEN1; 4984 } 4985 return SI_PCIE_GEN1; 4986 } 4987 4988 static int si_populate_smc_acpi_state(struct amdgpu_device *adev, 4989 SISLANDS_SMC_STATETABLE *table) 4990 { 4991 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4992 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4993 struct si_power_info *si_pi = si_get_pi(adev); 4994 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4995 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4996 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4997 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4998 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4999 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5000 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5001 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5002 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5003 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5004 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5005 u32 reg; 5006 int ret; 5007 5008 table->ACPIState = table->initialState; 5009 5010 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 5011 5012 if (pi->acpi_vddc) { 5013 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5014 pi->acpi_vddc, &table->ACPIState.level.vddc); 5015 if (!ret) { 5016 u16 std_vddc; 5017 5018 ret = si_get_std_voltage_value(adev, 5019 &table->ACPIState.level.vddc, &std_vddc); 5020 if (!ret) 5021 si_populate_std_voltage_value(adev, std_vddc, 5022 table->ACPIState.level.vddc.index, 5023 &table->ACPIState.level.std_vddc); 5024 } 5025 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; 5026 5027 if (si_pi->vddc_phase_shed_control) { 5028 si_populate_phase_shedding_value(adev, 5029 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5030 pi->acpi_vddc, 5031 0, 5032 0, 5033 &table->ACPIState.level.vddc); 5034 } 5035 } else { 5036 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5037 pi->min_vddc_in_table, &table->ACPIState.level.vddc); 5038 if (!ret) { 5039 u16 std_vddc; 5040 5041 ret = si_get_std_voltage_value(adev, 5042 &table->ACPIState.level.vddc, &std_vddc); 5043 5044 if (!ret) 5045 si_populate_std_voltage_value(adev, std_vddc, 5046 table->ACPIState.level.vddc.index, 5047 &table->ACPIState.level.std_vddc); 5048 } 5049 table->ACPIState.level.gen2PCIE = 5050 (u8)si_gen_pcie_gen_support(adev, 5051 si_pi->sys_pcie_mask, 5052 si_pi->boot_pcie_gen, 5053 SI_PCIE_GEN1); 5054 5055 if (si_pi->vddc_phase_shed_control) 5056 si_populate_phase_shedding_value(adev, 5057 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5058 pi->min_vddc_in_table, 5059 0, 5060 0, 5061 &table->ACPIState.level.vddc); 5062 } 5063 5064 if (pi->acpi_vddc) { 5065 if (eg_pi->acpi_vddci) 5066 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5067 eg_pi->acpi_vddci, 5068 &table->ACPIState.level.vddci); 5069 } 5070 5071 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 5072 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5073 5074 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 5075 5076 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 5077 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 5078 5079 table->ACPIState.level.mclk.vDLL_CNTL = 5080 cpu_to_be32(dll_cntl); 5081 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = 5082 cpu_to_be32(mclk_pwrmgt_cntl); 5083 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = 5084 cpu_to_be32(mpll_ad_func_cntl); 5085 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = 5086 cpu_to_be32(mpll_dq_func_cntl); 5087 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = 5088 cpu_to_be32(mpll_func_cntl); 5089 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = 5090 cpu_to_be32(mpll_func_cntl_1); 5091 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = 5092 cpu_to_be32(mpll_func_cntl_2); 5093 table->ACPIState.level.mclk.vMPLL_SS = 5094 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 5095 table->ACPIState.level.mclk.vMPLL_SS2 = 5096 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 5097 5098 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = 5099 cpu_to_be32(spll_func_cntl); 5100 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 5101 cpu_to_be32(spll_func_cntl_2); 5102 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 5103 cpu_to_be32(spll_func_cntl_3); 5104 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 5105 cpu_to_be32(spll_func_cntl_4); 5106 5107 table->ACPIState.level.mclk.mclk_value = 0; 5108 table->ACPIState.level.sclk.sclk_value = 0; 5109 5110 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd); 5111 5112 if (eg_pi->dynamic_ac_timing) 5113 table->ACPIState.level.ACIndex = 0; 5114 5115 table->ACPIState.level.dpm2.MaxPS = 0; 5116 table->ACPIState.level.dpm2.NearTDPDec = 0; 5117 table->ACPIState.level.dpm2.AboveSafeInc = 0; 5118 table->ACPIState.level.dpm2.BelowSafeInc = 0; 5119 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; 5120 5121 reg = MIN_POWER_MASK | MAX_POWER_MASK; 5122 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); 5123 5124 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 5125 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 5126 5127 return 0; 5128 } 5129 5130 static int si_populate_ulv_state(struct amdgpu_device *adev, 5131 struct SISLANDS_SMC_SWSTATE_SINGLE *state) 5132 { 5133 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5134 struct si_power_info *si_pi = si_get_pi(adev); 5135 struct si_ulv_param *ulv = &si_pi->ulv; 5136 u32 sclk_in_sr = 1350; /* ??? */ 5137 int ret; 5138 5139 ret = si_convert_power_level_to_smc(adev, &ulv->pl, 5140 &state->level); 5141 if (!ret) { 5142 if (eg_pi->sclk_deep_sleep) { 5143 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5144 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5145 else 5146 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5147 } 5148 if (ulv->one_pcie_lane_in_ulv) 5149 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 5150 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 5151 state->level.ACIndex = 1; 5152 state->level.std_vddc = state->level.vddc; 5153 state->levelCount = 1; 5154 5155 state->flags |= PPSMC_SWSTATE_FLAG_DC; 5156 } 5157 5158 return ret; 5159 } 5160 5161 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) 5162 { 5163 struct si_power_info *si_pi = si_get_pi(adev); 5164 struct si_ulv_param *ulv = &si_pi->ulv; 5165 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 5166 int ret; 5167 5168 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, 5169 &arb_regs); 5170 if (ret) 5171 return ret; 5172 5173 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 5174 ulv->volt_change_delay); 5175 5176 ret = amdgpu_si_copy_bytes_to_smc(adev, 5177 si_pi->arb_table_start + 5178 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5179 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5180 (u8 *)&arb_regs, 5181 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5182 si_pi->sram_end); 5183 5184 return ret; 5185 } 5186 5187 static void si_get_mvdd_configuration(struct amdgpu_device *adev) 5188 { 5189 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5190 5191 pi->mvdd_split_frequency = 30000; 5192 } 5193 5194 static int si_init_smc_table(struct amdgpu_device *adev) 5195 { 5196 struct si_power_info *si_pi = si_get_pi(adev); 5197 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; 5198 const struct si_ulv_param *ulv = &si_pi->ulv; 5199 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 5200 int ret; 5201 u32 lane_width; 5202 u32 vr_hot_gpio; 5203 5204 si_populate_smc_voltage_tables(adev, table); 5205 5206 switch (adev->pm.int_thermal_type) { 5207 case THERMAL_TYPE_SI: 5208 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 5209 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 5210 break; 5211 case THERMAL_TYPE_NONE: 5212 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 5213 break; 5214 default: 5215 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 5216 break; 5217 } 5218 5219 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 5220 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 5221 5222 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 5223 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819)) 5224 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 5225 } 5226 5227 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 5228 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 5229 5230 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5231 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 5232 5233 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 5234 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 5235 5236 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 5237 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 5238 vr_hot_gpio = adev->pm.dpm.backbias_response_time; 5239 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 5240 vr_hot_gpio); 5241 } 5242 5243 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table); 5244 if (ret) 5245 return ret; 5246 5247 ret = si_populate_smc_acpi_state(adev, table); 5248 if (ret) 5249 return ret; 5250 5251 table->driverState.flags = table->initialState.flags; 5252 table->driverState.levelCount = table->initialState.levelCount; 5253 table->driverState.levels[0] = table->initialState.level; 5254 5255 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state, 5256 SISLANDS_INITIAL_STATE_ARB_INDEX); 5257 if (ret) 5258 return ret; 5259 5260 if (ulv->supported && ulv->pl.vddc) { 5261 ret = si_populate_ulv_state(adev, &table->ULVState); 5262 if (ret) 5263 return ret; 5264 5265 ret = si_program_ulv_memory_timing_parameters(adev); 5266 if (ret) 5267 return ret; 5268 5269 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 5270 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 5271 5272 lane_width = amdgpu_get_pcie_lanes(adev); 5273 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5274 } else { 5275 table->ULVState = table->initialState; 5276 } 5277 5278 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5279 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5280 si_pi->sram_end); 5281 } 5282 5283 static int si_calculate_sclk_params(struct amdgpu_device *adev, 5284 u32 engine_clock, 5285 SISLANDS_SMC_SCLK_VALUE *sclk) 5286 { 5287 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5288 struct si_power_info *si_pi = si_get_pi(adev); 5289 struct atom_clock_dividers dividers; 5290 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5291 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5292 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5293 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5294 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 5295 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 5296 u64 tmp; 5297 u32 reference_clock = adev->clock.spll.reference_freq; 5298 u32 reference_divider; 5299 u32 fbdiv; 5300 int ret; 5301 5302 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 5303 engine_clock, false, ÷rs); 5304 if (ret) 5305 return ret; 5306 5307 reference_divider = 1 + dividers.ref_div; 5308 5309 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 5310 do_div(tmp, reference_clock); 5311 fbdiv = (u32) tmp; 5312 5313 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 5314 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 5315 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 5316 5317 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 5318 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 5319 5320 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 5321 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 5322 spll_func_cntl_3 |= SPLL_DITHEN; 5323 5324 if (pi->sclk_ss) { 5325 struct amdgpu_atom_ss ss; 5326 u32 vco_freq = engine_clock * dividers.post_div; 5327 5328 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5329 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 5330 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 5331 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 5332 5333 cg_spll_spread_spectrum &= ~CLK_S_MASK; 5334 cg_spll_spread_spectrum |= CLK_S(clk_s); 5335 cg_spll_spread_spectrum |= SSEN; 5336 5337 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 5338 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 5339 } 5340 } 5341 5342 sclk->sclk_value = engine_clock; 5343 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 5344 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 5345 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 5346 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 5347 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 5348 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 5349 5350 return 0; 5351 } 5352 5353 static int si_populate_sclk_value(struct amdgpu_device *adev, 5354 u32 engine_clock, 5355 SISLANDS_SMC_SCLK_VALUE *sclk) 5356 { 5357 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 5358 int ret; 5359 5360 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); 5361 if (!ret) { 5362 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 5363 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 5364 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 5365 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 5366 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 5367 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 5368 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 5369 } 5370 5371 return ret; 5372 } 5373 5374 static int si_populate_mclk_value(struct amdgpu_device *adev, 5375 u32 engine_clock, 5376 u32 memory_clock, 5377 SISLANDS_SMC_MCLK_VALUE *mclk, 5378 bool strobe_mode, 5379 bool dll_state_on) 5380 { 5381 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5382 struct si_power_info *si_pi = si_get_pi(adev); 5383 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5384 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5385 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5386 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5387 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5388 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5389 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5390 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 5391 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 5392 struct atom_mpll_param mpll_param; 5393 int ret; 5394 5395 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); 5396 if (ret) 5397 return ret; 5398 5399 mpll_func_cntl &= ~BWCTRL_MASK; 5400 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 5401 5402 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 5403 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 5404 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 5405 5406 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 5407 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 5408 5409 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5410 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 5411 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 5412 YCLK_POST_DIV(mpll_param.post_div); 5413 } 5414 5415 if (pi->mclk_ss) { 5416 struct amdgpu_atom_ss ss; 5417 u32 freq_nom; 5418 u32 tmp; 5419 u32 reference_clock = adev->clock.mpll.reference_freq; 5420 5421 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5422 freq_nom = memory_clock * 4; 5423 else 5424 freq_nom = memory_clock * 2; 5425 5426 tmp = freq_nom / reference_clock; 5427 tmp = tmp * tmp; 5428 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5429 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 5430 u32 clks = reference_clock * 5 / ss.rate; 5431 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 5432 5433 mpll_ss1 &= ~CLKV_MASK; 5434 mpll_ss1 |= CLKV(clkv); 5435 5436 mpll_ss2 &= ~CLKS_MASK; 5437 mpll_ss2 |= CLKS(clks); 5438 } 5439 } 5440 5441 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 5442 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 5443 5444 if (dll_state_on) 5445 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 5446 else 5447 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5448 5449 mclk->mclk_value = cpu_to_be32(memory_clock); 5450 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 5451 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 5452 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 5453 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 5454 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 5455 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 5456 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 5457 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 5458 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 5459 5460 return 0; 5461 } 5462 5463 static void si_populate_smc_sp(struct amdgpu_device *adev, 5464 struct amdgpu_ps *amdgpu_state, 5465 SISLANDS_SMC_SWSTATE *smc_state) 5466 { 5467 struct si_ps *ps = si_get_ps(amdgpu_state); 5468 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5469 int i; 5470 5471 for (i = 0; i < ps->performance_level_count - 1; i++) 5472 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5473 5474 smc_state->levels[ps->performance_level_count - 1].bSP = 5475 cpu_to_be32(pi->psp); 5476 } 5477 5478 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 5479 struct rv7xx_pl *pl, 5480 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5481 { 5482 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5483 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5484 struct si_power_info *si_pi = si_get_pi(adev); 5485 int ret; 5486 bool dll_state_on; 5487 u16 std_vddc; 5488 5489 if (eg_pi->pcie_performance_request && 5490 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID)) 5491 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5492 else 5493 level->gen2PCIE = (u8)pl->pcie_gen; 5494 5495 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); 5496 if (ret) 5497 return ret; 5498 5499 level->mcFlags = 0; 5500 5501 if (pi->mclk_stutter_mode_threshold && 5502 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5503 !eg_pi->uvd_enabled && 5504 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5505 (adev->pm.dpm.new_active_crtc_count <= 2)) { 5506 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5507 } 5508 5509 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5510 if (pl->mclk > pi->mclk_edc_enable_threshold) 5511 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5512 5513 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5514 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5515 5516 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); 5517 5518 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5519 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5520 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5521 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5522 else 5523 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5524 } else { 5525 dll_state_on = false; 5526 } 5527 } else { 5528 level->strobeMode = si_get_strobe_mode_settings(adev, 5529 pl->mclk); 5530 5531 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5532 } 5533 5534 ret = si_populate_mclk_value(adev, 5535 pl->sclk, 5536 pl->mclk, 5537 &level->mclk, 5538 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5539 if (ret) 5540 return ret; 5541 5542 ret = si_populate_voltage_value(adev, 5543 &eg_pi->vddc_voltage_table, 5544 pl->vddc, &level->vddc); 5545 if (ret) 5546 return ret; 5547 5548 5549 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); 5550 if (ret) 5551 return ret; 5552 5553 ret = si_populate_std_voltage_value(adev, std_vddc, 5554 level->vddc.index, &level->std_vddc); 5555 if (ret) 5556 return ret; 5557 5558 if (eg_pi->vddci_control) { 5559 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5560 pl->vddci, &level->vddci); 5561 if (ret) 5562 return ret; 5563 } 5564 5565 if (si_pi->vddc_phase_shed_control) { 5566 ret = si_populate_phase_shedding_value(adev, 5567 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5568 pl->vddc, 5569 pl->sclk, 5570 pl->mclk, 5571 &level->vddc); 5572 if (ret) 5573 return ret; 5574 } 5575 5576 level->MaxPoweredUpCU = si_pi->max_cu; 5577 5578 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); 5579 5580 return ret; 5581 } 5582 5583 static int si_populate_smc_t(struct amdgpu_device *adev, 5584 struct amdgpu_ps *amdgpu_state, 5585 SISLANDS_SMC_SWSTATE *smc_state) 5586 { 5587 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5588 struct si_ps *state = si_get_ps(amdgpu_state); 5589 u32 a_t; 5590 u32 t_l, t_h; 5591 u32 high_bsp; 5592 int i, ret; 5593 5594 if (state->performance_level_count >= 9) 5595 return -EINVAL; 5596 5597 if (state->performance_level_count < 2) { 5598 a_t = CG_R(0xffff) | CG_L(0); 5599 smc_state->levels[0].aT = cpu_to_be32(a_t); 5600 return 0; 5601 } 5602 5603 smc_state->levels[0].aT = cpu_to_be32(0); 5604 5605 for (i = 0; i <= state->performance_level_count - 2; i++) { 5606 ret = r600_calculate_at( 5607 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5608 100 * R600_AH_DFLT, 5609 state->performance_levels[i + 1].sclk, 5610 state->performance_levels[i].sclk, 5611 &t_l, 5612 &t_h); 5613 5614 if (ret) { 5615 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5616 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5617 } 5618 5619 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5620 a_t |= CG_R(t_l * pi->bsp / 20000); 5621 smc_state->levels[i].aT = cpu_to_be32(a_t); 5622 5623 high_bsp = (i == state->performance_level_count - 2) ? 5624 pi->pbsp : pi->bsp; 5625 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5626 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5627 } 5628 5629 return 0; 5630 } 5631 5632 static int si_disable_ulv(struct amdgpu_device *adev) 5633 { 5634 struct si_power_info *si_pi = si_get_pi(adev); 5635 struct si_ulv_param *ulv = &si_pi->ulv; 5636 5637 if (ulv->supported) 5638 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5639 0 : -EINVAL; 5640 5641 return 0; 5642 } 5643 5644 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, 5645 struct amdgpu_ps *amdgpu_state) 5646 { 5647 const struct si_power_info *si_pi = si_get_pi(adev); 5648 const struct si_ulv_param *ulv = &si_pi->ulv; 5649 const struct si_ps *state = si_get_ps(amdgpu_state); 5650 int i; 5651 5652 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5653 return false; 5654 5655 /* XXX validate against display requirements! */ 5656 5657 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5658 if (adev->clock.current_dispclk <= 5659 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5660 if (ulv->pl.vddc < 5661 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5662 return false; 5663 } 5664 } 5665 5666 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) 5667 return false; 5668 5669 return true; 5670 } 5671 5672 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, 5673 struct amdgpu_ps *amdgpu_new_state) 5674 { 5675 const struct si_power_info *si_pi = si_get_pi(adev); 5676 const struct si_ulv_param *ulv = &si_pi->ulv; 5677 5678 if (ulv->supported) { 5679 if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) 5680 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5681 0 : -EINVAL; 5682 } 5683 return 0; 5684 } 5685 5686 static int si_convert_power_state_to_smc(struct amdgpu_device *adev, 5687 struct amdgpu_ps *amdgpu_state, 5688 SISLANDS_SMC_SWSTATE *smc_state) 5689 { 5690 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5691 struct ni_power_info *ni_pi = ni_get_pi(adev); 5692 struct si_power_info *si_pi = si_get_pi(adev); 5693 struct si_ps *state = si_get_ps(amdgpu_state); 5694 int i, ret; 5695 u32 threshold; 5696 u32 sclk_in_sr = 1350; /* ??? */ 5697 5698 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5699 return -EINVAL; 5700 5701 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5702 5703 if (amdgpu_state->vclk && amdgpu_state->dclk) { 5704 eg_pi->uvd_enabled = true; 5705 if (eg_pi->smu_uvd_hs) 5706 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5707 } else { 5708 eg_pi->uvd_enabled = false; 5709 } 5710 5711 if (state->dc_compatible) 5712 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5713 5714 smc_state->levelCount = 0; 5715 for (i = 0; i < state->performance_level_count; i++) { 5716 if (eg_pi->sclk_deep_sleep) { 5717 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5718 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5719 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5720 else 5721 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5722 } 5723 } 5724 5725 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], 5726 &smc_state->levels[i]); 5727 smc_state->levels[i].arbRefreshState = 5728 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5729 5730 if (ret) 5731 return ret; 5732 5733 if (ni_pi->enable_power_containment) 5734 smc_state->levels[i].displayWatermark = 5735 (state->performance_levels[i].sclk < threshold) ? 5736 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5737 else 5738 smc_state->levels[i].displayWatermark = (i < 2) ? 5739 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5740 5741 if (eg_pi->dynamic_ac_timing) 5742 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5743 else 5744 smc_state->levels[i].ACIndex = 0; 5745 5746 smc_state->levelCount++; 5747 } 5748 5749 si_write_smc_soft_register(adev, 5750 SI_SMC_SOFT_REGISTER_watermark_threshold, 5751 threshold / 512); 5752 5753 si_populate_smc_sp(adev, amdgpu_state, smc_state); 5754 5755 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state); 5756 if (ret) 5757 ni_pi->enable_power_containment = false; 5758 5759 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state); 5760 if (ret) 5761 ni_pi->enable_sq_ramping = false; 5762 5763 return si_populate_smc_t(adev, amdgpu_state, smc_state); 5764 } 5765 5766 static int si_upload_sw_state(struct amdgpu_device *adev, 5767 struct amdgpu_ps *amdgpu_new_state) 5768 { 5769 struct si_power_info *si_pi = si_get_pi(adev); 5770 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 5771 int ret; 5772 u32 address = si_pi->state_table_start + 5773 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5774 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5775 size_t state_size = struct_size(smc_state, levels, 5776 new_state->performance_level_count); 5777 memset(smc_state, 0, state_size); 5778 5779 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); 5780 if (ret) 5781 return ret; 5782 5783 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5784 state_size, si_pi->sram_end); 5785 } 5786 5787 static int si_upload_ulv_state(struct amdgpu_device *adev) 5788 { 5789 struct si_power_info *si_pi = si_get_pi(adev); 5790 struct si_ulv_param *ulv = &si_pi->ulv; 5791 int ret = 0; 5792 5793 if (ulv->supported && ulv->pl.vddc) { 5794 u32 address = si_pi->state_table_start + 5795 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5796 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; 5797 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE); 5798 5799 memset(smc_state, 0, state_size); 5800 5801 ret = si_populate_ulv_state(adev, smc_state); 5802 if (!ret) 5803 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5804 state_size, si_pi->sram_end); 5805 } 5806 5807 return ret; 5808 } 5809 5810 static int si_upload_smc_data(struct amdgpu_device *adev) 5811 { 5812 struct amdgpu_crtc *amdgpu_crtc = NULL; 5813 int i; 5814 5815 if (adev->pm.dpm.new_active_crtc_count == 0) 5816 return 0; 5817 5818 for (i = 0; i < adev->mode_info.num_crtc; i++) { 5819 if (adev->pm.dpm.new_active_crtcs & (1 << i)) { 5820 amdgpu_crtc = adev->mode_info.crtcs[i]; 5821 break; 5822 } 5823 } 5824 5825 if (amdgpu_crtc == NULL) 5826 return 0; 5827 5828 if (amdgpu_crtc->line_time <= 0) 5829 return 0; 5830 5831 if (si_write_smc_soft_register(adev, 5832 SI_SMC_SOFT_REGISTER_crtc_index, 5833 amdgpu_crtc->crtc_id) != PPSMC_Result_OK) 5834 return 0; 5835 5836 if (si_write_smc_soft_register(adev, 5837 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5838 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK) 5839 return 0; 5840 5841 if (si_write_smc_soft_register(adev, 5842 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5843 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK) 5844 return 0; 5845 5846 return 0; 5847 } 5848 5849 static int si_set_mc_special_registers(struct amdgpu_device *adev, 5850 struct si_mc_reg_table *table) 5851 { 5852 u8 i, j, k; 5853 u32 temp_reg; 5854 5855 for (i = 0, j = table->last; i < table->last; i++) { 5856 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5857 return -EINVAL; 5858 switch (table->mc_reg_address[i].s1) { 5859 case MC_SEQ_MISC1: 5860 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5861 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; 5862 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; 5863 for (k = 0; k < table->num_entries; k++) 5864 table->mc_reg_table_entry[k].mc_data[j] = 5865 ((temp_reg & 0xffff0000)) | 5866 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5867 j++; 5868 5869 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5870 return -EINVAL; 5871 temp_reg = RREG32(MC_PMG_CMD_MRS); 5872 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; 5873 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; 5874 for (k = 0; k < table->num_entries; k++) { 5875 table->mc_reg_table_entry[k].mc_data[j] = 5876 (temp_reg & 0xffff0000) | 5877 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5878 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) 5879 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5880 } 5881 j++; 5882 5883 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { 5884 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5885 return -EINVAL; 5886 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; 5887 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; 5888 for (k = 0; k < table->num_entries; k++) 5889 table->mc_reg_table_entry[k].mc_data[j] = 5890 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5891 j++; 5892 } 5893 break; 5894 case MC_SEQ_RESERVE_M: 5895 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5896 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; 5897 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; 5898 for(k = 0; k < table->num_entries; k++) 5899 table->mc_reg_table_entry[k].mc_data[j] = 5900 (temp_reg & 0xffff0000) | 5901 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5902 j++; 5903 break; 5904 default: 5905 break; 5906 } 5907 } 5908 5909 table->last = j; 5910 5911 return 0; 5912 } 5913 5914 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5915 { 5916 bool result = true; 5917 switch (in_reg) { 5918 case MC_SEQ_RAS_TIMING: 5919 *out_reg = MC_SEQ_RAS_TIMING_LP; 5920 break; 5921 case MC_SEQ_CAS_TIMING: 5922 *out_reg = MC_SEQ_CAS_TIMING_LP; 5923 break; 5924 case MC_SEQ_MISC_TIMING: 5925 *out_reg = MC_SEQ_MISC_TIMING_LP; 5926 break; 5927 case MC_SEQ_MISC_TIMING2: 5928 *out_reg = MC_SEQ_MISC_TIMING2_LP; 5929 break; 5930 case MC_SEQ_RD_CTL_D0: 5931 *out_reg = MC_SEQ_RD_CTL_D0_LP; 5932 break; 5933 case MC_SEQ_RD_CTL_D1: 5934 *out_reg = MC_SEQ_RD_CTL_D1_LP; 5935 break; 5936 case MC_SEQ_WR_CTL_D0: 5937 *out_reg = MC_SEQ_WR_CTL_D0_LP; 5938 break; 5939 case MC_SEQ_WR_CTL_D1: 5940 *out_reg = MC_SEQ_WR_CTL_D1_LP; 5941 break; 5942 case MC_PMG_CMD_EMRS: 5943 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP; 5944 break; 5945 case MC_PMG_CMD_MRS: 5946 *out_reg = MC_SEQ_PMG_CMD_MRS_LP; 5947 break; 5948 case MC_PMG_CMD_MRS1: 5949 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP; 5950 break; 5951 case MC_SEQ_PMG_TIMING: 5952 *out_reg = MC_SEQ_PMG_TIMING_LP; 5953 break; 5954 case MC_PMG_CMD_MRS2: 5955 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP; 5956 break; 5957 case MC_SEQ_WR_CTL_2: 5958 *out_reg = MC_SEQ_WR_CTL_2_LP; 5959 break; 5960 default: 5961 result = false; 5962 break; 5963 } 5964 5965 return result; 5966 } 5967 5968 static void si_set_valid_flag(struct si_mc_reg_table *table) 5969 { 5970 u8 i, j; 5971 5972 for (i = 0; i < table->last; i++) { 5973 for (j = 1; j < table->num_entries; j++) { 5974 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5975 table->valid_flag |= 1 << i; 5976 break; 5977 } 5978 } 5979 } 5980 } 5981 5982 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5983 { 5984 u32 i; 5985 u16 address; 5986 5987 for (i = 0; i < table->last; i++) 5988 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5989 address : table->mc_reg_address[i].s1; 5990 5991 } 5992 5993 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5994 struct si_mc_reg_table *si_table) 5995 { 5996 u8 i, j; 5997 5998 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5999 return -EINVAL; 6000 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 6001 return -EINVAL; 6002 6003 for (i = 0; i < table->last; i++) 6004 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 6005 si_table->last = table->last; 6006 6007 for (i = 0; i < table->num_entries; i++) { 6008 si_table->mc_reg_table_entry[i].mclk_max = 6009 table->mc_reg_table_entry[i].mclk_max; 6010 for (j = 0; j < table->last; j++) { 6011 si_table->mc_reg_table_entry[i].mc_data[j] = 6012 table->mc_reg_table_entry[i].mc_data[j]; 6013 } 6014 } 6015 si_table->num_entries = table->num_entries; 6016 6017 return 0; 6018 } 6019 6020 static int si_initialize_mc_reg_table(struct amdgpu_device *adev) 6021 { 6022 struct si_power_info *si_pi = si_get_pi(adev); 6023 struct atom_mc_reg_table *table; 6024 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 6025 u8 module_index = rv770_get_memory_module_index(adev); 6026 int ret; 6027 6028 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 6029 if (!table) 6030 return -ENOMEM; 6031 6032 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 6033 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 6034 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 6035 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 6036 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 6037 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 6038 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 6039 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 6040 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 6041 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 6042 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 6043 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 6044 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 6045 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 6046 6047 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); 6048 if (ret) 6049 goto init_mc_done; 6050 6051 ret = si_copy_vbios_mc_reg_table(table, si_table); 6052 if (ret) 6053 goto init_mc_done; 6054 6055 si_set_s0_mc_reg_index(si_table); 6056 6057 ret = si_set_mc_special_registers(adev, si_table); 6058 if (ret) 6059 goto init_mc_done; 6060 6061 si_set_valid_flag(si_table); 6062 6063 init_mc_done: 6064 kfree(table); 6065 6066 return ret; 6067 6068 } 6069 6070 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev, 6071 SMC_SIslands_MCRegisters *mc_reg_table) 6072 { 6073 struct si_power_info *si_pi = si_get_pi(adev); 6074 u32 i, j; 6075 6076 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 6077 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 6078 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6079 break; 6080 mc_reg_table->address[i].s0 = 6081 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 6082 mc_reg_table->address[i].s1 = 6083 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 6084 i++; 6085 } 6086 } 6087 mc_reg_table->last = (u8)i; 6088 } 6089 6090 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 6091 SMC_SIslands_MCRegisterSet *data, 6092 u32 num_entries, u32 valid_flag) 6093 { 6094 u32 i, j; 6095 6096 for(i = 0, j = 0; j < num_entries; j++) { 6097 if (valid_flag & (1 << j)) { 6098 data->value[i] = cpu_to_be32(entry->mc_data[j]); 6099 i++; 6100 } 6101 } 6102 } 6103 6104 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, 6105 struct rv7xx_pl *pl, 6106 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 6107 { 6108 struct si_power_info *si_pi = si_get_pi(adev); 6109 u32 i = 0; 6110 6111 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 6112 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 6113 break; 6114 } 6115 6116 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 6117 --i; 6118 6119 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 6120 mc_reg_table_data, si_pi->mc_reg_table.last, 6121 si_pi->mc_reg_table.valid_flag); 6122 } 6123 6124 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, 6125 struct amdgpu_ps *amdgpu_state, 6126 SMC_SIslands_MCRegisters *mc_reg_table) 6127 { 6128 struct si_ps *state = si_get_ps(amdgpu_state); 6129 int i; 6130 6131 for (i = 0; i < state->performance_level_count; i++) { 6132 si_convert_mc_reg_table_entry_to_smc(adev, 6133 &state->performance_levels[i], 6134 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 6135 } 6136 } 6137 6138 static int si_populate_mc_reg_table(struct amdgpu_device *adev, 6139 struct amdgpu_ps *amdgpu_boot_state) 6140 { 6141 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state); 6142 struct si_power_info *si_pi = si_get_pi(adev); 6143 struct si_ulv_param *ulv = &si_pi->ulv; 6144 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6145 6146 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6147 6148 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1); 6149 6150 si_populate_mc_reg_addresses(adev, smc_mc_reg_table); 6151 6152 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], 6153 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 6154 6155 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6156 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 6157 si_pi->mc_reg_table.last, 6158 si_pi->mc_reg_table.valid_flag); 6159 6160 if (ulv->supported && ulv->pl.vddc != 0) 6161 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, 6162 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 6163 else 6164 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6165 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 6166 si_pi->mc_reg_table.last, 6167 si_pi->mc_reg_table.valid_flag); 6168 6169 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); 6170 6171 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6172 (u8 *)smc_mc_reg_table, 6173 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6174 } 6175 6176 static int si_upload_mc_reg_table(struct amdgpu_device *adev, 6177 struct amdgpu_ps *amdgpu_new_state) 6178 { 6179 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 6180 struct si_power_info *si_pi = si_get_pi(adev); 6181 u32 address = si_pi->mc_reg_table_start + 6182 offsetof(SMC_SIslands_MCRegisters, 6183 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 6184 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6185 6186 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6187 6188 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); 6189 6190 return amdgpu_si_copy_bytes_to_smc(adev, address, 6191 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6192 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6193 si_pi->sram_end); 6194 } 6195 6196 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) 6197 { 6198 if (enable) 6199 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 6200 else 6201 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 6202 } 6203 6204 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev, 6205 struct amdgpu_ps *amdgpu_state) 6206 { 6207 struct si_ps *state = si_get_ps(amdgpu_state); 6208 int i; 6209 u16 pcie_speed, max_speed = 0; 6210 6211 for (i = 0; i < state->performance_level_count; i++) { 6212 pcie_speed = state->performance_levels[i].pcie_gen; 6213 if (max_speed < pcie_speed) 6214 max_speed = pcie_speed; 6215 } 6216 return max_speed; 6217 } 6218 6219 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev) 6220 { 6221 u32 speed_cntl; 6222 6223 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 6224 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 6225 6226 return (u16)speed_cntl; 6227 } 6228 6229 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, 6230 struct amdgpu_ps *amdgpu_new_state, 6231 struct amdgpu_ps *amdgpu_current_state) 6232 { 6233 struct si_power_info *si_pi = si_get_pi(adev); 6234 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6235 enum si_pcie_gen current_link_speed; 6236 6237 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID) 6238 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state); 6239 else 6240 current_link_speed = si_pi->force_pcie_gen; 6241 6242 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 6243 si_pi->pspp_notify_required = false; 6244 if (target_link_speed > current_link_speed) { 6245 switch (target_link_speed) { 6246 #if defined(CONFIG_ACPI) 6247 case SI_PCIE_GEN3: 6248 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 6249 break; 6250 si_pi->force_pcie_gen = SI_PCIE_GEN2; 6251 if (current_link_speed == SI_PCIE_GEN2) 6252 break; 6253 fallthrough; 6254 case SI_PCIE_GEN2: 6255 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 6256 break; 6257 fallthrough; 6258 #endif 6259 default: 6260 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); 6261 break; 6262 } 6263 } else { 6264 if (target_link_speed < current_link_speed) 6265 si_pi->pspp_notify_required = true; 6266 } 6267 } 6268 6269 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, 6270 struct amdgpu_ps *amdgpu_new_state, 6271 struct amdgpu_ps *amdgpu_current_state) 6272 { 6273 struct si_power_info *si_pi = si_get_pi(adev); 6274 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6275 u8 request; 6276 6277 if (si_pi->pspp_notify_required) { 6278 if (target_link_speed == SI_PCIE_GEN3) 6279 request = PCIE_PERF_REQ_PECI_GEN3; 6280 else if (target_link_speed == SI_PCIE_GEN2) 6281 request = PCIE_PERF_REQ_PECI_GEN2; 6282 else 6283 request = PCIE_PERF_REQ_PECI_GEN1; 6284 6285 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 6286 (si_get_current_pcie_speed(adev) > 0)) 6287 return; 6288 6289 #if defined(CONFIG_ACPI) 6290 amdgpu_acpi_pcie_performance_request(adev, request, false); 6291 #endif 6292 } 6293 } 6294 6295 #if 0 6296 static int si_ds_request(struct amdgpu_device *adev, 6297 bool ds_status_on, u32 count_write) 6298 { 6299 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6300 6301 if (eg_pi->sclk_deep_sleep) { 6302 if (ds_status_on) 6303 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6304 PPSMC_Result_OK) ? 6305 0 : -EINVAL; 6306 else 6307 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6308 PPSMC_Result_OK) ? 0 : -EINVAL; 6309 } 6310 return 0; 6311 } 6312 #endif 6313 6314 static void si_set_max_cu_value(struct amdgpu_device *adev) 6315 { 6316 struct si_power_info *si_pi = si_get_pi(adev); 6317 6318 if (adev->asic_type == CHIP_VERDE) { 6319 switch (adev->pdev->device) { 6320 case 0x6820: 6321 case 0x6825: 6322 case 0x6821: 6323 case 0x6823: 6324 case 0x6827: 6325 si_pi->max_cu = 10; 6326 break; 6327 case 0x682D: 6328 case 0x6824: 6329 case 0x682F: 6330 case 0x6826: 6331 si_pi->max_cu = 8; 6332 break; 6333 case 0x6828: 6334 case 0x6830: 6335 case 0x6831: 6336 case 0x6838: 6337 case 0x6839: 6338 case 0x683D: 6339 si_pi->max_cu = 10; 6340 break; 6341 case 0x683B: 6342 case 0x683F: 6343 case 0x6829: 6344 si_pi->max_cu = 8; 6345 break; 6346 default: 6347 si_pi->max_cu = 0; 6348 break; 6349 } 6350 } else { 6351 si_pi->max_cu = 0; 6352 } 6353 } 6354 6355 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, 6356 struct amdgpu_clock_voltage_dependency_table *table) 6357 { 6358 u32 i; 6359 int j; 6360 u16 leakage_voltage; 6361 6362 if (table) { 6363 for (i = 0; i < table->count; i++) { 6364 switch (si_get_leakage_voltage_from_leakage_index(adev, 6365 table->entries[i].v, 6366 &leakage_voltage)) { 6367 case 0: 6368 table->entries[i].v = leakage_voltage; 6369 break; 6370 case -EAGAIN: 6371 return -EINVAL; 6372 case -EINVAL: 6373 default: 6374 break; 6375 } 6376 } 6377 6378 for (j = (table->count - 2); j >= 0; j--) { 6379 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 6380 table->entries[j].v : table->entries[j + 1].v; 6381 } 6382 } 6383 return 0; 6384 } 6385 6386 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) 6387 { 6388 int ret = 0; 6389 6390 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6391 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 6392 if (ret) 6393 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n"); 6394 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6395 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 6396 if (ret) 6397 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n"); 6398 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6399 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 6400 if (ret) 6401 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n"); 6402 return ret; 6403 } 6404 6405 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, 6406 struct amdgpu_ps *amdgpu_new_state, 6407 struct amdgpu_ps *amdgpu_current_state) 6408 { 6409 u32 lane_width; 6410 u32 new_lane_width = 6411 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6412 u32 current_lane_width = 6413 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6414 6415 if (new_lane_width != current_lane_width) { 6416 amdgpu_set_pcie_lanes(adev, new_lane_width); 6417 lane_width = amdgpu_get_pcie_lanes(adev); 6418 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 6419 } 6420 } 6421 6422 static void si_dpm_setup_asic(struct amdgpu_device *adev) 6423 { 6424 si_read_clock_registers(adev); 6425 si_enable_acpi_power_management(adev); 6426 } 6427 6428 static int si_thermal_enable_alert(struct amdgpu_device *adev, 6429 bool enable) 6430 { 6431 u32 thermal_int = RREG32(CG_THERMAL_INT); 6432 6433 if (enable) { 6434 PPSMC_Result result; 6435 6436 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 6437 WREG32(CG_THERMAL_INT, thermal_int); 6438 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6439 if (result != PPSMC_Result_OK) { 6440 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6441 return -EINVAL; 6442 } 6443 } else { 6444 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 6445 WREG32(CG_THERMAL_INT, thermal_int); 6446 } 6447 6448 return 0; 6449 } 6450 6451 static int si_thermal_set_temperature_range(struct amdgpu_device *adev, 6452 int min_temp, int max_temp) 6453 { 6454 int low_temp = 0 * 1000; 6455 int high_temp = 255 * 1000; 6456 6457 if (low_temp < min_temp) 6458 low_temp = min_temp; 6459 if (high_temp > max_temp) 6460 high_temp = max_temp; 6461 if (high_temp < low_temp) { 6462 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6463 return -EINVAL; 6464 } 6465 6466 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 6467 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6468 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6469 6470 adev->pm.dpm.thermal.min_temp = low_temp; 6471 adev->pm.dpm.thermal.max_temp = high_temp; 6472 6473 return 0; 6474 } 6475 6476 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) 6477 { 6478 struct si_power_info *si_pi = si_get_pi(adev); 6479 u32 tmp; 6480 6481 if (si_pi->fan_ctrl_is_in_default_mode) { 6482 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6483 si_pi->fan_ctrl_default_mode = tmp; 6484 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6485 si_pi->t_min = tmp; 6486 si_pi->fan_ctrl_is_in_default_mode = false; 6487 } 6488 6489 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6490 tmp |= TMIN(0); 6491 WREG32(CG_FDO_CTRL2, tmp); 6492 6493 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6494 tmp |= FDO_PWM_MODE(mode); 6495 WREG32(CG_FDO_CTRL2, tmp); 6496 } 6497 6498 static int si_thermal_setup_fan_table(struct amdgpu_device *adev) 6499 { 6500 struct si_power_info *si_pi = si_get_pi(adev); 6501 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6502 u32 duty100; 6503 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6504 u16 fdo_min, slope1, slope2; 6505 u32 reference_clock, tmp; 6506 int ret; 6507 u64 tmp64; 6508 6509 if (!si_pi->fan_table_start) { 6510 adev->pm.dpm.fan.ucode_fan_control = false; 6511 return 0; 6512 } 6513 6514 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6515 6516 if (duty100 == 0) { 6517 adev->pm.dpm.fan.ucode_fan_control = false; 6518 return 0; 6519 } 6520 6521 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; 6522 do_div(tmp64, 10000); 6523 fdo_min = (u16)tmp64; 6524 6525 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; 6526 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; 6527 6528 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; 6529 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; 6530 6531 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6532 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6533 6534 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); 6535 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); 6536 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); 6537 fan_table.slope1 = cpu_to_be16(slope1); 6538 fan_table.slope2 = cpu_to_be16(slope2); 6539 fan_table.fdo_min = cpu_to_be16(fdo_min); 6540 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); 6541 fan_table.hys_up = cpu_to_be16(1); 6542 fan_table.hys_slope = cpu_to_be16(1); 6543 fan_table.temp_resp_lim = cpu_to_be16(5); 6544 reference_clock = amdgpu_asic_get_xclk(adev); 6545 6546 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * 6547 reference_clock) / 1600); 6548 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6549 6550 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6551 fan_table.temp_src = (uint8_t)tmp; 6552 6553 ret = amdgpu_si_copy_bytes_to_smc(adev, 6554 si_pi->fan_table_start, 6555 (u8 *)(&fan_table), 6556 sizeof(fan_table), 6557 si_pi->sram_end); 6558 6559 if (ret) { 6560 DRM_ERROR("Failed to load fan table to the SMC."); 6561 adev->pm.dpm.fan.ucode_fan_control = false; 6562 } 6563 6564 return ret; 6565 } 6566 6567 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) 6568 { 6569 struct si_power_info *si_pi = si_get_pi(adev); 6570 PPSMC_Result ret; 6571 6572 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6573 if (ret == PPSMC_Result_OK) { 6574 si_pi->fan_is_controlled_by_smc = true; 6575 return 0; 6576 } else { 6577 return -EINVAL; 6578 } 6579 } 6580 6581 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) 6582 { 6583 struct si_power_info *si_pi = si_get_pi(adev); 6584 PPSMC_Result ret; 6585 6586 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6587 6588 if (ret == PPSMC_Result_OK) { 6589 si_pi->fan_is_controlled_by_smc = false; 6590 return 0; 6591 } else { 6592 return -EINVAL; 6593 } 6594 } 6595 6596 static int si_dpm_get_fan_speed_pwm(void *handle, 6597 u32 *speed) 6598 { 6599 u32 duty, duty100; 6600 u64 tmp64; 6601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6602 6603 if (!speed) 6604 return -EINVAL; 6605 6606 if (adev->pm.no_fan) 6607 return -ENOENT; 6608 6609 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6610 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6611 6612 if (duty100 == 0) 6613 return -EINVAL; 6614 6615 tmp64 = (u64)duty * 255; 6616 do_div(tmp64, duty100); 6617 *speed = min_t(u32, tmp64, 255); 6618 6619 return 0; 6620 } 6621 6622 static int si_dpm_set_fan_speed_pwm(void *handle, 6623 u32 speed) 6624 { 6625 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6626 struct si_power_info *si_pi = si_get_pi(adev); 6627 u32 tmp; 6628 u32 duty, duty100; 6629 u64 tmp64; 6630 6631 if (adev->pm.no_fan) 6632 return -ENOENT; 6633 6634 if (si_pi->fan_is_controlled_by_smc) 6635 return -EINVAL; 6636 6637 if (speed > 255) 6638 return -EINVAL; 6639 6640 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6641 6642 if (duty100 == 0) 6643 return -EINVAL; 6644 6645 tmp64 = (u64)speed * duty100; 6646 do_div(tmp64, 255); 6647 duty = (u32)tmp64; 6648 6649 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6650 tmp |= FDO_STATIC_DUTY(duty); 6651 WREG32(CG_FDO_CTRL0, tmp); 6652 6653 return 0; 6654 } 6655 6656 static int si_dpm_set_fan_control_mode(void *handle, u32 mode) 6657 { 6658 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6659 6660 if (mode == U32_MAX) 6661 return -EINVAL; 6662 6663 if (mode) { 6664 /* stop auto-manage */ 6665 if (adev->pm.dpm.fan.ucode_fan_control) 6666 si_fan_ctrl_stop_smc_fan_control(adev); 6667 si_fan_ctrl_set_static_mode(adev, mode); 6668 } else { 6669 /* restart auto-manage */ 6670 if (adev->pm.dpm.fan.ucode_fan_control) 6671 si_thermal_start_smc_fan_control(adev); 6672 else 6673 si_fan_ctrl_set_default_mode(adev); 6674 } 6675 6676 return 0; 6677 } 6678 6679 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode) 6680 { 6681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6682 struct si_power_info *si_pi = si_get_pi(adev); 6683 u32 tmp; 6684 6685 if (!fan_mode) 6686 return -EINVAL; 6687 6688 if (si_pi->fan_is_controlled_by_smc) 6689 return 0; 6690 6691 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6692 *fan_mode = (tmp >> FDO_PWM_MODE_SHIFT); 6693 6694 return 0; 6695 } 6696 6697 #if 0 6698 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, 6699 u32 *speed) 6700 { 6701 u32 tach_period; 6702 u32 xclk = amdgpu_asic_get_xclk(adev); 6703 6704 if (adev->pm.no_fan) 6705 return -ENOENT; 6706 6707 if (adev->pm.fan_pulses_per_revolution == 0) 6708 return -ENOENT; 6709 6710 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6711 if (tach_period == 0) 6712 return -ENOENT; 6713 6714 *speed = 60 * xclk * 10000 / tach_period; 6715 6716 return 0; 6717 } 6718 6719 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, 6720 u32 speed) 6721 { 6722 u32 tach_period, tmp; 6723 u32 xclk = amdgpu_asic_get_xclk(adev); 6724 6725 if (adev->pm.no_fan) 6726 return -ENOENT; 6727 6728 if (adev->pm.fan_pulses_per_revolution == 0) 6729 return -ENOENT; 6730 6731 if ((speed < adev->pm.fan_min_rpm) || 6732 (speed > adev->pm.fan_max_rpm)) 6733 return -EINVAL; 6734 6735 if (adev->pm.dpm.fan.ucode_fan_control) 6736 si_fan_ctrl_stop_smc_fan_control(adev); 6737 6738 tach_period = 60 * xclk * 10000 / (8 * speed); 6739 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6740 tmp |= TARGET_PERIOD(tach_period); 6741 WREG32(CG_TACH_CTRL, tmp); 6742 6743 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); 6744 6745 return 0; 6746 } 6747 #endif 6748 6749 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) 6750 { 6751 struct si_power_info *si_pi = si_get_pi(adev); 6752 u32 tmp; 6753 6754 if (!si_pi->fan_ctrl_is_in_default_mode) { 6755 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6756 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6757 WREG32(CG_FDO_CTRL2, tmp); 6758 6759 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6760 tmp |= TMIN(si_pi->t_min); 6761 WREG32(CG_FDO_CTRL2, tmp); 6762 si_pi->fan_ctrl_is_in_default_mode = true; 6763 } 6764 } 6765 6766 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev) 6767 { 6768 if (adev->pm.dpm.fan.ucode_fan_control) { 6769 si_fan_ctrl_start_smc_fan_control(adev); 6770 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); 6771 } 6772 } 6773 6774 static void si_thermal_initialize(struct amdgpu_device *adev) 6775 { 6776 u32 tmp; 6777 6778 if (adev->pm.fan_pulses_per_revolution) { 6779 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6780 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1); 6781 WREG32(CG_TACH_CTRL, tmp); 6782 } 6783 6784 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6785 tmp |= TACH_PWM_RESP_RATE(0x28); 6786 WREG32(CG_FDO_CTRL2, tmp); 6787 } 6788 6789 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev) 6790 { 6791 int ret; 6792 6793 si_thermal_initialize(adev); 6794 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6795 if (ret) 6796 return ret; 6797 ret = si_thermal_enable_alert(adev, true); 6798 if (ret) 6799 return ret; 6800 if (adev->pm.dpm.fan.ucode_fan_control) { 6801 ret = si_halt_smc(adev); 6802 if (ret) 6803 return ret; 6804 ret = si_thermal_setup_fan_table(adev); 6805 if (ret) 6806 return ret; 6807 ret = si_resume_smc(adev); 6808 if (ret) 6809 return ret; 6810 si_thermal_start_smc_fan_control(adev); 6811 } 6812 6813 return 0; 6814 } 6815 6816 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev) 6817 { 6818 if (!adev->pm.no_fan) { 6819 si_fan_ctrl_set_default_mode(adev); 6820 si_fan_ctrl_stop_smc_fan_control(adev); 6821 } 6822 } 6823 6824 static int si_dpm_enable(struct amdgpu_device *adev) 6825 { 6826 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6827 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6828 struct si_power_info *si_pi = si_get_pi(adev); 6829 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6830 int ret; 6831 6832 if (amdgpu_si_is_smc_running(adev)) 6833 return -EINVAL; 6834 if (pi->voltage_control || si_pi->voltage_control_svi2) 6835 si_enable_voltage_control(adev, true); 6836 if (pi->mvdd_control) 6837 si_get_mvdd_configuration(adev); 6838 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6839 ret = si_construct_voltage_tables(adev); 6840 if (ret) { 6841 DRM_ERROR("si_construct_voltage_tables failed\n"); 6842 return ret; 6843 } 6844 } 6845 if (eg_pi->dynamic_ac_timing) { 6846 ret = si_initialize_mc_reg_table(adev); 6847 if (ret) 6848 eg_pi->dynamic_ac_timing = false; 6849 } 6850 if (pi->dynamic_ss) 6851 si_enable_spread_spectrum(adev, true); 6852 if (pi->thermal_protection) 6853 si_enable_thermal_protection(adev, true); 6854 si_setup_bsp(adev); 6855 si_program_git(adev); 6856 si_program_tp(adev); 6857 si_program_tpp(adev); 6858 si_program_sstp(adev); 6859 si_enable_display_gap(adev); 6860 si_program_vc(adev); 6861 ret = si_upload_firmware(adev); 6862 if (ret) { 6863 DRM_ERROR("si_upload_firmware failed\n"); 6864 return ret; 6865 } 6866 ret = si_process_firmware_header(adev); 6867 if (ret) { 6868 DRM_ERROR("si_process_firmware_header failed\n"); 6869 return ret; 6870 } 6871 ret = si_initial_switch_from_arb_f0_to_f1(adev); 6872 if (ret) { 6873 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6874 return ret; 6875 } 6876 ret = si_init_smc_table(adev); 6877 if (ret) { 6878 DRM_ERROR("si_init_smc_table failed\n"); 6879 return ret; 6880 } 6881 ret = si_init_smc_spll_table(adev); 6882 if (ret) { 6883 DRM_ERROR("si_init_smc_spll_table failed\n"); 6884 return ret; 6885 } 6886 ret = si_init_arb_table_index(adev); 6887 if (ret) { 6888 DRM_ERROR("si_init_arb_table_index failed\n"); 6889 return ret; 6890 } 6891 if (eg_pi->dynamic_ac_timing) { 6892 ret = si_populate_mc_reg_table(adev, boot_ps); 6893 if (ret) { 6894 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6895 return ret; 6896 } 6897 } 6898 ret = si_initialize_smc_cac_tables(adev); 6899 if (ret) { 6900 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6901 return ret; 6902 } 6903 ret = si_initialize_hardware_cac_manager(adev); 6904 if (ret) { 6905 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6906 return ret; 6907 } 6908 ret = si_initialize_smc_dte_tables(adev); 6909 if (ret) { 6910 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6911 return ret; 6912 } 6913 ret = si_populate_smc_tdp_limits(adev, boot_ps); 6914 if (ret) { 6915 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6916 return ret; 6917 } 6918 ret = si_populate_smc_tdp_limits_2(adev, boot_ps); 6919 if (ret) { 6920 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6921 return ret; 6922 } 6923 si_program_response_times(adev); 6924 si_program_ds_registers(adev); 6925 si_dpm_start_smc(adev); 6926 ret = si_notify_smc_display_change(adev, false); 6927 if (ret) { 6928 DRM_ERROR("si_notify_smc_display_change failed\n"); 6929 return ret; 6930 } 6931 si_enable_sclk_control(adev, true); 6932 si_start_dpm(adev); 6933 6934 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6935 si_thermal_start_thermal_controller(adev); 6936 6937 ni_update_current_ps(adev, boot_ps); 6938 6939 return 0; 6940 } 6941 6942 static int si_set_temperature_range(struct amdgpu_device *adev) 6943 { 6944 int ret; 6945 6946 ret = si_thermal_enable_alert(adev, false); 6947 if (ret) 6948 return ret; 6949 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6950 if (ret) 6951 return ret; 6952 ret = si_thermal_enable_alert(adev, true); 6953 if (ret) 6954 return ret; 6955 6956 return ret; 6957 } 6958 6959 static void si_dpm_disable(struct amdgpu_device *adev) 6960 { 6961 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6962 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6963 6964 if (!amdgpu_si_is_smc_running(adev)) 6965 return; 6966 si_thermal_stop_thermal_controller(adev); 6967 si_disable_ulv(adev); 6968 si_clear_vc(adev); 6969 if (pi->thermal_protection) 6970 si_enable_thermal_protection(adev, false); 6971 si_enable_power_containment(adev, boot_ps, false); 6972 si_enable_smc_cac(adev, boot_ps, false); 6973 si_enable_spread_spectrum(adev, false); 6974 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6975 si_stop_dpm(adev); 6976 si_reset_to_default(adev); 6977 si_dpm_stop_smc(adev); 6978 si_force_switch_to_arb_f0(adev); 6979 6980 ni_update_current_ps(adev, boot_ps); 6981 } 6982 6983 static int si_dpm_pre_set_power_state(void *handle) 6984 { 6985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6986 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6987 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 6988 struct amdgpu_ps *new_ps = &requested_ps; 6989 6990 ni_update_requested_ps(adev, new_ps); 6991 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); 6992 6993 return 0; 6994 } 6995 6996 static int si_power_control_set_level(struct amdgpu_device *adev) 6997 { 6998 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; 6999 int ret; 7000 7001 ret = si_restrict_performance_levels_before_switch(adev); 7002 if (ret) 7003 return ret; 7004 ret = si_halt_smc(adev); 7005 if (ret) 7006 return ret; 7007 ret = si_populate_smc_tdp_limits(adev, new_ps); 7008 if (ret) 7009 return ret; 7010 ret = si_populate_smc_tdp_limits_2(adev, new_ps); 7011 if (ret) 7012 return ret; 7013 ret = si_resume_smc(adev); 7014 if (ret) 7015 return ret; 7016 return si_set_sw_state(adev); 7017 } 7018 7019 static void si_set_vce_clock(struct amdgpu_device *adev, 7020 struct amdgpu_ps *new_rps, 7021 struct amdgpu_ps *old_rps) 7022 { 7023 if ((old_rps->evclk != new_rps->evclk) || 7024 (old_rps->ecclk != new_rps->ecclk)) { 7025 /* Turn the clocks on when encoding, off otherwise */ 7026 if (new_rps->evclk || new_rps->ecclk) { 7027 /* Place holder for future VCE1.0 porting to amdgpu 7028 vce_v1_0_enable_mgcg(adev, false, false);*/ 7029 } else { 7030 /* Place holder for future VCE1.0 porting to amdgpu 7031 vce_v1_0_enable_mgcg(adev, true, false); 7032 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/ 7033 } 7034 } 7035 } 7036 7037 static int si_dpm_set_power_state(void *handle) 7038 { 7039 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7040 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7041 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7042 struct amdgpu_ps *old_ps = &eg_pi->current_rps; 7043 int ret; 7044 7045 ret = si_disable_ulv(adev); 7046 if (ret) { 7047 DRM_ERROR("si_disable_ulv failed\n"); 7048 return ret; 7049 } 7050 ret = si_restrict_performance_levels_before_switch(adev); 7051 if (ret) { 7052 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 7053 return ret; 7054 } 7055 if (eg_pi->pcie_performance_request) 7056 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps); 7057 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps); 7058 ret = si_enable_power_containment(adev, new_ps, false); 7059 if (ret) { 7060 DRM_ERROR("si_enable_power_containment failed\n"); 7061 return ret; 7062 } 7063 ret = si_enable_smc_cac(adev, new_ps, false); 7064 if (ret) { 7065 DRM_ERROR("si_enable_smc_cac failed\n"); 7066 return ret; 7067 } 7068 ret = si_halt_smc(adev); 7069 if (ret) { 7070 DRM_ERROR("si_halt_smc failed\n"); 7071 return ret; 7072 } 7073 ret = si_upload_sw_state(adev, new_ps); 7074 if (ret) { 7075 DRM_ERROR("si_upload_sw_state failed\n"); 7076 return ret; 7077 } 7078 ret = si_upload_smc_data(adev); 7079 if (ret) { 7080 DRM_ERROR("si_upload_smc_data failed\n"); 7081 return ret; 7082 } 7083 ret = si_upload_ulv_state(adev); 7084 if (ret) { 7085 DRM_ERROR("si_upload_ulv_state failed\n"); 7086 return ret; 7087 } 7088 if (eg_pi->dynamic_ac_timing) { 7089 ret = si_upload_mc_reg_table(adev, new_ps); 7090 if (ret) { 7091 DRM_ERROR("si_upload_mc_reg_table failed\n"); 7092 return ret; 7093 } 7094 } 7095 ret = si_program_memory_timing_parameters(adev, new_ps); 7096 if (ret) { 7097 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 7098 return ret; 7099 } 7100 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps); 7101 7102 ret = si_resume_smc(adev); 7103 if (ret) { 7104 DRM_ERROR("si_resume_smc failed\n"); 7105 return ret; 7106 } 7107 ret = si_set_sw_state(adev); 7108 if (ret) { 7109 DRM_ERROR("si_set_sw_state failed\n"); 7110 return ret; 7111 } 7112 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps); 7113 si_set_vce_clock(adev, new_ps, old_ps); 7114 if (eg_pi->pcie_performance_request) 7115 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); 7116 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps); 7117 if (ret) { 7118 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 7119 return ret; 7120 } 7121 ret = si_enable_smc_cac(adev, new_ps, true); 7122 if (ret) { 7123 DRM_ERROR("si_enable_smc_cac failed\n"); 7124 return ret; 7125 } 7126 ret = si_enable_power_containment(adev, new_ps, true); 7127 if (ret) { 7128 DRM_ERROR("si_enable_power_containment failed\n"); 7129 return ret; 7130 } 7131 7132 ret = si_power_control_set_level(adev); 7133 if (ret) { 7134 DRM_ERROR("si_power_control_set_level failed\n"); 7135 return ret; 7136 } 7137 7138 return 0; 7139 } 7140 7141 static void si_dpm_post_set_power_state(void *handle) 7142 { 7143 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7144 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7145 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7146 7147 ni_update_current_ps(adev, new_ps); 7148 } 7149 7150 #if 0 7151 void si_dpm_reset_asic(struct amdgpu_device *adev) 7152 { 7153 si_restrict_performance_levels_before_switch(adev); 7154 si_disable_ulv(adev); 7155 si_set_boot_state(adev); 7156 } 7157 #endif 7158 7159 static void si_dpm_display_configuration_changed(void *handle) 7160 { 7161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7162 7163 si_program_display_gap(adev); 7164 } 7165 7166 7167 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, 7168 struct amdgpu_ps *rps, 7169 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 7170 u8 table_rev) 7171 { 7172 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 7173 rps->class = le16_to_cpu(non_clock_info->usClassification); 7174 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 7175 7176 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 7177 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 7178 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 7179 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 7180 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 7181 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 7182 } else { 7183 rps->vclk = 0; 7184 rps->dclk = 0; 7185 } 7186 7187 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 7188 adev->pm.dpm.boot_ps = rps; 7189 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 7190 adev->pm.dpm.uvd_ps = rps; 7191 } 7192 7193 static void si_parse_pplib_clock_info(struct amdgpu_device *adev, 7194 struct amdgpu_ps *rps, int index, 7195 union pplib_clock_info *clock_info) 7196 { 7197 struct rv7xx_power_info *pi = rv770_get_pi(adev); 7198 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7199 struct si_power_info *si_pi = si_get_pi(adev); 7200 struct si_ps *ps = si_get_ps(rps); 7201 u16 leakage_voltage; 7202 struct rv7xx_pl *pl = &ps->performance_levels[index]; 7203 int ret; 7204 7205 ps->performance_level_count = index + 1; 7206 7207 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7208 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 7209 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7210 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 7211 7212 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 7213 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 7214 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 7215 pl->pcie_gen = si_gen_pcie_gen_support(adev, 7216 si_pi->sys_pcie_mask, 7217 si_pi->boot_pcie_gen, 7218 clock_info->si.ucPCIEGen); 7219 7220 /* patch up vddc if necessary */ 7221 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, 7222 &leakage_voltage); 7223 if (ret == 0) 7224 pl->vddc = leakage_voltage; 7225 7226 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 7227 pi->acpi_vddc = pl->vddc; 7228 eg_pi->acpi_vddci = pl->vddci; 7229 si_pi->acpi_pcie_gen = pl->pcie_gen; 7230 } 7231 7232 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 7233 index == 0) { 7234 /* XXX disable for A0 tahiti */ 7235 si_pi->ulv.supported = false; 7236 si_pi->ulv.pl = *pl; 7237 si_pi->ulv.one_pcie_lane_in_ulv = false; 7238 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 7239 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 7240 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 7241 } 7242 7243 if (pi->min_vddc_in_table > pl->vddc) 7244 pi->min_vddc_in_table = pl->vddc; 7245 7246 if (pi->max_vddc_in_table < pl->vddc) 7247 pi->max_vddc_in_table = pl->vddc; 7248 7249 /* patch up boot state */ 7250 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 7251 u16 vddc, vddci, mvdd; 7252 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd); 7253 pl->mclk = adev->clock.default_mclk; 7254 pl->sclk = adev->clock.default_sclk; 7255 pl->vddc = vddc; 7256 pl->vddci = vddci; 7257 si_pi->mvdd_bootup_value = mvdd; 7258 } 7259 7260 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 7261 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 7262 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 7263 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 7264 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 7265 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 7266 } 7267 } 7268 7269 union pplib_power_state { 7270 struct _ATOM_PPLIB_STATE v1; 7271 struct _ATOM_PPLIB_STATE_V2 v2; 7272 }; 7273 7274 static int si_parse_power_table(struct amdgpu_device *adev) 7275 { 7276 struct amdgpu_mode_info *mode_info = &adev->mode_info; 7277 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 7278 union pplib_power_state *power_state; 7279 int i, j, k, non_clock_array_index, clock_array_index; 7280 union pplib_clock_info *clock_info; 7281 struct _StateArray *state_array; 7282 struct _ClockInfoArray *clock_info_array; 7283 struct _NonClockInfoArray *non_clock_info_array; 7284 union power_info *power_info; 7285 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 7286 u16 data_offset; 7287 u8 frev, crev; 7288 u8 *power_state_offset; 7289 struct si_ps *ps; 7290 7291 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 7292 &frev, &crev, &data_offset)) 7293 return -EINVAL; 7294 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 7295 7296 amdgpu_add_thermal_controller(adev); 7297 7298 state_array = (struct _StateArray *) 7299 (mode_info->atom_context->bios + data_offset + 7300 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 7301 clock_info_array = (struct _ClockInfoArray *) 7302 (mode_info->atom_context->bios + data_offset + 7303 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 7304 non_clock_info_array = (struct _NonClockInfoArray *) 7305 (mode_info->atom_context->bios + data_offset + 7306 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 7307 7308 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 7309 sizeof(struct amdgpu_ps), 7310 GFP_KERNEL); 7311 if (!adev->pm.dpm.ps) 7312 return -ENOMEM; 7313 power_state_offset = (u8 *)state_array->states; 7314 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { 7315 u8 *idx; 7316 power_state = (union pplib_power_state *)power_state_offset; 7317 non_clock_array_index = power_state->v2.nonClockInfoIndex; 7318 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 7319 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 7320 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL); 7321 if (ps == NULL) 7322 return -ENOMEM; 7323 adev->pm.dpm.ps[i].ps_priv = ps; 7324 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], 7325 non_clock_info, 7326 non_clock_info_array->ucEntrySize); 7327 k = 0; 7328 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 7329 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 7330 clock_array_index = idx[j]; 7331 if (clock_array_index >= clock_info_array->ucNumEntries) 7332 continue; 7333 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 7334 break; 7335 clock_info = (union pplib_clock_info *) 7336 ((u8 *)&clock_info_array->clockInfo[0] + 7337 (clock_array_index * clock_info_array->ucEntrySize)); 7338 si_parse_pplib_clock_info(adev, 7339 &adev->pm.dpm.ps[i], k, 7340 clock_info); 7341 k++; 7342 } 7343 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 7344 adev->pm.dpm.num_ps++; 7345 } 7346 7347 /* fill in the vce power states */ 7348 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 7349 u32 sclk, mclk; 7350 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 7351 clock_info = (union pplib_clock_info *) 7352 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 7353 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7354 sclk |= clock_info->si.ucEngineClockHigh << 16; 7355 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7356 mclk |= clock_info->si.ucMemoryClockHigh << 16; 7357 adev->pm.dpm.vce_states[i].sclk = sclk; 7358 adev->pm.dpm.vce_states[i].mclk = mclk; 7359 } 7360 7361 return 0; 7362 } 7363 7364 static int si_dpm_init(struct amdgpu_device *adev) 7365 { 7366 struct rv7xx_power_info *pi; 7367 struct evergreen_power_info *eg_pi; 7368 struct ni_power_info *ni_pi; 7369 struct si_power_info *si_pi; 7370 struct atom_clock_dividers dividers; 7371 int ret; 7372 7373 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 7374 if (si_pi == NULL) 7375 return -ENOMEM; 7376 adev->pm.dpm.priv = si_pi; 7377 ni_pi = &si_pi->ni; 7378 eg_pi = &ni_pi->eg; 7379 pi = &eg_pi->rv7xx; 7380 7381 si_pi->sys_pcie_mask = 7382 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK; 7383 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 7384 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); 7385 7386 si_set_max_cu_value(adev); 7387 7388 rv770_get_max_vddc(adev); 7389 si_get_leakage_vddc(adev); 7390 si_patch_dependency_tables_based_on_leakage(adev); 7391 7392 pi->acpi_vddc = 0; 7393 eg_pi->acpi_vddci = 0; 7394 pi->min_vddc_in_table = 0; 7395 pi->max_vddc_in_table = 0; 7396 7397 ret = amdgpu_get_platform_caps(adev); 7398 if (ret) 7399 return ret; 7400 7401 ret = amdgpu_parse_extended_power_table(adev); 7402 if (ret) 7403 return ret; 7404 7405 ret = si_parse_power_table(adev); 7406 if (ret) 7407 return ret; 7408 7409 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 7410 kcalloc(4, 7411 sizeof(struct amdgpu_clock_voltage_dependency_entry), 7412 GFP_KERNEL); 7413 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) 7414 return -ENOMEM; 7415 7416 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 7417 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 7418 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 7419 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 7420 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 7421 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 7422 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 7423 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 7424 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 7425 7426 if (adev->pm.dpm.voltage_response_time == 0) 7427 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 7428 if (adev->pm.dpm.backbias_response_time == 0) 7429 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 7430 7431 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 7432 0, false, ÷rs); 7433 if (ret) 7434 pi->ref_div = dividers.ref_div + 1; 7435 else 7436 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7437 7438 eg_pi->smu_uvd_hs = false; 7439 7440 pi->mclk_strobe_mode_threshold = 40000; 7441 if (si_is_special_1gb_platform(adev)) 7442 pi->mclk_stutter_mode_threshold = 0; 7443 else 7444 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7445 pi->mclk_edc_enable_threshold = 40000; 7446 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7447 7448 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7449 7450 pi->voltage_control = 7451 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7452 VOLTAGE_OBJ_GPIO_LUT); 7453 if (!pi->voltage_control) { 7454 si_pi->voltage_control_svi2 = 7455 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7456 VOLTAGE_OBJ_SVID2); 7457 if (si_pi->voltage_control_svi2) 7458 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7459 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7460 } 7461 7462 pi->mvdd_control = 7463 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7464 VOLTAGE_OBJ_GPIO_LUT); 7465 7466 eg_pi->vddci_control = 7467 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7468 VOLTAGE_OBJ_GPIO_LUT); 7469 if (!eg_pi->vddci_control) 7470 si_pi->vddci_control_svi2 = 7471 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7472 VOLTAGE_OBJ_SVID2); 7473 7474 si_pi->vddc_phase_shed_control = 7475 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7476 VOLTAGE_OBJ_PHASE_LUT); 7477 7478 rv770_get_engine_memory_ss(adev); 7479 7480 pi->asi = RV770_ASI_DFLT; 7481 pi->pasi = CYPRESS_HASI_DFLT; 7482 pi->vrc = SISLANDS_VRC_DFLT; 7483 7484 pi->gfx_clock_gating = true; 7485 7486 eg_pi->sclk_deep_sleep = true; 7487 si_pi->sclk_deep_sleep_above_low = false; 7488 7489 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7490 pi->thermal_protection = true; 7491 else 7492 pi->thermal_protection = false; 7493 7494 eg_pi->dynamic_ac_timing = true; 7495 7496 eg_pi->light_sleep = true; 7497 #if defined(CONFIG_ACPI) 7498 eg_pi->pcie_performance_request = 7499 amdgpu_acpi_is_pcie_performance_request_supported(adev); 7500 #else 7501 eg_pi->pcie_performance_request = false; 7502 #endif 7503 7504 si_pi->sram_end = SMC_RAM_END; 7505 7506 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7507 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7508 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7509 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7510 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7511 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7512 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7513 7514 si_initialize_powertune_defaults(adev); 7515 7516 /* make sure dc limits are valid */ 7517 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7518 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7519 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7520 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7521 7522 si_pi->fan_ctrl_is_in_default_mode = true; 7523 7524 return 0; 7525 } 7526 7527 static void si_dpm_fini(struct amdgpu_device *adev) 7528 { 7529 int i; 7530 7531 if (adev->pm.dpm.ps) 7532 for (i = 0; i < adev->pm.dpm.num_ps; i++) 7533 kfree(adev->pm.dpm.ps[i].ps_priv); 7534 kfree(adev->pm.dpm.ps); 7535 kfree(adev->pm.dpm.priv); 7536 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7537 amdgpu_free_extended_power_table(adev); 7538 } 7539 7540 static void si_dpm_debugfs_print_current_performance_level(void *handle, 7541 struct seq_file *m) 7542 { 7543 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7544 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7545 struct amdgpu_ps *rps = &eg_pi->current_rps; 7546 struct si_ps *ps = si_get_ps(rps); 7547 struct rv7xx_pl *pl; 7548 u32 current_index = 7549 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7550 CURRENT_STATE_INDEX_SHIFT; 7551 7552 if (current_index >= ps->performance_level_count) { 7553 seq_printf(m, "invalid dpm profile %d\n", current_index); 7554 } else { 7555 pl = &ps->performance_levels[current_index]; 7556 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7557 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7558 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7559 } 7560 } 7561 7562 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev, 7563 struct amdgpu_irq_src *source, 7564 unsigned type, 7565 enum amdgpu_interrupt_state state) 7566 { 7567 u32 cg_thermal_int; 7568 7569 switch (type) { 7570 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: 7571 switch (state) { 7572 case AMDGPU_IRQ_STATE_DISABLE: 7573 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); 7574 cg_thermal_int |= THERM_INT_MASK_HIGH; 7575 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7576 break; 7577 case AMDGPU_IRQ_STATE_ENABLE: 7578 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); 7579 cg_thermal_int &= ~THERM_INT_MASK_HIGH; 7580 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7581 break; 7582 default: 7583 break; 7584 } 7585 break; 7586 7587 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: 7588 switch (state) { 7589 case AMDGPU_IRQ_STATE_DISABLE: 7590 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); 7591 cg_thermal_int |= THERM_INT_MASK_LOW; 7592 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7593 break; 7594 case AMDGPU_IRQ_STATE_ENABLE: 7595 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); 7596 cg_thermal_int &= ~THERM_INT_MASK_LOW; 7597 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7598 break; 7599 default: 7600 break; 7601 } 7602 break; 7603 7604 default: 7605 break; 7606 } 7607 return 0; 7608 } 7609 7610 static int si_dpm_process_interrupt(struct amdgpu_device *adev, 7611 struct amdgpu_irq_src *source, 7612 struct amdgpu_iv_entry *entry) 7613 { 7614 bool queue_thermal = false; 7615 7616 if (entry == NULL) 7617 return -EINVAL; 7618 7619 switch (entry->src_id) { 7620 case 230: /* thermal low to high */ 7621 DRM_DEBUG("IH: thermal low to high\n"); 7622 adev->pm.dpm.thermal.high_to_low = false; 7623 queue_thermal = true; 7624 break; 7625 case 231: /* thermal high to low */ 7626 DRM_DEBUG("IH: thermal high to low\n"); 7627 adev->pm.dpm.thermal.high_to_low = true; 7628 queue_thermal = true; 7629 break; 7630 default: 7631 break; 7632 } 7633 7634 if (queue_thermal) 7635 schedule_work(&adev->pm.dpm.thermal.work); 7636 7637 return 0; 7638 } 7639 7640 static int si_dpm_late_init(struct amdgpu_ip_block *ip_block) 7641 { 7642 int ret; 7643 struct amdgpu_device *adev = ip_block->adev; 7644 7645 if (!adev->pm.dpm_enabled) 7646 return 0; 7647 7648 ret = si_set_temperature_range(adev); 7649 if (ret) 7650 return ret; 7651 #if 0 //TODO ? 7652 si_dpm_powergate_uvd(adev, true); 7653 #endif 7654 return 0; 7655 } 7656 7657 /** 7658 * si_dpm_init_microcode - load ucode images from disk 7659 * 7660 * @adev: amdgpu_device pointer 7661 * 7662 * Use the firmware interface to load the ucode images into 7663 * the driver (not loaded into hw). 7664 * Returns 0 on success, error on failure. 7665 */ 7666 static int si_dpm_init_microcode(struct amdgpu_device *adev) 7667 { 7668 const char *chip_name; 7669 int err; 7670 7671 DRM_DEBUG("\n"); 7672 switch (adev->asic_type) { 7673 case CHIP_TAHITI: 7674 chip_name = "tahiti"; 7675 break; 7676 case CHIP_PITCAIRN: 7677 if ((adev->pdev->revision == 0x81) && 7678 ((adev->pdev->device == 0x6810) || 7679 (adev->pdev->device == 0x6811))) 7680 chip_name = "pitcairn_k"; 7681 else 7682 chip_name = "pitcairn"; 7683 break; 7684 case CHIP_VERDE: 7685 if (((adev->pdev->device == 0x6820) && 7686 ((adev->pdev->revision == 0x81) || 7687 (adev->pdev->revision == 0x83))) || 7688 ((adev->pdev->device == 0x6821) && 7689 ((adev->pdev->revision == 0x83) || 7690 (adev->pdev->revision == 0x87))) || 7691 ((adev->pdev->revision == 0x87) && 7692 ((adev->pdev->device == 0x6823) || 7693 (adev->pdev->device == 0x682b)))) 7694 chip_name = "verde_k"; 7695 else 7696 chip_name = "verde"; 7697 break; 7698 case CHIP_OLAND: 7699 if (((adev->pdev->revision == 0x81) && 7700 ((adev->pdev->device == 0x6600) || 7701 (adev->pdev->device == 0x6604) || 7702 (adev->pdev->device == 0x6605) || 7703 (adev->pdev->device == 0x6610))) || 7704 ((adev->pdev->revision == 0x83) && 7705 (adev->pdev->device == 0x6610))) 7706 chip_name = "oland_k"; 7707 else 7708 chip_name = "oland"; 7709 break; 7710 case CHIP_HAINAN: 7711 if (((adev->pdev->revision == 0x81) && 7712 (adev->pdev->device == 0x6660)) || 7713 ((adev->pdev->revision == 0x83) && 7714 ((adev->pdev->device == 0x6660) || 7715 (adev->pdev->device == 0x6663) || 7716 (adev->pdev->device == 0x6665) || 7717 (adev->pdev->device == 0x6667)))) 7718 chip_name = "hainan_k"; 7719 else if ((adev->pdev->revision == 0xc3) && 7720 (adev->pdev->device == 0x6665)) 7721 chip_name = "banks_k_2"; 7722 else 7723 chip_name = "hainan"; 7724 break; 7725 default: BUG(); 7726 } 7727 7728 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 7729 "amdgpu/%s_smc.bin", chip_name); 7730 if (err) { 7731 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n", 7732 err, chip_name); 7733 amdgpu_ucode_release(&adev->pm.fw); 7734 } 7735 return err; 7736 } 7737 7738 static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block) 7739 { 7740 int ret; 7741 struct amdgpu_device *adev = ip_block->adev; 7742 7743 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); 7744 if (ret) 7745 return ret; 7746 7747 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); 7748 if (ret) 7749 return ret; 7750 7751 /* default to balanced state */ 7752 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 7753 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 7754 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; 7755 adev->pm.default_sclk = adev->clock.default_sclk; 7756 adev->pm.default_mclk = adev->clock.default_mclk; 7757 adev->pm.current_sclk = adev->clock.default_sclk; 7758 adev->pm.current_mclk = adev->clock.default_mclk; 7759 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 7760 7761 if (amdgpu_dpm == 0) 7762 return 0; 7763 7764 ret = si_dpm_init_microcode(adev); 7765 if (ret) 7766 return ret; 7767 7768 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 7769 ret = si_dpm_init(adev); 7770 if (ret) 7771 goto dpm_failed; 7772 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7773 if (amdgpu_dpm == 1) 7774 amdgpu_pm_print_power_states(adev); 7775 DRM_INFO("amdgpu: dpm initialized\n"); 7776 7777 return 0; 7778 7779 dpm_failed: 7780 si_dpm_fini(adev); 7781 DRM_ERROR("amdgpu: dpm initialization failed\n"); 7782 return ret; 7783 } 7784 7785 static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block) 7786 { 7787 struct amdgpu_device *adev = ip_block->adev; 7788 7789 flush_work(&adev->pm.dpm.thermal.work); 7790 7791 si_dpm_fini(adev); 7792 7793 return 0; 7794 } 7795 7796 static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block) 7797 { 7798 int ret; 7799 7800 struct amdgpu_device *adev = ip_block->adev; 7801 7802 if (!amdgpu_dpm) 7803 return 0; 7804 7805 mutex_lock(&adev->pm.mutex); 7806 si_dpm_setup_asic(adev); 7807 ret = si_dpm_enable(adev); 7808 if (ret) 7809 adev->pm.dpm_enabled = false; 7810 else 7811 adev->pm.dpm_enabled = true; 7812 amdgpu_legacy_dpm_compute_clocks(adev); 7813 mutex_unlock(&adev->pm.mutex); 7814 return ret; 7815 } 7816 7817 static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block) 7818 { 7819 struct amdgpu_device *adev = ip_block->adev; 7820 7821 if (adev->pm.dpm_enabled) 7822 si_dpm_disable(adev); 7823 7824 return 0; 7825 } 7826 7827 static int si_dpm_suspend(struct amdgpu_ip_block *ip_block) 7828 { 7829 struct amdgpu_device *adev = ip_block->adev; 7830 7831 cancel_work_sync(&adev->pm.dpm.thermal.work); 7832 7833 if (adev->pm.dpm_enabled) { 7834 mutex_lock(&adev->pm.mutex); 7835 adev->pm.dpm_enabled = false; 7836 /* disable dpm */ 7837 si_dpm_disable(adev); 7838 /* reset the power state */ 7839 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7840 mutex_unlock(&adev->pm.mutex); 7841 } 7842 7843 return 0; 7844 } 7845 7846 static int si_dpm_resume(struct amdgpu_ip_block *ip_block) 7847 { 7848 int ret = 0; 7849 struct amdgpu_device *adev = ip_block->adev; 7850 7851 if (!amdgpu_dpm) 7852 return 0; 7853 7854 if (!adev->pm.dpm_enabled) { 7855 /* asic init will reset to the boot state */ 7856 mutex_lock(&adev->pm.mutex); 7857 si_dpm_setup_asic(adev); 7858 ret = si_dpm_enable(adev); 7859 if (ret) { 7860 adev->pm.dpm_enabled = false; 7861 } else { 7862 adev->pm.dpm_enabled = true; 7863 amdgpu_legacy_dpm_compute_clocks(adev); 7864 } 7865 mutex_unlock(&adev->pm.mutex); 7866 } 7867 7868 return ret; 7869 } 7870 7871 static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block) 7872 { 7873 /* XXX */ 7874 return true; 7875 } 7876 7877 static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) 7878 { 7879 /* XXX */ 7880 return 0; 7881 } 7882 7883 static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 7884 enum amd_clockgating_state state) 7885 { 7886 return 0; 7887 } 7888 7889 static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block, 7890 enum amd_powergating_state state) 7891 { 7892 return 0; 7893 } 7894 7895 /* get temperature in millidegrees */ 7896 static int si_dpm_get_temp(void *handle) 7897 { 7898 u32 temp; 7899 int actual_temp = 0; 7900 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7901 7902 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> 7903 CTF_TEMP_SHIFT; 7904 7905 if (temp & 0x200) 7906 actual_temp = 255; 7907 else 7908 actual_temp = temp & 0x1ff; 7909 7910 actual_temp = (actual_temp * 1000); 7911 7912 return actual_temp; 7913 } 7914 7915 static u32 si_dpm_get_sclk(void *handle, bool low) 7916 { 7917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7918 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7919 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7920 7921 if (low) 7922 return requested_state->performance_levels[0].sclk; 7923 else 7924 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 7925 } 7926 7927 static u32 si_dpm_get_mclk(void *handle, bool low) 7928 { 7929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7930 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7931 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7932 7933 if (low) 7934 return requested_state->performance_levels[0].mclk; 7935 else 7936 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 7937 } 7938 7939 static void si_dpm_print_power_state(void *handle, 7940 void *current_ps) 7941 { 7942 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7943 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; 7944 struct si_ps *ps = si_get_ps(rps); 7945 struct rv7xx_pl *pl; 7946 int i; 7947 7948 amdgpu_dpm_print_class_info(rps->class, rps->class2); 7949 amdgpu_dpm_print_cap_info(rps->caps); 7950 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7951 for (i = 0; i < ps->performance_level_count; i++) { 7952 pl = &ps->performance_levels[i]; 7953 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7954 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7955 } 7956 amdgpu_dpm_print_ps_status(adev, rps); 7957 } 7958 7959 static int si_dpm_early_init(struct amdgpu_ip_block *ip_block) 7960 { 7961 7962 struct amdgpu_device *adev = ip_block->adev; 7963 7964 adev->powerplay.pp_funcs = &si_dpm_funcs; 7965 adev->powerplay.pp_handle = adev; 7966 si_dpm_set_irq_funcs(adev); 7967 return 0; 7968 } 7969 7970 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, 7971 const struct rv7xx_pl *si_cpl2) 7972 { 7973 return ((si_cpl1->mclk == si_cpl2->mclk) && 7974 (si_cpl1->sclk == si_cpl2->sclk) && 7975 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && 7976 (si_cpl1->vddc == si_cpl2->vddc) && 7977 (si_cpl1->vddci == si_cpl2->vddci)); 7978 } 7979 7980 static int si_check_state_equal(void *handle, 7981 void *current_ps, 7982 void *request_ps, 7983 bool *equal) 7984 { 7985 struct si_ps *si_cps; 7986 struct si_ps *si_rps; 7987 int i; 7988 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 7989 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 7990 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7991 7992 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 7993 return -EINVAL; 7994 7995 si_cps = si_get_ps((struct amdgpu_ps *)cps); 7996 si_rps = si_get_ps((struct amdgpu_ps *)rps); 7997 7998 if (si_cps == NULL) { 7999 printk("si_cps is NULL\n"); 8000 *equal = false; 8001 return 0; 8002 } 8003 8004 if (si_cps->performance_level_count != si_rps->performance_level_count) { 8005 *equal = false; 8006 return 0; 8007 } 8008 8009 for (i = 0; i < si_cps->performance_level_count; i++) { 8010 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), 8011 &(si_rps->performance_levels[i]))) { 8012 *equal = false; 8013 return 0; 8014 } 8015 } 8016 8017 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 8018 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); 8019 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); 8020 8021 return 0; 8022 } 8023 8024 static int si_dpm_read_sensor(void *handle, int idx, 8025 void *value, int *size) 8026 { 8027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8028 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 8029 struct amdgpu_ps *rps = &eg_pi->current_rps; 8030 struct si_ps *ps = si_get_ps(rps); 8031 uint32_t sclk, mclk; 8032 u32 pl_index = 8033 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 8034 CURRENT_STATE_INDEX_SHIFT; 8035 8036 /* size must be at least 4 bytes for all sensors */ 8037 if (*size < 4) 8038 return -EINVAL; 8039 8040 switch (idx) { 8041 case AMDGPU_PP_SENSOR_GFX_SCLK: 8042 if (pl_index < ps->performance_level_count) { 8043 sclk = ps->performance_levels[pl_index].sclk; 8044 *((uint32_t *)value) = sclk; 8045 *size = 4; 8046 return 0; 8047 } 8048 return -EINVAL; 8049 case AMDGPU_PP_SENSOR_GFX_MCLK: 8050 if (pl_index < ps->performance_level_count) { 8051 mclk = ps->performance_levels[pl_index].mclk; 8052 *((uint32_t *)value) = mclk; 8053 *size = 4; 8054 return 0; 8055 } 8056 return -EINVAL; 8057 case AMDGPU_PP_SENSOR_GPU_TEMP: 8058 *((uint32_t *)value) = si_dpm_get_temp(adev); 8059 *size = 4; 8060 return 0; 8061 default: 8062 return -EOPNOTSUPP; 8063 } 8064 } 8065 8066 static const struct amd_ip_funcs si_dpm_ip_funcs = { 8067 .name = "si_dpm", 8068 .early_init = si_dpm_early_init, 8069 .late_init = si_dpm_late_init, 8070 .sw_init = si_dpm_sw_init, 8071 .sw_fini = si_dpm_sw_fini, 8072 .hw_init = si_dpm_hw_init, 8073 .hw_fini = si_dpm_hw_fini, 8074 .suspend = si_dpm_suspend, 8075 .resume = si_dpm_resume, 8076 .is_idle = si_dpm_is_idle, 8077 .wait_for_idle = si_dpm_wait_for_idle, 8078 .set_clockgating_state = si_dpm_set_clockgating_state, 8079 .set_powergating_state = si_dpm_set_powergating_state, 8080 }; 8081 8082 const struct amdgpu_ip_block_version si_smu_ip_block = 8083 { 8084 .type = AMD_IP_BLOCK_TYPE_SMC, 8085 .major = 6, 8086 .minor = 0, 8087 .rev = 0, 8088 .funcs = &si_dpm_ip_funcs, 8089 }; 8090 8091 static const struct amd_pm_funcs si_dpm_funcs = { 8092 .pre_set_power_state = &si_dpm_pre_set_power_state, 8093 .set_power_state = &si_dpm_set_power_state, 8094 .post_set_power_state = &si_dpm_post_set_power_state, 8095 .display_configuration_changed = &si_dpm_display_configuration_changed, 8096 .get_sclk = &si_dpm_get_sclk, 8097 .get_mclk = &si_dpm_get_mclk, 8098 .print_power_state = &si_dpm_print_power_state, 8099 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 8100 .force_performance_level = &si_dpm_force_performance_level, 8101 .vblank_too_short = &si_dpm_vblank_too_short, 8102 .set_fan_control_mode = &si_dpm_set_fan_control_mode, 8103 .get_fan_control_mode = &si_dpm_get_fan_control_mode, 8104 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm, 8105 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm, 8106 .check_state_equal = &si_check_state_equal, 8107 .get_vce_clock_state = amdgpu_get_vce_clock_state, 8108 .read_sensor = &si_dpm_read_sensor, 8109 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks, 8110 }; 8111 8112 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = { 8113 .set = si_dpm_set_interrupt_state, 8114 .process = si_dpm_process_interrupt, 8115 }; 8116 8117 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) 8118 { 8119 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 8120 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; 8121 } 8122 8123