1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "amdgpu_atombios.h" 31 #include "amdgpu_dpm_internal.h" 32 #include "amd_pcie.h" 33 #include "atom.h" 34 #include "gfx_v6_0.h" 35 #include "r600_dpm.h" 36 #include "sid.h" 37 #include "si_dpm.h" 38 #include "../include/pptable.h" 39 #include <linux/math64.h> 40 #include <linux/seq_file.h> 41 #include <linux/firmware.h> 42 #include <legacy_dpm.h> 43 44 #include "bif/bif_3_0_d.h" 45 #include "bif/bif_3_0_sh_mask.h" 46 47 #include "dce/dce_6_0_d.h" 48 #include "dce/dce_6_0_sh_mask.h" 49 50 #include "gca/gfx_6_0_d.h" 51 #include "gca/gfx_6_0_sh_mask.h" 52 53 #include"gmc/gmc_6_0_d.h" 54 #include"gmc/gmc_6_0_sh_mask.h" 55 56 #include "smu/smu_6_0_d.h" 57 #include "smu/smu_6_0_sh_mask.h" 58 59 #define MC_CG_ARB_FREQ_F0 0x0a 60 #define MC_CG_ARB_FREQ_F1 0x0b 61 #define MC_CG_ARB_FREQ_F2 0x0c 62 #define MC_CG_ARB_FREQ_F3 0x0d 63 64 #define SMC_RAM_END 0x20000 65 66 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 67 68 69 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ 70 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 71 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 72 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 73 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 74 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 75 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 76 77 #define BIOS_SCRATCH_4 0x5cd 78 79 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin"); 80 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin"); 81 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin"); 82 MODULE_FIRMWARE("amdgpu/verde_smc.bin"); 83 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin"); 84 MODULE_FIRMWARE("amdgpu/oland_smc.bin"); 85 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin"); 86 MODULE_FIRMWARE("amdgpu/hainan_smc.bin"); 87 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin"); 88 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin"); 89 90 static const struct amd_pm_funcs si_dpm_funcs; 91 92 union power_info { 93 struct _ATOM_POWERPLAY_INFO info; 94 struct _ATOM_POWERPLAY_INFO_V2 info_2; 95 struct _ATOM_POWERPLAY_INFO_V3 info_3; 96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; 100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; 101 }; 102 103 union fan_info { 104 struct _ATOM_PPLIB_FANTABLE fan; 105 struct _ATOM_PPLIB_FANTABLE2 fan2; 106 struct _ATOM_PPLIB_FANTABLE3 fan3; 107 }; 108 109 union pplib_clock_info { 110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 114 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 115 }; 116 117 enum si_dpm_auto_throttle_src { 118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL, 119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL 120 }; 121 122 enum si_dpm_event_src { 123 SI_DPM_EVENT_SRC_ANALOG = 0, 124 SI_DPM_EVENT_SRC_EXTERNAL = 1, 125 SI_DPM_EVENT_SRC_DIGITAL = 2, 126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 128 }; 129 130 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] = 131 { 132 R600_UTC_DFLT_00, 133 R600_UTC_DFLT_01, 134 R600_UTC_DFLT_02, 135 R600_UTC_DFLT_03, 136 R600_UTC_DFLT_04, 137 R600_UTC_DFLT_05, 138 R600_UTC_DFLT_06, 139 R600_UTC_DFLT_07, 140 R600_UTC_DFLT_08, 141 R600_UTC_DFLT_09, 142 R600_UTC_DFLT_10, 143 R600_UTC_DFLT_11, 144 R600_UTC_DFLT_12, 145 R600_UTC_DFLT_13, 146 R600_UTC_DFLT_14, 147 }; 148 149 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = 150 { 151 R600_DTC_DFLT_00, 152 R600_DTC_DFLT_01, 153 R600_DTC_DFLT_02, 154 R600_DTC_DFLT_03, 155 R600_DTC_DFLT_04, 156 R600_DTC_DFLT_05, 157 R600_DTC_DFLT_06, 158 R600_DTC_DFLT_07, 159 R600_DTC_DFLT_08, 160 R600_DTC_DFLT_09, 161 R600_DTC_DFLT_10, 162 R600_DTC_DFLT_11, 163 R600_DTC_DFLT_12, 164 R600_DTC_DFLT_13, 165 R600_DTC_DFLT_14, 166 }; 167 168 static const struct si_cac_config_reg cac_weights_tahiti[] = 169 { 170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 230 { 0xFFFFFFFF } 231 }; 232 233 static const struct si_cac_config_reg lcac_tahiti[] = 234 { 235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 321 { 0xFFFFFFFF } 322 323 }; 324 325 static const struct si_cac_config_reg cac_override_tahiti[] = 326 { 327 { 0xFFFFFFFF } 328 }; 329 330 static const struct si_powertune_data powertune_data_tahiti = 331 { 332 ((1 << 16) | 27027), 333 6, 334 0, 335 4, 336 95, 337 { 338 0UL, 339 0UL, 340 4521550UL, 341 309631529UL, 342 -1270850L, 343 4513710L, 344 40 345 }, 346 595000000UL, 347 12, 348 { 349 0, 350 0, 351 0, 352 0, 353 0, 354 0, 355 0, 356 0 357 }, 358 true 359 }; 360 361 static const struct si_dte_data dte_data_tahiti = 362 { 363 { 1159409, 0, 0, 0, 0 }, 364 { 777, 0, 0, 0, 0 }, 365 2, 366 54000, 367 127000, 368 25, 369 2, 370 10, 371 13, 372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 375 85, 376 false 377 }; 378 379 static const struct si_dte_data dte_data_tahiti_pro = 380 { 381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 382 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 383 5, 384 45000, 385 100, 386 0xA, 387 1, 388 0, 389 0x10, 390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 393 90, 394 true 395 }; 396 397 static const struct si_dte_data dte_data_new_zealand = 398 { 399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 401 0x5, 402 0xAFC8, 403 0x69, 404 0x32, 405 1, 406 0, 407 0x10, 408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 411 85, 412 true 413 }; 414 415 static const struct si_dte_data dte_data_aruba_pro = 416 { 417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 418 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 419 5, 420 45000, 421 100, 422 0xA, 423 1, 424 0, 425 0x10, 426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 429 90, 430 true 431 }; 432 433 static const struct si_dte_data dte_data_malta = 434 { 435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 436 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 437 5, 438 45000, 439 100, 440 0xA, 441 1, 442 0, 443 0x10, 444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 447 90, 448 true 449 }; 450 451 static const struct si_cac_config_reg cac_weights_pitcairn[] = 452 { 453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 513 { 0xFFFFFFFF } 514 }; 515 516 static const struct si_cac_config_reg lcac_pitcairn[] = 517 { 518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 604 { 0xFFFFFFFF } 605 }; 606 607 static const struct si_cac_config_reg cac_override_pitcairn[] = 608 { 609 { 0xFFFFFFFF } 610 }; 611 612 static const struct si_powertune_data powertune_data_pitcairn = 613 { 614 ((1 << 16) | 27027), 615 5, 616 0, 617 6, 618 100, 619 { 620 51600000UL, 621 1800000UL, 622 7194395UL, 623 309631529UL, 624 -1270850L, 625 4513710L, 626 100 627 }, 628 117830498UL, 629 12, 630 { 631 0, 632 0, 633 0, 634 0, 635 0, 636 0, 637 0, 638 0 639 }, 640 true 641 }; 642 643 static const struct si_dte_data dte_data_pitcairn = 644 { 645 { 0, 0, 0, 0, 0 }, 646 { 0, 0, 0, 0, 0 }, 647 0, 648 0, 649 0, 650 0, 651 0, 652 0, 653 0, 654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 657 0, 658 false 659 }; 660 661 static const struct si_dte_data dte_data_curacao_xt = 662 { 663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 664 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 665 5, 666 45000, 667 100, 668 0xA, 669 1, 670 0, 671 0x10, 672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 675 90, 676 true 677 }; 678 679 static const struct si_dte_data dte_data_curacao_pro = 680 { 681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 682 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 683 5, 684 45000, 685 100, 686 0xA, 687 1, 688 0, 689 0x10, 690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 693 90, 694 true 695 }; 696 697 static const struct si_dte_data dte_data_neptune_xt = 698 { 699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 700 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 701 5, 702 45000, 703 100, 704 0xA, 705 1, 706 0, 707 0x10, 708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 711 90, 712 true 713 }; 714 715 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 716 { 717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 777 { 0xFFFFFFFF } 778 }; 779 780 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 781 { 782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 842 { 0xFFFFFFFF } 843 }; 844 845 static const struct si_cac_config_reg cac_weights_heathrow[] = 846 { 847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 907 { 0xFFFFFFFF } 908 }; 909 910 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 911 { 912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 972 { 0xFFFFFFFF } 973 }; 974 975 static const struct si_cac_config_reg cac_weights_cape_verde[] = 976 { 977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1037 { 0xFFFFFFFF } 1038 }; 1039 1040 static const struct si_cac_config_reg lcac_cape_verde[] = 1041 { 1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1096 { 0xFFFFFFFF } 1097 }; 1098 1099 static const struct si_cac_config_reg cac_override_cape_verde[] = 1100 { 1101 { 0xFFFFFFFF } 1102 }; 1103 1104 static const struct si_powertune_data powertune_data_cape_verde = 1105 { 1106 ((1 << 16) | 0x6993), 1107 5, 1108 0, 1109 7, 1110 105, 1111 { 1112 0UL, 1113 0UL, 1114 7194395UL, 1115 309631529UL, 1116 -1270850L, 1117 4513710L, 1118 100 1119 }, 1120 117830498UL, 1121 12, 1122 { 1123 0, 1124 0, 1125 0, 1126 0, 1127 0, 1128 0, 1129 0, 1130 0 1131 }, 1132 true 1133 }; 1134 1135 static const struct si_dte_data dte_data_cape_verde = 1136 { 1137 { 0, 0, 0, 0, 0 }, 1138 { 0, 0, 0, 0, 0 }, 1139 0, 1140 0, 1141 0, 1142 0, 1143 0, 1144 0, 1145 0, 1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1149 0, 1150 false 1151 }; 1152 1153 static const struct si_dte_data dte_data_venus_xtx = 1154 { 1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1157 5, 1158 55000, 1159 0x69, 1160 0xA, 1161 1, 1162 0, 1163 0x3, 1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1167 90, 1168 true 1169 }; 1170 1171 static const struct si_dte_data dte_data_venus_xt = 1172 { 1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1175 5, 1176 55000, 1177 0x69, 1178 0xA, 1179 1, 1180 0, 1181 0x3, 1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1185 90, 1186 true 1187 }; 1188 1189 static const struct si_dte_data dte_data_venus_pro = 1190 { 1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1193 5, 1194 55000, 1195 0x69, 1196 0xA, 1197 1, 1198 0, 1199 0x3, 1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1203 90, 1204 true 1205 }; 1206 1207 static const struct si_cac_config_reg cac_weights_oland[] = 1208 { 1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1269 { 0xFFFFFFFF } 1270 }; 1271 1272 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1273 { 1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1334 { 0xFFFFFFFF } 1335 }; 1336 1337 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1338 { 1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1399 { 0xFFFFFFFF } 1400 }; 1401 1402 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1403 { 1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1464 { 0xFFFFFFFF } 1465 }; 1466 1467 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1468 { 1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1529 { 0xFFFFFFFF } 1530 }; 1531 1532 static const struct si_cac_config_reg lcac_oland[] = 1533 { 1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1576 { 0xFFFFFFFF } 1577 }; 1578 1579 static const struct si_cac_config_reg lcac_mars_pro[] = 1580 { 1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1623 { 0xFFFFFFFF } 1624 }; 1625 1626 static const struct si_cac_config_reg cac_override_oland[] = 1627 { 1628 { 0xFFFFFFFF } 1629 }; 1630 1631 static const struct si_powertune_data powertune_data_oland = 1632 { 1633 ((1 << 16) | 0x6993), 1634 5, 1635 0, 1636 7, 1637 105, 1638 { 1639 0UL, 1640 0UL, 1641 7194395UL, 1642 309631529UL, 1643 -1270850L, 1644 4513710L, 1645 100 1646 }, 1647 117830498UL, 1648 12, 1649 { 1650 0, 1651 0, 1652 0, 1653 0, 1654 0, 1655 0, 1656 0, 1657 0 1658 }, 1659 true 1660 }; 1661 1662 static const struct si_powertune_data powertune_data_mars_pro = 1663 { 1664 ((1 << 16) | 0x6993), 1665 5, 1666 0, 1667 7, 1668 105, 1669 { 1670 0UL, 1671 0UL, 1672 7194395UL, 1673 309631529UL, 1674 -1270850L, 1675 4513710L, 1676 100 1677 }, 1678 117830498UL, 1679 12, 1680 { 1681 0, 1682 0, 1683 0, 1684 0, 1685 0, 1686 0, 1687 0, 1688 0 1689 }, 1690 true 1691 }; 1692 1693 static const struct si_dte_data dte_data_oland = 1694 { 1695 { 0, 0, 0, 0, 0 }, 1696 { 0, 0, 0, 0, 0 }, 1697 0, 1698 0, 1699 0, 1700 0, 1701 0, 1702 0, 1703 0, 1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1707 0, 1708 false 1709 }; 1710 1711 static const struct si_dte_data dte_data_mars_pro = 1712 { 1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1714 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1715 5, 1716 55000, 1717 105, 1718 0xA, 1719 1, 1720 0, 1721 0x10, 1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1725 90, 1726 true 1727 }; 1728 1729 static const struct si_dte_data dte_data_sun_xt = 1730 { 1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1732 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1733 5, 1734 55000, 1735 105, 1736 0xA, 1737 1, 1738 0, 1739 0x10, 1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1743 90, 1744 true 1745 }; 1746 1747 1748 static const struct si_cac_config_reg cac_weights_hainan[] = 1749 { 1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1810 { 0xFFFFFFFF } 1811 }; 1812 1813 static const struct si_powertune_data powertune_data_hainan = 1814 { 1815 ((1 << 16) | 0x6993), 1816 5, 1817 0, 1818 9, 1819 105, 1820 { 1821 0UL, 1822 0UL, 1823 7194395UL, 1824 309631529UL, 1825 -1270850L, 1826 4513710L, 1827 100 1828 }, 1829 117830498UL, 1830 12, 1831 { 1832 0, 1833 0, 1834 0, 1835 0, 1836 0, 1837 0, 1838 0, 1839 0 1840 }, 1841 true 1842 }; 1843 1844 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev); 1845 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev); 1846 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev); 1847 static struct si_ps *si_get_ps(struct amdgpu_ps *rps); 1848 1849 static int si_populate_voltage_value(struct amdgpu_device *adev, 1850 const struct atom_voltage_table *table, 1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1852 static int si_get_std_voltage_value(struct amdgpu_device *adev, 1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1854 u16 *std_voltage); 1855 static int si_write_smc_soft_register(struct amdgpu_device *adev, 1856 u16 reg_offset, u32 value); 1857 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 1858 struct rv7xx_pl *pl, 1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1860 static int si_calculate_sclk_params(struct amdgpu_device *adev, 1861 u32 engine_clock, 1862 SISLANDS_SMC_SCLK_VALUE *sclk); 1863 1864 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); 1865 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); 1866 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); 1867 1868 static struct si_power_info *si_get_pi(struct amdgpu_device *adev) 1869 { 1870 struct si_power_info *pi = adev->pm.dpm.priv; 1871 return pi; 1872 } 1873 1874 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1875 u16 v, s32 t, u32 ileakage, u32 *leakage) 1876 { 1877 s64 kt, kv, leakage_w, i_leakage, vddc; 1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1879 s64 tmp; 1880 1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1882 vddc = div64_s64(drm_int2fixp(v), 1000); 1883 temperature = div64_s64(drm_int2fixp(t), 1000); 1884 1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1889 t_ref = drm_int2fixp(coeff->t_ref); 1890 1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1895 1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1897 1898 *leakage = drm_fixp2int(leakage_w * 1000); 1899 } 1900 1901 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, 1902 const struct ni_leakage_coeffients *coeff, 1903 u16 v, 1904 s32 t, 1905 u32 i_leakage, 1906 u32 *leakage) 1907 { 1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1909 } 1910 1911 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1912 const u32 fixed_kt, u16 v, 1913 u32 ileakage, u32 *leakage) 1914 { 1915 s64 kt, kv, leakage_w, i_leakage, vddc; 1916 1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1918 vddc = div64_s64(drm_int2fixp(v), 1000); 1919 1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1923 1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1925 1926 *leakage = drm_fixp2int(leakage_w * 1000); 1927 } 1928 1929 static void si_calculate_leakage_for_v(struct amdgpu_device *adev, 1930 const struct ni_leakage_coeffients *coeff, 1931 const u32 fixed_kt, 1932 u16 v, 1933 u32 i_leakage, 1934 u32 *leakage) 1935 { 1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1937 } 1938 1939 1940 static void si_update_dte_from_pl2(struct amdgpu_device *adev, 1941 struct si_dte_data *dte_data) 1942 { 1943 u32 p_limit1 = adev->pm.dpm.tdp_limit; 1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; 1945 u32 k = dte_data->k; 1946 u32 t_max = dte_data->max_t; 1947 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1948 u32 t_0 = dte_data->t0; 1949 u32 i; 1950 1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1952 dte_data->tdep_count = 3; 1953 1954 for (i = 0; i < k; i++) { 1955 dte_data->r[i] = 1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1957 (p_limit2 * (u32)100); 1958 } 1959 1960 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1961 1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1963 dte_data->tdep_r[i] = dte_data->r[4]; 1964 } 1965 } else { 1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1967 } 1968 } 1969 1970 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev) 1971 { 1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv; 1973 1974 return pi; 1975 } 1976 1977 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev) 1978 { 1979 struct ni_power_info *pi = adev->pm.dpm.priv; 1980 1981 return pi; 1982 } 1983 1984 static struct si_ps *si_get_ps(struct amdgpu_ps *aps) 1985 { 1986 struct si_ps *ps = aps->ps_priv; 1987 1988 return ps; 1989 } 1990 1991 static void si_initialize_powertune_defaults(struct amdgpu_device *adev) 1992 { 1993 struct ni_power_info *ni_pi = ni_get_pi(adev); 1994 struct si_power_info *si_pi = si_get_pi(adev); 1995 bool update_dte_from_pl2 = false; 1996 1997 if (adev->asic_type == CHIP_TAHITI) { 1998 si_pi->cac_weights = cac_weights_tahiti; 1999 si_pi->lcac_config = lcac_tahiti; 2000 si_pi->cac_override = cac_override_tahiti; 2001 si_pi->powertune_data = &powertune_data_tahiti; 2002 si_pi->dte_data = dte_data_tahiti; 2003 2004 switch (adev->pdev->device) { 2005 case 0x6798: 2006 si_pi->dte_data.enable_dte_by_default = true; 2007 break; 2008 case 0x6799: 2009 si_pi->dte_data = dte_data_new_zealand; 2010 break; 2011 case 0x6790: 2012 case 0x6791: 2013 case 0x6792: 2014 case 0x679E: 2015 si_pi->dte_data = dte_data_aruba_pro; 2016 update_dte_from_pl2 = true; 2017 break; 2018 case 0x679B: 2019 si_pi->dte_data = dte_data_malta; 2020 update_dte_from_pl2 = true; 2021 break; 2022 case 0x679A: 2023 si_pi->dte_data = dte_data_tahiti_pro; 2024 update_dte_from_pl2 = true; 2025 break; 2026 default: 2027 if (si_pi->dte_data.enable_dte_by_default == true) 2028 DRM_ERROR("DTE is not enabled!\n"); 2029 break; 2030 } 2031 } else if (adev->asic_type == CHIP_PITCAIRN) { 2032 si_pi->cac_weights = cac_weights_pitcairn; 2033 si_pi->lcac_config = lcac_pitcairn; 2034 si_pi->cac_override = cac_override_pitcairn; 2035 si_pi->powertune_data = &powertune_data_pitcairn; 2036 2037 switch (adev->pdev->device) { 2038 case 0x6810: 2039 case 0x6818: 2040 si_pi->dte_data = dte_data_curacao_xt; 2041 update_dte_from_pl2 = true; 2042 break; 2043 case 0x6819: 2044 case 0x6811: 2045 si_pi->dte_data = dte_data_curacao_pro; 2046 update_dte_from_pl2 = true; 2047 break; 2048 case 0x6800: 2049 case 0x6806: 2050 si_pi->dte_data = dte_data_neptune_xt; 2051 update_dte_from_pl2 = true; 2052 break; 2053 default: 2054 si_pi->dte_data = dte_data_pitcairn; 2055 break; 2056 } 2057 } else if (adev->asic_type == CHIP_VERDE) { 2058 si_pi->lcac_config = lcac_cape_verde; 2059 si_pi->cac_override = cac_override_cape_verde; 2060 si_pi->powertune_data = &powertune_data_cape_verde; 2061 2062 switch (adev->pdev->device) { 2063 case 0x683B: 2064 case 0x683F: 2065 case 0x6829: 2066 case 0x6835: 2067 si_pi->cac_weights = cac_weights_cape_verde_pro; 2068 si_pi->dte_data = dte_data_cape_verde; 2069 break; 2070 case 0x682C: 2071 si_pi->cac_weights = cac_weights_cape_verde_pro; 2072 si_pi->dte_data = dte_data_sun_xt; 2073 update_dte_from_pl2 = true; 2074 break; 2075 case 0x6825: 2076 case 0x6827: 2077 si_pi->cac_weights = cac_weights_heathrow; 2078 si_pi->dte_data = dte_data_cape_verde; 2079 break; 2080 case 0x6824: 2081 case 0x682D: 2082 si_pi->cac_weights = cac_weights_chelsea_xt; 2083 si_pi->dte_data = dte_data_cape_verde; 2084 break; 2085 case 0x682F: 2086 si_pi->cac_weights = cac_weights_chelsea_pro; 2087 si_pi->dte_data = dte_data_cape_verde; 2088 break; 2089 case 0x6820: 2090 si_pi->cac_weights = cac_weights_heathrow; 2091 si_pi->dte_data = dte_data_venus_xtx; 2092 break; 2093 case 0x6821: 2094 si_pi->cac_weights = cac_weights_heathrow; 2095 si_pi->dte_data = dte_data_venus_xt; 2096 break; 2097 case 0x6823: 2098 case 0x682B: 2099 case 0x6822: 2100 case 0x682A: 2101 si_pi->cac_weights = cac_weights_chelsea_pro; 2102 si_pi->dte_data = dte_data_venus_pro; 2103 break; 2104 default: 2105 si_pi->cac_weights = cac_weights_cape_verde; 2106 si_pi->dte_data = dte_data_cape_verde; 2107 break; 2108 } 2109 } else if (adev->asic_type == CHIP_OLAND) { 2110 si_pi->lcac_config = lcac_mars_pro; 2111 si_pi->cac_override = cac_override_oland; 2112 si_pi->powertune_data = &powertune_data_mars_pro; 2113 si_pi->dte_data = dte_data_mars_pro; 2114 2115 switch (adev->pdev->device) { 2116 case 0x6601: 2117 case 0x6621: 2118 case 0x6603: 2119 case 0x6605: 2120 si_pi->cac_weights = cac_weights_mars_pro; 2121 update_dte_from_pl2 = true; 2122 break; 2123 case 0x6600: 2124 case 0x6606: 2125 case 0x6620: 2126 case 0x6604: 2127 si_pi->cac_weights = cac_weights_mars_xt; 2128 update_dte_from_pl2 = true; 2129 break; 2130 case 0x6611: 2131 case 0x6613: 2132 case 0x6608: 2133 si_pi->cac_weights = cac_weights_oland_pro; 2134 update_dte_from_pl2 = true; 2135 break; 2136 case 0x6610: 2137 si_pi->cac_weights = cac_weights_oland_xt; 2138 update_dte_from_pl2 = true; 2139 break; 2140 default: 2141 si_pi->cac_weights = cac_weights_oland; 2142 si_pi->lcac_config = lcac_oland; 2143 si_pi->cac_override = cac_override_oland; 2144 si_pi->powertune_data = &powertune_data_oland; 2145 si_pi->dte_data = dte_data_oland; 2146 break; 2147 } 2148 } else if (adev->asic_type == CHIP_HAINAN) { 2149 si_pi->cac_weights = cac_weights_hainan; 2150 si_pi->lcac_config = lcac_oland; 2151 si_pi->cac_override = cac_override_oland; 2152 si_pi->powertune_data = &powertune_data_hainan; 2153 si_pi->dte_data = dte_data_sun_xt; 2154 update_dte_from_pl2 = true; 2155 } else { 2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2157 return; 2158 } 2159 2160 ni_pi->enable_power_containment = false; 2161 ni_pi->enable_cac = false; 2162 ni_pi->enable_sq_ramping = false; 2163 si_pi->enable_dte = false; 2164 2165 if (si_pi->powertune_data->enable_powertune_by_default) { 2166 ni_pi->enable_power_containment = true; 2167 ni_pi->enable_cac = true; 2168 if (si_pi->dte_data.enable_dte_by_default) { 2169 si_pi->enable_dte = true; 2170 if (update_dte_from_pl2) 2171 si_update_dte_from_pl2(adev, &si_pi->dte_data); 2172 2173 } 2174 ni_pi->enable_sq_ramping = true; 2175 } 2176 2177 ni_pi->driver_calculate_cac_leakage = true; 2178 ni_pi->cac_configuration_required = true; 2179 2180 if (ni_pi->cac_configuration_required) { 2181 ni_pi->support_cac_long_term_average = true; 2182 si_pi->dyn_powertune_data.l2_lta_window_size = 2183 si_pi->powertune_data->l2_lta_window_size_default; 2184 si_pi->dyn_powertune_data.lts_truncate = 2185 si_pi->powertune_data->lts_truncate_default; 2186 } else { 2187 ni_pi->support_cac_long_term_average = false; 2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2189 si_pi->dyn_powertune_data.lts_truncate = 0; 2190 } 2191 2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2193 } 2194 2195 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) 2196 { 2197 return 1; 2198 } 2199 2200 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev) 2201 { 2202 u32 xclk; 2203 u32 wintime; 2204 u32 cac_window; 2205 u32 cac_window_size; 2206 2207 xclk = amdgpu_asic_get_xclk(adev); 2208 2209 if (xclk == 0) 2210 return 0; 2211 2212 cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK; 2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2214 2215 wintime = (cac_window_size * 100) / xclk; 2216 2217 return wintime; 2218 } 2219 2220 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2221 { 2222 return power_in_watts; 2223 } 2224 2225 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, 2226 bool adjust_polarity, 2227 u32 tdp_adjustment, 2228 u32 *tdp_limit, 2229 u32 *near_tdp_limit) 2230 { 2231 u32 adjustment_delta, max_tdp_limit; 2232 2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) 2234 return -EINVAL; 2235 2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; 2237 2238 if (adjust_polarity) { 2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); 2241 } else { 2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; 2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) 2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2246 else 2247 *near_tdp_limit = 0; 2248 } 2249 2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2251 return -EINVAL; 2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2253 return -EINVAL; 2254 2255 return 0; 2256 } 2257 2258 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, 2259 struct amdgpu_ps *amdgpu_state) 2260 { 2261 struct ni_power_info *ni_pi = ni_get_pi(adev); 2262 struct si_power_info *si_pi = si_get_pi(adev); 2263 2264 if (ni_pi->enable_power_containment) { 2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2266 PP_SIslands_PAPMParameters *papm_parm; 2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; 2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2269 u32 tdp_limit; 2270 u32 near_tdp_limit; 2271 int ret; 2272 2273 if (scaling_factor == 0) 2274 return -EINVAL; 2275 2276 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2277 2278 ret = si_calculate_adjusted_tdp_limits(adev, 2279 false, /* ??? */ 2280 adev->pm.dpm.tdp_adjustment, 2281 &tdp_limit, 2282 &near_tdp_limit); 2283 if (ret) 2284 return ret; 2285 2286 smc_table->dpm2Params.TDPLimit = 2287 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2288 smc_table->dpm2Params.NearTDPLimit = 2289 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2290 smc_table->dpm2Params.SafePowerLimit = 2291 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2292 2293 ret = amdgpu_si_copy_bytes_to_smc(adev, 2294 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2295 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2296 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2297 sizeof(u32) * 3, 2298 si_pi->sram_end); 2299 if (ret) 2300 return ret; 2301 2302 if (si_pi->enable_ppm) { 2303 papm_parm = &si_pi->papm_parm; 2304 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2305 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2306 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2307 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2308 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2309 papm_parm->PlatformPowerLimit = 0xffffffff; 2310 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2311 2312 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2313 (u8 *)papm_parm, 2314 sizeof(PP_SIslands_PAPMParameters), 2315 si_pi->sram_end); 2316 if (ret) 2317 return ret; 2318 } 2319 } 2320 return 0; 2321 } 2322 2323 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, 2324 struct amdgpu_ps *amdgpu_state) 2325 { 2326 struct ni_power_info *ni_pi = ni_get_pi(adev); 2327 struct si_power_info *si_pi = si_get_pi(adev); 2328 2329 if (ni_pi->enable_power_containment) { 2330 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2331 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2332 int ret; 2333 2334 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2335 2336 smc_table->dpm2Params.NearTDPLimit = 2337 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2338 smc_table->dpm2Params.SafePowerLimit = 2339 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2340 2341 ret = amdgpu_si_copy_bytes_to_smc(adev, 2342 (si_pi->state_table_start + 2343 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2344 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2345 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2346 sizeof(u32) * 2, 2347 si_pi->sram_end); 2348 if (ret) 2349 return ret; 2350 } 2351 2352 return 0; 2353 } 2354 2355 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, 2356 const u16 prev_std_vddc, 2357 const u16 curr_std_vddc) 2358 { 2359 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2360 u64 prev_vddc = (u64)prev_std_vddc; 2361 u64 curr_vddc = (u64)curr_std_vddc; 2362 u64 pwr_efficiency_ratio, n, d; 2363 2364 if ((prev_vddc == 0) || (curr_vddc == 0)) 2365 return 0; 2366 2367 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2368 d = prev_vddc * prev_vddc; 2369 pwr_efficiency_ratio = div64_u64(n, d); 2370 2371 if (pwr_efficiency_ratio > (u64)0xFFFF) 2372 return 0; 2373 2374 return (u16)pwr_efficiency_ratio; 2375 } 2376 2377 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev, 2378 struct amdgpu_ps *amdgpu_state) 2379 { 2380 struct si_power_info *si_pi = si_get_pi(adev); 2381 2382 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2383 amdgpu_state->vclk && amdgpu_state->dclk) 2384 return true; 2385 2386 return false; 2387 } 2388 2389 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev) 2390 { 2391 struct evergreen_power_info *pi = adev->pm.dpm.priv; 2392 2393 return pi; 2394 } 2395 2396 static int si_populate_power_containment_values(struct amdgpu_device *adev, 2397 struct amdgpu_ps *amdgpu_state, 2398 SISLANDS_SMC_SWSTATE *smc_state) 2399 { 2400 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 2401 struct ni_power_info *ni_pi = ni_get_pi(adev); 2402 struct si_ps *state = si_get_ps(amdgpu_state); 2403 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2404 u32 prev_sclk; 2405 u32 max_sclk; 2406 u32 min_sclk; 2407 u16 prev_std_vddc; 2408 u16 curr_std_vddc; 2409 int i; 2410 u16 pwr_efficiency_ratio; 2411 u8 max_ps_percent; 2412 bool disable_uvd_power_tune; 2413 int ret; 2414 2415 if (ni_pi->enable_power_containment == false) 2416 return 0; 2417 2418 if (state->performance_level_count == 0) 2419 return -EINVAL; 2420 2421 if (smc_state->levelCount != state->performance_level_count) 2422 return -EINVAL; 2423 2424 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state); 2425 2426 smc_state->levels[0].dpm2.MaxPS = 0; 2427 smc_state->levels[0].dpm2.NearTDPDec = 0; 2428 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2429 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2430 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2431 2432 for (i = 1; i < state->performance_level_count; i++) { 2433 prev_sclk = state->performance_levels[i-1].sclk; 2434 max_sclk = state->performance_levels[i].sclk; 2435 if (i == 1) 2436 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2437 else 2438 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2439 2440 if (prev_sclk > max_sclk) 2441 return -EINVAL; 2442 2443 if ((max_ps_percent == 0) || 2444 (prev_sclk == max_sclk) || 2445 disable_uvd_power_tune) 2446 min_sclk = max_sclk; 2447 else if (i == 1) 2448 min_sclk = prev_sclk; 2449 else 2450 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2451 2452 if (min_sclk < state->performance_levels[0].sclk) 2453 min_sclk = state->performance_levels[0].sclk; 2454 2455 if (min_sclk == 0) 2456 return -EINVAL; 2457 2458 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2459 state->performance_levels[i-1].vddc, &vddc); 2460 if (ret) 2461 return ret; 2462 2463 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc); 2464 if (ret) 2465 return ret; 2466 2467 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2468 state->performance_levels[i].vddc, &vddc); 2469 if (ret) 2470 return ret; 2471 2472 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc); 2473 if (ret) 2474 return ret; 2475 2476 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev, 2477 prev_std_vddc, curr_std_vddc); 2478 2479 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2480 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2481 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2482 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2483 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2484 } 2485 2486 return 0; 2487 } 2488 2489 static int si_populate_sq_ramping_values(struct amdgpu_device *adev, 2490 struct amdgpu_ps *amdgpu_state, 2491 SISLANDS_SMC_SWSTATE *smc_state) 2492 { 2493 struct ni_power_info *ni_pi = ni_get_pi(adev); 2494 struct si_ps *state = si_get_ps(amdgpu_state); 2495 u32 sq_power_throttle, sq_power_throttle2; 2496 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2497 int i; 2498 2499 if (state->performance_level_count == 0) 2500 return -EINVAL; 2501 2502 if (smc_state->levelCount != state->performance_level_count) 2503 return -EINVAL; 2504 2505 if (adev->pm.dpm.sq_ramping_threshold == 0) 2506 return -EINVAL; 2507 2508 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (SQ_POWER_THROTTLE__MAX_POWER_MASK >> SQ_POWER_THROTTLE__MAX_POWER__SHIFT)) 2509 enable_sq_ramping = false; 2510 2511 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (SQ_POWER_THROTTLE__MIN_POWER_MASK >> SQ_POWER_THROTTLE__MIN_POWER__SHIFT)) 2512 enable_sq_ramping = false; 2513 2514 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK >> SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT)) 2515 enable_sq_ramping = false; 2516 2517 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK >> SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT)) 2518 enable_sq_ramping = false; 2519 2520 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK >> SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT)) 2521 enable_sq_ramping = false; 2522 2523 for (i = 0; i < state->performance_level_count; i++) { 2524 sq_power_throttle = 0; 2525 sq_power_throttle2 = 0; 2526 2527 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && 2528 enable_sq_ramping) { 2529 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER << SQ_POWER_THROTTLE__MAX_POWER__SHIFT; 2530 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MIN_POWER << SQ_POWER_THROTTLE__MIN_POWER__SHIFT; 2531 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA << SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT; 2532 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_STI_SIZE << SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT; 2533 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_LTI_RATIO << SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT; 2534 } else { 2535 sq_power_throttle |= SQ_POWER_THROTTLE__MAX_POWER_MASK | 2536 SQ_POWER_THROTTLE__MIN_POWER_MASK; 2537 sq_power_throttle2 |= SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | 2538 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | 2539 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 2540 } 2541 2542 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2543 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2544 } 2545 2546 return 0; 2547 } 2548 2549 static int si_enable_power_containment(struct amdgpu_device *adev, 2550 struct amdgpu_ps *amdgpu_new_state, 2551 bool enable) 2552 { 2553 struct ni_power_info *ni_pi = ni_get_pi(adev); 2554 PPSMC_Result smc_result; 2555 int ret = 0; 2556 2557 if (ni_pi->enable_power_containment) { 2558 if (enable) { 2559 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2560 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2561 if (smc_result != PPSMC_Result_OK) { 2562 ret = -EINVAL; 2563 ni_pi->pc_enabled = false; 2564 } else { 2565 ni_pi->pc_enabled = true; 2566 } 2567 } 2568 } else { 2569 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2570 if (smc_result != PPSMC_Result_OK) 2571 ret = -EINVAL; 2572 ni_pi->pc_enabled = false; 2573 } 2574 } 2575 2576 return ret; 2577 } 2578 2579 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) 2580 { 2581 struct si_power_info *si_pi = si_get_pi(adev); 2582 int ret = 0; 2583 struct si_dte_data *dte_data = &si_pi->dte_data; 2584 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2585 u32 table_size; 2586 u8 tdep_count; 2587 u32 i; 2588 2589 if (dte_data == NULL) 2590 si_pi->enable_dte = false; 2591 2592 if (si_pi->enable_dte == false) 2593 return 0; 2594 2595 if (dte_data->k <= 0) 2596 return -EINVAL; 2597 2598 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2599 if (dte_tables == NULL) { 2600 si_pi->enable_dte = false; 2601 return -ENOMEM; 2602 } 2603 2604 table_size = dte_data->k; 2605 2606 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2607 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2608 2609 tdep_count = dte_data->tdep_count; 2610 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2611 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2612 2613 dte_tables->K = cpu_to_be32(table_size); 2614 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2615 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2616 dte_tables->WindowSize = dte_data->window_size; 2617 dte_tables->temp_select = dte_data->temp_select; 2618 dte_tables->DTE_mode = dte_data->dte_mode; 2619 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2620 2621 if (tdep_count > 0) 2622 table_size--; 2623 2624 for (i = 0; i < table_size; i++) { 2625 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2626 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2627 } 2628 2629 dte_tables->Tdep_count = tdep_count; 2630 2631 for (i = 0; i < (u32)tdep_count; i++) { 2632 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2633 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2634 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2635 } 2636 2637 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, 2638 (u8 *)dte_tables, 2639 sizeof(Smc_SIslands_DTE_Configuration), 2640 si_pi->sram_end); 2641 kfree(dte_tables); 2642 2643 return ret; 2644 } 2645 2646 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, 2647 u16 *max, u16 *min) 2648 { 2649 struct si_power_info *si_pi = si_get_pi(adev); 2650 struct amdgpu_cac_leakage_table *table = 2651 &adev->pm.dpm.dyn_state.cac_leakage_table; 2652 u32 i; 2653 u32 v0_loadline; 2654 2655 if (table == NULL) 2656 return -EINVAL; 2657 2658 *max = 0; 2659 *min = 0xFFFF; 2660 2661 for (i = 0; i < table->count; i++) { 2662 if (table->entries[i].vddc > *max) 2663 *max = table->entries[i].vddc; 2664 if (table->entries[i].vddc < *min) 2665 *min = table->entries[i].vddc; 2666 } 2667 2668 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2669 return -EINVAL; 2670 2671 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2672 2673 if (v0_loadline > 0xFFFFUL) 2674 return -EINVAL; 2675 2676 *min = (u16)v0_loadline; 2677 2678 if ((*min > *max) || (*max == 0) || (*min == 0)) 2679 return -EINVAL; 2680 2681 return 0; 2682 } 2683 2684 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2685 { 2686 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2687 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2688 } 2689 2690 static int si_init_dte_leakage_table(struct amdgpu_device *adev, 2691 PP_SIslands_CacConfig *cac_tables, 2692 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2693 u16 t0, u16 t_step) 2694 { 2695 struct si_power_info *si_pi = si_get_pi(adev); 2696 u32 leakage; 2697 unsigned int i, j; 2698 s32 t; 2699 u32 smc_leakage; 2700 u32 scaling_factor; 2701 u16 voltage; 2702 2703 scaling_factor = si_get_smc_power_scaling_factor(adev); 2704 2705 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2706 t = (1000 * (i * t_step + t0)); 2707 2708 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2709 voltage = vddc_max - (vddc_step * j); 2710 2711 si_calculate_leakage_for_v_and_t(adev, 2712 &si_pi->powertune_data->leakage_coefficients, 2713 voltage, 2714 t, 2715 si_pi->dyn_powertune_data.cac_leakage, 2716 &leakage); 2717 2718 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2719 2720 if (smc_leakage > 0xFFFF) 2721 smc_leakage = 0xFFFF; 2722 2723 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2724 cpu_to_be16((u16)smc_leakage); 2725 } 2726 } 2727 return 0; 2728 } 2729 2730 static int si_init_simplified_leakage_table(struct amdgpu_device *adev, 2731 PP_SIslands_CacConfig *cac_tables, 2732 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2733 { 2734 struct si_power_info *si_pi = si_get_pi(adev); 2735 u32 leakage; 2736 unsigned int i, j; 2737 u32 smc_leakage; 2738 u32 scaling_factor; 2739 u16 voltage; 2740 2741 scaling_factor = si_get_smc_power_scaling_factor(adev); 2742 2743 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2744 voltage = vddc_max - (vddc_step * j); 2745 2746 si_calculate_leakage_for_v(adev, 2747 &si_pi->powertune_data->leakage_coefficients, 2748 si_pi->powertune_data->fixed_kt, 2749 voltage, 2750 si_pi->dyn_powertune_data.cac_leakage, 2751 &leakage); 2752 2753 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2754 2755 if (smc_leakage > 0xFFFF) 2756 smc_leakage = 0xFFFF; 2757 2758 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2759 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2760 cpu_to_be16((u16)smc_leakage); 2761 } 2762 return 0; 2763 } 2764 2765 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) 2766 { 2767 struct ni_power_info *ni_pi = ni_get_pi(adev); 2768 struct si_power_info *si_pi = si_get_pi(adev); 2769 PP_SIslands_CacConfig *cac_tables = NULL; 2770 u16 vddc_max, vddc_min, vddc_step; 2771 u16 t0, t_step; 2772 u32 load_line_slope, reg; 2773 int ret = 0; 2774 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100; 2775 2776 if (ni_pi->enable_cac == false) 2777 return 0; 2778 2779 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2780 if (!cac_tables) 2781 return -ENOMEM; 2782 2783 reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK; 2784 reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT); 2785 WREG32(mmCG_CAC_CTRL, reg); 2786 2787 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; 2788 si_pi->dyn_powertune_data.dc_pwr_value = 2789 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2790 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); 2791 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2792 2793 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2794 2795 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min); 2796 if (ret) 2797 goto done_free; 2798 2799 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2800 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2801 t_step = 4; 2802 t0 = 60; 2803 2804 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2805 ret = si_init_dte_leakage_table(adev, cac_tables, 2806 vddc_max, vddc_min, vddc_step, 2807 t0, t_step); 2808 else 2809 ret = si_init_simplified_leakage_table(adev, cac_tables, 2810 vddc_max, vddc_min, vddc_step); 2811 if (ret) 2812 goto done_free; 2813 2814 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2815 2816 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2817 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2818 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2819 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2820 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2821 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2822 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2823 cac_tables->calculation_repeats = cpu_to_be32(2); 2824 cac_tables->dc_cac = cpu_to_be32(0); 2825 cac_tables->log2_PG_LKG_SCALE = 12; 2826 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2827 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2828 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2829 2830 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, 2831 (u8 *)cac_tables, 2832 sizeof(PP_SIslands_CacConfig), 2833 si_pi->sram_end); 2834 2835 if (ret) 2836 goto done_free; 2837 2838 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2839 2840 done_free: 2841 if (ret) { 2842 ni_pi->enable_cac = false; 2843 ni_pi->enable_power_containment = false; 2844 } 2845 2846 kfree(cac_tables); 2847 2848 return ret; 2849 } 2850 2851 static int si_program_cac_config_registers(struct amdgpu_device *adev, 2852 const struct si_cac_config_reg *cac_config_regs) 2853 { 2854 const struct si_cac_config_reg *config_regs = cac_config_regs; 2855 u32 data = 0, offset; 2856 2857 if (!config_regs) 2858 return -EINVAL; 2859 2860 while (config_regs->offset != 0xFFFFFFFF) { 2861 switch (config_regs->type) { 2862 case SISLANDS_CACCONFIG_CGIND: 2863 offset = SMC_CG_IND_START + config_regs->offset; 2864 if (offset < SMC_CG_IND_END) 2865 data = RREG32_SMC(offset); 2866 break; 2867 default: 2868 data = RREG32(config_regs->offset); 2869 break; 2870 } 2871 2872 data &= ~config_regs->mask; 2873 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2874 2875 switch (config_regs->type) { 2876 case SISLANDS_CACCONFIG_CGIND: 2877 offset = SMC_CG_IND_START + config_regs->offset; 2878 if (offset < SMC_CG_IND_END) 2879 WREG32_SMC(offset, data); 2880 break; 2881 default: 2882 WREG32(config_regs->offset, data); 2883 break; 2884 } 2885 config_regs++; 2886 } 2887 return 0; 2888 } 2889 2890 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev) 2891 { 2892 struct ni_power_info *ni_pi = ni_get_pi(adev); 2893 struct si_power_info *si_pi = si_get_pi(adev); 2894 int ret; 2895 2896 if ((ni_pi->enable_cac == false) || 2897 (ni_pi->cac_configuration_required == false)) 2898 return 0; 2899 2900 ret = si_program_cac_config_registers(adev, si_pi->lcac_config); 2901 if (ret) 2902 return ret; 2903 ret = si_program_cac_config_registers(adev, si_pi->cac_override); 2904 if (ret) 2905 return ret; 2906 ret = si_program_cac_config_registers(adev, si_pi->cac_weights); 2907 if (ret) 2908 return ret; 2909 2910 return 0; 2911 } 2912 2913 static int si_enable_smc_cac(struct amdgpu_device *adev, 2914 struct amdgpu_ps *amdgpu_new_state, 2915 bool enable) 2916 { 2917 struct ni_power_info *ni_pi = ni_get_pi(adev); 2918 struct si_power_info *si_pi = si_get_pi(adev); 2919 PPSMC_Result smc_result; 2920 int ret = 0; 2921 2922 if (ni_pi->enable_cac) { 2923 if (enable) { 2924 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2925 if (ni_pi->support_cac_long_term_average) { 2926 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2927 if (smc_result != PPSMC_Result_OK) 2928 ni_pi->support_cac_long_term_average = false; 2929 } 2930 2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2932 if (smc_result != PPSMC_Result_OK) { 2933 ret = -EINVAL; 2934 ni_pi->cac_enabled = false; 2935 } else { 2936 ni_pi->cac_enabled = true; 2937 } 2938 2939 if (si_pi->enable_dte) { 2940 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2941 if (smc_result != PPSMC_Result_OK) 2942 ret = -EINVAL; 2943 } 2944 } 2945 } else if (ni_pi->cac_enabled) { 2946 if (si_pi->enable_dte) 2947 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2948 2949 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2950 2951 ni_pi->cac_enabled = false; 2952 2953 if (ni_pi->support_cac_long_term_average) 2954 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2955 } 2956 } 2957 return ret; 2958 } 2959 2960 static int si_init_smc_spll_table(struct amdgpu_device *adev) 2961 { 2962 struct ni_power_info *ni_pi = ni_get_pi(adev); 2963 struct si_power_info *si_pi = si_get_pi(adev); 2964 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2965 SISLANDS_SMC_SCLK_VALUE sclk_params; 2966 u32 fb_div, p_div; 2967 u32 clk_s, clk_v; 2968 u32 sclk = 0; 2969 int ret = 0; 2970 u32 tmp; 2971 int i; 2972 2973 if (si_pi->spll_table_start == 0) 2974 return -EINVAL; 2975 2976 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2977 if (spll_table == NULL) 2978 return -ENOMEM; 2979 2980 for (i = 0; i < 256; i++) { 2981 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); 2982 if (ret) 2983 break; 2984 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK) >> CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT; 2985 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT; 2986 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK) >> CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT; 2987 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK) >> CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT; 2988 2989 fb_div &= ~0x00001FFF; 2990 fb_div >>= 1; 2991 clk_v >>= 6; 2992 2993 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2994 ret = -EINVAL; 2995 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2996 ret = -EINVAL; 2997 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2998 ret = -EINVAL; 2999 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 3000 ret = -EINVAL; 3001 3002 if (ret) 3003 break; 3004 3005 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 3006 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 3007 spll_table->freq[i] = cpu_to_be32(tmp); 3008 3009 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 3010 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 3011 spll_table->ss[i] = cpu_to_be32(tmp); 3012 3013 sclk += 512; 3014 } 3015 3016 3017 if (!ret) 3018 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 3019 (u8 *)spll_table, 3020 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 3021 si_pi->sram_end); 3022 3023 if (ret) 3024 ni_pi->enable_power_containment = false; 3025 3026 kfree(spll_table); 3027 3028 return ret; 3029 } 3030 3031 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, 3032 u16 vce_voltage) 3033 { 3034 u16 highest_leakage = 0; 3035 struct si_power_info *si_pi = si_get_pi(adev); 3036 int i; 3037 3038 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 3039 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 3040 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 3041 } 3042 3043 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 3044 return highest_leakage; 3045 3046 return vce_voltage; 3047 } 3048 3049 static int si_get_vce_clock_voltage(struct amdgpu_device *adev, 3050 u32 evclk, u32 ecclk, u16 *voltage) 3051 { 3052 u32 i; 3053 int ret = -EINVAL; 3054 struct amdgpu_vce_clock_voltage_dependency_table *table = 3055 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3056 3057 if (((evclk == 0) && (ecclk == 0)) || 3058 (table && (table->count == 0))) { 3059 *voltage = 0; 3060 return 0; 3061 } 3062 3063 for (i = 0; i < table->count; i++) { 3064 if ((evclk <= table->entries[i].evclk) && 3065 (ecclk <= table->entries[i].ecclk)) { 3066 *voltage = table->entries[i].v; 3067 ret = 0; 3068 break; 3069 } 3070 } 3071 3072 /* if no match return the highest voltage */ 3073 if (ret) 3074 *voltage = table->entries[table->count - 1].v; 3075 3076 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage); 3077 3078 return ret; 3079 } 3080 3081 static bool si_dpm_vblank_too_short(void *handle) 3082 { 3083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3084 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); 3085 /* we never hit the non-gddr5 limit so disable it */ 3086 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; 3087 3088 /* Consider zero vblank time too short and disable MCLK switching. 3089 * Note that the vblank time is set to maximum when no displays are attached, 3090 * so we'll still enable MCLK switching in that case. 3091 */ 3092 if (vblank_time == 0) 3093 return true; 3094 else if (vblank_time < switch_limit) 3095 return true; 3096 else 3097 return false; 3098 3099 } 3100 3101 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, 3102 u32 arb_freq_src, u32 arb_freq_dest) 3103 { 3104 u32 mc_arb_dram_timing; 3105 u32 mc_arb_dram_timing2; 3106 u32 burst_time; 3107 u32 mc_cg_config; 3108 3109 switch (arb_freq_src) { 3110 case MC_CG_ARB_FREQ_F0: 3111 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 3112 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 3113 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; 3114 break; 3115 case MC_CG_ARB_FREQ_F1: 3116 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); 3117 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 3118 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; 3119 break; 3120 case MC_CG_ARB_FREQ_F2: 3121 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); 3122 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 3123 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; 3124 break; 3125 case MC_CG_ARB_FREQ_F3: 3126 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); 3127 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 3128 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; 3129 break; 3130 default: 3131 return -EINVAL; 3132 } 3133 3134 switch (arb_freq_dest) { 3135 case MC_CG_ARB_FREQ_F0: 3136 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); 3137 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 3138 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); 3139 break; 3140 case MC_CG_ARB_FREQ_F1: 3141 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 3142 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 3143 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); 3144 break; 3145 case MC_CG_ARB_FREQ_F2: 3146 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); 3147 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); 3148 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); 3149 break; 3150 case MC_CG_ARB_FREQ_F3: 3151 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); 3152 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); 3153 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); 3154 break; 3155 default: 3156 return -EINVAL; 3157 } 3158 3159 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; 3160 WREG32(MC_CG_CONFIG, mc_cg_config); 3161 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); 3162 3163 return 0; 3164 } 3165 3166 static void ni_update_current_ps(struct amdgpu_device *adev, 3167 struct amdgpu_ps *rps) 3168 { 3169 struct si_ps *new_ps = si_get_ps(rps); 3170 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3171 struct ni_power_info *ni_pi = ni_get_pi(adev); 3172 3173 eg_pi->current_rps = *rps; 3174 ni_pi->current_ps = *new_ps; 3175 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; 3176 adev->pm.dpm.current_ps = &eg_pi->current_rps; 3177 } 3178 3179 static void ni_update_requested_ps(struct amdgpu_device *adev, 3180 struct amdgpu_ps *rps) 3181 { 3182 struct si_ps *new_ps = si_get_ps(rps); 3183 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3184 struct ni_power_info *ni_pi = ni_get_pi(adev); 3185 3186 eg_pi->requested_rps = *rps; 3187 ni_pi->requested_ps = *new_ps; 3188 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; 3189 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; 3190 } 3191 3192 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, 3193 struct amdgpu_ps *new_ps, 3194 struct amdgpu_ps *old_ps) 3195 { 3196 struct si_ps *new_state = si_get_ps(new_ps); 3197 struct si_ps *current_state = si_get_ps(old_ps); 3198 3199 if ((new_ps->vclk == old_ps->vclk) && 3200 (new_ps->dclk == old_ps->dclk)) 3201 return; 3202 3203 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= 3204 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3205 return; 3206 3207 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3208 } 3209 3210 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, 3211 struct amdgpu_ps *new_ps, 3212 struct amdgpu_ps *old_ps) 3213 { 3214 struct si_ps *new_state = si_get_ps(new_ps); 3215 struct si_ps *current_state = si_get_ps(old_ps); 3216 3217 if ((new_ps->vclk == old_ps->vclk) && 3218 (new_ps->dclk == old_ps->dclk)) 3219 return; 3220 3221 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < 3222 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3223 return; 3224 3225 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3226 } 3227 3228 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) 3229 { 3230 unsigned int i; 3231 3232 for (i = 0; i < table->count; i++) 3233 if (voltage <= table->entries[i].value) 3234 return table->entries[i].value; 3235 3236 return table->entries[table->count - 1].value; 3237 } 3238 3239 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, 3240 u32 max_clock, u32 requested_clock) 3241 { 3242 unsigned int i; 3243 3244 if ((clocks == NULL) || (clocks->count == 0)) 3245 return (requested_clock < max_clock) ? requested_clock : max_clock; 3246 3247 for (i = 0; i < clocks->count; i++) { 3248 if (clocks->values[i] >= requested_clock) 3249 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; 3250 } 3251 3252 return (clocks->values[clocks->count - 1] < max_clock) ? 3253 clocks->values[clocks->count - 1] : max_clock; 3254 } 3255 3256 static u32 btc_get_valid_mclk(struct amdgpu_device *adev, 3257 u32 max_mclk, u32 requested_mclk) 3258 { 3259 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, 3260 max_mclk, requested_mclk); 3261 } 3262 3263 static u32 btc_get_valid_sclk(struct amdgpu_device *adev, 3264 u32 max_sclk, u32 requested_sclk) 3265 { 3266 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, 3267 max_sclk, requested_sclk); 3268 } 3269 3270 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table, 3271 u32 *max_clock) 3272 { 3273 u32 i, clock = 0; 3274 3275 if ((table == NULL) || (table->count == 0)) { 3276 *max_clock = clock; 3277 return; 3278 } 3279 3280 for (i = 0; i < table->count; i++) { 3281 if (clock < table->entries[i].clk) 3282 clock = table->entries[i].clk; 3283 } 3284 *max_clock = clock; 3285 } 3286 3287 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table, 3288 u32 clock, u16 max_voltage, u16 *voltage) 3289 { 3290 u32 i; 3291 3292 if ((table == NULL) || (table->count == 0)) 3293 return; 3294 3295 for (i= 0; i < table->count; i++) { 3296 if (clock <= table->entries[i].clk) { 3297 if (*voltage < table->entries[i].v) 3298 *voltage = (u16)((table->entries[i].v < max_voltage) ? 3299 table->entries[i].v : max_voltage); 3300 return; 3301 } 3302 } 3303 3304 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage; 3305 } 3306 3307 static void btc_adjust_clock_combinations(struct amdgpu_device *adev, 3308 const struct amdgpu_clock_and_voltage_limits *max_limits, 3309 struct rv7xx_pl *pl) 3310 { 3311 3312 if ((pl->mclk == 0) || (pl->sclk == 0)) 3313 return; 3314 3315 if (pl->mclk == pl->sclk) 3316 return; 3317 3318 if (pl->mclk > pl->sclk) { 3319 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) 3320 pl->sclk = btc_get_valid_sclk(adev, 3321 max_limits->sclk, 3322 (pl->mclk + 3323 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / 3324 adev->pm.dpm.dyn_state.mclk_sclk_ratio); 3325 } else { 3326 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) 3327 pl->mclk = btc_get_valid_mclk(adev, 3328 max_limits->mclk, 3329 pl->sclk - 3330 adev->pm.dpm.dyn_state.sclk_mclk_delta); 3331 } 3332 } 3333 3334 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, 3335 u16 max_vddc, u16 max_vddci, 3336 u16 *vddc, u16 *vddci) 3337 { 3338 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3339 u16 new_voltage; 3340 3341 if ((0 == *vddc) || (0 == *vddci)) 3342 return; 3343 3344 if (*vddc > *vddci) { 3345 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3346 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, 3347 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3348 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; 3349 } 3350 } else { 3351 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3352 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, 3353 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3354 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; 3355 } 3356 } 3357 } 3358 3359 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 3360 u32 *p, u32 *u) 3361 { 3362 u32 b_c = 0; 3363 u32 i_c; 3364 u32 tmp; 3365 3366 i_c = (i * r_c) / 100; 3367 tmp = i_c >> p_b; 3368 3369 while (tmp) { 3370 b_c++; 3371 tmp >>= 1; 3372 } 3373 3374 *u = (b_c + 1) / 2; 3375 *p = i_c / (1 << (2 * (*u))); 3376 } 3377 3378 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) 3379 { 3380 u32 k, a, ah, al; 3381 u32 t1; 3382 3383 if ((fl == 0) || (fh == 0) || (fl > fh)) 3384 return -EINVAL; 3385 3386 k = (100 * fh) / fl; 3387 t1 = (t * (k - 100)); 3388 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); 3389 a = (a + 5) / 10; 3390 ah = ((a * t) + 5000) / 10000; 3391 al = a - ah; 3392 3393 *th = t - ah; 3394 *tl = t + al; 3395 3396 return 0; 3397 } 3398 3399 static bool r600_is_uvd_state(u32 class, u32 class2) 3400 { 3401 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 3402 return true; 3403 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 3404 return true; 3405 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 3406 return true; 3407 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 3408 return true; 3409 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 3410 return true; 3411 return false; 3412 } 3413 3414 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev) 3415 { 3416 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); 3417 } 3418 3419 static void rv770_get_max_vddc(struct amdgpu_device *adev) 3420 { 3421 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3422 u16 vddc; 3423 3424 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc)) 3425 pi->max_vddc = 0; 3426 else 3427 pi->max_vddc = vddc; 3428 } 3429 3430 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) 3431 { 3432 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3433 struct amdgpu_atom_ss ss; 3434 3435 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3436 ASIC_INTERNAL_ENGINE_SS, 0); 3437 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3438 ASIC_INTERNAL_MEMORY_SS, 0); 3439 3440 if (pi->sclk_ss || pi->mclk_ss) 3441 pi->dynamic_ss = true; 3442 else 3443 pi->dynamic_ss = false; 3444 } 3445 3446 3447 static void si_apply_state_adjust_rules(struct amdgpu_device *adev, 3448 struct amdgpu_ps *rps) 3449 { 3450 struct si_ps *ps = si_get_ps(rps); 3451 struct amdgpu_clock_and_voltage_limits *max_limits; 3452 struct amdgpu_connector *conn; 3453 bool disable_mclk_switching = false; 3454 bool disable_sclk_switching = false; 3455 u32 mclk, sclk; 3456 u16 vddc, vddci, min_vce_voltage = 0; 3457 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 3458 u32 max_sclk = 0, max_mclk = 0; 3459 u32 high_pixelclock_count = 0; 3460 int i; 3461 3462 if (adev->asic_type == CHIP_HAINAN) { 3463 if ((adev->pdev->revision == 0x81) || 3464 (adev->pdev->revision == 0xC3) || 3465 (adev->pdev->device == 0x6664) || 3466 (adev->pdev->device == 0x6665) || 3467 (adev->pdev->device == 0x6667)) { 3468 max_sclk = 75000; 3469 } 3470 if ((adev->pdev->revision == 0xC3) || 3471 (adev->pdev->device == 0x6665)) { 3472 max_sclk = 60000; 3473 max_mclk = 80000; 3474 } 3475 } else if (adev->asic_type == CHIP_OLAND) { 3476 if ((adev->pdev->revision == 0xC7) || 3477 (adev->pdev->revision == 0x80) || 3478 (adev->pdev->revision == 0x81) || 3479 (adev->pdev->revision == 0x83) || 3480 (adev->pdev->revision == 0x87) || 3481 (adev->pdev->device == 0x6604) || 3482 (adev->pdev->device == 0x6605)) { 3483 max_sclk = 75000; 3484 } 3485 } 3486 3487 /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz. 3488 * For example, 4K 60Hz and 1080p 144Hz fall into this category. 3489 * Find number of such displays connected. 3490 */ 3491 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3492 if (!(adev->pm.dpm.new_active_crtcs & (1 << i)) || 3493 !adev->mode_info.crtcs[i]->enabled) 3494 continue; 3495 3496 conn = to_amdgpu_connector(adev->mode_info.crtcs[i]->connector); 3497 3498 if (conn->pixelclock_for_modeset > 297000) 3499 high_pixelclock_count++; 3500 } 3501 3502 /* These are some ad-hoc fixes to some issues observed with SI GPUs. 3503 * They are necessary because we don't have something like dce_calcs 3504 * for these GPUs to calculate bandwidth requirements. 3505 */ 3506 if (high_pixelclock_count) { 3507 /* On Oland, we observe some flickering when two 4K 60Hz 3508 * displays are connected, possibly because voltage is too low. 3509 * Raise the voltage by requiring a higher SCLK. 3510 * (Voltage cannot be adjusted independently without also SCLK.) 3511 */ 3512 if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND) 3513 disable_sclk_switching = true; 3514 } 3515 3516 if (rps->vce_active) { 3517 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 3518 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; 3519 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, 3520 &min_vce_voltage); 3521 } else { 3522 rps->evclk = 0; 3523 rps->ecclk = 0; 3524 } 3525 3526 if ((adev->pm.dpm.new_active_crtc_count > 1) || 3527 si_dpm_vblank_too_short(adev)) 3528 disable_mclk_switching = true; 3529 3530 if (rps->vclk || rps->dclk) { 3531 disable_mclk_switching = true; 3532 disable_sclk_switching = true; 3533 } 3534 3535 if (adev->pm.ac_power) 3536 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3537 else 3538 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3539 3540 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3541 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3542 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3543 } 3544 if (adev->pm.ac_power == false) { 3545 for (i = 0; i < ps->performance_level_count; i++) { 3546 if (ps->performance_levels[i].mclk > max_limits->mclk) 3547 ps->performance_levels[i].mclk = max_limits->mclk; 3548 if (ps->performance_levels[i].sclk > max_limits->sclk) 3549 ps->performance_levels[i].sclk = max_limits->sclk; 3550 if (ps->performance_levels[i].vddc > max_limits->vddc) 3551 ps->performance_levels[i].vddc = max_limits->vddc; 3552 if (ps->performance_levels[i].vddci > max_limits->vddci) 3553 ps->performance_levels[i].vddci = max_limits->vddci; 3554 } 3555 } 3556 3557 /* limit clocks to max supported clocks based on voltage dependency tables */ 3558 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3559 &max_sclk_vddc); 3560 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3561 &max_mclk_vddci); 3562 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3563 &max_mclk_vddc); 3564 3565 for (i = 0; i < ps->performance_level_count; i++) { 3566 if (max_sclk_vddc) { 3567 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3568 ps->performance_levels[i].sclk = max_sclk_vddc; 3569 } 3570 if (max_mclk_vddci) { 3571 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3572 ps->performance_levels[i].mclk = max_mclk_vddci; 3573 } 3574 if (max_mclk_vddc) { 3575 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3576 ps->performance_levels[i].mclk = max_mclk_vddc; 3577 } 3578 if (max_mclk) { 3579 if (ps->performance_levels[i].mclk > max_mclk) 3580 ps->performance_levels[i].mclk = max_mclk; 3581 } 3582 if (max_sclk) { 3583 if (ps->performance_levels[i].sclk > max_sclk) 3584 ps->performance_levels[i].sclk = max_sclk; 3585 } 3586 } 3587 3588 /* XXX validate the min clocks required for display */ 3589 3590 if (disable_mclk_switching) { 3591 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3592 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3593 } else { 3594 mclk = ps->performance_levels[0].mclk; 3595 vddci = ps->performance_levels[0].vddci; 3596 } 3597 3598 if (disable_sclk_switching) { 3599 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3600 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3601 } else { 3602 sclk = ps->performance_levels[0].sclk; 3603 vddc = ps->performance_levels[0].vddc; 3604 } 3605 3606 if (rps->vce_active) { 3607 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) 3608 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; 3609 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) 3610 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; 3611 } 3612 3613 /* adjusted low state */ 3614 ps->performance_levels[0].sclk = sclk; 3615 ps->performance_levels[0].mclk = mclk; 3616 ps->performance_levels[0].vddc = vddc; 3617 ps->performance_levels[0].vddci = vddci; 3618 3619 if (disable_sclk_switching) { 3620 sclk = ps->performance_levels[0].sclk; 3621 for (i = 1; i < ps->performance_level_count; i++) { 3622 if (sclk < ps->performance_levels[i].sclk) 3623 sclk = ps->performance_levels[i].sclk; 3624 } 3625 for (i = 0; i < ps->performance_level_count; i++) { 3626 ps->performance_levels[i].sclk = sclk; 3627 ps->performance_levels[i].vddc = vddc; 3628 } 3629 } else { 3630 for (i = 1; i < ps->performance_level_count; i++) { 3631 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3632 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3633 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3634 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3635 } 3636 } 3637 3638 if (disable_mclk_switching) { 3639 mclk = ps->performance_levels[0].mclk; 3640 for (i = 1; i < ps->performance_level_count; i++) { 3641 if (mclk < ps->performance_levels[i].mclk) 3642 mclk = ps->performance_levels[i].mclk; 3643 } 3644 for (i = 0; i < ps->performance_level_count; i++) { 3645 ps->performance_levels[i].mclk = mclk; 3646 ps->performance_levels[i].vddci = vddci; 3647 } 3648 } else { 3649 for (i = 1; i < ps->performance_level_count; i++) { 3650 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3651 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3652 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3653 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3654 } 3655 } 3656 3657 for (i = 0; i < ps->performance_level_count; i++) 3658 btc_adjust_clock_combinations(adev, max_limits, 3659 &ps->performance_levels[i]); 3660 3661 for (i = 0; i < ps->performance_level_count; i++) { 3662 if (ps->performance_levels[i].vddc < min_vce_voltage) 3663 ps->performance_levels[i].vddc = min_vce_voltage; 3664 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3665 ps->performance_levels[i].sclk, 3666 max_limits->vddc, &ps->performance_levels[i].vddc); 3667 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3668 ps->performance_levels[i].mclk, 3669 max_limits->vddci, &ps->performance_levels[i].vddci); 3670 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3671 ps->performance_levels[i].mclk, 3672 max_limits->vddc, &ps->performance_levels[i].vddc); 3673 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3674 adev->clock.current_dispclk, 3675 max_limits->vddc, &ps->performance_levels[i].vddc); 3676 } 3677 3678 for (i = 0; i < ps->performance_level_count; i++) { 3679 btc_apply_voltage_delta_rules(adev, 3680 max_limits->vddc, max_limits->vddci, 3681 &ps->performance_levels[i].vddc, 3682 &ps->performance_levels[i].vddci); 3683 } 3684 3685 ps->dc_compatible = true; 3686 for (i = 0; i < ps->performance_level_count; i++) { 3687 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3688 ps->dc_compatible = false; 3689 } 3690 } 3691 3692 #if 0 3693 static int si_read_smc_soft_register(struct amdgpu_device *adev, 3694 u16 reg_offset, u32 *value) 3695 { 3696 struct si_power_info *si_pi = si_get_pi(adev); 3697 3698 return amdgpu_si_read_smc_sram_dword(adev, 3699 si_pi->soft_regs_start + reg_offset, value, 3700 si_pi->sram_end); 3701 } 3702 #endif 3703 3704 static int si_write_smc_soft_register(struct amdgpu_device *adev, 3705 u16 reg_offset, u32 value) 3706 { 3707 struct si_power_info *si_pi = si_get_pi(adev); 3708 3709 return amdgpu_si_write_smc_sram_dword(adev, 3710 si_pi->soft_regs_start + reg_offset, 3711 value, si_pi->sram_end); 3712 } 3713 3714 static bool si_is_special_1gb_platform(struct amdgpu_device *adev) 3715 { 3716 bool ret = false; 3717 u32 tmp, width, row, column, bank, density; 3718 bool is_memory_gddr5, is_special; 3719 3720 tmp = RREG32(MC_SEQ_MISC0); 3721 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3722 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3723 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3724 3725 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3726 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3727 3728 tmp = RREG32(mmMC_ARB_RAMCFG); 3729 row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10; 3730 column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8; 3731 bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2; 3732 3733 density = (1 << (row + column - 20 + bank)) * width; 3734 3735 if ((adev->pdev->device == 0x6819) && 3736 is_memory_gddr5 && is_special && (density == 0x400)) 3737 ret = true; 3738 3739 return ret; 3740 } 3741 3742 static void si_get_leakage_vddc(struct amdgpu_device *adev) 3743 { 3744 struct si_power_info *si_pi = si_get_pi(adev); 3745 u16 vddc, count = 0; 3746 int i, ret; 3747 3748 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3749 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3750 3751 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3752 si_pi->leakage_voltage.entries[count].voltage = vddc; 3753 si_pi->leakage_voltage.entries[count].leakage_index = 3754 SISLANDS_LEAKAGE_INDEX0 + i; 3755 count++; 3756 } 3757 } 3758 si_pi->leakage_voltage.count = count; 3759 } 3760 3761 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, 3762 u32 index, u16 *leakage_voltage) 3763 { 3764 struct si_power_info *si_pi = si_get_pi(adev); 3765 int i; 3766 3767 if (leakage_voltage == NULL) 3768 return -EINVAL; 3769 3770 if ((index & 0xff00) != 0xff00) 3771 return -EINVAL; 3772 3773 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3774 return -EINVAL; 3775 3776 if (index < SISLANDS_LEAKAGE_INDEX0) 3777 return -EINVAL; 3778 3779 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3780 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3781 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3782 return 0; 3783 } 3784 } 3785 return -EAGAIN; 3786 } 3787 3788 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) 3789 { 3790 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3791 bool want_thermal_protection; 3792 enum si_dpm_event_src dpm_event_src; 3793 3794 switch (sources) { 3795 case 0: 3796 default: 3797 want_thermal_protection = false; 3798 break; 3799 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL): 3800 want_thermal_protection = true; 3801 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL; 3802 break; 3803 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3804 want_thermal_protection = true; 3805 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL; 3806 break; 3807 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3808 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3809 want_thermal_protection = true; 3810 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3811 break; 3812 } 3813 3814 if (want_thermal_protection) { 3815 WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK); 3816 if (pi->thermal_protection) 3817 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 3818 } else { 3819 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 3820 } 3821 } 3822 3823 static void si_enable_auto_throttle_source(struct amdgpu_device *adev, 3824 enum si_dpm_auto_throttle_src source, 3825 bool enable) 3826 { 3827 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3828 3829 if (enable) { 3830 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3831 pi->active_auto_throttle_sources |= 1 << source; 3832 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3833 } 3834 } else { 3835 if (pi->active_auto_throttle_sources & (1 << source)) { 3836 pi->active_auto_throttle_sources &= ~(1 << source); 3837 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3838 } 3839 } 3840 } 3841 3842 static void si_start_dpm(struct amdgpu_device *adev) 3843 { 3844 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK); 3845 } 3846 3847 static void si_stop_dpm(struct amdgpu_device *adev) 3848 { 3849 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK); 3850 } 3851 3852 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable) 3853 { 3854 if (enable) 3855 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK); 3856 else 3857 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK); 3858 3859 } 3860 3861 #if 0 3862 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, 3863 u32 thermal_level) 3864 { 3865 PPSMC_Result ret; 3866 3867 if (thermal_level == 0) { 3868 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3869 if (ret == PPSMC_Result_OK) 3870 return 0; 3871 else 3872 return -EINVAL; 3873 } 3874 return 0; 3875 } 3876 3877 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) 3878 { 3879 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3880 } 3881 #endif 3882 3883 #if 0 3884 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) 3885 { 3886 if (ac_power) 3887 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3888 0 : -EINVAL; 3889 3890 return 0; 3891 } 3892 #endif 3893 3894 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, 3895 PPSMC_Msg msg, u32 parameter) 3896 { 3897 WREG32(mmSMC_SCRATCH0, parameter); 3898 return amdgpu_si_send_msg_to_smc(adev, msg); 3899 } 3900 3901 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) 3902 { 3903 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3904 return -EINVAL; 3905 3906 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3907 0 : -EINVAL; 3908 } 3909 3910 static int si_dpm_force_performance_level(void *handle, 3911 enum amd_dpm_forced_level level) 3912 { 3913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3914 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; 3915 struct si_ps *ps = si_get_ps(rps); 3916 u32 levels = ps->performance_level_count; 3917 3918 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 3919 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3920 return -EINVAL; 3921 3922 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3923 return -EINVAL; 3924 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { 3925 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3926 return -EINVAL; 3927 3928 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3929 return -EINVAL; 3930 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { 3931 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3932 return -EINVAL; 3933 3934 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3935 return -EINVAL; 3936 } 3937 3938 adev->pm.dpm.forced_level = level; 3939 3940 return 0; 3941 } 3942 3943 #if 0 3944 static int si_set_boot_state(struct amdgpu_device *adev) 3945 { 3946 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3947 0 : -EINVAL; 3948 } 3949 #endif 3950 3951 static int si_set_sw_state(struct amdgpu_device *adev) 3952 { 3953 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3954 0 : -EINVAL; 3955 } 3956 3957 static int si_halt_smc(struct amdgpu_device *adev) 3958 { 3959 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3960 return -EINVAL; 3961 3962 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3963 0 : -EINVAL; 3964 } 3965 3966 static int si_resume_smc(struct amdgpu_device *adev) 3967 { 3968 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3969 return -EINVAL; 3970 3971 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3972 0 : -EINVAL; 3973 } 3974 3975 static void si_dpm_start_smc(struct amdgpu_device *adev) 3976 { 3977 amdgpu_si_program_jump_on_start(adev); 3978 amdgpu_si_start_smc(adev); 3979 amdgpu_si_smc_clock(adev, true); 3980 } 3981 3982 static void si_dpm_stop_smc(struct amdgpu_device *adev) 3983 { 3984 amdgpu_si_reset_smc(adev); 3985 amdgpu_si_smc_clock(adev, false); 3986 } 3987 3988 static int si_process_firmware_header(struct amdgpu_device *adev) 3989 { 3990 struct si_power_info *si_pi = si_get_pi(adev); 3991 u32 tmp; 3992 int ret; 3993 3994 ret = amdgpu_si_read_smc_sram_dword(adev, 3995 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3996 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3997 &tmp, si_pi->sram_end); 3998 if (ret) 3999 return ret; 4000 4001 si_pi->state_table_start = tmp; 4002 4003 ret = amdgpu_si_read_smc_sram_dword(adev, 4004 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4005 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 4006 &tmp, si_pi->sram_end); 4007 if (ret) 4008 return ret; 4009 4010 si_pi->soft_regs_start = tmp; 4011 4012 ret = amdgpu_si_read_smc_sram_dword(adev, 4013 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4014 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 4015 &tmp, si_pi->sram_end); 4016 if (ret) 4017 return ret; 4018 4019 si_pi->mc_reg_table_start = tmp; 4020 4021 ret = amdgpu_si_read_smc_sram_dword(adev, 4022 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4023 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 4024 &tmp, si_pi->sram_end); 4025 if (ret) 4026 return ret; 4027 4028 si_pi->fan_table_start = tmp; 4029 4030 ret = amdgpu_si_read_smc_sram_dword(adev, 4031 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4032 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 4033 &tmp, si_pi->sram_end); 4034 if (ret) 4035 return ret; 4036 4037 si_pi->arb_table_start = tmp; 4038 4039 ret = amdgpu_si_read_smc_sram_dword(adev, 4040 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4041 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4042 &tmp, si_pi->sram_end); 4043 if (ret) 4044 return ret; 4045 4046 si_pi->cac_table_start = tmp; 4047 4048 ret = amdgpu_si_read_smc_sram_dword(adev, 4049 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4050 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4051 &tmp, si_pi->sram_end); 4052 if (ret) 4053 return ret; 4054 4055 si_pi->dte_table_start = tmp; 4056 4057 ret = amdgpu_si_read_smc_sram_dword(adev, 4058 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4059 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4060 &tmp, si_pi->sram_end); 4061 if (ret) 4062 return ret; 4063 4064 si_pi->spll_table_start = tmp; 4065 4066 ret = amdgpu_si_read_smc_sram_dword(adev, 4067 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4068 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4069 &tmp, si_pi->sram_end); 4070 if (ret) 4071 return ret; 4072 4073 si_pi->papm_cfg_table_start = tmp; 4074 4075 return ret; 4076 } 4077 4078 static void si_read_clock_registers(struct amdgpu_device *adev) 4079 { 4080 struct si_power_info *si_pi = si_get_pi(adev); 4081 4082 si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL); 4083 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2); 4084 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3); 4085 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4); 4086 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM); 4087 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2); 4088 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 4089 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 4090 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 4091 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 4092 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 4093 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 4094 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 4095 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 4096 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 4097 } 4098 4099 static void si_enable_thermal_protection(struct amdgpu_device *adev, 4100 bool enable) 4101 { 4102 if (enable) 4103 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 4104 else 4105 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 4106 } 4107 4108 static void si_enable_acpi_power_management(struct amdgpu_device *adev) 4109 { 4110 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK); 4111 } 4112 4113 #if 0 4114 static int si_enter_ulp_state(struct amdgpu_device *adev) 4115 { 4116 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 4117 4118 udelay(25000); 4119 4120 return 0; 4121 } 4122 4123 static int si_exit_ulp_state(struct amdgpu_device *adev) 4124 { 4125 int i; 4126 4127 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 4128 4129 udelay(7000); 4130 4131 for (i = 0; i < adev->usec_timeout; i++) { 4132 if (RREG32(SMC_RESP_0) == 1) 4133 break; 4134 udelay(1000); 4135 } 4136 4137 return 0; 4138 } 4139 #endif 4140 4141 static int si_notify_smc_display_change(struct amdgpu_device *adev, 4142 bool has_display) 4143 { 4144 PPSMC_Msg msg = has_display ? 4145 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 4146 4147 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4148 0 : -EINVAL; 4149 } 4150 4151 static void si_program_response_times(struct amdgpu_device *adev) 4152 { 4153 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 4154 u32 vddc_dly, acpi_dly, vbi_dly; 4155 u32 reference_clock; 4156 4157 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 4158 4159 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; 4160 4161 if (voltage_response_time == 0) 4162 voltage_response_time = 1000; 4163 4164 acpi_delay_time = 15000; 4165 vbi_time_out = 100000; 4166 4167 reference_clock = amdgpu_asic_get_xclk(adev); 4168 4169 vddc_dly = (voltage_response_time * reference_clock) / 100; 4170 acpi_dly = (acpi_delay_time * reference_clock) / 100; 4171 vbi_dly = (vbi_time_out * reference_clock) / 100; 4172 4173 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 4174 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 4175 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 4176 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 4177 } 4178 4179 static void si_program_ds_registers(struct amdgpu_device *adev) 4180 { 4181 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4182 u32 tmp; 4183 4184 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */ 4185 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0) 4186 tmp = 0x10; 4187 else 4188 tmp = 0x1; 4189 4190 if (eg_pi->sclk_deep_sleep) { 4191 WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK); 4192 WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK, 4193 ~CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK); 4194 } 4195 } 4196 4197 static void si_program_display_gap(struct amdgpu_device *adev) 4198 { 4199 u32 tmp, pipe; 4200 int i; 4201 4202 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); 4203 if (adev->pm.dpm.new_active_crtc_count > 0) 4204 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; 4205 else 4206 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; 4207 4208 if (adev->pm.dpm.new_active_crtc_count > 1) 4209 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; 4210 else 4211 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; 4212 4213 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp); 4214 4215 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 4216 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 4217 4218 if ((adev->pm.dpm.new_active_crtc_count > 0) && 4219 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 4220 /* find the first active crtc */ 4221 for (i = 0; i < adev->mode_info.num_crtc; i++) { 4222 if (adev->pm.dpm.new_active_crtcs & (1 << i)) 4223 break; 4224 } 4225 if (i == adev->mode_info.num_crtc) 4226 pipe = 0; 4227 else 4228 pipe = i; 4229 4230 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 4231 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 4232 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 4233 } 4234 4235 /* Setting this to false forces the performance state to low if the crtcs are disabled. 4236 * This can be a problem on PowerXpress systems or if you want to use the card 4237 * for offscreen rendering or compute if there are no crtcs enabled. 4238 */ 4239 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); 4240 } 4241 4242 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) 4243 { 4244 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4245 4246 if (enable) { 4247 if (pi->sclk_ss) 4248 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK); 4249 } else { 4250 WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK); 4251 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK); 4252 } 4253 } 4254 4255 static void si_setup_bsp(struct amdgpu_device *adev) 4256 { 4257 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4258 u32 xclk = amdgpu_asic_get_xclk(adev); 4259 4260 r600_calculate_u_and_p(pi->asi, 4261 xclk, 4262 16, 4263 &pi->bsp, 4264 &pi->bsu); 4265 4266 r600_calculate_u_and_p(pi->pasi, 4267 xclk, 4268 16, 4269 &pi->pbsp, 4270 &pi->pbsu); 4271 4272 4273 pi->dsp = (pi->bsp << CG_BSP__BSP__SHIFT) | (pi->bsu << CG_BSP__BSU__SHIFT); 4274 pi->psp = (pi->pbsp << CG_BSP__BSP__SHIFT) | (pi->pbsu << CG_BSP__BSU__SHIFT); 4275 4276 WREG32(mmCG_BSP, pi->dsp); 4277 } 4278 4279 static void si_program_git(struct amdgpu_device *adev) 4280 { 4281 WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK); 4282 } 4283 4284 static void si_program_tp(struct amdgpu_device *adev) 4285 { 4286 int i; 4287 enum r600_td td = R600_TD_DFLT; 4288 4289 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 4290 WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT)); 4291 4292 if (td == R600_TD_AUTO) 4293 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK); 4294 else 4295 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK); 4296 4297 if (td == R600_TD_UP) 4298 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK); 4299 4300 if (td == R600_TD_DOWN) 4301 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK); 4302 } 4303 4304 static void si_program_tpp(struct amdgpu_device *adev) 4305 { 4306 WREG32(mmCG_TPC, R600_TPC_DFLT); 4307 } 4308 4309 static void si_program_sstp(struct amdgpu_device *adev) 4310 { 4311 WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT)); 4312 } 4313 4314 static void si_enable_display_gap(struct amdgpu_device *adev) 4315 { 4316 u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL); 4317 4318 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); 4319 tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT | 4320 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT); 4321 4322 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK); 4323 tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT | 4324 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT); 4325 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp); 4326 } 4327 4328 static void si_program_vc(struct amdgpu_device *adev) 4329 { 4330 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4331 4332 WREG32(mmCG_FTV, pi->vrc); 4333 } 4334 4335 static void si_clear_vc(struct amdgpu_device *adev) 4336 { 4337 WREG32(mmCG_FTV, 0); 4338 } 4339 4340 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 4341 { 4342 u8 mc_para_index; 4343 4344 if (memory_clock < 10000) 4345 mc_para_index = 0; 4346 else if (memory_clock >= 80000) 4347 mc_para_index = 0x0f; 4348 else 4349 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 4350 return mc_para_index; 4351 } 4352 4353 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 4354 { 4355 u8 mc_para_index; 4356 4357 if (strobe_mode) { 4358 if (memory_clock < 12500) 4359 mc_para_index = 0x00; 4360 else if (memory_clock > 47500) 4361 mc_para_index = 0x0f; 4362 else 4363 mc_para_index = (u8)((memory_clock - 10000) / 2500); 4364 } else { 4365 if (memory_clock < 65000) 4366 mc_para_index = 0x00; 4367 else if (memory_clock > 135000) 4368 mc_para_index = 0x0f; 4369 else 4370 mc_para_index = (u8)((memory_clock - 60000) / 5000); 4371 } 4372 return mc_para_index; 4373 } 4374 4375 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) 4376 { 4377 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4378 bool strobe_mode = false; 4379 u8 result = 0; 4380 4381 if (mclk <= pi->mclk_strobe_mode_threshold) 4382 strobe_mode = true; 4383 4384 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 4385 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 4386 else 4387 result = si_get_ddr3_mclk_frequency_ratio(mclk); 4388 4389 if (strobe_mode) 4390 result |= SISLANDS_SMC_STROBE_ENABLE; 4391 4392 return result; 4393 } 4394 4395 static int si_upload_firmware(struct amdgpu_device *adev) 4396 { 4397 struct si_power_info *si_pi = si_get_pi(adev); 4398 4399 amdgpu_si_reset_smc(adev); 4400 amdgpu_si_smc_clock(adev, false); 4401 4402 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); 4403 } 4404 4405 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, 4406 const struct atom_voltage_table *table, 4407 const struct amdgpu_phase_shedding_limits_table *limits) 4408 { 4409 u32 data, num_bits, num_levels; 4410 4411 if ((table == NULL) || (limits == NULL)) 4412 return false; 4413 4414 data = table->mask_low; 4415 4416 num_bits = hweight32(data); 4417 4418 if (num_bits == 0) 4419 return false; 4420 4421 num_levels = (1 << num_bits); 4422 4423 if (table->count != num_levels) 4424 return false; 4425 4426 if (limits->count != (num_levels - 1)) 4427 return false; 4428 4429 return true; 4430 } 4431 4432 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, 4433 u32 max_voltage_steps, 4434 struct atom_voltage_table *voltage_table) 4435 { 4436 unsigned int i, diff; 4437 4438 if (voltage_table->count <= max_voltage_steps) 4439 return; 4440 4441 diff = voltage_table->count - max_voltage_steps; 4442 4443 for (i= 0; i < max_voltage_steps; i++) 4444 voltage_table->entries[i] = voltage_table->entries[i + diff]; 4445 4446 voltage_table->count = max_voltage_steps; 4447 } 4448 4449 static int si_get_svi2_voltage_table(struct amdgpu_device *adev, 4450 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, 4451 struct atom_voltage_table *voltage_table) 4452 { 4453 u32 i; 4454 4455 if (voltage_dependency_table == NULL) 4456 return -EINVAL; 4457 4458 voltage_table->mask_low = 0; 4459 voltage_table->phase_delay = 0; 4460 4461 voltage_table->count = voltage_dependency_table->count; 4462 for (i = 0; i < voltage_table->count; i++) { 4463 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 4464 voltage_table->entries[i].smio_low = 0; 4465 } 4466 4467 return 0; 4468 } 4469 4470 static int si_construct_voltage_tables(struct amdgpu_device *adev) 4471 { 4472 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4473 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4474 struct si_power_info *si_pi = si_get_pi(adev); 4475 int ret; 4476 4477 if (pi->voltage_control) { 4478 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4479 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 4480 if (ret) 4481 return ret; 4482 4483 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4484 si_trim_voltage_table_to_fit_state_table(adev, 4485 SISLANDS_MAX_NO_VREG_STEPS, 4486 &eg_pi->vddc_voltage_table); 4487 } else if (si_pi->voltage_control_svi2) { 4488 ret = si_get_svi2_voltage_table(adev, 4489 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4490 &eg_pi->vddc_voltage_table); 4491 if (ret) 4492 return ret; 4493 } else { 4494 return -EINVAL; 4495 } 4496 4497 if (eg_pi->vddci_control) { 4498 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, 4499 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4500 if (ret) 4501 return ret; 4502 4503 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4504 si_trim_voltage_table_to_fit_state_table(adev, 4505 SISLANDS_MAX_NO_VREG_STEPS, 4506 &eg_pi->vddci_voltage_table); 4507 } 4508 if (si_pi->vddci_control_svi2) { 4509 ret = si_get_svi2_voltage_table(adev, 4510 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4511 &eg_pi->vddci_voltage_table); 4512 if (ret) 4513 return ret; 4514 } 4515 4516 if (pi->mvdd_control) { 4517 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, 4518 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4519 4520 if (ret) { 4521 pi->mvdd_control = false; 4522 return ret; 4523 } 4524 4525 if (si_pi->mvdd_voltage_table.count == 0) { 4526 pi->mvdd_control = false; 4527 return -EINVAL; 4528 } 4529 4530 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4531 si_trim_voltage_table_to_fit_state_table(adev, 4532 SISLANDS_MAX_NO_VREG_STEPS, 4533 &si_pi->mvdd_voltage_table); 4534 } 4535 4536 if (si_pi->vddc_phase_shed_control) { 4537 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4538 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4539 if (ret) 4540 si_pi->vddc_phase_shed_control = false; 4541 4542 if ((si_pi->vddc_phase_shed_table.count == 0) || 4543 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4544 si_pi->vddc_phase_shed_control = false; 4545 } 4546 4547 return 0; 4548 } 4549 4550 static void si_populate_smc_voltage_table(struct amdgpu_device *adev, 4551 const struct atom_voltage_table *voltage_table, 4552 SISLANDS_SMC_STATETABLE *table) 4553 { 4554 unsigned int i; 4555 4556 for (i = 0; i < voltage_table->count; i++) 4557 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4558 } 4559 4560 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev, 4561 SISLANDS_SMC_STATETABLE *table) 4562 { 4563 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4564 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4565 struct si_power_info *si_pi = si_get_pi(adev); 4566 u8 i; 4567 4568 if (si_pi->voltage_control_svi2) { 4569 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4570 si_pi->svc_gpio_id); 4571 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4572 si_pi->svd_gpio_id); 4573 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4574 2); 4575 } else { 4576 if (eg_pi->vddc_voltage_table.count) { 4577 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); 4578 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4579 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4580 4581 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4582 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4583 table->maxVDDCIndexInPPTable = i; 4584 break; 4585 } 4586 } 4587 } 4588 4589 if (eg_pi->vddci_voltage_table.count) { 4590 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); 4591 4592 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4593 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4594 } 4595 4596 4597 if (si_pi->mvdd_voltage_table.count) { 4598 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); 4599 4600 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4601 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4602 } 4603 4604 if (si_pi->vddc_phase_shed_control) { 4605 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, 4606 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4607 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); 4608 4609 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4610 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4611 4612 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4613 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4614 } else { 4615 si_pi->vddc_phase_shed_control = false; 4616 } 4617 } 4618 } 4619 4620 return 0; 4621 } 4622 4623 static int si_populate_voltage_value(struct amdgpu_device *adev, 4624 const struct atom_voltage_table *table, 4625 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4626 { 4627 unsigned int i; 4628 4629 for (i = 0; i < table->count; i++) { 4630 if (value <= table->entries[i].value) { 4631 voltage->index = (u8)i; 4632 voltage->value = cpu_to_be16(table->entries[i].value); 4633 break; 4634 } 4635 } 4636 4637 if (i >= table->count) 4638 return -EINVAL; 4639 4640 return 0; 4641 } 4642 4643 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, 4644 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4645 { 4646 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4647 struct si_power_info *si_pi = si_get_pi(adev); 4648 4649 if (pi->mvdd_control) { 4650 if (mclk <= pi->mvdd_split_frequency) 4651 voltage->index = 0; 4652 else 4653 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4654 4655 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4656 } 4657 return 0; 4658 } 4659 4660 static int si_get_std_voltage_value(struct amdgpu_device *adev, 4661 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4662 u16 *std_voltage) 4663 { 4664 u16 v_index; 4665 bool voltage_found = false; 4666 *std_voltage = be16_to_cpu(voltage->value); 4667 4668 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4669 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4670 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4671 return -EINVAL; 4672 4673 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4674 if (be16_to_cpu(voltage->value) == 4675 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4676 voltage_found = true; 4677 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4678 *std_voltage = 4679 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4680 else 4681 *std_voltage = 4682 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4683 break; 4684 } 4685 } 4686 4687 if (!voltage_found) { 4688 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4689 if (be16_to_cpu(voltage->value) <= 4690 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4691 voltage_found = true; 4692 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4693 *std_voltage = 4694 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4695 else 4696 *std_voltage = 4697 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4698 break; 4699 } 4700 } 4701 } 4702 } else { 4703 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4704 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4705 } 4706 } 4707 4708 return 0; 4709 } 4710 4711 static int si_populate_std_voltage_value(struct amdgpu_device *adev, 4712 u16 value, u8 index, 4713 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4714 { 4715 voltage->index = index; 4716 voltage->value = cpu_to_be16(value); 4717 4718 return 0; 4719 } 4720 4721 static int si_populate_phase_shedding_value(struct amdgpu_device *adev, 4722 const struct amdgpu_phase_shedding_limits_table *limits, 4723 u16 voltage, u32 sclk, u32 mclk, 4724 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4725 { 4726 unsigned int i; 4727 4728 for (i = 0; i < limits->count; i++) { 4729 if ((voltage <= limits->entries[i].voltage) && 4730 (sclk <= limits->entries[i].sclk) && 4731 (mclk <= limits->entries[i].mclk)) 4732 break; 4733 } 4734 4735 smc_voltage->phase_settings = (u8)i; 4736 4737 return 0; 4738 } 4739 4740 static int si_init_arb_table_index(struct amdgpu_device *adev) 4741 { 4742 struct si_power_info *si_pi = si_get_pi(adev); 4743 u32 tmp; 4744 int ret; 4745 4746 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4747 &tmp, si_pi->sram_end); 4748 if (ret) 4749 return ret; 4750 4751 tmp &= 0x00FFFFFF; 4752 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4753 4754 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, 4755 tmp, si_pi->sram_end); 4756 } 4757 4758 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) 4759 { 4760 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4761 } 4762 4763 static int si_reset_to_default(struct amdgpu_device *adev) 4764 { 4765 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4766 0 : -EINVAL; 4767 } 4768 4769 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) 4770 { 4771 struct si_power_info *si_pi = si_get_pi(adev); 4772 u32 tmp; 4773 int ret; 4774 4775 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4776 &tmp, si_pi->sram_end); 4777 if (ret) 4778 return ret; 4779 4780 tmp = (tmp >> 24) & 0xff; 4781 4782 if (tmp == MC_CG_ARB_FREQ_F0) 4783 return 0; 4784 4785 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); 4786 } 4787 4788 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, 4789 u32 engine_clock) 4790 { 4791 u32 dram_rows; 4792 u32 dram_refresh_rate; 4793 u32 mc_arb_rfsh_rate; 4794 u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT; 4795 4796 if (tmp >= 4) 4797 dram_rows = 16384; 4798 else 4799 dram_rows = 1 << (tmp + 10); 4800 4801 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4802 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4803 4804 return mc_arb_rfsh_rate; 4805 } 4806 4807 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, 4808 struct rv7xx_pl *pl, 4809 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4810 { 4811 u32 dram_timing; 4812 u32 dram_timing2; 4813 u32 burst_time; 4814 int ret; 4815 4816 arb_regs->mc_arb_rfsh_rate = 4817 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); 4818 4819 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk, 4820 pl->mclk); 4821 if (ret) 4822 return ret; 4823 4824 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4825 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4826 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4827 4828 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4829 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4830 arb_regs->mc_arb_burst_time = (u8)burst_time; 4831 4832 return 0; 4833 } 4834 4835 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, 4836 struct amdgpu_ps *amdgpu_state, 4837 unsigned int first_arb_set) 4838 { 4839 struct si_power_info *si_pi = si_get_pi(adev); 4840 struct si_ps *state = si_get_ps(amdgpu_state); 4841 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4842 int i, ret = 0; 4843 4844 for (i = 0; i < state->performance_level_count; i++) { 4845 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4846 if (ret) 4847 break; 4848 ret = amdgpu_si_copy_bytes_to_smc(adev, 4849 si_pi->arb_table_start + 4850 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4851 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4852 (u8 *)&arb_regs, 4853 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4854 si_pi->sram_end); 4855 if (ret) 4856 break; 4857 } 4858 4859 return ret; 4860 } 4861 4862 static int si_program_memory_timing_parameters(struct amdgpu_device *adev, 4863 struct amdgpu_ps *amdgpu_new_state) 4864 { 4865 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state, 4866 SISLANDS_DRIVER_STATE_ARB_INDEX); 4867 } 4868 4869 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev, 4870 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4871 { 4872 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4873 struct si_power_info *si_pi = si_get_pi(adev); 4874 4875 if (pi->mvdd_control) 4876 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, 4877 si_pi->mvdd_bootup_value, voltage); 4878 4879 return 0; 4880 } 4881 4882 static int si_populate_smc_initial_state(struct amdgpu_device *adev, 4883 struct amdgpu_ps *amdgpu_initial_state, 4884 SISLANDS_SMC_STATETABLE *table) 4885 { 4886 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); 4887 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4888 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4889 struct si_power_info *si_pi = si_get_pi(adev); 4890 u32 reg; 4891 int ret; 4892 4893 table->initialState.level.mclk.vDLL_CNTL = 4894 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4895 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = 4896 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4897 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = 4898 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4899 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = 4900 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4901 table->initialState.level.mclk.vMPLL_FUNC_CNTL = 4902 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4903 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = 4904 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4905 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = 4906 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4907 table->initialState.level.mclk.vMPLL_SS = 4908 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4909 table->initialState.level.mclk.vMPLL_SS2 = 4910 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4911 4912 table->initialState.level.mclk.mclk_value = 4913 cpu_to_be32(initial_state->performance_levels[0].mclk); 4914 4915 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = 4916 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4917 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 4918 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4919 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 4920 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4921 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 4922 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4923 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = 4924 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4925 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4926 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4927 4928 table->initialState.level.sclk.sclk_value = 4929 cpu_to_be32(initial_state->performance_levels[0].sclk); 4930 4931 table->initialState.level.arbRefreshState = 4932 SISLANDS_INITIAL_STATE_ARB_INDEX; 4933 4934 table->initialState.level.ACIndex = 0; 4935 4936 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 4937 initial_state->performance_levels[0].vddc, 4938 &table->initialState.level.vddc); 4939 4940 if (!ret) { 4941 u16 std_vddc; 4942 4943 ret = si_get_std_voltage_value(adev, 4944 &table->initialState.level.vddc, 4945 &std_vddc); 4946 if (!ret) 4947 si_populate_std_voltage_value(adev, std_vddc, 4948 table->initialState.level.vddc.index, 4949 &table->initialState.level.std_vddc); 4950 } 4951 4952 if (eg_pi->vddci_control) 4953 si_populate_voltage_value(adev, 4954 &eg_pi->vddci_voltage_table, 4955 initial_state->performance_levels[0].vddci, 4956 &table->initialState.level.vddci); 4957 4958 if (si_pi->vddc_phase_shed_control) 4959 si_populate_phase_shedding_value(adev, 4960 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 4961 initial_state->performance_levels[0].vddc, 4962 initial_state->performance_levels[0].sclk, 4963 initial_state->performance_levels[0].mclk, 4964 &table->initialState.level.vddc); 4965 4966 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd); 4967 4968 reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT; 4969 table->initialState.level.aT = cpu_to_be32(reg); 4970 table->initialState.level.bSP = cpu_to_be32(pi->dsp); 4971 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; 4972 4973 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 4974 table->initialState.level.strobeMode = 4975 si_get_strobe_mode_settings(adev, 4976 initial_state->performance_levels[0].mclk); 4977 4978 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4979 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4980 else 4981 table->initialState.level.mcFlags = 0; 4982 } 4983 4984 table->initialState.levelCount = 1; 4985 4986 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4987 4988 table->initialState.level.dpm2.MaxPS = 0; 4989 table->initialState.level.dpm2.NearTDPDec = 0; 4990 table->initialState.level.dpm2.AboveSafeInc = 0; 4991 table->initialState.level.dpm2.BelowSafeInc = 0; 4992 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; 4993 4994 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | 4995 SQ_POWER_THROTTLE__MAX_POWER_MASK; 4996 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); 4997 4998 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | 4999 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | 5000 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 5001 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 5002 5003 return 0; 5004 } 5005 5006 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev, 5007 u32 sys_mask, 5008 enum si_pcie_gen asic_gen, 5009 enum si_pcie_gen default_gen) 5010 { 5011 switch (asic_gen) { 5012 case SI_PCIE_GEN1: 5013 return SI_PCIE_GEN1; 5014 case SI_PCIE_GEN2: 5015 return SI_PCIE_GEN2; 5016 case SI_PCIE_GEN3: 5017 return SI_PCIE_GEN3; 5018 default: 5019 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) && 5020 (default_gen == SI_PCIE_GEN3)) 5021 return SI_PCIE_GEN3; 5022 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) && 5023 (default_gen == SI_PCIE_GEN2)) 5024 return SI_PCIE_GEN2; 5025 else 5026 return SI_PCIE_GEN1; 5027 } 5028 return SI_PCIE_GEN1; 5029 } 5030 5031 static int si_populate_smc_acpi_state(struct amdgpu_device *adev, 5032 SISLANDS_SMC_STATETABLE *table) 5033 { 5034 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5035 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5036 struct si_power_info *si_pi = si_get_pi(adev); 5037 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5038 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5039 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5040 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5041 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5042 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5043 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5044 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5045 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5046 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5047 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5048 u32 reg; 5049 int ret; 5050 5051 table->ACPIState = table->initialState; 5052 5053 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 5054 5055 if (pi->acpi_vddc) { 5056 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5057 pi->acpi_vddc, &table->ACPIState.level.vddc); 5058 if (!ret) { 5059 u16 std_vddc; 5060 5061 ret = si_get_std_voltage_value(adev, 5062 &table->ACPIState.level.vddc, &std_vddc); 5063 if (!ret) 5064 si_populate_std_voltage_value(adev, std_vddc, 5065 table->ACPIState.level.vddc.index, 5066 &table->ACPIState.level.std_vddc); 5067 } 5068 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; 5069 5070 if (si_pi->vddc_phase_shed_control) { 5071 si_populate_phase_shedding_value(adev, 5072 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5073 pi->acpi_vddc, 5074 0, 5075 0, 5076 &table->ACPIState.level.vddc); 5077 } 5078 } else { 5079 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5080 pi->min_vddc_in_table, &table->ACPIState.level.vddc); 5081 if (!ret) { 5082 u16 std_vddc; 5083 5084 ret = si_get_std_voltage_value(adev, 5085 &table->ACPIState.level.vddc, &std_vddc); 5086 5087 if (!ret) 5088 si_populate_std_voltage_value(adev, std_vddc, 5089 table->ACPIState.level.vddc.index, 5090 &table->ACPIState.level.std_vddc); 5091 } 5092 table->ACPIState.level.gen2PCIE = 5093 (u8)si_gen_pcie_gen_support(adev, 5094 si_pi->sys_pcie_mask, 5095 si_pi->boot_pcie_gen, 5096 SI_PCIE_GEN1); 5097 5098 if (si_pi->vddc_phase_shed_control) 5099 si_populate_phase_shedding_value(adev, 5100 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5101 pi->min_vddc_in_table, 5102 0, 5103 0, 5104 &table->ACPIState.level.vddc); 5105 } 5106 5107 if (pi->acpi_vddc) { 5108 if (eg_pi->acpi_vddci) 5109 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5110 eg_pi->acpi_vddci, 5111 &table->ACPIState.level.vddci); 5112 } 5113 5114 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 5115 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5116 5117 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 5118 5119 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; 5120 spll_func_cntl_2 |= 4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT; 5121 5122 table->ACPIState.level.mclk.vDLL_CNTL = 5123 cpu_to_be32(dll_cntl); 5124 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = 5125 cpu_to_be32(mclk_pwrmgt_cntl); 5126 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = 5127 cpu_to_be32(mpll_ad_func_cntl); 5128 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = 5129 cpu_to_be32(mpll_dq_func_cntl); 5130 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = 5131 cpu_to_be32(mpll_func_cntl); 5132 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = 5133 cpu_to_be32(mpll_func_cntl_1); 5134 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = 5135 cpu_to_be32(mpll_func_cntl_2); 5136 table->ACPIState.level.mclk.vMPLL_SS = 5137 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 5138 table->ACPIState.level.mclk.vMPLL_SS2 = 5139 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 5140 5141 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = 5142 cpu_to_be32(spll_func_cntl); 5143 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 5144 cpu_to_be32(spll_func_cntl_2); 5145 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 5146 cpu_to_be32(spll_func_cntl_3); 5147 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 5148 cpu_to_be32(spll_func_cntl_4); 5149 5150 table->ACPIState.level.mclk.mclk_value = 0; 5151 table->ACPIState.level.sclk.sclk_value = 0; 5152 5153 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd); 5154 5155 if (eg_pi->dynamic_ac_timing) 5156 table->ACPIState.level.ACIndex = 0; 5157 5158 table->ACPIState.level.dpm2.MaxPS = 0; 5159 table->ACPIState.level.dpm2.NearTDPDec = 0; 5160 table->ACPIState.level.dpm2.AboveSafeInc = 0; 5161 table->ACPIState.level.dpm2.BelowSafeInc = 0; 5162 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; 5163 5164 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK; 5165 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); 5166 5167 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 5168 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 5169 5170 return 0; 5171 } 5172 5173 static int si_populate_ulv_state(struct amdgpu_device *adev, 5174 struct SISLANDS_SMC_SWSTATE_SINGLE *state) 5175 { 5176 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5177 struct si_power_info *si_pi = si_get_pi(adev); 5178 struct si_ulv_param *ulv = &si_pi->ulv; 5179 u32 sclk_in_sr = 1350; /* ??? */ 5180 int ret; 5181 5182 ret = si_convert_power_level_to_smc(adev, &ulv->pl, 5183 &state->level); 5184 if (!ret) { 5185 if (eg_pi->sclk_deep_sleep) { 5186 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5187 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5188 else 5189 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5190 } 5191 if (ulv->one_pcie_lane_in_ulv) 5192 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 5193 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 5194 state->level.ACIndex = 1; 5195 state->level.std_vddc = state->level.vddc; 5196 state->levelCount = 1; 5197 5198 state->flags |= PPSMC_SWSTATE_FLAG_DC; 5199 } 5200 5201 return ret; 5202 } 5203 5204 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) 5205 { 5206 struct si_power_info *si_pi = si_get_pi(adev); 5207 struct si_ulv_param *ulv = &si_pi->ulv; 5208 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 5209 int ret; 5210 5211 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, 5212 &arb_regs); 5213 if (ret) 5214 return ret; 5215 5216 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 5217 ulv->volt_change_delay); 5218 5219 ret = amdgpu_si_copy_bytes_to_smc(adev, 5220 si_pi->arb_table_start + 5221 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5222 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5223 (u8 *)&arb_regs, 5224 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5225 si_pi->sram_end); 5226 5227 return ret; 5228 } 5229 5230 static void si_get_mvdd_configuration(struct amdgpu_device *adev) 5231 { 5232 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5233 5234 pi->mvdd_split_frequency = 30000; 5235 } 5236 5237 static int si_init_smc_table(struct amdgpu_device *adev) 5238 { 5239 struct si_power_info *si_pi = si_get_pi(adev); 5240 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; 5241 const struct si_ulv_param *ulv = &si_pi->ulv; 5242 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 5243 int ret; 5244 u32 lane_width; 5245 u32 vr_hot_gpio; 5246 5247 si_populate_smc_voltage_tables(adev, table); 5248 5249 switch (adev->pm.int_thermal_type) { 5250 case THERMAL_TYPE_SI: 5251 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 5252 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 5253 break; 5254 case THERMAL_TYPE_NONE: 5255 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 5256 break; 5257 default: 5258 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 5259 break; 5260 } 5261 5262 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 5263 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 5264 5265 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 5266 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819)) 5267 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 5268 } 5269 5270 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 5271 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 5272 5273 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5274 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 5275 5276 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 5277 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 5278 5279 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 5280 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 5281 vr_hot_gpio = adev->pm.dpm.backbias_response_time; 5282 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 5283 vr_hot_gpio); 5284 } 5285 5286 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table); 5287 if (ret) 5288 return ret; 5289 5290 ret = si_populate_smc_acpi_state(adev, table); 5291 if (ret) 5292 return ret; 5293 5294 table->driverState.flags = table->initialState.flags; 5295 table->driverState.levelCount = table->initialState.levelCount; 5296 table->driverState.levels[0] = table->initialState.level; 5297 5298 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state, 5299 SISLANDS_INITIAL_STATE_ARB_INDEX); 5300 if (ret) 5301 return ret; 5302 5303 if (ulv->supported && ulv->pl.vddc) { 5304 ret = si_populate_ulv_state(adev, &table->ULVState); 5305 if (ret) 5306 return ret; 5307 5308 ret = si_program_ulv_memory_timing_parameters(adev); 5309 if (ret) 5310 return ret; 5311 5312 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control); 5313 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter); 5314 5315 lane_width = amdgpu_get_pcie_lanes(adev); 5316 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5317 } else { 5318 table->ULVState = table->initialState; 5319 } 5320 5321 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5322 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5323 si_pi->sram_end); 5324 } 5325 5326 static int si_calculate_sclk_params(struct amdgpu_device *adev, 5327 u32 engine_clock, 5328 SISLANDS_SMC_SCLK_VALUE *sclk) 5329 { 5330 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5331 struct si_power_info *si_pi = si_get_pi(adev); 5332 struct atom_clock_dividers dividers; 5333 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5334 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5335 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5336 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5337 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 5338 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 5339 u64 tmp; 5340 u32 reference_clock = adev->clock.spll.reference_freq; 5341 u32 reference_divider; 5342 u32 fbdiv; 5343 int ret; 5344 5345 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 5346 engine_clock, false, ÷rs); 5347 if (ret) 5348 return ret; 5349 5350 reference_divider = 1 + dividers.ref_div; 5351 5352 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 5353 do_div(tmp, reference_clock); 5354 fbdiv = (u32) tmp; 5355 5356 spll_func_cntl &= ~(CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK | CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK); 5357 spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT; 5358 spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT; 5359 5360 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; 5361 spll_func_cntl_2 |= 2 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT; 5362 5363 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK; 5364 spll_func_cntl_3 |= fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT; 5365 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK; 5366 5367 if (pi->sclk_ss) { 5368 struct amdgpu_atom_ss ss; 5369 u32 vco_freq = engine_clock * dividers.post_div; 5370 5371 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5372 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 5373 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 5374 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 5375 5376 cg_spll_spread_spectrum &= ~CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK; 5377 cg_spll_spread_spectrum |= clk_s << CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT; 5378 cg_spll_spread_spectrum |= CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK; 5379 5380 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK; 5381 cg_spll_spread_spectrum_2 |= clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT; 5382 } 5383 } 5384 5385 sclk->sclk_value = engine_clock; 5386 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 5387 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 5388 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 5389 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 5390 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 5391 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 5392 5393 return 0; 5394 } 5395 5396 static int si_populate_sclk_value(struct amdgpu_device *adev, 5397 u32 engine_clock, 5398 SISLANDS_SMC_SCLK_VALUE *sclk) 5399 { 5400 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 5401 int ret; 5402 5403 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); 5404 if (!ret) { 5405 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 5406 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 5407 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 5408 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 5409 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 5410 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 5411 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 5412 } 5413 5414 return ret; 5415 } 5416 5417 static int si_populate_mclk_value(struct amdgpu_device *adev, 5418 u32 engine_clock, 5419 u32 memory_clock, 5420 SISLANDS_SMC_MCLK_VALUE *mclk, 5421 bool strobe_mode, 5422 bool dll_state_on) 5423 { 5424 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5425 struct si_power_info *si_pi = si_get_pi(adev); 5426 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5427 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5428 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5429 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5430 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5431 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5432 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5433 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 5434 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 5435 struct atom_mpll_param mpll_param; 5436 int ret; 5437 5438 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); 5439 if (ret) 5440 return ret; 5441 5442 mpll_func_cntl &= ~BWCTRL_MASK; 5443 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 5444 5445 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 5446 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 5447 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 5448 5449 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 5450 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 5451 5452 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5453 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 5454 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 5455 YCLK_POST_DIV(mpll_param.post_div); 5456 } 5457 5458 if (pi->mclk_ss) { 5459 struct amdgpu_atom_ss ss; 5460 u32 freq_nom; 5461 u32 tmp; 5462 u32 reference_clock = adev->clock.mpll.reference_freq; 5463 5464 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5465 freq_nom = memory_clock * 4; 5466 else 5467 freq_nom = memory_clock * 2; 5468 5469 tmp = freq_nom / reference_clock; 5470 tmp = tmp * tmp; 5471 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5472 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 5473 u32 clks = reference_clock * 5 / ss.rate; 5474 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 5475 5476 mpll_ss1 &= ~CLKV_MASK; 5477 mpll_ss1 |= CLKV(clkv); 5478 5479 mpll_ss2 &= ~CLKS_MASK; 5480 mpll_ss2 |= CLKS(clks); 5481 } 5482 } 5483 5484 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 5485 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 5486 5487 if (dll_state_on) 5488 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 5489 else 5490 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5491 5492 mclk->mclk_value = cpu_to_be32(memory_clock); 5493 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 5494 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 5495 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 5496 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 5497 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 5498 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 5499 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 5500 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 5501 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 5502 5503 return 0; 5504 } 5505 5506 static void si_populate_smc_sp(struct amdgpu_device *adev, 5507 struct amdgpu_ps *amdgpu_state, 5508 SISLANDS_SMC_SWSTATE *smc_state) 5509 { 5510 struct si_ps *ps = si_get_ps(amdgpu_state); 5511 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5512 int i; 5513 5514 for (i = 0; i < ps->performance_level_count - 1; i++) 5515 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5516 5517 smc_state->levels[ps->performance_level_count - 1].bSP = 5518 cpu_to_be32(pi->psp); 5519 } 5520 5521 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 5522 struct rv7xx_pl *pl, 5523 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5524 { 5525 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5526 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5527 struct si_power_info *si_pi = si_get_pi(adev); 5528 int ret; 5529 bool dll_state_on; 5530 u16 std_vddc; 5531 5532 if (eg_pi->pcie_performance_request && 5533 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID)) 5534 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5535 else 5536 level->gen2PCIE = (u8)pl->pcie_gen; 5537 5538 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); 5539 if (ret) 5540 return ret; 5541 5542 level->mcFlags = 0; 5543 5544 if (pi->mclk_stutter_mode_threshold && 5545 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5546 !eg_pi->uvd_enabled && 5547 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) && 5548 (adev->pm.dpm.new_active_crtc_count <= 2)) { 5549 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5550 } 5551 5552 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5553 if (pl->mclk > pi->mclk_edc_enable_threshold) 5554 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5555 5556 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5557 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5558 5559 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); 5560 5561 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5562 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5563 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5564 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5565 else 5566 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5567 } else { 5568 dll_state_on = false; 5569 } 5570 } else { 5571 level->strobeMode = si_get_strobe_mode_settings(adev, 5572 pl->mclk); 5573 5574 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5575 } 5576 5577 ret = si_populate_mclk_value(adev, 5578 pl->sclk, 5579 pl->mclk, 5580 &level->mclk, 5581 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5582 if (ret) 5583 return ret; 5584 5585 ret = si_populate_voltage_value(adev, 5586 &eg_pi->vddc_voltage_table, 5587 pl->vddc, &level->vddc); 5588 if (ret) 5589 return ret; 5590 5591 5592 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); 5593 if (ret) 5594 return ret; 5595 5596 ret = si_populate_std_voltage_value(adev, std_vddc, 5597 level->vddc.index, &level->std_vddc); 5598 if (ret) 5599 return ret; 5600 5601 if (eg_pi->vddci_control) { 5602 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5603 pl->vddci, &level->vddci); 5604 if (ret) 5605 return ret; 5606 } 5607 5608 if (si_pi->vddc_phase_shed_control) { 5609 ret = si_populate_phase_shedding_value(adev, 5610 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5611 pl->vddc, 5612 pl->sclk, 5613 pl->mclk, 5614 &level->vddc); 5615 if (ret) 5616 return ret; 5617 } 5618 5619 level->MaxPoweredUpCU = si_pi->max_cu; 5620 5621 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); 5622 5623 return ret; 5624 } 5625 5626 static int si_populate_smc_t(struct amdgpu_device *adev, 5627 struct amdgpu_ps *amdgpu_state, 5628 SISLANDS_SMC_SWSTATE *smc_state) 5629 { 5630 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5631 struct si_ps *state = si_get_ps(amdgpu_state); 5632 u32 a_t; 5633 u32 t_l, t_h; 5634 u32 high_bsp; 5635 int i, ret; 5636 5637 if (state->performance_level_count >= 9) 5638 return -EINVAL; 5639 5640 if (state->performance_level_count < 2) { 5641 a_t = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT; 5642 smc_state->levels[0].aT = cpu_to_be32(a_t); 5643 return 0; 5644 } 5645 5646 smc_state->levels[0].aT = cpu_to_be32(0); 5647 5648 for (i = 0; i <= state->performance_level_count - 2; i++) { 5649 ret = r600_calculate_at( 5650 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5651 100 * R600_AH_DFLT, 5652 state->performance_levels[i + 1].sclk, 5653 state->performance_levels[i].sclk, 5654 &t_l, 5655 &t_h); 5656 5657 if (ret) { 5658 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5659 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5660 } 5661 5662 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_AT__CG_R_MASK; 5663 a_t |= (t_l * pi->bsp / 20000) << CG_AT__CG_R__SHIFT; 5664 smc_state->levels[i].aT = cpu_to_be32(a_t); 5665 5666 high_bsp = (i == state->performance_level_count - 2) ? 5667 pi->pbsp : pi->bsp; 5668 a_t = (0xffff) << CG_AT__CG_R__SHIFT | (t_h * high_bsp / 20000) << CG_AT__CG_L__SHIFT; 5669 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5670 } 5671 5672 return 0; 5673 } 5674 5675 static int si_disable_ulv(struct amdgpu_device *adev) 5676 { 5677 PPSMC_Result r; 5678 5679 r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV); 5680 return (r == PPSMC_Result_OK) ? 0 : -EINVAL; 5681 } 5682 5683 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, 5684 struct amdgpu_ps *amdgpu_state) 5685 { 5686 const struct si_power_info *si_pi = si_get_pi(adev); 5687 const struct si_ulv_param *ulv = &si_pi->ulv; 5688 const struct si_ps *state = si_get_ps(amdgpu_state); 5689 int i; 5690 5691 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5692 return false; 5693 5694 /* XXX validate against display requirements! */ 5695 5696 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5697 if (adev->clock.current_dispclk <= 5698 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5699 if (ulv->pl.vddc < 5700 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5701 return false; 5702 } 5703 } 5704 5705 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) 5706 return false; 5707 5708 return true; 5709 } 5710 5711 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, 5712 struct amdgpu_ps *amdgpu_new_state) 5713 { 5714 const struct si_power_info *si_pi = si_get_pi(adev); 5715 const struct si_ulv_param *ulv = &si_pi->ulv; 5716 5717 if (ulv->supported) { 5718 if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) 5719 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5720 0 : -EINVAL; 5721 } 5722 return 0; 5723 } 5724 5725 static int si_convert_power_state_to_smc(struct amdgpu_device *adev, 5726 struct amdgpu_ps *amdgpu_state, 5727 SISLANDS_SMC_SWSTATE *smc_state) 5728 { 5729 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5730 struct ni_power_info *ni_pi = ni_get_pi(adev); 5731 struct si_power_info *si_pi = si_get_pi(adev); 5732 struct si_ps *state = si_get_ps(amdgpu_state); 5733 int i, ret; 5734 u32 threshold; 5735 u32 sclk_in_sr = 1350; /* ??? */ 5736 5737 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5738 return -EINVAL; 5739 5740 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5741 5742 if (amdgpu_state->vclk && amdgpu_state->dclk) { 5743 eg_pi->uvd_enabled = true; 5744 if (eg_pi->smu_uvd_hs) 5745 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5746 } else { 5747 eg_pi->uvd_enabled = false; 5748 } 5749 5750 if (state->dc_compatible) 5751 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5752 5753 smc_state->levelCount = 0; 5754 for (i = 0; i < state->performance_level_count; i++) { 5755 if (eg_pi->sclk_deep_sleep) { 5756 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5757 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5758 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5759 else 5760 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5761 } 5762 } 5763 5764 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], 5765 &smc_state->levels[i]); 5766 smc_state->levels[i].arbRefreshState = 5767 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5768 5769 if (ret) 5770 return ret; 5771 5772 if (ni_pi->enable_power_containment) 5773 smc_state->levels[i].displayWatermark = 5774 (state->performance_levels[i].sclk < threshold) ? 5775 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5776 else 5777 smc_state->levels[i].displayWatermark = (i < 2) ? 5778 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5779 5780 if (eg_pi->dynamic_ac_timing) 5781 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5782 else 5783 smc_state->levels[i].ACIndex = 0; 5784 5785 smc_state->levelCount++; 5786 } 5787 5788 si_write_smc_soft_register(adev, 5789 SI_SMC_SOFT_REGISTER_watermark_threshold, 5790 threshold / 512); 5791 5792 si_populate_smc_sp(adev, amdgpu_state, smc_state); 5793 5794 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state); 5795 if (ret) 5796 ni_pi->enable_power_containment = false; 5797 5798 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state); 5799 if (ret) 5800 ni_pi->enable_sq_ramping = false; 5801 5802 return si_populate_smc_t(adev, amdgpu_state, smc_state); 5803 } 5804 5805 static int si_upload_sw_state(struct amdgpu_device *adev, 5806 struct amdgpu_ps *amdgpu_new_state) 5807 { 5808 struct si_power_info *si_pi = si_get_pi(adev); 5809 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 5810 int ret; 5811 u32 address = si_pi->state_table_start + 5812 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5813 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5814 size_t state_size = struct_size(smc_state, levels, 5815 new_state->performance_level_count); 5816 memset(smc_state, 0, state_size); 5817 5818 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); 5819 if (ret) 5820 return ret; 5821 5822 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5823 state_size, si_pi->sram_end); 5824 } 5825 5826 static int si_upload_ulv_state(struct amdgpu_device *adev) 5827 { 5828 struct si_power_info *si_pi = si_get_pi(adev); 5829 struct si_ulv_param *ulv = &si_pi->ulv; 5830 int ret = 0; 5831 5832 if (ulv->supported && ulv->pl.vddc) { 5833 u32 address = si_pi->state_table_start + 5834 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5835 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; 5836 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE); 5837 5838 memset(smc_state, 0, state_size); 5839 5840 ret = si_populate_ulv_state(adev, smc_state); 5841 if (!ret) 5842 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5843 state_size, si_pi->sram_end); 5844 } 5845 5846 return ret; 5847 } 5848 5849 static int si_upload_smc_data(struct amdgpu_device *adev) 5850 { 5851 struct amdgpu_crtc *amdgpu_crtc = NULL; 5852 int i; 5853 u32 crtc_index = 0; 5854 u32 mclk_change_block_cp_min = 0; 5855 u32 mclk_change_block_cp_max = 0; 5856 5857 for (i = 0; i < adev->mode_info.num_crtc; i++) { 5858 if (adev->pm.dpm.new_active_crtcs & (1 << i)) { 5859 amdgpu_crtc = adev->mode_info.crtcs[i]; 5860 break; 5861 } 5862 } 5863 5864 /* When a display is plugged in, program these so that the SMC 5865 * performs MCLK switching when it doesn't cause flickering. 5866 * When no display is plugged in, there is no need to restrict 5867 * MCLK switching, so program them to zero. 5868 */ 5869 if (adev->pm.dpm.new_active_crtc_count && amdgpu_crtc) { 5870 crtc_index = amdgpu_crtc->crtc_id; 5871 5872 if (amdgpu_crtc->line_time) { 5873 mclk_change_block_cp_min = 200 / amdgpu_crtc->line_time; 5874 mclk_change_block_cp_max = 100 / amdgpu_crtc->line_time; 5875 } 5876 } 5877 5878 si_write_smc_soft_register(adev, 5879 SI_SMC_SOFT_REGISTER_crtc_index, 5880 crtc_index); 5881 5882 si_write_smc_soft_register(adev, 5883 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5884 mclk_change_block_cp_min); 5885 5886 si_write_smc_soft_register(adev, 5887 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5888 mclk_change_block_cp_max); 5889 5890 return 0; 5891 } 5892 5893 static int si_set_mc_special_registers(struct amdgpu_device *adev, 5894 struct si_mc_reg_table *table) 5895 { 5896 u8 i, j, k; 5897 u32 temp_reg; 5898 5899 for (i = 0, j = table->last; i < table->last; i++) { 5900 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5901 return -EINVAL; 5902 switch (table->mc_reg_address[i].s1) { 5903 case MC_SEQ_MISC1: 5904 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5905 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; 5906 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; 5907 for (k = 0; k < table->num_entries; k++) 5908 table->mc_reg_table_entry[k].mc_data[j] = 5909 ((temp_reg & 0xffff0000)) | 5910 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5911 j++; 5912 5913 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5914 return -EINVAL; 5915 temp_reg = RREG32(MC_PMG_CMD_MRS); 5916 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; 5917 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; 5918 for (k = 0; k < table->num_entries; k++) { 5919 table->mc_reg_table_entry[k].mc_data[j] = 5920 (temp_reg & 0xffff0000) | 5921 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5922 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) 5923 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5924 } 5925 j++; 5926 5927 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { 5928 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5929 return -EINVAL; 5930 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; 5931 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; 5932 for (k = 0; k < table->num_entries; k++) 5933 table->mc_reg_table_entry[k].mc_data[j] = 5934 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5935 j++; 5936 } 5937 break; 5938 case MC_SEQ_RESERVE_M: 5939 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5940 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; 5941 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; 5942 for(k = 0; k < table->num_entries; k++) 5943 table->mc_reg_table_entry[k].mc_data[j] = 5944 (temp_reg & 0xffff0000) | 5945 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5946 j++; 5947 break; 5948 default: 5949 break; 5950 } 5951 } 5952 5953 table->last = j; 5954 5955 return 0; 5956 } 5957 5958 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5959 { 5960 bool result = true; 5961 switch (in_reg) { 5962 case MC_SEQ_RAS_TIMING: 5963 *out_reg = MC_SEQ_RAS_TIMING_LP; 5964 break; 5965 case MC_SEQ_CAS_TIMING: 5966 *out_reg = MC_SEQ_CAS_TIMING_LP; 5967 break; 5968 case MC_SEQ_MISC_TIMING: 5969 *out_reg = MC_SEQ_MISC_TIMING_LP; 5970 break; 5971 case MC_SEQ_MISC_TIMING2: 5972 *out_reg = MC_SEQ_MISC_TIMING2_LP; 5973 break; 5974 case MC_SEQ_RD_CTL_D0: 5975 *out_reg = MC_SEQ_RD_CTL_D0_LP; 5976 break; 5977 case MC_SEQ_RD_CTL_D1: 5978 *out_reg = MC_SEQ_RD_CTL_D1_LP; 5979 break; 5980 case MC_SEQ_WR_CTL_D0: 5981 *out_reg = MC_SEQ_WR_CTL_D0_LP; 5982 break; 5983 case MC_SEQ_WR_CTL_D1: 5984 *out_reg = MC_SEQ_WR_CTL_D1_LP; 5985 break; 5986 case MC_PMG_CMD_EMRS: 5987 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP; 5988 break; 5989 case MC_PMG_CMD_MRS: 5990 *out_reg = MC_SEQ_PMG_CMD_MRS_LP; 5991 break; 5992 case MC_PMG_CMD_MRS1: 5993 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP; 5994 break; 5995 case MC_SEQ_PMG_TIMING: 5996 *out_reg = MC_SEQ_PMG_TIMING_LP; 5997 break; 5998 case MC_PMG_CMD_MRS2: 5999 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP; 6000 break; 6001 case MC_SEQ_WR_CTL_2: 6002 *out_reg = MC_SEQ_WR_CTL_2_LP; 6003 break; 6004 default: 6005 result = false; 6006 break; 6007 } 6008 6009 return result; 6010 } 6011 6012 static void si_set_valid_flag(struct si_mc_reg_table *table) 6013 { 6014 u8 i, j; 6015 6016 for (i = 0; i < table->last; i++) { 6017 for (j = 1; j < table->num_entries; j++) { 6018 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 6019 table->valid_flag |= 1 << i; 6020 break; 6021 } 6022 } 6023 } 6024 } 6025 6026 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 6027 { 6028 u32 i; 6029 u16 address; 6030 6031 for (i = 0; i < table->last; i++) 6032 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 6033 address : table->mc_reg_address[i].s1; 6034 6035 } 6036 6037 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 6038 struct si_mc_reg_table *si_table) 6039 { 6040 u8 i, j; 6041 6042 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6043 return -EINVAL; 6044 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 6045 return -EINVAL; 6046 6047 for (i = 0; i < table->last; i++) 6048 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 6049 si_table->last = table->last; 6050 6051 for (i = 0; i < table->num_entries; i++) { 6052 si_table->mc_reg_table_entry[i].mclk_max = 6053 table->mc_reg_table_entry[i].mclk_max; 6054 for (j = 0; j < table->last; j++) { 6055 si_table->mc_reg_table_entry[i].mc_data[j] = 6056 table->mc_reg_table_entry[i].mc_data[j]; 6057 } 6058 } 6059 si_table->num_entries = table->num_entries; 6060 6061 return 0; 6062 } 6063 6064 static int si_initialize_mc_reg_table(struct amdgpu_device *adev) 6065 { 6066 struct si_power_info *si_pi = si_get_pi(adev); 6067 struct atom_mc_reg_table *table; 6068 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 6069 u8 module_index = rv770_get_memory_module_index(adev); 6070 int ret; 6071 6072 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 6073 if (!table) 6074 return -ENOMEM; 6075 6076 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 6077 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 6078 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 6079 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 6080 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 6081 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 6082 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 6083 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 6084 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 6085 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 6086 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 6087 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 6088 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 6089 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 6090 6091 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); 6092 if (ret) 6093 goto init_mc_done; 6094 6095 ret = si_copy_vbios_mc_reg_table(table, si_table); 6096 if (ret) 6097 goto init_mc_done; 6098 6099 si_set_s0_mc_reg_index(si_table); 6100 6101 ret = si_set_mc_special_registers(adev, si_table); 6102 if (ret) 6103 goto init_mc_done; 6104 6105 si_set_valid_flag(si_table); 6106 6107 init_mc_done: 6108 kfree(table); 6109 6110 return ret; 6111 6112 } 6113 6114 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev, 6115 SMC_SIslands_MCRegisters *mc_reg_table) 6116 { 6117 struct si_power_info *si_pi = si_get_pi(adev); 6118 u32 i, j; 6119 6120 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 6121 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 6122 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6123 break; 6124 mc_reg_table->address[i].s0 = 6125 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 6126 mc_reg_table->address[i].s1 = 6127 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 6128 i++; 6129 } 6130 } 6131 mc_reg_table->last = (u8)i; 6132 } 6133 6134 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 6135 SMC_SIslands_MCRegisterSet *data, 6136 u32 num_entries, u32 valid_flag) 6137 { 6138 u32 i, j; 6139 6140 for(i = 0, j = 0; j < num_entries; j++) { 6141 if (valid_flag & (1 << j)) { 6142 data->value[i] = cpu_to_be32(entry->mc_data[j]); 6143 i++; 6144 } 6145 } 6146 } 6147 6148 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, 6149 struct rv7xx_pl *pl, 6150 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 6151 { 6152 struct si_power_info *si_pi = si_get_pi(adev); 6153 u32 i = 0; 6154 6155 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 6156 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 6157 break; 6158 } 6159 6160 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 6161 --i; 6162 6163 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 6164 mc_reg_table_data, si_pi->mc_reg_table.last, 6165 si_pi->mc_reg_table.valid_flag); 6166 } 6167 6168 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, 6169 struct amdgpu_ps *amdgpu_state, 6170 SMC_SIslands_MCRegisters *mc_reg_table) 6171 { 6172 struct si_ps *state = si_get_ps(amdgpu_state); 6173 int i; 6174 6175 for (i = 0; i < state->performance_level_count; i++) { 6176 si_convert_mc_reg_table_entry_to_smc(adev, 6177 &state->performance_levels[i], 6178 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 6179 } 6180 } 6181 6182 static int si_populate_mc_reg_table(struct amdgpu_device *adev, 6183 struct amdgpu_ps *amdgpu_boot_state) 6184 { 6185 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state); 6186 struct si_power_info *si_pi = si_get_pi(adev); 6187 struct si_ulv_param *ulv = &si_pi->ulv; 6188 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6189 6190 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6191 6192 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1); 6193 6194 si_populate_mc_reg_addresses(adev, smc_mc_reg_table); 6195 6196 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], 6197 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 6198 6199 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6200 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 6201 si_pi->mc_reg_table.last, 6202 si_pi->mc_reg_table.valid_flag); 6203 6204 if (ulv->supported && ulv->pl.vddc != 0) 6205 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, 6206 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 6207 else 6208 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6209 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 6210 si_pi->mc_reg_table.last, 6211 si_pi->mc_reg_table.valid_flag); 6212 6213 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); 6214 6215 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6216 (u8 *)smc_mc_reg_table, 6217 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6218 } 6219 6220 static int si_upload_mc_reg_table(struct amdgpu_device *adev, 6221 struct amdgpu_ps *amdgpu_new_state) 6222 { 6223 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 6224 struct si_power_info *si_pi = si_get_pi(adev); 6225 u32 address = si_pi->mc_reg_table_start + 6226 offsetof(SMC_SIslands_MCRegisters, 6227 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 6228 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6229 6230 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6231 6232 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); 6233 6234 return amdgpu_si_copy_bytes_to_smc(adev, address, 6235 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6236 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6237 si_pi->sram_end); 6238 } 6239 6240 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) 6241 { 6242 if (enable) 6243 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK); 6244 else 6245 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK); 6246 } 6247 6248 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev, 6249 struct amdgpu_ps *amdgpu_state) 6250 { 6251 struct si_ps *state = si_get_ps(amdgpu_state); 6252 int i; 6253 u16 pcie_speed, max_speed = 0; 6254 6255 for (i = 0; i < state->performance_level_count; i++) { 6256 pcie_speed = state->performance_levels[i].pcie_gen; 6257 if (max_speed < pcie_speed) 6258 max_speed = pcie_speed; 6259 } 6260 return max_speed; 6261 } 6262 6263 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev) 6264 { 6265 u32 speed_cntl; 6266 6267 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL) & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK; 6268 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 6269 6270 return (u16)speed_cntl; 6271 } 6272 6273 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, 6274 struct amdgpu_ps *amdgpu_new_state, 6275 struct amdgpu_ps *amdgpu_current_state) 6276 { 6277 struct si_power_info *si_pi = si_get_pi(adev); 6278 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6279 enum si_pcie_gen current_link_speed; 6280 6281 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID) 6282 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state); 6283 else 6284 current_link_speed = si_pi->force_pcie_gen; 6285 6286 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 6287 si_pi->pspp_notify_required = false; 6288 if (target_link_speed > current_link_speed) { 6289 switch (target_link_speed) { 6290 #if defined(CONFIG_ACPI) 6291 case SI_PCIE_GEN3: 6292 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 6293 break; 6294 si_pi->force_pcie_gen = SI_PCIE_GEN2; 6295 if (current_link_speed == SI_PCIE_GEN2) 6296 break; 6297 fallthrough; 6298 case SI_PCIE_GEN2: 6299 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 6300 break; 6301 fallthrough; 6302 #endif 6303 default: 6304 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); 6305 break; 6306 } 6307 } else { 6308 if (target_link_speed < current_link_speed) 6309 si_pi->pspp_notify_required = true; 6310 } 6311 } 6312 6313 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, 6314 struct amdgpu_ps *amdgpu_new_state, 6315 struct amdgpu_ps *amdgpu_current_state) 6316 { 6317 struct si_power_info *si_pi = si_get_pi(adev); 6318 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6319 u8 request; 6320 6321 if (si_pi->pspp_notify_required) { 6322 if (target_link_speed == SI_PCIE_GEN3) 6323 request = PCIE_PERF_REQ_PECI_GEN3; 6324 else if (target_link_speed == SI_PCIE_GEN2) 6325 request = PCIE_PERF_REQ_PECI_GEN2; 6326 else 6327 request = PCIE_PERF_REQ_PECI_GEN1; 6328 6329 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 6330 (si_get_current_pcie_speed(adev) > 0)) 6331 return; 6332 6333 #if defined(CONFIG_ACPI) 6334 amdgpu_acpi_pcie_performance_request(adev, request, false); 6335 #endif 6336 } 6337 } 6338 6339 #if 0 6340 static int si_ds_request(struct amdgpu_device *adev, 6341 bool ds_status_on, u32 count_write) 6342 { 6343 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6344 6345 if (eg_pi->sclk_deep_sleep) { 6346 if (ds_status_on) 6347 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6348 PPSMC_Result_OK) ? 6349 0 : -EINVAL; 6350 else 6351 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6352 PPSMC_Result_OK) ? 0 : -EINVAL; 6353 } 6354 return 0; 6355 } 6356 #endif 6357 6358 static void si_set_max_cu_value(struct amdgpu_device *adev) 6359 { 6360 struct si_power_info *si_pi = si_get_pi(adev); 6361 6362 if (adev->asic_type == CHIP_VERDE) { 6363 switch (adev->pdev->device) { 6364 case 0x6820: 6365 case 0x6825: 6366 case 0x6821: 6367 case 0x6823: 6368 case 0x6827: 6369 si_pi->max_cu = 10; 6370 break; 6371 case 0x682D: 6372 case 0x6824: 6373 case 0x682F: 6374 case 0x6826: 6375 si_pi->max_cu = 8; 6376 break; 6377 case 0x6828: 6378 case 0x6830: 6379 case 0x6831: 6380 case 0x6838: 6381 case 0x6839: 6382 case 0x683D: 6383 si_pi->max_cu = 10; 6384 break; 6385 case 0x683B: 6386 case 0x683F: 6387 case 0x6829: 6388 si_pi->max_cu = 8; 6389 break; 6390 default: 6391 si_pi->max_cu = 0; 6392 break; 6393 } 6394 } else { 6395 si_pi->max_cu = 0; 6396 } 6397 } 6398 6399 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, 6400 struct amdgpu_clock_voltage_dependency_table *table) 6401 { 6402 u32 i; 6403 int j; 6404 u16 leakage_voltage; 6405 6406 if (table) { 6407 for (i = 0; i < table->count; i++) { 6408 switch (si_get_leakage_voltage_from_leakage_index(adev, 6409 table->entries[i].v, 6410 &leakage_voltage)) { 6411 case 0: 6412 table->entries[i].v = leakage_voltage; 6413 break; 6414 case -EAGAIN: 6415 return -EINVAL; 6416 case -EINVAL: 6417 default: 6418 break; 6419 } 6420 } 6421 6422 for (j = (table->count - 2); j >= 0; j--) { 6423 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 6424 table->entries[j].v : table->entries[j + 1].v; 6425 } 6426 } 6427 return 0; 6428 } 6429 6430 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) 6431 { 6432 int ret = 0; 6433 6434 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6435 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 6436 if (ret) 6437 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n"); 6438 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6439 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 6440 if (ret) 6441 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n"); 6442 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6443 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 6444 if (ret) 6445 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n"); 6446 return ret; 6447 } 6448 6449 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, 6450 struct amdgpu_ps *amdgpu_new_state, 6451 struct amdgpu_ps *amdgpu_current_state) 6452 { 6453 u32 lane_width; 6454 u32 new_lane_width = 6455 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6456 u32 current_lane_width = 6457 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6458 6459 if (new_lane_width != current_lane_width) { 6460 amdgpu_set_pcie_lanes(adev, new_lane_width); 6461 lane_width = amdgpu_get_pcie_lanes(adev); 6462 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 6463 } 6464 } 6465 6466 static void si_dpm_setup_asic(struct amdgpu_device *adev) 6467 { 6468 si_read_clock_registers(adev); 6469 si_enable_acpi_power_management(adev); 6470 } 6471 6472 static int si_thermal_enable_alert(struct amdgpu_device *adev, 6473 bool enable) 6474 { 6475 u32 thermal_int = RREG32(mmCG_THERMAL_INT); 6476 6477 if (enable) { 6478 PPSMC_Result result; 6479 6480 thermal_int &= ~(CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK); 6481 WREG32(mmCG_THERMAL_INT, thermal_int); 6482 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6483 if (result != PPSMC_Result_OK) { 6484 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6485 return -EINVAL; 6486 } 6487 } else { 6488 thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 6489 WREG32(mmCG_THERMAL_INT, thermal_int); 6490 } 6491 6492 return 0; 6493 } 6494 6495 static int si_thermal_set_temperature_range(struct amdgpu_device *adev, 6496 int min_temp, int max_temp) 6497 { 6498 int low_temp = 0 * 1000; 6499 int high_temp = 255 * 1000; 6500 6501 if (low_temp < min_temp) 6502 low_temp = min_temp; 6503 if (high_temp > max_temp) 6504 high_temp = max_temp; 6505 if (high_temp < low_temp) { 6506 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6507 return -EINVAL; 6508 } 6509 6510 WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK); 6511 WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK); 6512 WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK); 6513 6514 adev->pm.dpm.thermal.min_temp = low_temp; 6515 adev->pm.dpm.thermal.max_temp = high_temp; 6516 6517 return 0; 6518 } 6519 6520 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) 6521 { 6522 struct si_power_info *si_pi = si_get_pi(adev); 6523 u32 tmp; 6524 6525 if (si_pi->fan_ctrl_is_in_default_mode) { 6526 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6527 si_pi->fan_ctrl_default_mode = tmp; 6528 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT; 6529 si_pi->t_min = tmp; 6530 si_pi->fan_ctrl_is_in_default_mode = false; 6531 } 6532 6533 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; 6534 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT; 6535 WREG32(mmCG_FDO_CTRL2, tmp); 6536 6537 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6538 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6539 WREG32(mmCG_FDO_CTRL2, tmp); 6540 } 6541 6542 static int si_thermal_setup_fan_table(struct amdgpu_device *adev) 6543 { 6544 struct si_power_info *si_pi = si_get_pi(adev); 6545 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6546 u32 duty100; 6547 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6548 u16 fdo_min, slope1, slope2; 6549 u32 reference_clock, tmp; 6550 int ret; 6551 u64 tmp64; 6552 6553 if (!si_pi->fan_table_start) { 6554 adev->pm.dpm.fan.ucode_fan_control = false; 6555 return 0; 6556 } 6557 6558 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6559 6560 if (duty100 == 0) { 6561 adev->pm.dpm.fan.ucode_fan_control = false; 6562 return 0; 6563 } 6564 6565 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; 6566 do_div(tmp64, 10000); 6567 fdo_min = (u16)tmp64; 6568 6569 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; 6570 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; 6571 6572 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; 6573 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; 6574 6575 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6576 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6577 6578 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); 6579 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); 6580 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); 6581 fan_table.slope1 = cpu_to_be16(slope1); 6582 fan_table.slope2 = cpu_to_be16(slope2); 6583 fan_table.fdo_min = cpu_to_be16(fdo_min); 6584 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); 6585 fan_table.hys_up = cpu_to_be16(1); 6586 fan_table.hys_slope = cpu_to_be16(1); 6587 fan_table.temp_resp_lim = cpu_to_be16(5); 6588 reference_clock = amdgpu_asic_get_xclk(adev); 6589 6590 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * 6591 reference_clock) / 1600); 6592 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6593 6594 tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT; 6595 fan_table.temp_src = (uint8_t)tmp; 6596 6597 ret = amdgpu_si_copy_bytes_to_smc(adev, 6598 si_pi->fan_table_start, 6599 (u8 *)(&fan_table), 6600 sizeof(fan_table), 6601 si_pi->sram_end); 6602 6603 if (ret) { 6604 DRM_ERROR("Failed to load fan table to the SMC."); 6605 adev->pm.dpm.fan.ucode_fan_control = false; 6606 } 6607 6608 return ret; 6609 } 6610 6611 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) 6612 { 6613 struct si_power_info *si_pi = si_get_pi(adev); 6614 PPSMC_Result ret; 6615 6616 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6617 if (ret == PPSMC_Result_OK) { 6618 si_pi->fan_is_controlled_by_smc = true; 6619 return 0; 6620 } else { 6621 return -EINVAL; 6622 } 6623 } 6624 6625 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) 6626 { 6627 struct si_power_info *si_pi = si_get_pi(adev); 6628 PPSMC_Result ret; 6629 6630 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6631 6632 if (ret == PPSMC_Result_OK) { 6633 si_pi->fan_is_controlled_by_smc = false; 6634 return 0; 6635 } else { 6636 return -EINVAL; 6637 } 6638 } 6639 6640 static int si_dpm_get_fan_speed_pwm(void *handle, 6641 u32 *speed) 6642 { 6643 u32 duty, duty100; 6644 u64 tmp64; 6645 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6646 6647 if (!speed) 6648 return -EINVAL; 6649 6650 if (adev->pm.no_fan) 6651 return -ENOENT; 6652 6653 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6654 duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT; 6655 6656 if (duty100 == 0) 6657 return -EINVAL; 6658 6659 tmp64 = (u64)duty * 255; 6660 do_div(tmp64, duty100); 6661 *speed = min_t(u32, tmp64, 255); 6662 6663 return 0; 6664 } 6665 6666 static int si_dpm_set_fan_speed_pwm(void *handle, 6667 u32 speed) 6668 { 6669 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6670 struct si_power_info *si_pi = si_get_pi(adev); 6671 u32 tmp; 6672 u32 duty, duty100; 6673 u64 tmp64; 6674 6675 if (adev->pm.no_fan) 6676 return -ENOENT; 6677 6678 if (si_pi->fan_is_controlled_by_smc) 6679 return -EINVAL; 6680 6681 if (speed > 255) 6682 return -EINVAL; 6683 6684 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6685 6686 if (duty100 == 0) 6687 return -EINVAL; 6688 6689 tmp64 = (u64)speed * duty100; 6690 do_div(tmp64, 255); 6691 duty = (u32)tmp64; 6692 6693 tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK; 6694 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT; 6695 WREG32(mmCG_FDO_CTRL0, tmp); 6696 6697 return 0; 6698 } 6699 6700 static int si_dpm_set_fan_control_mode(void *handle, u32 mode) 6701 { 6702 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6703 6704 if (mode == U32_MAX) 6705 return -EINVAL; 6706 6707 if (mode) { 6708 /* stop auto-manage */ 6709 if (adev->pm.dpm.fan.ucode_fan_control) 6710 si_fan_ctrl_stop_smc_fan_control(adev); 6711 si_fan_ctrl_set_static_mode(adev, mode); 6712 } else { 6713 /* restart auto-manage */ 6714 if (adev->pm.dpm.fan.ucode_fan_control) 6715 si_thermal_start_smc_fan_control(adev); 6716 else 6717 si_fan_ctrl_set_default_mode(adev); 6718 } 6719 6720 return 0; 6721 } 6722 6723 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode) 6724 { 6725 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6726 struct si_power_info *si_pi = si_get_pi(adev); 6727 u32 tmp; 6728 6729 if (!fan_mode) 6730 return -EINVAL; 6731 6732 if (si_pi->fan_is_controlled_by_smc) 6733 return 0; 6734 6735 tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6736 *fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT); 6737 6738 return 0; 6739 } 6740 6741 #if 0 6742 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, 6743 u32 *speed) 6744 { 6745 u32 tach_period; 6746 u32 xclk = amdgpu_asic_get_xclk(adev); 6747 6748 if (adev->pm.no_fan) 6749 return -ENOENT; 6750 6751 if (adev->pm.fan_pulses_per_revolution == 0) 6752 return -ENOENT; 6753 6754 tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT; 6755 if (tach_period == 0) 6756 return -ENOENT; 6757 6758 *speed = 60 * xclk * 10000 / tach_period; 6759 6760 return 0; 6761 } 6762 6763 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, 6764 u32 speed) 6765 { 6766 u32 tach_period, tmp; 6767 u32 xclk = amdgpu_asic_get_xclk(adev); 6768 6769 if (adev->pm.no_fan) 6770 return -ENOENT; 6771 6772 if (adev->pm.fan_pulses_per_revolution == 0) 6773 return -ENOENT; 6774 6775 if ((speed < adev->pm.fan_min_rpm) || 6776 (speed > adev->pm.fan_max_rpm)) 6777 return -EINVAL; 6778 6779 if (adev->pm.dpm.fan.ucode_fan_control) 6780 si_fan_ctrl_stop_smc_fan_control(adev); 6781 6782 tach_period = 60 * xclk * 10000 / (8 * speed); 6783 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK; 6784 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT; 6785 WREG32(mmCG_TACH_CTRL, tmp); 6786 6787 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); 6788 6789 return 0; 6790 } 6791 #endif 6792 6793 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) 6794 { 6795 struct si_power_info *si_pi = si_get_pi(adev); 6796 u32 tmp; 6797 6798 if (!si_pi->fan_ctrl_is_in_default_mode) { 6799 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6800 tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6801 WREG32(mmCG_FDO_CTRL2, tmp); 6802 6803 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; 6804 tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT; 6805 WREG32(mmCG_FDO_CTRL2, tmp); 6806 si_pi->fan_ctrl_is_in_default_mode = true; 6807 } 6808 } 6809 6810 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev) 6811 { 6812 if (adev->pm.dpm.fan.ucode_fan_control) { 6813 si_fan_ctrl_start_smc_fan_control(adev); 6814 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); 6815 } 6816 } 6817 6818 static void si_thermal_initialize(struct amdgpu_device *adev) 6819 { 6820 u32 tmp; 6821 6822 if (adev->pm.fan_pulses_per_revolution) { 6823 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK; 6824 tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT; 6825 WREG32(mmCG_TACH_CTRL, tmp); 6826 } 6827 6828 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK; 6829 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT; 6830 WREG32(mmCG_FDO_CTRL2, tmp); 6831 } 6832 6833 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev) 6834 { 6835 int ret; 6836 6837 si_thermal_initialize(adev); 6838 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6839 if (ret) 6840 return ret; 6841 ret = si_thermal_enable_alert(adev, true); 6842 if (ret) 6843 return ret; 6844 if (adev->pm.dpm.fan.ucode_fan_control) { 6845 ret = si_halt_smc(adev); 6846 if (ret) 6847 return ret; 6848 ret = si_thermal_setup_fan_table(adev); 6849 if (ret) 6850 return ret; 6851 ret = si_resume_smc(adev); 6852 if (ret) 6853 return ret; 6854 si_thermal_start_smc_fan_control(adev); 6855 } 6856 6857 return 0; 6858 } 6859 6860 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev) 6861 { 6862 if (!adev->pm.no_fan) { 6863 si_fan_ctrl_set_default_mode(adev); 6864 si_fan_ctrl_stop_smc_fan_control(adev); 6865 } 6866 } 6867 6868 static int si_dpm_enable(struct amdgpu_device *adev) 6869 { 6870 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6871 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6872 struct si_power_info *si_pi = si_get_pi(adev); 6873 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6874 int ret; 6875 6876 if (amdgpu_si_is_smc_running(adev)) 6877 return -EINVAL; 6878 if (pi->voltage_control || si_pi->voltage_control_svi2) 6879 si_enable_voltage_control(adev, true); 6880 if (pi->mvdd_control) 6881 si_get_mvdd_configuration(adev); 6882 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6883 ret = si_construct_voltage_tables(adev); 6884 if (ret) { 6885 DRM_ERROR("si_construct_voltage_tables failed\n"); 6886 return ret; 6887 } 6888 } 6889 if (eg_pi->dynamic_ac_timing) { 6890 ret = si_initialize_mc_reg_table(adev); 6891 if (ret) 6892 eg_pi->dynamic_ac_timing = false; 6893 } 6894 if (pi->dynamic_ss) 6895 si_enable_spread_spectrum(adev, true); 6896 if (pi->thermal_protection) 6897 si_enable_thermal_protection(adev, true); 6898 si_setup_bsp(adev); 6899 si_program_git(adev); 6900 si_program_tp(adev); 6901 si_program_tpp(adev); 6902 si_program_sstp(adev); 6903 si_enable_display_gap(adev); 6904 si_program_vc(adev); 6905 ret = si_upload_firmware(adev); 6906 if (ret) { 6907 DRM_ERROR("si_upload_firmware failed\n"); 6908 return ret; 6909 } 6910 ret = si_process_firmware_header(adev); 6911 if (ret) { 6912 DRM_ERROR("si_process_firmware_header failed\n"); 6913 return ret; 6914 } 6915 ret = si_initial_switch_from_arb_f0_to_f1(adev); 6916 if (ret) { 6917 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6918 return ret; 6919 } 6920 ret = si_init_smc_table(adev); 6921 if (ret) { 6922 DRM_ERROR("si_init_smc_table failed\n"); 6923 return ret; 6924 } 6925 ret = si_init_smc_spll_table(adev); 6926 if (ret) { 6927 DRM_ERROR("si_init_smc_spll_table failed\n"); 6928 return ret; 6929 } 6930 ret = si_init_arb_table_index(adev); 6931 if (ret) { 6932 DRM_ERROR("si_init_arb_table_index failed\n"); 6933 return ret; 6934 } 6935 if (eg_pi->dynamic_ac_timing) { 6936 ret = si_populate_mc_reg_table(adev, boot_ps); 6937 if (ret) { 6938 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6939 return ret; 6940 } 6941 } 6942 ret = si_initialize_smc_cac_tables(adev); 6943 if (ret) { 6944 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6945 return ret; 6946 } 6947 ret = si_initialize_hardware_cac_manager(adev); 6948 if (ret) { 6949 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6950 return ret; 6951 } 6952 ret = si_initialize_smc_dte_tables(adev); 6953 if (ret) { 6954 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6955 return ret; 6956 } 6957 ret = si_populate_smc_tdp_limits(adev, boot_ps); 6958 if (ret) { 6959 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6960 return ret; 6961 } 6962 ret = si_populate_smc_tdp_limits_2(adev, boot_ps); 6963 if (ret) { 6964 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6965 return ret; 6966 } 6967 si_program_response_times(adev); 6968 si_program_ds_registers(adev); 6969 si_dpm_start_smc(adev); 6970 ret = si_notify_smc_display_change(adev, false); 6971 if (ret) { 6972 DRM_ERROR("si_notify_smc_display_change failed\n"); 6973 return ret; 6974 } 6975 si_enable_sclk_control(adev, true); 6976 si_start_dpm(adev); 6977 6978 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6979 si_thermal_start_thermal_controller(adev); 6980 6981 ni_update_current_ps(adev, boot_ps); 6982 6983 return 0; 6984 } 6985 6986 static int si_set_temperature_range(struct amdgpu_device *adev) 6987 { 6988 int ret; 6989 6990 ret = si_thermal_enable_alert(adev, false); 6991 if (ret) 6992 return ret; 6993 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6994 if (ret) 6995 return ret; 6996 ret = si_thermal_enable_alert(adev, true); 6997 if (ret) 6998 return ret; 6999 7000 return ret; 7001 } 7002 7003 static void si_dpm_disable(struct amdgpu_device *adev) 7004 { 7005 struct rv7xx_power_info *pi = rv770_get_pi(adev); 7006 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 7007 7008 if (!amdgpu_si_is_smc_running(adev)) 7009 return; 7010 si_thermal_stop_thermal_controller(adev); 7011 si_disable_ulv(adev); 7012 si_clear_vc(adev); 7013 if (pi->thermal_protection) 7014 si_enable_thermal_protection(adev, false); 7015 si_enable_power_containment(adev, boot_ps, false); 7016 si_enable_smc_cac(adev, boot_ps, false); 7017 si_enable_spread_spectrum(adev, false); 7018 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 7019 si_stop_dpm(adev); 7020 si_reset_to_default(adev); 7021 si_dpm_stop_smc(adev); 7022 si_force_switch_to_arb_f0(adev); 7023 7024 ni_update_current_ps(adev, boot_ps); 7025 } 7026 7027 static int si_dpm_pre_set_power_state(void *handle) 7028 { 7029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7030 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7031 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 7032 struct amdgpu_ps *new_ps = &requested_ps; 7033 7034 ni_update_requested_ps(adev, new_ps); 7035 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); 7036 7037 return 0; 7038 } 7039 7040 static int si_power_control_set_level(struct amdgpu_device *adev) 7041 { 7042 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; 7043 int ret; 7044 7045 ret = si_restrict_performance_levels_before_switch(adev); 7046 if (ret) 7047 return ret; 7048 ret = si_halt_smc(adev); 7049 if (ret) 7050 return ret; 7051 ret = si_populate_smc_tdp_limits(adev, new_ps); 7052 if (ret) 7053 return ret; 7054 ret = si_populate_smc_tdp_limits_2(adev, new_ps); 7055 if (ret) 7056 return ret; 7057 ret = si_resume_smc(adev); 7058 if (ret) 7059 return ret; 7060 return si_set_sw_state(adev); 7061 } 7062 7063 static void si_set_vce_clock(struct amdgpu_device *adev, 7064 struct amdgpu_ps *new_rps, 7065 struct amdgpu_ps *old_rps) 7066 { 7067 if ((old_rps->evclk != new_rps->evclk) || 7068 (old_rps->ecclk != new_rps->ecclk)) { 7069 /* Turn the clocks on when encoding, off otherwise */ 7070 if (new_rps->evclk || new_rps->ecclk) { 7071 /* Place holder for future VCE1.0 porting to amdgpu 7072 vce_v1_0_enable_mgcg(adev, false, false);*/ 7073 } else { 7074 /* Place holder for future VCE1.0 porting to amdgpu 7075 vce_v1_0_enable_mgcg(adev, true, false); 7076 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/ 7077 } 7078 } 7079 } 7080 7081 static int si_dpm_set_power_state(void *handle) 7082 { 7083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7084 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7085 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7086 struct amdgpu_ps *old_ps = &eg_pi->current_rps; 7087 int ret; 7088 7089 ret = si_disable_ulv(adev); 7090 if (ret) { 7091 DRM_ERROR("si_disable_ulv failed\n"); 7092 return ret; 7093 } 7094 ret = si_restrict_performance_levels_before_switch(adev); 7095 if (ret) { 7096 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 7097 return ret; 7098 } 7099 if (eg_pi->pcie_performance_request) 7100 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps); 7101 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps); 7102 ret = si_enable_power_containment(adev, new_ps, false); 7103 if (ret) { 7104 DRM_ERROR("si_enable_power_containment failed\n"); 7105 return ret; 7106 } 7107 ret = si_enable_smc_cac(adev, new_ps, false); 7108 if (ret) { 7109 DRM_ERROR("si_enable_smc_cac failed\n"); 7110 return ret; 7111 } 7112 ret = si_halt_smc(adev); 7113 if (ret) { 7114 DRM_ERROR("si_halt_smc failed\n"); 7115 return ret; 7116 } 7117 ret = si_upload_sw_state(adev, new_ps); 7118 if (ret) { 7119 DRM_ERROR("si_upload_sw_state failed\n"); 7120 return ret; 7121 } 7122 ret = si_upload_smc_data(adev); 7123 if (ret) { 7124 DRM_ERROR("si_upload_smc_data failed\n"); 7125 return ret; 7126 } 7127 ret = si_upload_ulv_state(adev); 7128 if (ret) { 7129 DRM_ERROR("si_upload_ulv_state failed\n"); 7130 return ret; 7131 } 7132 if (eg_pi->dynamic_ac_timing) { 7133 ret = si_upload_mc_reg_table(adev, new_ps); 7134 if (ret) { 7135 DRM_ERROR("si_upload_mc_reg_table failed\n"); 7136 return ret; 7137 } 7138 } 7139 ret = si_program_memory_timing_parameters(adev, new_ps); 7140 if (ret) { 7141 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 7142 return ret; 7143 } 7144 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps); 7145 7146 ret = si_resume_smc(adev); 7147 if (ret) { 7148 DRM_ERROR("si_resume_smc failed\n"); 7149 return ret; 7150 } 7151 ret = si_set_sw_state(adev); 7152 if (ret) { 7153 DRM_ERROR("si_set_sw_state failed\n"); 7154 return ret; 7155 } 7156 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps); 7157 si_set_vce_clock(adev, new_ps, old_ps); 7158 if (eg_pi->pcie_performance_request) 7159 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); 7160 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps); 7161 if (ret) { 7162 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 7163 return ret; 7164 } 7165 ret = si_enable_smc_cac(adev, new_ps, true); 7166 if (ret) { 7167 DRM_ERROR("si_enable_smc_cac failed\n"); 7168 return ret; 7169 } 7170 ret = si_enable_power_containment(adev, new_ps, true); 7171 if (ret) { 7172 DRM_ERROR("si_enable_power_containment failed\n"); 7173 return ret; 7174 } 7175 7176 ret = si_power_control_set_level(adev); 7177 if (ret) { 7178 DRM_ERROR("si_power_control_set_level failed\n"); 7179 return ret; 7180 } 7181 7182 return 0; 7183 } 7184 7185 static void si_dpm_post_set_power_state(void *handle) 7186 { 7187 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7188 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7189 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7190 7191 ni_update_current_ps(adev, new_ps); 7192 } 7193 7194 #if 0 7195 void si_dpm_reset_asic(struct amdgpu_device *adev) 7196 { 7197 si_restrict_performance_levels_before_switch(adev); 7198 si_disable_ulv(adev); 7199 si_set_boot_state(adev); 7200 } 7201 #endif 7202 7203 static void si_dpm_display_configuration_changed(void *handle) 7204 { 7205 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7206 7207 si_program_display_gap(adev); 7208 } 7209 7210 7211 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, 7212 struct amdgpu_ps *rps, 7213 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 7214 u8 table_rev) 7215 { 7216 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 7217 rps->class = le16_to_cpu(non_clock_info->usClassification); 7218 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 7219 7220 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 7221 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 7222 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 7223 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 7224 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 7225 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 7226 } else { 7227 rps->vclk = 0; 7228 rps->dclk = 0; 7229 } 7230 7231 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 7232 adev->pm.dpm.boot_ps = rps; 7233 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 7234 adev->pm.dpm.uvd_ps = rps; 7235 } 7236 7237 static void si_parse_pplib_clock_info(struct amdgpu_device *adev, 7238 struct amdgpu_ps *rps, int index, 7239 union pplib_clock_info *clock_info) 7240 { 7241 struct rv7xx_power_info *pi = rv770_get_pi(adev); 7242 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7243 struct si_power_info *si_pi = si_get_pi(adev); 7244 struct si_ps *ps = si_get_ps(rps); 7245 u16 leakage_voltage; 7246 struct rv7xx_pl *pl = &ps->performance_levels[index]; 7247 int ret; 7248 7249 ps->performance_level_count = index + 1; 7250 7251 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7252 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 7253 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7254 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 7255 7256 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 7257 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 7258 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 7259 pl->pcie_gen = si_gen_pcie_gen_support(adev, 7260 si_pi->sys_pcie_mask, 7261 si_pi->boot_pcie_gen, 7262 clock_info->si.ucPCIEGen); 7263 7264 /* patch up vddc if necessary */ 7265 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, 7266 &leakage_voltage); 7267 if (ret == 0) 7268 pl->vddc = leakage_voltage; 7269 7270 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 7271 pi->acpi_vddc = pl->vddc; 7272 eg_pi->acpi_vddci = pl->vddci; 7273 si_pi->acpi_pcie_gen = pl->pcie_gen; 7274 } 7275 7276 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 7277 index == 0) { 7278 /* XXX disable for A0 tahiti */ 7279 si_pi->ulv.supported = false; 7280 si_pi->ulv.pl = *pl; 7281 si_pi->ulv.one_pcie_lane_in_ulv = false; 7282 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 7283 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 7284 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 7285 } 7286 7287 if (pi->min_vddc_in_table > pl->vddc) 7288 pi->min_vddc_in_table = pl->vddc; 7289 7290 if (pi->max_vddc_in_table < pl->vddc) 7291 pi->max_vddc_in_table = pl->vddc; 7292 7293 /* patch up boot state */ 7294 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 7295 u16 vddc, vddci, mvdd; 7296 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd); 7297 pl->mclk = adev->clock.default_mclk; 7298 pl->sclk = adev->clock.default_sclk; 7299 pl->vddc = vddc; 7300 pl->vddci = vddci; 7301 si_pi->mvdd_bootup_value = mvdd; 7302 } 7303 7304 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 7305 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 7306 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 7307 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 7308 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 7309 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 7310 } 7311 } 7312 7313 union pplib_power_state { 7314 struct _ATOM_PPLIB_STATE v1; 7315 struct _ATOM_PPLIB_STATE_V2 v2; 7316 }; 7317 7318 static int si_parse_power_table(struct amdgpu_device *adev) 7319 { 7320 struct amdgpu_mode_info *mode_info = &adev->mode_info; 7321 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 7322 union pplib_power_state *power_state; 7323 int i, j, k, non_clock_array_index, clock_array_index; 7324 union pplib_clock_info *clock_info; 7325 struct _StateArray *state_array; 7326 struct _ClockInfoArray *clock_info_array; 7327 struct _NonClockInfoArray *non_clock_info_array; 7328 union power_info *power_info; 7329 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 7330 u16 data_offset; 7331 u8 frev, crev; 7332 u8 *power_state_offset; 7333 struct si_ps *ps; 7334 7335 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 7336 &frev, &crev, &data_offset)) 7337 return -EINVAL; 7338 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 7339 7340 amdgpu_add_thermal_controller(adev); 7341 7342 state_array = (struct _StateArray *) 7343 (mode_info->atom_context->bios + data_offset + 7344 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 7345 clock_info_array = (struct _ClockInfoArray *) 7346 (mode_info->atom_context->bios + data_offset + 7347 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 7348 non_clock_info_array = (struct _NonClockInfoArray *) 7349 (mode_info->atom_context->bios + data_offset + 7350 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 7351 7352 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 7353 sizeof(struct amdgpu_ps), 7354 GFP_KERNEL); 7355 if (!adev->pm.dpm.ps) 7356 return -ENOMEM; 7357 power_state_offset = (u8 *)state_array->states; 7358 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { 7359 u8 *idx; 7360 power_state = (union pplib_power_state *)power_state_offset; 7361 non_clock_array_index = power_state->v2.nonClockInfoIndex; 7362 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 7363 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 7364 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL); 7365 if (ps == NULL) 7366 return -ENOMEM; 7367 adev->pm.dpm.ps[i].ps_priv = ps; 7368 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], 7369 non_clock_info, 7370 non_clock_info_array->ucEntrySize); 7371 k = 0; 7372 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 7373 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 7374 clock_array_index = idx[j]; 7375 if (clock_array_index >= clock_info_array->ucNumEntries) 7376 continue; 7377 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 7378 break; 7379 clock_info = (union pplib_clock_info *) 7380 ((u8 *)&clock_info_array->clockInfo[0] + 7381 (clock_array_index * clock_info_array->ucEntrySize)); 7382 si_parse_pplib_clock_info(adev, 7383 &adev->pm.dpm.ps[i], k, 7384 clock_info); 7385 k++; 7386 } 7387 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 7388 adev->pm.dpm.num_ps++; 7389 } 7390 7391 /* fill in the vce power states */ 7392 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 7393 u32 sclk, mclk; 7394 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 7395 clock_info = (union pplib_clock_info *) 7396 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 7397 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7398 sclk |= clock_info->si.ucEngineClockHigh << 16; 7399 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7400 mclk |= clock_info->si.ucMemoryClockHigh << 16; 7401 adev->pm.dpm.vce_states[i].sclk = sclk; 7402 adev->pm.dpm.vce_states[i].mclk = mclk; 7403 } 7404 7405 return 0; 7406 } 7407 7408 static int si_dpm_init(struct amdgpu_device *adev) 7409 { 7410 struct rv7xx_power_info *pi; 7411 struct evergreen_power_info *eg_pi; 7412 struct ni_power_info *ni_pi; 7413 struct si_power_info *si_pi; 7414 struct atom_clock_dividers dividers; 7415 int ret; 7416 7417 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 7418 if (si_pi == NULL) 7419 return -ENOMEM; 7420 adev->pm.dpm.priv = si_pi; 7421 ni_pi = &si_pi->ni; 7422 eg_pi = &ni_pi->eg; 7423 pi = &eg_pi->rv7xx; 7424 7425 si_pi->sys_pcie_mask = 7426 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK; 7427 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 7428 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); 7429 7430 si_set_max_cu_value(adev); 7431 7432 rv770_get_max_vddc(adev); 7433 si_get_leakage_vddc(adev); 7434 si_patch_dependency_tables_based_on_leakage(adev); 7435 7436 pi->acpi_vddc = 0; 7437 eg_pi->acpi_vddci = 0; 7438 pi->min_vddc_in_table = 0; 7439 pi->max_vddc_in_table = 0; 7440 7441 ret = amdgpu_get_platform_caps(adev); 7442 if (ret) 7443 return ret; 7444 7445 ret = amdgpu_parse_extended_power_table(adev); 7446 if (ret) 7447 return ret; 7448 7449 ret = si_parse_power_table(adev); 7450 if (ret) 7451 return ret; 7452 7453 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 7454 kcalloc(4, 7455 sizeof(struct amdgpu_clock_voltage_dependency_entry), 7456 GFP_KERNEL); 7457 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) 7458 return -ENOMEM; 7459 7460 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 7461 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 7462 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 7463 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 7464 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 7465 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 7466 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 7467 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 7468 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 7469 7470 if (adev->pm.dpm.voltage_response_time == 0) 7471 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 7472 if (adev->pm.dpm.backbias_response_time == 0) 7473 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 7474 7475 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 7476 0, false, ÷rs); 7477 if (ret) 7478 pi->ref_div = dividers.ref_div + 1; 7479 else 7480 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7481 7482 eg_pi->smu_uvd_hs = false; 7483 7484 pi->mclk_strobe_mode_threshold = 40000; 7485 if (si_is_special_1gb_platform(adev)) 7486 pi->mclk_stutter_mode_threshold = 0; 7487 else 7488 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7489 pi->mclk_edc_enable_threshold = 40000; 7490 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7491 7492 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7493 7494 pi->voltage_control = 7495 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7496 VOLTAGE_OBJ_GPIO_LUT); 7497 if (!pi->voltage_control) { 7498 si_pi->voltage_control_svi2 = 7499 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7500 VOLTAGE_OBJ_SVID2); 7501 if (si_pi->voltage_control_svi2) 7502 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7503 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7504 } 7505 7506 pi->mvdd_control = 7507 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7508 VOLTAGE_OBJ_GPIO_LUT); 7509 7510 eg_pi->vddci_control = 7511 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7512 VOLTAGE_OBJ_GPIO_LUT); 7513 if (!eg_pi->vddci_control) 7514 si_pi->vddci_control_svi2 = 7515 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7516 VOLTAGE_OBJ_SVID2); 7517 7518 si_pi->vddc_phase_shed_control = 7519 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7520 VOLTAGE_OBJ_PHASE_LUT); 7521 7522 rv770_get_engine_memory_ss(adev); 7523 7524 pi->asi = RV770_ASI_DFLT; 7525 pi->pasi = CYPRESS_HASI_DFLT; 7526 pi->vrc = SISLANDS_VRC_DFLT; 7527 7528 pi->gfx_clock_gating = true; 7529 7530 eg_pi->sclk_deep_sleep = true; 7531 si_pi->sclk_deep_sleep_above_low = false; 7532 7533 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7534 pi->thermal_protection = true; 7535 else 7536 pi->thermal_protection = false; 7537 7538 eg_pi->dynamic_ac_timing = true; 7539 7540 eg_pi->light_sleep = true; 7541 #if defined(CONFIG_ACPI) 7542 eg_pi->pcie_performance_request = 7543 amdgpu_acpi_is_pcie_performance_request_supported(adev); 7544 #else 7545 eg_pi->pcie_performance_request = false; 7546 #endif 7547 7548 si_pi->sram_end = SMC_RAM_END; 7549 7550 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7551 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7552 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7553 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7554 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7555 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7556 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7557 7558 si_initialize_powertune_defaults(adev); 7559 7560 /* make sure dc limits are valid */ 7561 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7562 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7563 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7564 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7565 7566 si_pi->fan_ctrl_is_in_default_mode = true; 7567 7568 return 0; 7569 } 7570 7571 static void si_dpm_fini(struct amdgpu_device *adev) 7572 { 7573 int i; 7574 7575 if (adev->pm.dpm.ps) 7576 for (i = 0; i < adev->pm.dpm.num_ps; i++) 7577 kfree(adev->pm.dpm.ps[i].ps_priv); 7578 kfree(adev->pm.dpm.ps); 7579 kfree(adev->pm.dpm.priv); 7580 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7581 amdgpu_free_extended_power_table(adev); 7582 } 7583 7584 static void si_dpm_debugfs_print_current_performance_level(void *handle, 7585 struct seq_file *m) 7586 { 7587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7588 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7589 struct amdgpu_ps *rps = &eg_pi->current_rps; 7590 struct si_ps *ps = si_get_ps(rps); 7591 struct rv7xx_pl *pl; 7592 u32 current_index = 7593 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >> 7594 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT; 7595 7596 if (current_index >= ps->performance_level_count) { 7597 seq_printf(m, "invalid dpm profile %d\n", current_index); 7598 } else { 7599 pl = &ps->performance_levels[current_index]; 7600 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7601 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7602 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7603 } 7604 } 7605 7606 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev, 7607 struct amdgpu_irq_src *source, 7608 unsigned type, 7609 enum amdgpu_interrupt_state state) 7610 { 7611 u32 cg_thermal_int; 7612 7613 switch (type) { 7614 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: 7615 switch (state) { 7616 case AMDGPU_IRQ_STATE_DISABLE: 7617 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7618 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK; 7619 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int); 7620 break; 7621 case AMDGPU_IRQ_STATE_ENABLE: 7622 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7623 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK; 7624 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int); 7625 break; 7626 default: 7627 break; 7628 } 7629 break; 7630 7631 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: 7632 switch (state) { 7633 case AMDGPU_IRQ_STATE_DISABLE: 7634 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7635 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 7636 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int); 7637 break; 7638 case AMDGPU_IRQ_STATE_ENABLE: 7639 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7640 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 7641 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int); 7642 break; 7643 default: 7644 break; 7645 } 7646 break; 7647 7648 default: 7649 break; 7650 } 7651 return 0; 7652 } 7653 7654 static int si_dpm_process_interrupt(struct amdgpu_device *adev, 7655 struct amdgpu_irq_src *source, 7656 struct amdgpu_iv_entry *entry) 7657 { 7658 bool queue_thermal = false; 7659 7660 if (entry == NULL) 7661 return -EINVAL; 7662 7663 switch (entry->src_id) { 7664 case 230: /* thermal low to high */ 7665 DRM_DEBUG("IH: thermal low to high\n"); 7666 adev->pm.dpm.thermal.high_to_low = false; 7667 queue_thermal = true; 7668 break; 7669 case 231: /* thermal high to low */ 7670 DRM_DEBUG("IH: thermal high to low\n"); 7671 adev->pm.dpm.thermal.high_to_low = true; 7672 queue_thermal = true; 7673 break; 7674 default: 7675 break; 7676 } 7677 7678 if (queue_thermal) 7679 schedule_work(&adev->pm.dpm.thermal.work); 7680 7681 return 0; 7682 } 7683 7684 static int si_dpm_late_init(struct amdgpu_ip_block *ip_block) 7685 { 7686 int ret; 7687 struct amdgpu_device *adev = ip_block->adev; 7688 7689 if (!adev->pm.dpm_enabled) 7690 return 0; 7691 7692 ret = si_set_temperature_range(adev); 7693 if (ret) 7694 return ret; 7695 #if 0 //TODO ? 7696 si_dpm_powergate_uvd(adev, true); 7697 #endif 7698 return 0; 7699 } 7700 7701 /** 7702 * si_dpm_init_microcode - load ucode images from disk 7703 * 7704 * @adev: amdgpu_device pointer 7705 * 7706 * Use the firmware interface to load the ucode images into 7707 * the driver (not loaded into hw). 7708 * Returns 0 on success, error on failure. 7709 */ 7710 static int si_dpm_init_microcode(struct amdgpu_device *adev) 7711 { 7712 const char *chip_name; 7713 int err; 7714 7715 DRM_DEBUG("\n"); 7716 switch (adev->asic_type) { 7717 case CHIP_TAHITI: 7718 chip_name = "tahiti"; 7719 break; 7720 case CHIP_PITCAIRN: 7721 if ((adev->pdev->revision == 0x81) && 7722 ((adev->pdev->device == 0x6810) || 7723 (adev->pdev->device == 0x6811))) 7724 chip_name = "pitcairn_k"; 7725 else 7726 chip_name = "pitcairn"; 7727 break; 7728 case CHIP_VERDE: 7729 if (((adev->pdev->device == 0x6820) && 7730 ((adev->pdev->revision == 0x81) || 7731 (adev->pdev->revision == 0x83))) || 7732 ((adev->pdev->device == 0x6821) && 7733 ((adev->pdev->revision == 0x83) || 7734 (adev->pdev->revision == 0x87))) || 7735 ((adev->pdev->revision == 0x87) && 7736 ((adev->pdev->device == 0x6823) || 7737 (adev->pdev->device == 0x682b)))) 7738 chip_name = "verde_k"; 7739 else 7740 chip_name = "verde"; 7741 break; 7742 case CHIP_OLAND: 7743 if (((adev->pdev->revision == 0x81) && 7744 ((adev->pdev->device == 0x6600) || 7745 (adev->pdev->device == 0x6604) || 7746 (adev->pdev->device == 0x6605) || 7747 (adev->pdev->device == 0x6610))) || 7748 ((adev->pdev->revision == 0x83) && 7749 (adev->pdev->device == 0x6610))) 7750 chip_name = "oland_k"; 7751 else 7752 chip_name = "oland"; 7753 break; 7754 case CHIP_HAINAN: 7755 if (((adev->pdev->revision == 0x81) && 7756 (adev->pdev->device == 0x6660)) || 7757 ((adev->pdev->revision == 0x83) && 7758 ((adev->pdev->device == 0x6660) || 7759 (adev->pdev->device == 0x6663) || 7760 (adev->pdev->device == 0x6665) || 7761 (adev->pdev->device == 0x6667)))) 7762 chip_name = "hainan_k"; 7763 else if ((adev->pdev->revision == 0xc3) && 7764 (adev->pdev->device == 0x6665)) 7765 chip_name = "banks_k_2"; 7766 else 7767 chip_name = "hainan"; 7768 break; 7769 default: BUG(); 7770 } 7771 7772 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 7773 "amdgpu/%s_smc.bin", chip_name); 7774 if (err) { 7775 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n", 7776 err, chip_name); 7777 amdgpu_ucode_release(&adev->pm.fw); 7778 } 7779 return err; 7780 } 7781 7782 static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block) 7783 { 7784 int ret; 7785 struct amdgpu_device *adev = ip_block->adev; 7786 7787 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); 7788 if (ret) 7789 return ret; 7790 7791 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); 7792 if (ret) 7793 return ret; 7794 7795 /* default to balanced state */ 7796 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 7797 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 7798 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; 7799 adev->pm.default_sclk = adev->clock.default_sclk; 7800 adev->pm.default_mclk = adev->clock.default_mclk; 7801 adev->pm.current_sclk = adev->clock.default_sclk; 7802 adev->pm.current_mclk = adev->clock.default_mclk; 7803 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 7804 7805 if (amdgpu_dpm == 0) 7806 return 0; 7807 7808 ret = si_dpm_init_microcode(adev); 7809 if (ret) 7810 return ret; 7811 7812 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 7813 ret = si_dpm_init(adev); 7814 if (ret) 7815 goto dpm_failed; 7816 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7817 if (amdgpu_dpm == 1) 7818 amdgpu_pm_print_power_states(adev); 7819 DRM_INFO("amdgpu: dpm initialized\n"); 7820 7821 return 0; 7822 7823 dpm_failed: 7824 si_dpm_fini(adev); 7825 DRM_ERROR("amdgpu: dpm initialization failed\n"); 7826 return ret; 7827 } 7828 7829 static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block) 7830 { 7831 struct amdgpu_device *adev = ip_block->adev; 7832 7833 flush_work(&adev->pm.dpm.thermal.work); 7834 7835 si_dpm_fini(adev); 7836 7837 return 0; 7838 } 7839 7840 static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block) 7841 { 7842 int ret; 7843 7844 struct amdgpu_device *adev = ip_block->adev; 7845 7846 if (!amdgpu_dpm) 7847 return 0; 7848 7849 mutex_lock(&adev->pm.mutex); 7850 si_dpm_setup_asic(adev); 7851 ret = si_dpm_enable(adev); 7852 if (ret) 7853 adev->pm.dpm_enabled = false; 7854 else 7855 adev->pm.dpm_enabled = true; 7856 amdgpu_legacy_dpm_compute_clocks(adev); 7857 mutex_unlock(&adev->pm.mutex); 7858 return ret; 7859 } 7860 7861 static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block) 7862 { 7863 struct amdgpu_device *adev = ip_block->adev; 7864 7865 if (adev->pm.dpm_enabled) 7866 si_dpm_disable(adev); 7867 7868 return 0; 7869 } 7870 7871 static int si_dpm_suspend(struct amdgpu_ip_block *ip_block) 7872 { 7873 struct amdgpu_device *adev = ip_block->adev; 7874 7875 cancel_work_sync(&adev->pm.dpm.thermal.work); 7876 7877 if (adev->pm.dpm_enabled) { 7878 mutex_lock(&adev->pm.mutex); 7879 adev->pm.dpm_enabled = false; 7880 /* disable dpm */ 7881 si_dpm_disable(adev); 7882 /* reset the power state */ 7883 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7884 mutex_unlock(&adev->pm.mutex); 7885 } 7886 7887 return 0; 7888 } 7889 7890 static int si_dpm_resume(struct amdgpu_ip_block *ip_block) 7891 { 7892 int ret = 0; 7893 struct amdgpu_device *adev = ip_block->adev; 7894 7895 if (!amdgpu_dpm) 7896 return 0; 7897 7898 if (!adev->pm.dpm_enabled) { 7899 /* asic init will reset to the boot state */ 7900 mutex_lock(&adev->pm.mutex); 7901 si_dpm_setup_asic(adev); 7902 ret = si_dpm_enable(adev); 7903 if (ret) { 7904 adev->pm.dpm_enabled = false; 7905 } else { 7906 adev->pm.dpm_enabled = true; 7907 amdgpu_legacy_dpm_compute_clocks(adev); 7908 } 7909 mutex_unlock(&adev->pm.mutex); 7910 } 7911 7912 return ret; 7913 } 7914 7915 static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block) 7916 { 7917 /* XXX */ 7918 return true; 7919 } 7920 7921 static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) 7922 { 7923 /* XXX */ 7924 return 0; 7925 } 7926 7927 static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 7928 enum amd_clockgating_state state) 7929 { 7930 return 0; 7931 } 7932 7933 static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block, 7934 enum amd_powergating_state state) 7935 { 7936 return 0; 7937 } 7938 7939 /* get temperature in millidegrees */ 7940 static int si_dpm_get_temp(void *handle) 7941 { 7942 u32 temp; 7943 int actual_temp = 0; 7944 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7945 7946 temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 7947 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; 7948 7949 if (temp & 0x200) 7950 actual_temp = 255; 7951 else 7952 actual_temp = temp & 0x1ff; 7953 7954 actual_temp = (actual_temp * 1000); 7955 7956 return actual_temp; 7957 } 7958 7959 static u32 si_dpm_get_sclk(void *handle, bool low) 7960 { 7961 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7962 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7963 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7964 7965 if (low) 7966 return requested_state->performance_levels[0].sclk; 7967 else 7968 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 7969 } 7970 7971 static u32 si_dpm_get_mclk(void *handle, bool low) 7972 { 7973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7974 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7975 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7976 7977 if (low) 7978 return requested_state->performance_levels[0].mclk; 7979 else 7980 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 7981 } 7982 7983 static void si_dpm_print_power_state(void *handle, 7984 void *current_ps) 7985 { 7986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7987 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; 7988 struct si_ps *ps = si_get_ps(rps); 7989 struct rv7xx_pl *pl; 7990 int i; 7991 7992 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2); 7993 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps); 7994 drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7995 drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk); 7996 for (i = 0; i < ps->performance_level_count; i++) { 7997 pl = &ps->performance_levels[i]; 7998 drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7999 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 8000 } 8001 amdgpu_dpm_dbg_print_ps_status(adev, rps); 8002 } 8003 8004 static int si_dpm_early_init(struct amdgpu_ip_block *ip_block) 8005 { 8006 8007 struct amdgpu_device *adev = ip_block->adev; 8008 8009 adev->powerplay.pp_funcs = &si_dpm_funcs; 8010 adev->powerplay.pp_handle = adev; 8011 si_dpm_set_irq_funcs(adev); 8012 return 0; 8013 } 8014 8015 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, 8016 const struct rv7xx_pl *si_cpl2) 8017 { 8018 return ((si_cpl1->mclk == si_cpl2->mclk) && 8019 (si_cpl1->sclk == si_cpl2->sclk) && 8020 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && 8021 (si_cpl1->vddc == si_cpl2->vddc) && 8022 (si_cpl1->vddci == si_cpl2->vddci)); 8023 } 8024 8025 static int si_check_state_equal(void *handle, 8026 void *current_ps, 8027 void *request_ps, 8028 bool *equal) 8029 { 8030 struct si_ps *si_cps; 8031 struct si_ps *si_rps; 8032 int i; 8033 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 8034 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 8035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8036 8037 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 8038 return -EINVAL; 8039 8040 si_cps = si_get_ps((struct amdgpu_ps *)cps); 8041 si_rps = si_get_ps((struct amdgpu_ps *)rps); 8042 8043 if (si_cps == NULL) { 8044 printk("si_cps is NULL\n"); 8045 *equal = false; 8046 return 0; 8047 } 8048 8049 if (si_cps->performance_level_count != si_rps->performance_level_count) { 8050 *equal = false; 8051 return 0; 8052 } 8053 8054 for (i = 0; i < si_cps->performance_level_count; i++) { 8055 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), 8056 &(si_rps->performance_levels[i]))) { 8057 *equal = false; 8058 return 0; 8059 } 8060 } 8061 8062 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 8063 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); 8064 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); 8065 8066 return 0; 8067 } 8068 8069 static int si_dpm_read_sensor(void *handle, int idx, 8070 void *value, int *size) 8071 { 8072 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8073 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 8074 struct amdgpu_ps *rps = &eg_pi->current_rps; 8075 struct si_ps *ps = si_get_ps(rps); 8076 uint32_t sclk, mclk; 8077 u32 pl_index = 8078 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >> 8079 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT; 8080 8081 /* size must be at least 4 bytes for all sensors */ 8082 if (*size < 4) 8083 return -EINVAL; 8084 8085 switch (idx) { 8086 case AMDGPU_PP_SENSOR_GFX_SCLK: 8087 if (pl_index < ps->performance_level_count) { 8088 sclk = ps->performance_levels[pl_index].sclk; 8089 *((uint32_t *)value) = sclk; 8090 *size = 4; 8091 return 0; 8092 } 8093 return -EINVAL; 8094 case AMDGPU_PP_SENSOR_GFX_MCLK: 8095 if (pl_index < ps->performance_level_count) { 8096 mclk = ps->performance_levels[pl_index].mclk; 8097 *((uint32_t *)value) = mclk; 8098 *size = 4; 8099 return 0; 8100 } 8101 return -EINVAL; 8102 case AMDGPU_PP_SENSOR_GPU_TEMP: 8103 *((uint32_t *)value) = si_dpm_get_temp(adev); 8104 *size = 4; 8105 return 0; 8106 default: 8107 return -EOPNOTSUPP; 8108 } 8109 } 8110 8111 static const struct amd_ip_funcs si_dpm_ip_funcs = { 8112 .name = "si_dpm", 8113 .early_init = si_dpm_early_init, 8114 .late_init = si_dpm_late_init, 8115 .sw_init = si_dpm_sw_init, 8116 .sw_fini = si_dpm_sw_fini, 8117 .hw_init = si_dpm_hw_init, 8118 .hw_fini = si_dpm_hw_fini, 8119 .suspend = si_dpm_suspend, 8120 .resume = si_dpm_resume, 8121 .is_idle = si_dpm_is_idle, 8122 .wait_for_idle = si_dpm_wait_for_idle, 8123 .set_clockgating_state = si_dpm_set_clockgating_state, 8124 .set_powergating_state = si_dpm_set_powergating_state, 8125 }; 8126 8127 const struct amdgpu_ip_block_version si_smu_ip_block = 8128 { 8129 .type = AMD_IP_BLOCK_TYPE_SMC, 8130 .major = 6, 8131 .minor = 0, 8132 .rev = 0, 8133 .funcs = &si_dpm_ip_funcs, 8134 }; 8135 8136 static const struct amd_pm_funcs si_dpm_funcs = { 8137 .pre_set_power_state = &si_dpm_pre_set_power_state, 8138 .set_power_state = &si_dpm_set_power_state, 8139 .post_set_power_state = &si_dpm_post_set_power_state, 8140 .display_configuration_changed = &si_dpm_display_configuration_changed, 8141 .get_sclk = &si_dpm_get_sclk, 8142 .get_mclk = &si_dpm_get_mclk, 8143 .print_power_state = &si_dpm_print_power_state, 8144 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 8145 .force_performance_level = &si_dpm_force_performance_level, 8146 .vblank_too_short = &si_dpm_vblank_too_short, 8147 .set_fan_control_mode = &si_dpm_set_fan_control_mode, 8148 .get_fan_control_mode = &si_dpm_get_fan_control_mode, 8149 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm, 8150 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm, 8151 .check_state_equal = &si_check_state_equal, 8152 .get_vce_clock_state = amdgpu_get_vce_clock_state, 8153 .read_sensor = &si_dpm_read_sensor, 8154 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks, 8155 }; 8156 8157 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = { 8158 .set = si_dpm_set_interrupt_state, 8159 .process = si_dpm_process_interrupt, 8160 }; 8161 8162 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) 8163 { 8164 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 8165 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; 8166 } 8167 8168