1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_DPM_H__ 24 #define __AMDGPU_DPM_H__ 25 26 /* Argument for PPSMC_MSG_GpuChangeState */ 27 enum gfx_change_state { 28 sGpuChangeState_D0Entry = 1, 29 sGpuChangeState_D3Entry, 30 }; 31 32 enum amdgpu_int_thermal_type { 33 THERMAL_TYPE_NONE, 34 THERMAL_TYPE_EXTERNAL, 35 THERMAL_TYPE_EXTERNAL_GPIO, 36 THERMAL_TYPE_RV6XX, 37 THERMAL_TYPE_RV770, 38 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 39 THERMAL_TYPE_EVERGREEN, 40 THERMAL_TYPE_SUMO, 41 THERMAL_TYPE_NI, 42 THERMAL_TYPE_SI, 43 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 44 THERMAL_TYPE_CI, 45 THERMAL_TYPE_KV, 46 }; 47 48 enum amdgpu_runpm_mode { 49 AMDGPU_RUNPM_NONE, 50 AMDGPU_RUNPM_PX, 51 AMDGPU_RUNPM_BOCO, 52 AMDGPU_RUNPM_BACO, 53 AMDGPU_RUNPM_BAMACO, 54 }; 55 56 #define BACO_SUPPORT (1<<0) 57 #define MACO_SUPPORT (1<<1) 58 59 struct amdgpu_ps { 60 u32 caps; /* vbios flags */ 61 u32 class; /* vbios flags */ 62 u32 class2; /* vbios flags */ 63 /* UVD clocks */ 64 u32 vclk; 65 u32 dclk; 66 /* VCE clocks */ 67 u32 evclk; 68 u32 ecclk; 69 bool vce_active; 70 enum amd_vce_level vce_level; 71 /* asic priv */ 72 void *ps_priv; 73 }; 74 75 struct amdgpu_dpm_thermal { 76 /* thermal interrupt work */ 77 struct work_struct work; 78 /* low temperature threshold */ 79 int min_temp; 80 /* high temperature threshold */ 81 int max_temp; 82 /* edge max emergency(shutdown) temp */ 83 int max_edge_emergency_temp; 84 /* hotspot low temperature threshold */ 85 int min_hotspot_temp; 86 /* hotspot high temperature critical threshold */ 87 int max_hotspot_crit_temp; 88 /* hotspot max emergency(shutdown) temp */ 89 int max_hotspot_emergency_temp; 90 /* memory low temperature threshold */ 91 int min_mem_temp; 92 /* memory high temperature critical threshold */ 93 int max_mem_crit_temp; 94 /* memory max emergency(shutdown) temp */ 95 int max_mem_emergency_temp; 96 /* SWCTF threshold */ 97 int sw_ctf_threshold; 98 /* was last interrupt low to high or high to low */ 99 bool high_to_low; 100 /* interrupt source */ 101 struct amdgpu_irq_src irq; 102 }; 103 104 struct amdgpu_clock_and_voltage_limits { 105 u32 sclk; 106 u32 mclk; 107 u16 vddc; 108 u16 vddci; 109 }; 110 111 struct amdgpu_clock_array { 112 u32 count; 113 u32 *values; 114 }; 115 116 struct amdgpu_clock_voltage_dependency_entry { 117 u32 clk; 118 u16 v; 119 }; 120 121 struct amdgpu_clock_voltage_dependency_table { 122 u32 count; 123 struct amdgpu_clock_voltage_dependency_entry *entries; 124 }; 125 126 union amdgpu_cac_leakage_entry { 127 struct { 128 u16 vddc; 129 u32 leakage; 130 }; 131 struct { 132 u16 vddc1; 133 u16 vddc2; 134 u16 vddc3; 135 }; 136 }; 137 138 struct amdgpu_cac_leakage_table { 139 u32 count; 140 union amdgpu_cac_leakage_entry *entries; 141 }; 142 143 struct amdgpu_phase_shedding_limits_entry { 144 u16 voltage; 145 u32 sclk; 146 u32 mclk; 147 }; 148 149 struct amdgpu_phase_shedding_limits_table { 150 u32 count; 151 struct amdgpu_phase_shedding_limits_entry *entries; 152 }; 153 154 struct amdgpu_uvd_clock_voltage_dependency_entry { 155 u32 vclk; 156 u32 dclk; 157 u16 v; 158 }; 159 160 struct amdgpu_uvd_clock_voltage_dependency_table { 161 u8 count; 162 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 163 }; 164 165 struct amdgpu_vce_clock_voltage_dependency_entry { 166 u32 ecclk; 167 u32 evclk; 168 u16 v; 169 }; 170 171 struct amdgpu_vce_clock_voltage_dependency_table { 172 u8 count; 173 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 174 }; 175 176 struct amdgpu_ppm_table { 177 u8 ppm_design; 178 u16 cpu_core_number; 179 u32 platform_tdp; 180 u32 small_ac_platform_tdp; 181 u32 platform_tdc; 182 u32 small_ac_platform_tdc; 183 u32 apu_tdp; 184 u32 dgpu_tdp; 185 u32 dgpu_ulv_power; 186 u32 tj_max; 187 }; 188 189 struct amdgpu_cac_tdp_table { 190 u16 tdp; 191 u16 configurable_tdp; 192 u16 tdc; 193 u16 battery_power_limit; 194 u16 small_power_limit; 195 u16 low_cac_leakage; 196 u16 high_cac_leakage; 197 u16 maximum_power_delivery_limit; 198 }; 199 200 struct amdgpu_dpm_dynamic_state { 201 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 202 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 203 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 204 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 205 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 206 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 207 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 208 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 209 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 210 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 211 struct amdgpu_clock_array valid_sclk_values; 212 struct amdgpu_clock_array valid_mclk_values; 213 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 214 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 215 u32 mclk_sclk_ratio; 216 u32 sclk_mclk_delta; 217 u16 vddc_vddci_delta; 218 u16 min_vddc_for_pcie_gen2; 219 struct amdgpu_cac_leakage_table cac_leakage_table; 220 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 221 struct amdgpu_ppm_table *ppm_table; 222 struct amdgpu_cac_tdp_table *cac_tdp_table; 223 }; 224 225 struct amdgpu_dpm_fan { 226 u16 t_min; 227 u16 t_med; 228 u16 t_high; 229 u16 pwm_min; 230 u16 pwm_med; 231 u16 pwm_high; 232 u8 t_hyst; 233 u32 cycle_delay; 234 u16 t_max; 235 u8 control_mode; 236 u16 default_max_fan_pwm; 237 u16 default_fan_output_sensitivity; 238 u16 fan_output_sensitivity; 239 bool ucode_fan_control; 240 }; 241 242 struct amdgpu_dpm { 243 struct amdgpu_ps *ps; 244 /* number of valid power states */ 245 int num_ps; 246 /* current power state that is active */ 247 struct amdgpu_ps *current_ps; 248 /* requested power state */ 249 struct amdgpu_ps *requested_ps; 250 /* boot up power state */ 251 struct amdgpu_ps *boot_ps; 252 /* default uvd power state */ 253 struct amdgpu_ps *uvd_ps; 254 /* vce requirements */ 255 u32 num_of_vce_states; 256 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 257 enum amd_vce_level vce_level; 258 enum amd_pm_state_type state; 259 enum amd_pm_state_type user_state; 260 enum amd_pm_state_type last_state; 261 enum amd_pm_state_type last_user_state; 262 u32 platform_caps; 263 u32 voltage_response_time; 264 u32 backbias_response_time; 265 void *priv; 266 u32 new_active_crtcs; 267 int new_active_crtc_count; 268 u32 current_active_crtcs; 269 int current_active_crtc_count; 270 struct amdgpu_dpm_dynamic_state dyn_state; 271 struct amdgpu_dpm_fan fan; 272 u32 tdp_limit; 273 u32 near_tdp_limit; 274 u32 near_tdp_limit_adjusted; 275 u32 sq_ramping_threshold; 276 u32 cac_leakage; 277 u16 tdp_od_limit; 278 u32 tdp_adjustment; 279 u16 load_line_slope; 280 bool power_control; 281 /* special states active */ 282 bool thermal_active; 283 bool uvd_active; 284 bool vce_active; 285 /* thermal handling */ 286 struct amdgpu_dpm_thermal thermal; 287 /* forced levels */ 288 enum amd_dpm_forced_level forced_level; 289 }; 290 291 enum ip_power_state { 292 POWER_STATE_UNKNOWN, 293 POWER_STATE_ON, 294 POWER_STATE_OFF, 295 }; 296 297 /* Used to mask smu debug modes */ 298 #define SMU_DEBUG_HALT_ON_ERROR 0x1 299 300 #define MAX_SMU_I2C_BUSES 2 301 302 struct amdgpu_smu_i2c_bus { 303 struct i2c_adapter adapter; 304 struct amdgpu_device *adev; 305 int port; 306 struct mutex mutex; 307 }; 308 309 struct config_table_setting 310 { 311 uint16_t gfxclk_average_tau; 312 uint16_t socclk_average_tau; 313 uint16_t uclk_average_tau; 314 uint16_t gfx_activity_average_tau; 315 uint16_t mem_activity_average_tau; 316 uint16_t socket_power_average_tau; 317 uint16_t apu_socket_power_average_tau; 318 uint16_t fclk_average_tau; 319 }; 320 321 #define OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE BIT(0) 322 #define OD_OPS_SUPPORT_FAN_CURVE_SET BIT(1) 323 #define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE BIT(2) 324 #define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET BIT(3) 325 #define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE BIT(4) 326 #define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET BIT(5) 327 #define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE BIT(6) 328 #define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET BIT(7) 329 #define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE BIT(8) 330 #define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET BIT(9) 331 332 struct amdgpu_pm { 333 struct mutex mutex; 334 u32 current_sclk; 335 u32 current_mclk; 336 u32 default_sclk; 337 u32 default_mclk; 338 struct amdgpu_i2c_chan *i2c_bus; 339 bool bus_locked; 340 /* internal thermal controller on rv6xx+ */ 341 enum amdgpu_int_thermal_type int_thermal_type; 342 struct device *int_hwmon_dev; 343 /* fan control parameters */ 344 bool no_fan; 345 u8 fan_pulses_per_revolution; 346 u8 fan_min_rpm; 347 u8 fan_max_rpm; 348 /* dpm */ 349 bool dpm_enabled; 350 bool sysfs_initialized; 351 struct amdgpu_dpm dpm; 352 const struct firmware *fw; /* SMC firmware */ 353 uint32_t fw_version; 354 uint32_t pcie_gen_mask; 355 uint32_t pcie_mlw_mask; 356 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ 357 uint32_t smu_prv_buffer_size; 358 struct amdgpu_bo *smu_prv_buffer; 359 bool ac_power; 360 /* powerplay feature */ 361 uint32_t pp_feature; 362 363 /* Used for I2C access to various EEPROMs on relevant ASICs */ 364 struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES]; 365 struct i2c_adapter *ras_eeprom_i2c_bus; 366 struct i2c_adapter *fru_eeprom_i2c_bus; 367 struct list_head pm_attr_list; 368 369 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM]; 370 371 /* 372 * 0 = disabled (default), otherwise enable corresponding debug mode 373 */ 374 uint32_t smu_debug_mask; 375 376 bool pp_force_state_enabled; 377 378 struct mutex stable_pstate_ctx_lock; 379 struct amdgpu_ctx *stable_pstate_ctx; 380 381 struct config_table_setting config_table; 382 /* runtime mode */ 383 enum amdgpu_runpm_mode rpm_mode; 384 385 struct list_head od_kobj_list; 386 uint32_t od_feature_mask; 387 }; 388 389 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 390 void *data, uint32_t *size); 391 392 int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit); 393 int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit); 394 395 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, 396 uint32_t block_type, bool gate); 397 398 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); 399 400 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); 401 402 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 403 uint32_t pstate); 404 405 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 406 enum PP_SMC_POWER_PROFILE type, 407 bool en); 408 409 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev); 410 411 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev); 412 int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev); 413 414 int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); 415 416 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev); 417 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); 418 419 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 420 enum pp_mp1_state mp1_state); 421 422 int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en); 423 424 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev); 425 426 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); 427 428 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); 429 430 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 431 uint32_t cstate); 432 433 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev); 434 435 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 436 uint32_t msg_id); 437 438 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 439 bool acquire); 440 441 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); 442 443 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev); 444 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); 445 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); 446 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable); 447 void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable); 448 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); 449 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable); 450 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size); 451 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size); 452 int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev); 453 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 454 enum pp_clock_type type, 455 uint32_t *min, 456 uint32_t *max); 457 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 458 enum pp_clock_type type, 459 uint32_t min, 460 uint32_t max); 461 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev); 462 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 463 uint64_t event_arg); 464 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value); 465 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value); 466 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value); 467 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); 468 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev); 469 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 470 enum gfx_change_state state); 471 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 472 void *umc_ecc); 473 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 474 uint32_t idx); 475 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state); 476 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 477 enum amd_pm_state_type state); 478 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev); 479 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 480 enum amd_dpm_forced_level level); 481 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 482 struct pp_states_info *states); 483 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 484 enum amd_pp_task task_id, 485 enum amd_pm_state_type *user_state); 486 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table); 487 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 488 uint32_t type, 489 long *input, 490 uint32_t size); 491 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 492 uint32_t type, 493 long *input, 494 uint32_t size); 495 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 496 enum pp_clock_type type, 497 char *buf); 498 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, 499 enum pp_clock_type type, 500 char *buf, 501 int *offset); 502 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 503 uint64_t ppfeature_masks); 504 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf); 505 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 506 enum pp_clock_type type, 507 uint32_t mask); 508 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev); 509 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value); 510 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev); 511 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value); 512 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 513 char *buf); 514 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 515 long *input, uint32_t size); 516 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table); 517 518 /** 519 * @get_pm_metrics: Get one snapshot of power management metrics from PMFW. The 520 * sample is copied to pm_metrics buffer. It's expected to be allocated by the 521 * caller and size of the allocated buffer is passed. Max size expected for a 522 * metrics sample is 4096 bytes. 523 * 524 * Return: Actual size of the metrics sample 525 */ 526 ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, 527 size_t size); 528 529 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 530 uint32_t *fan_mode); 531 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 532 uint32_t speed); 533 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 534 uint32_t *speed); 535 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 536 uint32_t *speed); 537 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 538 uint32_t speed); 539 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 540 uint32_t mode); 541 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 542 uint32_t *limit, 543 enum pp_power_limit_level pp_limit_level, 544 enum pp_power_type power_type); 545 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 546 uint32_t limit); 547 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev); 548 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 549 struct seq_file *m); 550 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 551 void **addr, 552 size_t *size); 553 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev); 554 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 555 const char *buf, 556 size_t size); 557 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev); 558 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev); 559 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 560 const struct amd_pp_display_configuration *input); 561 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 562 enum amd_pp_clock_type type, 563 struct amd_pp_clocks *clocks); 564 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 565 struct amd_pp_simple_clock_info *clocks); 566 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 567 enum amd_pp_clock_type type, 568 struct pp_clock_levels_with_latency *clocks); 569 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 570 enum amd_pp_clock_type type, 571 struct pp_clock_levels_with_voltage *clocks); 572 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 573 void *clock_ranges); 574 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 575 struct pp_display_clock_request *clock); 576 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 577 struct amd_pp_clock_info *clocks); 578 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev); 579 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 580 uint32_t count); 581 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 582 uint32_t clock); 583 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 584 uint32_t clock); 585 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 586 uint32_t clock); 587 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 588 bool disable_memory_clock_switch); 589 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 590 struct pp_smu_nv_clock_table *max_clocks); 591 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 592 unsigned int *clock_values_in_khz, 593 unsigned int *num_states); 594 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 595 struct dpm_clocks *clock_table); 596 int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, 597 int policy_level); 598 ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, 599 enum pp_pm_policy p_type, char *buf); 600 601 #endif 602