1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/pci.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 #include <linux/pm_runtime.h> 36 #include <asm/processor.h> 37 38 #define MAX_NUM_OF_FEATURES_PER_SUBSET 8 39 #define MAX_NUM_OF_SUBSETS 8 40 41 struct od_attribute { 42 struct kobj_attribute attribute; 43 struct list_head entry; 44 }; 45 46 struct od_kobj { 47 struct kobject kobj; 48 struct list_head entry; 49 struct list_head attribute; 50 void *priv; 51 }; 52 53 struct od_feature_ops { 54 umode_t (*is_visible)(struct amdgpu_device *adev); 55 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr, 56 char *buf); 57 ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr, 58 const char *buf, size_t count); 59 }; 60 61 struct od_feature_item { 62 const char *name; 63 struct od_feature_ops ops; 64 }; 65 66 struct od_feature_container { 67 char *name; 68 struct od_feature_ops ops; 69 struct od_feature_item sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET]; 70 }; 71 72 struct od_feature_set { 73 struct od_feature_container containers[MAX_NUM_OF_SUBSETS]; 74 }; 75 76 static const struct hwmon_temp_label { 77 enum PP_HWMON_TEMP channel; 78 const char *label; 79 } temp_label[] = { 80 {PP_TEMP_EDGE, "edge"}, 81 {PP_TEMP_JUNCTION, "junction"}, 82 {PP_TEMP_MEM, "mem"}, 83 }; 84 85 const char * const amdgpu_pp_profile_name[] = { 86 "BOOTUP_DEFAULT", 87 "3D_FULL_SCREEN", 88 "POWER_SAVING", 89 "VIDEO", 90 "VR", 91 "COMPUTE", 92 "CUSTOM", 93 "WINDOW_3D", 94 "CAPPED", 95 "UNCAPPED", 96 }; 97 98 /** 99 * DOC: power_dpm_state 100 * 101 * The power_dpm_state file is a legacy interface and is only provided for 102 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 103 * certain power related parameters. The file power_dpm_state is used for this. 104 * It accepts the following arguments: 105 * 106 * - battery 107 * 108 * - balanced 109 * 110 * - performance 111 * 112 * battery 113 * 114 * On older GPUs, the vbios provided a special power state for battery 115 * operation. Selecting battery switched to this state. This is no 116 * longer provided on newer GPUs so the option does nothing in that case. 117 * 118 * balanced 119 * 120 * On older GPUs, the vbios provided a special power state for balanced 121 * operation. Selecting balanced switched to this state. This is no 122 * longer provided on newer GPUs so the option does nothing in that case. 123 * 124 * performance 125 * 126 * On older GPUs, the vbios provided a special power state for performance 127 * operation. Selecting performance switched to this state. This is no 128 * longer provided on newer GPUs so the option does nothing in that case. 129 * 130 */ 131 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 133 struct device_attribute *attr, 134 char *buf) 135 { 136 struct drm_device *ddev = dev_get_drvdata(dev); 137 struct amdgpu_device *adev = drm_to_adev(ddev); 138 enum amd_pm_state_type pm; 139 int ret; 140 141 if (amdgpu_in_reset(adev)) 142 return -EPERM; 143 if (adev->in_suspend && !adev->in_runpm) 144 return -EPERM; 145 146 ret = pm_runtime_get_sync(ddev->dev); 147 if (ret < 0) { 148 pm_runtime_put_autosuspend(ddev->dev); 149 return ret; 150 } 151 152 amdgpu_dpm_get_current_power_state(adev, &pm); 153 154 pm_runtime_mark_last_busy(ddev->dev); 155 pm_runtime_put_autosuspend(ddev->dev); 156 157 return sysfs_emit(buf, "%s\n", 158 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 159 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 160 } 161 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 163 struct device_attribute *attr, 164 const char *buf, 165 size_t count) 166 { 167 struct drm_device *ddev = dev_get_drvdata(dev); 168 struct amdgpu_device *adev = drm_to_adev(ddev); 169 enum amd_pm_state_type state; 170 int ret; 171 172 if (amdgpu_in_reset(adev)) 173 return -EPERM; 174 if (adev->in_suspend && !adev->in_runpm) 175 return -EPERM; 176 177 if (strncmp("battery", buf, strlen("battery")) == 0) 178 state = POWER_STATE_TYPE_BATTERY; 179 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 180 state = POWER_STATE_TYPE_BALANCED; 181 else if (strncmp("performance", buf, strlen("performance")) == 0) 182 state = POWER_STATE_TYPE_PERFORMANCE; 183 else 184 return -EINVAL; 185 186 ret = pm_runtime_get_sync(ddev->dev); 187 if (ret < 0) { 188 pm_runtime_put_autosuspend(ddev->dev); 189 return ret; 190 } 191 192 amdgpu_dpm_set_power_state(adev, state); 193 194 pm_runtime_mark_last_busy(ddev->dev); 195 pm_runtime_put_autosuspend(ddev->dev); 196 197 return count; 198 } 199 200 201 /** 202 * DOC: power_dpm_force_performance_level 203 * 204 * The amdgpu driver provides a sysfs API for adjusting certain power 205 * related parameters. The file power_dpm_force_performance_level is 206 * used for this. It accepts the following arguments: 207 * 208 * - auto 209 * 210 * - low 211 * 212 * - high 213 * 214 * - manual 215 * 216 * - profile_standard 217 * 218 * - profile_min_sclk 219 * 220 * - profile_min_mclk 221 * 222 * - profile_peak 223 * 224 * auto 225 * 226 * When auto is selected, the driver will attempt to dynamically select 227 * the optimal power profile for current conditions in the driver. 228 * 229 * low 230 * 231 * When low is selected, the clocks are forced to the lowest power state. 232 * 233 * high 234 * 235 * When high is selected, the clocks are forced to the highest power state. 236 * 237 * manual 238 * 239 * When manual is selected, the user can manually adjust which power states 240 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 241 * and pp_dpm_pcie files and adjust the power state transition heuristics 242 * via the pp_power_profile_mode sysfs file. 243 * 244 * profile_standard 245 * profile_min_sclk 246 * profile_min_mclk 247 * profile_peak 248 * 249 * When the profiling modes are selected, clock and power gating are 250 * disabled and the clocks are set for different profiling cases. This 251 * mode is recommended for profiling specific work loads where you do 252 * not want clock or power gating for clock fluctuation to interfere 253 * with your results. profile_standard sets the clocks to a fixed clock 254 * level which varies from asic to asic. profile_min_sclk forces the sclk 255 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 256 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 257 * 258 */ 259 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 261 struct device_attribute *attr, 262 char *buf) 263 { 264 struct drm_device *ddev = dev_get_drvdata(dev); 265 struct amdgpu_device *adev = drm_to_adev(ddev); 266 enum amd_dpm_forced_level level = 0xff; 267 int ret; 268 269 if (amdgpu_in_reset(adev)) 270 return -EPERM; 271 if (adev->in_suspend && !adev->in_runpm) 272 return -EPERM; 273 274 ret = pm_runtime_get_sync(ddev->dev); 275 if (ret < 0) { 276 pm_runtime_put_autosuspend(ddev->dev); 277 return ret; 278 } 279 280 level = amdgpu_dpm_get_performance_level(adev); 281 282 pm_runtime_mark_last_busy(ddev->dev); 283 pm_runtime_put_autosuspend(ddev->dev); 284 285 return sysfs_emit(buf, "%s\n", 286 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 287 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 288 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 289 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 290 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 291 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 292 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 293 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 294 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 295 "unknown"); 296 } 297 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 299 struct device_attribute *attr, 300 const char *buf, 301 size_t count) 302 { 303 struct drm_device *ddev = dev_get_drvdata(dev); 304 struct amdgpu_device *adev = drm_to_adev(ddev); 305 enum amd_dpm_forced_level level; 306 int ret = 0; 307 308 if (amdgpu_in_reset(adev)) 309 return -EPERM; 310 if (adev->in_suspend && !adev->in_runpm) 311 return -EPERM; 312 313 if (strncmp("low", buf, strlen("low")) == 0) { 314 level = AMD_DPM_FORCED_LEVEL_LOW; 315 } else if (strncmp("high", buf, strlen("high")) == 0) { 316 level = AMD_DPM_FORCED_LEVEL_HIGH; 317 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 318 level = AMD_DPM_FORCED_LEVEL_AUTO; 319 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 320 level = AMD_DPM_FORCED_LEVEL_MANUAL; 321 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 322 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 323 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 324 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 325 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 326 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 327 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 328 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 329 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 330 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 331 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 332 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 333 } else { 334 return -EINVAL; 335 } 336 337 ret = pm_runtime_get_sync(ddev->dev); 338 if (ret < 0) { 339 pm_runtime_put_autosuspend(ddev->dev); 340 return ret; 341 } 342 343 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 344 if (amdgpu_dpm_force_performance_level(adev, level)) { 345 pm_runtime_mark_last_busy(ddev->dev); 346 pm_runtime_put_autosuspend(ddev->dev); 347 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 348 return -EINVAL; 349 } 350 /* override whatever a user ctx may have set */ 351 adev->pm.stable_pstate_ctx = NULL; 352 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 353 354 pm_runtime_mark_last_busy(ddev->dev); 355 pm_runtime_put_autosuspend(ddev->dev); 356 357 return count; 358 } 359 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 361 struct device_attribute *attr, 362 char *buf) 363 { 364 struct drm_device *ddev = dev_get_drvdata(dev); 365 struct amdgpu_device *adev = drm_to_adev(ddev); 366 struct pp_states_info data; 367 uint32_t i; 368 int buf_len, ret; 369 370 if (amdgpu_in_reset(adev)) 371 return -EPERM; 372 if (adev->in_suspend && !adev->in_runpm) 373 return -EPERM; 374 375 ret = pm_runtime_get_sync(ddev->dev); 376 if (ret < 0) { 377 pm_runtime_put_autosuspend(ddev->dev); 378 return ret; 379 } 380 381 if (amdgpu_dpm_get_pp_num_states(adev, &data)) 382 memset(&data, 0, sizeof(data)); 383 384 pm_runtime_mark_last_busy(ddev->dev); 385 pm_runtime_put_autosuspend(ddev->dev); 386 387 buf_len = sysfs_emit(buf, "states: %d\n", data.nums); 388 for (i = 0; i < data.nums; i++) 389 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, 390 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 391 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 392 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 393 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 394 395 return buf_len; 396 } 397 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 399 struct device_attribute *attr, 400 char *buf) 401 { 402 struct drm_device *ddev = dev_get_drvdata(dev); 403 struct amdgpu_device *adev = drm_to_adev(ddev); 404 struct pp_states_info data = {0}; 405 enum amd_pm_state_type pm = 0; 406 int i = 0, ret = 0; 407 408 if (amdgpu_in_reset(adev)) 409 return -EPERM; 410 if (adev->in_suspend && !adev->in_runpm) 411 return -EPERM; 412 413 ret = pm_runtime_get_sync(ddev->dev); 414 if (ret < 0) { 415 pm_runtime_put_autosuspend(ddev->dev); 416 return ret; 417 } 418 419 amdgpu_dpm_get_current_power_state(adev, &pm); 420 421 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 422 423 pm_runtime_mark_last_busy(ddev->dev); 424 pm_runtime_put_autosuspend(ddev->dev); 425 426 if (ret) 427 return ret; 428 429 for (i = 0; i < data.nums; i++) { 430 if (pm == data.states[i]) 431 break; 432 } 433 434 if (i == data.nums) 435 i = -EINVAL; 436 437 return sysfs_emit(buf, "%d\n", i); 438 } 439 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 441 struct device_attribute *attr, 442 char *buf) 443 { 444 struct drm_device *ddev = dev_get_drvdata(dev); 445 struct amdgpu_device *adev = drm_to_adev(ddev); 446 447 if (amdgpu_in_reset(adev)) 448 return -EPERM; 449 if (adev->in_suspend && !adev->in_runpm) 450 return -EPERM; 451 452 if (adev->pm.pp_force_state_enabled) 453 return amdgpu_get_pp_cur_state(dev, attr, buf); 454 else 455 return sysfs_emit(buf, "\n"); 456 } 457 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 459 struct device_attribute *attr, 460 const char *buf, 461 size_t count) 462 { 463 struct drm_device *ddev = dev_get_drvdata(dev); 464 struct amdgpu_device *adev = drm_to_adev(ddev); 465 enum amd_pm_state_type state = 0; 466 struct pp_states_info data; 467 unsigned long idx; 468 int ret; 469 470 if (amdgpu_in_reset(adev)) 471 return -EPERM; 472 if (adev->in_suspend && !adev->in_runpm) 473 return -EPERM; 474 475 adev->pm.pp_force_state_enabled = false; 476 477 if (strlen(buf) == 1) 478 return count; 479 480 ret = kstrtoul(buf, 0, &idx); 481 if (ret || idx >= ARRAY_SIZE(data.states)) 482 return -EINVAL; 483 484 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 485 486 ret = pm_runtime_get_sync(ddev->dev); 487 if (ret < 0) { 488 pm_runtime_put_autosuspend(ddev->dev); 489 return ret; 490 } 491 492 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 493 if (ret) 494 goto err_out; 495 496 state = data.states[idx]; 497 498 /* only set user selected power states */ 499 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 500 state != POWER_STATE_TYPE_DEFAULT) { 501 ret = amdgpu_dpm_dispatch_task(adev, 502 AMD_PP_TASK_ENABLE_USER_STATE, &state); 503 if (ret) 504 goto err_out; 505 506 adev->pm.pp_force_state_enabled = true; 507 } 508 509 pm_runtime_mark_last_busy(ddev->dev); 510 pm_runtime_put_autosuspend(ddev->dev); 511 512 return count; 513 514 err_out: 515 pm_runtime_mark_last_busy(ddev->dev); 516 pm_runtime_put_autosuspend(ddev->dev); 517 return ret; 518 } 519 520 /** 521 * DOC: pp_table 522 * 523 * The amdgpu driver provides a sysfs API for uploading new powerplay 524 * tables. The file pp_table is used for this. Reading the file 525 * will dump the current power play table. Writing to the file 526 * will attempt to upload a new powerplay table and re-initialize 527 * powerplay using that new table. 528 * 529 */ 530 531 static ssize_t amdgpu_get_pp_table(struct device *dev, 532 struct device_attribute *attr, 533 char *buf) 534 { 535 struct drm_device *ddev = dev_get_drvdata(dev); 536 struct amdgpu_device *adev = drm_to_adev(ddev); 537 char *table = NULL; 538 int size, ret; 539 540 if (amdgpu_in_reset(adev)) 541 return -EPERM; 542 if (adev->in_suspend && !adev->in_runpm) 543 return -EPERM; 544 545 ret = pm_runtime_get_sync(ddev->dev); 546 if (ret < 0) { 547 pm_runtime_put_autosuspend(ddev->dev); 548 return ret; 549 } 550 551 size = amdgpu_dpm_get_pp_table(adev, &table); 552 553 pm_runtime_mark_last_busy(ddev->dev); 554 pm_runtime_put_autosuspend(ddev->dev); 555 556 if (size <= 0) 557 return size; 558 559 if (size >= PAGE_SIZE) 560 size = PAGE_SIZE - 1; 561 562 memcpy(buf, table, size); 563 564 return size; 565 } 566 567 static ssize_t amdgpu_set_pp_table(struct device *dev, 568 struct device_attribute *attr, 569 const char *buf, 570 size_t count) 571 { 572 struct drm_device *ddev = dev_get_drvdata(dev); 573 struct amdgpu_device *adev = drm_to_adev(ddev); 574 int ret = 0; 575 576 if (amdgpu_in_reset(adev)) 577 return -EPERM; 578 if (adev->in_suspend && !adev->in_runpm) 579 return -EPERM; 580 581 ret = pm_runtime_get_sync(ddev->dev); 582 if (ret < 0) { 583 pm_runtime_put_autosuspend(ddev->dev); 584 return ret; 585 } 586 587 ret = amdgpu_dpm_set_pp_table(adev, buf, count); 588 589 pm_runtime_mark_last_busy(ddev->dev); 590 pm_runtime_put_autosuspend(ddev->dev); 591 592 if (ret) 593 return ret; 594 595 return count; 596 } 597 598 /** 599 * DOC: pp_od_clk_voltage 600 * 601 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 602 * in each power level within a power state. The pp_od_clk_voltage is used for 603 * this. 604 * 605 * Note that the actual memory controller clock rate are exposed, not 606 * the effective memory clock of the DRAMs. To translate it, use the 607 * following formula: 608 * 609 * Clock conversion (Mhz): 610 * 611 * HBM: effective_memory_clock = memory_controller_clock * 1 612 * 613 * G5: effective_memory_clock = memory_controller_clock * 1 614 * 615 * G6: effective_memory_clock = memory_controller_clock * 2 616 * 617 * DRAM data rate (MT/s): 618 * 619 * HBM: effective_memory_clock * 2 = data_rate 620 * 621 * G5: effective_memory_clock * 4 = data_rate 622 * 623 * G6: effective_memory_clock * 8 = data_rate 624 * 625 * Bandwidth (MB/s): 626 * 627 * data_rate * vram_bit_width / 8 = memory_bandwidth 628 * 629 * Some examples: 630 * 631 * G5 on RX460: 632 * 633 * memory_controller_clock = 1750 Mhz 634 * 635 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 636 * 637 * data rate = 1750 * 4 = 7000 MT/s 638 * 639 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 640 * 641 * G6 on RX5700: 642 * 643 * memory_controller_clock = 875 Mhz 644 * 645 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 646 * 647 * data rate = 1750 * 8 = 14000 MT/s 648 * 649 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 650 * 651 * < For Vega10 and previous ASICs > 652 * 653 * Reading the file will display: 654 * 655 * - a list of engine clock levels and voltages labeled OD_SCLK 656 * 657 * - a list of memory clock levels and voltages labeled OD_MCLK 658 * 659 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 660 * 661 * To manually adjust these settings, first select manual using 662 * power_dpm_force_performance_level. Enter a new value for each 663 * level by writing a string that contains "s/m level clock voltage" to 664 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 665 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 666 * 810 mV. When you have edited all of the states as needed, write 667 * "c" (commit) to the file to commit your changes. If you want to reset to the 668 * default power levels, write "r" (reset) to the file to reset them. 669 * 670 * 671 * < For Vega20 and newer ASICs > 672 * 673 * Reading the file will display: 674 * 675 * - minimum and maximum engine clock labeled OD_SCLK 676 * 677 * - minimum(not available for Vega20 and Navi1x) and maximum memory 678 * clock labeled OD_MCLK 679 * 680 * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 681 * They can be used to calibrate the sclk voltage curve. This is 682 * available for Vega20 and NV1X. 683 * 684 * - voltage offset(in mV) applied on target voltage calculation. 685 * This is available for Sienna Cichlid, Navy Flounder, Dimgrey 686 * Cavefish and some later SMU13 ASICs. For these ASICs, the target 687 * voltage calculation can be illustrated by "voltage = voltage 688 * calculated from v/f curve + overdrive vddgfx offset" 689 * 690 * - a list of valid ranges for sclk, mclk, voltage curve points 691 * or voltage offset labeled OD_RANGE 692 * 693 * < For APUs > 694 * 695 * Reading the file will display: 696 * 697 * - minimum and maximum engine clock labeled OD_SCLK 698 * 699 * - a list of valid ranges for sclk labeled OD_RANGE 700 * 701 * < For VanGogh > 702 * 703 * Reading the file will display: 704 * 705 * - minimum and maximum engine clock labeled OD_SCLK 706 * - minimum and maximum core clocks labeled OD_CCLK 707 * 708 * - a list of valid ranges for sclk and cclk labeled OD_RANGE 709 * 710 * To manually adjust these settings: 711 * 712 * - First select manual using power_dpm_force_performance_level 713 * 714 * - For clock frequency setting, enter a new value by writing a 715 * string that contains "s/m index clock" to the file. The index 716 * should be 0 if to set minimum clock. And 1 if to set maximum 717 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 718 * "m 1 800" will update maximum mclk to be 800Mhz. For core 719 * clocks on VanGogh, the string contains "p core index clock". 720 * E.g., "p 2 0 800" would set the minimum core clock on core 721 * 2 to 800Mhz. 722 * 723 * For sclk voltage curve supported by Vega20 and NV1X, enter the new 724 * values by writing a string that contains "vc point clock voltage" 725 * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300 726 * 600" will update point1 with clock set as 300Mhz and voltage as 600mV. 727 * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and 728 * voltage 1000mV. 729 * 730 * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey 731 * Cavefish and some later SMU13 ASICs, enter the new value by writing a 732 * string that contains "vo offset". E.g., "vo -10" will update the extra 733 * voltage offset applied to the whole v/f curve line as -10mv. 734 * 735 * - When you have edited all of the states as needed, write "c" (commit) 736 * to the file to commit your changes 737 * 738 * - If you want to reset to the default power levels, write "r" (reset) 739 * to the file to reset them 740 * 741 */ 742 743 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 744 struct device_attribute *attr, 745 const char *buf, 746 size_t count) 747 { 748 struct drm_device *ddev = dev_get_drvdata(dev); 749 struct amdgpu_device *adev = drm_to_adev(ddev); 750 int ret; 751 uint32_t parameter_size = 0; 752 long parameter[64]; 753 char buf_cpy[128]; 754 char *tmp_str; 755 char *sub_str; 756 const char delimiter[3] = {' ', '\n', '\0'}; 757 uint32_t type; 758 759 if (amdgpu_in_reset(adev)) 760 return -EPERM; 761 if (adev->in_suspend && !adev->in_runpm) 762 return -EPERM; 763 764 if (count > 127 || count == 0) 765 return -EINVAL; 766 767 if (*buf == 's') 768 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 769 else if (*buf == 'p') 770 type = PP_OD_EDIT_CCLK_VDDC_TABLE; 771 else if (*buf == 'm') 772 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 773 else if (*buf == 'r') 774 type = PP_OD_RESTORE_DEFAULT_TABLE; 775 else if (*buf == 'c') 776 type = PP_OD_COMMIT_DPM_TABLE; 777 else if (!strncmp(buf, "vc", 2)) 778 type = PP_OD_EDIT_VDDC_CURVE; 779 else if (!strncmp(buf, "vo", 2)) 780 type = PP_OD_EDIT_VDDGFX_OFFSET; 781 else 782 return -EINVAL; 783 784 memcpy(buf_cpy, buf, count); 785 buf_cpy[count] = 0; 786 787 tmp_str = buf_cpy; 788 789 if ((type == PP_OD_EDIT_VDDC_CURVE) || 790 (type == PP_OD_EDIT_VDDGFX_OFFSET)) 791 tmp_str++; 792 while (isspace(*++tmp_str)); 793 794 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 795 if (strlen(sub_str) == 0) 796 continue; 797 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 798 if (ret) 799 return -EINVAL; 800 parameter_size++; 801 802 if (!tmp_str) 803 break; 804 805 while (isspace(*tmp_str)) 806 tmp_str++; 807 } 808 809 ret = pm_runtime_get_sync(ddev->dev); 810 if (ret < 0) { 811 pm_runtime_put_autosuspend(ddev->dev); 812 return ret; 813 } 814 815 if (amdgpu_dpm_set_fine_grain_clk_vol(adev, 816 type, 817 parameter, 818 parameter_size)) 819 goto err_out; 820 821 if (amdgpu_dpm_odn_edit_dpm_table(adev, type, 822 parameter, parameter_size)) 823 goto err_out; 824 825 if (type == PP_OD_COMMIT_DPM_TABLE) { 826 if (amdgpu_dpm_dispatch_task(adev, 827 AMD_PP_TASK_READJUST_POWER_STATE, 828 NULL)) 829 goto err_out; 830 } 831 832 pm_runtime_mark_last_busy(ddev->dev); 833 pm_runtime_put_autosuspend(ddev->dev); 834 835 return count; 836 837 err_out: 838 pm_runtime_mark_last_busy(ddev->dev); 839 pm_runtime_put_autosuspend(ddev->dev); 840 return -EINVAL; 841 } 842 843 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 844 struct device_attribute *attr, 845 char *buf) 846 { 847 struct drm_device *ddev = dev_get_drvdata(dev); 848 struct amdgpu_device *adev = drm_to_adev(ddev); 849 int size = 0; 850 int ret; 851 enum pp_clock_type od_clocks[6] = { 852 OD_SCLK, 853 OD_MCLK, 854 OD_VDDC_CURVE, 855 OD_RANGE, 856 OD_VDDGFX_OFFSET, 857 OD_CCLK, 858 }; 859 uint clk_index; 860 861 if (amdgpu_in_reset(adev)) 862 return -EPERM; 863 if (adev->in_suspend && !adev->in_runpm) 864 return -EPERM; 865 866 ret = pm_runtime_get_sync(ddev->dev); 867 if (ret < 0) { 868 pm_runtime_put_autosuspend(ddev->dev); 869 return ret; 870 } 871 872 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { 873 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); 874 if (ret) 875 break; 876 } 877 if (ret == -ENOENT) { 878 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 879 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); 880 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); 881 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); 882 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); 883 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); 884 } 885 886 if (size == 0) 887 size = sysfs_emit(buf, "\n"); 888 889 pm_runtime_mark_last_busy(ddev->dev); 890 pm_runtime_put_autosuspend(ddev->dev); 891 892 return size; 893 } 894 895 /** 896 * DOC: pp_features 897 * 898 * The amdgpu driver provides a sysfs API for adjusting what powerplay 899 * features to be enabled. The file pp_features is used for this. And 900 * this is only available for Vega10 and later dGPUs. 901 * 902 * Reading back the file will show you the followings: 903 * - Current ppfeature masks 904 * - List of the all supported powerplay features with their naming, 905 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 906 * 907 * To manually enable or disable a specific feature, just set or clear 908 * the corresponding bit from original ppfeature masks and input the 909 * new ppfeature masks. 910 */ 911 static ssize_t amdgpu_set_pp_features(struct device *dev, 912 struct device_attribute *attr, 913 const char *buf, 914 size_t count) 915 { 916 struct drm_device *ddev = dev_get_drvdata(dev); 917 struct amdgpu_device *adev = drm_to_adev(ddev); 918 uint64_t featuremask; 919 int ret; 920 921 if (amdgpu_in_reset(adev)) 922 return -EPERM; 923 if (adev->in_suspend && !adev->in_runpm) 924 return -EPERM; 925 926 ret = kstrtou64(buf, 0, &featuremask); 927 if (ret) 928 return -EINVAL; 929 930 ret = pm_runtime_get_sync(ddev->dev); 931 if (ret < 0) { 932 pm_runtime_put_autosuspend(ddev->dev); 933 return ret; 934 } 935 936 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 937 938 pm_runtime_mark_last_busy(ddev->dev); 939 pm_runtime_put_autosuspend(ddev->dev); 940 941 if (ret) 942 return -EINVAL; 943 944 return count; 945 } 946 947 static ssize_t amdgpu_get_pp_features(struct device *dev, 948 struct device_attribute *attr, 949 char *buf) 950 { 951 struct drm_device *ddev = dev_get_drvdata(dev); 952 struct amdgpu_device *adev = drm_to_adev(ddev); 953 ssize_t size; 954 int ret; 955 956 if (amdgpu_in_reset(adev)) 957 return -EPERM; 958 if (adev->in_suspend && !adev->in_runpm) 959 return -EPERM; 960 961 ret = pm_runtime_get_sync(ddev->dev); 962 if (ret < 0) { 963 pm_runtime_put_autosuspend(ddev->dev); 964 return ret; 965 } 966 967 size = amdgpu_dpm_get_ppfeature_status(adev, buf); 968 if (size <= 0) 969 size = sysfs_emit(buf, "\n"); 970 971 pm_runtime_mark_last_busy(ddev->dev); 972 pm_runtime_put_autosuspend(ddev->dev); 973 974 return size; 975 } 976 977 /** 978 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 979 * 980 * The amdgpu driver provides a sysfs API for adjusting what power levels 981 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 982 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 983 * this. 984 * 985 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 986 * Vega10 and later ASICs. 987 * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 988 * 989 * Reading back the files will show you the available power levels within 990 * the power state and the clock information for those levels. If deep sleep is 991 * applied to a clock, the level will be denoted by a special level 'S:' 992 * E.g., :: 993 * 994 * S: 19Mhz * 995 * 0: 615Mhz 996 * 1: 800Mhz 997 * 2: 888Mhz 998 * 3: 1000Mhz 999 * 1000 * 1001 * To manually adjust these states, first select manual using 1002 * power_dpm_force_performance_level. 1003 * Secondly, enter a new value for each level by inputing a string that 1004 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 1005 * E.g., 1006 * 1007 * .. code-block:: bash 1008 * 1009 * echo "4 5 6" > pp_dpm_sclk 1010 * 1011 * will enable sclk levels 4, 5, and 6. 1012 * 1013 * NOTE: change to the dcefclk max dpm level is not supported now 1014 */ 1015 1016 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 1017 enum pp_clock_type type, 1018 char *buf) 1019 { 1020 struct drm_device *ddev = dev_get_drvdata(dev); 1021 struct amdgpu_device *adev = drm_to_adev(ddev); 1022 int size = 0; 1023 int ret = 0; 1024 1025 if (amdgpu_in_reset(adev)) 1026 return -EPERM; 1027 if (adev->in_suspend && !adev->in_runpm) 1028 return -EPERM; 1029 1030 ret = pm_runtime_get_sync(ddev->dev); 1031 if (ret < 0) { 1032 pm_runtime_put_autosuspend(ddev->dev); 1033 return ret; 1034 } 1035 1036 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); 1037 if (ret == -ENOENT) 1038 size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1039 1040 if (size == 0) 1041 size = sysfs_emit(buf, "\n"); 1042 1043 pm_runtime_mark_last_busy(ddev->dev); 1044 pm_runtime_put_autosuspend(ddev->dev); 1045 1046 return size; 1047 } 1048 1049 /* 1050 * Worst case: 32 bits individually specified, in octal at 12 characters 1051 * per line (+1 for \n). 1052 */ 1053 #define AMDGPU_MASK_BUF_MAX (32 * 13) 1054 1055 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1056 { 1057 int ret; 1058 unsigned long level; 1059 char *sub_str = NULL; 1060 char *tmp; 1061 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1062 const char delimiter[3] = {' ', '\n', '\0'}; 1063 size_t bytes; 1064 1065 *mask = 0; 1066 1067 bytes = min(count, sizeof(buf_cpy) - 1); 1068 memcpy(buf_cpy, buf, bytes); 1069 buf_cpy[bytes] = '\0'; 1070 tmp = buf_cpy; 1071 while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1072 if (strlen(sub_str)) { 1073 ret = kstrtoul(sub_str, 0, &level); 1074 if (ret || level > 31) 1075 return -EINVAL; 1076 *mask |= 1 << level; 1077 } else 1078 break; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 1085 enum pp_clock_type type, 1086 const char *buf, 1087 size_t count) 1088 { 1089 struct drm_device *ddev = dev_get_drvdata(dev); 1090 struct amdgpu_device *adev = drm_to_adev(ddev); 1091 int ret; 1092 uint32_t mask = 0; 1093 1094 if (amdgpu_in_reset(adev)) 1095 return -EPERM; 1096 if (adev->in_suspend && !adev->in_runpm) 1097 return -EPERM; 1098 1099 ret = amdgpu_read_mask(buf, count, &mask); 1100 if (ret) 1101 return ret; 1102 1103 ret = pm_runtime_get_sync(ddev->dev); 1104 if (ret < 0) { 1105 pm_runtime_put_autosuspend(ddev->dev); 1106 return ret; 1107 } 1108 1109 ret = amdgpu_dpm_force_clock_level(adev, type, mask); 1110 1111 pm_runtime_mark_last_busy(ddev->dev); 1112 pm_runtime_put_autosuspend(ddev->dev); 1113 1114 if (ret) 1115 return -EINVAL; 1116 1117 return count; 1118 } 1119 1120 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1121 struct device_attribute *attr, 1122 char *buf) 1123 { 1124 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 1125 } 1126 1127 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1128 struct device_attribute *attr, 1129 const char *buf, 1130 size_t count) 1131 { 1132 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 1133 } 1134 1135 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1136 struct device_attribute *attr, 1137 char *buf) 1138 { 1139 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1140 } 1141 1142 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1143 struct device_attribute *attr, 1144 const char *buf, 1145 size_t count) 1146 { 1147 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1148 } 1149 1150 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1151 struct device_attribute *attr, 1152 char *buf) 1153 { 1154 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1155 } 1156 1157 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1158 struct device_attribute *attr, 1159 const char *buf, 1160 size_t count) 1161 { 1162 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1163 } 1164 1165 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1166 struct device_attribute *attr, 1167 char *buf) 1168 { 1169 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1170 } 1171 1172 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1173 struct device_attribute *attr, 1174 const char *buf, 1175 size_t count) 1176 { 1177 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1178 } 1179 1180 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 1181 struct device_attribute *attr, 1182 char *buf) 1183 { 1184 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 1185 } 1186 1187 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 1188 struct device_attribute *attr, 1189 const char *buf, 1190 size_t count) 1191 { 1192 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 1193 } 1194 1195 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev, 1196 struct device_attribute *attr, 1197 char *buf) 1198 { 1199 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf); 1200 } 1201 1202 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev, 1203 struct device_attribute *attr, 1204 const char *buf, 1205 size_t count) 1206 { 1207 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count); 1208 } 1209 1210 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 1211 struct device_attribute *attr, 1212 char *buf) 1213 { 1214 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 1215 } 1216 1217 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 1218 struct device_attribute *attr, 1219 const char *buf, 1220 size_t count) 1221 { 1222 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 1223 } 1224 1225 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev, 1226 struct device_attribute *attr, 1227 char *buf) 1228 { 1229 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf); 1230 } 1231 1232 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev, 1233 struct device_attribute *attr, 1234 const char *buf, 1235 size_t count) 1236 { 1237 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count); 1238 } 1239 1240 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1241 struct device_attribute *attr, 1242 char *buf) 1243 { 1244 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1245 } 1246 1247 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1248 struct device_attribute *attr, 1249 const char *buf, 1250 size_t count) 1251 { 1252 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1253 } 1254 1255 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1256 struct device_attribute *attr, 1257 char *buf) 1258 { 1259 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1260 } 1261 1262 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1263 struct device_attribute *attr, 1264 const char *buf, 1265 size_t count) 1266 { 1267 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1268 } 1269 1270 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1271 struct device_attribute *attr, 1272 char *buf) 1273 { 1274 struct drm_device *ddev = dev_get_drvdata(dev); 1275 struct amdgpu_device *adev = drm_to_adev(ddev); 1276 uint32_t value = 0; 1277 int ret; 1278 1279 if (amdgpu_in_reset(adev)) 1280 return -EPERM; 1281 if (adev->in_suspend && !adev->in_runpm) 1282 return -EPERM; 1283 1284 ret = pm_runtime_get_sync(ddev->dev); 1285 if (ret < 0) { 1286 pm_runtime_put_autosuspend(ddev->dev); 1287 return ret; 1288 } 1289 1290 value = amdgpu_dpm_get_sclk_od(adev); 1291 1292 pm_runtime_mark_last_busy(ddev->dev); 1293 pm_runtime_put_autosuspend(ddev->dev); 1294 1295 return sysfs_emit(buf, "%d\n", value); 1296 } 1297 1298 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1299 struct device_attribute *attr, 1300 const char *buf, 1301 size_t count) 1302 { 1303 struct drm_device *ddev = dev_get_drvdata(dev); 1304 struct amdgpu_device *adev = drm_to_adev(ddev); 1305 int ret; 1306 long int value; 1307 1308 if (amdgpu_in_reset(adev)) 1309 return -EPERM; 1310 if (adev->in_suspend && !adev->in_runpm) 1311 return -EPERM; 1312 1313 ret = kstrtol(buf, 0, &value); 1314 1315 if (ret) 1316 return -EINVAL; 1317 1318 ret = pm_runtime_get_sync(ddev->dev); 1319 if (ret < 0) { 1320 pm_runtime_put_autosuspend(ddev->dev); 1321 return ret; 1322 } 1323 1324 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1325 1326 pm_runtime_mark_last_busy(ddev->dev); 1327 pm_runtime_put_autosuspend(ddev->dev); 1328 1329 return count; 1330 } 1331 1332 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1333 struct device_attribute *attr, 1334 char *buf) 1335 { 1336 struct drm_device *ddev = dev_get_drvdata(dev); 1337 struct amdgpu_device *adev = drm_to_adev(ddev); 1338 uint32_t value = 0; 1339 int ret; 1340 1341 if (amdgpu_in_reset(adev)) 1342 return -EPERM; 1343 if (adev->in_suspend && !adev->in_runpm) 1344 return -EPERM; 1345 1346 ret = pm_runtime_get_sync(ddev->dev); 1347 if (ret < 0) { 1348 pm_runtime_put_autosuspend(ddev->dev); 1349 return ret; 1350 } 1351 1352 value = amdgpu_dpm_get_mclk_od(adev); 1353 1354 pm_runtime_mark_last_busy(ddev->dev); 1355 pm_runtime_put_autosuspend(ddev->dev); 1356 1357 return sysfs_emit(buf, "%d\n", value); 1358 } 1359 1360 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1361 struct device_attribute *attr, 1362 const char *buf, 1363 size_t count) 1364 { 1365 struct drm_device *ddev = dev_get_drvdata(dev); 1366 struct amdgpu_device *adev = drm_to_adev(ddev); 1367 int ret; 1368 long int value; 1369 1370 if (amdgpu_in_reset(adev)) 1371 return -EPERM; 1372 if (adev->in_suspend && !adev->in_runpm) 1373 return -EPERM; 1374 1375 ret = kstrtol(buf, 0, &value); 1376 1377 if (ret) 1378 return -EINVAL; 1379 1380 ret = pm_runtime_get_sync(ddev->dev); 1381 if (ret < 0) { 1382 pm_runtime_put_autosuspend(ddev->dev); 1383 return ret; 1384 } 1385 1386 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1387 1388 pm_runtime_mark_last_busy(ddev->dev); 1389 pm_runtime_put_autosuspend(ddev->dev); 1390 1391 return count; 1392 } 1393 1394 /** 1395 * DOC: pp_power_profile_mode 1396 * 1397 * The amdgpu driver provides a sysfs API for adjusting the heuristics 1398 * related to switching between power levels in a power state. The file 1399 * pp_power_profile_mode is used for this. 1400 * 1401 * Reading this file outputs a list of all of the predefined power profiles 1402 * and the relevant heuristics settings for that profile. 1403 * 1404 * To select a profile or create a custom profile, first select manual using 1405 * power_dpm_force_performance_level. Writing the number of a predefined 1406 * profile to pp_power_profile_mode will enable those heuristics. To 1407 * create a custom set of heuristics, write a string of numbers to the file 1408 * starting with the number of the custom profile along with a setting 1409 * for each heuristic parameter. Due to differences across asic families 1410 * the heuristic parameters vary from family to family. 1411 * 1412 */ 1413 1414 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1415 struct device_attribute *attr, 1416 char *buf) 1417 { 1418 struct drm_device *ddev = dev_get_drvdata(dev); 1419 struct amdgpu_device *adev = drm_to_adev(ddev); 1420 ssize_t size; 1421 int ret; 1422 1423 if (amdgpu_in_reset(adev)) 1424 return -EPERM; 1425 if (adev->in_suspend && !adev->in_runpm) 1426 return -EPERM; 1427 1428 ret = pm_runtime_get_sync(ddev->dev); 1429 if (ret < 0) { 1430 pm_runtime_put_autosuspend(ddev->dev); 1431 return ret; 1432 } 1433 1434 size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1435 if (size <= 0) 1436 size = sysfs_emit(buf, "\n"); 1437 1438 pm_runtime_mark_last_busy(ddev->dev); 1439 pm_runtime_put_autosuspend(ddev->dev); 1440 1441 return size; 1442 } 1443 1444 1445 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1446 struct device_attribute *attr, 1447 const char *buf, 1448 size_t count) 1449 { 1450 int ret; 1451 struct drm_device *ddev = dev_get_drvdata(dev); 1452 struct amdgpu_device *adev = drm_to_adev(ddev); 1453 uint32_t parameter_size = 0; 1454 long parameter[64]; 1455 char *sub_str, buf_cpy[128]; 1456 char *tmp_str; 1457 uint32_t i = 0; 1458 char tmp[2]; 1459 long int profile_mode = 0; 1460 const char delimiter[3] = {' ', '\n', '\0'}; 1461 1462 if (amdgpu_in_reset(adev)) 1463 return -EPERM; 1464 if (adev->in_suspend && !adev->in_runpm) 1465 return -EPERM; 1466 1467 tmp[0] = *(buf); 1468 tmp[1] = '\0'; 1469 ret = kstrtol(tmp, 0, &profile_mode); 1470 if (ret) 1471 return -EINVAL; 1472 1473 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1474 if (count < 2 || count > 127) 1475 return -EINVAL; 1476 while (isspace(*++buf)) 1477 i++; 1478 memcpy(buf_cpy, buf, count-i); 1479 tmp_str = buf_cpy; 1480 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1481 if (strlen(sub_str) == 0) 1482 continue; 1483 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1484 if (ret) 1485 return -EINVAL; 1486 parameter_size++; 1487 while (isspace(*tmp_str)) 1488 tmp_str++; 1489 } 1490 } 1491 parameter[parameter_size] = profile_mode; 1492 1493 ret = pm_runtime_get_sync(ddev->dev); 1494 if (ret < 0) { 1495 pm_runtime_put_autosuspend(ddev->dev); 1496 return ret; 1497 } 1498 1499 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1500 1501 pm_runtime_mark_last_busy(ddev->dev); 1502 pm_runtime_put_autosuspend(ddev->dev); 1503 1504 if (!ret) 1505 return count; 1506 1507 return -EINVAL; 1508 } 1509 1510 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev, 1511 enum amd_pp_sensors sensor, 1512 void *query) 1513 { 1514 int r, size = sizeof(uint32_t); 1515 1516 if (amdgpu_in_reset(adev)) 1517 return -EPERM; 1518 if (adev->in_suspend && !adev->in_runpm) 1519 return -EPERM; 1520 1521 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 1522 if (r < 0) { 1523 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1524 return r; 1525 } 1526 1527 /* get the sensor value */ 1528 r = amdgpu_dpm_read_sensor(adev, sensor, query, &size); 1529 1530 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1531 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1532 1533 return r; 1534 } 1535 1536 /** 1537 * DOC: gpu_busy_percent 1538 * 1539 * The amdgpu driver provides a sysfs API for reading how busy the GPU 1540 * is as a percentage. The file gpu_busy_percent is used for this. 1541 * The SMU firmware computes a percentage of load based on the 1542 * aggregate activity level in the IP cores. 1543 */ 1544 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1545 struct device_attribute *attr, 1546 char *buf) 1547 { 1548 struct drm_device *ddev = dev_get_drvdata(dev); 1549 struct amdgpu_device *adev = drm_to_adev(ddev); 1550 unsigned int value; 1551 int r; 1552 1553 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value); 1554 if (r) 1555 return r; 1556 1557 return sysfs_emit(buf, "%d\n", value); 1558 } 1559 1560 /** 1561 * DOC: mem_busy_percent 1562 * 1563 * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1564 * is as a percentage. The file mem_busy_percent is used for this. 1565 * The SMU firmware computes a percentage of load based on the 1566 * aggregate activity level in the IP cores. 1567 */ 1568 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1569 struct device_attribute *attr, 1570 char *buf) 1571 { 1572 struct drm_device *ddev = dev_get_drvdata(dev); 1573 struct amdgpu_device *adev = drm_to_adev(ddev); 1574 unsigned int value; 1575 int r; 1576 1577 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value); 1578 if (r) 1579 return r; 1580 1581 return sysfs_emit(buf, "%d\n", value); 1582 } 1583 1584 /** 1585 * DOC: pcie_bw 1586 * 1587 * The amdgpu driver provides a sysfs API for estimating how much data 1588 * has been received and sent by the GPU in the last second through PCIe. 1589 * The file pcie_bw is used for this. 1590 * The Perf counters count the number of received and sent messages and return 1591 * those values, as well as the maximum payload size of a PCIe packet (mps). 1592 * Note that it is not possible to easily and quickly obtain the size of each 1593 * packet transmitted, so we output the max payload size (mps) to allow for 1594 * quick estimation of the PCIe bandwidth usage 1595 */ 1596 static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1597 struct device_attribute *attr, 1598 char *buf) 1599 { 1600 struct drm_device *ddev = dev_get_drvdata(dev); 1601 struct amdgpu_device *adev = drm_to_adev(ddev); 1602 uint64_t count0 = 0, count1 = 0; 1603 int ret; 1604 1605 if (amdgpu_in_reset(adev)) 1606 return -EPERM; 1607 if (adev->in_suspend && !adev->in_runpm) 1608 return -EPERM; 1609 1610 if (adev->flags & AMD_IS_APU) 1611 return -ENODATA; 1612 1613 if (!adev->asic_funcs->get_pcie_usage) 1614 return -ENODATA; 1615 1616 ret = pm_runtime_get_sync(ddev->dev); 1617 if (ret < 0) { 1618 pm_runtime_put_autosuspend(ddev->dev); 1619 return ret; 1620 } 1621 1622 amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1623 1624 pm_runtime_mark_last_busy(ddev->dev); 1625 pm_runtime_put_autosuspend(ddev->dev); 1626 1627 return sysfs_emit(buf, "%llu %llu %i\n", 1628 count0, count1, pcie_get_mps(adev->pdev)); 1629 } 1630 1631 /** 1632 * DOC: unique_id 1633 * 1634 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1635 * The file unique_id is used for this. 1636 * This will provide a Unique ID that will persist from machine to machine 1637 * 1638 * NOTE: This will only work for GFX9 and newer. This file will be absent 1639 * on unsupported ASICs (GFX8 and older) 1640 */ 1641 static ssize_t amdgpu_get_unique_id(struct device *dev, 1642 struct device_attribute *attr, 1643 char *buf) 1644 { 1645 struct drm_device *ddev = dev_get_drvdata(dev); 1646 struct amdgpu_device *adev = drm_to_adev(ddev); 1647 1648 if (amdgpu_in_reset(adev)) 1649 return -EPERM; 1650 if (adev->in_suspend && !adev->in_runpm) 1651 return -EPERM; 1652 1653 if (adev->unique_id) 1654 return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1655 1656 return 0; 1657 } 1658 1659 /** 1660 * DOC: thermal_throttling_logging 1661 * 1662 * Thermal throttling pulls down the clock frequency and thus the performance. 1663 * It's an useful mechanism to protect the chip from overheating. Since it 1664 * impacts performance, the user controls whether it is enabled and if so, 1665 * the log frequency. 1666 * 1667 * Reading back the file shows you the status(enabled or disabled) and 1668 * the interval(in seconds) between each thermal logging. 1669 * 1670 * Writing an integer to the file, sets a new logging interval, in seconds. 1671 * The value should be between 1 and 3600. If the value is less than 1, 1672 * thermal logging is disabled. Values greater than 3600 are ignored. 1673 */ 1674 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1675 struct device_attribute *attr, 1676 char *buf) 1677 { 1678 struct drm_device *ddev = dev_get_drvdata(dev); 1679 struct amdgpu_device *adev = drm_to_adev(ddev); 1680 1681 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 1682 adev_to_drm(adev)->unique, 1683 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1684 adev->throttling_logging_rs.interval / HZ + 1); 1685 } 1686 1687 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1688 struct device_attribute *attr, 1689 const char *buf, 1690 size_t count) 1691 { 1692 struct drm_device *ddev = dev_get_drvdata(dev); 1693 struct amdgpu_device *adev = drm_to_adev(ddev); 1694 long throttling_logging_interval; 1695 unsigned long flags; 1696 int ret = 0; 1697 1698 ret = kstrtol(buf, 0, &throttling_logging_interval); 1699 if (ret) 1700 return ret; 1701 1702 if (throttling_logging_interval > 3600) 1703 return -EINVAL; 1704 1705 if (throttling_logging_interval > 0) { 1706 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1707 /* 1708 * Reset the ratelimit timer internals. 1709 * This can effectively restart the timer. 1710 */ 1711 adev->throttling_logging_rs.interval = 1712 (throttling_logging_interval - 1) * HZ; 1713 adev->throttling_logging_rs.begin = 0; 1714 adev->throttling_logging_rs.printed = 0; 1715 adev->throttling_logging_rs.missed = 0; 1716 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1717 1718 atomic_set(&adev->throttling_logging_enabled, 1); 1719 } else { 1720 atomic_set(&adev->throttling_logging_enabled, 0); 1721 } 1722 1723 return count; 1724 } 1725 1726 /** 1727 * DOC: apu_thermal_cap 1728 * 1729 * The amdgpu driver provides a sysfs API for retrieving/updating thermal 1730 * limit temperature in millidegrees Celsius 1731 * 1732 * Reading back the file shows you core limit value 1733 * 1734 * Writing an integer to the file, sets a new thermal limit. The value 1735 * should be between 0 and 100. If the value is less than 0 or greater 1736 * than 100, then the write request will be ignored. 1737 */ 1738 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, 1739 struct device_attribute *attr, 1740 char *buf) 1741 { 1742 int ret, size; 1743 u32 limit; 1744 struct drm_device *ddev = dev_get_drvdata(dev); 1745 struct amdgpu_device *adev = drm_to_adev(ddev); 1746 1747 ret = pm_runtime_get_sync(ddev->dev); 1748 if (ret < 0) { 1749 pm_runtime_put_autosuspend(ddev->dev); 1750 return ret; 1751 } 1752 1753 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit); 1754 if (!ret) 1755 size = sysfs_emit(buf, "%u\n", limit); 1756 else 1757 size = sysfs_emit(buf, "failed to get thermal limit\n"); 1758 1759 pm_runtime_mark_last_busy(ddev->dev); 1760 pm_runtime_put_autosuspend(ddev->dev); 1761 1762 return size; 1763 } 1764 1765 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, 1766 struct device_attribute *attr, 1767 const char *buf, 1768 size_t count) 1769 { 1770 int ret; 1771 u32 value; 1772 struct drm_device *ddev = dev_get_drvdata(dev); 1773 struct amdgpu_device *adev = drm_to_adev(ddev); 1774 1775 ret = kstrtou32(buf, 10, &value); 1776 if (ret) 1777 return ret; 1778 1779 if (value > 100) { 1780 dev_err(dev, "Invalid argument !\n"); 1781 return -EINVAL; 1782 } 1783 1784 ret = pm_runtime_get_sync(ddev->dev); 1785 if (ret < 0) { 1786 pm_runtime_put_autosuspend(ddev->dev); 1787 return ret; 1788 } 1789 1790 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value); 1791 if (ret) { 1792 dev_err(dev, "failed to update thermal limit\n"); 1793 return ret; 1794 } 1795 1796 pm_runtime_mark_last_busy(ddev->dev); 1797 pm_runtime_put_autosuspend(ddev->dev); 1798 1799 return count; 1800 } 1801 1802 static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev, 1803 struct amdgpu_device_attr *attr, 1804 uint32_t mask, 1805 enum amdgpu_device_attr_states *states) 1806 { 1807 if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP) 1808 *states = ATTR_STATE_UNSUPPORTED; 1809 1810 return 0; 1811 } 1812 1813 static ssize_t amdgpu_get_pm_metrics(struct device *dev, 1814 struct device_attribute *attr, char *buf) 1815 { 1816 struct drm_device *ddev = dev_get_drvdata(dev); 1817 struct amdgpu_device *adev = drm_to_adev(ddev); 1818 ssize_t size = 0; 1819 int ret; 1820 1821 if (amdgpu_in_reset(adev)) 1822 return -EPERM; 1823 if (adev->in_suspend && !adev->in_runpm) 1824 return -EPERM; 1825 1826 ret = pm_runtime_get_sync(ddev->dev); 1827 if (ret < 0) { 1828 pm_runtime_put_autosuspend(ddev->dev); 1829 return ret; 1830 } 1831 1832 size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE); 1833 1834 pm_runtime_mark_last_busy(ddev->dev); 1835 pm_runtime_put_autosuspend(ddev->dev); 1836 1837 return size; 1838 } 1839 1840 /** 1841 * DOC: gpu_metrics 1842 * 1843 * The amdgpu driver provides a sysfs API for retrieving current gpu 1844 * metrics data. The file gpu_metrics is used for this. Reading the 1845 * file will dump all the current gpu metrics data. 1846 * 1847 * These data include temperature, frequency, engines utilization, 1848 * power consume, throttler status, fan speed and cpu core statistics( 1849 * available for APU only). That's it will give a snapshot of all sensors 1850 * at the same time. 1851 */ 1852 static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1853 struct device_attribute *attr, 1854 char *buf) 1855 { 1856 struct drm_device *ddev = dev_get_drvdata(dev); 1857 struct amdgpu_device *adev = drm_to_adev(ddev); 1858 void *gpu_metrics; 1859 ssize_t size = 0; 1860 int ret; 1861 1862 if (amdgpu_in_reset(adev)) 1863 return -EPERM; 1864 if (adev->in_suspend && !adev->in_runpm) 1865 return -EPERM; 1866 1867 ret = pm_runtime_get_sync(ddev->dev); 1868 if (ret < 0) { 1869 pm_runtime_put_autosuspend(ddev->dev); 1870 return ret; 1871 } 1872 1873 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1874 if (size <= 0) 1875 goto out; 1876 1877 if (size >= PAGE_SIZE) 1878 size = PAGE_SIZE - 1; 1879 1880 memcpy(buf, gpu_metrics, size); 1881 1882 out: 1883 pm_runtime_mark_last_busy(ddev->dev); 1884 pm_runtime_put_autosuspend(ddev->dev); 1885 1886 return size; 1887 } 1888 1889 static int amdgpu_show_powershift_percent(struct device *dev, 1890 char *buf, enum amd_pp_sensors sensor) 1891 { 1892 struct drm_device *ddev = dev_get_drvdata(dev); 1893 struct amdgpu_device *adev = drm_to_adev(ddev); 1894 uint32_t ss_power; 1895 int r = 0, i; 1896 1897 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1898 if (r == -EOPNOTSUPP) { 1899 /* sensor not available on dGPU, try to read from APU */ 1900 adev = NULL; 1901 mutex_lock(&mgpu_info.mutex); 1902 for (i = 0; i < mgpu_info.num_gpu; i++) { 1903 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { 1904 adev = mgpu_info.gpu_ins[i].adev; 1905 break; 1906 } 1907 } 1908 mutex_unlock(&mgpu_info.mutex); 1909 if (adev) 1910 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1911 } 1912 1913 if (r) 1914 return r; 1915 1916 return sysfs_emit(buf, "%u%%\n", ss_power); 1917 } 1918 1919 /** 1920 * DOC: smartshift_apu_power 1921 * 1922 * The amdgpu driver provides a sysfs API for reporting APU power 1923 * shift in percentage if platform supports smartshift. Value 0 means that 1924 * there is no powershift and values between [1-100] means that the power 1925 * is shifted to APU, the percentage of boost is with respect to APU power 1926 * limit on the platform. 1927 */ 1928 1929 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, 1930 char *buf) 1931 { 1932 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE); 1933 } 1934 1935 /** 1936 * DOC: smartshift_dgpu_power 1937 * 1938 * The amdgpu driver provides a sysfs API for reporting dGPU power 1939 * shift in percentage if platform supports smartshift. Value 0 means that 1940 * there is no powershift and values between [1-100] means that the power is 1941 * shifted to dGPU, the percentage of boost is with respect to dGPU power 1942 * limit on the platform. 1943 */ 1944 1945 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, 1946 char *buf) 1947 { 1948 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE); 1949 } 1950 1951 /** 1952 * DOC: smartshift_bias 1953 * 1954 * The amdgpu driver provides a sysfs API for reporting the 1955 * smartshift(SS2.0) bias level. The value ranges from -100 to 100 1956 * and the default is 0. -100 sets maximum preference to APU 1957 * and 100 sets max perference to dGPU. 1958 */ 1959 1960 static ssize_t amdgpu_get_smartshift_bias(struct device *dev, 1961 struct device_attribute *attr, 1962 char *buf) 1963 { 1964 int r = 0; 1965 1966 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); 1967 1968 return r; 1969 } 1970 1971 static ssize_t amdgpu_set_smartshift_bias(struct device *dev, 1972 struct device_attribute *attr, 1973 const char *buf, size_t count) 1974 { 1975 struct drm_device *ddev = dev_get_drvdata(dev); 1976 struct amdgpu_device *adev = drm_to_adev(ddev); 1977 int r = 0; 1978 int bias = 0; 1979 1980 if (amdgpu_in_reset(adev)) 1981 return -EPERM; 1982 if (adev->in_suspend && !adev->in_runpm) 1983 return -EPERM; 1984 1985 r = pm_runtime_get_sync(ddev->dev); 1986 if (r < 0) { 1987 pm_runtime_put_autosuspend(ddev->dev); 1988 return r; 1989 } 1990 1991 r = kstrtoint(buf, 10, &bias); 1992 if (r) 1993 goto out; 1994 1995 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) 1996 bias = AMDGPU_SMARTSHIFT_MAX_BIAS; 1997 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) 1998 bias = AMDGPU_SMARTSHIFT_MIN_BIAS; 1999 2000 amdgpu_smartshift_bias = bias; 2001 r = count; 2002 2003 /* TODO: update bias level with SMU message */ 2004 2005 out: 2006 pm_runtime_mark_last_busy(ddev->dev); 2007 pm_runtime_put_autosuspend(ddev->dev); 2008 return r; 2009 } 2010 2011 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2012 uint32_t mask, enum amdgpu_device_attr_states *states) 2013 { 2014 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 2015 *states = ATTR_STATE_UNSUPPORTED; 2016 2017 return 0; 2018 } 2019 2020 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2021 uint32_t mask, enum amdgpu_device_attr_states *states) 2022 { 2023 uint32_t ss_power; 2024 2025 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 2026 *states = ATTR_STATE_UNSUPPORTED; 2027 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 2028 (void *)&ss_power)) 2029 *states = ATTR_STATE_UNSUPPORTED; 2030 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 2031 (void *)&ss_power)) 2032 *states = ATTR_STATE_UNSUPPORTED; 2033 2034 return 0; 2035 } 2036 2037 static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2038 uint32_t mask, enum amdgpu_device_attr_states *states) 2039 { 2040 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2041 2042 *states = ATTR_STATE_SUPPORTED; 2043 2044 if (!amdgpu_dpm_is_overdrive_supported(adev)) { 2045 *states = ATTR_STATE_UNSUPPORTED; 2046 return 0; 2047 } 2048 2049 /* Enable pp_od_clk_voltage node for gc 9.4.3 SRIOV/BM support */ 2050 if (gc_ver == IP_VERSION(9, 4, 3)) { 2051 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2052 *states = ATTR_STATE_UNSUPPORTED; 2053 return 0; 2054 } 2055 2056 if (!(attr->flags & mask)) 2057 *states = ATTR_STATE_UNSUPPORTED; 2058 2059 return 0; 2060 } 2061 2062 /* Following items will be read out to indicate current plpd policy: 2063 * - -1: none 2064 * - 0: disallow 2065 * - 1: default 2066 * - 2: optimized 2067 */ 2068 static ssize_t amdgpu_get_xgmi_plpd_policy(struct device *dev, 2069 struct device_attribute *attr, 2070 char *buf) 2071 { 2072 struct drm_device *ddev = dev_get_drvdata(dev); 2073 struct amdgpu_device *adev = drm_to_adev(ddev); 2074 char *mode_desc = "none"; 2075 int mode; 2076 2077 if (amdgpu_in_reset(adev)) 2078 return -EPERM; 2079 if (adev->in_suspend && !adev->in_runpm) 2080 return -EPERM; 2081 2082 mode = amdgpu_dpm_get_xgmi_plpd_mode(adev, &mode_desc); 2083 2084 return sysfs_emit(buf, "%d: %s\n", mode, mode_desc); 2085 } 2086 2087 /* Following argument value is expected from user to change plpd policy 2088 * - arg 0: disallow plpd 2089 * - arg 1: default policy 2090 * - arg 2: optimized policy 2091 */ 2092 static ssize_t amdgpu_set_xgmi_plpd_policy(struct device *dev, 2093 struct device_attribute *attr, 2094 const char *buf, size_t count) 2095 { 2096 struct drm_device *ddev = dev_get_drvdata(dev); 2097 struct amdgpu_device *adev = drm_to_adev(ddev); 2098 int mode, ret; 2099 2100 if (amdgpu_in_reset(adev)) 2101 return -EPERM; 2102 if (adev->in_suspend && !adev->in_runpm) 2103 return -EPERM; 2104 2105 ret = kstrtos32(buf, 0, &mode); 2106 if (ret) 2107 return -EINVAL; 2108 2109 ret = pm_runtime_get_sync(ddev->dev); 2110 if (ret < 0) { 2111 pm_runtime_put_autosuspend(ddev->dev); 2112 return ret; 2113 } 2114 2115 ret = amdgpu_dpm_set_xgmi_plpd_mode(adev, mode); 2116 2117 pm_runtime_mark_last_busy(ddev->dev); 2118 pm_runtime_put_autosuspend(ddev->dev); 2119 2120 if (ret) 2121 return ret; 2122 2123 return count; 2124 } 2125 2126 static struct amdgpu_device_attr amdgpu_device_attrs[] = { 2127 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2128 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2129 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2130 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2131 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2132 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2133 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2134 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2135 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2136 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2137 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2138 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2139 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2140 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2141 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2142 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2143 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 2144 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 2145 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2146 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC, 2147 .attr_update = pp_od_clk_voltage_attr_update), 2148 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2149 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2150 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 2151 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2152 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2153 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2154 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2155 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2156 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, 2157 .attr_update = ss_power_attr_update), 2158 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, 2159 .attr_update = ss_power_attr_update), 2160 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, 2161 .attr_update = ss_bias_attr_update), 2162 AMDGPU_DEVICE_ATTR_RW(xgmi_plpd_policy, ATTR_FLAG_BASIC), 2163 AMDGPU_DEVICE_ATTR_RO(pm_metrics, ATTR_FLAG_BASIC, 2164 .attr_update = amdgpu_pm_metrics_attr_update), 2165 }; 2166 2167 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2168 uint32_t mask, enum amdgpu_device_attr_states *states) 2169 { 2170 struct device_attribute *dev_attr = &attr->dev_attr; 2171 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0); 2172 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2173 const char *attr_name = dev_attr->attr.name; 2174 2175 if (!(attr->flags & mask)) { 2176 *states = ATTR_STATE_UNSUPPORTED; 2177 return 0; 2178 } 2179 2180 #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) 2181 2182 if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 2183 if (gc_ver < IP_VERSION(9, 0, 0)) 2184 *states = ATTR_STATE_UNSUPPORTED; 2185 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2186 if (gc_ver < IP_VERSION(9, 0, 0) || 2187 !amdgpu_device_has_display_hardware(adev)) 2188 *states = ATTR_STATE_UNSUPPORTED; 2189 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 2190 if (mp1_ver < IP_VERSION(10, 0, 0)) 2191 *states = ATTR_STATE_UNSUPPORTED; 2192 } else if (DEVICE_ATTR_IS(mem_busy_percent)) { 2193 if ((adev->flags & AMD_IS_APU && 2194 gc_ver != IP_VERSION(9, 4, 3)) || 2195 gc_ver == IP_VERSION(9, 0, 1)) 2196 *states = ATTR_STATE_UNSUPPORTED; 2197 } else if (DEVICE_ATTR_IS(pcie_bw)) { 2198 /* PCIe Perf counters won't work on APU nodes */ 2199 if (adev->flags & AMD_IS_APU || 2200 !adev->asic_funcs->get_pcie_usage) 2201 *states = ATTR_STATE_UNSUPPORTED; 2202 } else if (DEVICE_ATTR_IS(unique_id)) { 2203 switch (gc_ver) { 2204 case IP_VERSION(9, 0, 1): 2205 case IP_VERSION(9, 4, 0): 2206 case IP_VERSION(9, 4, 1): 2207 case IP_VERSION(9, 4, 2): 2208 case IP_VERSION(9, 4, 3): 2209 case IP_VERSION(10, 3, 0): 2210 case IP_VERSION(11, 0, 0): 2211 case IP_VERSION(11, 0, 1): 2212 case IP_VERSION(11, 0, 2): 2213 case IP_VERSION(11, 0, 3): 2214 *states = ATTR_STATE_SUPPORTED; 2215 break; 2216 default: 2217 *states = ATTR_STATE_UNSUPPORTED; 2218 } 2219 } else if (DEVICE_ATTR_IS(pp_features)) { 2220 if ((adev->flags & AMD_IS_APU && 2221 gc_ver != IP_VERSION(9, 4, 3)) || 2222 gc_ver < IP_VERSION(9, 0, 0)) 2223 *states = ATTR_STATE_UNSUPPORTED; 2224 } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2225 if (gc_ver < IP_VERSION(9, 1, 0)) 2226 *states = ATTR_STATE_UNSUPPORTED; 2227 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 2228 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2229 gc_ver == IP_VERSION(10, 3, 0) || 2230 gc_ver == IP_VERSION(10, 1, 2) || 2231 gc_ver == IP_VERSION(11, 0, 0) || 2232 gc_ver == IP_VERSION(11, 0, 2) || 2233 gc_ver == IP_VERSION(11, 0, 3) || 2234 gc_ver == IP_VERSION(9, 4, 3))) 2235 *states = ATTR_STATE_UNSUPPORTED; 2236 } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { 2237 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2238 gc_ver == IP_VERSION(10, 3, 0) || 2239 gc_ver == IP_VERSION(11, 0, 2) || 2240 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2241 *states = ATTR_STATE_UNSUPPORTED; 2242 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 2243 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2244 gc_ver == IP_VERSION(10, 3, 0) || 2245 gc_ver == IP_VERSION(10, 1, 2) || 2246 gc_ver == IP_VERSION(11, 0, 0) || 2247 gc_ver == IP_VERSION(11, 0, 2) || 2248 gc_ver == IP_VERSION(11, 0, 3) || 2249 gc_ver == IP_VERSION(9, 4, 3))) 2250 *states = ATTR_STATE_UNSUPPORTED; 2251 } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { 2252 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2253 gc_ver == IP_VERSION(10, 3, 0) || 2254 gc_ver == IP_VERSION(11, 0, 2) || 2255 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2256 *states = ATTR_STATE_UNSUPPORTED; 2257 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { 2258 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) 2259 *states = ATTR_STATE_UNSUPPORTED; 2260 else if ((gc_ver == IP_VERSION(10, 3, 0) || 2261 gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev)) 2262 *states = ATTR_STATE_UNSUPPORTED; 2263 } else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) { 2264 if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE) 2265 *states = ATTR_STATE_UNSUPPORTED; 2266 } else if (DEVICE_ATTR_IS(pp_mclk_od)) { 2267 if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP) 2268 *states = ATTR_STATE_UNSUPPORTED; 2269 } else if (DEVICE_ATTR_IS(pp_sclk_od)) { 2270 if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP) 2271 *states = ATTR_STATE_UNSUPPORTED; 2272 } else if (DEVICE_ATTR_IS(apu_thermal_cap)) { 2273 u32 limit; 2274 2275 if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) == 2276 -EOPNOTSUPP) 2277 *states = ATTR_STATE_UNSUPPORTED; 2278 } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { 2279 if (gc_ver == IP_VERSION(9, 4, 2) || 2280 gc_ver == IP_VERSION(9, 4, 3)) 2281 *states = ATTR_STATE_UNSUPPORTED; 2282 } 2283 2284 switch (gc_ver) { 2285 case IP_VERSION(9, 4, 1): 2286 case IP_VERSION(9, 4, 2): 2287 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 2288 if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2289 DEVICE_ATTR_IS(pp_dpm_socclk) || 2290 DEVICE_ATTR_IS(pp_dpm_fclk)) { 2291 dev_attr->attr.mode &= ~S_IWUGO; 2292 dev_attr->store = NULL; 2293 } 2294 break; 2295 case IP_VERSION(10, 3, 0): 2296 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) && 2297 amdgpu_sriov_vf(adev)) { 2298 dev_attr->attr.mode &= ~0222; 2299 dev_attr->store = NULL; 2300 } 2301 break; 2302 default: 2303 break; 2304 } 2305 2306 if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2307 /* SMU MP1 does not support dcefclk level setting */ 2308 if (gc_ver >= IP_VERSION(10, 0, 0)) { 2309 dev_attr->attr.mode &= ~S_IWUGO; 2310 dev_attr->store = NULL; 2311 } 2312 } 2313 2314 /* setting should not be allowed from VF if not in one VF mode */ 2315 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 2316 dev_attr->attr.mode &= ~S_IWUGO; 2317 dev_attr->store = NULL; 2318 } 2319 2320 #undef DEVICE_ATTR_IS 2321 2322 return 0; 2323 } 2324 2325 2326 static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2327 struct amdgpu_device_attr *attr, 2328 uint32_t mask, struct list_head *attr_list) 2329 { 2330 int ret = 0; 2331 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2332 struct amdgpu_device_attr_entry *attr_entry; 2333 struct device_attribute *dev_attr; 2334 const char *name; 2335 2336 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2337 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2338 2339 if (!attr) 2340 return -EINVAL; 2341 2342 dev_attr = &attr->dev_attr; 2343 name = dev_attr->attr.name; 2344 2345 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; 2346 2347 ret = attr_update(adev, attr, mask, &attr_states); 2348 if (ret) { 2349 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2350 name, ret); 2351 return ret; 2352 } 2353 2354 if (attr_states == ATTR_STATE_UNSUPPORTED) 2355 return 0; 2356 2357 ret = device_create_file(adev->dev, dev_attr); 2358 if (ret) { 2359 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2360 name, ret); 2361 } 2362 2363 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2364 if (!attr_entry) 2365 return -ENOMEM; 2366 2367 attr_entry->attr = attr; 2368 INIT_LIST_HEAD(&attr_entry->entry); 2369 2370 list_add_tail(&attr_entry->entry, attr_list); 2371 2372 return ret; 2373 } 2374 2375 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2376 { 2377 struct device_attribute *dev_attr = &attr->dev_attr; 2378 2379 device_remove_file(adev->dev, dev_attr); 2380 } 2381 2382 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2383 struct list_head *attr_list); 2384 2385 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2386 struct amdgpu_device_attr *attrs, 2387 uint32_t counts, 2388 uint32_t mask, 2389 struct list_head *attr_list) 2390 { 2391 int ret = 0; 2392 uint32_t i = 0; 2393 2394 for (i = 0; i < counts; i++) { 2395 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2396 if (ret) 2397 goto failed; 2398 } 2399 2400 return 0; 2401 2402 failed: 2403 amdgpu_device_attr_remove_groups(adev, attr_list); 2404 2405 return ret; 2406 } 2407 2408 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2409 struct list_head *attr_list) 2410 { 2411 struct amdgpu_device_attr_entry *entry, *entry_tmp; 2412 2413 if (list_empty(attr_list)) 2414 return ; 2415 2416 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2417 amdgpu_device_attr_remove(adev, entry->attr); 2418 list_del(&entry->entry); 2419 kfree(entry); 2420 } 2421 } 2422 2423 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2424 struct device_attribute *attr, 2425 char *buf) 2426 { 2427 struct amdgpu_device *adev = dev_get_drvdata(dev); 2428 int channel = to_sensor_dev_attr(attr)->index; 2429 int r, temp = 0; 2430 2431 if (channel >= PP_TEMP_MAX) 2432 return -EINVAL; 2433 2434 switch (channel) { 2435 case PP_TEMP_JUNCTION: 2436 /* get current junction temperature */ 2437 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2438 (void *)&temp); 2439 break; 2440 case PP_TEMP_EDGE: 2441 /* get current edge temperature */ 2442 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2443 (void *)&temp); 2444 break; 2445 case PP_TEMP_MEM: 2446 /* get current memory temperature */ 2447 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2448 (void *)&temp); 2449 break; 2450 default: 2451 r = -EINVAL; 2452 break; 2453 } 2454 2455 if (r) 2456 return r; 2457 2458 return sysfs_emit(buf, "%d\n", temp); 2459 } 2460 2461 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2462 struct device_attribute *attr, 2463 char *buf) 2464 { 2465 struct amdgpu_device *adev = dev_get_drvdata(dev); 2466 int hyst = to_sensor_dev_attr(attr)->index; 2467 int temp; 2468 2469 if (hyst) 2470 temp = adev->pm.dpm.thermal.min_temp; 2471 else 2472 temp = adev->pm.dpm.thermal.max_temp; 2473 2474 return sysfs_emit(buf, "%d\n", temp); 2475 } 2476 2477 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2478 struct device_attribute *attr, 2479 char *buf) 2480 { 2481 struct amdgpu_device *adev = dev_get_drvdata(dev); 2482 int hyst = to_sensor_dev_attr(attr)->index; 2483 int temp; 2484 2485 if (hyst) 2486 temp = adev->pm.dpm.thermal.min_hotspot_temp; 2487 else 2488 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2489 2490 return sysfs_emit(buf, "%d\n", temp); 2491 } 2492 2493 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2494 struct device_attribute *attr, 2495 char *buf) 2496 { 2497 struct amdgpu_device *adev = dev_get_drvdata(dev); 2498 int hyst = to_sensor_dev_attr(attr)->index; 2499 int temp; 2500 2501 if (hyst) 2502 temp = adev->pm.dpm.thermal.min_mem_temp; 2503 else 2504 temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2505 2506 return sysfs_emit(buf, "%d\n", temp); 2507 } 2508 2509 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2510 struct device_attribute *attr, 2511 char *buf) 2512 { 2513 int channel = to_sensor_dev_attr(attr)->index; 2514 2515 if (channel >= PP_TEMP_MAX) 2516 return -EINVAL; 2517 2518 return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2519 } 2520 2521 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2522 struct device_attribute *attr, 2523 char *buf) 2524 { 2525 struct amdgpu_device *adev = dev_get_drvdata(dev); 2526 int channel = to_sensor_dev_attr(attr)->index; 2527 int temp = 0; 2528 2529 if (channel >= PP_TEMP_MAX) 2530 return -EINVAL; 2531 2532 switch (channel) { 2533 case PP_TEMP_JUNCTION: 2534 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2535 break; 2536 case PP_TEMP_EDGE: 2537 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2538 break; 2539 case PP_TEMP_MEM: 2540 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2541 break; 2542 } 2543 2544 return sysfs_emit(buf, "%d\n", temp); 2545 } 2546 2547 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2548 struct device_attribute *attr, 2549 char *buf) 2550 { 2551 struct amdgpu_device *adev = dev_get_drvdata(dev); 2552 u32 pwm_mode = 0; 2553 int ret; 2554 2555 if (amdgpu_in_reset(adev)) 2556 return -EPERM; 2557 if (adev->in_suspend && !adev->in_runpm) 2558 return -EPERM; 2559 2560 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2561 if (ret < 0) { 2562 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2563 return ret; 2564 } 2565 2566 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2567 2568 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2569 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2570 2571 if (ret) 2572 return -EINVAL; 2573 2574 return sysfs_emit(buf, "%u\n", pwm_mode); 2575 } 2576 2577 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2578 struct device_attribute *attr, 2579 const char *buf, 2580 size_t count) 2581 { 2582 struct amdgpu_device *adev = dev_get_drvdata(dev); 2583 int err, ret; 2584 int value; 2585 2586 if (amdgpu_in_reset(adev)) 2587 return -EPERM; 2588 if (adev->in_suspend && !adev->in_runpm) 2589 return -EPERM; 2590 2591 err = kstrtoint(buf, 10, &value); 2592 if (err) 2593 return err; 2594 2595 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2596 if (ret < 0) { 2597 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2598 return ret; 2599 } 2600 2601 ret = amdgpu_dpm_set_fan_control_mode(adev, value); 2602 2603 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2604 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2605 2606 if (ret) 2607 return -EINVAL; 2608 2609 return count; 2610 } 2611 2612 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2613 struct device_attribute *attr, 2614 char *buf) 2615 { 2616 return sysfs_emit(buf, "%i\n", 0); 2617 } 2618 2619 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2620 struct device_attribute *attr, 2621 char *buf) 2622 { 2623 return sysfs_emit(buf, "%i\n", 255); 2624 } 2625 2626 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2627 struct device_attribute *attr, 2628 const char *buf, size_t count) 2629 { 2630 struct amdgpu_device *adev = dev_get_drvdata(dev); 2631 int err; 2632 u32 value; 2633 u32 pwm_mode; 2634 2635 if (amdgpu_in_reset(adev)) 2636 return -EPERM; 2637 if (adev->in_suspend && !adev->in_runpm) 2638 return -EPERM; 2639 2640 err = kstrtou32(buf, 10, &value); 2641 if (err) 2642 return err; 2643 2644 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2645 if (err < 0) { 2646 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2647 return err; 2648 } 2649 2650 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2651 if (err) 2652 goto out; 2653 2654 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2655 pr_info("manual fan speed control should be enabled first\n"); 2656 err = -EINVAL; 2657 goto out; 2658 } 2659 2660 err = amdgpu_dpm_set_fan_speed_pwm(adev, value); 2661 2662 out: 2663 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2664 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2665 2666 if (err) 2667 return err; 2668 2669 return count; 2670 } 2671 2672 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2673 struct device_attribute *attr, 2674 char *buf) 2675 { 2676 struct amdgpu_device *adev = dev_get_drvdata(dev); 2677 int err; 2678 u32 speed = 0; 2679 2680 if (amdgpu_in_reset(adev)) 2681 return -EPERM; 2682 if (adev->in_suspend && !adev->in_runpm) 2683 return -EPERM; 2684 2685 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2686 if (err < 0) { 2687 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2688 return err; 2689 } 2690 2691 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); 2692 2693 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2694 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2695 2696 if (err) 2697 return err; 2698 2699 return sysfs_emit(buf, "%i\n", speed); 2700 } 2701 2702 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2703 struct device_attribute *attr, 2704 char *buf) 2705 { 2706 struct amdgpu_device *adev = dev_get_drvdata(dev); 2707 int err; 2708 u32 speed = 0; 2709 2710 if (amdgpu_in_reset(adev)) 2711 return -EPERM; 2712 if (adev->in_suspend && !adev->in_runpm) 2713 return -EPERM; 2714 2715 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2716 if (err < 0) { 2717 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2718 return err; 2719 } 2720 2721 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2722 2723 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2724 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2725 2726 if (err) 2727 return err; 2728 2729 return sysfs_emit(buf, "%i\n", speed); 2730 } 2731 2732 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2733 struct device_attribute *attr, 2734 char *buf) 2735 { 2736 struct amdgpu_device *adev = dev_get_drvdata(dev); 2737 u32 min_rpm = 0; 2738 int r; 2739 2740 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2741 (void *)&min_rpm); 2742 2743 if (r) 2744 return r; 2745 2746 return sysfs_emit(buf, "%d\n", min_rpm); 2747 } 2748 2749 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2750 struct device_attribute *attr, 2751 char *buf) 2752 { 2753 struct amdgpu_device *adev = dev_get_drvdata(dev); 2754 u32 max_rpm = 0; 2755 int r; 2756 2757 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2758 (void *)&max_rpm); 2759 2760 if (r) 2761 return r; 2762 2763 return sysfs_emit(buf, "%d\n", max_rpm); 2764 } 2765 2766 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2767 struct device_attribute *attr, 2768 char *buf) 2769 { 2770 struct amdgpu_device *adev = dev_get_drvdata(dev); 2771 int err; 2772 u32 rpm = 0; 2773 2774 if (amdgpu_in_reset(adev)) 2775 return -EPERM; 2776 if (adev->in_suspend && !adev->in_runpm) 2777 return -EPERM; 2778 2779 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2780 if (err < 0) { 2781 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2782 return err; 2783 } 2784 2785 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2786 2787 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2788 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2789 2790 if (err) 2791 return err; 2792 2793 return sysfs_emit(buf, "%i\n", rpm); 2794 } 2795 2796 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2797 struct device_attribute *attr, 2798 const char *buf, size_t count) 2799 { 2800 struct amdgpu_device *adev = dev_get_drvdata(dev); 2801 int err; 2802 u32 value; 2803 u32 pwm_mode; 2804 2805 if (amdgpu_in_reset(adev)) 2806 return -EPERM; 2807 if (adev->in_suspend && !adev->in_runpm) 2808 return -EPERM; 2809 2810 err = kstrtou32(buf, 10, &value); 2811 if (err) 2812 return err; 2813 2814 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2815 if (err < 0) { 2816 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2817 return err; 2818 } 2819 2820 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2821 if (err) 2822 goto out; 2823 2824 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2825 err = -ENODATA; 2826 goto out; 2827 } 2828 2829 err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2830 2831 out: 2832 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2833 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2834 2835 if (err) 2836 return err; 2837 2838 return count; 2839 } 2840 2841 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2842 struct device_attribute *attr, 2843 char *buf) 2844 { 2845 struct amdgpu_device *adev = dev_get_drvdata(dev); 2846 u32 pwm_mode = 0; 2847 int ret; 2848 2849 if (amdgpu_in_reset(adev)) 2850 return -EPERM; 2851 if (adev->in_suspend && !adev->in_runpm) 2852 return -EPERM; 2853 2854 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2855 if (ret < 0) { 2856 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2857 return ret; 2858 } 2859 2860 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2861 2862 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2863 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2864 2865 if (ret) 2866 return -EINVAL; 2867 2868 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2869 } 2870 2871 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2872 struct device_attribute *attr, 2873 const char *buf, 2874 size_t count) 2875 { 2876 struct amdgpu_device *adev = dev_get_drvdata(dev); 2877 int err; 2878 int value; 2879 u32 pwm_mode; 2880 2881 if (amdgpu_in_reset(adev)) 2882 return -EPERM; 2883 if (adev->in_suspend && !adev->in_runpm) 2884 return -EPERM; 2885 2886 err = kstrtoint(buf, 10, &value); 2887 if (err) 2888 return err; 2889 2890 if (value == 0) 2891 pwm_mode = AMD_FAN_CTRL_AUTO; 2892 else if (value == 1) 2893 pwm_mode = AMD_FAN_CTRL_MANUAL; 2894 else 2895 return -EINVAL; 2896 2897 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2898 if (err < 0) { 2899 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2900 return err; 2901 } 2902 2903 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2904 2905 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2906 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2907 2908 if (err) 2909 return -EINVAL; 2910 2911 return count; 2912 } 2913 2914 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 2915 struct device_attribute *attr, 2916 char *buf) 2917 { 2918 struct amdgpu_device *adev = dev_get_drvdata(dev); 2919 u32 vddgfx; 2920 int r; 2921 2922 /* get the voltage */ 2923 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX, 2924 (void *)&vddgfx); 2925 if (r) 2926 return r; 2927 2928 return sysfs_emit(buf, "%d\n", vddgfx); 2929 } 2930 2931 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 2932 struct device_attribute *attr, 2933 char *buf) 2934 { 2935 return sysfs_emit(buf, "vddgfx\n"); 2936 } 2937 2938 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 2939 struct device_attribute *attr, 2940 char *buf) 2941 { 2942 struct amdgpu_device *adev = dev_get_drvdata(dev); 2943 u32 vddnb; 2944 int r; 2945 2946 /* only APUs have vddnb */ 2947 if (!(adev->flags & AMD_IS_APU)) 2948 return -EINVAL; 2949 2950 /* get the voltage */ 2951 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB, 2952 (void *)&vddnb); 2953 if (r) 2954 return r; 2955 2956 return sysfs_emit(buf, "%d\n", vddnb); 2957 } 2958 2959 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 2960 struct device_attribute *attr, 2961 char *buf) 2962 { 2963 return sysfs_emit(buf, "vddnb\n"); 2964 } 2965 2966 static int amdgpu_hwmon_get_power(struct device *dev, 2967 enum amd_pp_sensors sensor) 2968 { 2969 struct amdgpu_device *adev = dev_get_drvdata(dev); 2970 unsigned int uw; 2971 u32 query = 0; 2972 int r; 2973 2974 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query); 2975 if (r) 2976 return r; 2977 2978 /* convert to microwatts */ 2979 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 2980 2981 return uw; 2982 } 2983 2984 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 2985 struct device_attribute *attr, 2986 char *buf) 2987 { 2988 ssize_t val; 2989 2990 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER); 2991 if (val < 0) 2992 return val; 2993 2994 return sysfs_emit(buf, "%zd\n", val); 2995 } 2996 2997 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev, 2998 struct device_attribute *attr, 2999 char *buf) 3000 { 3001 ssize_t val; 3002 3003 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER); 3004 if (val < 0) 3005 return val; 3006 3007 return sysfs_emit(buf, "%zd\n", val); 3008 } 3009 3010 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, 3011 struct device_attribute *attr, 3012 char *buf, 3013 enum pp_power_limit_level pp_limit_level) 3014 { 3015 struct amdgpu_device *adev = dev_get_drvdata(dev); 3016 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; 3017 uint32_t limit; 3018 ssize_t size; 3019 int r; 3020 3021 if (amdgpu_in_reset(adev)) 3022 return -EPERM; 3023 if (adev->in_suspend && !adev->in_runpm) 3024 return -EPERM; 3025 3026 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3027 if (r < 0) { 3028 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3029 return r; 3030 } 3031 3032 r = amdgpu_dpm_get_power_limit(adev, &limit, 3033 pp_limit_level, power_type); 3034 3035 if (!r) 3036 size = sysfs_emit(buf, "%u\n", limit * 1000000); 3037 else 3038 size = sysfs_emit(buf, "\n"); 3039 3040 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3041 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3042 3043 return size; 3044 } 3045 3046 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 3047 struct device_attribute *attr, 3048 char *buf) 3049 { 3050 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN); 3051 } 3052 3053 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 3054 struct device_attribute *attr, 3055 char *buf) 3056 { 3057 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); 3058 3059 } 3060 3061 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 3062 struct device_attribute *attr, 3063 char *buf) 3064 { 3065 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); 3066 3067 } 3068 3069 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 3070 struct device_attribute *attr, 3071 char *buf) 3072 { 3073 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); 3074 3075 } 3076 3077 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 3078 struct device_attribute *attr, 3079 char *buf) 3080 { 3081 struct amdgpu_device *adev = dev_get_drvdata(dev); 3082 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 3083 3084 if (gc_ver == IP_VERSION(10, 3, 1)) 3085 return sysfs_emit(buf, "%s\n", 3086 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? 3087 "fastPPT" : "slowPPT"); 3088 else 3089 return sysfs_emit(buf, "PPT\n"); 3090 } 3091 3092 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 3093 struct device_attribute *attr, 3094 const char *buf, 3095 size_t count) 3096 { 3097 struct amdgpu_device *adev = dev_get_drvdata(dev); 3098 int limit_type = to_sensor_dev_attr(attr)->index; 3099 int err; 3100 u32 value; 3101 3102 if (amdgpu_in_reset(adev)) 3103 return -EPERM; 3104 if (adev->in_suspend && !adev->in_runpm) 3105 return -EPERM; 3106 3107 if (amdgpu_sriov_vf(adev)) 3108 return -EINVAL; 3109 3110 err = kstrtou32(buf, 10, &value); 3111 if (err) 3112 return err; 3113 3114 value = value / 1000000; /* convert to Watt */ 3115 value |= limit_type << 24; 3116 3117 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3118 if (err < 0) { 3119 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3120 return err; 3121 } 3122 3123 err = amdgpu_dpm_set_power_limit(adev, value); 3124 3125 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3126 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3127 3128 if (err) 3129 return err; 3130 3131 return count; 3132 } 3133 3134 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 3135 struct device_attribute *attr, 3136 char *buf) 3137 { 3138 struct amdgpu_device *adev = dev_get_drvdata(dev); 3139 uint32_t sclk; 3140 int r; 3141 3142 /* get the sclk */ 3143 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 3144 (void *)&sclk); 3145 if (r) 3146 return r; 3147 3148 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 3149 } 3150 3151 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 3152 struct device_attribute *attr, 3153 char *buf) 3154 { 3155 return sysfs_emit(buf, "sclk\n"); 3156 } 3157 3158 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 3159 struct device_attribute *attr, 3160 char *buf) 3161 { 3162 struct amdgpu_device *adev = dev_get_drvdata(dev); 3163 uint32_t mclk; 3164 int r; 3165 3166 /* get the sclk */ 3167 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 3168 (void *)&mclk); 3169 if (r) 3170 return r; 3171 3172 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 3173 } 3174 3175 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 3176 struct device_attribute *attr, 3177 char *buf) 3178 { 3179 return sysfs_emit(buf, "mclk\n"); 3180 } 3181 3182 /** 3183 * DOC: hwmon 3184 * 3185 * The amdgpu driver exposes the following sensor interfaces: 3186 * 3187 * - GPU temperature (via the on-die sensor) 3188 * 3189 * - GPU voltage 3190 * 3191 * - Northbridge voltage (APUs only) 3192 * 3193 * - GPU power 3194 * 3195 * - GPU fan 3196 * 3197 * - GPU gfx/compute engine clock 3198 * 3199 * - GPU memory clock (dGPU only) 3200 * 3201 * hwmon interfaces for GPU temperature: 3202 * 3203 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3204 * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3205 * 3206 * - temp[1-3]_label: temperature channel label 3207 * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3208 * 3209 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3210 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3211 * 3212 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3213 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3214 * 3215 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3216 * - these are supported on SOC15 dGPUs only 3217 * 3218 * hwmon interfaces for GPU voltage: 3219 * 3220 * - in0_input: the voltage on the GPU in millivolts 3221 * 3222 * - in1_input: the voltage on the Northbridge in millivolts 3223 * 3224 * hwmon interfaces for GPU power: 3225 * 3226 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. 3227 * 3228 * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU. 3229 * 3230 * - power1_cap_min: minimum cap supported in microWatts 3231 * 3232 * - power1_cap_max: maximum cap supported in microWatts 3233 * 3234 * - power1_cap: selected power cap in microWatts 3235 * 3236 * hwmon interfaces for GPU fan: 3237 * 3238 * - pwm1: pulse width modulation fan level (0-255) 3239 * 3240 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3241 * 3242 * - pwm1_min: pulse width modulation fan control minimum level (0) 3243 * 3244 * - pwm1_max: pulse width modulation fan control maximum level (255) 3245 * 3246 * - fan1_min: a minimum value Unit: revolution/min (RPM) 3247 * 3248 * - fan1_max: a maximum value Unit: revolution/max (RPM) 3249 * 3250 * - fan1_input: fan speed in RPM 3251 * 3252 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3253 * 3254 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3255 * 3256 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. 3257 * That will get the former one overridden. 3258 * 3259 * hwmon interfaces for GPU clocks: 3260 * 3261 * - freq1_input: the gfx/compute clock in hertz 3262 * 3263 * - freq2_input: the memory clock in hertz 3264 * 3265 * You can use hwmon tools like sensors to view this information on your system. 3266 * 3267 */ 3268 3269 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3270 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3271 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3272 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3273 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3274 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3275 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3276 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3277 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3278 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3279 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3280 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3281 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3282 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3283 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3284 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3285 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3286 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3287 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3288 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3289 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3290 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3291 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3292 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3293 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3294 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3295 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3296 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3297 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3298 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0); 3299 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3300 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3301 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3302 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3303 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3304 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3305 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3306 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3307 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 3308 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3309 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3310 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3311 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3312 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3313 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3314 3315 static struct attribute *hwmon_attributes[] = { 3316 &sensor_dev_attr_temp1_input.dev_attr.attr, 3317 &sensor_dev_attr_temp1_crit.dev_attr.attr, 3318 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3319 &sensor_dev_attr_temp2_input.dev_attr.attr, 3320 &sensor_dev_attr_temp2_crit.dev_attr.attr, 3321 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3322 &sensor_dev_attr_temp3_input.dev_attr.attr, 3323 &sensor_dev_attr_temp3_crit.dev_attr.attr, 3324 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3325 &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3326 &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3327 &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3328 &sensor_dev_attr_temp1_label.dev_attr.attr, 3329 &sensor_dev_attr_temp2_label.dev_attr.attr, 3330 &sensor_dev_attr_temp3_label.dev_attr.attr, 3331 &sensor_dev_attr_pwm1.dev_attr.attr, 3332 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3333 &sensor_dev_attr_pwm1_min.dev_attr.attr, 3334 &sensor_dev_attr_pwm1_max.dev_attr.attr, 3335 &sensor_dev_attr_fan1_input.dev_attr.attr, 3336 &sensor_dev_attr_fan1_min.dev_attr.attr, 3337 &sensor_dev_attr_fan1_max.dev_attr.attr, 3338 &sensor_dev_attr_fan1_target.dev_attr.attr, 3339 &sensor_dev_attr_fan1_enable.dev_attr.attr, 3340 &sensor_dev_attr_in0_input.dev_attr.attr, 3341 &sensor_dev_attr_in0_label.dev_attr.attr, 3342 &sensor_dev_attr_in1_input.dev_attr.attr, 3343 &sensor_dev_attr_in1_label.dev_attr.attr, 3344 &sensor_dev_attr_power1_average.dev_attr.attr, 3345 &sensor_dev_attr_power1_input.dev_attr.attr, 3346 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3347 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3348 &sensor_dev_attr_power1_cap.dev_attr.attr, 3349 &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3350 &sensor_dev_attr_power1_label.dev_attr.attr, 3351 &sensor_dev_attr_power2_average.dev_attr.attr, 3352 &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3353 &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3354 &sensor_dev_attr_power2_cap.dev_attr.attr, 3355 &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3356 &sensor_dev_attr_power2_label.dev_attr.attr, 3357 &sensor_dev_attr_freq1_input.dev_attr.attr, 3358 &sensor_dev_attr_freq1_label.dev_attr.attr, 3359 &sensor_dev_attr_freq2_input.dev_attr.attr, 3360 &sensor_dev_attr_freq2_label.dev_attr.attr, 3361 NULL 3362 }; 3363 3364 static umode_t hwmon_attributes_visible(struct kobject *kobj, 3365 struct attribute *attr, int index) 3366 { 3367 struct device *dev = kobj_to_dev(kobj); 3368 struct amdgpu_device *adev = dev_get_drvdata(dev); 3369 umode_t effective_mode = attr->mode; 3370 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 3371 uint32_t tmp; 3372 3373 /* under pp one vf mode manage of hwmon attributes is not supported */ 3374 if (amdgpu_sriov_is_pp_one_vf(adev)) 3375 effective_mode &= ~S_IWUSR; 3376 3377 /* Skip fan attributes if fan is not present */ 3378 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3379 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3380 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3381 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3382 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3383 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3384 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3385 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3386 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3387 return 0; 3388 3389 /* Skip fan attributes on APU */ 3390 if ((adev->flags & AMD_IS_APU) && 3391 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3392 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3393 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3394 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3395 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3396 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3397 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3398 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3399 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3400 return 0; 3401 3402 /* Skip crit temp on APU */ 3403 if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || 3404 (gc_ver == IP_VERSION(9, 4, 3))) && 3405 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3406 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3407 return 0; 3408 3409 /* Skip limit attributes if DPM is not enabled */ 3410 if (!adev->pm.dpm_enabled && 3411 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3412 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3413 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3414 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3415 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3416 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3417 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3418 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3419 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3420 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3421 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3422 return 0; 3423 3424 /* mask fan attributes if we have no bindings for this asic to expose */ 3425 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3426 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3427 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && 3428 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3429 effective_mode &= ~S_IRUGO; 3430 3431 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3432 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3433 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && 3434 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3435 effective_mode &= ~S_IWUSR; 3436 3437 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ 3438 if (((adev->family == AMDGPU_FAMILY_SI) || 3439 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && 3440 (gc_ver != IP_VERSION(9, 4, 3)))) && 3441 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3442 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3443 attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3444 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3445 return 0; 3446 3447 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ 3448 if (((adev->family == AMDGPU_FAMILY_SI) || 3449 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && 3450 (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3451 return 0; 3452 3453 /* not all products support both average and instantaneous */ 3454 if (attr == &sensor_dev_attr_power1_average.dev_attr.attr && 3455 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP) 3456 return 0; 3457 if (attr == &sensor_dev_attr_power1_input.dev_attr.attr && 3458 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP) 3459 return 0; 3460 3461 /* hide max/min values if we can't both query and manage the fan */ 3462 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3463 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3464 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3465 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && 3466 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3467 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3468 return 0; 3469 3470 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3471 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && 3472 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3473 attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3474 return 0; 3475 3476 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3477 adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ 3478 (gc_ver == IP_VERSION(9, 4, 3))) && 3479 (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3480 attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3481 return 0; 3482 3483 /* only APUs other than gc 9,4,3 have vddnb */ 3484 if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) && 3485 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3486 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3487 return 0; 3488 3489 /* no mclk on APUs other than gc 9,4,3*/ 3490 if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) && 3491 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3492 attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3493 return 0; 3494 3495 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3496 (gc_ver != IP_VERSION(9, 4, 3)) && 3497 (attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3498 attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3499 attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3500 attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3501 attr == &sensor_dev_attr_temp3_label.dev_attr.attr || 3502 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr)) 3503 return 0; 3504 3505 /* hotspot temperature for gc 9,4,3*/ 3506 if (gc_ver == IP_VERSION(9, 4, 3)) { 3507 if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr || 3508 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3509 attr == &sensor_dev_attr_temp1_label.dev_attr.attr) 3510 return 0; 3511 3512 if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3513 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr) 3514 return attr->mode; 3515 } 3516 3517 /* only SOC15 dGPUs support hotspot and mem temperatures */ 3518 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3519 (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3520 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3521 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3522 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3523 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)) 3524 return 0; 3525 3526 /* only Vangogh has fast PPT limit and power labels */ 3527 if (!(gc_ver == IP_VERSION(10, 3, 1)) && 3528 (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3529 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3530 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3531 attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 3532 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3533 attr == &sensor_dev_attr_power2_label.dev_attr.attr)) 3534 return 0; 3535 3536 return effective_mode; 3537 } 3538 3539 static const struct attribute_group hwmon_attrgroup = { 3540 .attrs = hwmon_attributes, 3541 .is_visible = hwmon_attributes_visible, 3542 }; 3543 3544 static const struct attribute_group *hwmon_groups[] = { 3545 &hwmon_attrgroup, 3546 NULL 3547 }; 3548 3549 static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev, 3550 enum pp_clock_type od_type, 3551 char *buf) 3552 { 3553 int size = 0; 3554 int ret; 3555 3556 if (amdgpu_in_reset(adev)) 3557 return -EPERM; 3558 if (adev->in_suspend && !adev->in_runpm) 3559 return -EPERM; 3560 3561 ret = pm_runtime_get_sync(adev->dev); 3562 if (ret < 0) { 3563 pm_runtime_put_autosuspend(adev->dev); 3564 return ret; 3565 } 3566 3567 size = amdgpu_dpm_print_clock_levels(adev, od_type, buf); 3568 if (size == 0) 3569 size = sysfs_emit(buf, "\n"); 3570 3571 pm_runtime_mark_last_busy(adev->dev); 3572 pm_runtime_put_autosuspend(adev->dev); 3573 3574 return size; 3575 } 3576 3577 static int parse_input_od_command_lines(const char *buf, 3578 size_t count, 3579 u32 *type, 3580 long *params, 3581 uint32_t *num_of_params) 3582 { 3583 const char delimiter[3] = {' ', '\n', '\0'}; 3584 uint32_t parameter_size = 0; 3585 char buf_cpy[128] = {0}; 3586 char *tmp_str, *sub_str; 3587 int ret; 3588 3589 if (count > sizeof(buf_cpy) - 1) 3590 return -EINVAL; 3591 3592 memcpy(buf_cpy, buf, count); 3593 tmp_str = buf_cpy; 3594 3595 /* skip heading spaces */ 3596 while (isspace(*tmp_str)) 3597 tmp_str++; 3598 3599 switch (*tmp_str) { 3600 case 'c': 3601 *type = PP_OD_COMMIT_DPM_TABLE; 3602 return 0; 3603 case 'r': 3604 params[parameter_size] = *type; 3605 *num_of_params = 1; 3606 *type = PP_OD_RESTORE_DEFAULT_TABLE; 3607 return 0; 3608 default: 3609 break; 3610 } 3611 3612 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 3613 if (strlen(sub_str) == 0) 3614 continue; 3615 3616 ret = kstrtol(sub_str, 0, ¶ms[parameter_size]); 3617 if (ret) 3618 return -EINVAL; 3619 parameter_size++; 3620 3621 while (isspace(*tmp_str)) 3622 tmp_str++; 3623 } 3624 3625 *num_of_params = parameter_size; 3626 3627 return 0; 3628 } 3629 3630 static int 3631 amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev, 3632 enum PP_OD_DPM_TABLE_COMMAND cmd_type, 3633 const char *in_buf, 3634 size_t count) 3635 { 3636 uint32_t parameter_size = 0; 3637 long parameter[64]; 3638 int ret; 3639 3640 if (amdgpu_in_reset(adev)) 3641 return -EPERM; 3642 if (adev->in_suspend && !adev->in_runpm) 3643 return -EPERM; 3644 3645 ret = parse_input_od_command_lines(in_buf, 3646 count, 3647 &cmd_type, 3648 parameter, 3649 ¶meter_size); 3650 if (ret) 3651 return ret; 3652 3653 ret = pm_runtime_get_sync(adev->dev); 3654 if (ret < 0) 3655 goto err_out0; 3656 3657 ret = amdgpu_dpm_odn_edit_dpm_table(adev, 3658 cmd_type, 3659 parameter, 3660 parameter_size); 3661 if (ret) 3662 goto err_out1; 3663 3664 if (cmd_type == PP_OD_COMMIT_DPM_TABLE) { 3665 ret = amdgpu_dpm_dispatch_task(adev, 3666 AMD_PP_TASK_READJUST_POWER_STATE, 3667 NULL); 3668 if (ret) 3669 goto err_out1; 3670 } 3671 3672 pm_runtime_mark_last_busy(adev->dev); 3673 pm_runtime_put_autosuspend(adev->dev); 3674 3675 return count; 3676 3677 err_out1: 3678 pm_runtime_mark_last_busy(adev->dev); 3679 err_out0: 3680 pm_runtime_put_autosuspend(adev->dev); 3681 3682 return ret; 3683 } 3684 3685 /** 3686 * DOC: fan_curve 3687 * 3688 * The amdgpu driver provides a sysfs API for checking and adjusting the fan 3689 * control curve line. 3690 * 3691 * Reading back the file shows you the current settings(temperature in Celsius 3692 * degree and fan speed in pwm) applied to every anchor point of the curve line 3693 * and their permitted ranges if changable. 3694 * 3695 * Writing a desired string(with the format like "anchor_point_index temperature 3696 * fan_speed_in_pwm") to the file, change the settings for the specific anchor 3697 * point accordingly. 3698 * 3699 * When you have finished the editing, write "c" (commit) to the file to commit 3700 * your changes. 3701 * 3702 * If you want to reset to the default value, write "r" (reset) to the file to 3703 * reset them 3704 * 3705 * There are two fan control modes supported: auto and manual. With auto mode, 3706 * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature). 3707 * While with manual mode, users can set their own fan curve line as what 3708 * described here. Normally the ASIC is booted up with auto mode. Any 3709 * settings via this interface will switch the fan control to manual mode 3710 * implicitly. 3711 */ 3712 static ssize_t fan_curve_show(struct kobject *kobj, 3713 struct kobj_attribute *attr, 3714 char *buf) 3715 { 3716 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3717 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3718 3719 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf); 3720 } 3721 3722 static ssize_t fan_curve_store(struct kobject *kobj, 3723 struct kobj_attribute *attr, 3724 const char *buf, 3725 size_t count) 3726 { 3727 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3728 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3729 3730 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3731 PP_OD_EDIT_FAN_CURVE, 3732 buf, 3733 count); 3734 } 3735 3736 static umode_t fan_curve_visible(struct amdgpu_device *adev) 3737 { 3738 umode_t umode = 0000; 3739 3740 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE) 3741 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3742 3743 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET) 3744 umode |= S_IWUSR; 3745 3746 return umode; 3747 } 3748 3749 /** 3750 * DOC: acoustic_limit_rpm_threshold 3751 * 3752 * The amdgpu driver provides a sysfs API for checking and adjusting the 3753 * acoustic limit in RPM for fan control. 3754 * 3755 * Reading back the file shows you the current setting and the permitted 3756 * ranges if changable. 3757 * 3758 * Writing an integer to the file, change the setting accordingly. 3759 * 3760 * When you have finished the editing, write "c" (commit) to the file to commit 3761 * your changes. 3762 * 3763 * If you want to reset to the default value, write "r" (reset) to the file to 3764 * reset them 3765 * 3766 * This setting works under auto fan control mode only. It adjusts the PMFW's 3767 * behavior about the maximum speed in RPM the fan can spin. Setting via this 3768 * interface will switch the fan control to auto mode implicitly. 3769 */ 3770 static ssize_t acoustic_limit_threshold_show(struct kobject *kobj, 3771 struct kobj_attribute *attr, 3772 char *buf) 3773 { 3774 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3775 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3776 3777 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf); 3778 } 3779 3780 static ssize_t acoustic_limit_threshold_store(struct kobject *kobj, 3781 struct kobj_attribute *attr, 3782 const char *buf, 3783 size_t count) 3784 { 3785 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3786 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3787 3788 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3789 PP_OD_EDIT_ACOUSTIC_LIMIT, 3790 buf, 3791 count); 3792 } 3793 3794 static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev) 3795 { 3796 umode_t umode = 0000; 3797 3798 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE) 3799 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3800 3801 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET) 3802 umode |= S_IWUSR; 3803 3804 return umode; 3805 } 3806 3807 /** 3808 * DOC: acoustic_target_rpm_threshold 3809 * 3810 * The amdgpu driver provides a sysfs API for checking and adjusting the 3811 * acoustic target in RPM for fan control. 3812 * 3813 * Reading back the file shows you the current setting and the permitted 3814 * ranges if changable. 3815 * 3816 * Writing an integer to the file, change the setting accordingly. 3817 * 3818 * When you have finished the editing, write "c" (commit) to the file to commit 3819 * your changes. 3820 * 3821 * If you want to reset to the default value, write "r" (reset) to the file to 3822 * reset them 3823 * 3824 * This setting works under auto fan control mode only. It can co-exist with 3825 * other settings which can work also under auto mode. It adjusts the PMFW's 3826 * behavior about the maximum speed in RPM the fan can spin when ASIC 3827 * temperature is not greater than target temperature. Setting via this 3828 * interface will switch the fan control to auto mode implicitly. 3829 */ 3830 static ssize_t acoustic_target_threshold_show(struct kobject *kobj, 3831 struct kobj_attribute *attr, 3832 char *buf) 3833 { 3834 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3835 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3836 3837 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf); 3838 } 3839 3840 static ssize_t acoustic_target_threshold_store(struct kobject *kobj, 3841 struct kobj_attribute *attr, 3842 const char *buf, 3843 size_t count) 3844 { 3845 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3846 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3847 3848 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3849 PP_OD_EDIT_ACOUSTIC_TARGET, 3850 buf, 3851 count); 3852 } 3853 3854 static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev) 3855 { 3856 umode_t umode = 0000; 3857 3858 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE) 3859 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3860 3861 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET) 3862 umode |= S_IWUSR; 3863 3864 return umode; 3865 } 3866 3867 /** 3868 * DOC: fan_target_temperature 3869 * 3870 * The amdgpu driver provides a sysfs API for checking and adjusting the 3871 * target tempeature in Celsius degree for fan control. 3872 * 3873 * Reading back the file shows you the current setting and the permitted 3874 * ranges if changable. 3875 * 3876 * Writing an integer to the file, change the setting accordingly. 3877 * 3878 * When you have finished the editing, write "c" (commit) to the file to commit 3879 * your changes. 3880 * 3881 * If you want to reset to the default value, write "r" (reset) to the file to 3882 * reset them 3883 * 3884 * This setting works under auto fan control mode only. It can co-exist with 3885 * other settings which can work also under auto mode. Paring with the 3886 * acoustic_target_rpm_threshold setting, they define the maximum speed in 3887 * RPM the fan can spin when ASIC temperature is not greater than target 3888 * temperature. Setting via this interface will switch the fan control to 3889 * auto mode implicitly. 3890 */ 3891 static ssize_t fan_target_temperature_show(struct kobject *kobj, 3892 struct kobj_attribute *attr, 3893 char *buf) 3894 { 3895 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3896 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3897 3898 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf); 3899 } 3900 3901 static ssize_t fan_target_temperature_store(struct kobject *kobj, 3902 struct kobj_attribute *attr, 3903 const char *buf, 3904 size_t count) 3905 { 3906 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3907 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3908 3909 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3910 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 3911 buf, 3912 count); 3913 } 3914 3915 static umode_t fan_target_temperature_visible(struct amdgpu_device *adev) 3916 { 3917 umode_t umode = 0000; 3918 3919 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE) 3920 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3921 3922 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET) 3923 umode |= S_IWUSR; 3924 3925 return umode; 3926 } 3927 3928 /** 3929 * DOC: fan_minimum_pwm 3930 * 3931 * The amdgpu driver provides a sysfs API for checking and adjusting the 3932 * minimum fan speed in PWM. 3933 * 3934 * Reading back the file shows you the current setting and the permitted 3935 * ranges if changable. 3936 * 3937 * Writing an integer to the file, change the setting accordingly. 3938 * 3939 * When you have finished the editing, write "c" (commit) to the file to commit 3940 * your changes. 3941 * 3942 * If you want to reset to the default value, write "r" (reset) to the file to 3943 * reset them 3944 * 3945 * This setting works under auto fan control mode only. It can co-exist with 3946 * other settings which can work also under auto mode. It adjusts the PMFW's 3947 * behavior about the minimum fan speed in PWM the fan should spin. Setting 3948 * via this interface will switch the fan control to auto mode implicitly. 3949 */ 3950 static ssize_t fan_minimum_pwm_show(struct kobject *kobj, 3951 struct kobj_attribute *attr, 3952 char *buf) 3953 { 3954 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3955 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3956 3957 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf); 3958 } 3959 3960 static ssize_t fan_minimum_pwm_store(struct kobject *kobj, 3961 struct kobj_attribute *attr, 3962 const char *buf, 3963 size_t count) 3964 { 3965 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3966 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3967 3968 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3969 PP_OD_EDIT_FAN_MINIMUM_PWM, 3970 buf, 3971 count); 3972 } 3973 3974 static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev) 3975 { 3976 umode_t umode = 0000; 3977 3978 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE) 3979 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3980 3981 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET) 3982 umode |= S_IWUSR; 3983 3984 return umode; 3985 } 3986 3987 static struct od_feature_set amdgpu_od_set = { 3988 .containers = { 3989 [0] = { 3990 .name = "fan_ctrl", 3991 .sub_feature = { 3992 [0] = { 3993 .name = "fan_curve", 3994 .ops = { 3995 .is_visible = fan_curve_visible, 3996 .show = fan_curve_show, 3997 .store = fan_curve_store, 3998 }, 3999 }, 4000 [1] = { 4001 .name = "acoustic_limit_rpm_threshold", 4002 .ops = { 4003 .is_visible = acoustic_limit_threshold_visible, 4004 .show = acoustic_limit_threshold_show, 4005 .store = acoustic_limit_threshold_store, 4006 }, 4007 }, 4008 [2] = { 4009 .name = "acoustic_target_rpm_threshold", 4010 .ops = { 4011 .is_visible = acoustic_target_threshold_visible, 4012 .show = acoustic_target_threshold_show, 4013 .store = acoustic_target_threshold_store, 4014 }, 4015 }, 4016 [3] = { 4017 .name = "fan_target_temperature", 4018 .ops = { 4019 .is_visible = fan_target_temperature_visible, 4020 .show = fan_target_temperature_show, 4021 .store = fan_target_temperature_store, 4022 }, 4023 }, 4024 [4] = { 4025 .name = "fan_minimum_pwm", 4026 .ops = { 4027 .is_visible = fan_minimum_pwm_visible, 4028 .show = fan_minimum_pwm_show, 4029 .store = fan_minimum_pwm_store, 4030 }, 4031 }, 4032 }, 4033 }, 4034 }, 4035 }; 4036 4037 static void od_kobj_release(struct kobject *kobj) 4038 { 4039 struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj); 4040 4041 kfree(od_kobj); 4042 } 4043 4044 static const struct kobj_type od_ktype = { 4045 .release = od_kobj_release, 4046 .sysfs_ops = &kobj_sysfs_ops, 4047 }; 4048 4049 static void amdgpu_od_set_fini(struct amdgpu_device *adev) 4050 { 4051 struct od_kobj *container, *container_next; 4052 struct od_attribute *attribute, *attribute_next; 4053 4054 if (list_empty(&adev->pm.od_kobj_list)) 4055 return; 4056 4057 list_for_each_entry_safe(container, container_next, 4058 &adev->pm.od_kobj_list, entry) { 4059 list_del(&container->entry); 4060 4061 list_for_each_entry_safe(attribute, attribute_next, 4062 &container->attribute, entry) { 4063 list_del(&attribute->entry); 4064 sysfs_remove_file(&container->kobj, 4065 &attribute->attribute.attr); 4066 kfree(attribute); 4067 } 4068 4069 kobject_put(&container->kobj); 4070 } 4071 } 4072 4073 static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev, 4074 struct od_feature_ops *feature_ops) 4075 { 4076 umode_t mode; 4077 4078 if (!feature_ops->is_visible) 4079 return false; 4080 4081 /* 4082 * If the feature has no user read and write mode set, 4083 * we can assume the feature is actually not supported.(?) 4084 * And the revelant sysfs interface should not be exposed. 4085 */ 4086 mode = feature_ops->is_visible(adev); 4087 if (mode & (S_IRUSR | S_IWUSR)) 4088 return true; 4089 4090 return false; 4091 } 4092 4093 static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev, 4094 struct od_feature_container *container) 4095 { 4096 int i; 4097 4098 /* 4099 * If there is no valid entry within the container, the container 4100 * is recognized as a self contained container. And the valid entry 4101 * here means it has a valid naming and it is visible/supported by 4102 * the ASIC. 4103 */ 4104 for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) { 4105 if (container->sub_feature[i].name && 4106 amdgpu_is_od_feature_supported(adev, 4107 &container->sub_feature[i].ops)) 4108 return false; 4109 } 4110 4111 return true; 4112 } 4113 4114 static int amdgpu_od_set_init(struct amdgpu_device *adev) 4115 { 4116 struct od_kobj *top_set, *sub_set; 4117 struct od_attribute *attribute; 4118 struct od_feature_container *container; 4119 struct od_feature_item *feature; 4120 int i, j; 4121 int ret; 4122 4123 /* Setup the top `gpu_od` directory which holds all other OD interfaces */ 4124 top_set = kzalloc(sizeof(*top_set), GFP_KERNEL); 4125 if (!top_set) 4126 return -ENOMEM; 4127 list_add(&top_set->entry, &adev->pm.od_kobj_list); 4128 4129 ret = kobject_init_and_add(&top_set->kobj, 4130 &od_ktype, 4131 &adev->dev->kobj, 4132 "%s", 4133 "gpu_od"); 4134 if (ret) 4135 goto err_out; 4136 INIT_LIST_HEAD(&top_set->attribute); 4137 top_set->priv = adev; 4138 4139 for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) { 4140 container = &amdgpu_od_set.containers[i]; 4141 4142 if (!container->name) 4143 continue; 4144 4145 /* 4146 * If there is valid entries within the container, the container 4147 * will be presented as a sub directory and all its holding entries 4148 * will be presented as plain files under it. 4149 * While if there is no valid entry within the container, the container 4150 * itself will be presented as a plain file under top `gpu_od` directory. 4151 */ 4152 if (amdgpu_od_is_self_contained(adev, container)) { 4153 if (!amdgpu_is_od_feature_supported(adev, 4154 &container->ops)) 4155 continue; 4156 4157 /* 4158 * The container is presented as a plain file under top `gpu_od` 4159 * directory. 4160 */ 4161 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL); 4162 if (!attribute) { 4163 ret = -ENOMEM; 4164 goto err_out; 4165 } 4166 list_add(&attribute->entry, &top_set->attribute); 4167 4168 attribute->attribute.attr.mode = 4169 container->ops.is_visible(adev); 4170 attribute->attribute.attr.name = container->name; 4171 attribute->attribute.show = 4172 container->ops.show; 4173 attribute->attribute.store = 4174 container->ops.store; 4175 ret = sysfs_create_file(&top_set->kobj, 4176 &attribute->attribute.attr); 4177 if (ret) 4178 goto err_out; 4179 } else { 4180 /* The container is presented as a sub directory. */ 4181 sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL); 4182 if (!sub_set) { 4183 ret = -ENOMEM; 4184 goto err_out; 4185 } 4186 list_add(&sub_set->entry, &adev->pm.od_kobj_list); 4187 4188 ret = kobject_init_and_add(&sub_set->kobj, 4189 &od_ktype, 4190 &top_set->kobj, 4191 "%s", 4192 container->name); 4193 if (ret) 4194 goto err_out; 4195 INIT_LIST_HEAD(&sub_set->attribute); 4196 sub_set->priv = adev; 4197 4198 for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) { 4199 feature = &container->sub_feature[j]; 4200 if (!feature->name) 4201 continue; 4202 4203 if (!amdgpu_is_od_feature_supported(adev, 4204 &feature->ops)) 4205 continue; 4206 4207 /* 4208 * With the container presented as a sub directory, the entry within 4209 * it is presented as a plain file under the sub directory. 4210 */ 4211 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL); 4212 if (!attribute) { 4213 ret = -ENOMEM; 4214 goto err_out; 4215 } 4216 list_add(&attribute->entry, &sub_set->attribute); 4217 4218 attribute->attribute.attr.mode = 4219 feature->ops.is_visible(adev); 4220 attribute->attribute.attr.name = feature->name; 4221 attribute->attribute.show = 4222 feature->ops.show; 4223 attribute->attribute.store = 4224 feature->ops.store; 4225 ret = sysfs_create_file(&sub_set->kobj, 4226 &attribute->attribute.attr); 4227 if (ret) 4228 goto err_out; 4229 } 4230 } 4231 } 4232 4233 return 0; 4234 4235 err_out: 4236 amdgpu_od_set_fini(adev); 4237 4238 return ret; 4239 } 4240 4241 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 4242 { 4243 enum amdgpu_sriov_vf_mode mode; 4244 uint32_t mask = 0; 4245 int ret; 4246 4247 if (adev->pm.sysfs_initialized) 4248 return 0; 4249 4250 INIT_LIST_HEAD(&adev->pm.pm_attr_list); 4251 4252 if (adev->pm.dpm_enabled == 0) 4253 return 0; 4254 4255 mode = amdgpu_virt_get_sriov_vf_mode(adev); 4256 4257 /* under multi-vf mode, the hwmon attributes are all not supported */ 4258 if (mode != SRIOV_VF_MODE_MULTI_VF) { 4259 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 4260 DRIVER_NAME, adev, 4261 hwmon_groups); 4262 if (IS_ERR(adev->pm.int_hwmon_dev)) { 4263 ret = PTR_ERR(adev->pm.int_hwmon_dev); 4264 dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret); 4265 return ret; 4266 } 4267 } 4268 4269 switch (mode) { 4270 case SRIOV_VF_MODE_ONE_VF: 4271 mask = ATTR_FLAG_ONEVF; 4272 break; 4273 case SRIOV_VF_MODE_MULTI_VF: 4274 mask = 0; 4275 break; 4276 case SRIOV_VF_MODE_BARE_METAL: 4277 default: 4278 mask = ATTR_FLAG_MASK_ALL; 4279 break; 4280 } 4281 4282 ret = amdgpu_device_attr_create_groups(adev, 4283 amdgpu_device_attrs, 4284 ARRAY_SIZE(amdgpu_device_attrs), 4285 mask, 4286 &adev->pm.pm_attr_list); 4287 if (ret) 4288 goto err_out0; 4289 4290 if (amdgpu_dpm_is_overdrive_supported(adev)) { 4291 ret = amdgpu_od_set_init(adev); 4292 if (ret) 4293 goto err_out1; 4294 } 4295 4296 adev->pm.sysfs_initialized = true; 4297 4298 return 0; 4299 4300 err_out1: 4301 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 4302 err_out0: 4303 if (adev->pm.int_hwmon_dev) 4304 hwmon_device_unregister(adev->pm.int_hwmon_dev); 4305 4306 return ret; 4307 } 4308 4309 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 4310 { 4311 amdgpu_od_set_fini(adev); 4312 4313 if (adev->pm.int_hwmon_dev) 4314 hwmon_device_unregister(adev->pm.int_hwmon_dev); 4315 4316 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 4317 } 4318 4319 /* 4320 * Debugfs info 4321 */ 4322 #if defined(CONFIG_DEBUG_FS) 4323 4324 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 4325 struct amdgpu_device *adev) 4326 { 4327 uint16_t *p_val; 4328 uint32_t size; 4329 int i; 4330 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); 4331 4332 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { 4333 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), 4334 GFP_KERNEL); 4335 4336 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 4337 (void *)p_val, &size)) { 4338 for (i = 0; i < num_cpu_cores; i++) 4339 seq_printf(m, "\t%u MHz (CPU%d)\n", 4340 *(p_val + i), i); 4341 } 4342 4343 kfree(p_val); 4344 } 4345 } 4346 4347 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 4348 { 4349 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0); 4350 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 4351 uint32_t value; 4352 uint64_t value64 = 0; 4353 uint32_t query = 0; 4354 int size; 4355 4356 /* GPU Clocks */ 4357 size = sizeof(value); 4358 seq_printf(m, "GFX Clocks and Power:\n"); 4359 4360 amdgpu_debugfs_prints_cpu_info(m, adev); 4361 4362 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 4363 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 4364 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 4365 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 4366 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 4367 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 4368 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 4369 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 4370 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 4371 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 4372 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 4373 seq_printf(m, "\t%u mV (VDDNB)\n", value); 4374 size = sizeof(uint32_t); 4375 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) { 4376 if (adev->flags & AMD_IS_APU) 4377 seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n", query >> 8, query & 0xff); 4378 else 4379 seq_printf(m, "\t%u.%02u W (average SoC)\n", query >> 8, query & 0xff); 4380 } 4381 size = sizeof(uint32_t); 4382 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) { 4383 if (adev->flags & AMD_IS_APU) 4384 seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n", query >> 8, query & 0xff); 4385 else 4386 seq_printf(m, "\t%u.%02u W (current SoC)\n", query >> 8, query & 0xff); 4387 } 4388 size = sizeof(value); 4389 seq_printf(m, "\n"); 4390 4391 /* GPU Temp */ 4392 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 4393 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 4394 4395 /* GPU Load */ 4396 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 4397 seq_printf(m, "GPU Load: %u %%\n", value); 4398 /* MEM Load */ 4399 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 4400 seq_printf(m, "MEM Load: %u %%\n", value); 4401 4402 seq_printf(m, "\n"); 4403 4404 /* SMC feature mask */ 4405 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 4406 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 4407 4408 /* ASICs greater than CHIP_VEGA20 supports these sensors */ 4409 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { 4410 /* VCN clocks */ 4411 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 4412 if (!value) { 4413 seq_printf(m, "VCN: Powered down\n"); 4414 } else { 4415 seq_printf(m, "VCN: Powered up\n"); 4416 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 4417 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 4418 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 4419 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 4420 } 4421 } 4422 seq_printf(m, "\n"); 4423 } else { 4424 /* UVD clocks */ 4425 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 4426 if (!value) { 4427 seq_printf(m, "UVD: Powered down\n"); 4428 } else { 4429 seq_printf(m, "UVD: Powered up\n"); 4430 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 4431 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 4432 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 4433 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 4434 } 4435 } 4436 seq_printf(m, "\n"); 4437 4438 /* VCE clocks */ 4439 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 4440 if (!value) { 4441 seq_printf(m, "VCE: Powered down\n"); 4442 } else { 4443 seq_printf(m, "VCE: Powered up\n"); 4444 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 4445 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 4446 } 4447 } 4448 } 4449 4450 return 0; 4451 } 4452 4453 static const struct cg_flag_name clocks[] = { 4454 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 4455 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 4456 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 4457 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 4458 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 4459 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 4460 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 4461 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 4462 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 4463 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 4464 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 4465 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 4466 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 4467 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 4468 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 4469 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 4470 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 4471 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 4472 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 4473 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 4474 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 4475 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 4476 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 4477 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 4478 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 4479 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 4480 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 4481 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 4482 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 4483 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 4484 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, 4485 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, 4486 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 4487 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 4488 {0, NULL}, 4489 }; 4490 4491 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 4492 { 4493 int i; 4494 4495 for (i = 0; clocks[i].flag; i++) 4496 seq_printf(m, "\t%s: %s\n", clocks[i].name, 4497 (flags & clocks[i].flag) ? "On" : "Off"); 4498 } 4499 4500 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 4501 { 4502 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 4503 struct drm_device *dev = adev_to_drm(adev); 4504 u64 flags = 0; 4505 int r; 4506 4507 if (amdgpu_in_reset(adev)) 4508 return -EPERM; 4509 if (adev->in_suspend && !adev->in_runpm) 4510 return -EPERM; 4511 4512 r = pm_runtime_get_sync(dev->dev); 4513 if (r < 0) { 4514 pm_runtime_put_autosuspend(dev->dev); 4515 return r; 4516 } 4517 4518 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { 4519 r = amdgpu_debugfs_pm_info_pp(m, adev); 4520 if (r) 4521 goto out; 4522 } 4523 4524 amdgpu_device_ip_get_clockgating_state(adev, &flags); 4525 4526 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 4527 amdgpu_parse_cg_state(m, flags); 4528 seq_printf(m, "\n"); 4529 4530 out: 4531 pm_runtime_mark_last_busy(dev->dev); 4532 pm_runtime_put_autosuspend(dev->dev); 4533 4534 return r; 4535 } 4536 4537 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 4538 4539 /* 4540 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 4541 * 4542 * Reads debug memory region allocated to PMFW 4543 */ 4544 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 4545 size_t size, loff_t *pos) 4546 { 4547 struct amdgpu_device *adev = file_inode(f)->i_private; 4548 size_t smu_prv_buf_size; 4549 void *smu_prv_buf; 4550 int ret = 0; 4551 4552 if (amdgpu_in_reset(adev)) 4553 return -EPERM; 4554 if (adev->in_suspend && !adev->in_runpm) 4555 return -EPERM; 4556 4557 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); 4558 if (ret) 4559 return ret; 4560 4561 if (!smu_prv_buf || !smu_prv_buf_size) 4562 return -EINVAL; 4563 4564 return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 4565 smu_prv_buf_size); 4566 } 4567 4568 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 4569 .owner = THIS_MODULE, 4570 .open = simple_open, 4571 .read = amdgpu_pm_prv_buffer_read, 4572 .llseek = default_llseek, 4573 }; 4574 4575 #endif 4576 4577 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 4578 { 4579 #if defined(CONFIG_DEBUG_FS) 4580 struct drm_minor *minor = adev_to_drm(adev)->primary; 4581 struct dentry *root = minor->debugfs_root; 4582 4583 if (!adev->pm.dpm_enabled) 4584 return; 4585 4586 debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 4587 &amdgpu_debugfs_pm_info_fops); 4588 4589 if (adev->pm.smu_prv_buffer_size > 0) 4590 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 4591 adev, 4592 &amdgpu_debugfs_pm_prv_buffer_fops, 4593 adev->pm.smu_prv_buffer_size); 4594 4595 amdgpu_dpm_stb_debug_fs_init(adev); 4596 #endif 4597 } 4598