1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/pci.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 #include <linux/pm_runtime.h> 36 #include <asm/processor.h> 37 38 #define MAX_NUM_OF_FEATURES_PER_SUBSET 8 39 #define MAX_NUM_OF_SUBSETS 8 40 41 #define DEVICE_ATTR_IS(_name) (attr_id == device_attr_id__##_name) 42 43 struct od_attribute { 44 struct kobj_attribute attribute; 45 struct list_head entry; 46 }; 47 48 struct od_kobj { 49 struct kobject kobj; 50 struct list_head entry; 51 struct list_head attribute; 52 void *priv; 53 }; 54 55 struct od_feature_ops { 56 umode_t (*is_visible)(struct amdgpu_device *adev); 57 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr, 58 char *buf); 59 ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr, 60 const char *buf, size_t count); 61 }; 62 63 struct od_feature_item { 64 const char *name; 65 struct od_feature_ops ops; 66 }; 67 68 struct od_feature_container { 69 char *name; 70 struct od_feature_ops ops; 71 struct od_feature_item sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET]; 72 }; 73 74 struct od_feature_set { 75 struct od_feature_container containers[MAX_NUM_OF_SUBSETS]; 76 }; 77 78 static const struct hwmon_temp_label { 79 enum PP_HWMON_TEMP channel; 80 const char *label; 81 } temp_label[] = { 82 {PP_TEMP_EDGE, "edge"}, 83 {PP_TEMP_JUNCTION, "junction"}, 84 {PP_TEMP_MEM, "mem"}, 85 }; 86 87 const char * const amdgpu_pp_profile_name[] = { 88 "BOOTUP_DEFAULT", 89 "3D_FULL_SCREEN", 90 "POWER_SAVING", 91 "VIDEO", 92 "VR", 93 "COMPUTE", 94 "CUSTOM", 95 "WINDOW_3D", 96 "CAPPED", 97 "UNCAPPED", 98 }; 99 100 /** 101 * DOC: power_dpm_state 102 * 103 * The power_dpm_state file is a legacy interface and is only provided for 104 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 105 * certain power related parameters. The file power_dpm_state is used for this. 106 * It accepts the following arguments: 107 * 108 * - battery 109 * 110 * - balanced 111 * 112 * - performance 113 * 114 * battery 115 * 116 * On older GPUs, the vbios provided a special power state for battery 117 * operation. Selecting battery switched to this state. This is no 118 * longer provided on newer GPUs so the option does nothing in that case. 119 * 120 * balanced 121 * 122 * On older GPUs, the vbios provided a special power state for balanced 123 * operation. Selecting balanced switched to this state. This is no 124 * longer provided on newer GPUs so the option does nothing in that case. 125 * 126 * performance 127 * 128 * On older GPUs, the vbios provided a special power state for performance 129 * operation. Selecting performance switched to this state. This is no 130 * longer provided on newer GPUs so the option does nothing in that case. 131 * 132 */ 133 134 static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 135 struct device_attribute *attr, 136 char *buf) 137 { 138 struct drm_device *ddev = dev_get_drvdata(dev); 139 struct amdgpu_device *adev = drm_to_adev(ddev); 140 enum amd_pm_state_type pm; 141 int ret; 142 143 if (amdgpu_in_reset(adev)) 144 return -EPERM; 145 if (adev->in_suspend && !adev->in_runpm) 146 return -EPERM; 147 148 ret = pm_runtime_get_if_active(ddev->dev); 149 if (ret <= 0) 150 return ret ?: -EPERM; 151 152 amdgpu_dpm_get_current_power_state(adev, &pm); 153 154 pm_runtime_put_autosuspend(ddev->dev); 155 156 return sysfs_emit(buf, "%s\n", 157 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 158 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 159 } 160 161 static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 162 struct device_attribute *attr, 163 const char *buf, 164 size_t count) 165 { 166 struct drm_device *ddev = dev_get_drvdata(dev); 167 struct amdgpu_device *adev = drm_to_adev(ddev); 168 enum amd_pm_state_type state; 169 int ret; 170 171 if (amdgpu_in_reset(adev)) 172 return -EPERM; 173 if (adev->in_suspend && !adev->in_runpm) 174 return -EPERM; 175 176 if (strncmp("battery", buf, strlen("battery")) == 0) 177 state = POWER_STATE_TYPE_BATTERY; 178 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 179 state = POWER_STATE_TYPE_BALANCED; 180 else if (strncmp("performance", buf, strlen("performance")) == 0) 181 state = POWER_STATE_TYPE_PERFORMANCE; 182 else 183 return -EINVAL; 184 185 ret = pm_runtime_resume_and_get(ddev->dev); 186 if (ret < 0) 187 return ret; 188 189 amdgpu_dpm_set_power_state(adev, state); 190 191 pm_runtime_mark_last_busy(ddev->dev); 192 pm_runtime_put_autosuspend(ddev->dev); 193 194 return count; 195 } 196 197 198 /** 199 * DOC: power_dpm_force_performance_level 200 * 201 * The amdgpu driver provides a sysfs API for adjusting certain power 202 * related parameters. The file power_dpm_force_performance_level is 203 * used for this. It accepts the following arguments: 204 * 205 * - auto 206 * 207 * - low 208 * 209 * - high 210 * 211 * - manual 212 * 213 * - profile_standard 214 * 215 * - profile_min_sclk 216 * 217 * - profile_min_mclk 218 * 219 * - profile_peak 220 * 221 * auto 222 * 223 * When auto is selected, the driver will attempt to dynamically select 224 * the optimal power profile for current conditions in the driver. 225 * 226 * low 227 * 228 * When low is selected, the clocks are forced to the lowest power state. 229 * 230 * high 231 * 232 * When high is selected, the clocks are forced to the highest power state. 233 * 234 * manual 235 * 236 * When manual is selected, the user can manually adjust which power states 237 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 238 * and pp_dpm_pcie files and adjust the power state transition heuristics 239 * via the pp_power_profile_mode sysfs file. 240 * 241 * profile_standard 242 * profile_min_sclk 243 * profile_min_mclk 244 * profile_peak 245 * 246 * When the profiling modes are selected, clock and power gating are 247 * disabled and the clocks are set for different profiling cases. This 248 * mode is recommended for profiling specific work loads where you do 249 * not want clock or power gating for clock fluctuation to interfere 250 * with your results. profile_standard sets the clocks to a fixed clock 251 * level which varies from asic to asic. profile_min_sclk forces the sclk 252 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 253 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 254 * 255 */ 256 257 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 258 struct device_attribute *attr, 259 char *buf) 260 { 261 struct drm_device *ddev = dev_get_drvdata(dev); 262 struct amdgpu_device *adev = drm_to_adev(ddev); 263 enum amd_dpm_forced_level level = 0xff; 264 int ret; 265 266 if (amdgpu_in_reset(adev)) 267 return -EPERM; 268 if (adev->in_suspend && !adev->in_runpm) 269 return -EPERM; 270 271 ret = pm_runtime_get_if_active(ddev->dev); 272 if (ret <= 0) 273 return ret ?: -EPERM; 274 275 level = amdgpu_dpm_get_performance_level(adev); 276 277 pm_runtime_put_autosuspend(ddev->dev); 278 279 return sysfs_emit(buf, "%s\n", 280 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 281 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 282 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 283 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 284 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 285 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 286 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 287 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 288 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 289 "unknown"); 290 } 291 292 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 293 struct device_attribute *attr, 294 const char *buf, 295 size_t count) 296 { 297 struct drm_device *ddev = dev_get_drvdata(dev); 298 struct amdgpu_device *adev = drm_to_adev(ddev); 299 enum amd_dpm_forced_level level; 300 int ret = 0; 301 302 if (amdgpu_in_reset(adev)) 303 return -EPERM; 304 if (adev->in_suspend && !adev->in_runpm) 305 return -EPERM; 306 307 if (strncmp("low", buf, strlen("low")) == 0) { 308 level = AMD_DPM_FORCED_LEVEL_LOW; 309 } else if (strncmp("high", buf, strlen("high")) == 0) { 310 level = AMD_DPM_FORCED_LEVEL_HIGH; 311 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 312 level = AMD_DPM_FORCED_LEVEL_AUTO; 313 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 314 level = AMD_DPM_FORCED_LEVEL_MANUAL; 315 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 316 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 317 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 318 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 319 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 320 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 321 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 322 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 323 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 324 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 325 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 326 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 327 } else { 328 return -EINVAL; 329 } 330 331 ret = pm_runtime_resume_and_get(ddev->dev); 332 if (ret < 0) 333 return ret; 334 335 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 336 if (amdgpu_dpm_force_performance_level(adev, level)) { 337 pm_runtime_mark_last_busy(ddev->dev); 338 pm_runtime_put_autosuspend(ddev->dev); 339 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 340 return -EINVAL; 341 } 342 /* override whatever a user ctx may have set */ 343 adev->pm.stable_pstate_ctx = NULL; 344 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 345 346 pm_runtime_mark_last_busy(ddev->dev); 347 pm_runtime_put_autosuspend(ddev->dev); 348 349 return count; 350 } 351 352 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 353 struct device_attribute *attr, 354 char *buf) 355 { 356 struct drm_device *ddev = dev_get_drvdata(dev); 357 struct amdgpu_device *adev = drm_to_adev(ddev); 358 struct pp_states_info data; 359 uint32_t i; 360 int buf_len, ret; 361 362 if (amdgpu_in_reset(adev)) 363 return -EPERM; 364 if (adev->in_suspend && !adev->in_runpm) 365 return -EPERM; 366 367 ret = pm_runtime_get_if_active(ddev->dev); 368 if (ret <= 0) 369 return ret ?: -EPERM; 370 371 if (amdgpu_dpm_get_pp_num_states(adev, &data)) 372 memset(&data, 0, sizeof(data)); 373 374 pm_runtime_put_autosuspend(ddev->dev); 375 376 buf_len = sysfs_emit(buf, "states: %d\n", data.nums); 377 for (i = 0; i < data.nums; i++) 378 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, 379 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 380 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 381 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 382 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 383 384 return buf_len; 385 } 386 387 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 388 struct device_attribute *attr, 389 char *buf) 390 { 391 struct drm_device *ddev = dev_get_drvdata(dev); 392 struct amdgpu_device *adev = drm_to_adev(ddev); 393 struct pp_states_info data = {0}; 394 enum amd_pm_state_type pm = 0; 395 int i = 0, ret = 0; 396 397 if (amdgpu_in_reset(adev)) 398 return -EPERM; 399 if (adev->in_suspend && !adev->in_runpm) 400 return -EPERM; 401 402 ret = pm_runtime_get_if_active(ddev->dev); 403 if (ret <= 0) 404 return ret ?: -EPERM; 405 406 amdgpu_dpm_get_current_power_state(adev, &pm); 407 408 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 409 410 pm_runtime_put_autosuspend(ddev->dev); 411 412 if (ret) 413 return ret; 414 415 for (i = 0; i < data.nums; i++) { 416 if (pm == data.states[i]) 417 break; 418 } 419 420 if (i == data.nums) 421 i = -EINVAL; 422 423 return sysfs_emit(buf, "%d\n", i); 424 } 425 426 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 427 struct device_attribute *attr, 428 char *buf) 429 { 430 struct drm_device *ddev = dev_get_drvdata(dev); 431 struct amdgpu_device *adev = drm_to_adev(ddev); 432 433 if (amdgpu_in_reset(adev)) 434 return -EPERM; 435 if (adev->in_suspend && !adev->in_runpm) 436 return -EPERM; 437 438 if (adev->pm.pp_force_state_enabled) 439 return amdgpu_get_pp_cur_state(dev, attr, buf); 440 else 441 return sysfs_emit(buf, "\n"); 442 } 443 444 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 445 struct device_attribute *attr, 446 const char *buf, 447 size_t count) 448 { 449 struct drm_device *ddev = dev_get_drvdata(dev); 450 struct amdgpu_device *adev = drm_to_adev(ddev); 451 enum amd_pm_state_type state = 0; 452 struct pp_states_info data; 453 unsigned long idx; 454 int ret; 455 456 if (amdgpu_in_reset(adev)) 457 return -EPERM; 458 if (adev->in_suspend && !adev->in_runpm) 459 return -EPERM; 460 461 adev->pm.pp_force_state_enabled = false; 462 463 if (strlen(buf) == 1) 464 return count; 465 466 ret = kstrtoul(buf, 0, &idx); 467 if (ret || idx >= ARRAY_SIZE(data.states)) 468 return -EINVAL; 469 470 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 471 472 ret = pm_runtime_resume_and_get(ddev->dev); 473 if (ret < 0) 474 return ret; 475 476 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 477 if (ret) 478 goto err_out; 479 480 state = data.states[idx]; 481 482 /* only set user selected power states */ 483 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 484 state != POWER_STATE_TYPE_DEFAULT) { 485 ret = amdgpu_dpm_dispatch_task(adev, 486 AMD_PP_TASK_ENABLE_USER_STATE, &state); 487 if (ret) 488 goto err_out; 489 490 adev->pm.pp_force_state_enabled = true; 491 } 492 493 pm_runtime_mark_last_busy(ddev->dev); 494 pm_runtime_put_autosuspend(ddev->dev); 495 496 return count; 497 498 err_out: 499 pm_runtime_mark_last_busy(ddev->dev); 500 pm_runtime_put_autosuspend(ddev->dev); 501 return ret; 502 } 503 504 /** 505 * DOC: pp_table 506 * 507 * The amdgpu driver provides a sysfs API for uploading new powerplay 508 * tables. The file pp_table is used for this. Reading the file 509 * will dump the current power play table. Writing to the file 510 * will attempt to upload a new powerplay table and re-initialize 511 * powerplay using that new table. 512 * 513 */ 514 515 static ssize_t amdgpu_get_pp_table(struct device *dev, 516 struct device_attribute *attr, 517 char *buf) 518 { 519 struct drm_device *ddev = dev_get_drvdata(dev); 520 struct amdgpu_device *adev = drm_to_adev(ddev); 521 char *table = NULL; 522 int size, ret; 523 524 if (amdgpu_in_reset(adev)) 525 return -EPERM; 526 if (adev->in_suspend && !adev->in_runpm) 527 return -EPERM; 528 529 ret = pm_runtime_get_if_active(ddev->dev); 530 if (ret <= 0) 531 return ret ?: -EPERM; 532 533 size = amdgpu_dpm_get_pp_table(adev, &table); 534 535 pm_runtime_put_autosuspend(ddev->dev); 536 537 if (size <= 0) 538 return size; 539 540 if (size >= PAGE_SIZE) 541 size = PAGE_SIZE - 1; 542 543 memcpy(buf, table, size); 544 545 return size; 546 } 547 548 static ssize_t amdgpu_set_pp_table(struct device *dev, 549 struct device_attribute *attr, 550 const char *buf, 551 size_t count) 552 { 553 struct drm_device *ddev = dev_get_drvdata(dev); 554 struct amdgpu_device *adev = drm_to_adev(ddev); 555 int ret = 0; 556 557 if (amdgpu_in_reset(adev)) 558 return -EPERM; 559 if (adev->in_suspend && !adev->in_runpm) 560 return -EPERM; 561 562 ret = pm_runtime_resume_and_get(ddev->dev); 563 if (ret < 0) 564 return ret; 565 566 ret = amdgpu_dpm_set_pp_table(adev, buf, count); 567 568 pm_runtime_mark_last_busy(ddev->dev); 569 pm_runtime_put_autosuspend(ddev->dev); 570 571 if (ret) 572 return ret; 573 574 return count; 575 } 576 577 /** 578 * DOC: pp_od_clk_voltage 579 * 580 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 581 * in each power level within a power state. The pp_od_clk_voltage is used for 582 * this. 583 * 584 * Note that the actual memory controller clock rate are exposed, not 585 * the effective memory clock of the DRAMs. To translate it, use the 586 * following formula: 587 * 588 * Clock conversion (Mhz): 589 * 590 * HBM: effective_memory_clock = memory_controller_clock * 1 591 * 592 * G5: effective_memory_clock = memory_controller_clock * 1 593 * 594 * G6: effective_memory_clock = memory_controller_clock * 2 595 * 596 * DRAM data rate (MT/s): 597 * 598 * HBM: effective_memory_clock * 2 = data_rate 599 * 600 * G5: effective_memory_clock * 4 = data_rate 601 * 602 * G6: effective_memory_clock * 8 = data_rate 603 * 604 * Bandwidth (MB/s): 605 * 606 * data_rate * vram_bit_width / 8 = memory_bandwidth 607 * 608 * Some examples: 609 * 610 * G5 on RX460: 611 * 612 * memory_controller_clock = 1750 Mhz 613 * 614 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 615 * 616 * data rate = 1750 * 4 = 7000 MT/s 617 * 618 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 619 * 620 * G6 on RX5700: 621 * 622 * memory_controller_clock = 875 Mhz 623 * 624 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 625 * 626 * data rate = 1750 * 8 = 14000 MT/s 627 * 628 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 629 * 630 * < For Vega10 and previous ASICs > 631 * 632 * Reading the file will display: 633 * 634 * - a list of engine clock levels and voltages labeled OD_SCLK 635 * 636 * - a list of memory clock levels and voltages labeled OD_MCLK 637 * 638 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 639 * 640 * To manually adjust these settings, first select manual using 641 * power_dpm_force_performance_level. Enter a new value for each 642 * level by writing a string that contains "s/m level clock voltage" to 643 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 644 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 645 * 810 mV. When you have edited all of the states as needed, write 646 * "c" (commit) to the file to commit your changes. If you want to reset to the 647 * default power levels, write "r" (reset) to the file to reset them. 648 * 649 * 650 * < For Vega20 and newer ASICs > 651 * 652 * Reading the file will display: 653 * 654 * - minimum and maximum engine clock labeled OD_SCLK 655 * 656 * - minimum(not available for Vega20 and Navi1x) and maximum memory 657 * clock labeled OD_MCLK 658 * 659 * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 660 * They can be used to calibrate the sclk voltage curve. This is 661 * available for Vega20 and NV1X. 662 * 663 * - voltage offset(in mV) applied on target voltage calculation. 664 * This is available for Sienna Cichlid, Navy Flounder, Dimgrey 665 * Cavefish and some later SMU13 ASICs. For these ASICs, the target 666 * voltage calculation can be illustrated by "voltage = voltage 667 * calculated from v/f curve + overdrive vddgfx offset" 668 * 669 * - a list of valid ranges for sclk, mclk, voltage curve points 670 * or voltage offset labeled OD_RANGE 671 * 672 * < For APUs > 673 * 674 * Reading the file will display: 675 * 676 * - minimum and maximum engine clock labeled OD_SCLK 677 * 678 * - a list of valid ranges for sclk labeled OD_RANGE 679 * 680 * < For VanGogh > 681 * 682 * Reading the file will display: 683 * 684 * - minimum and maximum engine clock labeled OD_SCLK 685 * - minimum and maximum core clocks labeled OD_CCLK 686 * 687 * - a list of valid ranges for sclk and cclk labeled OD_RANGE 688 * 689 * To manually adjust these settings: 690 * 691 * - First select manual using power_dpm_force_performance_level 692 * 693 * - For clock frequency setting, enter a new value by writing a 694 * string that contains "s/m index clock" to the file. The index 695 * should be 0 if to set minimum clock. And 1 if to set maximum 696 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 697 * "m 1 800" will update maximum mclk to be 800Mhz. For core 698 * clocks on VanGogh, the string contains "p core index clock". 699 * E.g., "p 2 0 800" would set the minimum core clock on core 700 * 2 to 800Mhz. 701 * 702 * For sclk voltage curve supported by Vega20 and NV1X, enter the new 703 * values by writing a string that contains "vc point clock voltage" 704 * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300 705 * 600" will update point1 with clock set as 300Mhz and voltage as 600mV. 706 * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and 707 * voltage 1000mV. 708 * 709 * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey 710 * Cavefish and some later SMU13 ASICs, enter the new value by writing a 711 * string that contains "vo offset". E.g., "vo -10" will update the extra 712 * voltage offset applied to the whole v/f curve line as -10mv. 713 * 714 * - When you have edited all of the states as needed, write "c" (commit) 715 * to the file to commit your changes 716 * 717 * - If you want to reset to the default power levels, write "r" (reset) 718 * to the file to reset them 719 * 720 */ 721 722 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 723 struct device_attribute *attr, 724 const char *buf, 725 size_t count) 726 { 727 struct drm_device *ddev = dev_get_drvdata(dev); 728 struct amdgpu_device *adev = drm_to_adev(ddev); 729 int ret; 730 uint32_t parameter_size = 0; 731 long parameter[64]; 732 char buf_cpy[128]; 733 char *tmp_str; 734 char *sub_str; 735 const char delimiter[3] = {' ', '\n', '\0'}; 736 uint32_t type; 737 738 if (amdgpu_in_reset(adev)) 739 return -EPERM; 740 if (adev->in_suspend && !adev->in_runpm) 741 return -EPERM; 742 743 if (count > 127 || count == 0) 744 return -EINVAL; 745 746 if (*buf == 's') 747 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 748 else if (*buf == 'p') 749 type = PP_OD_EDIT_CCLK_VDDC_TABLE; 750 else if (*buf == 'm') 751 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 752 else if (*buf == 'r') 753 type = PP_OD_RESTORE_DEFAULT_TABLE; 754 else if (*buf == 'c') 755 type = PP_OD_COMMIT_DPM_TABLE; 756 else if (!strncmp(buf, "vc", 2)) 757 type = PP_OD_EDIT_VDDC_CURVE; 758 else if (!strncmp(buf, "vo", 2)) 759 type = PP_OD_EDIT_VDDGFX_OFFSET; 760 else 761 return -EINVAL; 762 763 memcpy(buf_cpy, buf, count); 764 buf_cpy[count] = 0; 765 766 tmp_str = buf_cpy; 767 768 if ((type == PP_OD_EDIT_VDDC_CURVE) || 769 (type == PP_OD_EDIT_VDDGFX_OFFSET)) 770 tmp_str++; 771 while (isspace(*++tmp_str)); 772 773 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 774 if (strlen(sub_str) == 0) 775 continue; 776 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 777 if (ret) 778 return -EINVAL; 779 parameter_size++; 780 781 if (!tmp_str) 782 break; 783 784 while (isspace(*tmp_str)) 785 tmp_str++; 786 } 787 788 ret = pm_runtime_resume_and_get(ddev->dev); 789 if (ret < 0) 790 return ret; 791 792 if (amdgpu_dpm_set_fine_grain_clk_vol(adev, 793 type, 794 parameter, 795 parameter_size)) 796 goto err_out; 797 798 if (amdgpu_dpm_odn_edit_dpm_table(adev, type, 799 parameter, parameter_size)) 800 goto err_out; 801 802 if (type == PP_OD_COMMIT_DPM_TABLE) { 803 if (amdgpu_dpm_dispatch_task(adev, 804 AMD_PP_TASK_READJUST_POWER_STATE, 805 NULL)) 806 goto err_out; 807 } 808 809 pm_runtime_mark_last_busy(ddev->dev); 810 pm_runtime_put_autosuspend(ddev->dev); 811 812 return count; 813 814 err_out: 815 pm_runtime_mark_last_busy(ddev->dev); 816 pm_runtime_put_autosuspend(ddev->dev); 817 return -EINVAL; 818 } 819 820 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 821 struct device_attribute *attr, 822 char *buf) 823 { 824 struct drm_device *ddev = dev_get_drvdata(dev); 825 struct amdgpu_device *adev = drm_to_adev(ddev); 826 int size = 0; 827 int ret; 828 enum pp_clock_type od_clocks[6] = { 829 OD_SCLK, 830 OD_MCLK, 831 OD_VDDC_CURVE, 832 OD_RANGE, 833 OD_VDDGFX_OFFSET, 834 OD_CCLK, 835 }; 836 uint clk_index; 837 838 if (amdgpu_in_reset(adev)) 839 return -EPERM; 840 if (adev->in_suspend && !adev->in_runpm) 841 return -EPERM; 842 843 ret = pm_runtime_get_if_active(ddev->dev); 844 if (ret <= 0) 845 return ret ?: -EPERM; 846 847 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { 848 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); 849 if (ret) 850 break; 851 } 852 if (ret == -ENOENT) { 853 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 854 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); 855 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); 856 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); 857 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); 858 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); 859 } 860 861 if (size == 0) 862 size = sysfs_emit(buf, "\n"); 863 864 pm_runtime_put_autosuspend(ddev->dev); 865 866 return size; 867 } 868 869 /** 870 * DOC: pp_features 871 * 872 * The amdgpu driver provides a sysfs API for adjusting what powerplay 873 * features to be enabled. The file pp_features is used for this. And 874 * this is only available for Vega10 and later dGPUs. 875 * 876 * Reading back the file will show you the followings: 877 * - Current ppfeature masks 878 * - List of the all supported powerplay features with their naming, 879 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 880 * 881 * To manually enable or disable a specific feature, just set or clear 882 * the corresponding bit from original ppfeature masks and input the 883 * new ppfeature masks. 884 */ 885 static ssize_t amdgpu_set_pp_features(struct device *dev, 886 struct device_attribute *attr, 887 const char *buf, 888 size_t count) 889 { 890 struct drm_device *ddev = dev_get_drvdata(dev); 891 struct amdgpu_device *adev = drm_to_adev(ddev); 892 uint64_t featuremask; 893 int ret; 894 895 if (amdgpu_in_reset(adev)) 896 return -EPERM; 897 if (adev->in_suspend && !adev->in_runpm) 898 return -EPERM; 899 900 ret = kstrtou64(buf, 0, &featuremask); 901 if (ret) 902 return -EINVAL; 903 904 ret = pm_runtime_resume_and_get(ddev->dev); 905 if (ret < 0) 906 return ret; 907 908 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 909 910 pm_runtime_mark_last_busy(ddev->dev); 911 pm_runtime_put_autosuspend(ddev->dev); 912 913 if (ret) 914 return -EINVAL; 915 916 return count; 917 } 918 919 static ssize_t amdgpu_get_pp_features(struct device *dev, 920 struct device_attribute *attr, 921 char *buf) 922 { 923 struct drm_device *ddev = dev_get_drvdata(dev); 924 struct amdgpu_device *adev = drm_to_adev(ddev); 925 ssize_t size; 926 int ret; 927 928 if (amdgpu_in_reset(adev)) 929 return -EPERM; 930 if (adev->in_suspend && !adev->in_runpm) 931 return -EPERM; 932 933 ret = pm_runtime_get_if_active(ddev->dev); 934 if (ret <= 0) 935 return ret ?: -EPERM; 936 937 size = amdgpu_dpm_get_ppfeature_status(adev, buf); 938 if (size <= 0) 939 size = sysfs_emit(buf, "\n"); 940 941 pm_runtime_put_autosuspend(ddev->dev); 942 943 return size; 944 } 945 946 /** 947 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 948 * 949 * The amdgpu driver provides a sysfs API for adjusting what power levels 950 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 951 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 952 * this. 953 * 954 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 955 * Vega10 and later ASICs. 956 * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 957 * 958 * Reading back the files will show you the available power levels within 959 * the power state and the clock information for those levels. If deep sleep is 960 * applied to a clock, the level will be denoted by a special level 'S:' 961 * E.g., :: 962 * 963 * S: 19Mhz * 964 * 0: 615Mhz 965 * 1: 800Mhz 966 * 2: 888Mhz 967 * 3: 1000Mhz 968 * 969 * 970 * To manually adjust these states, first select manual using 971 * power_dpm_force_performance_level. 972 * Secondly, enter a new value for each level by inputing a string that 973 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 974 * E.g., 975 * 976 * .. code-block:: bash 977 * 978 * echo "4 5 6" > pp_dpm_sclk 979 * 980 * will enable sclk levels 4, 5, and 6. 981 * 982 * NOTE: change to the dcefclk max dpm level is not supported now 983 */ 984 985 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 986 enum pp_clock_type type, 987 char *buf) 988 { 989 struct drm_device *ddev = dev_get_drvdata(dev); 990 struct amdgpu_device *adev = drm_to_adev(ddev); 991 int size = 0; 992 int ret = 0; 993 994 if (amdgpu_in_reset(adev)) 995 return -EPERM; 996 if (adev->in_suspend && !adev->in_runpm) 997 return -EPERM; 998 999 ret = pm_runtime_get_if_active(ddev->dev); 1000 if (ret <= 0) 1001 return ret ?: -EPERM; 1002 1003 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); 1004 if (ret == -ENOENT) 1005 size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1006 1007 if (size == 0) 1008 size = sysfs_emit(buf, "\n"); 1009 1010 pm_runtime_put_autosuspend(ddev->dev); 1011 1012 return size; 1013 } 1014 1015 /* 1016 * Worst case: 32 bits individually specified, in octal at 12 characters 1017 * per line (+1 for \n). 1018 */ 1019 #define AMDGPU_MASK_BUF_MAX (32 * 13) 1020 1021 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1022 { 1023 int ret; 1024 unsigned long level; 1025 char *sub_str = NULL; 1026 char *tmp; 1027 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1028 const char delimiter[3] = {' ', '\n', '\0'}; 1029 size_t bytes; 1030 1031 *mask = 0; 1032 1033 bytes = min(count, sizeof(buf_cpy) - 1); 1034 memcpy(buf_cpy, buf, bytes); 1035 buf_cpy[bytes] = '\0'; 1036 tmp = buf_cpy; 1037 while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1038 if (strlen(sub_str)) { 1039 ret = kstrtoul(sub_str, 0, &level); 1040 if (ret || level > 31) 1041 return -EINVAL; 1042 *mask |= 1 << level; 1043 } else 1044 break; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 1051 enum pp_clock_type type, 1052 const char *buf, 1053 size_t count) 1054 { 1055 struct drm_device *ddev = dev_get_drvdata(dev); 1056 struct amdgpu_device *adev = drm_to_adev(ddev); 1057 int ret; 1058 uint32_t mask = 0; 1059 1060 if (amdgpu_in_reset(adev)) 1061 return -EPERM; 1062 if (adev->in_suspend && !adev->in_runpm) 1063 return -EPERM; 1064 1065 ret = amdgpu_read_mask(buf, count, &mask); 1066 if (ret) 1067 return ret; 1068 1069 ret = pm_runtime_resume_and_get(ddev->dev); 1070 if (ret < 0) 1071 return ret; 1072 1073 ret = amdgpu_dpm_force_clock_level(adev, type, mask); 1074 1075 pm_runtime_mark_last_busy(ddev->dev); 1076 pm_runtime_put_autosuspend(ddev->dev); 1077 1078 if (ret) 1079 return -EINVAL; 1080 1081 return count; 1082 } 1083 1084 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1085 struct device_attribute *attr, 1086 char *buf) 1087 { 1088 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 1089 } 1090 1091 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1092 struct device_attribute *attr, 1093 const char *buf, 1094 size_t count) 1095 { 1096 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 1097 } 1098 1099 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1100 struct device_attribute *attr, 1101 char *buf) 1102 { 1103 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1104 } 1105 1106 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1107 struct device_attribute *attr, 1108 const char *buf, 1109 size_t count) 1110 { 1111 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1112 } 1113 1114 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1115 struct device_attribute *attr, 1116 char *buf) 1117 { 1118 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1119 } 1120 1121 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1122 struct device_attribute *attr, 1123 const char *buf, 1124 size_t count) 1125 { 1126 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1127 } 1128 1129 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1130 struct device_attribute *attr, 1131 char *buf) 1132 { 1133 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1134 } 1135 1136 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1137 struct device_attribute *attr, 1138 const char *buf, 1139 size_t count) 1140 { 1141 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1142 } 1143 1144 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 1145 struct device_attribute *attr, 1146 char *buf) 1147 { 1148 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 1149 } 1150 1151 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 1152 struct device_attribute *attr, 1153 const char *buf, 1154 size_t count) 1155 { 1156 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 1157 } 1158 1159 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev, 1160 struct device_attribute *attr, 1161 char *buf) 1162 { 1163 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf); 1164 } 1165 1166 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev, 1167 struct device_attribute *attr, 1168 const char *buf, 1169 size_t count) 1170 { 1171 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count); 1172 } 1173 1174 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 1175 struct device_attribute *attr, 1176 char *buf) 1177 { 1178 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 1179 } 1180 1181 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 1182 struct device_attribute *attr, 1183 const char *buf, 1184 size_t count) 1185 { 1186 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 1187 } 1188 1189 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev, 1190 struct device_attribute *attr, 1191 char *buf) 1192 { 1193 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf); 1194 } 1195 1196 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev, 1197 struct device_attribute *attr, 1198 const char *buf, 1199 size_t count) 1200 { 1201 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count); 1202 } 1203 1204 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1205 struct device_attribute *attr, 1206 char *buf) 1207 { 1208 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1209 } 1210 1211 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1212 struct device_attribute *attr, 1213 const char *buf, 1214 size_t count) 1215 { 1216 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1217 } 1218 1219 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1220 struct device_attribute *attr, 1221 char *buf) 1222 { 1223 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1224 } 1225 1226 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1227 struct device_attribute *attr, 1228 const char *buf, 1229 size_t count) 1230 { 1231 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1232 } 1233 1234 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1235 struct device_attribute *attr, 1236 char *buf) 1237 { 1238 struct drm_device *ddev = dev_get_drvdata(dev); 1239 struct amdgpu_device *adev = drm_to_adev(ddev); 1240 uint32_t value = 0; 1241 int ret; 1242 1243 if (amdgpu_in_reset(adev)) 1244 return -EPERM; 1245 if (adev->in_suspend && !adev->in_runpm) 1246 return -EPERM; 1247 1248 ret = pm_runtime_get_if_active(ddev->dev); 1249 if (ret <= 0) 1250 return ret ?: -EPERM; 1251 1252 value = amdgpu_dpm_get_sclk_od(adev); 1253 1254 pm_runtime_put_autosuspend(ddev->dev); 1255 1256 return sysfs_emit(buf, "%d\n", value); 1257 } 1258 1259 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1260 struct device_attribute *attr, 1261 const char *buf, 1262 size_t count) 1263 { 1264 struct drm_device *ddev = dev_get_drvdata(dev); 1265 struct amdgpu_device *adev = drm_to_adev(ddev); 1266 int ret; 1267 long int value; 1268 1269 if (amdgpu_in_reset(adev)) 1270 return -EPERM; 1271 if (adev->in_suspend && !adev->in_runpm) 1272 return -EPERM; 1273 1274 ret = kstrtol(buf, 0, &value); 1275 1276 if (ret) 1277 return -EINVAL; 1278 1279 ret = pm_runtime_resume_and_get(ddev->dev); 1280 if (ret < 0) 1281 return ret; 1282 1283 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1284 1285 pm_runtime_mark_last_busy(ddev->dev); 1286 pm_runtime_put_autosuspend(ddev->dev); 1287 1288 return count; 1289 } 1290 1291 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1292 struct device_attribute *attr, 1293 char *buf) 1294 { 1295 struct drm_device *ddev = dev_get_drvdata(dev); 1296 struct amdgpu_device *adev = drm_to_adev(ddev); 1297 uint32_t value = 0; 1298 int ret; 1299 1300 if (amdgpu_in_reset(adev)) 1301 return -EPERM; 1302 if (adev->in_suspend && !adev->in_runpm) 1303 return -EPERM; 1304 1305 ret = pm_runtime_get_if_active(ddev->dev); 1306 if (ret <= 0) 1307 return ret ?: -EPERM; 1308 1309 value = amdgpu_dpm_get_mclk_od(adev); 1310 1311 pm_runtime_put_autosuspend(ddev->dev); 1312 1313 return sysfs_emit(buf, "%d\n", value); 1314 } 1315 1316 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1317 struct device_attribute *attr, 1318 const char *buf, 1319 size_t count) 1320 { 1321 struct drm_device *ddev = dev_get_drvdata(dev); 1322 struct amdgpu_device *adev = drm_to_adev(ddev); 1323 int ret; 1324 long int value; 1325 1326 if (amdgpu_in_reset(adev)) 1327 return -EPERM; 1328 if (adev->in_suspend && !adev->in_runpm) 1329 return -EPERM; 1330 1331 ret = kstrtol(buf, 0, &value); 1332 1333 if (ret) 1334 return -EINVAL; 1335 1336 ret = pm_runtime_resume_and_get(ddev->dev); 1337 if (ret < 0) 1338 return ret; 1339 1340 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1341 1342 pm_runtime_mark_last_busy(ddev->dev); 1343 pm_runtime_put_autosuspend(ddev->dev); 1344 1345 return count; 1346 } 1347 1348 /** 1349 * DOC: pp_power_profile_mode 1350 * 1351 * The amdgpu driver provides a sysfs API for adjusting the heuristics 1352 * related to switching between power levels in a power state. The file 1353 * pp_power_profile_mode is used for this. 1354 * 1355 * Reading this file outputs a list of all of the predefined power profiles 1356 * and the relevant heuristics settings for that profile. 1357 * 1358 * To select a profile or create a custom profile, first select manual using 1359 * power_dpm_force_performance_level. Writing the number of a predefined 1360 * profile to pp_power_profile_mode will enable those heuristics. To 1361 * create a custom set of heuristics, write a string of numbers to the file 1362 * starting with the number of the custom profile along with a setting 1363 * for each heuristic parameter. Due to differences across asic families 1364 * the heuristic parameters vary from family to family. 1365 * 1366 */ 1367 1368 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1369 struct device_attribute *attr, 1370 char *buf) 1371 { 1372 struct drm_device *ddev = dev_get_drvdata(dev); 1373 struct amdgpu_device *adev = drm_to_adev(ddev); 1374 ssize_t size; 1375 int ret; 1376 1377 if (amdgpu_in_reset(adev)) 1378 return -EPERM; 1379 if (adev->in_suspend && !adev->in_runpm) 1380 return -EPERM; 1381 1382 ret = pm_runtime_get_if_active(ddev->dev); 1383 if (ret <= 0) 1384 return ret ?: -EPERM; 1385 1386 size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1387 if (size <= 0) 1388 size = sysfs_emit(buf, "\n"); 1389 1390 pm_runtime_put_autosuspend(ddev->dev); 1391 1392 return size; 1393 } 1394 1395 1396 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1397 struct device_attribute *attr, 1398 const char *buf, 1399 size_t count) 1400 { 1401 int ret; 1402 struct drm_device *ddev = dev_get_drvdata(dev); 1403 struct amdgpu_device *adev = drm_to_adev(ddev); 1404 uint32_t parameter_size = 0; 1405 long parameter[64]; 1406 char *sub_str, buf_cpy[128]; 1407 char *tmp_str; 1408 uint32_t i = 0; 1409 char tmp[2]; 1410 long int profile_mode = 0; 1411 const char delimiter[3] = {' ', '\n', '\0'}; 1412 1413 if (amdgpu_in_reset(adev)) 1414 return -EPERM; 1415 if (adev->in_suspend && !adev->in_runpm) 1416 return -EPERM; 1417 1418 tmp[0] = *(buf); 1419 tmp[1] = '\0'; 1420 ret = kstrtol(tmp, 0, &profile_mode); 1421 if (ret) 1422 return -EINVAL; 1423 1424 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1425 if (count < 2 || count > 127) 1426 return -EINVAL; 1427 while (isspace(*++buf)) 1428 i++; 1429 memcpy(buf_cpy, buf, count-i); 1430 tmp_str = buf_cpy; 1431 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1432 if (strlen(sub_str) == 0) 1433 continue; 1434 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1435 if (ret) 1436 return -EINVAL; 1437 parameter_size++; 1438 while (isspace(*tmp_str)) 1439 tmp_str++; 1440 } 1441 } 1442 parameter[parameter_size] = profile_mode; 1443 1444 ret = pm_runtime_resume_and_get(ddev->dev); 1445 if (ret < 0) 1446 return ret; 1447 1448 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1449 1450 pm_runtime_mark_last_busy(ddev->dev); 1451 pm_runtime_put_autosuspend(ddev->dev); 1452 1453 if (!ret) 1454 return count; 1455 1456 return -EINVAL; 1457 } 1458 1459 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev, 1460 enum amd_pp_sensors sensor, 1461 void *query) 1462 { 1463 int r, size = sizeof(uint32_t); 1464 1465 if (amdgpu_in_reset(adev)) 1466 return -EPERM; 1467 if (adev->in_suspend && !adev->in_runpm) 1468 return -EPERM; 1469 1470 r = pm_runtime_get_if_active(adev->dev); 1471 if (r <= 0) 1472 return r ?: -EPERM; 1473 1474 /* get the sensor value */ 1475 r = amdgpu_dpm_read_sensor(adev, sensor, query, &size); 1476 1477 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1478 1479 return r; 1480 } 1481 1482 /** 1483 * DOC: gpu_busy_percent 1484 * 1485 * The amdgpu driver provides a sysfs API for reading how busy the GPU 1486 * is as a percentage. The file gpu_busy_percent is used for this. 1487 * The SMU firmware computes a percentage of load based on the 1488 * aggregate activity level in the IP cores. 1489 */ 1490 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1491 struct device_attribute *attr, 1492 char *buf) 1493 { 1494 struct drm_device *ddev = dev_get_drvdata(dev); 1495 struct amdgpu_device *adev = drm_to_adev(ddev); 1496 unsigned int value; 1497 int r; 1498 1499 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value); 1500 if (r) 1501 return r; 1502 1503 return sysfs_emit(buf, "%d\n", value); 1504 } 1505 1506 /** 1507 * DOC: mem_busy_percent 1508 * 1509 * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1510 * is as a percentage. The file mem_busy_percent is used for this. 1511 * The SMU firmware computes a percentage of load based on the 1512 * aggregate activity level in the IP cores. 1513 */ 1514 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1515 struct device_attribute *attr, 1516 char *buf) 1517 { 1518 struct drm_device *ddev = dev_get_drvdata(dev); 1519 struct amdgpu_device *adev = drm_to_adev(ddev); 1520 unsigned int value; 1521 int r; 1522 1523 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value); 1524 if (r) 1525 return r; 1526 1527 return sysfs_emit(buf, "%d\n", value); 1528 } 1529 1530 /** 1531 * DOC: vcn_busy_percent 1532 * 1533 * The amdgpu driver provides a sysfs API for reading how busy the VCN 1534 * is as a percentage. The file vcn_busy_percent is used for this. 1535 * The SMU firmware computes a percentage of load based on the 1536 * aggregate activity level in the IP cores. 1537 */ 1538 static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev, 1539 struct device_attribute *attr, 1540 char *buf) 1541 { 1542 struct drm_device *ddev = dev_get_drvdata(dev); 1543 struct amdgpu_device *adev = drm_to_adev(ddev); 1544 unsigned int value; 1545 int r; 1546 1547 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD, &value); 1548 if (r) 1549 return r; 1550 1551 return sysfs_emit(buf, "%d\n", value); 1552 } 1553 1554 /** 1555 * DOC: pcie_bw 1556 * 1557 * The amdgpu driver provides a sysfs API for estimating how much data 1558 * has been received and sent by the GPU in the last second through PCIe. 1559 * The file pcie_bw is used for this. 1560 * The Perf counters count the number of received and sent messages and return 1561 * those values, as well as the maximum payload size of a PCIe packet (mps). 1562 * Note that it is not possible to easily and quickly obtain the size of each 1563 * packet transmitted, so we output the max payload size (mps) to allow for 1564 * quick estimation of the PCIe bandwidth usage 1565 */ 1566 static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1567 struct device_attribute *attr, 1568 char *buf) 1569 { 1570 struct drm_device *ddev = dev_get_drvdata(dev); 1571 struct amdgpu_device *adev = drm_to_adev(ddev); 1572 uint64_t count0 = 0, count1 = 0; 1573 int ret; 1574 1575 if (amdgpu_in_reset(adev)) 1576 return -EPERM; 1577 if (adev->in_suspend && !adev->in_runpm) 1578 return -EPERM; 1579 1580 if (adev->flags & AMD_IS_APU) 1581 return -ENODATA; 1582 1583 if (!adev->asic_funcs->get_pcie_usage) 1584 return -ENODATA; 1585 1586 ret = pm_runtime_get_if_active(ddev->dev); 1587 if (ret <= 0) 1588 return ret ?: -EPERM; 1589 1590 amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1591 1592 pm_runtime_put_autosuspend(ddev->dev); 1593 1594 return sysfs_emit(buf, "%llu %llu %i\n", 1595 count0, count1, pcie_get_mps(adev->pdev)); 1596 } 1597 1598 /** 1599 * DOC: unique_id 1600 * 1601 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1602 * The file unique_id is used for this. 1603 * This will provide a Unique ID that will persist from machine to machine 1604 * 1605 * NOTE: This will only work for GFX9 and newer. This file will be absent 1606 * on unsupported ASICs (GFX8 and older) 1607 */ 1608 static ssize_t amdgpu_get_unique_id(struct device *dev, 1609 struct device_attribute *attr, 1610 char *buf) 1611 { 1612 struct drm_device *ddev = dev_get_drvdata(dev); 1613 struct amdgpu_device *adev = drm_to_adev(ddev); 1614 1615 if (amdgpu_in_reset(adev)) 1616 return -EPERM; 1617 if (adev->in_suspend && !adev->in_runpm) 1618 return -EPERM; 1619 1620 if (adev->unique_id) 1621 return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1622 1623 return 0; 1624 } 1625 1626 /** 1627 * DOC: thermal_throttling_logging 1628 * 1629 * Thermal throttling pulls down the clock frequency and thus the performance. 1630 * It's an useful mechanism to protect the chip from overheating. Since it 1631 * impacts performance, the user controls whether it is enabled and if so, 1632 * the log frequency. 1633 * 1634 * Reading back the file shows you the status(enabled or disabled) and 1635 * the interval(in seconds) between each thermal logging. 1636 * 1637 * Writing an integer to the file, sets a new logging interval, in seconds. 1638 * The value should be between 1 and 3600. If the value is less than 1, 1639 * thermal logging is disabled. Values greater than 3600 are ignored. 1640 */ 1641 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1642 struct device_attribute *attr, 1643 char *buf) 1644 { 1645 struct drm_device *ddev = dev_get_drvdata(dev); 1646 struct amdgpu_device *adev = drm_to_adev(ddev); 1647 1648 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 1649 adev_to_drm(adev)->unique, 1650 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1651 adev->throttling_logging_rs.interval / HZ + 1); 1652 } 1653 1654 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1655 struct device_attribute *attr, 1656 const char *buf, 1657 size_t count) 1658 { 1659 struct drm_device *ddev = dev_get_drvdata(dev); 1660 struct amdgpu_device *adev = drm_to_adev(ddev); 1661 long throttling_logging_interval; 1662 unsigned long flags; 1663 int ret = 0; 1664 1665 ret = kstrtol(buf, 0, &throttling_logging_interval); 1666 if (ret) 1667 return ret; 1668 1669 if (throttling_logging_interval > 3600) 1670 return -EINVAL; 1671 1672 if (throttling_logging_interval > 0) { 1673 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1674 /* 1675 * Reset the ratelimit timer internals. 1676 * This can effectively restart the timer. 1677 */ 1678 adev->throttling_logging_rs.interval = 1679 (throttling_logging_interval - 1) * HZ; 1680 adev->throttling_logging_rs.begin = 0; 1681 adev->throttling_logging_rs.printed = 0; 1682 adev->throttling_logging_rs.missed = 0; 1683 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1684 1685 atomic_set(&adev->throttling_logging_enabled, 1); 1686 } else { 1687 atomic_set(&adev->throttling_logging_enabled, 0); 1688 } 1689 1690 return count; 1691 } 1692 1693 /** 1694 * DOC: apu_thermal_cap 1695 * 1696 * The amdgpu driver provides a sysfs API for retrieving/updating thermal 1697 * limit temperature in millidegrees Celsius 1698 * 1699 * Reading back the file shows you core limit value 1700 * 1701 * Writing an integer to the file, sets a new thermal limit. The value 1702 * should be between 0 and 100. If the value is less than 0 or greater 1703 * than 100, then the write request will be ignored. 1704 */ 1705 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, 1706 struct device_attribute *attr, 1707 char *buf) 1708 { 1709 int ret, size; 1710 u32 limit; 1711 struct drm_device *ddev = dev_get_drvdata(dev); 1712 struct amdgpu_device *adev = drm_to_adev(ddev); 1713 1714 ret = pm_runtime_get_if_active(ddev->dev); 1715 if (ret <= 0) 1716 return ret ?: -EPERM; 1717 1718 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit); 1719 if (!ret) 1720 size = sysfs_emit(buf, "%u\n", limit); 1721 else 1722 size = sysfs_emit(buf, "failed to get thermal limit\n"); 1723 1724 pm_runtime_put_autosuspend(ddev->dev); 1725 1726 return size; 1727 } 1728 1729 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, 1730 struct device_attribute *attr, 1731 const char *buf, 1732 size_t count) 1733 { 1734 int ret; 1735 u32 value; 1736 struct drm_device *ddev = dev_get_drvdata(dev); 1737 struct amdgpu_device *adev = drm_to_adev(ddev); 1738 1739 ret = kstrtou32(buf, 10, &value); 1740 if (ret) 1741 return ret; 1742 1743 if (value > 100) { 1744 dev_err(dev, "Invalid argument !\n"); 1745 return -EINVAL; 1746 } 1747 1748 ret = pm_runtime_resume_and_get(ddev->dev); 1749 if (ret < 0) 1750 return ret; 1751 1752 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value); 1753 if (ret) { 1754 pm_runtime_mark_last_busy(ddev->dev); 1755 pm_runtime_put_autosuspend(ddev->dev); 1756 dev_err(dev, "failed to update thermal limit\n"); 1757 return ret; 1758 } 1759 1760 pm_runtime_mark_last_busy(ddev->dev); 1761 pm_runtime_put_autosuspend(ddev->dev); 1762 1763 return count; 1764 } 1765 1766 static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev, 1767 struct amdgpu_device_attr *attr, 1768 uint32_t mask, 1769 enum amdgpu_device_attr_states *states) 1770 { 1771 if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP) 1772 *states = ATTR_STATE_UNSUPPORTED; 1773 1774 return 0; 1775 } 1776 1777 static ssize_t amdgpu_get_pm_metrics(struct device *dev, 1778 struct device_attribute *attr, char *buf) 1779 { 1780 struct drm_device *ddev = dev_get_drvdata(dev); 1781 struct amdgpu_device *adev = drm_to_adev(ddev); 1782 ssize_t size = 0; 1783 int ret; 1784 1785 if (amdgpu_in_reset(adev)) 1786 return -EPERM; 1787 if (adev->in_suspend && !adev->in_runpm) 1788 return -EPERM; 1789 1790 ret = pm_runtime_get_if_active(ddev->dev); 1791 if (ret <= 0) 1792 return ret ?: -EPERM; 1793 1794 size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE); 1795 1796 pm_runtime_put_autosuspend(ddev->dev); 1797 1798 return size; 1799 } 1800 1801 /** 1802 * DOC: gpu_metrics 1803 * 1804 * The amdgpu driver provides a sysfs API for retrieving current gpu 1805 * metrics data. The file gpu_metrics is used for this. Reading the 1806 * file will dump all the current gpu metrics data. 1807 * 1808 * These data include temperature, frequency, engines utilization, 1809 * power consume, throttler status, fan speed and cpu core statistics( 1810 * available for APU only). That's it will give a snapshot of all sensors 1811 * at the same time. 1812 */ 1813 static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1814 struct device_attribute *attr, 1815 char *buf) 1816 { 1817 struct drm_device *ddev = dev_get_drvdata(dev); 1818 struct amdgpu_device *adev = drm_to_adev(ddev); 1819 void *gpu_metrics; 1820 ssize_t size = 0; 1821 int ret; 1822 1823 if (amdgpu_in_reset(adev)) 1824 return -EPERM; 1825 if (adev->in_suspend && !adev->in_runpm) 1826 return -EPERM; 1827 1828 ret = pm_runtime_get_if_active(ddev->dev); 1829 if (ret <= 0) 1830 return ret ?: -EPERM; 1831 1832 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1833 if (size <= 0) 1834 goto out; 1835 1836 if (size >= PAGE_SIZE) 1837 size = PAGE_SIZE - 1; 1838 1839 memcpy(buf, gpu_metrics, size); 1840 1841 out: 1842 pm_runtime_put_autosuspend(ddev->dev); 1843 1844 return size; 1845 } 1846 1847 static int amdgpu_show_powershift_percent(struct device *dev, 1848 char *buf, enum amd_pp_sensors sensor) 1849 { 1850 struct drm_device *ddev = dev_get_drvdata(dev); 1851 struct amdgpu_device *adev = drm_to_adev(ddev); 1852 uint32_t ss_power; 1853 int r = 0, i; 1854 1855 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1856 if (r == -EOPNOTSUPP) { 1857 /* sensor not available on dGPU, try to read from APU */ 1858 adev = NULL; 1859 mutex_lock(&mgpu_info.mutex); 1860 for (i = 0; i < mgpu_info.num_gpu; i++) { 1861 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { 1862 adev = mgpu_info.gpu_ins[i].adev; 1863 break; 1864 } 1865 } 1866 mutex_unlock(&mgpu_info.mutex); 1867 if (adev) 1868 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1869 } 1870 1871 if (r) 1872 return r; 1873 1874 return sysfs_emit(buf, "%u%%\n", ss_power); 1875 } 1876 1877 /** 1878 * DOC: smartshift_apu_power 1879 * 1880 * The amdgpu driver provides a sysfs API for reporting APU power 1881 * shift in percentage if platform supports smartshift. Value 0 means that 1882 * there is no powershift and values between [1-100] means that the power 1883 * is shifted to APU, the percentage of boost is with respect to APU power 1884 * limit on the platform. 1885 */ 1886 1887 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, 1888 char *buf) 1889 { 1890 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE); 1891 } 1892 1893 /** 1894 * DOC: smartshift_dgpu_power 1895 * 1896 * The amdgpu driver provides a sysfs API for reporting dGPU power 1897 * shift in percentage if platform supports smartshift. Value 0 means that 1898 * there is no powershift and values between [1-100] means that the power is 1899 * shifted to dGPU, the percentage of boost is with respect to dGPU power 1900 * limit on the platform. 1901 */ 1902 1903 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, 1904 char *buf) 1905 { 1906 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE); 1907 } 1908 1909 /** 1910 * DOC: smartshift_bias 1911 * 1912 * The amdgpu driver provides a sysfs API for reporting the 1913 * smartshift(SS2.0) bias level. The value ranges from -100 to 100 1914 * and the default is 0. -100 sets maximum preference to APU 1915 * and 100 sets max perference to dGPU. 1916 */ 1917 1918 static ssize_t amdgpu_get_smartshift_bias(struct device *dev, 1919 struct device_attribute *attr, 1920 char *buf) 1921 { 1922 int r = 0; 1923 1924 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); 1925 1926 return r; 1927 } 1928 1929 static ssize_t amdgpu_set_smartshift_bias(struct device *dev, 1930 struct device_attribute *attr, 1931 const char *buf, size_t count) 1932 { 1933 struct drm_device *ddev = dev_get_drvdata(dev); 1934 struct amdgpu_device *adev = drm_to_adev(ddev); 1935 int r = 0; 1936 int bias = 0; 1937 1938 if (amdgpu_in_reset(adev)) 1939 return -EPERM; 1940 if (adev->in_suspend && !adev->in_runpm) 1941 return -EPERM; 1942 1943 r = pm_runtime_resume_and_get(ddev->dev); 1944 if (r < 0) 1945 return r; 1946 1947 r = kstrtoint(buf, 10, &bias); 1948 if (r) 1949 goto out; 1950 1951 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) 1952 bias = AMDGPU_SMARTSHIFT_MAX_BIAS; 1953 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) 1954 bias = AMDGPU_SMARTSHIFT_MIN_BIAS; 1955 1956 amdgpu_smartshift_bias = bias; 1957 r = count; 1958 1959 /* TODO: update bias level with SMU message */ 1960 1961 out: 1962 pm_runtime_mark_last_busy(ddev->dev); 1963 pm_runtime_put_autosuspend(ddev->dev); 1964 return r; 1965 } 1966 1967 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1968 uint32_t mask, enum amdgpu_device_attr_states *states) 1969 { 1970 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 1971 *states = ATTR_STATE_UNSUPPORTED; 1972 1973 return 0; 1974 } 1975 1976 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1977 uint32_t mask, enum amdgpu_device_attr_states *states) 1978 { 1979 uint32_t ss_power; 1980 1981 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 1982 *states = ATTR_STATE_UNSUPPORTED; 1983 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 1984 (void *)&ss_power)) 1985 *states = ATTR_STATE_UNSUPPORTED; 1986 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1987 (void *)&ss_power)) 1988 *states = ATTR_STATE_UNSUPPORTED; 1989 1990 return 0; 1991 } 1992 1993 static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1994 uint32_t mask, enum amdgpu_device_attr_states *states) 1995 { 1996 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 1997 1998 *states = ATTR_STATE_SUPPORTED; 1999 2000 if (!amdgpu_dpm_is_overdrive_supported(adev)) { 2001 *states = ATTR_STATE_UNSUPPORTED; 2002 return 0; 2003 } 2004 2005 /* Enable pp_od_clk_voltage node for gc 9.4.3 SRIOV/BM support */ 2006 if (gc_ver == IP_VERSION(9, 4, 3) || 2007 gc_ver == IP_VERSION(9, 4, 4)) { 2008 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2009 *states = ATTR_STATE_UNSUPPORTED; 2010 return 0; 2011 } 2012 2013 if (!(attr->flags & mask)) 2014 *states = ATTR_STATE_UNSUPPORTED; 2015 2016 return 0; 2017 } 2018 2019 static int pp_dpm_dcefclk_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2020 uint32_t mask, enum amdgpu_device_attr_states *states) 2021 { 2022 struct device_attribute *dev_attr = &attr->dev_attr; 2023 uint32_t gc_ver; 2024 2025 *states = ATTR_STATE_SUPPORTED; 2026 2027 if (!(attr->flags & mask)) { 2028 *states = ATTR_STATE_UNSUPPORTED; 2029 return 0; 2030 } 2031 2032 gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2033 /* dcefclk node is not available on gfx 11.0.3 sriov */ 2034 if ((gc_ver == IP_VERSION(11, 0, 3) && amdgpu_sriov_is_pp_one_vf(adev)) || 2035 gc_ver < IP_VERSION(9, 0, 0) || 2036 !amdgpu_device_has_display_hardware(adev)) 2037 *states = ATTR_STATE_UNSUPPORTED; 2038 2039 /* SMU MP1 does not support dcefclk level setting, 2040 * setting should not be allowed from VF if not in one VF mode. 2041 */ 2042 if (gc_ver >= IP_VERSION(10, 0, 0) || 2043 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))) { 2044 dev_attr->attr.mode &= ~S_IWUGO; 2045 dev_attr->store = NULL; 2046 } 2047 2048 return 0; 2049 } 2050 2051 static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2052 uint32_t mask, enum amdgpu_device_attr_states *states) 2053 { 2054 struct device_attribute *dev_attr = &attr->dev_attr; 2055 enum amdgpu_device_attr_id attr_id = attr->attr_id; 2056 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0); 2057 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2058 2059 *states = ATTR_STATE_SUPPORTED; 2060 2061 if (!(attr->flags & mask)) { 2062 *states = ATTR_STATE_UNSUPPORTED; 2063 return 0; 2064 } 2065 2066 if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 2067 if (gc_ver < IP_VERSION(9, 0, 0)) 2068 *states = ATTR_STATE_UNSUPPORTED; 2069 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 2070 if (mp1_ver < IP_VERSION(10, 0, 0)) 2071 *states = ATTR_STATE_UNSUPPORTED; 2072 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 2073 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2074 gc_ver == IP_VERSION(10, 3, 3) || 2075 gc_ver == IP_VERSION(10, 3, 6) || 2076 gc_ver == IP_VERSION(10, 3, 7) || 2077 gc_ver == IP_VERSION(10, 3, 0) || 2078 gc_ver == IP_VERSION(10, 1, 2) || 2079 gc_ver == IP_VERSION(11, 0, 0) || 2080 gc_ver == IP_VERSION(11, 0, 1) || 2081 gc_ver == IP_VERSION(11, 0, 4) || 2082 gc_ver == IP_VERSION(11, 5, 0) || 2083 gc_ver == IP_VERSION(11, 0, 2) || 2084 gc_ver == IP_VERSION(11, 0, 3) || 2085 gc_ver == IP_VERSION(9, 4, 3) || 2086 gc_ver == IP_VERSION(9, 4, 4))) 2087 *states = ATTR_STATE_UNSUPPORTED; 2088 } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { 2089 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2090 gc_ver == IP_VERSION(10, 3, 0) || 2091 gc_ver == IP_VERSION(11, 0, 2) || 2092 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2093 *states = ATTR_STATE_UNSUPPORTED; 2094 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 2095 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2096 gc_ver == IP_VERSION(10, 3, 3) || 2097 gc_ver == IP_VERSION(10, 3, 6) || 2098 gc_ver == IP_VERSION(10, 3, 7) || 2099 gc_ver == IP_VERSION(10, 3, 0) || 2100 gc_ver == IP_VERSION(10, 1, 2) || 2101 gc_ver == IP_VERSION(11, 0, 0) || 2102 gc_ver == IP_VERSION(11, 0, 1) || 2103 gc_ver == IP_VERSION(11, 0, 4) || 2104 gc_ver == IP_VERSION(11, 5, 0) || 2105 gc_ver == IP_VERSION(11, 0, 2) || 2106 gc_ver == IP_VERSION(11, 0, 3) || 2107 gc_ver == IP_VERSION(9, 4, 3) || 2108 gc_ver == IP_VERSION(9, 4, 4))) 2109 *states = ATTR_STATE_UNSUPPORTED; 2110 } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { 2111 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2112 gc_ver == IP_VERSION(10, 3, 0) || 2113 gc_ver == IP_VERSION(11, 0, 2) || 2114 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2115 *states = ATTR_STATE_UNSUPPORTED; 2116 } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { 2117 if (gc_ver == IP_VERSION(9, 4, 2) || 2118 gc_ver == IP_VERSION(9, 4, 3) || 2119 gc_ver == IP_VERSION(9, 4, 4)) 2120 *states = ATTR_STATE_UNSUPPORTED; 2121 } 2122 2123 switch (gc_ver) { 2124 case IP_VERSION(9, 4, 1): 2125 case IP_VERSION(9, 4, 2): 2126 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 2127 if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2128 DEVICE_ATTR_IS(pp_dpm_socclk) || 2129 DEVICE_ATTR_IS(pp_dpm_fclk)) { 2130 dev_attr->attr.mode &= ~S_IWUGO; 2131 dev_attr->store = NULL; 2132 } 2133 break; 2134 default: 2135 break; 2136 } 2137 2138 /* setting should not be allowed from VF if not in one VF mode */ 2139 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_is_pp_one_vf(adev)) { 2140 dev_attr->attr.mode &= ~S_IWUGO; 2141 dev_attr->store = NULL; 2142 } 2143 2144 return 0; 2145 } 2146 2147 /* pm policy attributes */ 2148 struct amdgpu_pm_policy_attr { 2149 struct device_attribute dev_attr; 2150 enum pp_pm_policy id; 2151 }; 2152 2153 /** 2154 * DOC: pm_policy 2155 * 2156 * Certain SOCs can support different power policies to optimize application 2157 * performance. However, this policy is provided only at SOC level and not at a 2158 * per-process level. This is useful especially when entire SOC is utilized for 2159 * dedicated workload. 2160 * 2161 * The amdgpu driver provides a sysfs API for selecting the policy. Presently, 2162 * only two types of policies are supported through this interface. 2163 * 2164 * Pstate Policy Selection - This is to select different Pstate profiles which 2165 * decides clock/throttling preferences. 2166 * 2167 * XGMI PLPD Policy Selection - When multiple devices are connected over XGMI, 2168 * this helps to select policy to be applied for per link power down. 2169 * 2170 * The list of available policies and policy levels vary between SOCs. They can 2171 * be viewed under pm_policy node directory. If SOC doesn't support any policy, 2172 * this node won't be available. The different policies supported will be 2173 * available as separate nodes under pm_policy. 2174 * 2175 * cat /sys/bus/pci/devices/.../pm_policy/<policy_type> 2176 * 2177 * Reading the policy file shows the different levels supported. The level which 2178 * is applied presently is denoted by * (asterisk). E.g., 2179 * 2180 * .. code-block:: console 2181 * 2182 * cat /sys/bus/pci/devices/.../pm_policy/soc_pstate 2183 * 0 : soc_pstate_default 2184 * 1 : soc_pstate_0 2185 * 2 : soc_pstate_1* 2186 * 3 : soc_pstate_2 2187 * 2188 * cat /sys/bus/pci/devices/.../pm_policy/xgmi_plpd 2189 * 0 : plpd_disallow 2190 * 1 : plpd_default 2191 * 2 : plpd_optimized* 2192 * 2193 * To apply a specific policy 2194 * 2195 * "echo <level> > /sys/bus/pci/devices/.../pm_policy/<policy_type>" 2196 * 2197 * For the levels listed in the example above, to select "plpd_optimized" for 2198 * XGMI and "soc_pstate_2" for soc pstate policy - 2199 * 2200 * .. code-block:: console 2201 * 2202 * echo "2" > /sys/bus/pci/devices/.../pm_policy/xgmi_plpd 2203 * echo "3" > /sys/bus/pci/devices/.../pm_policy/soc_pstate 2204 * 2205 */ 2206 static ssize_t amdgpu_get_pm_policy_attr(struct device *dev, 2207 struct device_attribute *attr, 2208 char *buf) 2209 { 2210 struct drm_device *ddev = dev_get_drvdata(dev); 2211 struct amdgpu_device *adev = drm_to_adev(ddev); 2212 struct amdgpu_pm_policy_attr *policy_attr; 2213 2214 policy_attr = 2215 container_of(attr, struct amdgpu_pm_policy_attr, dev_attr); 2216 2217 if (amdgpu_in_reset(adev)) 2218 return -EPERM; 2219 if (adev->in_suspend && !adev->in_runpm) 2220 return -EPERM; 2221 2222 return amdgpu_dpm_get_pm_policy_info(adev, policy_attr->id, buf); 2223 } 2224 2225 static ssize_t amdgpu_set_pm_policy_attr(struct device *dev, 2226 struct device_attribute *attr, 2227 const char *buf, size_t count) 2228 { 2229 struct drm_device *ddev = dev_get_drvdata(dev); 2230 struct amdgpu_device *adev = drm_to_adev(ddev); 2231 struct amdgpu_pm_policy_attr *policy_attr; 2232 int ret, num_params = 0; 2233 char delimiter[] = " \n\t"; 2234 char tmp_buf[128]; 2235 char *tmp, *param; 2236 long val; 2237 2238 if (amdgpu_in_reset(adev)) 2239 return -EPERM; 2240 if (adev->in_suspend && !adev->in_runpm) 2241 return -EPERM; 2242 2243 count = min(count, sizeof(tmp_buf)); 2244 memcpy(tmp_buf, buf, count); 2245 tmp_buf[count - 1] = '\0'; 2246 tmp = tmp_buf; 2247 2248 tmp = skip_spaces(tmp); 2249 while ((param = strsep(&tmp, delimiter))) { 2250 if (!strlen(param)) { 2251 tmp = skip_spaces(tmp); 2252 continue; 2253 } 2254 ret = kstrtol(param, 0, &val); 2255 if (ret) 2256 return -EINVAL; 2257 num_params++; 2258 if (num_params > 1) 2259 return -EINVAL; 2260 } 2261 2262 if (num_params != 1) 2263 return -EINVAL; 2264 2265 policy_attr = 2266 container_of(attr, struct amdgpu_pm_policy_attr, dev_attr); 2267 2268 ret = pm_runtime_resume_and_get(ddev->dev); 2269 if (ret < 0) 2270 return ret; 2271 2272 ret = amdgpu_dpm_set_pm_policy(adev, policy_attr->id, val); 2273 2274 pm_runtime_mark_last_busy(ddev->dev); 2275 pm_runtime_put_autosuspend(ddev->dev); 2276 2277 if (ret) 2278 return ret; 2279 2280 return count; 2281 } 2282 2283 #define AMDGPU_PM_POLICY_ATTR(_name, _id) \ 2284 static struct amdgpu_pm_policy_attr pm_policy_attr_##_name = { \ 2285 .dev_attr = __ATTR(_name, 0644, amdgpu_get_pm_policy_attr, \ 2286 amdgpu_set_pm_policy_attr), \ 2287 .id = PP_PM_POLICY_##_id, \ 2288 }; 2289 2290 #define AMDGPU_PM_POLICY_ATTR_VAR(_name) pm_policy_attr_##_name.dev_attr.attr 2291 2292 AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE) 2293 AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD) 2294 2295 static struct attribute *pm_policy_attrs[] = { 2296 &AMDGPU_PM_POLICY_ATTR_VAR(soc_pstate), 2297 &AMDGPU_PM_POLICY_ATTR_VAR(xgmi_plpd), 2298 NULL 2299 }; 2300 2301 static umode_t amdgpu_pm_policy_attr_visible(struct kobject *kobj, 2302 struct attribute *attr, int n) 2303 { 2304 struct device *dev = kobj_to_dev(kobj); 2305 struct drm_device *ddev = dev_get_drvdata(dev); 2306 struct amdgpu_device *adev = drm_to_adev(ddev); 2307 struct amdgpu_pm_policy_attr *policy_attr; 2308 2309 policy_attr = 2310 container_of(attr, struct amdgpu_pm_policy_attr, dev_attr.attr); 2311 2312 if (amdgpu_dpm_get_pm_policy_info(adev, policy_attr->id, NULL) == 2313 -ENOENT) 2314 return 0; 2315 2316 return attr->mode; 2317 } 2318 2319 const struct attribute_group amdgpu_pm_policy_attr_group = { 2320 .name = "pm_policy", 2321 .attrs = pm_policy_attrs, 2322 .is_visible = amdgpu_pm_policy_attr_visible, 2323 }; 2324 2325 static struct amdgpu_device_attr amdgpu_device_attrs[] = { 2326 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2327 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2328 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2329 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2330 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2331 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2332 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2333 .attr_update = pp_dpm_clk_default_attr_update), 2334 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2335 .attr_update = pp_dpm_clk_default_attr_update), 2336 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2337 .attr_update = pp_dpm_clk_default_attr_update), 2338 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2339 .attr_update = pp_dpm_clk_default_attr_update), 2340 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2341 .attr_update = pp_dpm_clk_default_attr_update), 2342 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2343 .attr_update = pp_dpm_clk_default_attr_update), 2344 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2345 .attr_update = pp_dpm_clk_default_attr_update), 2346 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2347 .attr_update = pp_dpm_clk_default_attr_update), 2348 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2349 .attr_update = pp_dpm_dcefclk_attr_update), 2350 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2351 .attr_update = pp_dpm_clk_default_attr_update), 2352 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 2353 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 2354 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2355 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC, 2356 .attr_update = pp_od_clk_voltage_attr_update), 2357 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2358 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2359 AMDGPU_DEVICE_ATTR_RO(vcn_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2360 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 2361 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2362 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2363 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2364 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2365 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2366 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, 2367 .attr_update = ss_power_attr_update), 2368 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, 2369 .attr_update = ss_power_attr_update), 2370 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, 2371 .attr_update = ss_bias_attr_update), 2372 AMDGPU_DEVICE_ATTR_RO(pm_metrics, ATTR_FLAG_BASIC, 2373 .attr_update = amdgpu_pm_metrics_attr_update), 2374 }; 2375 2376 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2377 uint32_t mask, enum amdgpu_device_attr_states *states) 2378 { 2379 struct device_attribute *dev_attr = &attr->dev_attr; 2380 enum amdgpu_device_attr_id attr_id = attr->attr_id; 2381 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2382 2383 if (!(attr->flags & mask)) { 2384 *states = ATTR_STATE_UNSUPPORTED; 2385 return 0; 2386 } 2387 2388 if (DEVICE_ATTR_IS(mem_busy_percent)) { 2389 if ((adev->flags & AMD_IS_APU && 2390 gc_ver != IP_VERSION(9, 4, 3)) || 2391 gc_ver == IP_VERSION(9, 0, 1)) 2392 *states = ATTR_STATE_UNSUPPORTED; 2393 } else if (DEVICE_ATTR_IS(vcn_busy_percent)) { 2394 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2395 gc_ver == IP_VERSION(10, 3, 3) || 2396 gc_ver == IP_VERSION(10, 3, 6) || 2397 gc_ver == IP_VERSION(10, 3, 7) || 2398 gc_ver == IP_VERSION(11, 0, 1) || 2399 gc_ver == IP_VERSION(11, 0, 4) || 2400 gc_ver == IP_VERSION(11, 5, 0))) 2401 *states = ATTR_STATE_UNSUPPORTED; 2402 } else if (DEVICE_ATTR_IS(pcie_bw)) { 2403 /* PCIe Perf counters won't work on APU nodes */ 2404 if (adev->flags & AMD_IS_APU || 2405 !adev->asic_funcs->get_pcie_usage) 2406 *states = ATTR_STATE_UNSUPPORTED; 2407 } else if (DEVICE_ATTR_IS(unique_id)) { 2408 switch (gc_ver) { 2409 case IP_VERSION(9, 0, 1): 2410 case IP_VERSION(9, 4, 0): 2411 case IP_VERSION(9, 4, 1): 2412 case IP_VERSION(9, 4, 2): 2413 case IP_VERSION(9, 4, 3): 2414 case IP_VERSION(9, 4, 4): 2415 case IP_VERSION(10, 3, 0): 2416 case IP_VERSION(11, 0, 0): 2417 case IP_VERSION(11, 0, 1): 2418 case IP_VERSION(11, 0, 2): 2419 case IP_VERSION(11, 0, 3): 2420 *states = ATTR_STATE_SUPPORTED; 2421 break; 2422 default: 2423 *states = ATTR_STATE_UNSUPPORTED; 2424 } 2425 } else if (DEVICE_ATTR_IS(pp_features)) { 2426 if ((adev->flags & AMD_IS_APU && 2427 gc_ver != IP_VERSION(9, 4, 3)) || 2428 gc_ver < IP_VERSION(9, 0, 0)) 2429 *states = ATTR_STATE_UNSUPPORTED; 2430 } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2431 if (gc_ver < IP_VERSION(9, 1, 0)) 2432 *states = ATTR_STATE_UNSUPPORTED; 2433 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { 2434 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) 2435 *states = ATTR_STATE_UNSUPPORTED; 2436 else if ((gc_ver == IP_VERSION(10, 3, 0) || 2437 gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev)) 2438 *states = ATTR_STATE_UNSUPPORTED; 2439 } else if (DEVICE_ATTR_IS(pp_mclk_od)) { 2440 if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP) 2441 *states = ATTR_STATE_UNSUPPORTED; 2442 } else if (DEVICE_ATTR_IS(pp_sclk_od)) { 2443 if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP) 2444 *states = ATTR_STATE_UNSUPPORTED; 2445 } else if (DEVICE_ATTR_IS(apu_thermal_cap)) { 2446 u32 limit; 2447 2448 if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) == 2449 -EOPNOTSUPP) 2450 *states = ATTR_STATE_UNSUPPORTED; 2451 } 2452 2453 switch (gc_ver) { 2454 case IP_VERSION(10, 3, 0): 2455 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) && 2456 amdgpu_sriov_vf(adev)) { 2457 dev_attr->attr.mode &= ~0222; 2458 dev_attr->store = NULL; 2459 } 2460 break; 2461 default: 2462 break; 2463 } 2464 2465 return 0; 2466 } 2467 2468 2469 static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2470 struct amdgpu_device_attr *attr, 2471 uint32_t mask, struct list_head *attr_list) 2472 { 2473 int ret = 0; 2474 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2475 struct amdgpu_device_attr_entry *attr_entry; 2476 struct device_attribute *dev_attr; 2477 const char *name; 2478 2479 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2480 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2481 2482 if (!attr) 2483 return -EINVAL; 2484 2485 dev_attr = &attr->dev_attr; 2486 name = dev_attr->attr.name; 2487 2488 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; 2489 2490 ret = attr_update(adev, attr, mask, &attr_states); 2491 if (ret) { 2492 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2493 name, ret); 2494 return ret; 2495 } 2496 2497 if (attr_states == ATTR_STATE_UNSUPPORTED) 2498 return 0; 2499 2500 ret = device_create_file(adev->dev, dev_attr); 2501 if (ret) { 2502 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2503 name, ret); 2504 } 2505 2506 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2507 if (!attr_entry) 2508 return -ENOMEM; 2509 2510 attr_entry->attr = attr; 2511 INIT_LIST_HEAD(&attr_entry->entry); 2512 2513 list_add_tail(&attr_entry->entry, attr_list); 2514 2515 return ret; 2516 } 2517 2518 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2519 { 2520 struct device_attribute *dev_attr = &attr->dev_attr; 2521 2522 device_remove_file(adev->dev, dev_attr); 2523 } 2524 2525 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2526 struct list_head *attr_list); 2527 2528 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2529 struct amdgpu_device_attr *attrs, 2530 uint32_t counts, 2531 uint32_t mask, 2532 struct list_head *attr_list) 2533 { 2534 int ret = 0; 2535 uint32_t i = 0; 2536 2537 for (i = 0; i < counts; i++) { 2538 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2539 if (ret) 2540 goto failed; 2541 } 2542 2543 return 0; 2544 2545 failed: 2546 amdgpu_device_attr_remove_groups(adev, attr_list); 2547 2548 return ret; 2549 } 2550 2551 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2552 struct list_head *attr_list) 2553 { 2554 struct amdgpu_device_attr_entry *entry, *entry_tmp; 2555 2556 if (list_empty(attr_list)) 2557 return ; 2558 2559 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2560 amdgpu_device_attr_remove(adev, entry->attr); 2561 list_del(&entry->entry); 2562 kfree(entry); 2563 } 2564 } 2565 2566 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2567 struct device_attribute *attr, 2568 char *buf) 2569 { 2570 struct amdgpu_device *adev = dev_get_drvdata(dev); 2571 int channel = to_sensor_dev_attr(attr)->index; 2572 int r, temp = 0; 2573 2574 if (channel >= PP_TEMP_MAX) 2575 return -EINVAL; 2576 2577 switch (channel) { 2578 case PP_TEMP_JUNCTION: 2579 /* get current junction temperature */ 2580 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2581 (void *)&temp); 2582 break; 2583 case PP_TEMP_EDGE: 2584 /* get current edge temperature */ 2585 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2586 (void *)&temp); 2587 break; 2588 case PP_TEMP_MEM: 2589 /* get current memory temperature */ 2590 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2591 (void *)&temp); 2592 break; 2593 default: 2594 r = -EINVAL; 2595 break; 2596 } 2597 2598 if (r) 2599 return r; 2600 2601 return sysfs_emit(buf, "%d\n", temp); 2602 } 2603 2604 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2605 struct device_attribute *attr, 2606 char *buf) 2607 { 2608 struct amdgpu_device *adev = dev_get_drvdata(dev); 2609 int hyst = to_sensor_dev_attr(attr)->index; 2610 int temp; 2611 2612 if (hyst) 2613 temp = adev->pm.dpm.thermal.min_temp; 2614 else 2615 temp = adev->pm.dpm.thermal.max_temp; 2616 2617 return sysfs_emit(buf, "%d\n", temp); 2618 } 2619 2620 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2621 struct device_attribute *attr, 2622 char *buf) 2623 { 2624 struct amdgpu_device *adev = dev_get_drvdata(dev); 2625 int hyst = to_sensor_dev_attr(attr)->index; 2626 int temp; 2627 2628 if (hyst) 2629 temp = adev->pm.dpm.thermal.min_hotspot_temp; 2630 else 2631 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2632 2633 return sysfs_emit(buf, "%d\n", temp); 2634 } 2635 2636 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2637 struct device_attribute *attr, 2638 char *buf) 2639 { 2640 struct amdgpu_device *adev = dev_get_drvdata(dev); 2641 int hyst = to_sensor_dev_attr(attr)->index; 2642 int temp; 2643 2644 if (hyst) 2645 temp = adev->pm.dpm.thermal.min_mem_temp; 2646 else 2647 temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2648 2649 return sysfs_emit(buf, "%d\n", temp); 2650 } 2651 2652 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2653 struct device_attribute *attr, 2654 char *buf) 2655 { 2656 int channel = to_sensor_dev_attr(attr)->index; 2657 2658 if (channel >= PP_TEMP_MAX) 2659 return -EINVAL; 2660 2661 return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2662 } 2663 2664 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2665 struct device_attribute *attr, 2666 char *buf) 2667 { 2668 struct amdgpu_device *adev = dev_get_drvdata(dev); 2669 int channel = to_sensor_dev_attr(attr)->index; 2670 int temp = 0; 2671 2672 if (channel >= PP_TEMP_MAX) 2673 return -EINVAL; 2674 2675 switch (channel) { 2676 case PP_TEMP_JUNCTION: 2677 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2678 break; 2679 case PP_TEMP_EDGE: 2680 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2681 break; 2682 case PP_TEMP_MEM: 2683 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2684 break; 2685 } 2686 2687 return sysfs_emit(buf, "%d\n", temp); 2688 } 2689 2690 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2691 struct device_attribute *attr, 2692 char *buf) 2693 { 2694 struct amdgpu_device *adev = dev_get_drvdata(dev); 2695 u32 pwm_mode = 0; 2696 int ret; 2697 2698 if (amdgpu_in_reset(adev)) 2699 return -EPERM; 2700 if (adev->in_suspend && !adev->in_runpm) 2701 return -EPERM; 2702 2703 ret = pm_runtime_get_if_active(adev->dev); 2704 if (ret <= 0) 2705 return ret ?: -EPERM; 2706 2707 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2708 2709 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2710 2711 if (ret) 2712 return -EINVAL; 2713 2714 return sysfs_emit(buf, "%u\n", pwm_mode); 2715 } 2716 2717 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2718 struct device_attribute *attr, 2719 const char *buf, 2720 size_t count) 2721 { 2722 struct amdgpu_device *adev = dev_get_drvdata(dev); 2723 int err, ret; 2724 u32 pwm_mode; 2725 int value; 2726 2727 if (amdgpu_in_reset(adev)) 2728 return -EPERM; 2729 if (adev->in_suspend && !adev->in_runpm) 2730 return -EPERM; 2731 2732 err = kstrtoint(buf, 10, &value); 2733 if (err) 2734 return err; 2735 2736 if (value == 0) 2737 pwm_mode = AMD_FAN_CTRL_NONE; 2738 else if (value == 1) 2739 pwm_mode = AMD_FAN_CTRL_MANUAL; 2740 else if (value == 2) 2741 pwm_mode = AMD_FAN_CTRL_AUTO; 2742 else 2743 return -EINVAL; 2744 2745 ret = pm_runtime_resume_and_get(adev->dev); 2746 if (ret < 0) 2747 return ret; 2748 2749 ret = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2750 2751 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2752 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2753 2754 if (ret) 2755 return -EINVAL; 2756 2757 return count; 2758 } 2759 2760 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2761 struct device_attribute *attr, 2762 char *buf) 2763 { 2764 return sysfs_emit(buf, "%i\n", 0); 2765 } 2766 2767 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2768 struct device_attribute *attr, 2769 char *buf) 2770 { 2771 return sysfs_emit(buf, "%i\n", 255); 2772 } 2773 2774 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2775 struct device_attribute *attr, 2776 const char *buf, size_t count) 2777 { 2778 struct amdgpu_device *adev = dev_get_drvdata(dev); 2779 int err; 2780 u32 value; 2781 u32 pwm_mode; 2782 2783 if (amdgpu_in_reset(adev)) 2784 return -EPERM; 2785 if (adev->in_suspend && !adev->in_runpm) 2786 return -EPERM; 2787 2788 err = kstrtou32(buf, 10, &value); 2789 if (err) 2790 return err; 2791 2792 err = pm_runtime_resume_and_get(adev->dev); 2793 if (err < 0) 2794 return err; 2795 2796 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2797 if (err) 2798 goto out; 2799 2800 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2801 pr_info("manual fan speed control should be enabled first\n"); 2802 err = -EINVAL; 2803 goto out; 2804 } 2805 2806 err = amdgpu_dpm_set_fan_speed_pwm(adev, value); 2807 2808 out: 2809 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2810 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2811 2812 if (err) 2813 return err; 2814 2815 return count; 2816 } 2817 2818 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2819 struct device_attribute *attr, 2820 char *buf) 2821 { 2822 struct amdgpu_device *adev = dev_get_drvdata(dev); 2823 int err; 2824 u32 speed = 0; 2825 2826 if (amdgpu_in_reset(adev)) 2827 return -EPERM; 2828 if (adev->in_suspend && !adev->in_runpm) 2829 return -EPERM; 2830 2831 err = pm_runtime_get_if_active(adev->dev); 2832 if (err <= 0) 2833 return err ?: -EPERM; 2834 2835 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); 2836 2837 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2838 2839 if (err) 2840 return err; 2841 2842 return sysfs_emit(buf, "%i\n", speed); 2843 } 2844 2845 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2846 struct device_attribute *attr, 2847 char *buf) 2848 { 2849 struct amdgpu_device *adev = dev_get_drvdata(dev); 2850 int err; 2851 u32 speed = 0; 2852 2853 if (amdgpu_in_reset(adev)) 2854 return -EPERM; 2855 if (adev->in_suspend && !adev->in_runpm) 2856 return -EPERM; 2857 2858 err = pm_runtime_get_if_active(adev->dev); 2859 if (err <= 0) 2860 return err ?: -EPERM; 2861 2862 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2863 2864 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2865 2866 if (err) 2867 return err; 2868 2869 return sysfs_emit(buf, "%i\n", speed); 2870 } 2871 2872 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2873 struct device_attribute *attr, 2874 char *buf) 2875 { 2876 struct amdgpu_device *adev = dev_get_drvdata(dev); 2877 u32 min_rpm = 0; 2878 int r; 2879 2880 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2881 (void *)&min_rpm); 2882 2883 if (r) 2884 return r; 2885 2886 return sysfs_emit(buf, "%d\n", min_rpm); 2887 } 2888 2889 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2890 struct device_attribute *attr, 2891 char *buf) 2892 { 2893 struct amdgpu_device *adev = dev_get_drvdata(dev); 2894 u32 max_rpm = 0; 2895 int r; 2896 2897 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2898 (void *)&max_rpm); 2899 2900 if (r) 2901 return r; 2902 2903 return sysfs_emit(buf, "%d\n", max_rpm); 2904 } 2905 2906 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2907 struct device_attribute *attr, 2908 char *buf) 2909 { 2910 struct amdgpu_device *adev = dev_get_drvdata(dev); 2911 int err; 2912 u32 rpm = 0; 2913 2914 if (amdgpu_in_reset(adev)) 2915 return -EPERM; 2916 if (adev->in_suspend && !adev->in_runpm) 2917 return -EPERM; 2918 2919 err = pm_runtime_get_if_active(adev->dev); 2920 if (err <= 0) 2921 return err ?: -EPERM; 2922 2923 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2924 2925 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2926 2927 if (err) 2928 return err; 2929 2930 return sysfs_emit(buf, "%i\n", rpm); 2931 } 2932 2933 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2934 struct device_attribute *attr, 2935 const char *buf, size_t count) 2936 { 2937 struct amdgpu_device *adev = dev_get_drvdata(dev); 2938 int err; 2939 u32 value; 2940 u32 pwm_mode; 2941 2942 if (amdgpu_in_reset(adev)) 2943 return -EPERM; 2944 if (adev->in_suspend && !adev->in_runpm) 2945 return -EPERM; 2946 2947 err = kstrtou32(buf, 10, &value); 2948 if (err) 2949 return err; 2950 2951 err = pm_runtime_resume_and_get(adev->dev); 2952 if (err < 0) 2953 return err; 2954 2955 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2956 if (err) 2957 goto out; 2958 2959 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2960 err = -ENODATA; 2961 goto out; 2962 } 2963 2964 err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2965 2966 out: 2967 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2968 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2969 2970 if (err) 2971 return err; 2972 2973 return count; 2974 } 2975 2976 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2977 struct device_attribute *attr, 2978 char *buf) 2979 { 2980 struct amdgpu_device *adev = dev_get_drvdata(dev); 2981 u32 pwm_mode = 0; 2982 int ret; 2983 2984 if (amdgpu_in_reset(adev)) 2985 return -EPERM; 2986 if (adev->in_suspend && !adev->in_runpm) 2987 return -EPERM; 2988 2989 ret = pm_runtime_get_if_active(adev->dev); 2990 if (ret <= 0) 2991 return ret ?: -EPERM; 2992 2993 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2994 2995 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2996 2997 if (ret) 2998 return -EINVAL; 2999 3000 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 3001 } 3002 3003 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 3004 struct device_attribute *attr, 3005 const char *buf, 3006 size_t count) 3007 { 3008 struct amdgpu_device *adev = dev_get_drvdata(dev); 3009 int err; 3010 int value; 3011 u32 pwm_mode; 3012 3013 if (amdgpu_in_reset(adev)) 3014 return -EPERM; 3015 if (adev->in_suspend && !adev->in_runpm) 3016 return -EPERM; 3017 3018 err = kstrtoint(buf, 10, &value); 3019 if (err) 3020 return err; 3021 3022 if (value == 0) 3023 pwm_mode = AMD_FAN_CTRL_AUTO; 3024 else if (value == 1) 3025 pwm_mode = AMD_FAN_CTRL_MANUAL; 3026 else 3027 return -EINVAL; 3028 3029 err = pm_runtime_resume_and_get(adev->dev); 3030 if (err < 0) 3031 return err; 3032 3033 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 3034 3035 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3036 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3037 3038 if (err) 3039 return -EINVAL; 3040 3041 return count; 3042 } 3043 3044 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 3045 struct device_attribute *attr, 3046 char *buf) 3047 { 3048 struct amdgpu_device *adev = dev_get_drvdata(dev); 3049 u32 vddgfx; 3050 int r; 3051 3052 /* get the voltage */ 3053 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX, 3054 (void *)&vddgfx); 3055 if (r) 3056 return r; 3057 3058 return sysfs_emit(buf, "%d\n", vddgfx); 3059 } 3060 3061 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 3062 struct device_attribute *attr, 3063 char *buf) 3064 { 3065 return sysfs_emit(buf, "vddgfx\n"); 3066 } 3067 3068 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 3069 struct device_attribute *attr, 3070 char *buf) 3071 { 3072 struct amdgpu_device *adev = dev_get_drvdata(dev); 3073 u32 vddnb; 3074 int r; 3075 3076 /* only APUs have vddnb */ 3077 if (!(adev->flags & AMD_IS_APU)) 3078 return -EINVAL; 3079 3080 /* get the voltage */ 3081 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB, 3082 (void *)&vddnb); 3083 if (r) 3084 return r; 3085 3086 return sysfs_emit(buf, "%d\n", vddnb); 3087 } 3088 3089 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 3090 struct device_attribute *attr, 3091 char *buf) 3092 { 3093 return sysfs_emit(buf, "vddnb\n"); 3094 } 3095 3096 static int amdgpu_hwmon_get_power(struct device *dev, 3097 enum amd_pp_sensors sensor) 3098 { 3099 struct amdgpu_device *adev = dev_get_drvdata(dev); 3100 unsigned int uw; 3101 u32 query = 0; 3102 int r; 3103 3104 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query); 3105 if (r) 3106 return r; 3107 3108 /* convert to microwatts */ 3109 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 3110 3111 return uw; 3112 } 3113 3114 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 3115 struct device_attribute *attr, 3116 char *buf) 3117 { 3118 ssize_t val; 3119 3120 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER); 3121 if (val < 0) 3122 return val; 3123 3124 return sysfs_emit(buf, "%zd\n", val); 3125 } 3126 3127 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev, 3128 struct device_attribute *attr, 3129 char *buf) 3130 { 3131 ssize_t val; 3132 3133 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER); 3134 if (val < 0) 3135 return val; 3136 3137 return sysfs_emit(buf, "%zd\n", val); 3138 } 3139 3140 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, 3141 struct device_attribute *attr, 3142 char *buf, 3143 enum pp_power_limit_level pp_limit_level) 3144 { 3145 struct amdgpu_device *adev = dev_get_drvdata(dev); 3146 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; 3147 uint32_t limit; 3148 ssize_t size; 3149 int r; 3150 3151 if (amdgpu_in_reset(adev)) 3152 return -EPERM; 3153 if (adev->in_suspend && !adev->in_runpm) 3154 return -EPERM; 3155 3156 r = pm_runtime_get_if_active(adev->dev); 3157 if (r <= 0) 3158 return r ?: -EPERM; 3159 3160 r = amdgpu_dpm_get_power_limit(adev, &limit, 3161 pp_limit_level, power_type); 3162 3163 if (!r) 3164 size = sysfs_emit(buf, "%u\n", limit * 1000000); 3165 else 3166 size = sysfs_emit(buf, "\n"); 3167 3168 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3169 3170 return size; 3171 } 3172 3173 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 3174 struct device_attribute *attr, 3175 char *buf) 3176 { 3177 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN); 3178 } 3179 3180 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 3181 struct device_attribute *attr, 3182 char *buf) 3183 { 3184 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); 3185 3186 } 3187 3188 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 3189 struct device_attribute *attr, 3190 char *buf) 3191 { 3192 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); 3193 3194 } 3195 3196 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 3197 struct device_attribute *attr, 3198 char *buf) 3199 { 3200 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); 3201 3202 } 3203 3204 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 3205 struct device_attribute *attr, 3206 char *buf) 3207 { 3208 struct amdgpu_device *adev = dev_get_drvdata(dev); 3209 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 3210 3211 if (gc_ver == IP_VERSION(10, 3, 1)) 3212 return sysfs_emit(buf, "%s\n", 3213 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? 3214 "fastPPT" : "slowPPT"); 3215 else 3216 return sysfs_emit(buf, "PPT\n"); 3217 } 3218 3219 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 3220 struct device_attribute *attr, 3221 const char *buf, 3222 size_t count) 3223 { 3224 struct amdgpu_device *adev = dev_get_drvdata(dev); 3225 int limit_type = to_sensor_dev_attr(attr)->index; 3226 int err; 3227 u32 value; 3228 3229 if (amdgpu_in_reset(adev)) 3230 return -EPERM; 3231 if (adev->in_suspend && !adev->in_runpm) 3232 return -EPERM; 3233 3234 if (amdgpu_sriov_vf(adev)) 3235 return -EINVAL; 3236 3237 err = kstrtou32(buf, 10, &value); 3238 if (err) 3239 return err; 3240 3241 value = value / 1000000; /* convert to Watt */ 3242 value |= limit_type << 24; 3243 3244 err = pm_runtime_resume_and_get(adev->dev); 3245 if (err < 0) 3246 return err; 3247 3248 err = amdgpu_dpm_set_power_limit(adev, value); 3249 3250 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3251 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3252 3253 if (err) 3254 return err; 3255 3256 return count; 3257 } 3258 3259 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 3260 struct device_attribute *attr, 3261 char *buf) 3262 { 3263 struct amdgpu_device *adev = dev_get_drvdata(dev); 3264 uint32_t sclk; 3265 int r; 3266 3267 /* get the sclk */ 3268 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 3269 (void *)&sclk); 3270 if (r) 3271 return r; 3272 3273 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 3274 } 3275 3276 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 3277 struct device_attribute *attr, 3278 char *buf) 3279 { 3280 return sysfs_emit(buf, "sclk\n"); 3281 } 3282 3283 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 3284 struct device_attribute *attr, 3285 char *buf) 3286 { 3287 struct amdgpu_device *adev = dev_get_drvdata(dev); 3288 uint32_t mclk; 3289 int r; 3290 3291 /* get the sclk */ 3292 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 3293 (void *)&mclk); 3294 if (r) 3295 return r; 3296 3297 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 3298 } 3299 3300 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 3301 struct device_attribute *attr, 3302 char *buf) 3303 { 3304 return sysfs_emit(buf, "mclk\n"); 3305 } 3306 3307 /** 3308 * DOC: hwmon 3309 * 3310 * The amdgpu driver exposes the following sensor interfaces: 3311 * 3312 * - GPU temperature (via the on-die sensor) 3313 * 3314 * - GPU voltage 3315 * 3316 * - Northbridge voltage (APUs only) 3317 * 3318 * - GPU power 3319 * 3320 * - GPU fan 3321 * 3322 * - GPU gfx/compute engine clock 3323 * 3324 * - GPU memory clock (dGPU only) 3325 * 3326 * hwmon interfaces for GPU temperature: 3327 * 3328 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3329 * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3330 * 3331 * - temp[1-3]_label: temperature channel label 3332 * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3333 * 3334 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3335 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3336 * 3337 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3338 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3339 * 3340 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3341 * - these are supported on SOC15 dGPUs only 3342 * 3343 * hwmon interfaces for GPU voltage: 3344 * 3345 * - in0_input: the voltage on the GPU in millivolts 3346 * 3347 * - in1_input: the voltage on the Northbridge in millivolts 3348 * 3349 * hwmon interfaces for GPU power: 3350 * 3351 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. 3352 * 3353 * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU. 3354 * 3355 * - power1_cap_min: minimum cap supported in microWatts 3356 * 3357 * - power1_cap_max: maximum cap supported in microWatts 3358 * 3359 * - power1_cap: selected power cap in microWatts 3360 * 3361 * hwmon interfaces for GPU fan: 3362 * 3363 * - pwm1: pulse width modulation fan level (0-255) 3364 * 3365 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3366 * 3367 * - pwm1_min: pulse width modulation fan control minimum level (0) 3368 * 3369 * - pwm1_max: pulse width modulation fan control maximum level (255) 3370 * 3371 * - fan1_min: a minimum value Unit: revolution/min (RPM) 3372 * 3373 * - fan1_max: a maximum value Unit: revolution/max (RPM) 3374 * 3375 * - fan1_input: fan speed in RPM 3376 * 3377 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3378 * 3379 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3380 * 3381 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. 3382 * That will get the former one overridden. 3383 * 3384 * hwmon interfaces for GPU clocks: 3385 * 3386 * - freq1_input: the gfx/compute clock in hertz 3387 * 3388 * - freq2_input: the memory clock in hertz 3389 * 3390 * You can use hwmon tools like sensors to view this information on your system. 3391 * 3392 */ 3393 3394 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3395 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3396 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3397 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3398 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3399 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3400 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3401 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3402 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3403 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3404 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3405 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3406 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3407 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3408 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3409 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3410 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3411 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3412 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3413 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3414 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3415 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3416 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3417 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3418 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3419 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3420 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3421 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3422 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3423 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0); 3424 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3425 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3426 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3427 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3428 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3429 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3430 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3431 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3432 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 3433 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3434 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3435 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3436 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3437 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3438 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3439 3440 static struct attribute *hwmon_attributes[] = { 3441 &sensor_dev_attr_temp1_input.dev_attr.attr, 3442 &sensor_dev_attr_temp1_crit.dev_attr.attr, 3443 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3444 &sensor_dev_attr_temp2_input.dev_attr.attr, 3445 &sensor_dev_attr_temp2_crit.dev_attr.attr, 3446 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3447 &sensor_dev_attr_temp3_input.dev_attr.attr, 3448 &sensor_dev_attr_temp3_crit.dev_attr.attr, 3449 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3450 &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3451 &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3452 &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3453 &sensor_dev_attr_temp1_label.dev_attr.attr, 3454 &sensor_dev_attr_temp2_label.dev_attr.attr, 3455 &sensor_dev_attr_temp3_label.dev_attr.attr, 3456 &sensor_dev_attr_pwm1.dev_attr.attr, 3457 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3458 &sensor_dev_attr_pwm1_min.dev_attr.attr, 3459 &sensor_dev_attr_pwm1_max.dev_attr.attr, 3460 &sensor_dev_attr_fan1_input.dev_attr.attr, 3461 &sensor_dev_attr_fan1_min.dev_attr.attr, 3462 &sensor_dev_attr_fan1_max.dev_attr.attr, 3463 &sensor_dev_attr_fan1_target.dev_attr.attr, 3464 &sensor_dev_attr_fan1_enable.dev_attr.attr, 3465 &sensor_dev_attr_in0_input.dev_attr.attr, 3466 &sensor_dev_attr_in0_label.dev_attr.attr, 3467 &sensor_dev_attr_in1_input.dev_attr.attr, 3468 &sensor_dev_attr_in1_label.dev_attr.attr, 3469 &sensor_dev_attr_power1_average.dev_attr.attr, 3470 &sensor_dev_attr_power1_input.dev_attr.attr, 3471 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3472 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3473 &sensor_dev_attr_power1_cap.dev_attr.attr, 3474 &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3475 &sensor_dev_attr_power1_label.dev_attr.attr, 3476 &sensor_dev_attr_power2_average.dev_attr.attr, 3477 &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3478 &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3479 &sensor_dev_attr_power2_cap.dev_attr.attr, 3480 &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3481 &sensor_dev_attr_power2_label.dev_attr.attr, 3482 &sensor_dev_attr_freq1_input.dev_attr.attr, 3483 &sensor_dev_attr_freq1_label.dev_attr.attr, 3484 &sensor_dev_attr_freq2_input.dev_attr.attr, 3485 &sensor_dev_attr_freq2_label.dev_attr.attr, 3486 NULL 3487 }; 3488 3489 static umode_t hwmon_attributes_visible(struct kobject *kobj, 3490 struct attribute *attr, int index) 3491 { 3492 struct device *dev = kobj_to_dev(kobj); 3493 struct amdgpu_device *adev = dev_get_drvdata(dev); 3494 umode_t effective_mode = attr->mode; 3495 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 3496 uint32_t tmp; 3497 3498 /* under pp one vf mode manage of hwmon attributes is not supported */ 3499 if (amdgpu_sriov_is_pp_one_vf(adev)) 3500 effective_mode &= ~S_IWUSR; 3501 3502 /* Skip fan attributes if fan is not present */ 3503 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3504 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3505 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3506 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3507 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3508 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3509 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3510 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3511 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3512 return 0; 3513 3514 /* Skip fan attributes on APU */ 3515 if ((adev->flags & AMD_IS_APU) && 3516 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3517 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3518 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3519 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3520 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3521 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3522 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3523 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3524 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3525 return 0; 3526 3527 /* Skip crit temp on APU */ 3528 if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || 3529 (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4))) && 3530 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3531 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3532 return 0; 3533 3534 /* Skip limit attributes if DPM is not enabled */ 3535 if (!adev->pm.dpm_enabled && 3536 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3537 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3538 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3539 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3540 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3541 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3542 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3543 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3544 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3545 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3546 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3547 return 0; 3548 3549 /* mask fan attributes if we have no bindings for this asic to expose */ 3550 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3551 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3552 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && 3553 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3554 effective_mode &= ~S_IRUGO; 3555 3556 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3557 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3558 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && 3559 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3560 effective_mode &= ~S_IWUSR; 3561 3562 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ 3563 if (((adev->family == AMDGPU_FAMILY_SI) || 3564 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && 3565 (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)))) && 3566 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3567 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3568 attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3569 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3570 return 0; 3571 3572 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ 3573 if (((adev->family == AMDGPU_FAMILY_SI) || 3574 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && 3575 (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3576 return 0; 3577 3578 /* not all products support both average and instantaneous */ 3579 if (attr == &sensor_dev_attr_power1_average.dev_attr.attr && 3580 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP) 3581 return 0; 3582 if (attr == &sensor_dev_attr_power1_input.dev_attr.attr && 3583 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP) 3584 return 0; 3585 3586 /* hide max/min values if we can't both query and manage the fan */ 3587 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3588 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3589 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3590 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && 3591 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3592 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3593 return 0; 3594 3595 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3596 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && 3597 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3598 attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3599 return 0; 3600 3601 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3602 adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ 3603 (gc_ver == IP_VERSION(9, 4, 3) || 3604 gc_ver == IP_VERSION(9, 4, 4))) && 3605 (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3606 attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3607 return 0; 3608 3609 /* only APUs other than gc 9,4,3 have vddnb */ 3610 if ((!(adev->flags & AMD_IS_APU) || 3611 (gc_ver == IP_VERSION(9, 4, 3) || 3612 gc_ver == IP_VERSION(9, 4, 4))) && 3613 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3614 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3615 return 0; 3616 3617 /* no mclk on APUs other than gc 9,4,3*/ 3618 if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) && 3619 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3620 attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3621 return 0; 3622 3623 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3624 (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)) && 3625 (attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3626 attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3627 attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3628 attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3629 attr == &sensor_dev_attr_temp3_label.dev_attr.attr || 3630 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr)) 3631 return 0; 3632 3633 /* hotspot temperature for gc 9,4,3*/ 3634 if (gc_ver == IP_VERSION(9, 4, 3) || 3635 gc_ver == IP_VERSION(9, 4, 4)) { 3636 if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr || 3637 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3638 attr == &sensor_dev_attr_temp1_label.dev_attr.attr) 3639 return 0; 3640 3641 if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3642 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr) 3643 return attr->mode; 3644 } 3645 3646 /* only SOC15 dGPUs support hotspot and mem temperatures */ 3647 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3648 (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3649 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3650 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3651 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3652 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)) 3653 return 0; 3654 3655 /* only Vangogh has fast PPT limit and power labels */ 3656 if (!(gc_ver == IP_VERSION(10, 3, 1)) && 3657 (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3658 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3659 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3660 attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 3661 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3662 attr == &sensor_dev_attr_power2_label.dev_attr.attr)) 3663 return 0; 3664 3665 return effective_mode; 3666 } 3667 3668 static const struct attribute_group hwmon_attrgroup = { 3669 .attrs = hwmon_attributes, 3670 .is_visible = hwmon_attributes_visible, 3671 }; 3672 3673 static const struct attribute_group *hwmon_groups[] = { 3674 &hwmon_attrgroup, 3675 NULL 3676 }; 3677 3678 static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev, 3679 enum pp_clock_type od_type, 3680 char *buf) 3681 { 3682 int size = 0; 3683 int ret; 3684 3685 if (amdgpu_in_reset(adev)) 3686 return -EPERM; 3687 if (adev->in_suspend && !adev->in_runpm) 3688 return -EPERM; 3689 3690 ret = pm_runtime_get_if_active(adev->dev); 3691 if (ret <= 0) 3692 return ret ?: -EPERM; 3693 3694 size = amdgpu_dpm_print_clock_levels(adev, od_type, buf); 3695 if (size == 0) 3696 size = sysfs_emit(buf, "\n"); 3697 3698 pm_runtime_put_autosuspend(adev->dev); 3699 3700 return size; 3701 } 3702 3703 static int parse_input_od_command_lines(const char *buf, 3704 size_t count, 3705 u32 *type, 3706 long *params, 3707 uint32_t *num_of_params) 3708 { 3709 const char delimiter[3] = {' ', '\n', '\0'}; 3710 uint32_t parameter_size = 0; 3711 char buf_cpy[128] = {0}; 3712 char *tmp_str, *sub_str; 3713 int ret; 3714 3715 if (count > sizeof(buf_cpy) - 1) 3716 return -EINVAL; 3717 3718 memcpy(buf_cpy, buf, count); 3719 tmp_str = buf_cpy; 3720 3721 /* skip heading spaces */ 3722 while (isspace(*tmp_str)) 3723 tmp_str++; 3724 3725 switch (*tmp_str) { 3726 case 'c': 3727 *type = PP_OD_COMMIT_DPM_TABLE; 3728 return 0; 3729 case 'r': 3730 params[parameter_size] = *type; 3731 *num_of_params = 1; 3732 *type = PP_OD_RESTORE_DEFAULT_TABLE; 3733 return 0; 3734 default: 3735 break; 3736 } 3737 3738 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 3739 if (strlen(sub_str) == 0) 3740 continue; 3741 3742 ret = kstrtol(sub_str, 0, ¶ms[parameter_size]); 3743 if (ret) 3744 return -EINVAL; 3745 parameter_size++; 3746 3747 while (isspace(*tmp_str)) 3748 tmp_str++; 3749 } 3750 3751 *num_of_params = parameter_size; 3752 3753 return 0; 3754 } 3755 3756 static int 3757 amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev, 3758 enum PP_OD_DPM_TABLE_COMMAND cmd_type, 3759 const char *in_buf, 3760 size_t count) 3761 { 3762 uint32_t parameter_size = 0; 3763 long parameter[64]; 3764 int ret; 3765 3766 if (amdgpu_in_reset(adev)) 3767 return -EPERM; 3768 if (adev->in_suspend && !adev->in_runpm) 3769 return -EPERM; 3770 3771 ret = parse_input_od_command_lines(in_buf, 3772 count, 3773 &cmd_type, 3774 parameter, 3775 ¶meter_size); 3776 if (ret) 3777 return ret; 3778 3779 ret = pm_runtime_resume_and_get(adev->dev); 3780 if (ret < 0) 3781 return ret; 3782 3783 ret = amdgpu_dpm_odn_edit_dpm_table(adev, 3784 cmd_type, 3785 parameter, 3786 parameter_size); 3787 if (ret) 3788 goto err_out; 3789 3790 if (cmd_type == PP_OD_COMMIT_DPM_TABLE) { 3791 ret = amdgpu_dpm_dispatch_task(adev, 3792 AMD_PP_TASK_READJUST_POWER_STATE, 3793 NULL); 3794 if (ret) 3795 goto err_out; 3796 } 3797 3798 pm_runtime_mark_last_busy(adev->dev); 3799 pm_runtime_put_autosuspend(adev->dev); 3800 3801 return count; 3802 3803 err_out: 3804 pm_runtime_mark_last_busy(adev->dev); 3805 pm_runtime_put_autosuspend(adev->dev); 3806 3807 return ret; 3808 } 3809 3810 /** 3811 * DOC: fan_curve 3812 * 3813 * The amdgpu driver provides a sysfs API for checking and adjusting the fan 3814 * control curve line. 3815 * 3816 * Reading back the file shows you the current settings(temperature in Celsius 3817 * degree and fan speed in pwm) applied to every anchor point of the curve line 3818 * and their permitted ranges if changable. 3819 * 3820 * Writing a desired string(with the format like "anchor_point_index temperature 3821 * fan_speed_in_pwm") to the file, change the settings for the specific anchor 3822 * point accordingly. 3823 * 3824 * When you have finished the editing, write "c" (commit) to the file to commit 3825 * your changes. 3826 * 3827 * If you want to reset to the default value, write "r" (reset) to the file to 3828 * reset them 3829 * 3830 * There are two fan control modes supported: auto and manual. With auto mode, 3831 * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature). 3832 * While with manual mode, users can set their own fan curve line as what 3833 * described here. Normally the ASIC is booted up with auto mode. Any 3834 * settings via this interface will switch the fan control to manual mode 3835 * implicitly. 3836 */ 3837 static ssize_t fan_curve_show(struct kobject *kobj, 3838 struct kobj_attribute *attr, 3839 char *buf) 3840 { 3841 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3842 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3843 3844 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf); 3845 } 3846 3847 static ssize_t fan_curve_store(struct kobject *kobj, 3848 struct kobj_attribute *attr, 3849 const char *buf, 3850 size_t count) 3851 { 3852 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3853 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3854 3855 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3856 PP_OD_EDIT_FAN_CURVE, 3857 buf, 3858 count); 3859 } 3860 3861 static umode_t fan_curve_visible(struct amdgpu_device *adev) 3862 { 3863 umode_t umode = 0000; 3864 3865 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE) 3866 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3867 3868 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET) 3869 umode |= S_IWUSR; 3870 3871 return umode; 3872 } 3873 3874 /** 3875 * DOC: acoustic_limit_rpm_threshold 3876 * 3877 * The amdgpu driver provides a sysfs API for checking and adjusting the 3878 * acoustic limit in RPM for fan control. 3879 * 3880 * Reading back the file shows you the current setting and the permitted 3881 * ranges if changable. 3882 * 3883 * Writing an integer to the file, change the setting accordingly. 3884 * 3885 * When you have finished the editing, write "c" (commit) to the file to commit 3886 * your changes. 3887 * 3888 * If you want to reset to the default value, write "r" (reset) to the file to 3889 * reset them 3890 * 3891 * This setting works under auto fan control mode only. It adjusts the PMFW's 3892 * behavior about the maximum speed in RPM the fan can spin. Setting via this 3893 * interface will switch the fan control to auto mode implicitly. 3894 */ 3895 static ssize_t acoustic_limit_threshold_show(struct kobject *kobj, 3896 struct kobj_attribute *attr, 3897 char *buf) 3898 { 3899 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3900 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3901 3902 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf); 3903 } 3904 3905 static ssize_t acoustic_limit_threshold_store(struct kobject *kobj, 3906 struct kobj_attribute *attr, 3907 const char *buf, 3908 size_t count) 3909 { 3910 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3911 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3912 3913 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3914 PP_OD_EDIT_ACOUSTIC_LIMIT, 3915 buf, 3916 count); 3917 } 3918 3919 static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev) 3920 { 3921 umode_t umode = 0000; 3922 3923 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE) 3924 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3925 3926 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET) 3927 umode |= S_IWUSR; 3928 3929 return umode; 3930 } 3931 3932 /** 3933 * DOC: acoustic_target_rpm_threshold 3934 * 3935 * The amdgpu driver provides a sysfs API for checking and adjusting the 3936 * acoustic target in RPM for fan control. 3937 * 3938 * Reading back the file shows you the current setting and the permitted 3939 * ranges if changable. 3940 * 3941 * Writing an integer to the file, change the setting accordingly. 3942 * 3943 * When you have finished the editing, write "c" (commit) to the file to commit 3944 * your changes. 3945 * 3946 * If you want to reset to the default value, write "r" (reset) to the file to 3947 * reset them 3948 * 3949 * This setting works under auto fan control mode only. It can co-exist with 3950 * other settings which can work also under auto mode. It adjusts the PMFW's 3951 * behavior about the maximum speed in RPM the fan can spin when ASIC 3952 * temperature is not greater than target temperature. Setting via this 3953 * interface will switch the fan control to auto mode implicitly. 3954 */ 3955 static ssize_t acoustic_target_threshold_show(struct kobject *kobj, 3956 struct kobj_attribute *attr, 3957 char *buf) 3958 { 3959 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3960 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3961 3962 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf); 3963 } 3964 3965 static ssize_t acoustic_target_threshold_store(struct kobject *kobj, 3966 struct kobj_attribute *attr, 3967 const char *buf, 3968 size_t count) 3969 { 3970 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3971 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3972 3973 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3974 PP_OD_EDIT_ACOUSTIC_TARGET, 3975 buf, 3976 count); 3977 } 3978 3979 static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev) 3980 { 3981 umode_t umode = 0000; 3982 3983 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE) 3984 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3985 3986 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET) 3987 umode |= S_IWUSR; 3988 3989 return umode; 3990 } 3991 3992 /** 3993 * DOC: fan_target_temperature 3994 * 3995 * The amdgpu driver provides a sysfs API for checking and adjusting the 3996 * target tempeature in Celsius degree for fan control. 3997 * 3998 * Reading back the file shows you the current setting and the permitted 3999 * ranges if changable. 4000 * 4001 * Writing an integer to the file, change the setting accordingly. 4002 * 4003 * When you have finished the editing, write "c" (commit) to the file to commit 4004 * your changes. 4005 * 4006 * If you want to reset to the default value, write "r" (reset) to the file to 4007 * reset them 4008 * 4009 * This setting works under auto fan control mode only. It can co-exist with 4010 * other settings which can work also under auto mode. Paring with the 4011 * acoustic_target_rpm_threshold setting, they define the maximum speed in 4012 * RPM the fan can spin when ASIC temperature is not greater than target 4013 * temperature. Setting via this interface will switch the fan control to 4014 * auto mode implicitly. 4015 */ 4016 static ssize_t fan_target_temperature_show(struct kobject *kobj, 4017 struct kobj_attribute *attr, 4018 char *buf) 4019 { 4020 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4021 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4022 4023 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf); 4024 } 4025 4026 static ssize_t fan_target_temperature_store(struct kobject *kobj, 4027 struct kobj_attribute *attr, 4028 const char *buf, 4029 size_t count) 4030 { 4031 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4032 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4033 4034 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4035 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 4036 buf, 4037 count); 4038 } 4039 4040 static umode_t fan_target_temperature_visible(struct amdgpu_device *adev) 4041 { 4042 umode_t umode = 0000; 4043 4044 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE) 4045 umode |= S_IRUSR | S_IRGRP | S_IROTH; 4046 4047 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET) 4048 umode |= S_IWUSR; 4049 4050 return umode; 4051 } 4052 4053 /** 4054 * DOC: fan_minimum_pwm 4055 * 4056 * The amdgpu driver provides a sysfs API for checking and adjusting the 4057 * minimum fan speed in PWM. 4058 * 4059 * Reading back the file shows you the current setting and the permitted 4060 * ranges if changable. 4061 * 4062 * Writing an integer to the file, change the setting accordingly. 4063 * 4064 * When you have finished the editing, write "c" (commit) to the file to commit 4065 * your changes. 4066 * 4067 * If you want to reset to the default value, write "r" (reset) to the file to 4068 * reset them 4069 * 4070 * This setting works under auto fan control mode only. It can co-exist with 4071 * other settings which can work also under auto mode. It adjusts the PMFW's 4072 * behavior about the minimum fan speed in PWM the fan should spin. Setting 4073 * via this interface will switch the fan control to auto mode implicitly. 4074 */ 4075 static ssize_t fan_minimum_pwm_show(struct kobject *kobj, 4076 struct kobj_attribute *attr, 4077 char *buf) 4078 { 4079 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4080 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4081 4082 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf); 4083 } 4084 4085 static ssize_t fan_minimum_pwm_store(struct kobject *kobj, 4086 struct kobj_attribute *attr, 4087 const char *buf, 4088 size_t count) 4089 { 4090 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4091 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4092 4093 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4094 PP_OD_EDIT_FAN_MINIMUM_PWM, 4095 buf, 4096 count); 4097 } 4098 4099 static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev) 4100 { 4101 umode_t umode = 0000; 4102 4103 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE) 4104 umode |= S_IRUSR | S_IRGRP | S_IROTH; 4105 4106 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET) 4107 umode |= S_IWUSR; 4108 4109 return umode; 4110 } 4111 4112 /** 4113 * DOC: fan_zero_rpm_enable 4114 * 4115 * The amdgpu driver provides a sysfs API for checking and adjusting the 4116 * zero RPM feature. 4117 * 4118 * Reading back the file shows you the current setting and the permitted 4119 * ranges if changable. 4120 * 4121 * Writing an integer to the file, change the setting accordingly. 4122 * 4123 * When you have finished the editing, write "c" (commit) to the file to commit 4124 * your changes. 4125 * 4126 * If you want to reset to the default value, write "r" (reset) to the file to 4127 * reset them. 4128 */ 4129 static ssize_t fan_zero_rpm_enable_show(struct kobject *kobj, 4130 struct kobj_attribute *attr, 4131 char *buf) 4132 { 4133 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4134 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4135 4136 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_ZERO_RPM_ENABLE, buf); 4137 } 4138 4139 static ssize_t fan_zero_rpm_enable_store(struct kobject *kobj, 4140 struct kobj_attribute *attr, 4141 const char *buf, 4142 size_t count) 4143 { 4144 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4145 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4146 4147 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4148 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 4149 buf, 4150 count); 4151 } 4152 4153 static umode_t fan_zero_rpm_enable_visible(struct amdgpu_device *adev) 4154 { 4155 umode_t umode = 0000; 4156 4157 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE) 4158 umode |= S_IRUSR | S_IRGRP | S_IROTH; 4159 4160 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET) 4161 umode |= S_IWUSR; 4162 4163 return umode; 4164 } 4165 4166 /** 4167 * DOC: fan_zero_rpm_stop_temperature 4168 * 4169 * The amdgpu driver provides a sysfs API for checking and adjusting the 4170 * zero RPM stop temperature feature. 4171 * 4172 * Reading back the file shows you the current setting and the permitted 4173 * ranges if changable. 4174 * 4175 * Writing an integer to the file, change the setting accordingly. 4176 * 4177 * When you have finished the editing, write "c" (commit) to the file to commit 4178 * your changes. 4179 * 4180 * If you want to reset to the default value, write "r" (reset) to the file to 4181 * reset them. 4182 * 4183 * This setting works only if the Zero RPM setting is enabled. It adjusts the 4184 * temperature below which the fan can stop. 4185 */ 4186 static ssize_t fan_zero_rpm_stop_temp_show(struct kobject *kobj, 4187 struct kobj_attribute *attr, 4188 char *buf) 4189 { 4190 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4191 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4192 4193 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_ZERO_RPM_STOP_TEMP, buf); 4194 } 4195 4196 static ssize_t fan_zero_rpm_stop_temp_store(struct kobject *kobj, 4197 struct kobj_attribute *attr, 4198 const char *buf, 4199 size_t count) 4200 { 4201 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4202 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4203 4204 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4205 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 4206 buf, 4207 count); 4208 } 4209 4210 static umode_t fan_zero_rpm_stop_temp_visible(struct amdgpu_device *adev) 4211 { 4212 umode_t umode = 0000; 4213 4214 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE) 4215 umode |= S_IRUSR | S_IRGRP | S_IROTH; 4216 4217 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET) 4218 umode |= S_IWUSR; 4219 4220 return umode; 4221 } 4222 4223 static struct od_feature_set amdgpu_od_set = { 4224 .containers = { 4225 [0] = { 4226 .name = "fan_ctrl", 4227 .sub_feature = { 4228 [0] = { 4229 .name = "fan_curve", 4230 .ops = { 4231 .is_visible = fan_curve_visible, 4232 .show = fan_curve_show, 4233 .store = fan_curve_store, 4234 }, 4235 }, 4236 [1] = { 4237 .name = "acoustic_limit_rpm_threshold", 4238 .ops = { 4239 .is_visible = acoustic_limit_threshold_visible, 4240 .show = acoustic_limit_threshold_show, 4241 .store = acoustic_limit_threshold_store, 4242 }, 4243 }, 4244 [2] = { 4245 .name = "acoustic_target_rpm_threshold", 4246 .ops = { 4247 .is_visible = acoustic_target_threshold_visible, 4248 .show = acoustic_target_threshold_show, 4249 .store = acoustic_target_threshold_store, 4250 }, 4251 }, 4252 [3] = { 4253 .name = "fan_target_temperature", 4254 .ops = { 4255 .is_visible = fan_target_temperature_visible, 4256 .show = fan_target_temperature_show, 4257 .store = fan_target_temperature_store, 4258 }, 4259 }, 4260 [4] = { 4261 .name = "fan_minimum_pwm", 4262 .ops = { 4263 .is_visible = fan_minimum_pwm_visible, 4264 .show = fan_minimum_pwm_show, 4265 .store = fan_minimum_pwm_store, 4266 }, 4267 }, 4268 [5] = { 4269 .name = "fan_zero_rpm_enable", 4270 .ops = { 4271 .is_visible = fan_zero_rpm_enable_visible, 4272 .show = fan_zero_rpm_enable_show, 4273 .store = fan_zero_rpm_enable_store, 4274 }, 4275 }, 4276 [6] = { 4277 .name = "fan_zero_rpm_stop_temperature", 4278 .ops = { 4279 .is_visible = fan_zero_rpm_stop_temp_visible, 4280 .show = fan_zero_rpm_stop_temp_show, 4281 .store = fan_zero_rpm_stop_temp_store, 4282 }, 4283 }, 4284 }, 4285 }, 4286 }, 4287 }; 4288 4289 static void od_kobj_release(struct kobject *kobj) 4290 { 4291 struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj); 4292 4293 kfree(od_kobj); 4294 } 4295 4296 static const struct kobj_type od_ktype = { 4297 .release = od_kobj_release, 4298 .sysfs_ops = &kobj_sysfs_ops, 4299 }; 4300 4301 static void amdgpu_od_set_fini(struct amdgpu_device *adev) 4302 { 4303 struct od_kobj *container, *container_next; 4304 struct od_attribute *attribute, *attribute_next; 4305 4306 if (list_empty(&adev->pm.od_kobj_list)) 4307 return; 4308 4309 list_for_each_entry_safe(container, container_next, 4310 &adev->pm.od_kobj_list, entry) { 4311 list_del(&container->entry); 4312 4313 list_for_each_entry_safe(attribute, attribute_next, 4314 &container->attribute, entry) { 4315 list_del(&attribute->entry); 4316 sysfs_remove_file(&container->kobj, 4317 &attribute->attribute.attr); 4318 kfree(attribute); 4319 } 4320 4321 kobject_put(&container->kobj); 4322 } 4323 } 4324 4325 static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev, 4326 struct od_feature_ops *feature_ops) 4327 { 4328 umode_t mode; 4329 4330 if (!feature_ops->is_visible) 4331 return false; 4332 4333 /* 4334 * If the feature has no user read and write mode set, 4335 * we can assume the feature is actually not supported.(?) 4336 * And the revelant sysfs interface should not be exposed. 4337 */ 4338 mode = feature_ops->is_visible(adev); 4339 if (mode & (S_IRUSR | S_IWUSR)) 4340 return true; 4341 4342 return false; 4343 } 4344 4345 static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev, 4346 struct od_feature_container *container) 4347 { 4348 int i; 4349 4350 /* 4351 * If there is no valid entry within the container, the container 4352 * is recognized as a self contained container. And the valid entry 4353 * here means it has a valid naming and it is visible/supported by 4354 * the ASIC. 4355 */ 4356 for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) { 4357 if (container->sub_feature[i].name && 4358 amdgpu_is_od_feature_supported(adev, 4359 &container->sub_feature[i].ops)) 4360 return false; 4361 } 4362 4363 return true; 4364 } 4365 4366 static int amdgpu_od_set_init(struct amdgpu_device *adev) 4367 { 4368 struct od_kobj *top_set, *sub_set; 4369 struct od_attribute *attribute; 4370 struct od_feature_container *container; 4371 struct od_feature_item *feature; 4372 int i, j; 4373 int ret; 4374 4375 /* Setup the top `gpu_od` directory which holds all other OD interfaces */ 4376 top_set = kzalloc(sizeof(*top_set), GFP_KERNEL); 4377 if (!top_set) 4378 return -ENOMEM; 4379 list_add(&top_set->entry, &adev->pm.od_kobj_list); 4380 4381 ret = kobject_init_and_add(&top_set->kobj, 4382 &od_ktype, 4383 &adev->dev->kobj, 4384 "%s", 4385 "gpu_od"); 4386 if (ret) 4387 goto err_out; 4388 INIT_LIST_HEAD(&top_set->attribute); 4389 top_set->priv = adev; 4390 4391 for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) { 4392 container = &amdgpu_od_set.containers[i]; 4393 4394 if (!container->name) 4395 continue; 4396 4397 /* 4398 * If there is valid entries within the container, the container 4399 * will be presented as a sub directory and all its holding entries 4400 * will be presented as plain files under it. 4401 * While if there is no valid entry within the container, the container 4402 * itself will be presented as a plain file under top `gpu_od` directory. 4403 */ 4404 if (amdgpu_od_is_self_contained(adev, container)) { 4405 if (!amdgpu_is_od_feature_supported(adev, 4406 &container->ops)) 4407 continue; 4408 4409 /* 4410 * The container is presented as a plain file under top `gpu_od` 4411 * directory. 4412 */ 4413 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL); 4414 if (!attribute) { 4415 ret = -ENOMEM; 4416 goto err_out; 4417 } 4418 list_add(&attribute->entry, &top_set->attribute); 4419 4420 attribute->attribute.attr.mode = 4421 container->ops.is_visible(adev); 4422 attribute->attribute.attr.name = container->name; 4423 attribute->attribute.show = 4424 container->ops.show; 4425 attribute->attribute.store = 4426 container->ops.store; 4427 ret = sysfs_create_file(&top_set->kobj, 4428 &attribute->attribute.attr); 4429 if (ret) 4430 goto err_out; 4431 } else { 4432 /* The container is presented as a sub directory. */ 4433 sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL); 4434 if (!sub_set) { 4435 ret = -ENOMEM; 4436 goto err_out; 4437 } 4438 list_add(&sub_set->entry, &adev->pm.od_kobj_list); 4439 4440 ret = kobject_init_and_add(&sub_set->kobj, 4441 &od_ktype, 4442 &top_set->kobj, 4443 "%s", 4444 container->name); 4445 if (ret) 4446 goto err_out; 4447 INIT_LIST_HEAD(&sub_set->attribute); 4448 sub_set->priv = adev; 4449 4450 for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) { 4451 feature = &container->sub_feature[j]; 4452 if (!feature->name) 4453 continue; 4454 4455 if (!amdgpu_is_od_feature_supported(adev, 4456 &feature->ops)) 4457 continue; 4458 4459 /* 4460 * With the container presented as a sub directory, the entry within 4461 * it is presented as a plain file under the sub directory. 4462 */ 4463 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL); 4464 if (!attribute) { 4465 ret = -ENOMEM; 4466 goto err_out; 4467 } 4468 list_add(&attribute->entry, &sub_set->attribute); 4469 4470 attribute->attribute.attr.mode = 4471 feature->ops.is_visible(adev); 4472 attribute->attribute.attr.name = feature->name; 4473 attribute->attribute.show = 4474 feature->ops.show; 4475 attribute->attribute.store = 4476 feature->ops.store; 4477 ret = sysfs_create_file(&sub_set->kobj, 4478 &attribute->attribute.attr); 4479 if (ret) 4480 goto err_out; 4481 } 4482 } 4483 } 4484 4485 /* 4486 * If gpu_od is the only member in the list, that means gpu_od is an 4487 * empty directory, so remove it. 4488 */ 4489 if (list_is_singular(&adev->pm.od_kobj_list)) 4490 goto err_out; 4491 4492 return 0; 4493 4494 err_out: 4495 amdgpu_od_set_fini(adev); 4496 4497 return ret; 4498 } 4499 4500 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 4501 { 4502 enum amdgpu_sriov_vf_mode mode; 4503 uint32_t mask = 0; 4504 int ret; 4505 4506 if (adev->pm.sysfs_initialized) 4507 return 0; 4508 4509 INIT_LIST_HEAD(&adev->pm.pm_attr_list); 4510 4511 if (adev->pm.dpm_enabled == 0) 4512 return 0; 4513 4514 mode = amdgpu_virt_get_sriov_vf_mode(adev); 4515 4516 /* under multi-vf mode, the hwmon attributes are all not supported */ 4517 if (mode != SRIOV_VF_MODE_MULTI_VF) { 4518 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 4519 DRIVER_NAME, adev, 4520 hwmon_groups); 4521 if (IS_ERR(adev->pm.int_hwmon_dev)) { 4522 ret = PTR_ERR(adev->pm.int_hwmon_dev); 4523 dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret); 4524 return ret; 4525 } 4526 } 4527 4528 switch (mode) { 4529 case SRIOV_VF_MODE_ONE_VF: 4530 mask = ATTR_FLAG_ONEVF; 4531 break; 4532 case SRIOV_VF_MODE_MULTI_VF: 4533 mask = 0; 4534 break; 4535 case SRIOV_VF_MODE_BARE_METAL: 4536 default: 4537 mask = ATTR_FLAG_MASK_ALL; 4538 break; 4539 } 4540 4541 ret = amdgpu_device_attr_create_groups(adev, 4542 amdgpu_device_attrs, 4543 ARRAY_SIZE(amdgpu_device_attrs), 4544 mask, 4545 &adev->pm.pm_attr_list); 4546 if (ret) 4547 goto err_out0; 4548 4549 if (amdgpu_dpm_is_overdrive_supported(adev)) { 4550 ret = amdgpu_od_set_init(adev); 4551 if (ret) 4552 goto err_out1; 4553 } else if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) { 4554 dev_info(adev->dev, "overdrive feature is not supported\n"); 4555 } 4556 4557 if (amdgpu_dpm_get_pm_policy_info(adev, PP_PM_POLICY_NONE, NULL) != 4558 -EOPNOTSUPP) { 4559 ret = devm_device_add_group(adev->dev, 4560 &amdgpu_pm_policy_attr_group); 4561 if (ret) 4562 goto err_out0; 4563 } 4564 4565 adev->pm.sysfs_initialized = true; 4566 4567 return 0; 4568 4569 err_out1: 4570 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 4571 err_out0: 4572 if (adev->pm.int_hwmon_dev) 4573 hwmon_device_unregister(adev->pm.int_hwmon_dev); 4574 4575 return ret; 4576 } 4577 4578 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 4579 { 4580 amdgpu_od_set_fini(adev); 4581 4582 if (adev->pm.int_hwmon_dev) 4583 hwmon_device_unregister(adev->pm.int_hwmon_dev); 4584 4585 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 4586 } 4587 4588 /* 4589 * Debugfs info 4590 */ 4591 #if defined(CONFIG_DEBUG_FS) 4592 4593 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 4594 struct amdgpu_device *adev) 4595 { 4596 uint16_t *p_val; 4597 uint32_t size; 4598 int i; 4599 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); 4600 4601 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { 4602 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), 4603 GFP_KERNEL); 4604 4605 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 4606 (void *)p_val, &size)) { 4607 for (i = 0; i < num_cpu_cores; i++) 4608 seq_printf(m, "\t%u MHz (CPU%d)\n", 4609 *(p_val + i), i); 4610 } 4611 4612 kfree(p_val); 4613 } 4614 } 4615 4616 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 4617 { 4618 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0); 4619 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 4620 uint32_t value; 4621 uint64_t value64 = 0; 4622 uint32_t query = 0; 4623 int size; 4624 4625 /* GPU Clocks */ 4626 size = sizeof(value); 4627 seq_printf(m, "GFX Clocks and Power:\n"); 4628 4629 amdgpu_debugfs_prints_cpu_info(m, adev); 4630 4631 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 4632 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 4633 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 4634 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 4635 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 4636 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 4637 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 4638 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 4639 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 4640 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 4641 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 4642 seq_printf(m, "\t%u mV (VDDNB)\n", value); 4643 size = sizeof(uint32_t); 4644 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) { 4645 if (adev->flags & AMD_IS_APU) 4646 seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n", query >> 8, query & 0xff); 4647 else 4648 seq_printf(m, "\t%u.%02u W (average SoC)\n", query >> 8, query & 0xff); 4649 } 4650 size = sizeof(uint32_t); 4651 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) { 4652 if (adev->flags & AMD_IS_APU) 4653 seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n", query >> 8, query & 0xff); 4654 else 4655 seq_printf(m, "\t%u.%02u W (current SoC)\n", query >> 8, query & 0xff); 4656 } 4657 size = sizeof(value); 4658 seq_printf(m, "\n"); 4659 4660 /* GPU Temp */ 4661 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 4662 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 4663 4664 /* GPU Load */ 4665 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 4666 seq_printf(m, "GPU Load: %u %%\n", value); 4667 /* MEM Load */ 4668 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 4669 seq_printf(m, "MEM Load: %u %%\n", value); 4670 /* VCN Load */ 4671 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_LOAD, (void *)&value, &size)) 4672 seq_printf(m, "VCN Load: %u %%\n", value); 4673 4674 seq_printf(m, "\n"); 4675 4676 /* SMC feature mask */ 4677 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 4678 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 4679 4680 /* ASICs greater than CHIP_VEGA20 supports these sensors */ 4681 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { 4682 /* VCN clocks */ 4683 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 4684 if (!value) { 4685 seq_printf(m, "VCN: Powered down\n"); 4686 } else { 4687 seq_printf(m, "VCN: Powered up\n"); 4688 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 4689 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 4690 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 4691 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 4692 } 4693 } 4694 seq_printf(m, "\n"); 4695 } else { 4696 /* UVD clocks */ 4697 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 4698 if (!value) { 4699 seq_printf(m, "UVD: Powered down\n"); 4700 } else { 4701 seq_printf(m, "UVD: Powered up\n"); 4702 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 4703 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 4704 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 4705 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 4706 } 4707 } 4708 seq_printf(m, "\n"); 4709 4710 /* VCE clocks */ 4711 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 4712 if (!value) { 4713 seq_printf(m, "VCE: Powered down\n"); 4714 } else { 4715 seq_printf(m, "VCE: Powered up\n"); 4716 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 4717 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 4718 } 4719 } 4720 } 4721 4722 return 0; 4723 } 4724 4725 static const struct cg_flag_name clocks[] = { 4726 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 4727 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 4728 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 4729 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 4730 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 4731 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 4732 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 4733 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 4734 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 4735 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 4736 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 4737 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 4738 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 4739 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 4740 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 4741 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 4742 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 4743 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 4744 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 4745 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 4746 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 4747 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 4748 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 4749 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 4750 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 4751 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 4752 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 4753 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 4754 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 4755 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 4756 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, 4757 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, 4758 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 4759 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 4760 {0, NULL}, 4761 }; 4762 4763 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 4764 { 4765 int i; 4766 4767 for (i = 0; clocks[i].flag; i++) 4768 seq_printf(m, "\t%s: %s\n", clocks[i].name, 4769 (flags & clocks[i].flag) ? "On" : "Off"); 4770 } 4771 4772 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 4773 { 4774 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 4775 struct drm_device *dev = adev_to_drm(adev); 4776 u64 flags = 0; 4777 int r; 4778 4779 if (amdgpu_in_reset(adev)) 4780 return -EPERM; 4781 if (adev->in_suspend && !adev->in_runpm) 4782 return -EPERM; 4783 4784 r = pm_runtime_resume_and_get(dev->dev); 4785 if (r < 0) 4786 return r; 4787 4788 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { 4789 r = amdgpu_debugfs_pm_info_pp(m, adev); 4790 if (r) 4791 goto out; 4792 } 4793 4794 amdgpu_device_ip_get_clockgating_state(adev, &flags); 4795 4796 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 4797 amdgpu_parse_cg_state(m, flags); 4798 seq_printf(m, "\n"); 4799 4800 out: 4801 pm_runtime_put_autosuspend(dev->dev); 4802 4803 return r; 4804 } 4805 4806 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 4807 4808 /* 4809 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 4810 * 4811 * Reads debug memory region allocated to PMFW 4812 */ 4813 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 4814 size_t size, loff_t *pos) 4815 { 4816 struct amdgpu_device *adev = file_inode(f)->i_private; 4817 size_t smu_prv_buf_size; 4818 void *smu_prv_buf; 4819 int ret = 0; 4820 4821 if (amdgpu_in_reset(adev)) 4822 return -EPERM; 4823 if (adev->in_suspend && !adev->in_runpm) 4824 return -EPERM; 4825 4826 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); 4827 if (ret) 4828 return ret; 4829 4830 if (!smu_prv_buf || !smu_prv_buf_size) 4831 return -EINVAL; 4832 4833 return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 4834 smu_prv_buf_size); 4835 } 4836 4837 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 4838 .owner = THIS_MODULE, 4839 .open = simple_open, 4840 .read = amdgpu_pm_prv_buffer_read, 4841 .llseek = default_llseek, 4842 }; 4843 4844 #endif 4845 4846 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 4847 { 4848 #if defined(CONFIG_DEBUG_FS) 4849 struct drm_minor *minor = adev_to_drm(adev)->primary; 4850 struct dentry *root = minor->debugfs_root; 4851 4852 if (!adev->pm.dpm_enabled) 4853 return; 4854 4855 debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 4856 &amdgpu_debugfs_pm_info_fops); 4857 4858 if (adev->pm.smu_prv_buffer_size > 0) 4859 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 4860 adev, 4861 &amdgpu_debugfs_pm_prv_buffer_fops, 4862 adev->pm.smu_prv_buffer_size); 4863 4864 amdgpu_dpm_stb_debug_fs_init(adev); 4865 #endif 4866 } 4867