1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/pci.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 #include <linux/pm_runtime.h> 36 #include <asm/processor.h> 37 38 #define MAX_NUM_OF_FEATURES_PER_SUBSET 8 39 #define MAX_NUM_OF_SUBSETS 8 40 41 struct od_attribute { 42 struct kobj_attribute attribute; 43 struct list_head entry; 44 }; 45 46 struct od_kobj { 47 struct kobject kobj; 48 struct list_head entry; 49 struct list_head attribute; 50 void *priv; 51 }; 52 53 struct od_feature_ops { 54 umode_t (*is_visible)(struct amdgpu_device *adev); 55 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr, 56 char *buf); 57 ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr, 58 const char *buf, size_t count); 59 }; 60 61 struct od_feature_item { 62 const char *name; 63 struct od_feature_ops ops; 64 }; 65 66 struct od_feature_container { 67 char *name; 68 struct od_feature_ops ops; 69 struct od_feature_item sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET]; 70 }; 71 72 struct od_feature_set { 73 struct od_feature_container containers[MAX_NUM_OF_SUBSETS]; 74 }; 75 76 static const struct hwmon_temp_label { 77 enum PP_HWMON_TEMP channel; 78 const char *label; 79 } temp_label[] = { 80 {PP_TEMP_EDGE, "edge"}, 81 {PP_TEMP_JUNCTION, "junction"}, 82 {PP_TEMP_MEM, "mem"}, 83 }; 84 85 const char * const amdgpu_pp_profile_name[] = { 86 "BOOTUP_DEFAULT", 87 "3D_FULL_SCREEN", 88 "POWER_SAVING", 89 "VIDEO", 90 "VR", 91 "COMPUTE", 92 "CUSTOM", 93 "WINDOW_3D", 94 "CAPPED", 95 "UNCAPPED", 96 }; 97 98 /** 99 * DOC: power_dpm_state 100 * 101 * The power_dpm_state file is a legacy interface and is only provided for 102 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 103 * certain power related parameters. The file power_dpm_state is used for this. 104 * It accepts the following arguments: 105 * 106 * - battery 107 * 108 * - balanced 109 * 110 * - performance 111 * 112 * battery 113 * 114 * On older GPUs, the vbios provided a special power state for battery 115 * operation. Selecting battery switched to this state. This is no 116 * longer provided on newer GPUs so the option does nothing in that case. 117 * 118 * balanced 119 * 120 * On older GPUs, the vbios provided a special power state for balanced 121 * operation. Selecting balanced switched to this state. This is no 122 * longer provided on newer GPUs so the option does nothing in that case. 123 * 124 * performance 125 * 126 * On older GPUs, the vbios provided a special power state for performance 127 * operation. Selecting performance switched to this state. This is no 128 * longer provided on newer GPUs so the option does nothing in that case. 129 * 130 */ 131 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 133 struct device_attribute *attr, 134 char *buf) 135 { 136 struct drm_device *ddev = dev_get_drvdata(dev); 137 struct amdgpu_device *adev = drm_to_adev(ddev); 138 enum amd_pm_state_type pm; 139 int ret; 140 141 if (amdgpu_in_reset(adev)) 142 return -EPERM; 143 if (adev->in_suspend && !adev->in_runpm) 144 return -EPERM; 145 146 ret = pm_runtime_get_sync(ddev->dev); 147 if (ret < 0) { 148 pm_runtime_put_autosuspend(ddev->dev); 149 return ret; 150 } 151 152 amdgpu_dpm_get_current_power_state(adev, &pm); 153 154 pm_runtime_mark_last_busy(ddev->dev); 155 pm_runtime_put_autosuspend(ddev->dev); 156 157 return sysfs_emit(buf, "%s\n", 158 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 159 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 160 } 161 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 163 struct device_attribute *attr, 164 const char *buf, 165 size_t count) 166 { 167 struct drm_device *ddev = dev_get_drvdata(dev); 168 struct amdgpu_device *adev = drm_to_adev(ddev); 169 enum amd_pm_state_type state; 170 int ret; 171 172 if (amdgpu_in_reset(adev)) 173 return -EPERM; 174 if (adev->in_suspend && !adev->in_runpm) 175 return -EPERM; 176 177 if (strncmp("battery", buf, strlen("battery")) == 0) 178 state = POWER_STATE_TYPE_BATTERY; 179 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 180 state = POWER_STATE_TYPE_BALANCED; 181 else if (strncmp("performance", buf, strlen("performance")) == 0) 182 state = POWER_STATE_TYPE_PERFORMANCE; 183 else 184 return -EINVAL; 185 186 ret = pm_runtime_get_sync(ddev->dev); 187 if (ret < 0) { 188 pm_runtime_put_autosuspend(ddev->dev); 189 return ret; 190 } 191 192 amdgpu_dpm_set_power_state(adev, state); 193 194 pm_runtime_mark_last_busy(ddev->dev); 195 pm_runtime_put_autosuspend(ddev->dev); 196 197 return count; 198 } 199 200 201 /** 202 * DOC: power_dpm_force_performance_level 203 * 204 * The amdgpu driver provides a sysfs API for adjusting certain power 205 * related parameters. The file power_dpm_force_performance_level is 206 * used for this. It accepts the following arguments: 207 * 208 * - auto 209 * 210 * - low 211 * 212 * - high 213 * 214 * - manual 215 * 216 * - profile_standard 217 * 218 * - profile_min_sclk 219 * 220 * - profile_min_mclk 221 * 222 * - profile_peak 223 * 224 * auto 225 * 226 * When auto is selected, the driver will attempt to dynamically select 227 * the optimal power profile for current conditions in the driver. 228 * 229 * low 230 * 231 * When low is selected, the clocks are forced to the lowest power state. 232 * 233 * high 234 * 235 * When high is selected, the clocks are forced to the highest power state. 236 * 237 * manual 238 * 239 * When manual is selected, the user can manually adjust which power states 240 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 241 * and pp_dpm_pcie files and adjust the power state transition heuristics 242 * via the pp_power_profile_mode sysfs file. 243 * 244 * profile_standard 245 * profile_min_sclk 246 * profile_min_mclk 247 * profile_peak 248 * 249 * When the profiling modes are selected, clock and power gating are 250 * disabled and the clocks are set for different profiling cases. This 251 * mode is recommended for profiling specific work loads where you do 252 * not want clock or power gating for clock fluctuation to interfere 253 * with your results. profile_standard sets the clocks to a fixed clock 254 * level which varies from asic to asic. profile_min_sclk forces the sclk 255 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 256 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 257 * 258 */ 259 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 261 struct device_attribute *attr, 262 char *buf) 263 { 264 struct drm_device *ddev = dev_get_drvdata(dev); 265 struct amdgpu_device *adev = drm_to_adev(ddev); 266 enum amd_dpm_forced_level level = 0xff; 267 int ret; 268 269 if (amdgpu_in_reset(adev)) 270 return -EPERM; 271 if (adev->in_suspend && !adev->in_runpm) 272 return -EPERM; 273 274 ret = pm_runtime_get_sync(ddev->dev); 275 if (ret < 0) { 276 pm_runtime_put_autosuspend(ddev->dev); 277 return ret; 278 } 279 280 level = amdgpu_dpm_get_performance_level(adev); 281 282 pm_runtime_mark_last_busy(ddev->dev); 283 pm_runtime_put_autosuspend(ddev->dev); 284 285 return sysfs_emit(buf, "%s\n", 286 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 287 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 288 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 289 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 290 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 291 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 292 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 293 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 294 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 295 "unknown"); 296 } 297 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 299 struct device_attribute *attr, 300 const char *buf, 301 size_t count) 302 { 303 struct drm_device *ddev = dev_get_drvdata(dev); 304 struct amdgpu_device *adev = drm_to_adev(ddev); 305 enum amd_dpm_forced_level level; 306 int ret = 0; 307 308 if (amdgpu_in_reset(adev)) 309 return -EPERM; 310 if (adev->in_suspend && !adev->in_runpm) 311 return -EPERM; 312 313 if (strncmp("low", buf, strlen("low")) == 0) { 314 level = AMD_DPM_FORCED_LEVEL_LOW; 315 } else if (strncmp("high", buf, strlen("high")) == 0) { 316 level = AMD_DPM_FORCED_LEVEL_HIGH; 317 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 318 level = AMD_DPM_FORCED_LEVEL_AUTO; 319 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 320 level = AMD_DPM_FORCED_LEVEL_MANUAL; 321 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 322 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 323 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 324 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 325 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 326 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 327 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 328 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 329 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 330 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 331 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 332 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 333 } else { 334 return -EINVAL; 335 } 336 337 ret = pm_runtime_get_sync(ddev->dev); 338 if (ret < 0) { 339 pm_runtime_put_autosuspend(ddev->dev); 340 return ret; 341 } 342 343 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 344 if (amdgpu_dpm_force_performance_level(adev, level)) { 345 pm_runtime_mark_last_busy(ddev->dev); 346 pm_runtime_put_autosuspend(ddev->dev); 347 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 348 return -EINVAL; 349 } 350 /* override whatever a user ctx may have set */ 351 adev->pm.stable_pstate_ctx = NULL; 352 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 353 354 pm_runtime_mark_last_busy(ddev->dev); 355 pm_runtime_put_autosuspend(ddev->dev); 356 357 return count; 358 } 359 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 361 struct device_attribute *attr, 362 char *buf) 363 { 364 struct drm_device *ddev = dev_get_drvdata(dev); 365 struct amdgpu_device *adev = drm_to_adev(ddev); 366 struct pp_states_info data; 367 uint32_t i; 368 int buf_len, ret; 369 370 if (amdgpu_in_reset(adev)) 371 return -EPERM; 372 if (adev->in_suspend && !adev->in_runpm) 373 return -EPERM; 374 375 ret = pm_runtime_get_sync(ddev->dev); 376 if (ret < 0) { 377 pm_runtime_put_autosuspend(ddev->dev); 378 return ret; 379 } 380 381 if (amdgpu_dpm_get_pp_num_states(adev, &data)) 382 memset(&data, 0, sizeof(data)); 383 384 pm_runtime_mark_last_busy(ddev->dev); 385 pm_runtime_put_autosuspend(ddev->dev); 386 387 buf_len = sysfs_emit(buf, "states: %d\n", data.nums); 388 for (i = 0; i < data.nums; i++) 389 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, 390 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 391 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 392 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 393 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 394 395 return buf_len; 396 } 397 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 399 struct device_attribute *attr, 400 char *buf) 401 { 402 struct drm_device *ddev = dev_get_drvdata(dev); 403 struct amdgpu_device *adev = drm_to_adev(ddev); 404 struct pp_states_info data = {0}; 405 enum amd_pm_state_type pm = 0; 406 int i = 0, ret = 0; 407 408 if (amdgpu_in_reset(adev)) 409 return -EPERM; 410 if (adev->in_suspend && !adev->in_runpm) 411 return -EPERM; 412 413 ret = pm_runtime_get_sync(ddev->dev); 414 if (ret < 0) { 415 pm_runtime_put_autosuspend(ddev->dev); 416 return ret; 417 } 418 419 amdgpu_dpm_get_current_power_state(adev, &pm); 420 421 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 422 423 pm_runtime_mark_last_busy(ddev->dev); 424 pm_runtime_put_autosuspend(ddev->dev); 425 426 if (ret) 427 return ret; 428 429 for (i = 0; i < data.nums; i++) { 430 if (pm == data.states[i]) 431 break; 432 } 433 434 if (i == data.nums) 435 i = -EINVAL; 436 437 return sysfs_emit(buf, "%d\n", i); 438 } 439 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 441 struct device_attribute *attr, 442 char *buf) 443 { 444 struct drm_device *ddev = dev_get_drvdata(dev); 445 struct amdgpu_device *adev = drm_to_adev(ddev); 446 447 if (amdgpu_in_reset(adev)) 448 return -EPERM; 449 if (adev->in_suspend && !adev->in_runpm) 450 return -EPERM; 451 452 if (adev->pm.pp_force_state_enabled) 453 return amdgpu_get_pp_cur_state(dev, attr, buf); 454 else 455 return sysfs_emit(buf, "\n"); 456 } 457 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 459 struct device_attribute *attr, 460 const char *buf, 461 size_t count) 462 { 463 struct drm_device *ddev = dev_get_drvdata(dev); 464 struct amdgpu_device *adev = drm_to_adev(ddev); 465 enum amd_pm_state_type state = 0; 466 struct pp_states_info data; 467 unsigned long idx; 468 int ret; 469 470 if (amdgpu_in_reset(adev)) 471 return -EPERM; 472 if (adev->in_suspend && !adev->in_runpm) 473 return -EPERM; 474 475 adev->pm.pp_force_state_enabled = false; 476 477 if (strlen(buf) == 1) 478 return count; 479 480 ret = kstrtoul(buf, 0, &idx); 481 if (ret || idx >= ARRAY_SIZE(data.states)) 482 return -EINVAL; 483 484 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 485 486 ret = pm_runtime_get_sync(ddev->dev); 487 if (ret < 0) { 488 pm_runtime_put_autosuspend(ddev->dev); 489 return ret; 490 } 491 492 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 493 if (ret) 494 goto err_out; 495 496 state = data.states[idx]; 497 498 /* only set user selected power states */ 499 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 500 state != POWER_STATE_TYPE_DEFAULT) { 501 ret = amdgpu_dpm_dispatch_task(adev, 502 AMD_PP_TASK_ENABLE_USER_STATE, &state); 503 if (ret) 504 goto err_out; 505 506 adev->pm.pp_force_state_enabled = true; 507 } 508 509 pm_runtime_mark_last_busy(ddev->dev); 510 pm_runtime_put_autosuspend(ddev->dev); 511 512 return count; 513 514 err_out: 515 pm_runtime_mark_last_busy(ddev->dev); 516 pm_runtime_put_autosuspend(ddev->dev); 517 return ret; 518 } 519 520 /** 521 * DOC: pp_table 522 * 523 * The amdgpu driver provides a sysfs API for uploading new powerplay 524 * tables. The file pp_table is used for this. Reading the file 525 * will dump the current power play table. Writing to the file 526 * will attempt to upload a new powerplay table and re-initialize 527 * powerplay using that new table. 528 * 529 */ 530 531 static ssize_t amdgpu_get_pp_table(struct device *dev, 532 struct device_attribute *attr, 533 char *buf) 534 { 535 struct drm_device *ddev = dev_get_drvdata(dev); 536 struct amdgpu_device *adev = drm_to_adev(ddev); 537 char *table = NULL; 538 int size, ret; 539 540 if (amdgpu_in_reset(adev)) 541 return -EPERM; 542 if (adev->in_suspend && !adev->in_runpm) 543 return -EPERM; 544 545 ret = pm_runtime_get_sync(ddev->dev); 546 if (ret < 0) { 547 pm_runtime_put_autosuspend(ddev->dev); 548 return ret; 549 } 550 551 size = amdgpu_dpm_get_pp_table(adev, &table); 552 553 pm_runtime_mark_last_busy(ddev->dev); 554 pm_runtime_put_autosuspend(ddev->dev); 555 556 if (size <= 0) 557 return size; 558 559 if (size >= PAGE_SIZE) 560 size = PAGE_SIZE - 1; 561 562 memcpy(buf, table, size); 563 564 return size; 565 } 566 567 static ssize_t amdgpu_set_pp_table(struct device *dev, 568 struct device_attribute *attr, 569 const char *buf, 570 size_t count) 571 { 572 struct drm_device *ddev = dev_get_drvdata(dev); 573 struct amdgpu_device *adev = drm_to_adev(ddev); 574 int ret = 0; 575 576 if (amdgpu_in_reset(adev)) 577 return -EPERM; 578 if (adev->in_suspend && !adev->in_runpm) 579 return -EPERM; 580 581 ret = pm_runtime_get_sync(ddev->dev); 582 if (ret < 0) { 583 pm_runtime_put_autosuspend(ddev->dev); 584 return ret; 585 } 586 587 ret = amdgpu_dpm_set_pp_table(adev, buf, count); 588 589 pm_runtime_mark_last_busy(ddev->dev); 590 pm_runtime_put_autosuspend(ddev->dev); 591 592 if (ret) 593 return ret; 594 595 return count; 596 } 597 598 /** 599 * DOC: pp_od_clk_voltage 600 * 601 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 602 * in each power level within a power state. The pp_od_clk_voltage is used for 603 * this. 604 * 605 * Note that the actual memory controller clock rate are exposed, not 606 * the effective memory clock of the DRAMs. To translate it, use the 607 * following formula: 608 * 609 * Clock conversion (Mhz): 610 * 611 * HBM: effective_memory_clock = memory_controller_clock * 1 612 * 613 * G5: effective_memory_clock = memory_controller_clock * 1 614 * 615 * G6: effective_memory_clock = memory_controller_clock * 2 616 * 617 * DRAM data rate (MT/s): 618 * 619 * HBM: effective_memory_clock * 2 = data_rate 620 * 621 * G5: effective_memory_clock * 4 = data_rate 622 * 623 * G6: effective_memory_clock * 8 = data_rate 624 * 625 * Bandwidth (MB/s): 626 * 627 * data_rate * vram_bit_width / 8 = memory_bandwidth 628 * 629 * Some examples: 630 * 631 * G5 on RX460: 632 * 633 * memory_controller_clock = 1750 Mhz 634 * 635 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 636 * 637 * data rate = 1750 * 4 = 7000 MT/s 638 * 639 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 640 * 641 * G6 on RX5700: 642 * 643 * memory_controller_clock = 875 Mhz 644 * 645 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 646 * 647 * data rate = 1750 * 8 = 14000 MT/s 648 * 649 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 650 * 651 * < For Vega10 and previous ASICs > 652 * 653 * Reading the file will display: 654 * 655 * - a list of engine clock levels and voltages labeled OD_SCLK 656 * 657 * - a list of memory clock levels and voltages labeled OD_MCLK 658 * 659 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 660 * 661 * To manually adjust these settings, first select manual using 662 * power_dpm_force_performance_level. Enter a new value for each 663 * level by writing a string that contains "s/m level clock voltage" to 664 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 665 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 666 * 810 mV. When you have edited all of the states as needed, write 667 * "c" (commit) to the file to commit your changes. If you want to reset to the 668 * default power levels, write "r" (reset) to the file to reset them. 669 * 670 * 671 * < For Vega20 and newer ASICs > 672 * 673 * Reading the file will display: 674 * 675 * - minimum and maximum engine clock labeled OD_SCLK 676 * 677 * - minimum(not available for Vega20 and Navi1x) and maximum memory 678 * clock labeled OD_MCLK 679 * 680 * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 681 * They can be used to calibrate the sclk voltage curve. This is 682 * available for Vega20 and NV1X. 683 * 684 * - voltage offset(in mV) applied on target voltage calculation. 685 * This is available for Sienna Cichlid, Navy Flounder, Dimgrey 686 * Cavefish and some later SMU13 ASICs. For these ASICs, the target 687 * voltage calculation can be illustrated by "voltage = voltage 688 * calculated from v/f curve + overdrive vddgfx offset" 689 * 690 * - a list of valid ranges for sclk, mclk, voltage curve points 691 * or voltage offset labeled OD_RANGE 692 * 693 * < For APUs > 694 * 695 * Reading the file will display: 696 * 697 * - minimum and maximum engine clock labeled OD_SCLK 698 * 699 * - a list of valid ranges for sclk labeled OD_RANGE 700 * 701 * < For VanGogh > 702 * 703 * Reading the file will display: 704 * 705 * - minimum and maximum engine clock labeled OD_SCLK 706 * - minimum and maximum core clocks labeled OD_CCLK 707 * 708 * - a list of valid ranges for sclk and cclk labeled OD_RANGE 709 * 710 * To manually adjust these settings: 711 * 712 * - First select manual using power_dpm_force_performance_level 713 * 714 * - For clock frequency setting, enter a new value by writing a 715 * string that contains "s/m index clock" to the file. The index 716 * should be 0 if to set minimum clock. And 1 if to set maximum 717 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 718 * "m 1 800" will update maximum mclk to be 800Mhz. For core 719 * clocks on VanGogh, the string contains "p core index clock". 720 * E.g., "p 2 0 800" would set the minimum core clock on core 721 * 2 to 800Mhz. 722 * 723 * For sclk voltage curve supported by Vega20 and NV1X, enter the new 724 * values by writing a string that contains "vc point clock voltage" 725 * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300 726 * 600" will update point1 with clock set as 300Mhz and voltage as 600mV. 727 * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and 728 * voltage 1000mV. 729 * 730 * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey 731 * Cavefish and some later SMU13 ASICs, enter the new value by writing a 732 * string that contains "vo offset". E.g., "vo -10" will update the extra 733 * voltage offset applied to the whole v/f curve line as -10mv. 734 * 735 * - When you have edited all of the states as needed, write "c" (commit) 736 * to the file to commit your changes 737 * 738 * - If you want to reset to the default power levels, write "r" (reset) 739 * to the file to reset them 740 * 741 */ 742 743 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 744 struct device_attribute *attr, 745 const char *buf, 746 size_t count) 747 { 748 struct drm_device *ddev = dev_get_drvdata(dev); 749 struct amdgpu_device *adev = drm_to_adev(ddev); 750 int ret; 751 uint32_t parameter_size = 0; 752 long parameter[64]; 753 char buf_cpy[128]; 754 char *tmp_str; 755 char *sub_str; 756 const char delimiter[3] = {' ', '\n', '\0'}; 757 uint32_t type; 758 759 if (amdgpu_in_reset(adev)) 760 return -EPERM; 761 if (adev->in_suspend && !adev->in_runpm) 762 return -EPERM; 763 764 if (count > 127 || count == 0) 765 return -EINVAL; 766 767 if (*buf == 's') 768 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 769 else if (*buf == 'p') 770 type = PP_OD_EDIT_CCLK_VDDC_TABLE; 771 else if (*buf == 'm') 772 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 773 else if (*buf == 'r') 774 type = PP_OD_RESTORE_DEFAULT_TABLE; 775 else if (*buf == 'c') 776 type = PP_OD_COMMIT_DPM_TABLE; 777 else if (!strncmp(buf, "vc", 2)) 778 type = PP_OD_EDIT_VDDC_CURVE; 779 else if (!strncmp(buf, "vo", 2)) 780 type = PP_OD_EDIT_VDDGFX_OFFSET; 781 else 782 return -EINVAL; 783 784 memcpy(buf_cpy, buf, count); 785 buf_cpy[count] = 0; 786 787 tmp_str = buf_cpy; 788 789 if ((type == PP_OD_EDIT_VDDC_CURVE) || 790 (type == PP_OD_EDIT_VDDGFX_OFFSET)) 791 tmp_str++; 792 while (isspace(*++tmp_str)); 793 794 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 795 if (strlen(sub_str) == 0) 796 continue; 797 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 798 if (ret) 799 return -EINVAL; 800 parameter_size++; 801 802 if (!tmp_str) 803 break; 804 805 while (isspace(*tmp_str)) 806 tmp_str++; 807 } 808 809 ret = pm_runtime_get_sync(ddev->dev); 810 if (ret < 0) { 811 pm_runtime_put_autosuspend(ddev->dev); 812 return ret; 813 } 814 815 if (amdgpu_dpm_set_fine_grain_clk_vol(adev, 816 type, 817 parameter, 818 parameter_size)) 819 goto err_out; 820 821 if (amdgpu_dpm_odn_edit_dpm_table(adev, type, 822 parameter, parameter_size)) 823 goto err_out; 824 825 if (type == PP_OD_COMMIT_DPM_TABLE) { 826 if (amdgpu_dpm_dispatch_task(adev, 827 AMD_PP_TASK_READJUST_POWER_STATE, 828 NULL)) 829 goto err_out; 830 } 831 832 pm_runtime_mark_last_busy(ddev->dev); 833 pm_runtime_put_autosuspend(ddev->dev); 834 835 return count; 836 837 err_out: 838 pm_runtime_mark_last_busy(ddev->dev); 839 pm_runtime_put_autosuspend(ddev->dev); 840 return -EINVAL; 841 } 842 843 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 844 struct device_attribute *attr, 845 char *buf) 846 { 847 struct drm_device *ddev = dev_get_drvdata(dev); 848 struct amdgpu_device *adev = drm_to_adev(ddev); 849 int size = 0; 850 int ret; 851 enum pp_clock_type od_clocks[6] = { 852 OD_SCLK, 853 OD_MCLK, 854 OD_VDDC_CURVE, 855 OD_RANGE, 856 OD_VDDGFX_OFFSET, 857 OD_CCLK, 858 }; 859 uint clk_index; 860 861 if (amdgpu_in_reset(adev)) 862 return -EPERM; 863 if (adev->in_suspend && !adev->in_runpm) 864 return -EPERM; 865 866 ret = pm_runtime_get_sync(ddev->dev); 867 if (ret < 0) { 868 pm_runtime_put_autosuspend(ddev->dev); 869 return ret; 870 } 871 872 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { 873 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); 874 if (ret) 875 break; 876 } 877 if (ret == -ENOENT) { 878 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 879 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); 880 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); 881 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); 882 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); 883 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); 884 } 885 886 if (size == 0) 887 size = sysfs_emit(buf, "\n"); 888 889 pm_runtime_mark_last_busy(ddev->dev); 890 pm_runtime_put_autosuspend(ddev->dev); 891 892 return size; 893 } 894 895 /** 896 * DOC: pp_features 897 * 898 * The amdgpu driver provides a sysfs API for adjusting what powerplay 899 * features to be enabled. The file pp_features is used for this. And 900 * this is only available for Vega10 and later dGPUs. 901 * 902 * Reading back the file will show you the followings: 903 * - Current ppfeature masks 904 * - List of the all supported powerplay features with their naming, 905 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 906 * 907 * To manually enable or disable a specific feature, just set or clear 908 * the corresponding bit from original ppfeature masks and input the 909 * new ppfeature masks. 910 */ 911 static ssize_t amdgpu_set_pp_features(struct device *dev, 912 struct device_attribute *attr, 913 const char *buf, 914 size_t count) 915 { 916 struct drm_device *ddev = dev_get_drvdata(dev); 917 struct amdgpu_device *adev = drm_to_adev(ddev); 918 uint64_t featuremask; 919 int ret; 920 921 if (amdgpu_in_reset(adev)) 922 return -EPERM; 923 if (adev->in_suspend && !adev->in_runpm) 924 return -EPERM; 925 926 ret = kstrtou64(buf, 0, &featuremask); 927 if (ret) 928 return -EINVAL; 929 930 ret = pm_runtime_get_sync(ddev->dev); 931 if (ret < 0) { 932 pm_runtime_put_autosuspend(ddev->dev); 933 return ret; 934 } 935 936 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 937 938 pm_runtime_mark_last_busy(ddev->dev); 939 pm_runtime_put_autosuspend(ddev->dev); 940 941 if (ret) 942 return -EINVAL; 943 944 return count; 945 } 946 947 static ssize_t amdgpu_get_pp_features(struct device *dev, 948 struct device_attribute *attr, 949 char *buf) 950 { 951 struct drm_device *ddev = dev_get_drvdata(dev); 952 struct amdgpu_device *adev = drm_to_adev(ddev); 953 ssize_t size; 954 int ret; 955 956 if (amdgpu_in_reset(adev)) 957 return -EPERM; 958 if (adev->in_suspend && !adev->in_runpm) 959 return -EPERM; 960 961 ret = pm_runtime_get_sync(ddev->dev); 962 if (ret < 0) { 963 pm_runtime_put_autosuspend(ddev->dev); 964 return ret; 965 } 966 967 size = amdgpu_dpm_get_ppfeature_status(adev, buf); 968 if (size <= 0) 969 size = sysfs_emit(buf, "\n"); 970 971 pm_runtime_mark_last_busy(ddev->dev); 972 pm_runtime_put_autosuspend(ddev->dev); 973 974 return size; 975 } 976 977 /** 978 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 979 * 980 * The amdgpu driver provides a sysfs API for adjusting what power levels 981 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 982 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 983 * this. 984 * 985 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 986 * Vega10 and later ASICs. 987 * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 988 * 989 * Reading back the files will show you the available power levels within 990 * the power state and the clock information for those levels. If deep sleep is 991 * applied to a clock, the level will be denoted by a special level 'S:' 992 * E.g., :: 993 * 994 * S: 19Mhz * 995 * 0: 615Mhz 996 * 1: 800Mhz 997 * 2: 888Mhz 998 * 3: 1000Mhz 999 * 1000 * 1001 * To manually adjust these states, first select manual using 1002 * power_dpm_force_performance_level. 1003 * Secondly, enter a new value for each level by inputing a string that 1004 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 1005 * E.g., 1006 * 1007 * .. code-block:: bash 1008 * 1009 * echo "4 5 6" > pp_dpm_sclk 1010 * 1011 * will enable sclk levels 4, 5, and 6. 1012 * 1013 * NOTE: change to the dcefclk max dpm level is not supported now 1014 */ 1015 1016 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 1017 enum pp_clock_type type, 1018 char *buf) 1019 { 1020 struct drm_device *ddev = dev_get_drvdata(dev); 1021 struct amdgpu_device *adev = drm_to_adev(ddev); 1022 int size = 0; 1023 int ret = 0; 1024 1025 if (amdgpu_in_reset(adev)) 1026 return -EPERM; 1027 if (adev->in_suspend && !adev->in_runpm) 1028 return -EPERM; 1029 1030 ret = pm_runtime_get_sync(ddev->dev); 1031 if (ret < 0) { 1032 pm_runtime_put_autosuspend(ddev->dev); 1033 return ret; 1034 } 1035 1036 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); 1037 if (ret == -ENOENT) 1038 size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1039 1040 if (size == 0) 1041 size = sysfs_emit(buf, "\n"); 1042 1043 pm_runtime_mark_last_busy(ddev->dev); 1044 pm_runtime_put_autosuspend(ddev->dev); 1045 1046 return size; 1047 } 1048 1049 /* 1050 * Worst case: 32 bits individually specified, in octal at 12 characters 1051 * per line (+1 for \n). 1052 */ 1053 #define AMDGPU_MASK_BUF_MAX (32 * 13) 1054 1055 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1056 { 1057 int ret; 1058 unsigned long level; 1059 char *sub_str = NULL; 1060 char *tmp; 1061 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1062 const char delimiter[3] = {' ', '\n', '\0'}; 1063 size_t bytes; 1064 1065 *mask = 0; 1066 1067 bytes = min(count, sizeof(buf_cpy) - 1); 1068 memcpy(buf_cpy, buf, bytes); 1069 buf_cpy[bytes] = '\0'; 1070 tmp = buf_cpy; 1071 while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1072 if (strlen(sub_str)) { 1073 ret = kstrtoul(sub_str, 0, &level); 1074 if (ret || level > 31) 1075 return -EINVAL; 1076 *mask |= 1 << level; 1077 } else 1078 break; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 1085 enum pp_clock_type type, 1086 const char *buf, 1087 size_t count) 1088 { 1089 struct drm_device *ddev = dev_get_drvdata(dev); 1090 struct amdgpu_device *adev = drm_to_adev(ddev); 1091 int ret; 1092 uint32_t mask = 0; 1093 1094 if (amdgpu_in_reset(adev)) 1095 return -EPERM; 1096 if (adev->in_suspend && !adev->in_runpm) 1097 return -EPERM; 1098 1099 ret = amdgpu_read_mask(buf, count, &mask); 1100 if (ret) 1101 return ret; 1102 1103 ret = pm_runtime_get_sync(ddev->dev); 1104 if (ret < 0) { 1105 pm_runtime_put_autosuspend(ddev->dev); 1106 return ret; 1107 } 1108 1109 ret = amdgpu_dpm_force_clock_level(adev, type, mask); 1110 1111 pm_runtime_mark_last_busy(ddev->dev); 1112 pm_runtime_put_autosuspend(ddev->dev); 1113 1114 if (ret) 1115 return -EINVAL; 1116 1117 return count; 1118 } 1119 1120 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1121 struct device_attribute *attr, 1122 char *buf) 1123 { 1124 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 1125 } 1126 1127 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1128 struct device_attribute *attr, 1129 const char *buf, 1130 size_t count) 1131 { 1132 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 1133 } 1134 1135 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1136 struct device_attribute *attr, 1137 char *buf) 1138 { 1139 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1140 } 1141 1142 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1143 struct device_attribute *attr, 1144 const char *buf, 1145 size_t count) 1146 { 1147 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1148 } 1149 1150 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1151 struct device_attribute *attr, 1152 char *buf) 1153 { 1154 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1155 } 1156 1157 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1158 struct device_attribute *attr, 1159 const char *buf, 1160 size_t count) 1161 { 1162 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1163 } 1164 1165 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1166 struct device_attribute *attr, 1167 char *buf) 1168 { 1169 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1170 } 1171 1172 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1173 struct device_attribute *attr, 1174 const char *buf, 1175 size_t count) 1176 { 1177 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1178 } 1179 1180 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 1181 struct device_attribute *attr, 1182 char *buf) 1183 { 1184 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 1185 } 1186 1187 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 1188 struct device_attribute *attr, 1189 const char *buf, 1190 size_t count) 1191 { 1192 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 1193 } 1194 1195 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev, 1196 struct device_attribute *attr, 1197 char *buf) 1198 { 1199 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf); 1200 } 1201 1202 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev, 1203 struct device_attribute *attr, 1204 const char *buf, 1205 size_t count) 1206 { 1207 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count); 1208 } 1209 1210 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 1211 struct device_attribute *attr, 1212 char *buf) 1213 { 1214 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 1215 } 1216 1217 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 1218 struct device_attribute *attr, 1219 const char *buf, 1220 size_t count) 1221 { 1222 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 1223 } 1224 1225 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev, 1226 struct device_attribute *attr, 1227 char *buf) 1228 { 1229 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf); 1230 } 1231 1232 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev, 1233 struct device_attribute *attr, 1234 const char *buf, 1235 size_t count) 1236 { 1237 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count); 1238 } 1239 1240 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1241 struct device_attribute *attr, 1242 char *buf) 1243 { 1244 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1245 } 1246 1247 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1248 struct device_attribute *attr, 1249 const char *buf, 1250 size_t count) 1251 { 1252 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1253 } 1254 1255 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1256 struct device_attribute *attr, 1257 char *buf) 1258 { 1259 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1260 } 1261 1262 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1263 struct device_attribute *attr, 1264 const char *buf, 1265 size_t count) 1266 { 1267 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1268 } 1269 1270 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1271 struct device_attribute *attr, 1272 char *buf) 1273 { 1274 struct drm_device *ddev = dev_get_drvdata(dev); 1275 struct amdgpu_device *adev = drm_to_adev(ddev); 1276 uint32_t value = 0; 1277 int ret; 1278 1279 if (amdgpu_in_reset(adev)) 1280 return -EPERM; 1281 if (adev->in_suspend && !adev->in_runpm) 1282 return -EPERM; 1283 1284 ret = pm_runtime_get_sync(ddev->dev); 1285 if (ret < 0) { 1286 pm_runtime_put_autosuspend(ddev->dev); 1287 return ret; 1288 } 1289 1290 value = amdgpu_dpm_get_sclk_od(adev); 1291 1292 pm_runtime_mark_last_busy(ddev->dev); 1293 pm_runtime_put_autosuspend(ddev->dev); 1294 1295 return sysfs_emit(buf, "%d\n", value); 1296 } 1297 1298 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1299 struct device_attribute *attr, 1300 const char *buf, 1301 size_t count) 1302 { 1303 struct drm_device *ddev = dev_get_drvdata(dev); 1304 struct amdgpu_device *adev = drm_to_adev(ddev); 1305 int ret; 1306 long int value; 1307 1308 if (amdgpu_in_reset(adev)) 1309 return -EPERM; 1310 if (adev->in_suspend && !adev->in_runpm) 1311 return -EPERM; 1312 1313 ret = kstrtol(buf, 0, &value); 1314 1315 if (ret) 1316 return -EINVAL; 1317 1318 ret = pm_runtime_get_sync(ddev->dev); 1319 if (ret < 0) { 1320 pm_runtime_put_autosuspend(ddev->dev); 1321 return ret; 1322 } 1323 1324 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1325 1326 pm_runtime_mark_last_busy(ddev->dev); 1327 pm_runtime_put_autosuspend(ddev->dev); 1328 1329 return count; 1330 } 1331 1332 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1333 struct device_attribute *attr, 1334 char *buf) 1335 { 1336 struct drm_device *ddev = dev_get_drvdata(dev); 1337 struct amdgpu_device *adev = drm_to_adev(ddev); 1338 uint32_t value = 0; 1339 int ret; 1340 1341 if (amdgpu_in_reset(adev)) 1342 return -EPERM; 1343 if (adev->in_suspend && !adev->in_runpm) 1344 return -EPERM; 1345 1346 ret = pm_runtime_get_sync(ddev->dev); 1347 if (ret < 0) { 1348 pm_runtime_put_autosuspend(ddev->dev); 1349 return ret; 1350 } 1351 1352 value = amdgpu_dpm_get_mclk_od(adev); 1353 1354 pm_runtime_mark_last_busy(ddev->dev); 1355 pm_runtime_put_autosuspend(ddev->dev); 1356 1357 return sysfs_emit(buf, "%d\n", value); 1358 } 1359 1360 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1361 struct device_attribute *attr, 1362 const char *buf, 1363 size_t count) 1364 { 1365 struct drm_device *ddev = dev_get_drvdata(dev); 1366 struct amdgpu_device *adev = drm_to_adev(ddev); 1367 int ret; 1368 long int value; 1369 1370 if (amdgpu_in_reset(adev)) 1371 return -EPERM; 1372 if (adev->in_suspend && !adev->in_runpm) 1373 return -EPERM; 1374 1375 ret = kstrtol(buf, 0, &value); 1376 1377 if (ret) 1378 return -EINVAL; 1379 1380 ret = pm_runtime_get_sync(ddev->dev); 1381 if (ret < 0) { 1382 pm_runtime_put_autosuspend(ddev->dev); 1383 return ret; 1384 } 1385 1386 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1387 1388 pm_runtime_mark_last_busy(ddev->dev); 1389 pm_runtime_put_autosuspend(ddev->dev); 1390 1391 return count; 1392 } 1393 1394 /** 1395 * DOC: pp_power_profile_mode 1396 * 1397 * The amdgpu driver provides a sysfs API for adjusting the heuristics 1398 * related to switching between power levels in a power state. The file 1399 * pp_power_profile_mode is used for this. 1400 * 1401 * Reading this file outputs a list of all of the predefined power profiles 1402 * and the relevant heuristics settings for that profile. 1403 * 1404 * To select a profile or create a custom profile, first select manual using 1405 * power_dpm_force_performance_level. Writing the number of a predefined 1406 * profile to pp_power_profile_mode will enable those heuristics. To 1407 * create a custom set of heuristics, write a string of numbers to the file 1408 * starting with the number of the custom profile along with a setting 1409 * for each heuristic parameter. Due to differences across asic families 1410 * the heuristic parameters vary from family to family. 1411 * 1412 */ 1413 1414 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1415 struct device_attribute *attr, 1416 char *buf) 1417 { 1418 struct drm_device *ddev = dev_get_drvdata(dev); 1419 struct amdgpu_device *adev = drm_to_adev(ddev); 1420 ssize_t size; 1421 int ret; 1422 1423 if (amdgpu_in_reset(adev)) 1424 return -EPERM; 1425 if (adev->in_suspend && !adev->in_runpm) 1426 return -EPERM; 1427 1428 ret = pm_runtime_get_sync(ddev->dev); 1429 if (ret < 0) { 1430 pm_runtime_put_autosuspend(ddev->dev); 1431 return ret; 1432 } 1433 1434 size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1435 if (size <= 0) 1436 size = sysfs_emit(buf, "\n"); 1437 1438 pm_runtime_mark_last_busy(ddev->dev); 1439 pm_runtime_put_autosuspend(ddev->dev); 1440 1441 return size; 1442 } 1443 1444 1445 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1446 struct device_attribute *attr, 1447 const char *buf, 1448 size_t count) 1449 { 1450 int ret; 1451 struct drm_device *ddev = dev_get_drvdata(dev); 1452 struct amdgpu_device *adev = drm_to_adev(ddev); 1453 uint32_t parameter_size = 0; 1454 long parameter[64]; 1455 char *sub_str, buf_cpy[128]; 1456 char *tmp_str; 1457 uint32_t i = 0; 1458 char tmp[2]; 1459 long int profile_mode = 0; 1460 const char delimiter[3] = {' ', '\n', '\0'}; 1461 1462 if (amdgpu_in_reset(adev)) 1463 return -EPERM; 1464 if (adev->in_suspend && !adev->in_runpm) 1465 return -EPERM; 1466 1467 tmp[0] = *(buf); 1468 tmp[1] = '\0'; 1469 ret = kstrtol(tmp, 0, &profile_mode); 1470 if (ret) 1471 return -EINVAL; 1472 1473 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1474 if (count < 2 || count > 127) 1475 return -EINVAL; 1476 while (isspace(*++buf)) 1477 i++; 1478 memcpy(buf_cpy, buf, count-i); 1479 tmp_str = buf_cpy; 1480 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1481 if (strlen(sub_str) == 0) 1482 continue; 1483 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1484 if (ret) 1485 return -EINVAL; 1486 parameter_size++; 1487 while (isspace(*tmp_str)) 1488 tmp_str++; 1489 } 1490 } 1491 parameter[parameter_size] = profile_mode; 1492 1493 ret = pm_runtime_get_sync(ddev->dev); 1494 if (ret < 0) { 1495 pm_runtime_put_autosuspend(ddev->dev); 1496 return ret; 1497 } 1498 1499 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1500 1501 pm_runtime_mark_last_busy(ddev->dev); 1502 pm_runtime_put_autosuspend(ddev->dev); 1503 1504 if (!ret) 1505 return count; 1506 1507 return -EINVAL; 1508 } 1509 1510 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev, 1511 enum amd_pp_sensors sensor, 1512 void *query) 1513 { 1514 int r, size = sizeof(uint32_t); 1515 1516 if (amdgpu_in_reset(adev)) 1517 return -EPERM; 1518 if (adev->in_suspend && !adev->in_runpm) 1519 return -EPERM; 1520 1521 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 1522 if (r < 0) { 1523 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1524 return r; 1525 } 1526 1527 /* get the sensor value */ 1528 r = amdgpu_dpm_read_sensor(adev, sensor, query, &size); 1529 1530 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1531 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1532 1533 return r; 1534 } 1535 1536 /** 1537 * DOC: gpu_busy_percent 1538 * 1539 * The amdgpu driver provides a sysfs API for reading how busy the GPU 1540 * is as a percentage. The file gpu_busy_percent is used for this. 1541 * The SMU firmware computes a percentage of load based on the 1542 * aggregate activity level in the IP cores. 1543 */ 1544 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1545 struct device_attribute *attr, 1546 char *buf) 1547 { 1548 struct drm_device *ddev = dev_get_drvdata(dev); 1549 struct amdgpu_device *adev = drm_to_adev(ddev); 1550 unsigned int value; 1551 int r; 1552 1553 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value); 1554 if (r) 1555 return r; 1556 1557 return sysfs_emit(buf, "%d\n", value); 1558 } 1559 1560 /** 1561 * DOC: mem_busy_percent 1562 * 1563 * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1564 * is as a percentage. The file mem_busy_percent is used for this. 1565 * The SMU firmware computes a percentage of load based on the 1566 * aggregate activity level in the IP cores. 1567 */ 1568 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1569 struct device_attribute *attr, 1570 char *buf) 1571 { 1572 struct drm_device *ddev = dev_get_drvdata(dev); 1573 struct amdgpu_device *adev = drm_to_adev(ddev); 1574 unsigned int value; 1575 int r; 1576 1577 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value); 1578 if (r) 1579 return r; 1580 1581 return sysfs_emit(buf, "%d\n", value); 1582 } 1583 1584 /** 1585 * DOC: vcn_busy_percent 1586 * 1587 * The amdgpu driver provides a sysfs API for reading how busy the VCN 1588 * is as a percentage. The file vcn_busy_percent is used for this. 1589 * The SMU firmware computes a percentage of load based on the 1590 * aggregate activity level in the IP cores. 1591 */ 1592 static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev, 1593 struct device_attribute *attr, 1594 char *buf) 1595 { 1596 struct drm_device *ddev = dev_get_drvdata(dev); 1597 struct amdgpu_device *adev = drm_to_adev(ddev); 1598 unsigned int value; 1599 int r; 1600 1601 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD, &value); 1602 if (r) 1603 return r; 1604 1605 return sysfs_emit(buf, "%d\n", value); 1606 } 1607 1608 /** 1609 * DOC: pcie_bw 1610 * 1611 * The amdgpu driver provides a sysfs API for estimating how much data 1612 * has been received and sent by the GPU in the last second through PCIe. 1613 * The file pcie_bw is used for this. 1614 * The Perf counters count the number of received and sent messages and return 1615 * those values, as well as the maximum payload size of a PCIe packet (mps). 1616 * Note that it is not possible to easily and quickly obtain the size of each 1617 * packet transmitted, so we output the max payload size (mps) to allow for 1618 * quick estimation of the PCIe bandwidth usage 1619 */ 1620 static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1621 struct device_attribute *attr, 1622 char *buf) 1623 { 1624 struct drm_device *ddev = dev_get_drvdata(dev); 1625 struct amdgpu_device *adev = drm_to_adev(ddev); 1626 uint64_t count0 = 0, count1 = 0; 1627 int ret; 1628 1629 if (amdgpu_in_reset(adev)) 1630 return -EPERM; 1631 if (adev->in_suspend && !adev->in_runpm) 1632 return -EPERM; 1633 1634 if (adev->flags & AMD_IS_APU) 1635 return -ENODATA; 1636 1637 if (!adev->asic_funcs->get_pcie_usage) 1638 return -ENODATA; 1639 1640 ret = pm_runtime_get_sync(ddev->dev); 1641 if (ret < 0) { 1642 pm_runtime_put_autosuspend(ddev->dev); 1643 return ret; 1644 } 1645 1646 amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1647 1648 pm_runtime_mark_last_busy(ddev->dev); 1649 pm_runtime_put_autosuspend(ddev->dev); 1650 1651 return sysfs_emit(buf, "%llu %llu %i\n", 1652 count0, count1, pcie_get_mps(adev->pdev)); 1653 } 1654 1655 /** 1656 * DOC: unique_id 1657 * 1658 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1659 * The file unique_id is used for this. 1660 * This will provide a Unique ID that will persist from machine to machine 1661 * 1662 * NOTE: This will only work for GFX9 and newer. This file will be absent 1663 * on unsupported ASICs (GFX8 and older) 1664 */ 1665 static ssize_t amdgpu_get_unique_id(struct device *dev, 1666 struct device_attribute *attr, 1667 char *buf) 1668 { 1669 struct drm_device *ddev = dev_get_drvdata(dev); 1670 struct amdgpu_device *adev = drm_to_adev(ddev); 1671 1672 if (amdgpu_in_reset(adev)) 1673 return -EPERM; 1674 if (adev->in_suspend && !adev->in_runpm) 1675 return -EPERM; 1676 1677 if (adev->unique_id) 1678 return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1679 1680 return 0; 1681 } 1682 1683 /** 1684 * DOC: thermal_throttling_logging 1685 * 1686 * Thermal throttling pulls down the clock frequency and thus the performance. 1687 * It's an useful mechanism to protect the chip from overheating. Since it 1688 * impacts performance, the user controls whether it is enabled and if so, 1689 * the log frequency. 1690 * 1691 * Reading back the file shows you the status(enabled or disabled) and 1692 * the interval(in seconds) between each thermal logging. 1693 * 1694 * Writing an integer to the file, sets a new logging interval, in seconds. 1695 * The value should be between 1 and 3600. If the value is less than 1, 1696 * thermal logging is disabled. Values greater than 3600 are ignored. 1697 */ 1698 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1699 struct device_attribute *attr, 1700 char *buf) 1701 { 1702 struct drm_device *ddev = dev_get_drvdata(dev); 1703 struct amdgpu_device *adev = drm_to_adev(ddev); 1704 1705 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 1706 adev_to_drm(adev)->unique, 1707 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1708 adev->throttling_logging_rs.interval / HZ + 1); 1709 } 1710 1711 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1712 struct device_attribute *attr, 1713 const char *buf, 1714 size_t count) 1715 { 1716 struct drm_device *ddev = dev_get_drvdata(dev); 1717 struct amdgpu_device *adev = drm_to_adev(ddev); 1718 long throttling_logging_interval; 1719 unsigned long flags; 1720 int ret = 0; 1721 1722 ret = kstrtol(buf, 0, &throttling_logging_interval); 1723 if (ret) 1724 return ret; 1725 1726 if (throttling_logging_interval > 3600) 1727 return -EINVAL; 1728 1729 if (throttling_logging_interval > 0) { 1730 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1731 /* 1732 * Reset the ratelimit timer internals. 1733 * This can effectively restart the timer. 1734 */ 1735 adev->throttling_logging_rs.interval = 1736 (throttling_logging_interval - 1) * HZ; 1737 adev->throttling_logging_rs.begin = 0; 1738 adev->throttling_logging_rs.printed = 0; 1739 adev->throttling_logging_rs.missed = 0; 1740 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1741 1742 atomic_set(&adev->throttling_logging_enabled, 1); 1743 } else { 1744 atomic_set(&adev->throttling_logging_enabled, 0); 1745 } 1746 1747 return count; 1748 } 1749 1750 /** 1751 * DOC: apu_thermal_cap 1752 * 1753 * The amdgpu driver provides a sysfs API for retrieving/updating thermal 1754 * limit temperature in millidegrees Celsius 1755 * 1756 * Reading back the file shows you core limit value 1757 * 1758 * Writing an integer to the file, sets a new thermal limit. The value 1759 * should be between 0 and 100. If the value is less than 0 or greater 1760 * than 100, then the write request will be ignored. 1761 */ 1762 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, 1763 struct device_attribute *attr, 1764 char *buf) 1765 { 1766 int ret, size; 1767 u32 limit; 1768 struct drm_device *ddev = dev_get_drvdata(dev); 1769 struct amdgpu_device *adev = drm_to_adev(ddev); 1770 1771 ret = pm_runtime_get_sync(ddev->dev); 1772 if (ret < 0) { 1773 pm_runtime_put_autosuspend(ddev->dev); 1774 return ret; 1775 } 1776 1777 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit); 1778 if (!ret) 1779 size = sysfs_emit(buf, "%u\n", limit); 1780 else 1781 size = sysfs_emit(buf, "failed to get thermal limit\n"); 1782 1783 pm_runtime_mark_last_busy(ddev->dev); 1784 pm_runtime_put_autosuspend(ddev->dev); 1785 1786 return size; 1787 } 1788 1789 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, 1790 struct device_attribute *attr, 1791 const char *buf, 1792 size_t count) 1793 { 1794 int ret; 1795 u32 value; 1796 struct drm_device *ddev = dev_get_drvdata(dev); 1797 struct amdgpu_device *adev = drm_to_adev(ddev); 1798 1799 ret = kstrtou32(buf, 10, &value); 1800 if (ret) 1801 return ret; 1802 1803 if (value > 100) { 1804 dev_err(dev, "Invalid argument !\n"); 1805 return -EINVAL; 1806 } 1807 1808 ret = pm_runtime_get_sync(ddev->dev); 1809 if (ret < 0) { 1810 pm_runtime_put_autosuspend(ddev->dev); 1811 return ret; 1812 } 1813 1814 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value); 1815 if (ret) { 1816 dev_err(dev, "failed to update thermal limit\n"); 1817 return ret; 1818 } 1819 1820 pm_runtime_mark_last_busy(ddev->dev); 1821 pm_runtime_put_autosuspend(ddev->dev); 1822 1823 return count; 1824 } 1825 1826 static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev, 1827 struct amdgpu_device_attr *attr, 1828 uint32_t mask, 1829 enum amdgpu_device_attr_states *states) 1830 { 1831 if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP) 1832 *states = ATTR_STATE_UNSUPPORTED; 1833 1834 return 0; 1835 } 1836 1837 static ssize_t amdgpu_get_pm_metrics(struct device *dev, 1838 struct device_attribute *attr, char *buf) 1839 { 1840 struct drm_device *ddev = dev_get_drvdata(dev); 1841 struct amdgpu_device *adev = drm_to_adev(ddev); 1842 ssize_t size = 0; 1843 int ret; 1844 1845 if (amdgpu_in_reset(adev)) 1846 return -EPERM; 1847 if (adev->in_suspend && !adev->in_runpm) 1848 return -EPERM; 1849 1850 ret = pm_runtime_get_sync(ddev->dev); 1851 if (ret < 0) { 1852 pm_runtime_put_autosuspend(ddev->dev); 1853 return ret; 1854 } 1855 1856 size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE); 1857 1858 pm_runtime_mark_last_busy(ddev->dev); 1859 pm_runtime_put_autosuspend(ddev->dev); 1860 1861 return size; 1862 } 1863 1864 /** 1865 * DOC: gpu_metrics 1866 * 1867 * The amdgpu driver provides a sysfs API for retrieving current gpu 1868 * metrics data. The file gpu_metrics is used for this. Reading the 1869 * file will dump all the current gpu metrics data. 1870 * 1871 * These data include temperature, frequency, engines utilization, 1872 * power consume, throttler status, fan speed and cpu core statistics( 1873 * available for APU only). That's it will give a snapshot of all sensors 1874 * at the same time. 1875 */ 1876 static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1877 struct device_attribute *attr, 1878 char *buf) 1879 { 1880 struct drm_device *ddev = dev_get_drvdata(dev); 1881 struct amdgpu_device *adev = drm_to_adev(ddev); 1882 void *gpu_metrics; 1883 ssize_t size = 0; 1884 int ret; 1885 1886 if (amdgpu_in_reset(adev)) 1887 return -EPERM; 1888 if (adev->in_suspend && !adev->in_runpm) 1889 return -EPERM; 1890 1891 ret = pm_runtime_get_sync(ddev->dev); 1892 if (ret < 0) { 1893 pm_runtime_put_autosuspend(ddev->dev); 1894 return ret; 1895 } 1896 1897 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1898 if (size <= 0) 1899 goto out; 1900 1901 if (size >= PAGE_SIZE) 1902 size = PAGE_SIZE - 1; 1903 1904 memcpy(buf, gpu_metrics, size); 1905 1906 out: 1907 pm_runtime_mark_last_busy(ddev->dev); 1908 pm_runtime_put_autosuspend(ddev->dev); 1909 1910 return size; 1911 } 1912 1913 static int amdgpu_show_powershift_percent(struct device *dev, 1914 char *buf, enum amd_pp_sensors sensor) 1915 { 1916 struct drm_device *ddev = dev_get_drvdata(dev); 1917 struct amdgpu_device *adev = drm_to_adev(ddev); 1918 uint32_t ss_power; 1919 int r = 0, i; 1920 1921 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1922 if (r == -EOPNOTSUPP) { 1923 /* sensor not available on dGPU, try to read from APU */ 1924 adev = NULL; 1925 mutex_lock(&mgpu_info.mutex); 1926 for (i = 0; i < mgpu_info.num_gpu; i++) { 1927 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { 1928 adev = mgpu_info.gpu_ins[i].adev; 1929 break; 1930 } 1931 } 1932 mutex_unlock(&mgpu_info.mutex); 1933 if (adev) 1934 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1935 } 1936 1937 if (r) 1938 return r; 1939 1940 return sysfs_emit(buf, "%u%%\n", ss_power); 1941 } 1942 1943 /** 1944 * DOC: smartshift_apu_power 1945 * 1946 * The amdgpu driver provides a sysfs API for reporting APU power 1947 * shift in percentage if platform supports smartshift. Value 0 means that 1948 * there is no powershift and values between [1-100] means that the power 1949 * is shifted to APU, the percentage of boost is with respect to APU power 1950 * limit on the platform. 1951 */ 1952 1953 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, 1954 char *buf) 1955 { 1956 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE); 1957 } 1958 1959 /** 1960 * DOC: smartshift_dgpu_power 1961 * 1962 * The amdgpu driver provides a sysfs API for reporting dGPU power 1963 * shift in percentage if platform supports smartshift. Value 0 means that 1964 * there is no powershift and values between [1-100] means that the power is 1965 * shifted to dGPU, the percentage of boost is with respect to dGPU power 1966 * limit on the platform. 1967 */ 1968 1969 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, 1970 char *buf) 1971 { 1972 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE); 1973 } 1974 1975 /** 1976 * DOC: smartshift_bias 1977 * 1978 * The amdgpu driver provides a sysfs API for reporting the 1979 * smartshift(SS2.0) bias level. The value ranges from -100 to 100 1980 * and the default is 0. -100 sets maximum preference to APU 1981 * and 100 sets max perference to dGPU. 1982 */ 1983 1984 static ssize_t amdgpu_get_smartshift_bias(struct device *dev, 1985 struct device_attribute *attr, 1986 char *buf) 1987 { 1988 int r = 0; 1989 1990 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); 1991 1992 return r; 1993 } 1994 1995 static ssize_t amdgpu_set_smartshift_bias(struct device *dev, 1996 struct device_attribute *attr, 1997 const char *buf, size_t count) 1998 { 1999 struct drm_device *ddev = dev_get_drvdata(dev); 2000 struct amdgpu_device *adev = drm_to_adev(ddev); 2001 int r = 0; 2002 int bias = 0; 2003 2004 if (amdgpu_in_reset(adev)) 2005 return -EPERM; 2006 if (adev->in_suspend && !adev->in_runpm) 2007 return -EPERM; 2008 2009 r = pm_runtime_get_sync(ddev->dev); 2010 if (r < 0) { 2011 pm_runtime_put_autosuspend(ddev->dev); 2012 return r; 2013 } 2014 2015 r = kstrtoint(buf, 10, &bias); 2016 if (r) 2017 goto out; 2018 2019 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) 2020 bias = AMDGPU_SMARTSHIFT_MAX_BIAS; 2021 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) 2022 bias = AMDGPU_SMARTSHIFT_MIN_BIAS; 2023 2024 amdgpu_smartshift_bias = bias; 2025 r = count; 2026 2027 /* TODO: update bias level with SMU message */ 2028 2029 out: 2030 pm_runtime_mark_last_busy(ddev->dev); 2031 pm_runtime_put_autosuspend(ddev->dev); 2032 return r; 2033 } 2034 2035 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2036 uint32_t mask, enum amdgpu_device_attr_states *states) 2037 { 2038 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 2039 *states = ATTR_STATE_UNSUPPORTED; 2040 2041 return 0; 2042 } 2043 2044 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2045 uint32_t mask, enum amdgpu_device_attr_states *states) 2046 { 2047 uint32_t ss_power; 2048 2049 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 2050 *states = ATTR_STATE_UNSUPPORTED; 2051 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 2052 (void *)&ss_power)) 2053 *states = ATTR_STATE_UNSUPPORTED; 2054 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 2055 (void *)&ss_power)) 2056 *states = ATTR_STATE_UNSUPPORTED; 2057 2058 return 0; 2059 } 2060 2061 static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2062 uint32_t mask, enum amdgpu_device_attr_states *states) 2063 { 2064 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2065 2066 *states = ATTR_STATE_SUPPORTED; 2067 2068 if (!amdgpu_dpm_is_overdrive_supported(adev)) { 2069 *states = ATTR_STATE_UNSUPPORTED; 2070 return 0; 2071 } 2072 2073 /* Enable pp_od_clk_voltage node for gc 9.4.3 SRIOV/BM support */ 2074 if (gc_ver == IP_VERSION(9, 4, 3)) { 2075 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2076 *states = ATTR_STATE_UNSUPPORTED; 2077 return 0; 2078 } 2079 2080 if (!(attr->flags & mask)) 2081 *states = ATTR_STATE_UNSUPPORTED; 2082 2083 return 0; 2084 } 2085 2086 static int pp_dpm_dcefclk_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2087 uint32_t mask, enum amdgpu_device_attr_states *states) 2088 { 2089 struct device_attribute *dev_attr = &attr->dev_attr; 2090 uint32_t gc_ver; 2091 2092 *states = ATTR_STATE_SUPPORTED; 2093 2094 if (!(attr->flags & mask)) { 2095 *states = ATTR_STATE_UNSUPPORTED; 2096 return 0; 2097 } 2098 2099 gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2100 /* dcefclk node is not available on gfx 11.0.3 sriov */ 2101 if ((gc_ver == IP_VERSION(11, 0, 3) && amdgpu_sriov_is_pp_one_vf(adev)) || 2102 gc_ver < IP_VERSION(9, 0, 0) || 2103 !amdgpu_device_has_display_hardware(adev)) 2104 *states = ATTR_STATE_UNSUPPORTED; 2105 2106 /* SMU MP1 does not support dcefclk level setting, 2107 * setting should not be allowed from VF if not in one VF mode. 2108 */ 2109 if (gc_ver >= IP_VERSION(10, 0, 0) || 2110 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))) { 2111 dev_attr->attr.mode &= ~S_IWUGO; 2112 dev_attr->store = NULL; 2113 } 2114 2115 return 0; 2116 } 2117 2118 /* Following items will be read out to indicate current plpd policy: 2119 * - -1: none 2120 * - 0: disallow 2121 * - 1: default 2122 * - 2: optimized 2123 */ 2124 static ssize_t amdgpu_get_xgmi_plpd_policy(struct device *dev, 2125 struct device_attribute *attr, 2126 char *buf) 2127 { 2128 struct drm_device *ddev = dev_get_drvdata(dev); 2129 struct amdgpu_device *adev = drm_to_adev(ddev); 2130 char *mode_desc = "none"; 2131 int mode; 2132 2133 if (amdgpu_in_reset(adev)) 2134 return -EPERM; 2135 if (adev->in_suspend && !adev->in_runpm) 2136 return -EPERM; 2137 2138 mode = amdgpu_dpm_get_xgmi_plpd_mode(adev, &mode_desc); 2139 2140 return sysfs_emit(buf, "%d: %s\n", mode, mode_desc); 2141 } 2142 2143 /* Following argument value is expected from user to change plpd policy 2144 * - arg 0: disallow plpd 2145 * - arg 1: default policy 2146 * - arg 2: optimized policy 2147 */ 2148 static ssize_t amdgpu_set_xgmi_plpd_policy(struct device *dev, 2149 struct device_attribute *attr, 2150 const char *buf, size_t count) 2151 { 2152 struct drm_device *ddev = dev_get_drvdata(dev); 2153 struct amdgpu_device *adev = drm_to_adev(ddev); 2154 int mode, ret; 2155 2156 if (amdgpu_in_reset(adev)) 2157 return -EPERM; 2158 if (adev->in_suspend && !adev->in_runpm) 2159 return -EPERM; 2160 2161 ret = kstrtos32(buf, 0, &mode); 2162 if (ret) 2163 return -EINVAL; 2164 2165 ret = pm_runtime_get_sync(ddev->dev); 2166 if (ret < 0) { 2167 pm_runtime_put_autosuspend(ddev->dev); 2168 return ret; 2169 } 2170 2171 ret = amdgpu_dpm_set_xgmi_plpd_mode(adev, mode); 2172 2173 pm_runtime_mark_last_busy(ddev->dev); 2174 pm_runtime_put_autosuspend(ddev->dev); 2175 2176 if (ret) 2177 return ret; 2178 2179 return count; 2180 } 2181 2182 static struct amdgpu_device_attr amdgpu_device_attrs[] = { 2183 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2184 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2185 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2186 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2187 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2188 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2189 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2190 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2191 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2192 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2193 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2194 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2195 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2196 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2197 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2198 .attr_update = pp_dpm_dcefclk_attr_update), 2199 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2200 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 2201 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 2202 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2203 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC, 2204 .attr_update = pp_od_clk_voltage_attr_update), 2205 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2206 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2207 AMDGPU_DEVICE_ATTR_RO(vcn_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2208 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 2209 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2210 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2211 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2212 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2213 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2214 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, 2215 .attr_update = ss_power_attr_update), 2216 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, 2217 .attr_update = ss_power_attr_update), 2218 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, 2219 .attr_update = ss_bias_attr_update), 2220 AMDGPU_DEVICE_ATTR_RW(xgmi_plpd_policy, ATTR_FLAG_BASIC), 2221 AMDGPU_DEVICE_ATTR_RO(pm_metrics, ATTR_FLAG_BASIC, 2222 .attr_update = amdgpu_pm_metrics_attr_update), 2223 }; 2224 2225 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2226 uint32_t mask, enum amdgpu_device_attr_states *states) 2227 { 2228 struct device_attribute *dev_attr = &attr->dev_attr; 2229 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0); 2230 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2231 const char *attr_name = dev_attr->attr.name; 2232 2233 if (!(attr->flags & mask)) { 2234 *states = ATTR_STATE_UNSUPPORTED; 2235 return 0; 2236 } 2237 2238 #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) 2239 2240 if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 2241 if (gc_ver < IP_VERSION(9, 0, 0)) 2242 *states = ATTR_STATE_UNSUPPORTED; 2243 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 2244 if (mp1_ver < IP_VERSION(10, 0, 0)) 2245 *states = ATTR_STATE_UNSUPPORTED; 2246 } else if (DEVICE_ATTR_IS(mem_busy_percent)) { 2247 if ((adev->flags & AMD_IS_APU && 2248 gc_ver != IP_VERSION(9, 4, 3)) || 2249 gc_ver == IP_VERSION(9, 0, 1)) 2250 *states = ATTR_STATE_UNSUPPORTED; 2251 } else if (DEVICE_ATTR_IS(vcn_busy_percent)) { 2252 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2253 gc_ver == IP_VERSION(10, 3, 3) || 2254 gc_ver == IP_VERSION(10, 3, 6) || 2255 gc_ver == IP_VERSION(10, 3, 7) || 2256 gc_ver == IP_VERSION(11, 0, 1) || 2257 gc_ver == IP_VERSION(11, 0, 4) || 2258 gc_ver == IP_VERSION(11, 5, 0))) 2259 *states = ATTR_STATE_UNSUPPORTED; 2260 } else if (DEVICE_ATTR_IS(pcie_bw)) { 2261 /* PCIe Perf counters won't work on APU nodes */ 2262 if (adev->flags & AMD_IS_APU || 2263 !adev->asic_funcs->get_pcie_usage) 2264 *states = ATTR_STATE_UNSUPPORTED; 2265 } else if (DEVICE_ATTR_IS(unique_id)) { 2266 switch (gc_ver) { 2267 case IP_VERSION(9, 0, 1): 2268 case IP_VERSION(9, 4, 0): 2269 case IP_VERSION(9, 4, 1): 2270 case IP_VERSION(9, 4, 2): 2271 case IP_VERSION(9, 4, 3): 2272 case IP_VERSION(10, 3, 0): 2273 case IP_VERSION(11, 0, 0): 2274 case IP_VERSION(11, 0, 1): 2275 case IP_VERSION(11, 0, 2): 2276 case IP_VERSION(11, 0, 3): 2277 *states = ATTR_STATE_SUPPORTED; 2278 break; 2279 default: 2280 *states = ATTR_STATE_UNSUPPORTED; 2281 } 2282 } else if (DEVICE_ATTR_IS(pp_features)) { 2283 if ((adev->flags & AMD_IS_APU && 2284 gc_ver != IP_VERSION(9, 4, 3)) || 2285 gc_ver < IP_VERSION(9, 0, 0)) 2286 *states = ATTR_STATE_UNSUPPORTED; 2287 } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2288 if (gc_ver < IP_VERSION(9, 1, 0)) 2289 *states = ATTR_STATE_UNSUPPORTED; 2290 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 2291 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2292 gc_ver == IP_VERSION(10, 3, 3) || 2293 gc_ver == IP_VERSION(10, 3, 6) || 2294 gc_ver == IP_VERSION(10, 3, 7) || 2295 gc_ver == IP_VERSION(10, 3, 0) || 2296 gc_ver == IP_VERSION(10, 1, 2) || 2297 gc_ver == IP_VERSION(11, 0, 0) || 2298 gc_ver == IP_VERSION(11, 0, 1) || 2299 gc_ver == IP_VERSION(11, 0, 4) || 2300 gc_ver == IP_VERSION(11, 5, 0) || 2301 gc_ver == IP_VERSION(11, 0, 2) || 2302 gc_ver == IP_VERSION(11, 0, 3) || 2303 gc_ver == IP_VERSION(9, 4, 3))) 2304 *states = ATTR_STATE_UNSUPPORTED; 2305 } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { 2306 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2307 gc_ver == IP_VERSION(10, 3, 0) || 2308 gc_ver == IP_VERSION(11, 0, 2) || 2309 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2310 *states = ATTR_STATE_UNSUPPORTED; 2311 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 2312 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2313 gc_ver == IP_VERSION(10, 3, 3) || 2314 gc_ver == IP_VERSION(10, 3, 6) || 2315 gc_ver == IP_VERSION(10, 3, 7) || 2316 gc_ver == IP_VERSION(10, 3, 0) || 2317 gc_ver == IP_VERSION(10, 1, 2) || 2318 gc_ver == IP_VERSION(11, 0, 0) || 2319 gc_ver == IP_VERSION(11, 0, 1) || 2320 gc_ver == IP_VERSION(11, 0, 4) || 2321 gc_ver == IP_VERSION(11, 5, 0) || 2322 gc_ver == IP_VERSION(11, 0, 2) || 2323 gc_ver == IP_VERSION(11, 0, 3) || 2324 gc_ver == IP_VERSION(9, 4, 3))) 2325 *states = ATTR_STATE_UNSUPPORTED; 2326 } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { 2327 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2328 gc_ver == IP_VERSION(10, 3, 0) || 2329 gc_ver == IP_VERSION(11, 0, 2) || 2330 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2331 *states = ATTR_STATE_UNSUPPORTED; 2332 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { 2333 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) 2334 *states = ATTR_STATE_UNSUPPORTED; 2335 else if ((gc_ver == IP_VERSION(10, 3, 0) || 2336 gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev)) 2337 *states = ATTR_STATE_UNSUPPORTED; 2338 } else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) { 2339 if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE) 2340 *states = ATTR_STATE_UNSUPPORTED; 2341 } else if (DEVICE_ATTR_IS(pp_mclk_od)) { 2342 if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP) 2343 *states = ATTR_STATE_UNSUPPORTED; 2344 } else if (DEVICE_ATTR_IS(pp_sclk_od)) { 2345 if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP) 2346 *states = ATTR_STATE_UNSUPPORTED; 2347 } else if (DEVICE_ATTR_IS(apu_thermal_cap)) { 2348 u32 limit; 2349 2350 if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) == 2351 -EOPNOTSUPP) 2352 *states = ATTR_STATE_UNSUPPORTED; 2353 } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { 2354 if (gc_ver == IP_VERSION(9, 4, 2) || 2355 gc_ver == IP_VERSION(9, 4, 3)) 2356 *states = ATTR_STATE_UNSUPPORTED; 2357 } 2358 2359 switch (gc_ver) { 2360 case IP_VERSION(9, 4, 1): 2361 case IP_VERSION(9, 4, 2): 2362 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 2363 if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2364 DEVICE_ATTR_IS(pp_dpm_socclk) || 2365 DEVICE_ATTR_IS(pp_dpm_fclk)) { 2366 dev_attr->attr.mode &= ~S_IWUGO; 2367 dev_attr->store = NULL; 2368 } 2369 break; 2370 case IP_VERSION(10, 3, 0): 2371 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) && 2372 amdgpu_sriov_vf(adev)) { 2373 dev_attr->attr.mode &= ~0222; 2374 dev_attr->store = NULL; 2375 } 2376 break; 2377 default: 2378 break; 2379 } 2380 2381 /* setting should not be allowed from VF if not in one VF mode */ 2382 if (amdgpu_sriov_vf(adev) && (!amdgpu_sriov_is_pp_one_vf(adev) || 2383 DEVICE_ATTR_IS(pp_dpm_sclk) || 2384 DEVICE_ATTR_IS(pp_dpm_mclk) || 2385 DEVICE_ATTR_IS(pp_dpm_socclk) || 2386 DEVICE_ATTR_IS(pp_dpm_fclk) || 2387 DEVICE_ATTR_IS(pp_dpm_vclk) || 2388 DEVICE_ATTR_IS(pp_dpm_vclk1) || 2389 DEVICE_ATTR_IS(pp_dpm_dclk) || 2390 DEVICE_ATTR_IS(pp_dpm_dclk1))) { 2391 dev_attr->attr.mode &= ~S_IWUGO; 2392 dev_attr->store = NULL; 2393 } 2394 2395 #undef DEVICE_ATTR_IS 2396 2397 return 0; 2398 } 2399 2400 2401 static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2402 struct amdgpu_device_attr *attr, 2403 uint32_t mask, struct list_head *attr_list) 2404 { 2405 int ret = 0; 2406 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2407 struct amdgpu_device_attr_entry *attr_entry; 2408 struct device_attribute *dev_attr; 2409 const char *name; 2410 2411 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2412 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2413 2414 if (!attr) 2415 return -EINVAL; 2416 2417 dev_attr = &attr->dev_attr; 2418 name = dev_attr->attr.name; 2419 2420 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; 2421 2422 ret = attr_update(adev, attr, mask, &attr_states); 2423 if (ret) { 2424 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2425 name, ret); 2426 return ret; 2427 } 2428 2429 if (attr_states == ATTR_STATE_UNSUPPORTED) 2430 return 0; 2431 2432 ret = device_create_file(adev->dev, dev_attr); 2433 if (ret) { 2434 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2435 name, ret); 2436 } 2437 2438 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2439 if (!attr_entry) 2440 return -ENOMEM; 2441 2442 attr_entry->attr = attr; 2443 INIT_LIST_HEAD(&attr_entry->entry); 2444 2445 list_add_tail(&attr_entry->entry, attr_list); 2446 2447 return ret; 2448 } 2449 2450 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2451 { 2452 struct device_attribute *dev_attr = &attr->dev_attr; 2453 2454 device_remove_file(adev->dev, dev_attr); 2455 } 2456 2457 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2458 struct list_head *attr_list); 2459 2460 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2461 struct amdgpu_device_attr *attrs, 2462 uint32_t counts, 2463 uint32_t mask, 2464 struct list_head *attr_list) 2465 { 2466 int ret = 0; 2467 uint32_t i = 0; 2468 2469 for (i = 0; i < counts; i++) { 2470 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2471 if (ret) 2472 goto failed; 2473 } 2474 2475 return 0; 2476 2477 failed: 2478 amdgpu_device_attr_remove_groups(adev, attr_list); 2479 2480 return ret; 2481 } 2482 2483 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2484 struct list_head *attr_list) 2485 { 2486 struct amdgpu_device_attr_entry *entry, *entry_tmp; 2487 2488 if (list_empty(attr_list)) 2489 return ; 2490 2491 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2492 amdgpu_device_attr_remove(adev, entry->attr); 2493 list_del(&entry->entry); 2494 kfree(entry); 2495 } 2496 } 2497 2498 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2499 struct device_attribute *attr, 2500 char *buf) 2501 { 2502 struct amdgpu_device *adev = dev_get_drvdata(dev); 2503 int channel = to_sensor_dev_attr(attr)->index; 2504 int r, temp = 0; 2505 2506 if (channel >= PP_TEMP_MAX) 2507 return -EINVAL; 2508 2509 switch (channel) { 2510 case PP_TEMP_JUNCTION: 2511 /* get current junction temperature */ 2512 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2513 (void *)&temp); 2514 break; 2515 case PP_TEMP_EDGE: 2516 /* get current edge temperature */ 2517 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2518 (void *)&temp); 2519 break; 2520 case PP_TEMP_MEM: 2521 /* get current memory temperature */ 2522 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2523 (void *)&temp); 2524 break; 2525 default: 2526 r = -EINVAL; 2527 break; 2528 } 2529 2530 if (r) 2531 return r; 2532 2533 return sysfs_emit(buf, "%d\n", temp); 2534 } 2535 2536 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2537 struct device_attribute *attr, 2538 char *buf) 2539 { 2540 struct amdgpu_device *adev = dev_get_drvdata(dev); 2541 int hyst = to_sensor_dev_attr(attr)->index; 2542 int temp; 2543 2544 if (hyst) 2545 temp = adev->pm.dpm.thermal.min_temp; 2546 else 2547 temp = adev->pm.dpm.thermal.max_temp; 2548 2549 return sysfs_emit(buf, "%d\n", temp); 2550 } 2551 2552 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2553 struct device_attribute *attr, 2554 char *buf) 2555 { 2556 struct amdgpu_device *adev = dev_get_drvdata(dev); 2557 int hyst = to_sensor_dev_attr(attr)->index; 2558 int temp; 2559 2560 if (hyst) 2561 temp = adev->pm.dpm.thermal.min_hotspot_temp; 2562 else 2563 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2564 2565 return sysfs_emit(buf, "%d\n", temp); 2566 } 2567 2568 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2569 struct device_attribute *attr, 2570 char *buf) 2571 { 2572 struct amdgpu_device *adev = dev_get_drvdata(dev); 2573 int hyst = to_sensor_dev_attr(attr)->index; 2574 int temp; 2575 2576 if (hyst) 2577 temp = adev->pm.dpm.thermal.min_mem_temp; 2578 else 2579 temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2580 2581 return sysfs_emit(buf, "%d\n", temp); 2582 } 2583 2584 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2585 struct device_attribute *attr, 2586 char *buf) 2587 { 2588 int channel = to_sensor_dev_attr(attr)->index; 2589 2590 if (channel >= PP_TEMP_MAX) 2591 return -EINVAL; 2592 2593 return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2594 } 2595 2596 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2597 struct device_attribute *attr, 2598 char *buf) 2599 { 2600 struct amdgpu_device *adev = dev_get_drvdata(dev); 2601 int channel = to_sensor_dev_attr(attr)->index; 2602 int temp = 0; 2603 2604 if (channel >= PP_TEMP_MAX) 2605 return -EINVAL; 2606 2607 switch (channel) { 2608 case PP_TEMP_JUNCTION: 2609 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2610 break; 2611 case PP_TEMP_EDGE: 2612 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2613 break; 2614 case PP_TEMP_MEM: 2615 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2616 break; 2617 } 2618 2619 return sysfs_emit(buf, "%d\n", temp); 2620 } 2621 2622 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2623 struct device_attribute *attr, 2624 char *buf) 2625 { 2626 struct amdgpu_device *adev = dev_get_drvdata(dev); 2627 u32 pwm_mode = 0; 2628 int ret; 2629 2630 if (amdgpu_in_reset(adev)) 2631 return -EPERM; 2632 if (adev->in_suspend && !adev->in_runpm) 2633 return -EPERM; 2634 2635 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2636 if (ret < 0) { 2637 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2638 return ret; 2639 } 2640 2641 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2642 2643 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2644 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2645 2646 if (ret) 2647 return -EINVAL; 2648 2649 return sysfs_emit(buf, "%u\n", pwm_mode); 2650 } 2651 2652 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2653 struct device_attribute *attr, 2654 const char *buf, 2655 size_t count) 2656 { 2657 struct amdgpu_device *adev = dev_get_drvdata(dev); 2658 int err, ret; 2659 u32 pwm_mode; 2660 int value; 2661 2662 if (amdgpu_in_reset(adev)) 2663 return -EPERM; 2664 if (adev->in_suspend && !adev->in_runpm) 2665 return -EPERM; 2666 2667 err = kstrtoint(buf, 10, &value); 2668 if (err) 2669 return err; 2670 2671 if (value == 0) 2672 pwm_mode = AMD_FAN_CTRL_NONE; 2673 else if (value == 1) 2674 pwm_mode = AMD_FAN_CTRL_MANUAL; 2675 else if (value == 2) 2676 pwm_mode = AMD_FAN_CTRL_AUTO; 2677 else 2678 return -EINVAL; 2679 2680 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2681 if (ret < 0) { 2682 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2683 return ret; 2684 } 2685 2686 ret = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2687 2688 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2689 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2690 2691 if (ret) 2692 return -EINVAL; 2693 2694 return count; 2695 } 2696 2697 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2698 struct device_attribute *attr, 2699 char *buf) 2700 { 2701 return sysfs_emit(buf, "%i\n", 0); 2702 } 2703 2704 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2705 struct device_attribute *attr, 2706 char *buf) 2707 { 2708 return sysfs_emit(buf, "%i\n", 255); 2709 } 2710 2711 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2712 struct device_attribute *attr, 2713 const char *buf, size_t count) 2714 { 2715 struct amdgpu_device *adev = dev_get_drvdata(dev); 2716 int err; 2717 u32 value; 2718 u32 pwm_mode; 2719 2720 if (amdgpu_in_reset(adev)) 2721 return -EPERM; 2722 if (adev->in_suspend && !adev->in_runpm) 2723 return -EPERM; 2724 2725 err = kstrtou32(buf, 10, &value); 2726 if (err) 2727 return err; 2728 2729 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2730 if (err < 0) { 2731 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2732 return err; 2733 } 2734 2735 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2736 if (err) 2737 goto out; 2738 2739 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2740 pr_info("manual fan speed control should be enabled first\n"); 2741 err = -EINVAL; 2742 goto out; 2743 } 2744 2745 err = amdgpu_dpm_set_fan_speed_pwm(adev, value); 2746 2747 out: 2748 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2749 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2750 2751 if (err) 2752 return err; 2753 2754 return count; 2755 } 2756 2757 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2758 struct device_attribute *attr, 2759 char *buf) 2760 { 2761 struct amdgpu_device *adev = dev_get_drvdata(dev); 2762 int err; 2763 u32 speed = 0; 2764 2765 if (amdgpu_in_reset(adev)) 2766 return -EPERM; 2767 if (adev->in_suspend && !adev->in_runpm) 2768 return -EPERM; 2769 2770 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2771 if (err < 0) { 2772 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2773 return err; 2774 } 2775 2776 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); 2777 2778 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2779 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2780 2781 if (err) 2782 return err; 2783 2784 return sysfs_emit(buf, "%i\n", speed); 2785 } 2786 2787 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2788 struct device_attribute *attr, 2789 char *buf) 2790 { 2791 struct amdgpu_device *adev = dev_get_drvdata(dev); 2792 int err; 2793 u32 speed = 0; 2794 2795 if (amdgpu_in_reset(adev)) 2796 return -EPERM; 2797 if (adev->in_suspend && !adev->in_runpm) 2798 return -EPERM; 2799 2800 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2801 if (err < 0) { 2802 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2803 return err; 2804 } 2805 2806 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2807 2808 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2809 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2810 2811 if (err) 2812 return err; 2813 2814 return sysfs_emit(buf, "%i\n", speed); 2815 } 2816 2817 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2818 struct device_attribute *attr, 2819 char *buf) 2820 { 2821 struct amdgpu_device *adev = dev_get_drvdata(dev); 2822 u32 min_rpm = 0; 2823 int r; 2824 2825 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2826 (void *)&min_rpm); 2827 2828 if (r) 2829 return r; 2830 2831 return sysfs_emit(buf, "%d\n", min_rpm); 2832 } 2833 2834 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2835 struct device_attribute *attr, 2836 char *buf) 2837 { 2838 struct amdgpu_device *adev = dev_get_drvdata(dev); 2839 u32 max_rpm = 0; 2840 int r; 2841 2842 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2843 (void *)&max_rpm); 2844 2845 if (r) 2846 return r; 2847 2848 return sysfs_emit(buf, "%d\n", max_rpm); 2849 } 2850 2851 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2852 struct device_attribute *attr, 2853 char *buf) 2854 { 2855 struct amdgpu_device *adev = dev_get_drvdata(dev); 2856 int err; 2857 u32 rpm = 0; 2858 2859 if (amdgpu_in_reset(adev)) 2860 return -EPERM; 2861 if (adev->in_suspend && !adev->in_runpm) 2862 return -EPERM; 2863 2864 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2865 if (err < 0) { 2866 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2867 return err; 2868 } 2869 2870 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2871 2872 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2873 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2874 2875 if (err) 2876 return err; 2877 2878 return sysfs_emit(buf, "%i\n", rpm); 2879 } 2880 2881 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2882 struct device_attribute *attr, 2883 const char *buf, size_t count) 2884 { 2885 struct amdgpu_device *adev = dev_get_drvdata(dev); 2886 int err; 2887 u32 value; 2888 u32 pwm_mode; 2889 2890 if (amdgpu_in_reset(adev)) 2891 return -EPERM; 2892 if (adev->in_suspend && !adev->in_runpm) 2893 return -EPERM; 2894 2895 err = kstrtou32(buf, 10, &value); 2896 if (err) 2897 return err; 2898 2899 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2900 if (err < 0) { 2901 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2902 return err; 2903 } 2904 2905 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2906 if (err) 2907 goto out; 2908 2909 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2910 err = -ENODATA; 2911 goto out; 2912 } 2913 2914 err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2915 2916 out: 2917 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2918 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2919 2920 if (err) 2921 return err; 2922 2923 return count; 2924 } 2925 2926 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2927 struct device_attribute *attr, 2928 char *buf) 2929 { 2930 struct amdgpu_device *adev = dev_get_drvdata(dev); 2931 u32 pwm_mode = 0; 2932 int ret; 2933 2934 if (amdgpu_in_reset(adev)) 2935 return -EPERM; 2936 if (adev->in_suspend && !adev->in_runpm) 2937 return -EPERM; 2938 2939 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2940 if (ret < 0) { 2941 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2942 return ret; 2943 } 2944 2945 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2946 2947 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2948 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2949 2950 if (ret) 2951 return -EINVAL; 2952 2953 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2954 } 2955 2956 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2957 struct device_attribute *attr, 2958 const char *buf, 2959 size_t count) 2960 { 2961 struct amdgpu_device *adev = dev_get_drvdata(dev); 2962 int err; 2963 int value; 2964 u32 pwm_mode; 2965 2966 if (amdgpu_in_reset(adev)) 2967 return -EPERM; 2968 if (adev->in_suspend && !adev->in_runpm) 2969 return -EPERM; 2970 2971 err = kstrtoint(buf, 10, &value); 2972 if (err) 2973 return err; 2974 2975 if (value == 0) 2976 pwm_mode = AMD_FAN_CTRL_AUTO; 2977 else if (value == 1) 2978 pwm_mode = AMD_FAN_CTRL_MANUAL; 2979 else 2980 return -EINVAL; 2981 2982 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2983 if (err < 0) { 2984 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2985 return err; 2986 } 2987 2988 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2989 2990 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2991 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2992 2993 if (err) 2994 return -EINVAL; 2995 2996 return count; 2997 } 2998 2999 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 3000 struct device_attribute *attr, 3001 char *buf) 3002 { 3003 struct amdgpu_device *adev = dev_get_drvdata(dev); 3004 u32 vddgfx; 3005 int r; 3006 3007 /* get the voltage */ 3008 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX, 3009 (void *)&vddgfx); 3010 if (r) 3011 return r; 3012 3013 return sysfs_emit(buf, "%d\n", vddgfx); 3014 } 3015 3016 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 3017 struct device_attribute *attr, 3018 char *buf) 3019 { 3020 return sysfs_emit(buf, "vddgfx\n"); 3021 } 3022 3023 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 3024 struct device_attribute *attr, 3025 char *buf) 3026 { 3027 struct amdgpu_device *adev = dev_get_drvdata(dev); 3028 u32 vddnb; 3029 int r; 3030 3031 /* only APUs have vddnb */ 3032 if (!(adev->flags & AMD_IS_APU)) 3033 return -EINVAL; 3034 3035 /* get the voltage */ 3036 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB, 3037 (void *)&vddnb); 3038 if (r) 3039 return r; 3040 3041 return sysfs_emit(buf, "%d\n", vddnb); 3042 } 3043 3044 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 3045 struct device_attribute *attr, 3046 char *buf) 3047 { 3048 return sysfs_emit(buf, "vddnb\n"); 3049 } 3050 3051 static int amdgpu_hwmon_get_power(struct device *dev, 3052 enum amd_pp_sensors sensor) 3053 { 3054 struct amdgpu_device *adev = dev_get_drvdata(dev); 3055 unsigned int uw; 3056 u32 query = 0; 3057 int r; 3058 3059 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query); 3060 if (r) 3061 return r; 3062 3063 /* convert to microwatts */ 3064 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 3065 3066 return uw; 3067 } 3068 3069 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 3070 struct device_attribute *attr, 3071 char *buf) 3072 { 3073 ssize_t val; 3074 3075 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER); 3076 if (val < 0) 3077 return val; 3078 3079 return sysfs_emit(buf, "%zd\n", val); 3080 } 3081 3082 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev, 3083 struct device_attribute *attr, 3084 char *buf) 3085 { 3086 ssize_t val; 3087 3088 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER); 3089 if (val < 0) 3090 return val; 3091 3092 return sysfs_emit(buf, "%zd\n", val); 3093 } 3094 3095 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, 3096 struct device_attribute *attr, 3097 char *buf, 3098 enum pp_power_limit_level pp_limit_level) 3099 { 3100 struct amdgpu_device *adev = dev_get_drvdata(dev); 3101 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; 3102 uint32_t limit; 3103 ssize_t size; 3104 int r; 3105 3106 if (amdgpu_in_reset(adev)) 3107 return -EPERM; 3108 if (adev->in_suspend && !adev->in_runpm) 3109 return -EPERM; 3110 3111 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3112 if (r < 0) { 3113 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3114 return r; 3115 } 3116 3117 r = amdgpu_dpm_get_power_limit(adev, &limit, 3118 pp_limit_level, power_type); 3119 3120 if (!r) 3121 size = sysfs_emit(buf, "%u\n", limit * 1000000); 3122 else 3123 size = sysfs_emit(buf, "\n"); 3124 3125 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3126 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3127 3128 return size; 3129 } 3130 3131 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 3132 struct device_attribute *attr, 3133 char *buf) 3134 { 3135 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN); 3136 } 3137 3138 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 3139 struct device_attribute *attr, 3140 char *buf) 3141 { 3142 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); 3143 3144 } 3145 3146 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 3147 struct device_attribute *attr, 3148 char *buf) 3149 { 3150 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); 3151 3152 } 3153 3154 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 3155 struct device_attribute *attr, 3156 char *buf) 3157 { 3158 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); 3159 3160 } 3161 3162 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 3163 struct device_attribute *attr, 3164 char *buf) 3165 { 3166 struct amdgpu_device *adev = dev_get_drvdata(dev); 3167 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 3168 3169 if (gc_ver == IP_VERSION(10, 3, 1)) 3170 return sysfs_emit(buf, "%s\n", 3171 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? 3172 "fastPPT" : "slowPPT"); 3173 else 3174 return sysfs_emit(buf, "PPT\n"); 3175 } 3176 3177 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 3178 struct device_attribute *attr, 3179 const char *buf, 3180 size_t count) 3181 { 3182 struct amdgpu_device *adev = dev_get_drvdata(dev); 3183 int limit_type = to_sensor_dev_attr(attr)->index; 3184 int err; 3185 u32 value; 3186 3187 if (amdgpu_in_reset(adev)) 3188 return -EPERM; 3189 if (adev->in_suspend && !adev->in_runpm) 3190 return -EPERM; 3191 3192 if (amdgpu_sriov_vf(adev)) 3193 return -EINVAL; 3194 3195 err = kstrtou32(buf, 10, &value); 3196 if (err) 3197 return err; 3198 3199 value = value / 1000000; /* convert to Watt */ 3200 value |= limit_type << 24; 3201 3202 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3203 if (err < 0) { 3204 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3205 return err; 3206 } 3207 3208 err = amdgpu_dpm_set_power_limit(adev, value); 3209 3210 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3211 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3212 3213 if (err) 3214 return err; 3215 3216 return count; 3217 } 3218 3219 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 3220 struct device_attribute *attr, 3221 char *buf) 3222 { 3223 struct amdgpu_device *adev = dev_get_drvdata(dev); 3224 uint32_t sclk; 3225 int r; 3226 3227 /* get the sclk */ 3228 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 3229 (void *)&sclk); 3230 if (r) 3231 return r; 3232 3233 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 3234 } 3235 3236 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 3237 struct device_attribute *attr, 3238 char *buf) 3239 { 3240 return sysfs_emit(buf, "sclk\n"); 3241 } 3242 3243 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 3244 struct device_attribute *attr, 3245 char *buf) 3246 { 3247 struct amdgpu_device *adev = dev_get_drvdata(dev); 3248 uint32_t mclk; 3249 int r; 3250 3251 /* get the sclk */ 3252 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 3253 (void *)&mclk); 3254 if (r) 3255 return r; 3256 3257 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 3258 } 3259 3260 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 3261 struct device_attribute *attr, 3262 char *buf) 3263 { 3264 return sysfs_emit(buf, "mclk\n"); 3265 } 3266 3267 /** 3268 * DOC: hwmon 3269 * 3270 * The amdgpu driver exposes the following sensor interfaces: 3271 * 3272 * - GPU temperature (via the on-die sensor) 3273 * 3274 * - GPU voltage 3275 * 3276 * - Northbridge voltage (APUs only) 3277 * 3278 * - GPU power 3279 * 3280 * - GPU fan 3281 * 3282 * - GPU gfx/compute engine clock 3283 * 3284 * - GPU memory clock (dGPU only) 3285 * 3286 * hwmon interfaces for GPU temperature: 3287 * 3288 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3289 * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3290 * 3291 * - temp[1-3]_label: temperature channel label 3292 * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3293 * 3294 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3295 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3296 * 3297 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3298 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3299 * 3300 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3301 * - these are supported on SOC15 dGPUs only 3302 * 3303 * hwmon interfaces for GPU voltage: 3304 * 3305 * - in0_input: the voltage on the GPU in millivolts 3306 * 3307 * - in1_input: the voltage on the Northbridge in millivolts 3308 * 3309 * hwmon interfaces for GPU power: 3310 * 3311 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. 3312 * 3313 * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU. 3314 * 3315 * - power1_cap_min: minimum cap supported in microWatts 3316 * 3317 * - power1_cap_max: maximum cap supported in microWatts 3318 * 3319 * - power1_cap: selected power cap in microWatts 3320 * 3321 * hwmon interfaces for GPU fan: 3322 * 3323 * - pwm1: pulse width modulation fan level (0-255) 3324 * 3325 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3326 * 3327 * - pwm1_min: pulse width modulation fan control minimum level (0) 3328 * 3329 * - pwm1_max: pulse width modulation fan control maximum level (255) 3330 * 3331 * - fan1_min: a minimum value Unit: revolution/min (RPM) 3332 * 3333 * - fan1_max: a maximum value Unit: revolution/max (RPM) 3334 * 3335 * - fan1_input: fan speed in RPM 3336 * 3337 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3338 * 3339 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3340 * 3341 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. 3342 * That will get the former one overridden. 3343 * 3344 * hwmon interfaces for GPU clocks: 3345 * 3346 * - freq1_input: the gfx/compute clock in hertz 3347 * 3348 * - freq2_input: the memory clock in hertz 3349 * 3350 * You can use hwmon tools like sensors to view this information on your system. 3351 * 3352 */ 3353 3354 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3355 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3356 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3357 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3358 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3359 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3360 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3361 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3362 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3363 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3364 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3365 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3366 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3367 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3368 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3369 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3370 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3371 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3372 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3373 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3374 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3375 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3376 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3377 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3378 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3379 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3380 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3381 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3382 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3383 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0); 3384 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3385 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3386 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3387 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3388 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3389 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3390 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3391 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3392 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 3393 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3394 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3395 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3396 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3397 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3398 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3399 3400 static struct attribute *hwmon_attributes[] = { 3401 &sensor_dev_attr_temp1_input.dev_attr.attr, 3402 &sensor_dev_attr_temp1_crit.dev_attr.attr, 3403 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3404 &sensor_dev_attr_temp2_input.dev_attr.attr, 3405 &sensor_dev_attr_temp2_crit.dev_attr.attr, 3406 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3407 &sensor_dev_attr_temp3_input.dev_attr.attr, 3408 &sensor_dev_attr_temp3_crit.dev_attr.attr, 3409 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3410 &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3411 &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3412 &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3413 &sensor_dev_attr_temp1_label.dev_attr.attr, 3414 &sensor_dev_attr_temp2_label.dev_attr.attr, 3415 &sensor_dev_attr_temp3_label.dev_attr.attr, 3416 &sensor_dev_attr_pwm1.dev_attr.attr, 3417 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3418 &sensor_dev_attr_pwm1_min.dev_attr.attr, 3419 &sensor_dev_attr_pwm1_max.dev_attr.attr, 3420 &sensor_dev_attr_fan1_input.dev_attr.attr, 3421 &sensor_dev_attr_fan1_min.dev_attr.attr, 3422 &sensor_dev_attr_fan1_max.dev_attr.attr, 3423 &sensor_dev_attr_fan1_target.dev_attr.attr, 3424 &sensor_dev_attr_fan1_enable.dev_attr.attr, 3425 &sensor_dev_attr_in0_input.dev_attr.attr, 3426 &sensor_dev_attr_in0_label.dev_attr.attr, 3427 &sensor_dev_attr_in1_input.dev_attr.attr, 3428 &sensor_dev_attr_in1_label.dev_attr.attr, 3429 &sensor_dev_attr_power1_average.dev_attr.attr, 3430 &sensor_dev_attr_power1_input.dev_attr.attr, 3431 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3432 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3433 &sensor_dev_attr_power1_cap.dev_attr.attr, 3434 &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3435 &sensor_dev_attr_power1_label.dev_attr.attr, 3436 &sensor_dev_attr_power2_average.dev_attr.attr, 3437 &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3438 &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3439 &sensor_dev_attr_power2_cap.dev_attr.attr, 3440 &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3441 &sensor_dev_attr_power2_label.dev_attr.attr, 3442 &sensor_dev_attr_freq1_input.dev_attr.attr, 3443 &sensor_dev_attr_freq1_label.dev_attr.attr, 3444 &sensor_dev_attr_freq2_input.dev_attr.attr, 3445 &sensor_dev_attr_freq2_label.dev_attr.attr, 3446 NULL 3447 }; 3448 3449 static umode_t hwmon_attributes_visible(struct kobject *kobj, 3450 struct attribute *attr, int index) 3451 { 3452 struct device *dev = kobj_to_dev(kobj); 3453 struct amdgpu_device *adev = dev_get_drvdata(dev); 3454 umode_t effective_mode = attr->mode; 3455 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 3456 uint32_t tmp; 3457 3458 /* under pp one vf mode manage of hwmon attributes is not supported */ 3459 if (amdgpu_sriov_is_pp_one_vf(adev)) 3460 effective_mode &= ~S_IWUSR; 3461 3462 /* Skip fan attributes if fan is not present */ 3463 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3464 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3465 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3466 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3467 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3468 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3469 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3470 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3471 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3472 return 0; 3473 3474 /* Skip fan attributes on APU */ 3475 if ((adev->flags & AMD_IS_APU) && 3476 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3477 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3478 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3479 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3480 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3481 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3482 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3483 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3484 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3485 return 0; 3486 3487 /* Skip crit temp on APU */ 3488 if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || 3489 (gc_ver == IP_VERSION(9, 4, 3))) && 3490 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3491 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3492 return 0; 3493 3494 /* Skip limit attributes if DPM is not enabled */ 3495 if (!adev->pm.dpm_enabled && 3496 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3497 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3498 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3499 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3500 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3501 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3502 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3503 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3504 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3505 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3506 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3507 return 0; 3508 3509 /* mask fan attributes if we have no bindings for this asic to expose */ 3510 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3511 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3512 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && 3513 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3514 effective_mode &= ~S_IRUGO; 3515 3516 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3517 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3518 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && 3519 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3520 effective_mode &= ~S_IWUSR; 3521 3522 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ 3523 if (((adev->family == AMDGPU_FAMILY_SI) || 3524 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && 3525 (gc_ver != IP_VERSION(9, 4, 3)))) && 3526 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3527 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3528 attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3529 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3530 return 0; 3531 3532 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ 3533 if (((adev->family == AMDGPU_FAMILY_SI) || 3534 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && 3535 (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3536 return 0; 3537 3538 /* not all products support both average and instantaneous */ 3539 if (attr == &sensor_dev_attr_power1_average.dev_attr.attr && 3540 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP) 3541 return 0; 3542 if (attr == &sensor_dev_attr_power1_input.dev_attr.attr && 3543 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP) 3544 return 0; 3545 3546 /* hide max/min values if we can't both query and manage the fan */ 3547 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3548 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3549 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3550 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && 3551 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3552 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3553 return 0; 3554 3555 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3556 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && 3557 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3558 attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3559 return 0; 3560 3561 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3562 adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ 3563 (gc_ver == IP_VERSION(9, 4, 3))) && 3564 (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3565 attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3566 return 0; 3567 3568 /* only APUs other than gc 9,4,3 have vddnb */ 3569 if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) && 3570 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3571 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3572 return 0; 3573 3574 /* no mclk on APUs other than gc 9,4,3*/ 3575 if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) && 3576 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3577 attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3578 return 0; 3579 3580 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3581 (gc_ver != IP_VERSION(9, 4, 3)) && 3582 (attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3583 attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3584 attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3585 attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3586 attr == &sensor_dev_attr_temp3_label.dev_attr.attr || 3587 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr)) 3588 return 0; 3589 3590 /* hotspot temperature for gc 9,4,3*/ 3591 if (gc_ver == IP_VERSION(9, 4, 3)) { 3592 if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr || 3593 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3594 attr == &sensor_dev_attr_temp1_label.dev_attr.attr) 3595 return 0; 3596 3597 if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3598 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr) 3599 return attr->mode; 3600 } 3601 3602 /* only SOC15 dGPUs support hotspot and mem temperatures */ 3603 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3604 (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3605 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3606 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3607 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3608 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)) 3609 return 0; 3610 3611 /* only Vangogh has fast PPT limit and power labels */ 3612 if (!(gc_ver == IP_VERSION(10, 3, 1)) && 3613 (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3614 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3615 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3616 attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 3617 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3618 attr == &sensor_dev_attr_power2_label.dev_attr.attr)) 3619 return 0; 3620 3621 return effective_mode; 3622 } 3623 3624 static const struct attribute_group hwmon_attrgroup = { 3625 .attrs = hwmon_attributes, 3626 .is_visible = hwmon_attributes_visible, 3627 }; 3628 3629 static const struct attribute_group *hwmon_groups[] = { 3630 &hwmon_attrgroup, 3631 NULL 3632 }; 3633 3634 static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev, 3635 enum pp_clock_type od_type, 3636 char *buf) 3637 { 3638 int size = 0; 3639 int ret; 3640 3641 if (amdgpu_in_reset(adev)) 3642 return -EPERM; 3643 if (adev->in_suspend && !adev->in_runpm) 3644 return -EPERM; 3645 3646 ret = pm_runtime_get_sync(adev->dev); 3647 if (ret < 0) { 3648 pm_runtime_put_autosuspend(adev->dev); 3649 return ret; 3650 } 3651 3652 size = amdgpu_dpm_print_clock_levels(adev, od_type, buf); 3653 if (size == 0) 3654 size = sysfs_emit(buf, "\n"); 3655 3656 pm_runtime_mark_last_busy(adev->dev); 3657 pm_runtime_put_autosuspend(adev->dev); 3658 3659 return size; 3660 } 3661 3662 static int parse_input_od_command_lines(const char *buf, 3663 size_t count, 3664 u32 *type, 3665 long *params, 3666 uint32_t *num_of_params) 3667 { 3668 const char delimiter[3] = {' ', '\n', '\0'}; 3669 uint32_t parameter_size = 0; 3670 char buf_cpy[128] = {0}; 3671 char *tmp_str, *sub_str; 3672 int ret; 3673 3674 if (count > sizeof(buf_cpy) - 1) 3675 return -EINVAL; 3676 3677 memcpy(buf_cpy, buf, count); 3678 tmp_str = buf_cpy; 3679 3680 /* skip heading spaces */ 3681 while (isspace(*tmp_str)) 3682 tmp_str++; 3683 3684 switch (*tmp_str) { 3685 case 'c': 3686 *type = PP_OD_COMMIT_DPM_TABLE; 3687 return 0; 3688 case 'r': 3689 params[parameter_size] = *type; 3690 *num_of_params = 1; 3691 *type = PP_OD_RESTORE_DEFAULT_TABLE; 3692 return 0; 3693 default: 3694 break; 3695 } 3696 3697 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 3698 if (strlen(sub_str) == 0) 3699 continue; 3700 3701 ret = kstrtol(sub_str, 0, ¶ms[parameter_size]); 3702 if (ret) 3703 return -EINVAL; 3704 parameter_size++; 3705 3706 while (isspace(*tmp_str)) 3707 tmp_str++; 3708 } 3709 3710 *num_of_params = parameter_size; 3711 3712 return 0; 3713 } 3714 3715 static int 3716 amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev, 3717 enum PP_OD_DPM_TABLE_COMMAND cmd_type, 3718 const char *in_buf, 3719 size_t count) 3720 { 3721 uint32_t parameter_size = 0; 3722 long parameter[64]; 3723 int ret; 3724 3725 if (amdgpu_in_reset(adev)) 3726 return -EPERM; 3727 if (adev->in_suspend && !adev->in_runpm) 3728 return -EPERM; 3729 3730 ret = parse_input_od_command_lines(in_buf, 3731 count, 3732 &cmd_type, 3733 parameter, 3734 ¶meter_size); 3735 if (ret) 3736 return ret; 3737 3738 ret = pm_runtime_get_sync(adev->dev); 3739 if (ret < 0) 3740 goto err_out0; 3741 3742 ret = amdgpu_dpm_odn_edit_dpm_table(adev, 3743 cmd_type, 3744 parameter, 3745 parameter_size); 3746 if (ret) 3747 goto err_out1; 3748 3749 if (cmd_type == PP_OD_COMMIT_DPM_TABLE) { 3750 ret = amdgpu_dpm_dispatch_task(adev, 3751 AMD_PP_TASK_READJUST_POWER_STATE, 3752 NULL); 3753 if (ret) 3754 goto err_out1; 3755 } 3756 3757 pm_runtime_mark_last_busy(adev->dev); 3758 pm_runtime_put_autosuspend(adev->dev); 3759 3760 return count; 3761 3762 err_out1: 3763 pm_runtime_mark_last_busy(adev->dev); 3764 err_out0: 3765 pm_runtime_put_autosuspend(adev->dev); 3766 3767 return ret; 3768 } 3769 3770 /** 3771 * DOC: fan_curve 3772 * 3773 * The amdgpu driver provides a sysfs API for checking and adjusting the fan 3774 * control curve line. 3775 * 3776 * Reading back the file shows you the current settings(temperature in Celsius 3777 * degree and fan speed in pwm) applied to every anchor point of the curve line 3778 * and their permitted ranges if changable. 3779 * 3780 * Writing a desired string(with the format like "anchor_point_index temperature 3781 * fan_speed_in_pwm") to the file, change the settings for the specific anchor 3782 * point accordingly. 3783 * 3784 * When you have finished the editing, write "c" (commit) to the file to commit 3785 * your changes. 3786 * 3787 * If you want to reset to the default value, write "r" (reset) to the file to 3788 * reset them 3789 * 3790 * There are two fan control modes supported: auto and manual. With auto mode, 3791 * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature). 3792 * While with manual mode, users can set their own fan curve line as what 3793 * described here. Normally the ASIC is booted up with auto mode. Any 3794 * settings via this interface will switch the fan control to manual mode 3795 * implicitly. 3796 */ 3797 static ssize_t fan_curve_show(struct kobject *kobj, 3798 struct kobj_attribute *attr, 3799 char *buf) 3800 { 3801 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3802 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3803 3804 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf); 3805 } 3806 3807 static ssize_t fan_curve_store(struct kobject *kobj, 3808 struct kobj_attribute *attr, 3809 const char *buf, 3810 size_t count) 3811 { 3812 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3813 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3814 3815 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3816 PP_OD_EDIT_FAN_CURVE, 3817 buf, 3818 count); 3819 } 3820 3821 static umode_t fan_curve_visible(struct amdgpu_device *adev) 3822 { 3823 umode_t umode = 0000; 3824 3825 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE) 3826 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3827 3828 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET) 3829 umode |= S_IWUSR; 3830 3831 return umode; 3832 } 3833 3834 /** 3835 * DOC: acoustic_limit_rpm_threshold 3836 * 3837 * The amdgpu driver provides a sysfs API for checking and adjusting the 3838 * acoustic limit in RPM for fan control. 3839 * 3840 * Reading back the file shows you the current setting and the permitted 3841 * ranges if changable. 3842 * 3843 * Writing an integer to the file, change the setting accordingly. 3844 * 3845 * When you have finished the editing, write "c" (commit) to the file to commit 3846 * your changes. 3847 * 3848 * If you want to reset to the default value, write "r" (reset) to the file to 3849 * reset them 3850 * 3851 * This setting works under auto fan control mode only. It adjusts the PMFW's 3852 * behavior about the maximum speed in RPM the fan can spin. Setting via this 3853 * interface will switch the fan control to auto mode implicitly. 3854 */ 3855 static ssize_t acoustic_limit_threshold_show(struct kobject *kobj, 3856 struct kobj_attribute *attr, 3857 char *buf) 3858 { 3859 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3860 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3861 3862 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf); 3863 } 3864 3865 static ssize_t acoustic_limit_threshold_store(struct kobject *kobj, 3866 struct kobj_attribute *attr, 3867 const char *buf, 3868 size_t count) 3869 { 3870 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3871 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3872 3873 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3874 PP_OD_EDIT_ACOUSTIC_LIMIT, 3875 buf, 3876 count); 3877 } 3878 3879 static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev) 3880 { 3881 umode_t umode = 0000; 3882 3883 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE) 3884 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3885 3886 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET) 3887 umode |= S_IWUSR; 3888 3889 return umode; 3890 } 3891 3892 /** 3893 * DOC: acoustic_target_rpm_threshold 3894 * 3895 * The amdgpu driver provides a sysfs API for checking and adjusting the 3896 * acoustic target in RPM for fan control. 3897 * 3898 * Reading back the file shows you the current setting and the permitted 3899 * ranges if changable. 3900 * 3901 * Writing an integer to the file, change the setting accordingly. 3902 * 3903 * When you have finished the editing, write "c" (commit) to the file to commit 3904 * your changes. 3905 * 3906 * If you want to reset to the default value, write "r" (reset) to the file to 3907 * reset them 3908 * 3909 * This setting works under auto fan control mode only. It can co-exist with 3910 * other settings which can work also under auto mode. It adjusts the PMFW's 3911 * behavior about the maximum speed in RPM the fan can spin when ASIC 3912 * temperature is not greater than target temperature. Setting via this 3913 * interface will switch the fan control to auto mode implicitly. 3914 */ 3915 static ssize_t acoustic_target_threshold_show(struct kobject *kobj, 3916 struct kobj_attribute *attr, 3917 char *buf) 3918 { 3919 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3920 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3921 3922 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf); 3923 } 3924 3925 static ssize_t acoustic_target_threshold_store(struct kobject *kobj, 3926 struct kobj_attribute *attr, 3927 const char *buf, 3928 size_t count) 3929 { 3930 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3931 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3932 3933 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3934 PP_OD_EDIT_ACOUSTIC_TARGET, 3935 buf, 3936 count); 3937 } 3938 3939 static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev) 3940 { 3941 umode_t umode = 0000; 3942 3943 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE) 3944 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3945 3946 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET) 3947 umode |= S_IWUSR; 3948 3949 return umode; 3950 } 3951 3952 /** 3953 * DOC: fan_target_temperature 3954 * 3955 * The amdgpu driver provides a sysfs API for checking and adjusting the 3956 * target tempeature in Celsius degree for fan control. 3957 * 3958 * Reading back the file shows you the current setting and the permitted 3959 * ranges if changable. 3960 * 3961 * Writing an integer to the file, change the setting accordingly. 3962 * 3963 * When you have finished the editing, write "c" (commit) to the file to commit 3964 * your changes. 3965 * 3966 * If you want to reset to the default value, write "r" (reset) to the file to 3967 * reset them 3968 * 3969 * This setting works under auto fan control mode only. It can co-exist with 3970 * other settings which can work also under auto mode. Paring with the 3971 * acoustic_target_rpm_threshold setting, they define the maximum speed in 3972 * RPM the fan can spin when ASIC temperature is not greater than target 3973 * temperature. Setting via this interface will switch the fan control to 3974 * auto mode implicitly. 3975 */ 3976 static ssize_t fan_target_temperature_show(struct kobject *kobj, 3977 struct kobj_attribute *attr, 3978 char *buf) 3979 { 3980 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3981 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3982 3983 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf); 3984 } 3985 3986 static ssize_t fan_target_temperature_store(struct kobject *kobj, 3987 struct kobj_attribute *attr, 3988 const char *buf, 3989 size_t count) 3990 { 3991 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3992 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3993 3994 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3995 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 3996 buf, 3997 count); 3998 } 3999 4000 static umode_t fan_target_temperature_visible(struct amdgpu_device *adev) 4001 { 4002 umode_t umode = 0000; 4003 4004 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE) 4005 umode |= S_IRUSR | S_IRGRP | S_IROTH; 4006 4007 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET) 4008 umode |= S_IWUSR; 4009 4010 return umode; 4011 } 4012 4013 /** 4014 * DOC: fan_minimum_pwm 4015 * 4016 * The amdgpu driver provides a sysfs API for checking and adjusting the 4017 * minimum fan speed in PWM. 4018 * 4019 * Reading back the file shows you the current setting and the permitted 4020 * ranges if changable. 4021 * 4022 * Writing an integer to the file, change the setting accordingly. 4023 * 4024 * When you have finished the editing, write "c" (commit) to the file to commit 4025 * your changes. 4026 * 4027 * If you want to reset to the default value, write "r" (reset) to the file to 4028 * reset them 4029 * 4030 * This setting works under auto fan control mode only. It can co-exist with 4031 * other settings which can work also under auto mode. It adjusts the PMFW's 4032 * behavior about the minimum fan speed in PWM the fan should spin. Setting 4033 * via this interface will switch the fan control to auto mode implicitly. 4034 */ 4035 static ssize_t fan_minimum_pwm_show(struct kobject *kobj, 4036 struct kobj_attribute *attr, 4037 char *buf) 4038 { 4039 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4040 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4041 4042 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf); 4043 } 4044 4045 static ssize_t fan_minimum_pwm_store(struct kobject *kobj, 4046 struct kobj_attribute *attr, 4047 const char *buf, 4048 size_t count) 4049 { 4050 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4051 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4052 4053 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4054 PP_OD_EDIT_FAN_MINIMUM_PWM, 4055 buf, 4056 count); 4057 } 4058 4059 static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev) 4060 { 4061 umode_t umode = 0000; 4062 4063 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE) 4064 umode |= S_IRUSR | S_IRGRP | S_IROTH; 4065 4066 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET) 4067 umode |= S_IWUSR; 4068 4069 return umode; 4070 } 4071 4072 static struct od_feature_set amdgpu_od_set = { 4073 .containers = { 4074 [0] = { 4075 .name = "fan_ctrl", 4076 .sub_feature = { 4077 [0] = { 4078 .name = "fan_curve", 4079 .ops = { 4080 .is_visible = fan_curve_visible, 4081 .show = fan_curve_show, 4082 .store = fan_curve_store, 4083 }, 4084 }, 4085 [1] = { 4086 .name = "acoustic_limit_rpm_threshold", 4087 .ops = { 4088 .is_visible = acoustic_limit_threshold_visible, 4089 .show = acoustic_limit_threshold_show, 4090 .store = acoustic_limit_threshold_store, 4091 }, 4092 }, 4093 [2] = { 4094 .name = "acoustic_target_rpm_threshold", 4095 .ops = { 4096 .is_visible = acoustic_target_threshold_visible, 4097 .show = acoustic_target_threshold_show, 4098 .store = acoustic_target_threshold_store, 4099 }, 4100 }, 4101 [3] = { 4102 .name = "fan_target_temperature", 4103 .ops = { 4104 .is_visible = fan_target_temperature_visible, 4105 .show = fan_target_temperature_show, 4106 .store = fan_target_temperature_store, 4107 }, 4108 }, 4109 [4] = { 4110 .name = "fan_minimum_pwm", 4111 .ops = { 4112 .is_visible = fan_minimum_pwm_visible, 4113 .show = fan_minimum_pwm_show, 4114 .store = fan_minimum_pwm_store, 4115 }, 4116 }, 4117 }, 4118 }, 4119 }, 4120 }; 4121 4122 static void od_kobj_release(struct kobject *kobj) 4123 { 4124 struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj); 4125 4126 kfree(od_kobj); 4127 } 4128 4129 static const struct kobj_type od_ktype = { 4130 .release = od_kobj_release, 4131 .sysfs_ops = &kobj_sysfs_ops, 4132 }; 4133 4134 static void amdgpu_od_set_fini(struct amdgpu_device *adev) 4135 { 4136 struct od_kobj *container, *container_next; 4137 struct od_attribute *attribute, *attribute_next; 4138 4139 if (list_empty(&adev->pm.od_kobj_list)) 4140 return; 4141 4142 list_for_each_entry_safe(container, container_next, 4143 &adev->pm.od_kobj_list, entry) { 4144 list_del(&container->entry); 4145 4146 list_for_each_entry_safe(attribute, attribute_next, 4147 &container->attribute, entry) { 4148 list_del(&attribute->entry); 4149 sysfs_remove_file(&container->kobj, 4150 &attribute->attribute.attr); 4151 kfree(attribute); 4152 } 4153 4154 kobject_put(&container->kobj); 4155 } 4156 } 4157 4158 static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev, 4159 struct od_feature_ops *feature_ops) 4160 { 4161 umode_t mode; 4162 4163 if (!feature_ops->is_visible) 4164 return false; 4165 4166 /* 4167 * If the feature has no user read and write mode set, 4168 * we can assume the feature is actually not supported.(?) 4169 * And the revelant sysfs interface should not be exposed. 4170 */ 4171 mode = feature_ops->is_visible(adev); 4172 if (mode & (S_IRUSR | S_IWUSR)) 4173 return true; 4174 4175 return false; 4176 } 4177 4178 static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev, 4179 struct od_feature_container *container) 4180 { 4181 int i; 4182 4183 /* 4184 * If there is no valid entry within the container, the container 4185 * is recognized as a self contained container. And the valid entry 4186 * here means it has a valid naming and it is visible/supported by 4187 * the ASIC. 4188 */ 4189 for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) { 4190 if (container->sub_feature[i].name && 4191 amdgpu_is_od_feature_supported(adev, 4192 &container->sub_feature[i].ops)) 4193 return false; 4194 } 4195 4196 return true; 4197 } 4198 4199 static int amdgpu_od_set_init(struct amdgpu_device *adev) 4200 { 4201 struct od_kobj *top_set, *sub_set; 4202 struct od_attribute *attribute; 4203 struct od_feature_container *container; 4204 struct od_feature_item *feature; 4205 int i, j; 4206 int ret; 4207 4208 /* Setup the top `gpu_od` directory which holds all other OD interfaces */ 4209 top_set = kzalloc(sizeof(*top_set), GFP_KERNEL); 4210 if (!top_set) 4211 return -ENOMEM; 4212 list_add(&top_set->entry, &adev->pm.od_kobj_list); 4213 4214 ret = kobject_init_and_add(&top_set->kobj, 4215 &od_ktype, 4216 &adev->dev->kobj, 4217 "%s", 4218 "gpu_od"); 4219 if (ret) 4220 goto err_out; 4221 INIT_LIST_HEAD(&top_set->attribute); 4222 top_set->priv = adev; 4223 4224 for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) { 4225 container = &amdgpu_od_set.containers[i]; 4226 4227 if (!container->name) 4228 continue; 4229 4230 /* 4231 * If there is valid entries within the container, the container 4232 * will be presented as a sub directory and all its holding entries 4233 * will be presented as plain files under it. 4234 * While if there is no valid entry within the container, the container 4235 * itself will be presented as a plain file under top `gpu_od` directory. 4236 */ 4237 if (amdgpu_od_is_self_contained(adev, container)) { 4238 if (!amdgpu_is_od_feature_supported(adev, 4239 &container->ops)) 4240 continue; 4241 4242 /* 4243 * The container is presented as a plain file under top `gpu_od` 4244 * directory. 4245 */ 4246 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL); 4247 if (!attribute) { 4248 ret = -ENOMEM; 4249 goto err_out; 4250 } 4251 list_add(&attribute->entry, &top_set->attribute); 4252 4253 attribute->attribute.attr.mode = 4254 container->ops.is_visible(adev); 4255 attribute->attribute.attr.name = container->name; 4256 attribute->attribute.show = 4257 container->ops.show; 4258 attribute->attribute.store = 4259 container->ops.store; 4260 ret = sysfs_create_file(&top_set->kobj, 4261 &attribute->attribute.attr); 4262 if (ret) 4263 goto err_out; 4264 } else { 4265 /* The container is presented as a sub directory. */ 4266 sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL); 4267 if (!sub_set) { 4268 ret = -ENOMEM; 4269 goto err_out; 4270 } 4271 list_add(&sub_set->entry, &adev->pm.od_kobj_list); 4272 4273 ret = kobject_init_and_add(&sub_set->kobj, 4274 &od_ktype, 4275 &top_set->kobj, 4276 "%s", 4277 container->name); 4278 if (ret) 4279 goto err_out; 4280 INIT_LIST_HEAD(&sub_set->attribute); 4281 sub_set->priv = adev; 4282 4283 for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) { 4284 feature = &container->sub_feature[j]; 4285 if (!feature->name) 4286 continue; 4287 4288 if (!amdgpu_is_od_feature_supported(adev, 4289 &feature->ops)) 4290 continue; 4291 4292 /* 4293 * With the container presented as a sub directory, the entry within 4294 * it is presented as a plain file under the sub directory. 4295 */ 4296 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL); 4297 if (!attribute) { 4298 ret = -ENOMEM; 4299 goto err_out; 4300 } 4301 list_add(&attribute->entry, &sub_set->attribute); 4302 4303 attribute->attribute.attr.mode = 4304 feature->ops.is_visible(adev); 4305 attribute->attribute.attr.name = feature->name; 4306 attribute->attribute.show = 4307 feature->ops.show; 4308 attribute->attribute.store = 4309 feature->ops.store; 4310 ret = sysfs_create_file(&sub_set->kobj, 4311 &attribute->attribute.attr); 4312 if (ret) 4313 goto err_out; 4314 } 4315 } 4316 } 4317 4318 return 0; 4319 4320 err_out: 4321 amdgpu_od_set_fini(adev); 4322 4323 return ret; 4324 } 4325 4326 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 4327 { 4328 enum amdgpu_sriov_vf_mode mode; 4329 uint32_t mask = 0; 4330 int ret; 4331 4332 if (adev->pm.sysfs_initialized) 4333 return 0; 4334 4335 INIT_LIST_HEAD(&adev->pm.pm_attr_list); 4336 4337 if (adev->pm.dpm_enabled == 0) 4338 return 0; 4339 4340 mode = amdgpu_virt_get_sriov_vf_mode(adev); 4341 4342 /* under multi-vf mode, the hwmon attributes are all not supported */ 4343 if (mode != SRIOV_VF_MODE_MULTI_VF) { 4344 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 4345 DRIVER_NAME, adev, 4346 hwmon_groups); 4347 if (IS_ERR(adev->pm.int_hwmon_dev)) { 4348 ret = PTR_ERR(adev->pm.int_hwmon_dev); 4349 dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret); 4350 return ret; 4351 } 4352 } 4353 4354 switch (mode) { 4355 case SRIOV_VF_MODE_ONE_VF: 4356 mask = ATTR_FLAG_ONEVF; 4357 break; 4358 case SRIOV_VF_MODE_MULTI_VF: 4359 mask = 0; 4360 break; 4361 case SRIOV_VF_MODE_BARE_METAL: 4362 default: 4363 mask = ATTR_FLAG_MASK_ALL; 4364 break; 4365 } 4366 4367 ret = amdgpu_device_attr_create_groups(adev, 4368 amdgpu_device_attrs, 4369 ARRAY_SIZE(amdgpu_device_attrs), 4370 mask, 4371 &adev->pm.pm_attr_list); 4372 if (ret) 4373 goto err_out0; 4374 4375 if (amdgpu_dpm_is_overdrive_supported(adev)) { 4376 ret = amdgpu_od_set_init(adev); 4377 if (ret) 4378 goto err_out1; 4379 } 4380 4381 adev->pm.sysfs_initialized = true; 4382 4383 return 0; 4384 4385 err_out1: 4386 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 4387 err_out0: 4388 if (adev->pm.int_hwmon_dev) 4389 hwmon_device_unregister(adev->pm.int_hwmon_dev); 4390 4391 return ret; 4392 } 4393 4394 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 4395 { 4396 amdgpu_od_set_fini(adev); 4397 4398 if (adev->pm.int_hwmon_dev) 4399 hwmon_device_unregister(adev->pm.int_hwmon_dev); 4400 4401 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 4402 } 4403 4404 /* 4405 * Debugfs info 4406 */ 4407 #if defined(CONFIG_DEBUG_FS) 4408 4409 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 4410 struct amdgpu_device *adev) 4411 { 4412 uint16_t *p_val; 4413 uint32_t size; 4414 int i; 4415 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); 4416 4417 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { 4418 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), 4419 GFP_KERNEL); 4420 4421 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 4422 (void *)p_val, &size)) { 4423 for (i = 0; i < num_cpu_cores; i++) 4424 seq_printf(m, "\t%u MHz (CPU%d)\n", 4425 *(p_val + i), i); 4426 } 4427 4428 kfree(p_val); 4429 } 4430 } 4431 4432 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 4433 { 4434 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0); 4435 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 4436 uint32_t value; 4437 uint64_t value64 = 0; 4438 uint32_t query = 0; 4439 int size; 4440 4441 /* GPU Clocks */ 4442 size = sizeof(value); 4443 seq_printf(m, "GFX Clocks and Power:\n"); 4444 4445 amdgpu_debugfs_prints_cpu_info(m, adev); 4446 4447 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 4448 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 4449 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 4450 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 4451 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 4452 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 4453 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 4454 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 4455 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 4456 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 4457 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 4458 seq_printf(m, "\t%u mV (VDDNB)\n", value); 4459 size = sizeof(uint32_t); 4460 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) { 4461 if (adev->flags & AMD_IS_APU) 4462 seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n", query >> 8, query & 0xff); 4463 else 4464 seq_printf(m, "\t%u.%02u W (average SoC)\n", query >> 8, query & 0xff); 4465 } 4466 size = sizeof(uint32_t); 4467 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) { 4468 if (adev->flags & AMD_IS_APU) 4469 seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n", query >> 8, query & 0xff); 4470 else 4471 seq_printf(m, "\t%u.%02u W (current SoC)\n", query >> 8, query & 0xff); 4472 } 4473 size = sizeof(value); 4474 seq_printf(m, "\n"); 4475 4476 /* GPU Temp */ 4477 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 4478 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 4479 4480 /* GPU Load */ 4481 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 4482 seq_printf(m, "GPU Load: %u %%\n", value); 4483 /* MEM Load */ 4484 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 4485 seq_printf(m, "MEM Load: %u %%\n", value); 4486 /* VCN Load */ 4487 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_LOAD, (void *)&value, &size)) 4488 seq_printf(m, "VCN Load: %u %%\n", value); 4489 4490 seq_printf(m, "\n"); 4491 4492 /* SMC feature mask */ 4493 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 4494 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 4495 4496 /* ASICs greater than CHIP_VEGA20 supports these sensors */ 4497 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { 4498 /* VCN clocks */ 4499 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 4500 if (!value) { 4501 seq_printf(m, "VCN: Powered down\n"); 4502 } else { 4503 seq_printf(m, "VCN: Powered up\n"); 4504 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 4505 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 4506 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 4507 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 4508 } 4509 } 4510 seq_printf(m, "\n"); 4511 } else { 4512 /* UVD clocks */ 4513 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 4514 if (!value) { 4515 seq_printf(m, "UVD: Powered down\n"); 4516 } else { 4517 seq_printf(m, "UVD: Powered up\n"); 4518 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 4519 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 4520 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 4521 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 4522 } 4523 } 4524 seq_printf(m, "\n"); 4525 4526 /* VCE clocks */ 4527 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 4528 if (!value) { 4529 seq_printf(m, "VCE: Powered down\n"); 4530 } else { 4531 seq_printf(m, "VCE: Powered up\n"); 4532 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 4533 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 4534 } 4535 } 4536 } 4537 4538 return 0; 4539 } 4540 4541 static const struct cg_flag_name clocks[] = { 4542 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 4543 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 4544 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 4545 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 4546 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 4547 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 4548 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 4549 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 4550 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 4551 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 4552 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 4553 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 4554 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 4555 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 4556 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 4557 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 4558 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 4559 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 4560 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 4561 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 4562 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 4563 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 4564 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 4565 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 4566 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 4567 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 4568 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 4569 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 4570 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 4571 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 4572 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, 4573 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, 4574 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 4575 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 4576 {0, NULL}, 4577 }; 4578 4579 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 4580 { 4581 int i; 4582 4583 for (i = 0; clocks[i].flag; i++) 4584 seq_printf(m, "\t%s: %s\n", clocks[i].name, 4585 (flags & clocks[i].flag) ? "On" : "Off"); 4586 } 4587 4588 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 4589 { 4590 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 4591 struct drm_device *dev = adev_to_drm(adev); 4592 u64 flags = 0; 4593 int r; 4594 4595 if (amdgpu_in_reset(adev)) 4596 return -EPERM; 4597 if (adev->in_suspend && !adev->in_runpm) 4598 return -EPERM; 4599 4600 r = pm_runtime_get_sync(dev->dev); 4601 if (r < 0) { 4602 pm_runtime_put_autosuspend(dev->dev); 4603 return r; 4604 } 4605 4606 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { 4607 r = amdgpu_debugfs_pm_info_pp(m, adev); 4608 if (r) 4609 goto out; 4610 } 4611 4612 amdgpu_device_ip_get_clockgating_state(adev, &flags); 4613 4614 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 4615 amdgpu_parse_cg_state(m, flags); 4616 seq_printf(m, "\n"); 4617 4618 out: 4619 pm_runtime_mark_last_busy(dev->dev); 4620 pm_runtime_put_autosuspend(dev->dev); 4621 4622 return r; 4623 } 4624 4625 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 4626 4627 /* 4628 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 4629 * 4630 * Reads debug memory region allocated to PMFW 4631 */ 4632 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 4633 size_t size, loff_t *pos) 4634 { 4635 struct amdgpu_device *adev = file_inode(f)->i_private; 4636 size_t smu_prv_buf_size; 4637 void *smu_prv_buf; 4638 int ret = 0; 4639 4640 if (amdgpu_in_reset(adev)) 4641 return -EPERM; 4642 if (adev->in_suspend && !adev->in_runpm) 4643 return -EPERM; 4644 4645 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); 4646 if (ret) 4647 return ret; 4648 4649 if (!smu_prv_buf || !smu_prv_buf_size) 4650 return -EINVAL; 4651 4652 return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 4653 smu_prv_buf_size); 4654 } 4655 4656 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 4657 .owner = THIS_MODULE, 4658 .open = simple_open, 4659 .read = amdgpu_pm_prv_buffer_read, 4660 .llseek = default_llseek, 4661 }; 4662 4663 #endif 4664 4665 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 4666 { 4667 #if defined(CONFIG_DEBUG_FS) 4668 struct drm_minor *minor = adev_to_drm(adev)->primary; 4669 struct dentry *root = minor->debugfs_root; 4670 4671 if (!adev->pm.dpm_enabled) 4672 return; 4673 4674 debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 4675 &amdgpu_debugfs_pm_info_fops); 4676 4677 if (adev->pm.smu_prv_buffer_size > 0) 4678 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 4679 adev, 4680 &amdgpu_debugfs_pm_prv_buffer_fops, 4681 adev->pm.smu_prv_buffer_size); 4682 4683 amdgpu_dpm_stb_debug_fs_init(adev); 4684 #endif 4685 } 4686