1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/pci.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 #include <linux/pm_runtime.h> 36 #include <asm/processor.h> 37 38 #define MAX_NUM_OF_FEATURES_PER_SUBSET 8 39 #define MAX_NUM_OF_SUBSETS 8 40 41 #define DEVICE_ATTR_IS(_name) (attr_id == device_attr_id__##_name) 42 43 struct od_attribute { 44 struct kobj_attribute attribute; 45 struct list_head entry; 46 }; 47 48 struct od_kobj { 49 struct kobject kobj; 50 struct list_head entry; 51 struct list_head attribute; 52 void *priv; 53 }; 54 55 struct od_feature_ops { 56 umode_t (*is_visible)(struct amdgpu_device *adev); 57 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr, 58 char *buf); 59 ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr, 60 const char *buf, size_t count); 61 }; 62 63 struct od_feature_item { 64 const char *name; 65 struct od_feature_ops ops; 66 }; 67 68 struct od_feature_container { 69 char *name; 70 struct od_feature_ops ops; 71 struct od_feature_item sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET]; 72 }; 73 74 struct od_feature_set { 75 struct od_feature_container containers[MAX_NUM_OF_SUBSETS]; 76 }; 77 78 static const struct hwmon_temp_label { 79 enum PP_HWMON_TEMP channel; 80 const char *label; 81 } temp_label[] = { 82 {PP_TEMP_EDGE, "edge"}, 83 {PP_TEMP_JUNCTION, "junction"}, 84 {PP_TEMP_MEM, "mem"}, 85 }; 86 87 const char * const amdgpu_pp_profile_name[] = { 88 "BOOTUP_DEFAULT", 89 "3D_FULL_SCREEN", 90 "POWER_SAVING", 91 "VIDEO", 92 "VR", 93 "COMPUTE", 94 "CUSTOM", 95 "WINDOW_3D", 96 "CAPPED", 97 "UNCAPPED", 98 }; 99 100 /** 101 * DOC: power_dpm_state 102 * 103 * The power_dpm_state file is a legacy interface and is only provided for 104 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 105 * certain power related parameters. The file power_dpm_state is used for this. 106 * It accepts the following arguments: 107 * 108 * - battery 109 * 110 * - balanced 111 * 112 * - performance 113 * 114 * battery 115 * 116 * On older GPUs, the vbios provided a special power state for battery 117 * operation. Selecting battery switched to this state. This is no 118 * longer provided on newer GPUs so the option does nothing in that case. 119 * 120 * balanced 121 * 122 * On older GPUs, the vbios provided a special power state for balanced 123 * operation. Selecting balanced switched to this state. This is no 124 * longer provided on newer GPUs so the option does nothing in that case. 125 * 126 * performance 127 * 128 * On older GPUs, the vbios provided a special power state for performance 129 * operation. Selecting performance switched to this state. This is no 130 * longer provided on newer GPUs so the option does nothing in that case. 131 * 132 */ 133 134 static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 135 struct device_attribute *attr, 136 char *buf) 137 { 138 struct drm_device *ddev = dev_get_drvdata(dev); 139 struct amdgpu_device *adev = drm_to_adev(ddev); 140 enum amd_pm_state_type pm; 141 int ret; 142 143 if (amdgpu_in_reset(adev)) 144 return -EPERM; 145 if (adev->in_suspend && !adev->in_runpm) 146 return -EPERM; 147 148 ret = pm_runtime_get_sync(ddev->dev); 149 if (ret < 0) { 150 pm_runtime_put_autosuspend(ddev->dev); 151 return ret; 152 } 153 154 amdgpu_dpm_get_current_power_state(adev, &pm); 155 156 pm_runtime_mark_last_busy(ddev->dev); 157 pm_runtime_put_autosuspend(ddev->dev); 158 159 return sysfs_emit(buf, "%s\n", 160 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 161 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 162 } 163 164 static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 165 struct device_attribute *attr, 166 const char *buf, 167 size_t count) 168 { 169 struct drm_device *ddev = dev_get_drvdata(dev); 170 struct amdgpu_device *adev = drm_to_adev(ddev); 171 enum amd_pm_state_type state; 172 int ret; 173 174 if (amdgpu_in_reset(adev)) 175 return -EPERM; 176 if (adev->in_suspend && !adev->in_runpm) 177 return -EPERM; 178 179 if (strncmp("battery", buf, strlen("battery")) == 0) 180 state = POWER_STATE_TYPE_BATTERY; 181 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 182 state = POWER_STATE_TYPE_BALANCED; 183 else if (strncmp("performance", buf, strlen("performance")) == 0) 184 state = POWER_STATE_TYPE_PERFORMANCE; 185 else 186 return -EINVAL; 187 188 ret = pm_runtime_get_sync(ddev->dev); 189 if (ret < 0) { 190 pm_runtime_put_autosuspend(ddev->dev); 191 return ret; 192 } 193 194 amdgpu_dpm_set_power_state(adev, state); 195 196 pm_runtime_mark_last_busy(ddev->dev); 197 pm_runtime_put_autosuspend(ddev->dev); 198 199 return count; 200 } 201 202 203 /** 204 * DOC: power_dpm_force_performance_level 205 * 206 * The amdgpu driver provides a sysfs API for adjusting certain power 207 * related parameters. The file power_dpm_force_performance_level is 208 * used for this. It accepts the following arguments: 209 * 210 * - auto 211 * 212 * - low 213 * 214 * - high 215 * 216 * - manual 217 * 218 * - profile_standard 219 * 220 * - profile_min_sclk 221 * 222 * - profile_min_mclk 223 * 224 * - profile_peak 225 * 226 * auto 227 * 228 * When auto is selected, the driver will attempt to dynamically select 229 * the optimal power profile for current conditions in the driver. 230 * 231 * low 232 * 233 * When low is selected, the clocks are forced to the lowest power state. 234 * 235 * high 236 * 237 * When high is selected, the clocks are forced to the highest power state. 238 * 239 * manual 240 * 241 * When manual is selected, the user can manually adjust which power states 242 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 243 * and pp_dpm_pcie files and adjust the power state transition heuristics 244 * via the pp_power_profile_mode sysfs file. 245 * 246 * profile_standard 247 * profile_min_sclk 248 * profile_min_mclk 249 * profile_peak 250 * 251 * When the profiling modes are selected, clock and power gating are 252 * disabled and the clocks are set for different profiling cases. This 253 * mode is recommended for profiling specific work loads where you do 254 * not want clock or power gating for clock fluctuation to interfere 255 * with your results. profile_standard sets the clocks to a fixed clock 256 * level which varies from asic to asic. profile_min_sclk forces the sclk 257 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 258 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 259 * 260 */ 261 262 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 263 struct device_attribute *attr, 264 char *buf) 265 { 266 struct drm_device *ddev = dev_get_drvdata(dev); 267 struct amdgpu_device *adev = drm_to_adev(ddev); 268 enum amd_dpm_forced_level level = 0xff; 269 int ret; 270 271 if (amdgpu_in_reset(adev)) 272 return -EPERM; 273 if (adev->in_suspend && !adev->in_runpm) 274 return -EPERM; 275 276 ret = pm_runtime_get_sync(ddev->dev); 277 if (ret < 0) { 278 pm_runtime_put_autosuspend(ddev->dev); 279 return ret; 280 } 281 282 level = amdgpu_dpm_get_performance_level(adev); 283 284 pm_runtime_mark_last_busy(ddev->dev); 285 pm_runtime_put_autosuspend(ddev->dev); 286 287 return sysfs_emit(buf, "%s\n", 288 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 289 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 290 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 291 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 292 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 293 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 294 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 295 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 296 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 297 "unknown"); 298 } 299 300 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 301 struct device_attribute *attr, 302 const char *buf, 303 size_t count) 304 { 305 struct drm_device *ddev = dev_get_drvdata(dev); 306 struct amdgpu_device *adev = drm_to_adev(ddev); 307 enum amd_dpm_forced_level level; 308 int ret = 0; 309 310 if (amdgpu_in_reset(adev)) 311 return -EPERM; 312 if (adev->in_suspend && !adev->in_runpm) 313 return -EPERM; 314 315 if (strncmp("low", buf, strlen("low")) == 0) { 316 level = AMD_DPM_FORCED_LEVEL_LOW; 317 } else if (strncmp("high", buf, strlen("high")) == 0) { 318 level = AMD_DPM_FORCED_LEVEL_HIGH; 319 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 320 level = AMD_DPM_FORCED_LEVEL_AUTO; 321 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 322 level = AMD_DPM_FORCED_LEVEL_MANUAL; 323 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 324 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 325 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 326 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 327 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 328 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 329 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 330 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 331 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 332 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 333 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 334 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 335 } else { 336 return -EINVAL; 337 } 338 339 ret = pm_runtime_get_sync(ddev->dev); 340 if (ret < 0) { 341 pm_runtime_put_autosuspend(ddev->dev); 342 return ret; 343 } 344 345 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 346 if (amdgpu_dpm_force_performance_level(adev, level)) { 347 pm_runtime_mark_last_busy(ddev->dev); 348 pm_runtime_put_autosuspend(ddev->dev); 349 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 350 return -EINVAL; 351 } 352 /* override whatever a user ctx may have set */ 353 adev->pm.stable_pstate_ctx = NULL; 354 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 355 356 pm_runtime_mark_last_busy(ddev->dev); 357 pm_runtime_put_autosuspend(ddev->dev); 358 359 return count; 360 } 361 362 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 363 struct device_attribute *attr, 364 char *buf) 365 { 366 struct drm_device *ddev = dev_get_drvdata(dev); 367 struct amdgpu_device *adev = drm_to_adev(ddev); 368 struct pp_states_info data; 369 uint32_t i; 370 int buf_len, ret; 371 372 if (amdgpu_in_reset(adev)) 373 return -EPERM; 374 if (adev->in_suspend && !adev->in_runpm) 375 return -EPERM; 376 377 ret = pm_runtime_get_sync(ddev->dev); 378 if (ret < 0) { 379 pm_runtime_put_autosuspend(ddev->dev); 380 return ret; 381 } 382 383 if (amdgpu_dpm_get_pp_num_states(adev, &data)) 384 memset(&data, 0, sizeof(data)); 385 386 pm_runtime_mark_last_busy(ddev->dev); 387 pm_runtime_put_autosuspend(ddev->dev); 388 389 buf_len = sysfs_emit(buf, "states: %d\n", data.nums); 390 for (i = 0; i < data.nums; i++) 391 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, 392 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 393 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 394 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 395 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 396 397 return buf_len; 398 } 399 400 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 401 struct device_attribute *attr, 402 char *buf) 403 { 404 struct drm_device *ddev = dev_get_drvdata(dev); 405 struct amdgpu_device *adev = drm_to_adev(ddev); 406 struct pp_states_info data = {0}; 407 enum amd_pm_state_type pm = 0; 408 int i = 0, ret = 0; 409 410 if (amdgpu_in_reset(adev)) 411 return -EPERM; 412 if (adev->in_suspend && !adev->in_runpm) 413 return -EPERM; 414 415 ret = pm_runtime_get_sync(ddev->dev); 416 if (ret < 0) { 417 pm_runtime_put_autosuspend(ddev->dev); 418 return ret; 419 } 420 421 amdgpu_dpm_get_current_power_state(adev, &pm); 422 423 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 424 425 pm_runtime_mark_last_busy(ddev->dev); 426 pm_runtime_put_autosuspend(ddev->dev); 427 428 if (ret) 429 return ret; 430 431 for (i = 0; i < data.nums; i++) { 432 if (pm == data.states[i]) 433 break; 434 } 435 436 if (i == data.nums) 437 i = -EINVAL; 438 439 return sysfs_emit(buf, "%d\n", i); 440 } 441 442 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 443 struct device_attribute *attr, 444 char *buf) 445 { 446 struct drm_device *ddev = dev_get_drvdata(dev); 447 struct amdgpu_device *adev = drm_to_adev(ddev); 448 449 if (amdgpu_in_reset(adev)) 450 return -EPERM; 451 if (adev->in_suspend && !adev->in_runpm) 452 return -EPERM; 453 454 if (adev->pm.pp_force_state_enabled) 455 return amdgpu_get_pp_cur_state(dev, attr, buf); 456 else 457 return sysfs_emit(buf, "\n"); 458 } 459 460 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 461 struct device_attribute *attr, 462 const char *buf, 463 size_t count) 464 { 465 struct drm_device *ddev = dev_get_drvdata(dev); 466 struct amdgpu_device *adev = drm_to_adev(ddev); 467 enum amd_pm_state_type state = 0; 468 struct pp_states_info data; 469 unsigned long idx; 470 int ret; 471 472 if (amdgpu_in_reset(adev)) 473 return -EPERM; 474 if (adev->in_suspend && !adev->in_runpm) 475 return -EPERM; 476 477 adev->pm.pp_force_state_enabled = false; 478 479 if (strlen(buf) == 1) 480 return count; 481 482 ret = kstrtoul(buf, 0, &idx); 483 if (ret || idx >= ARRAY_SIZE(data.states)) 484 return -EINVAL; 485 486 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 487 488 ret = pm_runtime_get_sync(ddev->dev); 489 if (ret < 0) { 490 pm_runtime_put_autosuspend(ddev->dev); 491 return ret; 492 } 493 494 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 495 if (ret) 496 goto err_out; 497 498 state = data.states[idx]; 499 500 /* only set user selected power states */ 501 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 502 state != POWER_STATE_TYPE_DEFAULT) { 503 ret = amdgpu_dpm_dispatch_task(adev, 504 AMD_PP_TASK_ENABLE_USER_STATE, &state); 505 if (ret) 506 goto err_out; 507 508 adev->pm.pp_force_state_enabled = true; 509 } 510 511 pm_runtime_mark_last_busy(ddev->dev); 512 pm_runtime_put_autosuspend(ddev->dev); 513 514 return count; 515 516 err_out: 517 pm_runtime_mark_last_busy(ddev->dev); 518 pm_runtime_put_autosuspend(ddev->dev); 519 return ret; 520 } 521 522 /** 523 * DOC: pp_table 524 * 525 * The amdgpu driver provides a sysfs API for uploading new powerplay 526 * tables. The file pp_table is used for this. Reading the file 527 * will dump the current power play table. Writing to the file 528 * will attempt to upload a new powerplay table and re-initialize 529 * powerplay using that new table. 530 * 531 */ 532 533 static ssize_t amdgpu_get_pp_table(struct device *dev, 534 struct device_attribute *attr, 535 char *buf) 536 { 537 struct drm_device *ddev = dev_get_drvdata(dev); 538 struct amdgpu_device *adev = drm_to_adev(ddev); 539 char *table = NULL; 540 int size, ret; 541 542 if (amdgpu_in_reset(adev)) 543 return -EPERM; 544 if (adev->in_suspend && !adev->in_runpm) 545 return -EPERM; 546 547 ret = pm_runtime_get_sync(ddev->dev); 548 if (ret < 0) { 549 pm_runtime_put_autosuspend(ddev->dev); 550 return ret; 551 } 552 553 size = amdgpu_dpm_get_pp_table(adev, &table); 554 555 pm_runtime_mark_last_busy(ddev->dev); 556 pm_runtime_put_autosuspend(ddev->dev); 557 558 if (size <= 0) 559 return size; 560 561 if (size >= PAGE_SIZE) 562 size = PAGE_SIZE - 1; 563 564 memcpy(buf, table, size); 565 566 return size; 567 } 568 569 static ssize_t amdgpu_set_pp_table(struct device *dev, 570 struct device_attribute *attr, 571 const char *buf, 572 size_t count) 573 { 574 struct drm_device *ddev = dev_get_drvdata(dev); 575 struct amdgpu_device *adev = drm_to_adev(ddev); 576 int ret = 0; 577 578 if (amdgpu_in_reset(adev)) 579 return -EPERM; 580 if (adev->in_suspend && !adev->in_runpm) 581 return -EPERM; 582 583 ret = pm_runtime_get_sync(ddev->dev); 584 if (ret < 0) { 585 pm_runtime_put_autosuspend(ddev->dev); 586 return ret; 587 } 588 589 ret = amdgpu_dpm_set_pp_table(adev, buf, count); 590 591 pm_runtime_mark_last_busy(ddev->dev); 592 pm_runtime_put_autosuspend(ddev->dev); 593 594 if (ret) 595 return ret; 596 597 return count; 598 } 599 600 /** 601 * DOC: pp_od_clk_voltage 602 * 603 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 604 * in each power level within a power state. The pp_od_clk_voltage is used for 605 * this. 606 * 607 * Note that the actual memory controller clock rate are exposed, not 608 * the effective memory clock of the DRAMs. To translate it, use the 609 * following formula: 610 * 611 * Clock conversion (Mhz): 612 * 613 * HBM: effective_memory_clock = memory_controller_clock * 1 614 * 615 * G5: effective_memory_clock = memory_controller_clock * 1 616 * 617 * G6: effective_memory_clock = memory_controller_clock * 2 618 * 619 * DRAM data rate (MT/s): 620 * 621 * HBM: effective_memory_clock * 2 = data_rate 622 * 623 * G5: effective_memory_clock * 4 = data_rate 624 * 625 * G6: effective_memory_clock * 8 = data_rate 626 * 627 * Bandwidth (MB/s): 628 * 629 * data_rate * vram_bit_width / 8 = memory_bandwidth 630 * 631 * Some examples: 632 * 633 * G5 on RX460: 634 * 635 * memory_controller_clock = 1750 Mhz 636 * 637 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 638 * 639 * data rate = 1750 * 4 = 7000 MT/s 640 * 641 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 642 * 643 * G6 on RX5700: 644 * 645 * memory_controller_clock = 875 Mhz 646 * 647 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 648 * 649 * data rate = 1750 * 8 = 14000 MT/s 650 * 651 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 652 * 653 * < For Vega10 and previous ASICs > 654 * 655 * Reading the file will display: 656 * 657 * - a list of engine clock levels and voltages labeled OD_SCLK 658 * 659 * - a list of memory clock levels and voltages labeled OD_MCLK 660 * 661 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 662 * 663 * To manually adjust these settings, first select manual using 664 * power_dpm_force_performance_level. Enter a new value for each 665 * level by writing a string that contains "s/m level clock voltage" to 666 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 667 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 668 * 810 mV. When you have edited all of the states as needed, write 669 * "c" (commit) to the file to commit your changes. If you want to reset to the 670 * default power levels, write "r" (reset) to the file to reset them. 671 * 672 * 673 * < For Vega20 and newer ASICs > 674 * 675 * Reading the file will display: 676 * 677 * - minimum and maximum engine clock labeled OD_SCLK 678 * 679 * - minimum(not available for Vega20 and Navi1x) and maximum memory 680 * clock labeled OD_MCLK 681 * 682 * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 683 * They can be used to calibrate the sclk voltage curve. This is 684 * available for Vega20 and NV1X. 685 * 686 * - voltage offset(in mV) applied on target voltage calculation. 687 * This is available for Sienna Cichlid, Navy Flounder, Dimgrey 688 * Cavefish and some later SMU13 ASICs. For these ASICs, the target 689 * voltage calculation can be illustrated by "voltage = voltage 690 * calculated from v/f curve + overdrive vddgfx offset" 691 * 692 * - a list of valid ranges for sclk, mclk, voltage curve points 693 * or voltage offset labeled OD_RANGE 694 * 695 * < For APUs > 696 * 697 * Reading the file will display: 698 * 699 * - minimum and maximum engine clock labeled OD_SCLK 700 * 701 * - a list of valid ranges for sclk labeled OD_RANGE 702 * 703 * < For VanGogh > 704 * 705 * Reading the file will display: 706 * 707 * - minimum and maximum engine clock labeled OD_SCLK 708 * - minimum and maximum core clocks labeled OD_CCLK 709 * 710 * - a list of valid ranges for sclk and cclk labeled OD_RANGE 711 * 712 * To manually adjust these settings: 713 * 714 * - First select manual using power_dpm_force_performance_level 715 * 716 * - For clock frequency setting, enter a new value by writing a 717 * string that contains "s/m index clock" to the file. The index 718 * should be 0 if to set minimum clock. And 1 if to set maximum 719 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 720 * "m 1 800" will update maximum mclk to be 800Mhz. For core 721 * clocks on VanGogh, the string contains "p core index clock". 722 * E.g., "p 2 0 800" would set the minimum core clock on core 723 * 2 to 800Mhz. 724 * 725 * For sclk voltage curve supported by Vega20 and NV1X, enter the new 726 * values by writing a string that contains "vc point clock voltage" 727 * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300 728 * 600" will update point1 with clock set as 300Mhz and voltage as 600mV. 729 * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and 730 * voltage 1000mV. 731 * 732 * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey 733 * Cavefish and some later SMU13 ASICs, enter the new value by writing a 734 * string that contains "vo offset". E.g., "vo -10" will update the extra 735 * voltage offset applied to the whole v/f curve line as -10mv. 736 * 737 * - When you have edited all of the states as needed, write "c" (commit) 738 * to the file to commit your changes 739 * 740 * - If you want to reset to the default power levels, write "r" (reset) 741 * to the file to reset them 742 * 743 */ 744 745 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 746 struct device_attribute *attr, 747 const char *buf, 748 size_t count) 749 { 750 struct drm_device *ddev = dev_get_drvdata(dev); 751 struct amdgpu_device *adev = drm_to_adev(ddev); 752 int ret; 753 uint32_t parameter_size = 0; 754 long parameter[64]; 755 char buf_cpy[128]; 756 char *tmp_str; 757 char *sub_str; 758 const char delimiter[3] = {' ', '\n', '\0'}; 759 uint32_t type; 760 761 if (amdgpu_in_reset(adev)) 762 return -EPERM; 763 if (adev->in_suspend && !adev->in_runpm) 764 return -EPERM; 765 766 if (count > 127 || count == 0) 767 return -EINVAL; 768 769 if (*buf == 's') 770 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 771 else if (*buf == 'p') 772 type = PP_OD_EDIT_CCLK_VDDC_TABLE; 773 else if (*buf == 'm') 774 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 775 else if (*buf == 'r') 776 type = PP_OD_RESTORE_DEFAULT_TABLE; 777 else if (*buf == 'c') 778 type = PP_OD_COMMIT_DPM_TABLE; 779 else if (!strncmp(buf, "vc", 2)) 780 type = PP_OD_EDIT_VDDC_CURVE; 781 else if (!strncmp(buf, "vo", 2)) 782 type = PP_OD_EDIT_VDDGFX_OFFSET; 783 else 784 return -EINVAL; 785 786 memcpy(buf_cpy, buf, count); 787 buf_cpy[count] = 0; 788 789 tmp_str = buf_cpy; 790 791 if ((type == PP_OD_EDIT_VDDC_CURVE) || 792 (type == PP_OD_EDIT_VDDGFX_OFFSET)) 793 tmp_str++; 794 while (isspace(*++tmp_str)); 795 796 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 797 if (strlen(sub_str) == 0) 798 continue; 799 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 800 if (ret) 801 return -EINVAL; 802 parameter_size++; 803 804 if (!tmp_str) 805 break; 806 807 while (isspace(*tmp_str)) 808 tmp_str++; 809 } 810 811 ret = pm_runtime_get_sync(ddev->dev); 812 if (ret < 0) { 813 pm_runtime_put_autosuspend(ddev->dev); 814 return ret; 815 } 816 817 if (amdgpu_dpm_set_fine_grain_clk_vol(adev, 818 type, 819 parameter, 820 parameter_size)) 821 goto err_out; 822 823 if (amdgpu_dpm_odn_edit_dpm_table(adev, type, 824 parameter, parameter_size)) 825 goto err_out; 826 827 if (type == PP_OD_COMMIT_DPM_TABLE) { 828 if (amdgpu_dpm_dispatch_task(adev, 829 AMD_PP_TASK_READJUST_POWER_STATE, 830 NULL)) 831 goto err_out; 832 } 833 834 pm_runtime_mark_last_busy(ddev->dev); 835 pm_runtime_put_autosuspend(ddev->dev); 836 837 return count; 838 839 err_out: 840 pm_runtime_mark_last_busy(ddev->dev); 841 pm_runtime_put_autosuspend(ddev->dev); 842 return -EINVAL; 843 } 844 845 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 846 struct device_attribute *attr, 847 char *buf) 848 { 849 struct drm_device *ddev = dev_get_drvdata(dev); 850 struct amdgpu_device *adev = drm_to_adev(ddev); 851 int size = 0; 852 int ret; 853 enum pp_clock_type od_clocks[6] = { 854 OD_SCLK, 855 OD_MCLK, 856 OD_VDDC_CURVE, 857 OD_RANGE, 858 OD_VDDGFX_OFFSET, 859 OD_CCLK, 860 }; 861 uint clk_index; 862 863 if (amdgpu_in_reset(adev)) 864 return -EPERM; 865 if (adev->in_suspend && !adev->in_runpm) 866 return -EPERM; 867 868 ret = pm_runtime_get_sync(ddev->dev); 869 if (ret < 0) { 870 pm_runtime_put_autosuspend(ddev->dev); 871 return ret; 872 } 873 874 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { 875 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); 876 if (ret) 877 break; 878 } 879 if (ret == -ENOENT) { 880 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 881 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); 882 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); 883 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); 884 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); 885 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); 886 } 887 888 if (size == 0) 889 size = sysfs_emit(buf, "\n"); 890 891 pm_runtime_mark_last_busy(ddev->dev); 892 pm_runtime_put_autosuspend(ddev->dev); 893 894 return size; 895 } 896 897 /** 898 * DOC: pp_features 899 * 900 * The amdgpu driver provides a sysfs API for adjusting what powerplay 901 * features to be enabled. The file pp_features is used for this. And 902 * this is only available for Vega10 and later dGPUs. 903 * 904 * Reading back the file will show you the followings: 905 * - Current ppfeature masks 906 * - List of the all supported powerplay features with their naming, 907 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 908 * 909 * To manually enable or disable a specific feature, just set or clear 910 * the corresponding bit from original ppfeature masks and input the 911 * new ppfeature masks. 912 */ 913 static ssize_t amdgpu_set_pp_features(struct device *dev, 914 struct device_attribute *attr, 915 const char *buf, 916 size_t count) 917 { 918 struct drm_device *ddev = dev_get_drvdata(dev); 919 struct amdgpu_device *adev = drm_to_adev(ddev); 920 uint64_t featuremask; 921 int ret; 922 923 if (amdgpu_in_reset(adev)) 924 return -EPERM; 925 if (adev->in_suspend && !adev->in_runpm) 926 return -EPERM; 927 928 ret = kstrtou64(buf, 0, &featuremask); 929 if (ret) 930 return -EINVAL; 931 932 ret = pm_runtime_get_sync(ddev->dev); 933 if (ret < 0) { 934 pm_runtime_put_autosuspend(ddev->dev); 935 return ret; 936 } 937 938 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 939 940 pm_runtime_mark_last_busy(ddev->dev); 941 pm_runtime_put_autosuspend(ddev->dev); 942 943 if (ret) 944 return -EINVAL; 945 946 return count; 947 } 948 949 static ssize_t amdgpu_get_pp_features(struct device *dev, 950 struct device_attribute *attr, 951 char *buf) 952 { 953 struct drm_device *ddev = dev_get_drvdata(dev); 954 struct amdgpu_device *adev = drm_to_adev(ddev); 955 ssize_t size; 956 int ret; 957 958 if (amdgpu_in_reset(adev)) 959 return -EPERM; 960 if (adev->in_suspend && !adev->in_runpm) 961 return -EPERM; 962 963 ret = pm_runtime_get_sync(ddev->dev); 964 if (ret < 0) { 965 pm_runtime_put_autosuspend(ddev->dev); 966 return ret; 967 } 968 969 size = amdgpu_dpm_get_ppfeature_status(adev, buf); 970 if (size <= 0) 971 size = sysfs_emit(buf, "\n"); 972 973 pm_runtime_mark_last_busy(ddev->dev); 974 pm_runtime_put_autosuspend(ddev->dev); 975 976 return size; 977 } 978 979 /** 980 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 981 * 982 * The amdgpu driver provides a sysfs API for adjusting what power levels 983 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 984 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 985 * this. 986 * 987 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 988 * Vega10 and later ASICs. 989 * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 990 * 991 * Reading back the files will show you the available power levels within 992 * the power state and the clock information for those levels. If deep sleep is 993 * applied to a clock, the level will be denoted by a special level 'S:' 994 * E.g., :: 995 * 996 * S: 19Mhz * 997 * 0: 615Mhz 998 * 1: 800Mhz 999 * 2: 888Mhz 1000 * 3: 1000Mhz 1001 * 1002 * 1003 * To manually adjust these states, first select manual using 1004 * power_dpm_force_performance_level. 1005 * Secondly, enter a new value for each level by inputing a string that 1006 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 1007 * E.g., 1008 * 1009 * .. code-block:: bash 1010 * 1011 * echo "4 5 6" > pp_dpm_sclk 1012 * 1013 * will enable sclk levels 4, 5, and 6. 1014 * 1015 * NOTE: change to the dcefclk max dpm level is not supported now 1016 */ 1017 1018 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 1019 enum pp_clock_type type, 1020 char *buf) 1021 { 1022 struct drm_device *ddev = dev_get_drvdata(dev); 1023 struct amdgpu_device *adev = drm_to_adev(ddev); 1024 int size = 0; 1025 int ret = 0; 1026 1027 if (amdgpu_in_reset(adev)) 1028 return -EPERM; 1029 if (adev->in_suspend && !adev->in_runpm) 1030 return -EPERM; 1031 1032 ret = pm_runtime_get_sync(ddev->dev); 1033 if (ret < 0) { 1034 pm_runtime_put_autosuspend(ddev->dev); 1035 return ret; 1036 } 1037 1038 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); 1039 if (ret == -ENOENT) 1040 size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1041 1042 if (size == 0) 1043 size = sysfs_emit(buf, "\n"); 1044 1045 pm_runtime_mark_last_busy(ddev->dev); 1046 pm_runtime_put_autosuspend(ddev->dev); 1047 1048 return size; 1049 } 1050 1051 /* 1052 * Worst case: 32 bits individually specified, in octal at 12 characters 1053 * per line (+1 for \n). 1054 */ 1055 #define AMDGPU_MASK_BUF_MAX (32 * 13) 1056 1057 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1058 { 1059 int ret; 1060 unsigned long level; 1061 char *sub_str = NULL; 1062 char *tmp; 1063 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1064 const char delimiter[3] = {' ', '\n', '\0'}; 1065 size_t bytes; 1066 1067 *mask = 0; 1068 1069 bytes = min(count, sizeof(buf_cpy) - 1); 1070 memcpy(buf_cpy, buf, bytes); 1071 buf_cpy[bytes] = '\0'; 1072 tmp = buf_cpy; 1073 while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1074 if (strlen(sub_str)) { 1075 ret = kstrtoul(sub_str, 0, &level); 1076 if (ret || level > 31) 1077 return -EINVAL; 1078 *mask |= 1 << level; 1079 } else 1080 break; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 1087 enum pp_clock_type type, 1088 const char *buf, 1089 size_t count) 1090 { 1091 struct drm_device *ddev = dev_get_drvdata(dev); 1092 struct amdgpu_device *adev = drm_to_adev(ddev); 1093 int ret; 1094 uint32_t mask = 0; 1095 1096 if (amdgpu_in_reset(adev)) 1097 return -EPERM; 1098 if (adev->in_suspend && !adev->in_runpm) 1099 return -EPERM; 1100 1101 ret = amdgpu_read_mask(buf, count, &mask); 1102 if (ret) 1103 return ret; 1104 1105 ret = pm_runtime_get_sync(ddev->dev); 1106 if (ret < 0) { 1107 pm_runtime_put_autosuspend(ddev->dev); 1108 return ret; 1109 } 1110 1111 ret = amdgpu_dpm_force_clock_level(adev, type, mask); 1112 1113 pm_runtime_mark_last_busy(ddev->dev); 1114 pm_runtime_put_autosuspend(ddev->dev); 1115 1116 if (ret) 1117 return -EINVAL; 1118 1119 return count; 1120 } 1121 1122 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1123 struct device_attribute *attr, 1124 char *buf) 1125 { 1126 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 1127 } 1128 1129 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1130 struct device_attribute *attr, 1131 const char *buf, 1132 size_t count) 1133 { 1134 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 1135 } 1136 1137 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1138 struct device_attribute *attr, 1139 char *buf) 1140 { 1141 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1142 } 1143 1144 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1145 struct device_attribute *attr, 1146 const char *buf, 1147 size_t count) 1148 { 1149 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1150 } 1151 1152 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1153 struct device_attribute *attr, 1154 char *buf) 1155 { 1156 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1157 } 1158 1159 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1160 struct device_attribute *attr, 1161 const char *buf, 1162 size_t count) 1163 { 1164 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1165 } 1166 1167 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1168 struct device_attribute *attr, 1169 char *buf) 1170 { 1171 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1172 } 1173 1174 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1175 struct device_attribute *attr, 1176 const char *buf, 1177 size_t count) 1178 { 1179 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1180 } 1181 1182 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 1183 struct device_attribute *attr, 1184 char *buf) 1185 { 1186 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 1187 } 1188 1189 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 1190 struct device_attribute *attr, 1191 const char *buf, 1192 size_t count) 1193 { 1194 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 1195 } 1196 1197 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev, 1198 struct device_attribute *attr, 1199 char *buf) 1200 { 1201 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf); 1202 } 1203 1204 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev, 1205 struct device_attribute *attr, 1206 const char *buf, 1207 size_t count) 1208 { 1209 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count); 1210 } 1211 1212 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 1213 struct device_attribute *attr, 1214 char *buf) 1215 { 1216 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 1217 } 1218 1219 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 1220 struct device_attribute *attr, 1221 const char *buf, 1222 size_t count) 1223 { 1224 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 1225 } 1226 1227 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev, 1228 struct device_attribute *attr, 1229 char *buf) 1230 { 1231 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf); 1232 } 1233 1234 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev, 1235 struct device_attribute *attr, 1236 const char *buf, 1237 size_t count) 1238 { 1239 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count); 1240 } 1241 1242 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1243 struct device_attribute *attr, 1244 char *buf) 1245 { 1246 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1247 } 1248 1249 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1250 struct device_attribute *attr, 1251 const char *buf, 1252 size_t count) 1253 { 1254 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1255 } 1256 1257 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1258 struct device_attribute *attr, 1259 char *buf) 1260 { 1261 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1262 } 1263 1264 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1265 struct device_attribute *attr, 1266 const char *buf, 1267 size_t count) 1268 { 1269 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1270 } 1271 1272 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1273 struct device_attribute *attr, 1274 char *buf) 1275 { 1276 struct drm_device *ddev = dev_get_drvdata(dev); 1277 struct amdgpu_device *adev = drm_to_adev(ddev); 1278 uint32_t value = 0; 1279 int ret; 1280 1281 if (amdgpu_in_reset(adev)) 1282 return -EPERM; 1283 if (adev->in_suspend && !adev->in_runpm) 1284 return -EPERM; 1285 1286 ret = pm_runtime_get_sync(ddev->dev); 1287 if (ret < 0) { 1288 pm_runtime_put_autosuspend(ddev->dev); 1289 return ret; 1290 } 1291 1292 value = amdgpu_dpm_get_sclk_od(adev); 1293 1294 pm_runtime_mark_last_busy(ddev->dev); 1295 pm_runtime_put_autosuspend(ddev->dev); 1296 1297 return sysfs_emit(buf, "%d\n", value); 1298 } 1299 1300 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1301 struct device_attribute *attr, 1302 const char *buf, 1303 size_t count) 1304 { 1305 struct drm_device *ddev = dev_get_drvdata(dev); 1306 struct amdgpu_device *adev = drm_to_adev(ddev); 1307 int ret; 1308 long int value; 1309 1310 if (amdgpu_in_reset(adev)) 1311 return -EPERM; 1312 if (adev->in_suspend && !adev->in_runpm) 1313 return -EPERM; 1314 1315 ret = kstrtol(buf, 0, &value); 1316 1317 if (ret) 1318 return -EINVAL; 1319 1320 ret = pm_runtime_get_sync(ddev->dev); 1321 if (ret < 0) { 1322 pm_runtime_put_autosuspend(ddev->dev); 1323 return ret; 1324 } 1325 1326 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1327 1328 pm_runtime_mark_last_busy(ddev->dev); 1329 pm_runtime_put_autosuspend(ddev->dev); 1330 1331 return count; 1332 } 1333 1334 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1335 struct device_attribute *attr, 1336 char *buf) 1337 { 1338 struct drm_device *ddev = dev_get_drvdata(dev); 1339 struct amdgpu_device *adev = drm_to_adev(ddev); 1340 uint32_t value = 0; 1341 int ret; 1342 1343 if (amdgpu_in_reset(adev)) 1344 return -EPERM; 1345 if (adev->in_suspend && !adev->in_runpm) 1346 return -EPERM; 1347 1348 ret = pm_runtime_get_sync(ddev->dev); 1349 if (ret < 0) { 1350 pm_runtime_put_autosuspend(ddev->dev); 1351 return ret; 1352 } 1353 1354 value = amdgpu_dpm_get_mclk_od(adev); 1355 1356 pm_runtime_mark_last_busy(ddev->dev); 1357 pm_runtime_put_autosuspend(ddev->dev); 1358 1359 return sysfs_emit(buf, "%d\n", value); 1360 } 1361 1362 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1363 struct device_attribute *attr, 1364 const char *buf, 1365 size_t count) 1366 { 1367 struct drm_device *ddev = dev_get_drvdata(dev); 1368 struct amdgpu_device *adev = drm_to_adev(ddev); 1369 int ret; 1370 long int value; 1371 1372 if (amdgpu_in_reset(adev)) 1373 return -EPERM; 1374 if (adev->in_suspend && !adev->in_runpm) 1375 return -EPERM; 1376 1377 ret = kstrtol(buf, 0, &value); 1378 1379 if (ret) 1380 return -EINVAL; 1381 1382 ret = pm_runtime_get_sync(ddev->dev); 1383 if (ret < 0) { 1384 pm_runtime_put_autosuspend(ddev->dev); 1385 return ret; 1386 } 1387 1388 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1389 1390 pm_runtime_mark_last_busy(ddev->dev); 1391 pm_runtime_put_autosuspend(ddev->dev); 1392 1393 return count; 1394 } 1395 1396 /** 1397 * DOC: pp_power_profile_mode 1398 * 1399 * The amdgpu driver provides a sysfs API for adjusting the heuristics 1400 * related to switching between power levels in a power state. The file 1401 * pp_power_profile_mode is used for this. 1402 * 1403 * Reading this file outputs a list of all of the predefined power profiles 1404 * and the relevant heuristics settings for that profile. 1405 * 1406 * To select a profile or create a custom profile, first select manual using 1407 * power_dpm_force_performance_level. Writing the number of a predefined 1408 * profile to pp_power_profile_mode will enable those heuristics. To 1409 * create a custom set of heuristics, write a string of numbers to the file 1410 * starting with the number of the custom profile along with a setting 1411 * for each heuristic parameter. Due to differences across asic families 1412 * the heuristic parameters vary from family to family. 1413 * 1414 */ 1415 1416 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1417 struct device_attribute *attr, 1418 char *buf) 1419 { 1420 struct drm_device *ddev = dev_get_drvdata(dev); 1421 struct amdgpu_device *adev = drm_to_adev(ddev); 1422 ssize_t size; 1423 int ret; 1424 1425 if (amdgpu_in_reset(adev)) 1426 return -EPERM; 1427 if (adev->in_suspend && !adev->in_runpm) 1428 return -EPERM; 1429 1430 ret = pm_runtime_get_sync(ddev->dev); 1431 if (ret < 0) { 1432 pm_runtime_put_autosuspend(ddev->dev); 1433 return ret; 1434 } 1435 1436 size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1437 if (size <= 0) 1438 size = sysfs_emit(buf, "\n"); 1439 1440 pm_runtime_mark_last_busy(ddev->dev); 1441 pm_runtime_put_autosuspend(ddev->dev); 1442 1443 return size; 1444 } 1445 1446 1447 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1448 struct device_attribute *attr, 1449 const char *buf, 1450 size_t count) 1451 { 1452 int ret; 1453 struct drm_device *ddev = dev_get_drvdata(dev); 1454 struct amdgpu_device *adev = drm_to_adev(ddev); 1455 uint32_t parameter_size = 0; 1456 long parameter[64]; 1457 char *sub_str, buf_cpy[128]; 1458 char *tmp_str; 1459 uint32_t i = 0; 1460 char tmp[2]; 1461 long int profile_mode = 0; 1462 const char delimiter[3] = {' ', '\n', '\0'}; 1463 1464 if (amdgpu_in_reset(adev)) 1465 return -EPERM; 1466 if (adev->in_suspend && !adev->in_runpm) 1467 return -EPERM; 1468 1469 tmp[0] = *(buf); 1470 tmp[1] = '\0'; 1471 ret = kstrtol(tmp, 0, &profile_mode); 1472 if (ret) 1473 return -EINVAL; 1474 1475 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1476 if (count < 2 || count > 127) 1477 return -EINVAL; 1478 while (isspace(*++buf)) 1479 i++; 1480 memcpy(buf_cpy, buf, count-i); 1481 tmp_str = buf_cpy; 1482 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1483 if (strlen(sub_str) == 0) 1484 continue; 1485 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1486 if (ret) 1487 return -EINVAL; 1488 parameter_size++; 1489 while (isspace(*tmp_str)) 1490 tmp_str++; 1491 } 1492 } 1493 parameter[parameter_size] = profile_mode; 1494 1495 ret = pm_runtime_get_sync(ddev->dev); 1496 if (ret < 0) { 1497 pm_runtime_put_autosuspend(ddev->dev); 1498 return ret; 1499 } 1500 1501 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1502 1503 pm_runtime_mark_last_busy(ddev->dev); 1504 pm_runtime_put_autosuspend(ddev->dev); 1505 1506 if (!ret) 1507 return count; 1508 1509 return -EINVAL; 1510 } 1511 1512 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev, 1513 enum amd_pp_sensors sensor, 1514 void *query) 1515 { 1516 int r, size = sizeof(uint32_t); 1517 1518 if (amdgpu_in_reset(adev)) 1519 return -EPERM; 1520 if (adev->in_suspend && !adev->in_runpm) 1521 return -EPERM; 1522 1523 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 1524 if (r < 0) { 1525 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1526 return r; 1527 } 1528 1529 /* get the sensor value */ 1530 r = amdgpu_dpm_read_sensor(adev, sensor, query, &size); 1531 1532 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1533 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1534 1535 return r; 1536 } 1537 1538 /** 1539 * DOC: gpu_busy_percent 1540 * 1541 * The amdgpu driver provides a sysfs API for reading how busy the GPU 1542 * is as a percentage. The file gpu_busy_percent is used for this. 1543 * The SMU firmware computes a percentage of load based on the 1544 * aggregate activity level in the IP cores. 1545 */ 1546 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1547 struct device_attribute *attr, 1548 char *buf) 1549 { 1550 struct drm_device *ddev = dev_get_drvdata(dev); 1551 struct amdgpu_device *adev = drm_to_adev(ddev); 1552 unsigned int value; 1553 int r; 1554 1555 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value); 1556 if (r) 1557 return r; 1558 1559 return sysfs_emit(buf, "%d\n", value); 1560 } 1561 1562 /** 1563 * DOC: mem_busy_percent 1564 * 1565 * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1566 * is as a percentage. The file mem_busy_percent is used for this. 1567 * The SMU firmware computes a percentage of load based on the 1568 * aggregate activity level in the IP cores. 1569 */ 1570 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1571 struct device_attribute *attr, 1572 char *buf) 1573 { 1574 struct drm_device *ddev = dev_get_drvdata(dev); 1575 struct amdgpu_device *adev = drm_to_adev(ddev); 1576 unsigned int value; 1577 int r; 1578 1579 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value); 1580 if (r) 1581 return r; 1582 1583 return sysfs_emit(buf, "%d\n", value); 1584 } 1585 1586 /** 1587 * DOC: vcn_busy_percent 1588 * 1589 * The amdgpu driver provides a sysfs API for reading how busy the VCN 1590 * is as a percentage. The file vcn_busy_percent is used for this. 1591 * The SMU firmware computes a percentage of load based on the 1592 * aggregate activity level in the IP cores. 1593 */ 1594 static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev, 1595 struct device_attribute *attr, 1596 char *buf) 1597 { 1598 struct drm_device *ddev = dev_get_drvdata(dev); 1599 struct amdgpu_device *adev = drm_to_adev(ddev); 1600 unsigned int value; 1601 int r; 1602 1603 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD, &value); 1604 if (r) 1605 return r; 1606 1607 return sysfs_emit(buf, "%d\n", value); 1608 } 1609 1610 /** 1611 * DOC: pcie_bw 1612 * 1613 * The amdgpu driver provides a sysfs API for estimating how much data 1614 * has been received and sent by the GPU in the last second through PCIe. 1615 * The file pcie_bw is used for this. 1616 * The Perf counters count the number of received and sent messages and return 1617 * those values, as well as the maximum payload size of a PCIe packet (mps). 1618 * Note that it is not possible to easily and quickly obtain the size of each 1619 * packet transmitted, so we output the max payload size (mps) to allow for 1620 * quick estimation of the PCIe bandwidth usage 1621 */ 1622 static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1623 struct device_attribute *attr, 1624 char *buf) 1625 { 1626 struct drm_device *ddev = dev_get_drvdata(dev); 1627 struct amdgpu_device *adev = drm_to_adev(ddev); 1628 uint64_t count0 = 0, count1 = 0; 1629 int ret; 1630 1631 if (amdgpu_in_reset(adev)) 1632 return -EPERM; 1633 if (adev->in_suspend && !adev->in_runpm) 1634 return -EPERM; 1635 1636 if (adev->flags & AMD_IS_APU) 1637 return -ENODATA; 1638 1639 if (!adev->asic_funcs->get_pcie_usage) 1640 return -ENODATA; 1641 1642 ret = pm_runtime_get_sync(ddev->dev); 1643 if (ret < 0) { 1644 pm_runtime_put_autosuspend(ddev->dev); 1645 return ret; 1646 } 1647 1648 amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1649 1650 pm_runtime_mark_last_busy(ddev->dev); 1651 pm_runtime_put_autosuspend(ddev->dev); 1652 1653 return sysfs_emit(buf, "%llu %llu %i\n", 1654 count0, count1, pcie_get_mps(adev->pdev)); 1655 } 1656 1657 /** 1658 * DOC: unique_id 1659 * 1660 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1661 * The file unique_id is used for this. 1662 * This will provide a Unique ID that will persist from machine to machine 1663 * 1664 * NOTE: This will only work for GFX9 and newer. This file will be absent 1665 * on unsupported ASICs (GFX8 and older) 1666 */ 1667 static ssize_t amdgpu_get_unique_id(struct device *dev, 1668 struct device_attribute *attr, 1669 char *buf) 1670 { 1671 struct drm_device *ddev = dev_get_drvdata(dev); 1672 struct amdgpu_device *adev = drm_to_adev(ddev); 1673 1674 if (amdgpu_in_reset(adev)) 1675 return -EPERM; 1676 if (adev->in_suspend && !adev->in_runpm) 1677 return -EPERM; 1678 1679 if (adev->unique_id) 1680 return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1681 1682 return 0; 1683 } 1684 1685 /** 1686 * DOC: thermal_throttling_logging 1687 * 1688 * Thermal throttling pulls down the clock frequency and thus the performance. 1689 * It's an useful mechanism to protect the chip from overheating. Since it 1690 * impacts performance, the user controls whether it is enabled and if so, 1691 * the log frequency. 1692 * 1693 * Reading back the file shows you the status(enabled or disabled) and 1694 * the interval(in seconds) between each thermal logging. 1695 * 1696 * Writing an integer to the file, sets a new logging interval, in seconds. 1697 * The value should be between 1 and 3600. If the value is less than 1, 1698 * thermal logging is disabled. Values greater than 3600 are ignored. 1699 */ 1700 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1701 struct device_attribute *attr, 1702 char *buf) 1703 { 1704 struct drm_device *ddev = dev_get_drvdata(dev); 1705 struct amdgpu_device *adev = drm_to_adev(ddev); 1706 1707 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 1708 adev_to_drm(adev)->unique, 1709 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1710 adev->throttling_logging_rs.interval / HZ + 1); 1711 } 1712 1713 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1714 struct device_attribute *attr, 1715 const char *buf, 1716 size_t count) 1717 { 1718 struct drm_device *ddev = dev_get_drvdata(dev); 1719 struct amdgpu_device *adev = drm_to_adev(ddev); 1720 long throttling_logging_interval; 1721 unsigned long flags; 1722 int ret = 0; 1723 1724 ret = kstrtol(buf, 0, &throttling_logging_interval); 1725 if (ret) 1726 return ret; 1727 1728 if (throttling_logging_interval > 3600) 1729 return -EINVAL; 1730 1731 if (throttling_logging_interval > 0) { 1732 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1733 /* 1734 * Reset the ratelimit timer internals. 1735 * This can effectively restart the timer. 1736 */ 1737 adev->throttling_logging_rs.interval = 1738 (throttling_logging_interval - 1) * HZ; 1739 adev->throttling_logging_rs.begin = 0; 1740 adev->throttling_logging_rs.printed = 0; 1741 adev->throttling_logging_rs.missed = 0; 1742 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1743 1744 atomic_set(&adev->throttling_logging_enabled, 1); 1745 } else { 1746 atomic_set(&adev->throttling_logging_enabled, 0); 1747 } 1748 1749 return count; 1750 } 1751 1752 /** 1753 * DOC: apu_thermal_cap 1754 * 1755 * The amdgpu driver provides a sysfs API for retrieving/updating thermal 1756 * limit temperature in millidegrees Celsius 1757 * 1758 * Reading back the file shows you core limit value 1759 * 1760 * Writing an integer to the file, sets a new thermal limit. The value 1761 * should be between 0 and 100. If the value is less than 0 or greater 1762 * than 100, then the write request will be ignored. 1763 */ 1764 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, 1765 struct device_attribute *attr, 1766 char *buf) 1767 { 1768 int ret, size; 1769 u32 limit; 1770 struct drm_device *ddev = dev_get_drvdata(dev); 1771 struct amdgpu_device *adev = drm_to_adev(ddev); 1772 1773 ret = pm_runtime_get_sync(ddev->dev); 1774 if (ret < 0) { 1775 pm_runtime_put_autosuspend(ddev->dev); 1776 return ret; 1777 } 1778 1779 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit); 1780 if (!ret) 1781 size = sysfs_emit(buf, "%u\n", limit); 1782 else 1783 size = sysfs_emit(buf, "failed to get thermal limit\n"); 1784 1785 pm_runtime_mark_last_busy(ddev->dev); 1786 pm_runtime_put_autosuspend(ddev->dev); 1787 1788 return size; 1789 } 1790 1791 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, 1792 struct device_attribute *attr, 1793 const char *buf, 1794 size_t count) 1795 { 1796 int ret; 1797 u32 value; 1798 struct drm_device *ddev = dev_get_drvdata(dev); 1799 struct amdgpu_device *adev = drm_to_adev(ddev); 1800 1801 ret = kstrtou32(buf, 10, &value); 1802 if (ret) 1803 return ret; 1804 1805 if (value > 100) { 1806 dev_err(dev, "Invalid argument !\n"); 1807 return -EINVAL; 1808 } 1809 1810 ret = pm_runtime_get_sync(ddev->dev); 1811 if (ret < 0) { 1812 pm_runtime_put_autosuspend(ddev->dev); 1813 return ret; 1814 } 1815 1816 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value); 1817 if (ret) { 1818 dev_err(dev, "failed to update thermal limit\n"); 1819 return ret; 1820 } 1821 1822 pm_runtime_mark_last_busy(ddev->dev); 1823 pm_runtime_put_autosuspend(ddev->dev); 1824 1825 return count; 1826 } 1827 1828 static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev, 1829 struct amdgpu_device_attr *attr, 1830 uint32_t mask, 1831 enum amdgpu_device_attr_states *states) 1832 { 1833 if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP) 1834 *states = ATTR_STATE_UNSUPPORTED; 1835 1836 return 0; 1837 } 1838 1839 static ssize_t amdgpu_get_pm_metrics(struct device *dev, 1840 struct device_attribute *attr, char *buf) 1841 { 1842 struct drm_device *ddev = dev_get_drvdata(dev); 1843 struct amdgpu_device *adev = drm_to_adev(ddev); 1844 ssize_t size = 0; 1845 int ret; 1846 1847 if (amdgpu_in_reset(adev)) 1848 return -EPERM; 1849 if (adev->in_suspend && !adev->in_runpm) 1850 return -EPERM; 1851 1852 ret = pm_runtime_get_sync(ddev->dev); 1853 if (ret < 0) { 1854 pm_runtime_put_autosuspend(ddev->dev); 1855 return ret; 1856 } 1857 1858 size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE); 1859 1860 pm_runtime_mark_last_busy(ddev->dev); 1861 pm_runtime_put_autosuspend(ddev->dev); 1862 1863 return size; 1864 } 1865 1866 /** 1867 * DOC: gpu_metrics 1868 * 1869 * The amdgpu driver provides a sysfs API for retrieving current gpu 1870 * metrics data. The file gpu_metrics is used for this. Reading the 1871 * file will dump all the current gpu metrics data. 1872 * 1873 * These data include temperature, frequency, engines utilization, 1874 * power consume, throttler status, fan speed and cpu core statistics( 1875 * available for APU only). That's it will give a snapshot of all sensors 1876 * at the same time. 1877 */ 1878 static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1879 struct device_attribute *attr, 1880 char *buf) 1881 { 1882 struct drm_device *ddev = dev_get_drvdata(dev); 1883 struct amdgpu_device *adev = drm_to_adev(ddev); 1884 void *gpu_metrics; 1885 ssize_t size = 0; 1886 int ret; 1887 1888 if (amdgpu_in_reset(adev)) 1889 return -EPERM; 1890 if (adev->in_suspend && !adev->in_runpm) 1891 return -EPERM; 1892 1893 ret = pm_runtime_get_sync(ddev->dev); 1894 if (ret < 0) { 1895 pm_runtime_put_autosuspend(ddev->dev); 1896 return ret; 1897 } 1898 1899 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1900 if (size <= 0) 1901 goto out; 1902 1903 if (size >= PAGE_SIZE) 1904 size = PAGE_SIZE - 1; 1905 1906 memcpy(buf, gpu_metrics, size); 1907 1908 out: 1909 pm_runtime_mark_last_busy(ddev->dev); 1910 pm_runtime_put_autosuspend(ddev->dev); 1911 1912 return size; 1913 } 1914 1915 static int amdgpu_show_powershift_percent(struct device *dev, 1916 char *buf, enum amd_pp_sensors sensor) 1917 { 1918 struct drm_device *ddev = dev_get_drvdata(dev); 1919 struct amdgpu_device *adev = drm_to_adev(ddev); 1920 uint32_t ss_power; 1921 int r = 0, i; 1922 1923 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1924 if (r == -EOPNOTSUPP) { 1925 /* sensor not available on dGPU, try to read from APU */ 1926 adev = NULL; 1927 mutex_lock(&mgpu_info.mutex); 1928 for (i = 0; i < mgpu_info.num_gpu; i++) { 1929 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { 1930 adev = mgpu_info.gpu_ins[i].adev; 1931 break; 1932 } 1933 } 1934 mutex_unlock(&mgpu_info.mutex); 1935 if (adev) 1936 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); 1937 } 1938 1939 if (r) 1940 return r; 1941 1942 return sysfs_emit(buf, "%u%%\n", ss_power); 1943 } 1944 1945 /** 1946 * DOC: smartshift_apu_power 1947 * 1948 * The amdgpu driver provides a sysfs API for reporting APU power 1949 * shift in percentage if platform supports smartshift. Value 0 means that 1950 * there is no powershift and values between [1-100] means that the power 1951 * is shifted to APU, the percentage of boost is with respect to APU power 1952 * limit on the platform. 1953 */ 1954 1955 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, 1956 char *buf) 1957 { 1958 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE); 1959 } 1960 1961 /** 1962 * DOC: smartshift_dgpu_power 1963 * 1964 * The amdgpu driver provides a sysfs API for reporting dGPU power 1965 * shift in percentage if platform supports smartshift. Value 0 means that 1966 * there is no powershift and values between [1-100] means that the power is 1967 * shifted to dGPU, the percentage of boost is with respect to dGPU power 1968 * limit on the platform. 1969 */ 1970 1971 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, 1972 char *buf) 1973 { 1974 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE); 1975 } 1976 1977 /** 1978 * DOC: smartshift_bias 1979 * 1980 * The amdgpu driver provides a sysfs API for reporting the 1981 * smartshift(SS2.0) bias level. The value ranges from -100 to 100 1982 * and the default is 0. -100 sets maximum preference to APU 1983 * and 100 sets max perference to dGPU. 1984 */ 1985 1986 static ssize_t amdgpu_get_smartshift_bias(struct device *dev, 1987 struct device_attribute *attr, 1988 char *buf) 1989 { 1990 int r = 0; 1991 1992 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); 1993 1994 return r; 1995 } 1996 1997 static ssize_t amdgpu_set_smartshift_bias(struct device *dev, 1998 struct device_attribute *attr, 1999 const char *buf, size_t count) 2000 { 2001 struct drm_device *ddev = dev_get_drvdata(dev); 2002 struct amdgpu_device *adev = drm_to_adev(ddev); 2003 int r = 0; 2004 int bias = 0; 2005 2006 if (amdgpu_in_reset(adev)) 2007 return -EPERM; 2008 if (adev->in_suspend && !adev->in_runpm) 2009 return -EPERM; 2010 2011 r = pm_runtime_get_sync(ddev->dev); 2012 if (r < 0) { 2013 pm_runtime_put_autosuspend(ddev->dev); 2014 return r; 2015 } 2016 2017 r = kstrtoint(buf, 10, &bias); 2018 if (r) 2019 goto out; 2020 2021 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) 2022 bias = AMDGPU_SMARTSHIFT_MAX_BIAS; 2023 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) 2024 bias = AMDGPU_SMARTSHIFT_MIN_BIAS; 2025 2026 amdgpu_smartshift_bias = bias; 2027 r = count; 2028 2029 /* TODO: update bias level with SMU message */ 2030 2031 out: 2032 pm_runtime_mark_last_busy(ddev->dev); 2033 pm_runtime_put_autosuspend(ddev->dev); 2034 return r; 2035 } 2036 2037 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2038 uint32_t mask, enum amdgpu_device_attr_states *states) 2039 { 2040 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 2041 *states = ATTR_STATE_UNSUPPORTED; 2042 2043 return 0; 2044 } 2045 2046 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2047 uint32_t mask, enum amdgpu_device_attr_states *states) 2048 { 2049 uint32_t ss_power; 2050 2051 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 2052 *states = ATTR_STATE_UNSUPPORTED; 2053 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 2054 (void *)&ss_power)) 2055 *states = ATTR_STATE_UNSUPPORTED; 2056 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 2057 (void *)&ss_power)) 2058 *states = ATTR_STATE_UNSUPPORTED; 2059 2060 return 0; 2061 } 2062 2063 static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2064 uint32_t mask, enum amdgpu_device_attr_states *states) 2065 { 2066 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2067 2068 *states = ATTR_STATE_SUPPORTED; 2069 2070 if (!amdgpu_dpm_is_overdrive_supported(adev)) { 2071 *states = ATTR_STATE_UNSUPPORTED; 2072 return 0; 2073 } 2074 2075 /* Enable pp_od_clk_voltage node for gc 9.4.3 SRIOV/BM support */ 2076 if (gc_ver == IP_VERSION(9, 4, 3)) { 2077 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2078 *states = ATTR_STATE_UNSUPPORTED; 2079 return 0; 2080 } 2081 2082 if (!(attr->flags & mask)) 2083 *states = ATTR_STATE_UNSUPPORTED; 2084 2085 return 0; 2086 } 2087 2088 static int pp_dpm_dcefclk_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2089 uint32_t mask, enum amdgpu_device_attr_states *states) 2090 { 2091 struct device_attribute *dev_attr = &attr->dev_attr; 2092 uint32_t gc_ver; 2093 2094 *states = ATTR_STATE_SUPPORTED; 2095 2096 if (!(attr->flags & mask)) { 2097 *states = ATTR_STATE_UNSUPPORTED; 2098 return 0; 2099 } 2100 2101 gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2102 /* dcefclk node is not available on gfx 11.0.3 sriov */ 2103 if ((gc_ver == IP_VERSION(11, 0, 3) && amdgpu_sriov_is_pp_one_vf(adev)) || 2104 gc_ver < IP_VERSION(9, 0, 0) || 2105 !amdgpu_device_has_display_hardware(adev)) 2106 *states = ATTR_STATE_UNSUPPORTED; 2107 2108 /* SMU MP1 does not support dcefclk level setting, 2109 * setting should not be allowed from VF if not in one VF mode. 2110 */ 2111 if (gc_ver >= IP_VERSION(10, 0, 0) || 2112 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))) { 2113 dev_attr->attr.mode &= ~S_IWUGO; 2114 dev_attr->store = NULL; 2115 } 2116 2117 return 0; 2118 } 2119 2120 static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2121 uint32_t mask, enum amdgpu_device_attr_states *states) 2122 { 2123 struct device_attribute *dev_attr = &attr->dev_attr; 2124 enum amdgpu_device_attr_id attr_id = attr->attr_id; 2125 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0); 2126 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2127 2128 *states = ATTR_STATE_SUPPORTED; 2129 2130 if (!(attr->flags & mask)) { 2131 *states = ATTR_STATE_UNSUPPORTED; 2132 return 0; 2133 } 2134 2135 if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 2136 if (gc_ver < IP_VERSION(9, 0, 0)) 2137 *states = ATTR_STATE_UNSUPPORTED; 2138 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 2139 if (mp1_ver < IP_VERSION(10, 0, 0)) 2140 *states = ATTR_STATE_UNSUPPORTED; 2141 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 2142 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2143 gc_ver == IP_VERSION(10, 3, 3) || 2144 gc_ver == IP_VERSION(10, 3, 6) || 2145 gc_ver == IP_VERSION(10, 3, 7) || 2146 gc_ver == IP_VERSION(10, 3, 0) || 2147 gc_ver == IP_VERSION(10, 1, 2) || 2148 gc_ver == IP_VERSION(11, 0, 0) || 2149 gc_ver == IP_VERSION(11, 0, 1) || 2150 gc_ver == IP_VERSION(11, 0, 4) || 2151 gc_ver == IP_VERSION(11, 5, 0) || 2152 gc_ver == IP_VERSION(11, 0, 2) || 2153 gc_ver == IP_VERSION(11, 0, 3) || 2154 gc_ver == IP_VERSION(9, 4, 3))) 2155 *states = ATTR_STATE_UNSUPPORTED; 2156 } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { 2157 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2158 gc_ver == IP_VERSION(10, 3, 0) || 2159 gc_ver == IP_VERSION(11, 0, 2) || 2160 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2161 *states = ATTR_STATE_UNSUPPORTED; 2162 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 2163 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2164 gc_ver == IP_VERSION(10, 3, 3) || 2165 gc_ver == IP_VERSION(10, 3, 6) || 2166 gc_ver == IP_VERSION(10, 3, 7) || 2167 gc_ver == IP_VERSION(10, 3, 0) || 2168 gc_ver == IP_VERSION(10, 1, 2) || 2169 gc_ver == IP_VERSION(11, 0, 0) || 2170 gc_ver == IP_VERSION(11, 0, 1) || 2171 gc_ver == IP_VERSION(11, 0, 4) || 2172 gc_ver == IP_VERSION(11, 5, 0) || 2173 gc_ver == IP_VERSION(11, 0, 2) || 2174 gc_ver == IP_VERSION(11, 0, 3) || 2175 gc_ver == IP_VERSION(9, 4, 3))) 2176 *states = ATTR_STATE_UNSUPPORTED; 2177 } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { 2178 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2179 gc_ver == IP_VERSION(10, 3, 0) || 2180 gc_ver == IP_VERSION(11, 0, 2) || 2181 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2182 *states = ATTR_STATE_UNSUPPORTED; 2183 } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { 2184 if (gc_ver == IP_VERSION(9, 4, 2) || 2185 gc_ver == IP_VERSION(9, 4, 3)) 2186 *states = ATTR_STATE_UNSUPPORTED; 2187 } 2188 2189 switch (gc_ver) { 2190 case IP_VERSION(9, 4, 1): 2191 case IP_VERSION(9, 4, 2): 2192 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 2193 if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2194 DEVICE_ATTR_IS(pp_dpm_socclk) || 2195 DEVICE_ATTR_IS(pp_dpm_fclk)) { 2196 dev_attr->attr.mode &= ~S_IWUGO; 2197 dev_attr->store = NULL; 2198 } 2199 break; 2200 default: 2201 break; 2202 } 2203 2204 /* setting should not be allowed from VF if not in one VF mode */ 2205 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_is_pp_one_vf(adev)) { 2206 dev_attr->attr.mode &= ~S_IWUGO; 2207 dev_attr->store = NULL; 2208 } 2209 2210 return 0; 2211 } 2212 2213 /* Following items will be read out to indicate current plpd policy: 2214 * - -1: none 2215 * - 0: disallow 2216 * - 1: default 2217 * - 2: optimized 2218 */ 2219 static ssize_t amdgpu_get_xgmi_plpd_policy(struct device *dev, 2220 struct device_attribute *attr, 2221 char *buf) 2222 { 2223 struct drm_device *ddev = dev_get_drvdata(dev); 2224 struct amdgpu_device *adev = drm_to_adev(ddev); 2225 char *mode_desc = "none"; 2226 int mode; 2227 2228 if (amdgpu_in_reset(adev)) 2229 return -EPERM; 2230 if (adev->in_suspend && !adev->in_runpm) 2231 return -EPERM; 2232 2233 mode = amdgpu_dpm_get_xgmi_plpd_mode(adev, &mode_desc); 2234 2235 return sysfs_emit(buf, "%d: %s\n", mode, mode_desc); 2236 } 2237 2238 /* Following argument value is expected from user to change plpd policy 2239 * - arg 0: disallow plpd 2240 * - arg 1: default policy 2241 * - arg 2: optimized policy 2242 */ 2243 static ssize_t amdgpu_set_xgmi_plpd_policy(struct device *dev, 2244 struct device_attribute *attr, 2245 const char *buf, size_t count) 2246 { 2247 struct drm_device *ddev = dev_get_drvdata(dev); 2248 struct amdgpu_device *adev = drm_to_adev(ddev); 2249 int mode, ret; 2250 2251 if (amdgpu_in_reset(adev)) 2252 return -EPERM; 2253 if (adev->in_suspend && !adev->in_runpm) 2254 return -EPERM; 2255 2256 ret = kstrtos32(buf, 0, &mode); 2257 if (ret) 2258 return -EINVAL; 2259 2260 ret = pm_runtime_get_sync(ddev->dev); 2261 if (ret < 0) { 2262 pm_runtime_put_autosuspend(ddev->dev); 2263 return ret; 2264 } 2265 2266 ret = amdgpu_dpm_set_xgmi_plpd_mode(adev, mode); 2267 2268 pm_runtime_mark_last_busy(ddev->dev); 2269 pm_runtime_put_autosuspend(ddev->dev); 2270 2271 if (ret) 2272 return ret; 2273 2274 return count; 2275 } 2276 2277 static struct amdgpu_device_attr amdgpu_device_attrs[] = { 2278 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2279 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2280 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2281 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2282 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2283 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2284 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2285 .attr_update = pp_dpm_clk_default_attr_update), 2286 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2287 .attr_update = pp_dpm_clk_default_attr_update), 2288 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2289 .attr_update = pp_dpm_clk_default_attr_update), 2290 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2291 .attr_update = pp_dpm_clk_default_attr_update), 2292 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2293 .attr_update = pp_dpm_clk_default_attr_update), 2294 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2295 .attr_update = pp_dpm_clk_default_attr_update), 2296 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2297 .attr_update = pp_dpm_clk_default_attr_update), 2298 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2299 .attr_update = pp_dpm_clk_default_attr_update), 2300 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2301 .attr_update = pp_dpm_dcefclk_attr_update), 2302 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF, 2303 .attr_update = pp_dpm_clk_default_attr_update), 2304 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 2305 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 2306 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2307 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC, 2308 .attr_update = pp_od_clk_voltage_attr_update), 2309 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2310 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2311 AMDGPU_DEVICE_ATTR_RO(vcn_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2312 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 2313 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2314 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2315 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2316 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2317 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2318 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, 2319 .attr_update = ss_power_attr_update), 2320 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, 2321 .attr_update = ss_power_attr_update), 2322 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, 2323 .attr_update = ss_bias_attr_update), 2324 AMDGPU_DEVICE_ATTR_RW(xgmi_plpd_policy, ATTR_FLAG_BASIC), 2325 AMDGPU_DEVICE_ATTR_RO(pm_metrics, ATTR_FLAG_BASIC, 2326 .attr_update = amdgpu_pm_metrics_attr_update), 2327 }; 2328 2329 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2330 uint32_t mask, enum amdgpu_device_attr_states *states) 2331 { 2332 struct device_attribute *dev_attr = &attr->dev_attr; 2333 enum amdgpu_device_attr_id attr_id = attr->attr_id; 2334 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 2335 2336 if (!(attr->flags & mask)) { 2337 *states = ATTR_STATE_UNSUPPORTED; 2338 return 0; 2339 } 2340 2341 if (DEVICE_ATTR_IS(mem_busy_percent)) { 2342 if ((adev->flags & AMD_IS_APU && 2343 gc_ver != IP_VERSION(9, 4, 3)) || 2344 gc_ver == IP_VERSION(9, 0, 1)) 2345 *states = ATTR_STATE_UNSUPPORTED; 2346 } else if (DEVICE_ATTR_IS(vcn_busy_percent)) { 2347 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2348 gc_ver == IP_VERSION(10, 3, 3) || 2349 gc_ver == IP_VERSION(10, 3, 6) || 2350 gc_ver == IP_VERSION(10, 3, 7) || 2351 gc_ver == IP_VERSION(11, 0, 1) || 2352 gc_ver == IP_VERSION(11, 0, 4) || 2353 gc_ver == IP_VERSION(11, 5, 0))) 2354 *states = ATTR_STATE_UNSUPPORTED; 2355 } else if (DEVICE_ATTR_IS(pcie_bw)) { 2356 /* PCIe Perf counters won't work on APU nodes */ 2357 if (adev->flags & AMD_IS_APU || 2358 !adev->asic_funcs->get_pcie_usage) 2359 *states = ATTR_STATE_UNSUPPORTED; 2360 } else if (DEVICE_ATTR_IS(unique_id)) { 2361 switch (gc_ver) { 2362 case IP_VERSION(9, 0, 1): 2363 case IP_VERSION(9, 4, 0): 2364 case IP_VERSION(9, 4, 1): 2365 case IP_VERSION(9, 4, 2): 2366 case IP_VERSION(9, 4, 3): 2367 case IP_VERSION(10, 3, 0): 2368 case IP_VERSION(11, 0, 0): 2369 case IP_VERSION(11, 0, 1): 2370 case IP_VERSION(11, 0, 2): 2371 case IP_VERSION(11, 0, 3): 2372 *states = ATTR_STATE_SUPPORTED; 2373 break; 2374 default: 2375 *states = ATTR_STATE_UNSUPPORTED; 2376 } 2377 } else if (DEVICE_ATTR_IS(pp_features)) { 2378 if ((adev->flags & AMD_IS_APU && 2379 gc_ver != IP_VERSION(9, 4, 3)) || 2380 gc_ver < IP_VERSION(9, 0, 0)) 2381 *states = ATTR_STATE_UNSUPPORTED; 2382 } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2383 if (gc_ver < IP_VERSION(9, 1, 0)) 2384 *states = ATTR_STATE_UNSUPPORTED; 2385 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { 2386 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) 2387 *states = ATTR_STATE_UNSUPPORTED; 2388 else if ((gc_ver == IP_VERSION(10, 3, 0) || 2389 gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev)) 2390 *states = ATTR_STATE_UNSUPPORTED; 2391 } else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) { 2392 if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE) 2393 *states = ATTR_STATE_UNSUPPORTED; 2394 } else if (DEVICE_ATTR_IS(pp_mclk_od)) { 2395 if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP) 2396 *states = ATTR_STATE_UNSUPPORTED; 2397 } else if (DEVICE_ATTR_IS(pp_sclk_od)) { 2398 if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP) 2399 *states = ATTR_STATE_UNSUPPORTED; 2400 } else if (DEVICE_ATTR_IS(apu_thermal_cap)) { 2401 u32 limit; 2402 2403 if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) == 2404 -EOPNOTSUPP) 2405 *states = ATTR_STATE_UNSUPPORTED; 2406 } 2407 2408 switch (gc_ver) { 2409 case IP_VERSION(10, 3, 0): 2410 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) && 2411 amdgpu_sriov_vf(adev)) { 2412 dev_attr->attr.mode &= ~0222; 2413 dev_attr->store = NULL; 2414 } 2415 break; 2416 default: 2417 break; 2418 } 2419 2420 return 0; 2421 } 2422 2423 2424 static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2425 struct amdgpu_device_attr *attr, 2426 uint32_t mask, struct list_head *attr_list) 2427 { 2428 int ret = 0; 2429 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2430 struct amdgpu_device_attr_entry *attr_entry; 2431 struct device_attribute *dev_attr; 2432 const char *name; 2433 2434 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2435 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2436 2437 if (!attr) 2438 return -EINVAL; 2439 2440 dev_attr = &attr->dev_attr; 2441 name = dev_attr->attr.name; 2442 2443 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; 2444 2445 ret = attr_update(adev, attr, mask, &attr_states); 2446 if (ret) { 2447 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2448 name, ret); 2449 return ret; 2450 } 2451 2452 if (attr_states == ATTR_STATE_UNSUPPORTED) 2453 return 0; 2454 2455 ret = device_create_file(adev->dev, dev_attr); 2456 if (ret) { 2457 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2458 name, ret); 2459 } 2460 2461 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2462 if (!attr_entry) 2463 return -ENOMEM; 2464 2465 attr_entry->attr = attr; 2466 INIT_LIST_HEAD(&attr_entry->entry); 2467 2468 list_add_tail(&attr_entry->entry, attr_list); 2469 2470 return ret; 2471 } 2472 2473 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2474 { 2475 struct device_attribute *dev_attr = &attr->dev_attr; 2476 2477 device_remove_file(adev->dev, dev_attr); 2478 } 2479 2480 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2481 struct list_head *attr_list); 2482 2483 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2484 struct amdgpu_device_attr *attrs, 2485 uint32_t counts, 2486 uint32_t mask, 2487 struct list_head *attr_list) 2488 { 2489 int ret = 0; 2490 uint32_t i = 0; 2491 2492 for (i = 0; i < counts; i++) { 2493 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2494 if (ret) 2495 goto failed; 2496 } 2497 2498 return 0; 2499 2500 failed: 2501 amdgpu_device_attr_remove_groups(adev, attr_list); 2502 2503 return ret; 2504 } 2505 2506 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2507 struct list_head *attr_list) 2508 { 2509 struct amdgpu_device_attr_entry *entry, *entry_tmp; 2510 2511 if (list_empty(attr_list)) 2512 return ; 2513 2514 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2515 amdgpu_device_attr_remove(adev, entry->attr); 2516 list_del(&entry->entry); 2517 kfree(entry); 2518 } 2519 } 2520 2521 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2522 struct device_attribute *attr, 2523 char *buf) 2524 { 2525 struct amdgpu_device *adev = dev_get_drvdata(dev); 2526 int channel = to_sensor_dev_attr(attr)->index; 2527 int r, temp = 0; 2528 2529 if (channel >= PP_TEMP_MAX) 2530 return -EINVAL; 2531 2532 switch (channel) { 2533 case PP_TEMP_JUNCTION: 2534 /* get current junction temperature */ 2535 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2536 (void *)&temp); 2537 break; 2538 case PP_TEMP_EDGE: 2539 /* get current edge temperature */ 2540 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2541 (void *)&temp); 2542 break; 2543 case PP_TEMP_MEM: 2544 /* get current memory temperature */ 2545 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2546 (void *)&temp); 2547 break; 2548 default: 2549 r = -EINVAL; 2550 break; 2551 } 2552 2553 if (r) 2554 return r; 2555 2556 return sysfs_emit(buf, "%d\n", temp); 2557 } 2558 2559 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2560 struct device_attribute *attr, 2561 char *buf) 2562 { 2563 struct amdgpu_device *adev = dev_get_drvdata(dev); 2564 int hyst = to_sensor_dev_attr(attr)->index; 2565 int temp; 2566 2567 if (hyst) 2568 temp = adev->pm.dpm.thermal.min_temp; 2569 else 2570 temp = adev->pm.dpm.thermal.max_temp; 2571 2572 return sysfs_emit(buf, "%d\n", temp); 2573 } 2574 2575 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2576 struct device_attribute *attr, 2577 char *buf) 2578 { 2579 struct amdgpu_device *adev = dev_get_drvdata(dev); 2580 int hyst = to_sensor_dev_attr(attr)->index; 2581 int temp; 2582 2583 if (hyst) 2584 temp = adev->pm.dpm.thermal.min_hotspot_temp; 2585 else 2586 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2587 2588 return sysfs_emit(buf, "%d\n", temp); 2589 } 2590 2591 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2592 struct device_attribute *attr, 2593 char *buf) 2594 { 2595 struct amdgpu_device *adev = dev_get_drvdata(dev); 2596 int hyst = to_sensor_dev_attr(attr)->index; 2597 int temp; 2598 2599 if (hyst) 2600 temp = adev->pm.dpm.thermal.min_mem_temp; 2601 else 2602 temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2603 2604 return sysfs_emit(buf, "%d\n", temp); 2605 } 2606 2607 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2608 struct device_attribute *attr, 2609 char *buf) 2610 { 2611 int channel = to_sensor_dev_attr(attr)->index; 2612 2613 if (channel >= PP_TEMP_MAX) 2614 return -EINVAL; 2615 2616 return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2617 } 2618 2619 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2620 struct device_attribute *attr, 2621 char *buf) 2622 { 2623 struct amdgpu_device *adev = dev_get_drvdata(dev); 2624 int channel = to_sensor_dev_attr(attr)->index; 2625 int temp = 0; 2626 2627 if (channel >= PP_TEMP_MAX) 2628 return -EINVAL; 2629 2630 switch (channel) { 2631 case PP_TEMP_JUNCTION: 2632 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2633 break; 2634 case PP_TEMP_EDGE: 2635 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2636 break; 2637 case PP_TEMP_MEM: 2638 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2639 break; 2640 } 2641 2642 return sysfs_emit(buf, "%d\n", temp); 2643 } 2644 2645 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2646 struct device_attribute *attr, 2647 char *buf) 2648 { 2649 struct amdgpu_device *adev = dev_get_drvdata(dev); 2650 u32 pwm_mode = 0; 2651 int ret; 2652 2653 if (amdgpu_in_reset(adev)) 2654 return -EPERM; 2655 if (adev->in_suspend && !adev->in_runpm) 2656 return -EPERM; 2657 2658 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2659 if (ret < 0) { 2660 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2661 return ret; 2662 } 2663 2664 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2665 2666 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2667 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2668 2669 if (ret) 2670 return -EINVAL; 2671 2672 return sysfs_emit(buf, "%u\n", pwm_mode); 2673 } 2674 2675 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2676 struct device_attribute *attr, 2677 const char *buf, 2678 size_t count) 2679 { 2680 struct amdgpu_device *adev = dev_get_drvdata(dev); 2681 int err, ret; 2682 u32 pwm_mode; 2683 int value; 2684 2685 if (amdgpu_in_reset(adev)) 2686 return -EPERM; 2687 if (adev->in_suspend && !adev->in_runpm) 2688 return -EPERM; 2689 2690 err = kstrtoint(buf, 10, &value); 2691 if (err) 2692 return err; 2693 2694 if (value == 0) 2695 pwm_mode = AMD_FAN_CTRL_NONE; 2696 else if (value == 1) 2697 pwm_mode = AMD_FAN_CTRL_MANUAL; 2698 else if (value == 2) 2699 pwm_mode = AMD_FAN_CTRL_AUTO; 2700 else 2701 return -EINVAL; 2702 2703 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2704 if (ret < 0) { 2705 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2706 return ret; 2707 } 2708 2709 ret = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2710 2711 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2712 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2713 2714 if (ret) 2715 return -EINVAL; 2716 2717 return count; 2718 } 2719 2720 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2721 struct device_attribute *attr, 2722 char *buf) 2723 { 2724 return sysfs_emit(buf, "%i\n", 0); 2725 } 2726 2727 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2728 struct device_attribute *attr, 2729 char *buf) 2730 { 2731 return sysfs_emit(buf, "%i\n", 255); 2732 } 2733 2734 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2735 struct device_attribute *attr, 2736 const char *buf, size_t count) 2737 { 2738 struct amdgpu_device *adev = dev_get_drvdata(dev); 2739 int err; 2740 u32 value; 2741 u32 pwm_mode; 2742 2743 if (amdgpu_in_reset(adev)) 2744 return -EPERM; 2745 if (adev->in_suspend && !adev->in_runpm) 2746 return -EPERM; 2747 2748 err = kstrtou32(buf, 10, &value); 2749 if (err) 2750 return err; 2751 2752 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2753 if (err < 0) { 2754 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2755 return err; 2756 } 2757 2758 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2759 if (err) 2760 goto out; 2761 2762 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2763 pr_info("manual fan speed control should be enabled first\n"); 2764 err = -EINVAL; 2765 goto out; 2766 } 2767 2768 err = amdgpu_dpm_set_fan_speed_pwm(adev, value); 2769 2770 out: 2771 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2772 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2773 2774 if (err) 2775 return err; 2776 2777 return count; 2778 } 2779 2780 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2781 struct device_attribute *attr, 2782 char *buf) 2783 { 2784 struct amdgpu_device *adev = dev_get_drvdata(dev); 2785 int err; 2786 u32 speed = 0; 2787 2788 if (amdgpu_in_reset(adev)) 2789 return -EPERM; 2790 if (adev->in_suspend && !adev->in_runpm) 2791 return -EPERM; 2792 2793 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2794 if (err < 0) { 2795 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2796 return err; 2797 } 2798 2799 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); 2800 2801 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2802 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2803 2804 if (err) 2805 return err; 2806 2807 return sysfs_emit(buf, "%i\n", speed); 2808 } 2809 2810 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2811 struct device_attribute *attr, 2812 char *buf) 2813 { 2814 struct amdgpu_device *adev = dev_get_drvdata(dev); 2815 int err; 2816 u32 speed = 0; 2817 2818 if (amdgpu_in_reset(adev)) 2819 return -EPERM; 2820 if (adev->in_suspend && !adev->in_runpm) 2821 return -EPERM; 2822 2823 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2824 if (err < 0) { 2825 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2826 return err; 2827 } 2828 2829 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2830 2831 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2832 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2833 2834 if (err) 2835 return err; 2836 2837 return sysfs_emit(buf, "%i\n", speed); 2838 } 2839 2840 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2841 struct device_attribute *attr, 2842 char *buf) 2843 { 2844 struct amdgpu_device *adev = dev_get_drvdata(dev); 2845 u32 min_rpm = 0; 2846 int r; 2847 2848 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2849 (void *)&min_rpm); 2850 2851 if (r) 2852 return r; 2853 2854 return sysfs_emit(buf, "%d\n", min_rpm); 2855 } 2856 2857 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2858 struct device_attribute *attr, 2859 char *buf) 2860 { 2861 struct amdgpu_device *adev = dev_get_drvdata(dev); 2862 u32 max_rpm = 0; 2863 int r; 2864 2865 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2866 (void *)&max_rpm); 2867 2868 if (r) 2869 return r; 2870 2871 return sysfs_emit(buf, "%d\n", max_rpm); 2872 } 2873 2874 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2875 struct device_attribute *attr, 2876 char *buf) 2877 { 2878 struct amdgpu_device *adev = dev_get_drvdata(dev); 2879 int err; 2880 u32 rpm = 0; 2881 2882 if (amdgpu_in_reset(adev)) 2883 return -EPERM; 2884 if (adev->in_suspend && !adev->in_runpm) 2885 return -EPERM; 2886 2887 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2888 if (err < 0) { 2889 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2890 return err; 2891 } 2892 2893 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2894 2895 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2896 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2897 2898 if (err) 2899 return err; 2900 2901 return sysfs_emit(buf, "%i\n", rpm); 2902 } 2903 2904 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2905 struct device_attribute *attr, 2906 const char *buf, size_t count) 2907 { 2908 struct amdgpu_device *adev = dev_get_drvdata(dev); 2909 int err; 2910 u32 value; 2911 u32 pwm_mode; 2912 2913 if (amdgpu_in_reset(adev)) 2914 return -EPERM; 2915 if (adev->in_suspend && !adev->in_runpm) 2916 return -EPERM; 2917 2918 err = kstrtou32(buf, 10, &value); 2919 if (err) 2920 return err; 2921 2922 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2923 if (err < 0) { 2924 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2925 return err; 2926 } 2927 2928 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2929 if (err) 2930 goto out; 2931 2932 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2933 err = -ENODATA; 2934 goto out; 2935 } 2936 2937 err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2938 2939 out: 2940 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2941 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2942 2943 if (err) 2944 return err; 2945 2946 return count; 2947 } 2948 2949 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2950 struct device_attribute *attr, 2951 char *buf) 2952 { 2953 struct amdgpu_device *adev = dev_get_drvdata(dev); 2954 u32 pwm_mode = 0; 2955 int ret; 2956 2957 if (amdgpu_in_reset(adev)) 2958 return -EPERM; 2959 if (adev->in_suspend && !adev->in_runpm) 2960 return -EPERM; 2961 2962 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2963 if (ret < 0) { 2964 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2965 return ret; 2966 } 2967 2968 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2969 2970 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2971 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2972 2973 if (ret) 2974 return -EINVAL; 2975 2976 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2977 } 2978 2979 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2980 struct device_attribute *attr, 2981 const char *buf, 2982 size_t count) 2983 { 2984 struct amdgpu_device *adev = dev_get_drvdata(dev); 2985 int err; 2986 int value; 2987 u32 pwm_mode; 2988 2989 if (amdgpu_in_reset(adev)) 2990 return -EPERM; 2991 if (adev->in_suspend && !adev->in_runpm) 2992 return -EPERM; 2993 2994 err = kstrtoint(buf, 10, &value); 2995 if (err) 2996 return err; 2997 2998 if (value == 0) 2999 pwm_mode = AMD_FAN_CTRL_AUTO; 3000 else if (value == 1) 3001 pwm_mode = AMD_FAN_CTRL_MANUAL; 3002 else 3003 return -EINVAL; 3004 3005 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3006 if (err < 0) { 3007 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3008 return err; 3009 } 3010 3011 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 3012 3013 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3014 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3015 3016 if (err) 3017 return -EINVAL; 3018 3019 return count; 3020 } 3021 3022 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 3023 struct device_attribute *attr, 3024 char *buf) 3025 { 3026 struct amdgpu_device *adev = dev_get_drvdata(dev); 3027 u32 vddgfx; 3028 int r; 3029 3030 /* get the voltage */ 3031 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX, 3032 (void *)&vddgfx); 3033 if (r) 3034 return r; 3035 3036 return sysfs_emit(buf, "%d\n", vddgfx); 3037 } 3038 3039 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 3040 struct device_attribute *attr, 3041 char *buf) 3042 { 3043 return sysfs_emit(buf, "vddgfx\n"); 3044 } 3045 3046 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 3047 struct device_attribute *attr, 3048 char *buf) 3049 { 3050 struct amdgpu_device *adev = dev_get_drvdata(dev); 3051 u32 vddnb; 3052 int r; 3053 3054 /* only APUs have vddnb */ 3055 if (!(adev->flags & AMD_IS_APU)) 3056 return -EINVAL; 3057 3058 /* get the voltage */ 3059 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB, 3060 (void *)&vddnb); 3061 if (r) 3062 return r; 3063 3064 return sysfs_emit(buf, "%d\n", vddnb); 3065 } 3066 3067 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 3068 struct device_attribute *attr, 3069 char *buf) 3070 { 3071 return sysfs_emit(buf, "vddnb\n"); 3072 } 3073 3074 static int amdgpu_hwmon_get_power(struct device *dev, 3075 enum amd_pp_sensors sensor) 3076 { 3077 struct amdgpu_device *adev = dev_get_drvdata(dev); 3078 unsigned int uw; 3079 u32 query = 0; 3080 int r; 3081 3082 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query); 3083 if (r) 3084 return r; 3085 3086 /* convert to microwatts */ 3087 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 3088 3089 return uw; 3090 } 3091 3092 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 3093 struct device_attribute *attr, 3094 char *buf) 3095 { 3096 ssize_t val; 3097 3098 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER); 3099 if (val < 0) 3100 return val; 3101 3102 return sysfs_emit(buf, "%zd\n", val); 3103 } 3104 3105 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev, 3106 struct device_attribute *attr, 3107 char *buf) 3108 { 3109 ssize_t val; 3110 3111 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER); 3112 if (val < 0) 3113 return val; 3114 3115 return sysfs_emit(buf, "%zd\n", val); 3116 } 3117 3118 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, 3119 struct device_attribute *attr, 3120 char *buf, 3121 enum pp_power_limit_level pp_limit_level) 3122 { 3123 struct amdgpu_device *adev = dev_get_drvdata(dev); 3124 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; 3125 uint32_t limit; 3126 ssize_t size; 3127 int r; 3128 3129 if (amdgpu_in_reset(adev)) 3130 return -EPERM; 3131 if (adev->in_suspend && !adev->in_runpm) 3132 return -EPERM; 3133 3134 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3135 if (r < 0) { 3136 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3137 return r; 3138 } 3139 3140 r = amdgpu_dpm_get_power_limit(adev, &limit, 3141 pp_limit_level, power_type); 3142 3143 if (!r) 3144 size = sysfs_emit(buf, "%u\n", limit * 1000000); 3145 else 3146 size = sysfs_emit(buf, "\n"); 3147 3148 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3149 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3150 3151 return size; 3152 } 3153 3154 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 3155 struct device_attribute *attr, 3156 char *buf) 3157 { 3158 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN); 3159 } 3160 3161 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 3162 struct device_attribute *attr, 3163 char *buf) 3164 { 3165 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); 3166 3167 } 3168 3169 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 3170 struct device_attribute *attr, 3171 char *buf) 3172 { 3173 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); 3174 3175 } 3176 3177 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 3178 struct device_attribute *attr, 3179 char *buf) 3180 { 3181 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); 3182 3183 } 3184 3185 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 3186 struct device_attribute *attr, 3187 char *buf) 3188 { 3189 struct amdgpu_device *adev = dev_get_drvdata(dev); 3190 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 3191 3192 if (gc_ver == IP_VERSION(10, 3, 1)) 3193 return sysfs_emit(buf, "%s\n", 3194 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? 3195 "fastPPT" : "slowPPT"); 3196 else 3197 return sysfs_emit(buf, "PPT\n"); 3198 } 3199 3200 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 3201 struct device_attribute *attr, 3202 const char *buf, 3203 size_t count) 3204 { 3205 struct amdgpu_device *adev = dev_get_drvdata(dev); 3206 int limit_type = to_sensor_dev_attr(attr)->index; 3207 int err; 3208 u32 value; 3209 3210 if (amdgpu_in_reset(adev)) 3211 return -EPERM; 3212 if (adev->in_suspend && !adev->in_runpm) 3213 return -EPERM; 3214 3215 if (amdgpu_sriov_vf(adev)) 3216 return -EINVAL; 3217 3218 err = kstrtou32(buf, 10, &value); 3219 if (err) 3220 return err; 3221 3222 value = value / 1000000; /* convert to Watt */ 3223 value |= limit_type << 24; 3224 3225 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3226 if (err < 0) { 3227 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3228 return err; 3229 } 3230 3231 err = amdgpu_dpm_set_power_limit(adev, value); 3232 3233 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3234 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3235 3236 if (err) 3237 return err; 3238 3239 return count; 3240 } 3241 3242 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 3243 struct device_attribute *attr, 3244 char *buf) 3245 { 3246 struct amdgpu_device *adev = dev_get_drvdata(dev); 3247 uint32_t sclk; 3248 int r; 3249 3250 /* get the sclk */ 3251 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 3252 (void *)&sclk); 3253 if (r) 3254 return r; 3255 3256 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 3257 } 3258 3259 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 3260 struct device_attribute *attr, 3261 char *buf) 3262 { 3263 return sysfs_emit(buf, "sclk\n"); 3264 } 3265 3266 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 3267 struct device_attribute *attr, 3268 char *buf) 3269 { 3270 struct amdgpu_device *adev = dev_get_drvdata(dev); 3271 uint32_t mclk; 3272 int r; 3273 3274 /* get the sclk */ 3275 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 3276 (void *)&mclk); 3277 if (r) 3278 return r; 3279 3280 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 3281 } 3282 3283 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 3284 struct device_attribute *attr, 3285 char *buf) 3286 { 3287 return sysfs_emit(buf, "mclk\n"); 3288 } 3289 3290 /** 3291 * DOC: hwmon 3292 * 3293 * The amdgpu driver exposes the following sensor interfaces: 3294 * 3295 * - GPU temperature (via the on-die sensor) 3296 * 3297 * - GPU voltage 3298 * 3299 * - Northbridge voltage (APUs only) 3300 * 3301 * - GPU power 3302 * 3303 * - GPU fan 3304 * 3305 * - GPU gfx/compute engine clock 3306 * 3307 * - GPU memory clock (dGPU only) 3308 * 3309 * hwmon interfaces for GPU temperature: 3310 * 3311 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3312 * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3313 * 3314 * - temp[1-3]_label: temperature channel label 3315 * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3316 * 3317 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3318 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3319 * 3320 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3321 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3322 * 3323 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3324 * - these are supported on SOC15 dGPUs only 3325 * 3326 * hwmon interfaces for GPU voltage: 3327 * 3328 * - in0_input: the voltage on the GPU in millivolts 3329 * 3330 * - in1_input: the voltage on the Northbridge in millivolts 3331 * 3332 * hwmon interfaces for GPU power: 3333 * 3334 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. 3335 * 3336 * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU. 3337 * 3338 * - power1_cap_min: minimum cap supported in microWatts 3339 * 3340 * - power1_cap_max: maximum cap supported in microWatts 3341 * 3342 * - power1_cap: selected power cap in microWatts 3343 * 3344 * hwmon interfaces for GPU fan: 3345 * 3346 * - pwm1: pulse width modulation fan level (0-255) 3347 * 3348 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3349 * 3350 * - pwm1_min: pulse width modulation fan control minimum level (0) 3351 * 3352 * - pwm1_max: pulse width modulation fan control maximum level (255) 3353 * 3354 * - fan1_min: a minimum value Unit: revolution/min (RPM) 3355 * 3356 * - fan1_max: a maximum value Unit: revolution/max (RPM) 3357 * 3358 * - fan1_input: fan speed in RPM 3359 * 3360 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3361 * 3362 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3363 * 3364 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. 3365 * That will get the former one overridden. 3366 * 3367 * hwmon interfaces for GPU clocks: 3368 * 3369 * - freq1_input: the gfx/compute clock in hertz 3370 * 3371 * - freq2_input: the memory clock in hertz 3372 * 3373 * You can use hwmon tools like sensors to view this information on your system. 3374 * 3375 */ 3376 3377 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3378 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3379 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3380 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3381 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3382 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3383 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3384 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3385 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3386 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3387 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3388 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3389 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3390 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3391 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3392 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3393 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3394 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3395 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3396 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3397 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3398 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3399 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3400 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3401 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3402 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3403 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3404 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3405 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3406 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0); 3407 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3408 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3409 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3410 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3411 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3412 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3413 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3414 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3415 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 3416 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3417 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3418 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3419 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3420 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3421 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3422 3423 static struct attribute *hwmon_attributes[] = { 3424 &sensor_dev_attr_temp1_input.dev_attr.attr, 3425 &sensor_dev_attr_temp1_crit.dev_attr.attr, 3426 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3427 &sensor_dev_attr_temp2_input.dev_attr.attr, 3428 &sensor_dev_attr_temp2_crit.dev_attr.attr, 3429 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3430 &sensor_dev_attr_temp3_input.dev_attr.attr, 3431 &sensor_dev_attr_temp3_crit.dev_attr.attr, 3432 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3433 &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3434 &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3435 &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3436 &sensor_dev_attr_temp1_label.dev_attr.attr, 3437 &sensor_dev_attr_temp2_label.dev_attr.attr, 3438 &sensor_dev_attr_temp3_label.dev_attr.attr, 3439 &sensor_dev_attr_pwm1.dev_attr.attr, 3440 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3441 &sensor_dev_attr_pwm1_min.dev_attr.attr, 3442 &sensor_dev_attr_pwm1_max.dev_attr.attr, 3443 &sensor_dev_attr_fan1_input.dev_attr.attr, 3444 &sensor_dev_attr_fan1_min.dev_attr.attr, 3445 &sensor_dev_attr_fan1_max.dev_attr.attr, 3446 &sensor_dev_attr_fan1_target.dev_attr.attr, 3447 &sensor_dev_attr_fan1_enable.dev_attr.attr, 3448 &sensor_dev_attr_in0_input.dev_attr.attr, 3449 &sensor_dev_attr_in0_label.dev_attr.attr, 3450 &sensor_dev_attr_in1_input.dev_attr.attr, 3451 &sensor_dev_attr_in1_label.dev_attr.attr, 3452 &sensor_dev_attr_power1_average.dev_attr.attr, 3453 &sensor_dev_attr_power1_input.dev_attr.attr, 3454 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3455 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3456 &sensor_dev_attr_power1_cap.dev_attr.attr, 3457 &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3458 &sensor_dev_attr_power1_label.dev_attr.attr, 3459 &sensor_dev_attr_power2_average.dev_attr.attr, 3460 &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3461 &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3462 &sensor_dev_attr_power2_cap.dev_attr.attr, 3463 &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3464 &sensor_dev_attr_power2_label.dev_attr.attr, 3465 &sensor_dev_attr_freq1_input.dev_attr.attr, 3466 &sensor_dev_attr_freq1_label.dev_attr.attr, 3467 &sensor_dev_attr_freq2_input.dev_attr.attr, 3468 &sensor_dev_attr_freq2_label.dev_attr.attr, 3469 NULL 3470 }; 3471 3472 static umode_t hwmon_attributes_visible(struct kobject *kobj, 3473 struct attribute *attr, int index) 3474 { 3475 struct device *dev = kobj_to_dev(kobj); 3476 struct amdgpu_device *adev = dev_get_drvdata(dev); 3477 umode_t effective_mode = attr->mode; 3478 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 3479 uint32_t tmp; 3480 3481 /* under pp one vf mode manage of hwmon attributes is not supported */ 3482 if (amdgpu_sriov_is_pp_one_vf(adev)) 3483 effective_mode &= ~S_IWUSR; 3484 3485 /* Skip fan attributes if fan is not present */ 3486 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3487 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3488 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3489 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3490 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3491 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3492 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3493 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3494 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3495 return 0; 3496 3497 /* Skip fan attributes on APU */ 3498 if ((adev->flags & AMD_IS_APU) && 3499 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3500 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3501 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3502 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3503 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3504 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3505 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3506 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3507 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3508 return 0; 3509 3510 /* Skip crit temp on APU */ 3511 if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || 3512 (gc_ver == IP_VERSION(9, 4, 3))) && 3513 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3514 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3515 return 0; 3516 3517 /* Skip limit attributes if DPM is not enabled */ 3518 if (!adev->pm.dpm_enabled && 3519 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3520 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3521 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3522 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3523 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3524 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3525 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3526 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3527 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3528 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3529 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3530 return 0; 3531 3532 /* mask fan attributes if we have no bindings for this asic to expose */ 3533 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3534 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3535 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && 3536 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3537 effective_mode &= ~S_IRUGO; 3538 3539 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3540 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3541 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && 3542 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3543 effective_mode &= ~S_IWUSR; 3544 3545 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ 3546 if (((adev->family == AMDGPU_FAMILY_SI) || 3547 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && 3548 (gc_ver != IP_VERSION(9, 4, 3)))) && 3549 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3550 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3551 attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3552 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3553 return 0; 3554 3555 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ 3556 if (((adev->family == AMDGPU_FAMILY_SI) || 3557 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && 3558 (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3559 return 0; 3560 3561 /* not all products support both average and instantaneous */ 3562 if (attr == &sensor_dev_attr_power1_average.dev_attr.attr && 3563 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP) 3564 return 0; 3565 if (attr == &sensor_dev_attr_power1_input.dev_attr.attr && 3566 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP) 3567 return 0; 3568 3569 /* hide max/min values if we can't both query and manage the fan */ 3570 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3571 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3572 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3573 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && 3574 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3575 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3576 return 0; 3577 3578 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3579 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && 3580 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3581 attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3582 return 0; 3583 3584 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3585 adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ 3586 (gc_ver == IP_VERSION(9, 4, 3))) && 3587 (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3588 attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3589 return 0; 3590 3591 /* only APUs other than gc 9,4,3 have vddnb */ 3592 if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) && 3593 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3594 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3595 return 0; 3596 3597 /* no mclk on APUs other than gc 9,4,3*/ 3598 if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) && 3599 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3600 attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3601 return 0; 3602 3603 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3604 (gc_ver != IP_VERSION(9, 4, 3)) && 3605 (attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3606 attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3607 attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3608 attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3609 attr == &sensor_dev_attr_temp3_label.dev_attr.attr || 3610 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr)) 3611 return 0; 3612 3613 /* hotspot temperature for gc 9,4,3*/ 3614 if (gc_ver == IP_VERSION(9, 4, 3)) { 3615 if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr || 3616 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3617 attr == &sensor_dev_attr_temp1_label.dev_attr.attr) 3618 return 0; 3619 3620 if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3621 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr) 3622 return attr->mode; 3623 } 3624 3625 /* only SOC15 dGPUs support hotspot and mem temperatures */ 3626 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3627 (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3628 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3629 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3630 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3631 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)) 3632 return 0; 3633 3634 /* only Vangogh has fast PPT limit and power labels */ 3635 if (!(gc_ver == IP_VERSION(10, 3, 1)) && 3636 (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3637 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3638 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3639 attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 3640 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3641 attr == &sensor_dev_attr_power2_label.dev_attr.attr)) 3642 return 0; 3643 3644 return effective_mode; 3645 } 3646 3647 static const struct attribute_group hwmon_attrgroup = { 3648 .attrs = hwmon_attributes, 3649 .is_visible = hwmon_attributes_visible, 3650 }; 3651 3652 static const struct attribute_group *hwmon_groups[] = { 3653 &hwmon_attrgroup, 3654 NULL 3655 }; 3656 3657 static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev, 3658 enum pp_clock_type od_type, 3659 char *buf) 3660 { 3661 int size = 0; 3662 int ret; 3663 3664 if (amdgpu_in_reset(adev)) 3665 return -EPERM; 3666 if (adev->in_suspend && !adev->in_runpm) 3667 return -EPERM; 3668 3669 ret = pm_runtime_get_sync(adev->dev); 3670 if (ret < 0) { 3671 pm_runtime_put_autosuspend(adev->dev); 3672 return ret; 3673 } 3674 3675 size = amdgpu_dpm_print_clock_levels(adev, od_type, buf); 3676 if (size == 0) 3677 size = sysfs_emit(buf, "\n"); 3678 3679 pm_runtime_mark_last_busy(adev->dev); 3680 pm_runtime_put_autosuspend(adev->dev); 3681 3682 return size; 3683 } 3684 3685 static int parse_input_od_command_lines(const char *buf, 3686 size_t count, 3687 u32 *type, 3688 long *params, 3689 uint32_t *num_of_params) 3690 { 3691 const char delimiter[3] = {' ', '\n', '\0'}; 3692 uint32_t parameter_size = 0; 3693 char buf_cpy[128] = {0}; 3694 char *tmp_str, *sub_str; 3695 int ret; 3696 3697 if (count > sizeof(buf_cpy) - 1) 3698 return -EINVAL; 3699 3700 memcpy(buf_cpy, buf, count); 3701 tmp_str = buf_cpy; 3702 3703 /* skip heading spaces */ 3704 while (isspace(*tmp_str)) 3705 tmp_str++; 3706 3707 switch (*tmp_str) { 3708 case 'c': 3709 *type = PP_OD_COMMIT_DPM_TABLE; 3710 return 0; 3711 case 'r': 3712 params[parameter_size] = *type; 3713 *num_of_params = 1; 3714 *type = PP_OD_RESTORE_DEFAULT_TABLE; 3715 return 0; 3716 default: 3717 break; 3718 } 3719 3720 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 3721 if (strlen(sub_str) == 0) 3722 continue; 3723 3724 ret = kstrtol(sub_str, 0, ¶ms[parameter_size]); 3725 if (ret) 3726 return -EINVAL; 3727 parameter_size++; 3728 3729 while (isspace(*tmp_str)) 3730 tmp_str++; 3731 } 3732 3733 *num_of_params = parameter_size; 3734 3735 return 0; 3736 } 3737 3738 static int 3739 amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev, 3740 enum PP_OD_DPM_TABLE_COMMAND cmd_type, 3741 const char *in_buf, 3742 size_t count) 3743 { 3744 uint32_t parameter_size = 0; 3745 long parameter[64]; 3746 int ret; 3747 3748 if (amdgpu_in_reset(adev)) 3749 return -EPERM; 3750 if (adev->in_suspend && !adev->in_runpm) 3751 return -EPERM; 3752 3753 ret = parse_input_od_command_lines(in_buf, 3754 count, 3755 &cmd_type, 3756 parameter, 3757 ¶meter_size); 3758 if (ret) 3759 return ret; 3760 3761 ret = pm_runtime_get_sync(adev->dev); 3762 if (ret < 0) 3763 goto err_out0; 3764 3765 ret = amdgpu_dpm_odn_edit_dpm_table(adev, 3766 cmd_type, 3767 parameter, 3768 parameter_size); 3769 if (ret) 3770 goto err_out1; 3771 3772 if (cmd_type == PP_OD_COMMIT_DPM_TABLE) { 3773 ret = amdgpu_dpm_dispatch_task(adev, 3774 AMD_PP_TASK_READJUST_POWER_STATE, 3775 NULL); 3776 if (ret) 3777 goto err_out1; 3778 } 3779 3780 pm_runtime_mark_last_busy(adev->dev); 3781 pm_runtime_put_autosuspend(adev->dev); 3782 3783 return count; 3784 3785 err_out1: 3786 pm_runtime_mark_last_busy(adev->dev); 3787 err_out0: 3788 pm_runtime_put_autosuspend(adev->dev); 3789 3790 return ret; 3791 } 3792 3793 /** 3794 * DOC: fan_curve 3795 * 3796 * The amdgpu driver provides a sysfs API for checking and adjusting the fan 3797 * control curve line. 3798 * 3799 * Reading back the file shows you the current settings(temperature in Celsius 3800 * degree and fan speed in pwm) applied to every anchor point of the curve line 3801 * and their permitted ranges if changable. 3802 * 3803 * Writing a desired string(with the format like "anchor_point_index temperature 3804 * fan_speed_in_pwm") to the file, change the settings for the specific anchor 3805 * point accordingly. 3806 * 3807 * When you have finished the editing, write "c" (commit) to the file to commit 3808 * your changes. 3809 * 3810 * If you want to reset to the default value, write "r" (reset) to the file to 3811 * reset them 3812 * 3813 * There are two fan control modes supported: auto and manual. With auto mode, 3814 * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature). 3815 * While with manual mode, users can set their own fan curve line as what 3816 * described here. Normally the ASIC is booted up with auto mode. Any 3817 * settings via this interface will switch the fan control to manual mode 3818 * implicitly. 3819 */ 3820 static ssize_t fan_curve_show(struct kobject *kobj, 3821 struct kobj_attribute *attr, 3822 char *buf) 3823 { 3824 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3825 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3826 3827 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf); 3828 } 3829 3830 static ssize_t fan_curve_store(struct kobject *kobj, 3831 struct kobj_attribute *attr, 3832 const char *buf, 3833 size_t count) 3834 { 3835 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3836 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3837 3838 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3839 PP_OD_EDIT_FAN_CURVE, 3840 buf, 3841 count); 3842 } 3843 3844 static umode_t fan_curve_visible(struct amdgpu_device *adev) 3845 { 3846 umode_t umode = 0000; 3847 3848 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE) 3849 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3850 3851 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET) 3852 umode |= S_IWUSR; 3853 3854 return umode; 3855 } 3856 3857 /** 3858 * DOC: acoustic_limit_rpm_threshold 3859 * 3860 * The amdgpu driver provides a sysfs API for checking and adjusting the 3861 * acoustic limit in RPM for fan control. 3862 * 3863 * Reading back the file shows you the current setting and the permitted 3864 * ranges if changable. 3865 * 3866 * Writing an integer to the file, change the setting accordingly. 3867 * 3868 * When you have finished the editing, write "c" (commit) to the file to commit 3869 * your changes. 3870 * 3871 * If you want to reset to the default value, write "r" (reset) to the file to 3872 * reset them 3873 * 3874 * This setting works under auto fan control mode only. It adjusts the PMFW's 3875 * behavior about the maximum speed in RPM the fan can spin. Setting via this 3876 * interface will switch the fan control to auto mode implicitly. 3877 */ 3878 static ssize_t acoustic_limit_threshold_show(struct kobject *kobj, 3879 struct kobj_attribute *attr, 3880 char *buf) 3881 { 3882 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3883 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3884 3885 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf); 3886 } 3887 3888 static ssize_t acoustic_limit_threshold_store(struct kobject *kobj, 3889 struct kobj_attribute *attr, 3890 const char *buf, 3891 size_t count) 3892 { 3893 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3894 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3895 3896 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3897 PP_OD_EDIT_ACOUSTIC_LIMIT, 3898 buf, 3899 count); 3900 } 3901 3902 static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev) 3903 { 3904 umode_t umode = 0000; 3905 3906 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE) 3907 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3908 3909 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET) 3910 umode |= S_IWUSR; 3911 3912 return umode; 3913 } 3914 3915 /** 3916 * DOC: acoustic_target_rpm_threshold 3917 * 3918 * The amdgpu driver provides a sysfs API for checking and adjusting the 3919 * acoustic target in RPM for fan control. 3920 * 3921 * Reading back the file shows you the current setting and the permitted 3922 * ranges if changable. 3923 * 3924 * Writing an integer to the file, change the setting accordingly. 3925 * 3926 * When you have finished the editing, write "c" (commit) to the file to commit 3927 * your changes. 3928 * 3929 * If you want to reset to the default value, write "r" (reset) to the file to 3930 * reset them 3931 * 3932 * This setting works under auto fan control mode only. It can co-exist with 3933 * other settings which can work also under auto mode. It adjusts the PMFW's 3934 * behavior about the maximum speed in RPM the fan can spin when ASIC 3935 * temperature is not greater than target temperature. Setting via this 3936 * interface will switch the fan control to auto mode implicitly. 3937 */ 3938 static ssize_t acoustic_target_threshold_show(struct kobject *kobj, 3939 struct kobj_attribute *attr, 3940 char *buf) 3941 { 3942 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3943 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3944 3945 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf); 3946 } 3947 3948 static ssize_t acoustic_target_threshold_store(struct kobject *kobj, 3949 struct kobj_attribute *attr, 3950 const char *buf, 3951 size_t count) 3952 { 3953 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 3954 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 3955 3956 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 3957 PP_OD_EDIT_ACOUSTIC_TARGET, 3958 buf, 3959 count); 3960 } 3961 3962 static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev) 3963 { 3964 umode_t umode = 0000; 3965 3966 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE) 3967 umode |= S_IRUSR | S_IRGRP | S_IROTH; 3968 3969 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET) 3970 umode |= S_IWUSR; 3971 3972 return umode; 3973 } 3974 3975 /** 3976 * DOC: fan_target_temperature 3977 * 3978 * The amdgpu driver provides a sysfs API for checking and adjusting the 3979 * target tempeature in Celsius degree for fan control. 3980 * 3981 * Reading back the file shows you the current setting and the permitted 3982 * ranges if changable. 3983 * 3984 * Writing an integer to the file, change the setting accordingly. 3985 * 3986 * When you have finished the editing, write "c" (commit) to the file to commit 3987 * your changes. 3988 * 3989 * If you want to reset to the default value, write "r" (reset) to the file to 3990 * reset them 3991 * 3992 * This setting works under auto fan control mode only. It can co-exist with 3993 * other settings which can work also under auto mode. Paring with the 3994 * acoustic_target_rpm_threshold setting, they define the maximum speed in 3995 * RPM the fan can spin when ASIC temperature is not greater than target 3996 * temperature. Setting via this interface will switch the fan control to 3997 * auto mode implicitly. 3998 */ 3999 static ssize_t fan_target_temperature_show(struct kobject *kobj, 4000 struct kobj_attribute *attr, 4001 char *buf) 4002 { 4003 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4004 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4005 4006 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf); 4007 } 4008 4009 static ssize_t fan_target_temperature_store(struct kobject *kobj, 4010 struct kobj_attribute *attr, 4011 const char *buf, 4012 size_t count) 4013 { 4014 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4015 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4016 4017 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4018 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 4019 buf, 4020 count); 4021 } 4022 4023 static umode_t fan_target_temperature_visible(struct amdgpu_device *adev) 4024 { 4025 umode_t umode = 0000; 4026 4027 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE) 4028 umode |= S_IRUSR | S_IRGRP | S_IROTH; 4029 4030 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET) 4031 umode |= S_IWUSR; 4032 4033 return umode; 4034 } 4035 4036 /** 4037 * DOC: fan_minimum_pwm 4038 * 4039 * The amdgpu driver provides a sysfs API for checking and adjusting the 4040 * minimum fan speed in PWM. 4041 * 4042 * Reading back the file shows you the current setting and the permitted 4043 * ranges if changable. 4044 * 4045 * Writing an integer to the file, change the setting accordingly. 4046 * 4047 * When you have finished the editing, write "c" (commit) to the file to commit 4048 * your changes. 4049 * 4050 * If you want to reset to the default value, write "r" (reset) to the file to 4051 * reset them 4052 * 4053 * This setting works under auto fan control mode only. It can co-exist with 4054 * other settings which can work also under auto mode. It adjusts the PMFW's 4055 * behavior about the minimum fan speed in PWM the fan should spin. Setting 4056 * via this interface will switch the fan control to auto mode implicitly. 4057 */ 4058 static ssize_t fan_minimum_pwm_show(struct kobject *kobj, 4059 struct kobj_attribute *attr, 4060 char *buf) 4061 { 4062 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4063 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4064 4065 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf); 4066 } 4067 4068 static ssize_t fan_minimum_pwm_store(struct kobject *kobj, 4069 struct kobj_attribute *attr, 4070 const char *buf, 4071 size_t count) 4072 { 4073 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4074 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4075 4076 return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4077 PP_OD_EDIT_FAN_MINIMUM_PWM, 4078 buf, 4079 count); 4080 } 4081 4082 static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev) 4083 { 4084 umode_t umode = 0000; 4085 4086 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE) 4087 umode |= S_IRUSR | S_IRGRP | S_IROTH; 4088 4089 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET) 4090 umode |= S_IWUSR; 4091 4092 return umode; 4093 } 4094 4095 static struct od_feature_set amdgpu_od_set = { 4096 .containers = { 4097 [0] = { 4098 .name = "fan_ctrl", 4099 .sub_feature = { 4100 [0] = { 4101 .name = "fan_curve", 4102 .ops = { 4103 .is_visible = fan_curve_visible, 4104 .show = fan_curve_show, 4105 .store = fan_curve_store, 4106 }, 4107 }, 4108 [1] = { 4109 .name = "acoustic_limit_rpm_threshold", 4110 .ops = { 4111 .is_visible = acoustic_limit_threshold_visible, 4112 .show = acoustic_limit_threshold_show, 4113 .store = acoustic_limit_threshold_store, 4114 }, 4115 }, 4116 [2] = { 4117 .name = "acoustic_target_rpm_threshold", 4118 .ops = { 4119 .is_visible = acoustic_target_threshold_visible, 4120 .show = acoustic_target_threshold_show, 4121 .store = acoustic_target_threshold_store, 4122 }, 4123 }, 4124 [3] = { 4125 .name = "fan_target_temperature", 4126 .ops = { 4127 .is_visible = fan_target_temperature_visible, 4128 .show = fan_target_temperature_show, 4129 .store = fan_target_temperature_store, 4130 }, 4131 }, 4132 [4] = { 4133 .name = "fan_minimum_pwm", 4134 .ops = { 4135 .is_visible = fan_minimum_pwm_visible, 4136 .show = fan_minimum_pwm_show, 4137 .store = fan_minimum_pwm_store, 4138 }, 4139 }, 4140 }, 4141 }, 4142 }, 4143 }; 4144 4145 static void od_kobj_release(struct kobject *kobj) 4146 { 4147 struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj); 4148 4149 kfree(od_kobj); 4150 } 4151 4152 static const struct kobj_type od_ktype = { 4153 .release = od_kobj_release, 4154 .sysfs_ops = &kobj_sysfs_ops, 4155 }; 4156 4157 static void amdgpu_od_set_fini(struct amdgpu_device *adev) 4158 { 4159 struct od_kobj *container, *container_next; 4160 struct od_attribute *attribute, *attribute_next; 4161 4162 if (list_empty(&adev->pm.od_kobj_list)) 4163 return; 4164 4165 list_for_each_entry_safe(container, container_next, 4166 &adev->pm.od_kobj_list, entry) { 4167 list_del(&container->entry); 4168 4169 list_for_each_entry_safe(attribute, attribute_next, 4170 &container->attribute, entry) { 4171 list_del(&attribute->entry); 4172 sysfs_remove_file(&container->kobj, 4173 &attribute->attribute.attr); 4174 kfree(attribute); 4175 } 4176 4177 kobject_put(&container->kobj); 4178 } 4179 } 4180 4181 static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev, 4182 struct od_feature_ops *feature_ops) 4183 { 4184 umode_t mode; 4185 4186 if (!feature_ops->is_visible) 4187 return false; 4188 4189 /* 4190 * If the feature has no user read and write mode set, 4191 * we can assume the feature is actually not supported.(?) 4192 * And the revelant sysfs interface should not be exposed. 4193 */ 4194 mode = feature_ops->is_visible(adev); 4195 if (mode & (S_IRUSR | S_IWUSR)) 4196 return true; 4197 4198 return false; 4199 } 4200 4201 static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev, 4202 struct od_feature_container *container) 4203 { 4204 int i; 4205 4206 /* 4207 * If there is no valid entry within the container, the container 4208 * is recognized as a self contained container. And the valid entry 4209 * here means it has a valid naming and it is visible/supported by 4210 * the ASIC. 4211 */ 4212 for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) { 4213 if (container->sub_feature[i].name && 4214 amdgpu_is_od_feature_supported(adev, 4215 &container->sub_feature[i].ops)) 4216 return false; 4217 } 4218 4219 return true; 4220 } 4221 4222 static int amdgpu_od_set_init(struct amdgpu_device *adev) 4223 { 4224 struct od_kobj *top_set, *sub_set; 4225 struct od_attribute *attribute; 4226 struct od_feature_container *container; 4227 struct od_feature_item *feature; 4228 int i, j; 4229 int ret; 4230 4231 /* Setup the top `gpu_od` directory which holds all other OD interfaces */ 4232 top_set = kzalloc(sizeof(*top_set), GFP_KERNEL); 4233 if (!top_set) 4234 return -ENOMEM; 4235 list_add(&top_set->entry, &adev->pm.od_kobj_list); 4236 4237 ret = kobject_init_and_add(&top_set->kobj, 4238 &od_ktype, 4239 &adev->dev->kobj, 4240 "%s", 4241 "gpu_od"); 4242 if (ret) 4243 goto err_out; 4244 INIT_LIST_HEAD(&top_set->attribute); 4245 top_set->priv = adev; 4246 4247 for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) { 4248 container = &amdgpu_od_set.containers[i]; 4249 4250 if (!container->name) 4251 continue; 4252 4253 /* 4254 * If there is valid entries within the container, the container 4255 * will be presented as a sub directory and all its holding entries 4256 * will be presented as plain files under it. 4257 * While if there is no valid entry within the container, the container 4258 * itself will be presented as a plain file under top `gpu_od` directory. 4259 */ 4260 if (amdgpu_od_is_self_contained(adev, container)) { 4261 if (!amdgpu_is_od_feature_supported(adev, 4262 &container->ops)) 4263 continue; 4264 4265 /* 4266 * The container is presented as a plain file under top `gpu_od` 4267 * directory. 4268 */ 4269 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL); 4270 if (!attribute) { 4271 ret = -ENOMEM; 4272 goto err_out; 4273 } 4274 list_add(&attribute->entry, &top_set->attribute); 4275 4276 attribute->attribute.attr.mode = 4277 container->ops.is_visible(adev); 4278 attribute->attribute.attr.name = container->name; 4279 attribute->attribute.show = 4280 container->ops.show; 4281 attribute->attribute.store = 4282 container->ops.store; 4283 ret = sysfs_create_file(&top_set->kobj, 4284 &attribute->attribute.attr); 4285 if (ret) 4286 goto err_out; 4287 } else { 4288 /* The container is presented as a sub directory. */ 4289 sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL); 4290 if (!sub_set) { 4291 ret = -ENOMEM; 4292 goto err_out; 4293 } 4294 list_add(&sub_set->entry, &adev->pm.od_kobj_list); 4295 4296 ret = kobject_init_and_add(&sub_set->kobj, 4297 &od_ktype, 4298 &top_set->kobj, 4299 "%s", 4300 container->name); 4301 if (ret) 4302 goto err_out; 4303 INIT_LIST_HEAD(&sub_set->attribute); 4304 sub_set->priv = adev; 4305 4306 for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) { 4307 feature = &container->sub_feature[j]; 4308 if (!feature->name) 4309 continue; 4310 4311 if (!amdgpu_is_od_feature_supported(adev, 4312 &feature->ops)) 4313 continue; 4314 4315 /* 4316 * With the container presented as a sub directory, the entry within 4317 * it is presented as a plain file under the sub directory. 4318 */ 4319 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL); 4320 if (!attribute) { 4321 ret = -ENOMEM; 4322 goto err_out; 4323 } 4324 list_add(&attribute->entry, &sub_set->attribute); 4325 4326 attribute->attribute.attr.mode = 4327 feature->ops.is_visible(adev); 4328 attribute->attribute.attr.name = feature->name; 4329 attribute->attribute.show = 4330 feature->ops.show; 4331 attribute->attribute.store = 4332 feature->ops.store; 4333 ret = sysfs_create_file(&sub_set->kobj, 4334 &attribute->attribute.attr); 4335 if (ret) 4336 goto err_out; 4337 } 4338 } 4339 } 4340 4341 /* 4342 * If gpu_od is the only member in the list, that means gpu_od is an 4343 * empty directory, so remove it. 4344 */ 4345 if (list_is_singular(&adev->pm.od_kobj_list)) 4346 goto err_out; 4347 4348 return 0; 4349 4350 err_out: 4351 amdgpu_od_set_fini(adev); 4352 4353 return ret; 4354 } 4355 4356 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 4357 { 4358 enum amdgpu_sriov_vf_mode mode; 4359 uint32_t mask = 0; 4360 int ret; 4361 4362 if (adev->pm.sysfs_initialized) 4363 return 0; 4364 4365 INIT_LIST_HEAD(&adev->pm.pm_attr_list); 4366 4367 if (adev->pm.dpm_enabled == 0) 4368 return 0; 4369 4370 mode = amdgpu_virt_get_sriov_vf_mode(adev); 4371 4372 /* under multi-vf mode, the hwmon attributes are all not supported */ 4373 if (mode != SRIOV_VF_MODE_MULTI_VF) { 4374 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 4375 DRIVER_NAME, adev, 4376 hwmon_groups); 4377 if (IS_ERR(adev->pm.int_hwmon_dev)) { 4378 ret = PTR_ERR(adev->pm.int_hwmon_dev); 4379 dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret); 4380 return ret; 4381 } 4382 } 4383 4384 switch (mode) { 4385 case SRIOV_VF_MODE_ONE_VF: 4386 mask = ATTR_FLAG_ONEVF; 4387 break; 4388 case SRIOV_VF_MODE_MULTI_VF: 4389 mask = 0; 4390 break; 4391 case SRIOV_VF_MODE_BARE_METAL: 4392 default: 4393 mask = ATTR_FLAG_MASK_ALL; 4394 break; 4395 } 4396 4397 ret = amdgpu_device_attr_create_groups(adev, 4398 amdgpu_device_attrs, 4399 ARRAY_SIZE(amdgpu_device_attrs), 4400 mask, 4401 &adev->pm.pm_attr_list); 4402 if (ret) 4403 goto err_out0; 4404 4405 if (amdgpu_dpm_is_overdrive_supported(adev)) { 4406 ret = amdgpu_od_set_init(adev); 4407 if (ret) 4408 goto err_out1; 4409 } else if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) { 4410 dev_info(adev->dev, "overdrive feature is not supported\n"); 4411 } 4412 4413 adev->pm.sysfs_initialized = true; 4414 4415 return 0; 4416 4417 err_out1: 4418 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 4419 err_out0: 4420 if (adev->pm.int_hwmon_dev) 4421 hwmon_device_unregister(adev->pm.int_hwmon_dev); 4422 4423 return ret; 4424 } 4425 4426 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 4427 { 4428 amdgpu_od_set_fini(adev); 4429 4430 if (adev->pm.int_hwmon_dev) 4431 hwmon_device_unregister(adev->pm.int_hwmon_dev); 4432 4433 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 4434 } 4435 4436 /* 4437 * Debugfs info 4438 */ 4439 #if defined(CONFIG_DEBUG_FS) 4440 4441 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 4442 struct amdgpu_device *adev) 4443 { 4444 uint16_t *p_val; 4445 uint32_t size; 4446 int i; 4447 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); 4448 4449 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { 4450 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), 4451 GFP_KERNEL); 4452 4453 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 4454 (void *)p_val, &size)) { 4455 for (i = 0; i < num_cpu_cores; i++) 4456 seq_printf(m, "\t%u MHz (CPU%d)\n", 4457 *(p_val + i), i); 4458 } 4459 4460 kfree(p_val); 4461 } 4462 } 4463 4464 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 4465 { 4466 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0); 4467 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 4468 uint32_t value; 4469 uint64_t value64 = 0; 4470 uint32_t query = 0; 4471 int size; 4472 4473 /* GPU Clocks */ 4474 size = sizeof(value); 4475 seq_printf(m, "GFX Clocks and Power:\n"); 4476 4477 amdgpu_debugfs_prints_cpu_info(m, adev); 4478 4479 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 4480 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 4481 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 4482 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 4483 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 4484 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 4485 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 4486 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 4487 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 4488 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 4489 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 4490 seq_printf(m, "\t%u mV (VDDNB)\n", value); 4491 size = sizeof(uint32_t); 4492 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) { 4493 if (adev->flags & AMD_IS_APU) 4494 seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n", query >> 8, query & 0xff); 4495 else 4496 seq_printf(m, "\t%u.%02u W (average SoC)\n", query >> 8, query & 0xff); 4497 } 4498 size = sizeof(uint32_t); 4499 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) { 4500 if (adev->flags & AMD_IS_APU) 4501 seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n", query >> 8, query & 0xff); 4502 else 4503 seq_printf(m, "\t%u.%02u W (current SoC)\n", query >> 8, query & 0xff); 4504 } 4505 size = sizeof(value); 4506 seq_printf(m, "\n"); 4507 4508 /* GPU Temp */ 4509 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 4510 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 4511 4512 /* GPU Load */ 4513 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 4514 seq_printf(m, "GPU Load: %u %%\n", value); 4515 /* MEM Load */ 4516 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 4517 seq_printf(m, "MEM Load: %u %%\n", value); 4518 /* VCN Load */ 4519 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_LOAD, (void *)&value, &size)) 4520 seq_printf(m, "VCN Load: %u %%\n", value); 4521 4522 seq_printf(m, "\n"); 4523 4524 /* SMC feature mask */ 4525 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 4526 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 4527 4528 /* ASICs greater than CHIP_VEGA20 supports these sensors */ 4529 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { 4530 /* VCN clocks */ 4531 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 4532 if (!value) { 4533 seq_printf(m, "VCN: Powered down\n"); 4534 } else { 4535 seq_printf(m, "VCN: Powered up\n"); 4536 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 4537 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 4538 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 4539 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 4540 } 4541 } 4542 seq_printf(m, "\n"); 4543 } else { 4544 /* UVD clocks */ 4545 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 4546 if (!value) { 4547 seq_printf(m, "UVD: Powered down\n"); 4548 } else { 4549 seq_printf(m, "UVD: Powered up\n"); 4550 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 4551 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 4552 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 4553 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 4554 } 4555 } 4556 seq_printf(m, "\n"); 4557 4558 /* VCE clocks */ 4559 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 4560 if (!value) { 4561 seq_printf(m, "VCE: Powered down\n"); 4562 } else { 4563 seq_printf(m, "VCE: Powered up\n"); 4564 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 4565 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 4566 } 4567 } 4568 } 4569 4570 return 0; 4571 } 4572 4573 static const struct cg_flag_name clocks[] = { 4574 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 4575 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 4576 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 4577 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 4578 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 4579 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 4580 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 4581 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 4582 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 4583 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 4584 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 4585 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 4586 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 4587 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 4588 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 4589 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 4590 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 4591 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 4592 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 4593 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 4594 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 4595 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 4596 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 4597 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 4598 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 4599 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 4600 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 4601 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 4602 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 4603 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 4604 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, 4605 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, 4606 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 4607 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 4608 {0, NULL}, 4609 }; 4610 4611 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 4612 { 4613 int i; 4614 4615 for (i = 0; clocks[i].flag; i++) 4616 seq_printf(m, "\t%s: %s\n", clocks[i].name, 4617 (flags & clocks[i].flag) ? "On" : "Off"); 4618 } 4619 4620 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 4621 { 4622 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 4623 struct drm_device *dev = adev_to_drm(adev); 4624 u64 flags = 0; 4625 int r; 4626 4627 if (amdgpu_in_reset(adev)) 4628 return -EPERM; 4629 if (adev->in_suspend && !adev->in_runpm) 4630 return -EPERM; 4631 4632 r = pm_runtime_get_sync(dev->dev); 4633 if (r < 0) { 4634 pm_runtime_put_autosuspend(dev->dev); 4635 return r; 4636 } 4637 4638 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { 4639 r = amdgpu_debugfs_pm_info_pp(m, adev); 4640 if (r) 4641 goto out; 4642 } 4643 4644 amdgpu_device_ip_get_clockgating_state(adev, &flags); 4645 4646 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 4647 amdgpu_parse_cg_state(m, flags); 4648 seq_printf(m, "\n"); 4649 4650 out: 4651 pm_runtime_mark_last_busy(dev->dev); 4652 pm_runtime_put_autosuspend(dev->dev); 4653 4654 return r; 4655 } 4656 4657 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 4658 4659 /* 4660 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 4661 * 4662 * Reads debug memory region allocated to PMFW 4663 */ 4664 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 4665 size_t size, loff_t *pos) 4666 { 4667 struct amdgpu_device *adev = file_inode(f)->i_private; 4668 size_t smu_prv_buf_size; 4669 void *smu_prv_buf; 4670 int ret = 0; 4671 4672 if (amdgpu_in_reset(adev)) 4673 return -EPERM; 4674 if (adev->in_suspend && !adev->in_runpm) 4675 return -EPERM; 4676 4677 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); 4678 if (ret) 4679 return ret; 4680 4681 if (!smu_prv_buf || !smu_prv_buf_size) 4682 return -EINVAL; 4683 4684 return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 4685 smu_prv_buf_size); 4686 } 4687 4688 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 4689 .owner = THIS_MODULE, 4690 .open = simple_open, 4691 .read = amdgpu_pm_prv_buffer_read, 4692 .llseek = default_llseek, 4693 }; 4694 4695 #endif 4696 4697 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 4698 { 4699 #if defined(CONFIG_DEBUG_FS) 4700 struct drm_minor *minor = adev_to_drm(adev)->primary; 4701 struct dentry *root = minor->debugfs_root; 4702 4703 if (!adev->pm.dpm_enabled) 4704 return; 4705 4706 debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 4707 &amdgpu_debugfs_pm_info_fops); 4708 4709 if (adev->pm.smu_prv_buffer_size > 0) 4710 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 4711 adev, 4712 &amdgpu_debugfs_pm_prv_buffer_fops, 4713 adev->pm.smu_prv_buffer_size); 4714 4715 amdgpu_dpm_stb_debug_fs_init(adev); 4716 #endif 4717 } 4718