1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2017 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan * Authors: Rafał Miłecki <zajec5@gmail.com> 23e098bc96SEvan Quan * Alex Deucher <alexdeucher@gmail.com> 24e098bc96SEvan Quan */ 25e098bc96SEvan Quan 26e098bc96SEvan Quan #include <drm/drm_debugfs.h> 27e098bc96SEvan Quan 28e098bc96SEvan Quan #include "amdgpu.h" 29e098bc96SEvan Quan #include "amdgpu_drv.h" 30e098bc96SEvan Quan #include "amdgpu_pm.h" 31e098bc96SEvan Quan #include "amdgpu_dpm.h" 32e098bc96SEvan Quan #include "amdgpu_smu.h" 33e098bc96SEvan Quan #include "atom.h" 34e098bc96SEvan Quan #include <linux/pci.h> 35e098bc96SEvan Quan #include <linux/hwmon.h> 36e098bc96SEvan Quan #include <linux/hwmon-sysfs.h> 37e098bc96SEvan Quan #include <linux/nospec.h> 38e098bc96SEvan Quan #include <linux/pm_runtime.h> 39e098bc96SEvan Quan #include "hwmgr.h" 40e098bc96SEvan Quan 41e098bc96SEvan Quan static const struct cg_flag_name clocks[] = { 42e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 43e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 44e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 45e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 46e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 47e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 48e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 49e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 50e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 51e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 52e098bc96SEvan Quan {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 53e098bc96SEvan Quan {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 54e098bc96SEvan Quan {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 55e098bc96SEvan Quan {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 56e098bc96SEvan Quan {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 57e098bc96SEvan Quan {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 58e098bc96SEvan Quan {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 59e098bc96SEvan Quan {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 60e098bc96SEvan Quan {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 61e098bc96SEvan Quan {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 62e098bc96SEvan Quan {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 63e098bc96SEvan Quan {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 64e098bc96SEvan Quan {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 65e098bc96SEvan Quan {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 66e098bc96SEvan Quan 67e098bc96SEvan Quan {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 68e098bc96SEvan Quan {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 69e098bc96SEvan Quan {0, NULL}, 70e098bc96SEvan Quan }; 71e098bc96SEvan Quan 72e098bc96SEvan Quan static const struct hwmon_temp_label { 73e098bc96SEvan Quan enum PP_HWMON_TEMP channel; 74e098bc96SEvan Quan const char *label; 75e098bc96SEvan Quan } temp_label[] = { 76e098bc96SEvan Quan {PP_TEMP_EDGE, "edge"}, 77e098bc96SEvan Quan {PP_TEMP_JUNCTION, "junction"}, 78e098bc96SEvan Quan {PP_TEMP_MEM, "mem"}, 79e098bc96SEvan Quan }; 80e098bc96SEvan Quan 81e098bc96SEvan Quan /** 82e098bc96SEvan Quan * DOC: power_dpm_state 83e098bc96SEvan Quan * 84e098bc96SEvan Quan * The power_dpm_state file is a legacy interface and is only provided for 85e098bc96SEvan Quan * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 86e098bc96SEvan Quan * certain power related parameters. The file power_dpm_state is used for this. 87e098bc96SEvan Quan * It accepts the following arguments: 88e098bc96SEvan Quan * 89e098bc96SEvan Quan * - battery 90e098bc96SEvan Quan * 91e098bc96SEvan Quan * - balanced 92e098bc96SEvan Quan * 93e098bc96SEvan Quan * - performance 94e098bc96SEvan Quan * 95e098bc96SEvan Quan * battery 96e098bc96SEvan Quan * 97e098bc96SEvan Quan * On older GPUs, the vbios provided a special power state for battery 98e098bc96SEvan Quan * operation. Selecting battery switched to this state. This is no 99e098bc96SEvan Quan * longer provided on newer GPUs so the option does nothing in that case. 100e098bc96SEvan Quan * 101e098bc96SEvan Quan * balanced 102e098bc96SEvan Quan * 103e098bc96SEvan Quan * On older GPUs, the vbios provided a special power state for balanced 104e098bc96SEvan Quan * operation. Selecting balanced switched to this state. This is no 105e098bc96SEvan Quan * longer provided on newer GPUs so the option does nothing in that case. 106e098bc96SEvan Quan * 107e098bc96SEvan Quan * performance 108e098bc96SEvan Quan * 109e098bc96SEvan Quan * On older GPUs, the vbios provided a special power state for performance 110e098bc96SEvan Quan * operation. Selecting performance switched to this state. This is no 111e098bc96SEvan Quan * longer provided on newer GPUs so the option does nothing in that case. 112e098bc96SEvan Quan * 113e098bc96SEvan Quan */ 114e098bc96SEvan Quan 115e098bc96SEvan Quan static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 116e098bc96SEvan Quan struct device_attribute *attr, 117e098bc96SEvan Quan char *buf) 118e098bc96SEvan Quan { 119e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 1201348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 121e098bc96SEvan Quan enum amd_pm_state_type pm; 122e098bc96SEvan Quan int ret; 123e098bc96SEvan Quan 12453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 125e098bc96SEvan Quan return -EPERM; 126e098bc96SEvan Quan 127e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 128e098bc96SEvan Quan if (ret < 0) { 129e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 130e098bc96SEvan Quan return ret; 131e098bc96SEvan Quan } 132e098bc96SEvan Quan 133e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 134e098bc96SEvan Quan if (adev->smu.ppt_funcs->get_current_power_state) 135e098bc96SEvan Quan pm = smu_get_current_power_state(&adev->smu); 136e098bc96SEvan Quan else 137e098bc96SEvan Quan pm = adev->pm.dpm.user_state; 138e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->get_current_power_state) { 139e098bc96SEvan Quan pm = amdgpu_dpm_get_current_power_state(adev); 140e098bc96SEvan Quan } else { 141e098bc96SEvan Quan pm = adev->pm.dpm.user_state; 142e098bc96SEvan Quan } 143e098bc96SEvan Quan 144e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 145e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 146e098bc96SEvan Quan 147e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%s\n", 148e098bc96SEvan Quan (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 149e098bc96SEvan Quan (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 150e098bc96SEvan Quan } 151e098bc96SEvan Quan 152e098bc96SEvan Quan static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 153e098bc96SEvan Quan struct device_attribute *attr, 154e098bc96SEvan Quan const char *buf, 155e098bc96SEvan Quan size_t count) 156e098bc96SEvan Quan { 157e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 1581348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 159e098bc96SEvan Quan enum amd_pm_state_type state; 160e098bc96SEvan Quan int ret; 161e098bc96SEvan Quan 16253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 163e098bc96SEvan Quan return -EPERM; 164e098bc96SEvan Quan 165e098bc96SEvan Quan if (strncmp("battery", buf, strlen("battery")) == 0) 166e098bc96SEvan Quan state = POWER_STATE_TYPE_BATTERY; 167e098bc96SEvan Quan else if (strncmp("balanced", buf, strlen("balanced")) == 0) 168e098bc96SEvan Quan state = POWER_STATE_TYPE_BALANCED; 169e098bc96SEvan Quan else if (strncmp("performance", buf, strlen("performance")) == 0) 170e098bc96SEvan Quan state = POWER_STATE_TYPE_PERFORMANCE; 171e098bc96SEvan Quan else 172e098bc96SEvan Quan return -EINVAL; 173e098bc96SEvan Quan 174e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 175e098bc96SEvan Quan if (ret < 0) { 176e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 177e098bc96SEvan Quan return ret; 178e098bc96SEvan Quan } 179e098bc96SEvan Quan 180e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 181e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 182e098bc96SEvan Quan adev->pm.dpm.user_state = state; 183e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 184e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->dispatch_tasks) { 185e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state); 186e098bc96SEvan Quan } else { 187e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 188e098bc96SEvan Quan adev->pm.dpm.user_state = state; 189e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 190e098bc96SEvan Quan 191e098bc96SEvan Quan amdgpu_pm_compute_clocks(adev); 192e098bc96SEvan Quan } 193e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 194e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 195e098bc96SEvan Quan 196e098bc96SEvan Quan return count; 197e098bc96SEvan Quan } 198e098bc96SEvan Quan 199e098bc96SEvan Quan 200e098bc96SEvan Quan /** 201e098bc96SEvan Quan * DOC: power_dpm_force_performance_level 202e098bc96SEvan Quan * 203e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting certain power 204e098bc96SEvan Quan * related parameters. The file power_dpm_force_performance_level is 205e098bc96SEvan Quan * used for this. It accepts the following arguments: 206e098bc96SEvan Quan * 207e098bc96SEvan Quan * - auto 208e098bc96SEvan Quan * 209e098bc96SEvan Quan * - low 210e098bc96SEvan Quan * 211e098bc96SEvan Quan * - high 212e098bc96SEvan Quan * 213e098bc96SEvan Quan * - manual 214e098bc96SEvan Quan * 215e098bc96SEvan Quan * - profile_standard 216e098bc96SEvan Quan * 217e098bc96SEvan Quan * - profile_min_sclk 218e098bc96SEvan Quan * 219e098bc96SEvan Quan * - profile_min_mclk 220e098bc96SEvan Quan * 221e098bc96SEvan Quan * - profile_peak 222e098bc96SEvan Quan * 223e098bc96SEvan Quan * auto 224e098bc96SEvan Quan * 225e098bc96SEvan Quan * When auto is selected, the driver will attempt to dynamically select 226e098bc96SEvan Quan * the optimal power profile for current conditions in the driver. 227e098bc96SEvan Quan * 228e098bc96SEvan Quan * low 229e098bc96SEvan Quan * 230e098bc96SEvan Quan * When low is selected, the clocks are forced to the lowest power state. 231e098bc96SEvan Quan * 232e098bc96SEvan Quan * high 233e098bc96SEvan Quan * 234e098bc96SEvan Quan * When high is selected, the clocks are forced to the highest power state. 235e098bc96SEvan Quan * 236e098bc96SEvan Quan * manual 237e098bc96SEvan Quan * 238e098bc96SEvan Quan * When manual is selected, the user can manually adjust which power states 239e098bc96SEvan Quan * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 240e098bc96SEvan Quan * and pp_dpm_pcie files and adjust the power state transition heuristics 241e098bc96SEvan Quan * via the pp_power_profile_mode sysfs file. 242e098bc96SEvan Quan * 243e098bc96SEvan Quan * profile_standard 244e098bc96SEvan Quan * profile_min_sclk 245e098bc96SEvan Quan * profile_min_mclk 246e098bc96SEvan Quan * profile_peak 247e098bc96SEvan Quan * 248e098bc96SEvan Quan * When the profiling modes are selected, clock and power gating are 249e098bc96SEvan Quan * disabled and the clocks are set for different profiling cases. This 250e098bc96SEvan Quan * mode is recommended for profiling specific work loads where you do 251e098bc96SEvan Quan * not want clock or power gating for clock fluctuation to interfere 252e098bc96SEvan Quan * with your results. profile_standard sets the clocks to a fixed clock 253e098bc96SEvan Quan * level which varies from asic to asic. profile_min_sclk forces the sclk 254e098bc96SEvan Quan * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 255e098bc96SEvan Quan * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 256e098bc96SEvan Quan * 257e098bc96SEvan Quan */ 258e098bc96SEvan Quan 259e098bc96SEvan Quan static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 260e098bc96SEvan Quan struct device_attribute *attr, 261e098bc96SEvan Quan char *buf) 262e098bc96SEvan Quan { 263e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 2641348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 265e098bc96SEvan Quan enum amd_dpm_forced_level level = 0xff; 266e098bc96SEvan Quan int ret; 267e098bc96SEvan Quan 26853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 269e098bc96SEvan Quan return -EPERM; 270e098bc96SEvan Quan 271e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 272e098bc96SEvan Quan if (ret < 0) { 273e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 274e098bc96SEvan Quan return ret; 275e098bc96SEvan Quan } 276e098bc96SEvan Quan 277e098bc96SEvan Quan if (is_support_sw_smu(adev)) 278e098bc96SEvan Quan level = smu_get_performance_level(&adev->smu); 279e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_performance_level) 280e098bc96SEvan Quan level = amdgpu_dpm_get_performance_level(adev); 281e098bc96SEvan Quan else 282e098bc96SEvan Quan level = adev->pm.dpm.forced_level; 283e098bc96SEvan Quan 284e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 285e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 286e098bc96SEvan Quan 287e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%s\n", 288e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 289e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 290e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 291e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 292e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 293e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 294e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 295e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 296e098bc96SEvan Quan "unknown"); 297e098bc96SEvan Quan } 298e098bc96SEvan Quan 299e098bc96SEvan Quan static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 300e098bc96SEvan Quan struct device_attribute *attr, 301e098bc96SEvan Quan const char *buf, 302e098bc96SEvan Quan size_t count) 303e098bc96SEvan Quan { 304e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 3051348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 306e098bc96SEvan Quan enum amd_dpm_forced_level level; 307e098bc96SEvan Quan enum amd_dpm_forced_level current_level = 0xff; 308e098bc96SEvan Quan int ret = 0; 309e098bc96SEvan Quan 31053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 311e098bc96SEvan Quan return -EPERM; 312e098bc96SEvan Quan 313e098bc96SEvan Quan if (strncmp("low", buf, strlen("low")) == 0) { 314e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_LOW; 315e098bc96SEvan Quan } else if (strncmp("high", buf, strlen("high")) == 0) { 316e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_HIGH; 317e098bc96SEvan Quan } else if (strncmp("auto", buf, strlen("auto")) == 0) { 318e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_AUTO; 319e098bc96SEvan Quan } else if (strncmp("manual", buf, strlen("manual")) == 0) { 320e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_MANUAL; 321e098bc96SEvan Quan } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 322e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 323e098bc96SEvan Quan } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 324e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 325e098bc96SEvan Quan } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 326e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 327e098bc96SEvan Quan } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 328e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 329e098bc96SEvan Quan } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 330e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 331e098bc96SEvan Quan } else { 332e098bc96SEvan Quan return -EINVAL; 333e098bc96SEvan Quan } 334e098bc96SEvan Quan 335e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 336e098bc96SEvan Quan if (ret < 0) { 337e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 338e098bc96SEvan Quan return ret; 339e098bc96SEvan Quan } 340e098bc96SEvan Quan 341e098bc96SEvan Quan if (is_support_sw_smu(adev)) 342e098bc96SEvan Quan current_level = smu_get_performance_level(&adev->smu); 343e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_performance_level) 344e098bc96SEvan Quan current_level = amdgpu_dpm_get_performance_level(adev); 345e098bc96SEvan Quan 346e098bc96SEvan Quan if (current_level == level) { 347e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 348e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 349e098bc96SEvan Quan return count; 350e098bc96SEvan Quan } 351e098bc96SEvan Quan 352e098bc96SEvan Quan if (adev->asic_type == CHIP_RAVEN) { 353e098bc96SEvan Quan if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { 354e098bc96SEvan Quan if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL) 355e098bc96SEvan Quan amdgpu_gfx_off_ctrl(adev, false); 356e098bc96SEvan Quan else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL) 357e098bc96SEvan Quan amdgpu_gfx_off_ctrl(adev, true); 358e098bc96SEvan Quan } 359e098bc96SEvan Quan } 360e098bc96SEvan Quan 361e098bc96SEvan Quan /* profile_exit setting is valid only when current mode is in profile mode */ 362e098bc96SEvan Quan if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 363e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 364e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 365e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) && 366e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) { 367e098bc96SEvan Quan pr_err("Currently not in any profile mode!\n"); 368e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 369e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 370e098bc96SEvan Quan return -EINVAL; 371e098bc96SEvan Quan } 372e098bc96SEvan Quan 373e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 374e098bc96SEvan Quan ret = smu_force_performance_level(&adev->smu, level); 375e098bc96SEvan Quan if (ret) { 376e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 377e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 378e098bc96SEvan Quan return -EINVAL; 379e098bc96SEvan Quan } 380e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->force_performance_level) { 381e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 382e098bc96SEvan Quan if (adev->pm.dpm.thermal_active) { 383e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 384e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 385e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 386e098bc96SEvan Quan return -EINVAL; 387e098bc96SEvan Quan } 388e098bc96SEvan Quan ret = amdgpu_dpm_force_performance_level(adev, level); 389e098bc96SEvan Quan if (ret) { 390e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 391e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 392e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 393e098bc96SEvan Quan return -EINVAL; 394e098bc96SEvan Quan } else { 395e098bc96SEvan Quan adev->pm.dpm.forced_level = level; 396e098bc96SEvan Quan } 397e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 398e098bc96SEvan Quan } 399e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 400e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 401e098bc96SEvan Quan 402e098bc96SEvan Quan return count; 403e098bc96SEvan Quan } 404e098bc96SEvan Quan 405e098bc96SEvan Quan static ssize_t amdgpu_get_pp_num_states(struct device *dev, 406e098bc96SEvan Quan struct device_attribute *attr, 407e098bc96SEvan Quan char *buf) 408e098bc96SEvan Quan { 409e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 4101348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 411e098bc96SEvan Quan struct pp_states_info data; 412e098bc96SEvan Quan int i, buf_len, ret; 413e098bc96SEvan Quan 41453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 415e098bc96SEvan Quan return -EPERM; 416e098bc96SEvan Quan 417e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 418e098bc96SEvan Quan if (ret < 0) { 419e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 420e098bc96SEvan Quan return ret; 421e098bc96SEvan Quan } 422e098bc96SEvan Quan 423e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 424e098bc96SEvan Quan ret = smu_get_power_num_states(&adev->smu, &data); 425e098bc96SEvan Quan if (ret) 426e098bc96SEvan Quan return ret; 427e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->get_pp_num_states) { 428e098bc96SEvan Quan amdgpu_dpm_get_pp_num_states(adev, &data); 429e098bc96SEvan Quan } else { 430e098bc96SEvan Quan memset(&data, 0, sizeof(data)); 431e098bc96SEvan Quan } 432e098bc96SEvan Quan 433e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 434e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 435e098bc96SEvan Quan 436e098bc96SEvan Quan buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums); 437e098bc96SEvan Quan for (i = 0; i < data.nums; i++) 438e098bc96SEvan Quan buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i, 439e098bc96SEvan Quan (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 440e098bc96SEvan Quan (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 441e098bc96SEvan Quan (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 442e098bc96SEvan Quan (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 443e098bc96SEvan Quan 444e098bc96SEvan Quan return buf_len; 445e098bc96SEvan Quan } 446e098bc96SEvan Quan 447e098bc96SEvan Quan static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 448e098bc96SEvan Quan struct device_attribute *attr, 449e098bc96SEvan Quan char *buf) 450e098bc96SEvan Quan { 451e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 4521348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 453e098bc96SEvan Quan struct pp_states_info data; 454e098bc96SEvan Quan struct smu_context *smu = &adev->smu; 455e098bc96SEvan Quan enum amd_pm_state_type pm = 0; 456e098bc96SEvan Quan int i = 0, ret = 0; 457e098bc96SEvan Quan 45853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 459e098bc96SEvan Quan return -EPERM; 460e098bc96SEvan Quan 461e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 462e098bc96SEvan Quan if (ret < 0) { 463e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 464e098bc96SEvan Quan return ret; 465e098bc96SEvan Quan } 466e098bc96SEvan Quan 467e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 468e098bc96SEvan Quan pm = smu_get_current_power_state(smu); 469e098bc96SEvan Quan ret = smu_get_power_num_states(smu, &data); 470e098bc96SEvan Quan if (ret) 471e098bc96SEvan Quan return ret; 472e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->get_current_power_state 473e098bc96SEvan Quan && adev->powerplay.pp_funcs->get_pp_num_states) { 474e098bc96SEvan Quan pm = amdgpu_dpm_get_current_power_state(adev); 475e098bc96SEvan Quan amdgpu_dpm_get_pp_num_states(adev, &data); 476e098bc96SEvan Quan } 477e098bc96SEvan Quan 478e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 479e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 480e098bc96SEvan Quan 481e098bc96SEvan Quan for (i = 0; i < data.nums; i++) { 482e098bc96SEvan Quan if (pm == data.states[i]) 483e098bc96SEvan Quan break; 484e098bc96SEvan Quan } 485e098bc96SEvan Quan 486e098bc96SEvan Quan if (i == data.nums) 487e098bc96SEvan Quan i = -EINVAL; 488e098bc96SEvan Quan 489e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", i); 490e098bc96SEvan Quan } 491e098bc96SEvan Quan 492e098bc96SEvan Quan static ssize_t amdgpu_get_pp_force_state(struct device *dev, 493e098bc96SEvan Quan struct device_attribute *attr, 494e098bc96SEvan Quan char *buf) 495e098bc96SEvan Quan { 496e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 4971348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 498e098bc96SEvan Quan 49953b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 500e098bc96SEvan Quan return -EPERM; 501e098bc96SEvan Quan 502e098bc96SEvan Quan if (adev->pp_force_state_enabled) 503e098bc96SEvan Quan return amdgpu_get_pp_cur_state(dev, attr, buf); 504e098bc96SEvan Quan else 505e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "\n"); 506e098bc96SEvan Quan } 507e098bc96SEvan Quan 508e098bc96SEvan Quan static ssize_t amdgpu_set_pp_force_state(struct device *dev, 509e098bc96SEvan Quan struct device_attribute *attr, 510e098bc96SEvan Quan const char *buf, 511e098bc96SEvan Quan size_t count) 512e098bc96SEvan Quan { 513e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 5141348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 515e098bc96SEvan Quan enum amd_pm_state_type state = 0; 516e098bc96SEvan Quan unsigned long idx; 517e098bc96SEvan Quan int ret; 518e098bc96SEvan Quan 51953b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 520e098bc96SEvan Quan return -EPERM; 521e098bc96SEvan Quan 522e098bc96SEvan Quan if (strlen(buf) == 1) 523e098bc96SEvan Quan adev->pp_force_state_enabled = false; 524e098bc96SEvan Quan else if (is_support_sw_smu(adev)) 525e098bc96SEvan Quan adev->pp_force_state_enabled = false; 526e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->dispatch_tasks && 527e098bc96SEvan Quan adev->powerplay.pp_funcs->get_pp_num_states) { 528e098bc96SEvan Quan struct pp_states_info data; 529e098bc96SEvan Quan 530e098bc96SEvan Quan ret = kstrtoul(buf, 0, &idx); 531e098bc96SEvan Quan if (ret || idx >= ARRAY_SIZE(data.states)) 532e098bc96SEvan Quan return -EINVAL; 533e098bc96SEvan Quan 534e098bc96SEvan Quan idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 535e098bc96SEvan Quan 536e098bc96SEvan Quan amdgpu_dpm_get_pp_num_states(adev, &data); 537e098bc96SEvan Quan state = data.states[idx]; 538e098bc96SEvan Quan 539e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 540e098bc96SEvan Quan if (ret < 0) { 541e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 542e098bc96SEvan Quan return ret; 543e098bc96SEvan Quan } 544e098bc96SEvan Quan 545e098bc96SEvan Quan /* only set user selected power states */ 546e098bc96SEvan Quan if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 547e098bc96SEvan Quan state != POWER_STATE_TYPE_DEFAULT) { 548e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, 549e098bc96SEvan Quan AMD_PP_TASK_ENABLE_USER_STATE, &state); 550e098bc96SEvan Quan adev->pp_force_state_enabled = true; 551e098bc96SEvan Quan } 552e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 553e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 554e098bc96SEvan Quan } 555e098bc96SEvan Quan 556e098bc96SEvan Quan return count; 557e098bc96SEvan Quan } 558e098bc96SEvan Quan 559e098bc96SEvan Quan /** 560e098bc96SEvan Quan * DOC: pp_table 561e098bc96SEvan Quan * 562e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for uploading new powerplay 563e098bc96SEvan Quan * tables. The file pp_table is used for this. Reading the file 564e098bc96SEvan Quan * will dump the current power play table. Writing to the file 565e098bc96SEvan Quan * will attempt to upload a new powerplay table and re-initialize 566e098bc96SEvan Quan * powerplay using that new table. 567e098bc96SEvan Quan * 568e098bc96SEvan Quan */ 569e098bc96SEvan Quan 570e098bc96SEvan Quan static ssize_t amdgpu_get_pp_table(struct device *dev, 571e098bc96SEvan Quan struct device_attribute *attr, 572e098bc96SEvan Quan char *buf) 573e098bc96SEvan Quan { 574e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 5751348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 576e098bc96SEvan Quan char *table = NULL; 577e098bc96SEvan Quan int size, ret; 578e098bc96SEvan Quan 57953b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 580e098bc96SEvan Quan return -EPERM; 581e098bc96SEvan Quan 582e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 583e098bc96SEvan Quan if (ret < 0) { 584e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 585e098bc96SEvan Quan return ret; 586e098bc96SEvan Quan } 587e098bc96SEvan Quan 588e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 589e098bc96SEvan Quan size = smu_sys_get_pp_table(&adev->smu, (void **)&table); 590e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 591e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 592e098bc96SEvan Quan if (size < 0) 593e098bc96SEvan Quan return size; 594e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->get_pp_table) { 595e098bc96SEvan Quan size = amdgpu_dpm_get_pp_table(adev, &table); 596e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 597e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 598e098bc96SEvan Quan if (size < 0) 599e098bc96SEvan Quan return size; 600e098bc96SEvan Quan } else { 601e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 602e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 603e098bc96SEvan Quan return 0; 604e098bc96SEvan Quan } 605e098bc96SEvan Quan 606e098bc96SEvan Quan if (size >= PAGE_SIZE) 607e098bc96SEvan Quan size = PAGE_SIZE - 1; 608e098bc96SEvan Quan 609e098bc96SEvan Quan memcpy(buf, table, size); 610e098bc96SEvan Quan 611e098bc96SEvan Quan return size; 612e098bc96SEvan Quan } 613e098bc96SEvan Quan 614e098bc96SEvan Quan static ssize_t amdgpu_set_pp_table(struct device *dev, 615e098bc96SEvan Quan struct device_attribute *attr, 616e098bc96SEvan Quan const char *buf, 617e098bc96SEvan Quan size_t count) 618e098bc96SEvan Quan { 619e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 6201348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 621e098bc96SEvan Quan int ret = 0; 622e098bc96SEvan Quan 62353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 624e098bc96SEvan Quan return -EPERM; 625e098bc96SEvan Quan 626e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 627e098bc96SEvan Quan if (ret < 0) { 628e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 629e098bc96SEvan Quan return ret; 630e098bc96SEvan Quan } 631e098bc96SEvan Quan 632e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 633e098bc96SEvan Quan ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count); 634e098bc96SEvan Quan if (ret) { 635e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 636e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 637e098bc96SEvan Quan return ret; 638e098bc96SEvan Quan } 639e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->set_pp_table) 640e098bc96SEvan Quan amdgpu_dpm_set_pp_table(adev, buf, count); 641e098bc96SEvan Quan 642e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 643e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 644e098bc96SEvan Quan 645e098bc96SEvan Quan return count; 646e098bc96SEvan Quan } 647e098bc96SEvan Quan 648e098bc96SEvan Quan /** 649e098bc96SEvan Quan * DOC: pp_od_clk_voltage 650e098bc96SEvan Quan * 651e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 652e098bc96SEvan Quan * in each power level within a power state. The pp_od_clk_voltage is used for 653e098bc96SEvan Quan * this. 654e098bc96SEvan Quan * 655e098bc96SEvan Quan * Note that the actual memory controller clock rate are exposed, not 656e098bc96SEvan Quan * the effective memory clock of the DRAMs. To translate it, use the 657e098bc96SEvan Quan * following formula: 658e098bc96SEvan Quan * 659e098bc96SEvan Quan * Clock conversion (Mhz): 660e098bc96SEvan Quan * 661e098bc96SEvan Quan * HBM: effective_memory_clock = memory_controller_clock * 1 662e098bc96SEvan Quan * 663e098bc96SEvan Quan * G5: effective_memory_clock = memory_controller_clock * 1 664e098bc96SEvan Quan * 665e098bc96SEvan Quan * G6: effective_memory_clock = memory_controller_clock * 2 666e098bc96SEvan Quan * 667e098bc96SEvan Quan * DRAM data rate (MT/s): 668e098bc96SEvan Quan * 669e098bc96SEvan Quan * HBM: effective_memory_clock * 2 = data_rate 670e098bc96SEvan Quan * 671e098bc96SEvan Quan * G5: effective_memory_clock * 4 = data_rate 672e098bc96SEvan Quan * 673e098bc96SEvan Quan * G6: effective_memory_clock * 8 = data_rate 674e098bc96SEvan Quan * 675e098bc96SEvan Quan * Bandwidth (MB/s): 676e098bc96SEvan Quan * 677e098bc96SEvan Quan * data_rate * vram_bit_width / 8 = memory_bandwidth 678e098bc96SEvan Quan * 679e098bc96SEvan Quan * Some examples: 680e098bc96SEvan Quan * 681e098bc96SEvan Quan * G5 on RX460: 682e098bc96SEvan Quan * 683e098bc96SEvan Quan * memory_controller_clock = 1750 Mhz 684e098bc96SEvan Quan * 685e098bc96SEvan Quan * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 686e098bc96SEvan Quan * 687e098bc96SEvan Quan * data rate = 1750 * 4 = 7000 MT/s 688e098bc96SEvan Quan * 689e098bc96SEvan Quan * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 690e098bc96SEvan Quan * 691e098bc96SEvan Quan * G6 on RX5700: 692e098bc96SEvan Quan * 693e098bc96SEvan Quan * memory_controller_clock = 875 Mhz 694e098bc96SEvan Quan * 695e098bc96SEvan Quan * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 696e098bc96SEvan Quan * 697e098bc96SEvan Quan * data rate = 1750 * 8 = 14000 MT/s 698e098bc96SEvan Quan * 699e098bc96SEvan Quan * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 700e098bc96SEvan Quan * 701e098bc96SEvan Quan * < For Vega10 and previous ASICs > 702e098bc96SEvan Quan * 703e098bc96SEvan Quan * Reading the file will display: 704e098bc96SEvan Quan * 705e098bc96SEvan Quan * - a list of engine clock levels and voltages labeled OD_SCLK 706e098bc96SEvan Quan * 707e098bc96SEvan Quan * - a list of memory clock levels and voltages labeled OD_MCLK 708e098bc96SEvan Quan * 709e098bc96SEvan Quan * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 710e098bc96SEvan Quan * 711e098bc96SEvan Quan * To manually adjust these settings, first select manual using 712e098bc96SEvan Quan * power_dpm_force_performance_level. Enter a new value for each 713e098bc96SEvan Quan * level by writing a string that contains "s/m level clock voltage" to 714e098bc96SEvan Quan * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 715e098bc96SEvan Quan * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 716e098bc96SEvan Quan * 810 mV. When you have edited all of the states as needed, write 717e098bc96SEvan Quan * "c" (commit) to the file to commit your changes. If you want to reset to the 718e098bc96SEvan Quan * default power levels, write "r" (reset) to the file to reset them. 719e098bc96SEvan Quan * 720e098bc96SEvan Quan * 721e098bc96SEvan Quan * < For Vega20 and newer ASICs > 722e098bc96SEvan Quan * 723e098bc96SEvan Quan * Reading the file will display: 724e098bc96SEvan Quan * 725e098bc96SEvan Quan * - minimum and maximum engine clock labeled OD_SCLK 726e098bc96SEvan Quan * 727e098bc96SEvan Quan * - maximum memory clock labeled OD_MCLK 728e098bc96SEvan Quan * 729e098bc96SEvan Quan * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 730e098bc96SEvan Quan * They can be used to calibrate the sclk voltage curve. 731e098bc96SEvan Quan * 732e098bc96SEvan Quan * - a list of valid ranges for sclk, mclk, and voltage curve points 733e098bc96SEvan Quan * labeled OD_RANGE 734e098bc96SEvan Quan * 735e098bc96SEvan Quan * To manually adjust these settings: 736e098bc96SEvan Quan * 737e098bc96SEvan Quan * - First select manual using power_dpm_force_performance_level 738e098bc96SEvan Quan * 739e098bc96SEvan Quan * - For clock frequency setting, enter a new value by writing a 740e098bc96SEvan Quan * string that contains "s/m index clock" to the file. The index 741e098bc96SEvan Quan * should be 0 if to set minimum clock. And 1 if to set maximum 742e098bc96SEvan Quan * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 743e098bc96SEvan Quan * "m 1 800" will update maximum mclk to be 800Mhz. 744e098bc96SEvan Quan * 745e098bc96SEvan Quan * For sclk voltage curve, enter the new values by writing a 746e098bc96SEvan Quan * string that contains "vc point clock voltage" to the file. The 747e098bc96SEvan Quan * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will 748e098bc96SEvan Quan * update point1 with clock set as 300Mhz and voltage as 749e098bc96SEvan Quan * 600mV. "vc 2 1000 1000" will update point3 with clock set 750e098bc96SEvan Quan * as 1000Mhz and voltage 1000mV. 751e098bc96SEvan Quan * 752e098bc96SEvan Quan * - When you have edited all of the states as needed, write "c" (commit) 753e098bc96SEvan Quan * to the file to commit your changes 754e098bc96SEvan Quan * 755e098bc96SEvan Quan * - If you want to reset to the default power levels, write "r" (reset) 756e098bc96SEvan Quan * to the file to reset them 757e098bc96SEvan Quan * 758e098bc96SEvan Quan */ 759e098bc96SEvan Quan 760e098bc96SEvan Quan static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 761e098bc96SEvan Quan struct device_attribute *attr, 762e098bc96SEvan Quan const char *buf, 763e098bc96SEvan Quan size_t count) 764e098bc96SEvan Quan { 765e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 7661348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 767e098bc96SEvan Quan int ret; 768e098bc96SEvan Quan uint32_t parameter_size = 0; 769e098bc96SEvan Quan long parameter[64]; 770e098bc96SEvan Quan char buf_cpy[128]; 771e098bc96SEvan Quan char *tmp_str; 772e098bc96SEvan Quan char *sub_str; 773e098bc96SEvan Quan const char delimiter[3] = {' ', '\n', '\0'}; 774e098bc96SEvan Quan uint32_t type; 775e098bc96SEvan Quan 77653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 777e098bc96SEvan Quan return -EPERM; 778e098bc96SEvan Quan 779e098bc96SEvan Quan if (count > 127) 780e098bc96SEvan Quan return -EINVAL; 781e098bc96SEvan Quan 782e098bc96SEvan Quan if (*buf == 's') 783e098bc96SEvan Quan type = PP_OD_EDIT_SCLK_VDDC_TABLE; 784e098bc96SEvan Quan else if (*buf == 'm') 785e098bc96SEvan Quan type = PP_OD_EDIT_MCLK_VDDC_TABLE; 786e098bc96SEvan Quan else if(*buf == 'r') 787e098bc96SEvan Quan type = PP_OD_RESTORE_DEFAULT_TABLE; 788e098bc96SEvan Quan else if (*buf == 'c') 789e098bc96SEvan Quan type = PP_OD_COMMIT_DPM_TABLE; 790e098bc96SEvan Quan else if (!strncmp(buf, "vc", 2)) 791e098bc96SEvan Quan type = PP_OD_EDIT_VDDC_CURVE; 792e098bc96SEvan Quan else 793e098bc96SEvan Quan return -EINVAL; 794e098bc96SEvan Quan 795e098bc96SEvan Quan memcpy(buf_cpy, buf, count+1); 796e098bc96SEvan Quan 797e098bc96SEvan Quan tmp_str = buf_cpy; 798e098bc96SEvan Quan 799e098bc96SEvan Quan if (type == PP_OD_EDIT_VDDC_CURVE) 800e098bc96SEvan Quan tmp_str++; 801e098bc96SEvan Quan while (isspace(*++tmp_str)); 802e098bc96SEvan Quan 803e098bc96SEvan Quan while (tmp_str[0]) { 804e098bc96SEvan Quan sub_str = strsep(&tmp_str, delimiter); 805e098bc96SEvan Quan ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 806e098bc96SEvan Quan if (ret) 807e098bc96SEvan Quan return -EINVAL; 808e098bc96SEvan Quan parameter_size++; 809e098bc96SEvan Quan 810e098bc96SEvan Quan while (isspace(*tmp_str)) 811e098bc96SEvan Quan tmp_str++; 812e098bc96SEvan Quan } 813e098bc96SEvan Quan 814e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 815e098bc96SEvan Quan if (ret < 0) { 816e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 817e098bc96SEvan Quan return ret; 818e098bc96SEvan Quan } 819e098bc96SEvan Quan 820e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 821e098bc96SEvan Quan ret = smu_od_edit_dpm_table(&adev->smu, type, 822e098bc96SEvan Quan parameter, parameter_size); 823e098bc96SEvan Quan 824e098bc96SEvan Quan if (ret) { 825e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 826e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 827e098bc96SEvan Quan return -EINVAL; 828e098bc96SEvan Quan } 829e098bc96SEvan Quan } else { 83012a6727dSXiaojian Du 83112a6727dSXiaojian Du if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) { 83212a6727dSXiaojian Du ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type, 83312a6727dSXiaojian Du parameter, 83412a6727dSXiaojian Du parameter_size); 83512a6727dSXiaojian Du if (ret) { 83612a6727dSXiaojian Du pm_runtime_mark_last_busy(ddev->dev); 83712a6727dSXiaojian Du pm_runtime_put_autosuspend(ddev->dev); 83812a6727dSXiaojian Du return -EINVAL; 83912a6727dSXiaojian Du } 84012a6727dSXiaojian Du } 84112a6727dSXiaojian Du 842e098bc96SEvan Quan if (adev->powerplay.pp_funcs->odn_edit_dpm_table) { 843e098bc96SEvan Quan ret = amdgpu_dpm_odn_edit_dpm_table(adev, type, 844e098bc96SEvan Quan parameter, parameter_size); 845e098bc96SEvan Quan if (ret) { 846e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 847e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 848e098bc96SEvan Quan return -EINVAL; 849e098bc96SEvan Quan } 850e098bc96SEvan Quan } 851e098bc96SEvan Quan 852e098bc96SEvan Quan if (type == PP_OD_COMMIT_DPM_TABLE) { 853e098bc96SEvan Quan if (adev->powerplay.pp_funcs->dispatch_tasks) { 854e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, 855e098bc96SEvan Quan AMD_PP_TASK_READJUST_POWER_STATE, 856e098bc96SEvan Quan NULL); 857e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 858e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 859e098bc96SEvan Quan return count; 860e098bc96SEvan Quan } else { 861e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 862e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 863e098bc96SEvan Quan return -EINVAL; 864e098bc96SEvan Quan } 865e098bc96SEvan Quan } 866e098bc96SEvan Quan } 867e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 868e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 869e098bc96SEvan Quan 870e098bc96SEvan Quan return count; 871e098bc96SEvan Quan } 872e098bc96SEvan Quan 873e098bc96SEvan Quan static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 874e098bc96SEvan Quan struct device_attribute *attr, 875e098bc96SEvan Quan char *buf) 876e098bc96SEvan Quan { 877e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 8781348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 879e098bc96SEvan Quan ssize_t size; 880e098bc96SEvan Quan int ret; 881e098bc96SEvan Quan 88253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 883e098bc96SEvan Quan return -EPERM; 884e098bc96SEvan Quan 885e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 886e098bc96SEvan Quan if (ret < 0) { 887e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 888e098bc96SEvan Quan return ret; 889e098bc96SEvan Quan } 890e098bc96SEvan Quan 891e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 892e098bc96SEvan Quan size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf); 893e098bc96SEvan Quan size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size); 894e098bc96SEvan Quan size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size); 895e098bc96SEvan Quan size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size); 896e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->print_clock_levels) { 897e098bc96SEvan Quan size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 898e098bc96SEvan Quan size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size); 899e098bc96SEvan Quan size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size); 900e098bc96SEvan Quan size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size); 901e098bc96SEvan Quan } else { 902e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 903e098bc96SEvan Quan } 904e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 905e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 906e098bc96SEvan Quan 907e098bc96SEvan Quan return size; 908e098bc96SEvan Quan } 909e098bc96SEvan Quan 910e098bc96SEvan Quan /** 911e098bc96SEvan Quan * DOC: pp_features 912e098bc96SEvan Quan * 913e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting what powerplay 914e098bc96SEvan Quan * features to be enabled. The file pp_features is used for this. And 915e098bc96SEvan Quan * this is only available for Vega10 and later dGPUs. 916e098bc96SEvan Quan * 917e098bc96SEvan Quan * Reading back the file will show you the followings: 918e098bc96SEvan Quan * - Current ppfeature masks 919e098bc96SEvan Quan * - List of the all supported powerplay features with their naming, 920e098bc96SEvan Quan * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 921e098bc96SEvan Quan * 922e098bc96SEvan Quan * To manually enable or disable a specific feature, just set or clear 923e098bc96SEvan Quan * the corresponding bit from original ppfeature masks and input the 924e098bc96SEvan Quan * new ppfeature masks. 925e098bc96SEvan Quan */ 926e098bc96SEvan Quan static ssize_t amdgpu_set_pp_features(struct device *dev, 927e098bc96SEvan Quan struct device_attribute *attr, 928e098bc96SEvan Quan const char *buf, 929e098bc96SEvan Quan size_t count) 930e098bc96SEvan Quan { 931e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 9321348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 933e098bc96SEvan Quan uint64_t featuremask; 934e098bc96SEvan Quan int ret; 935e098bc96SEvan Quan 93653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 937e098bc96SEvan Quan return -EPERM; 938e098bc96SEvan Quan 939e098bc96SEvan Quan ret = kstrtou64(buf, 0, &featuremask); 940e098bc96SEvan Quan if (ret) 941e098bc96SEvan Quan return -EINVAL; 942e098bc96SEvan Quan 943e098bc96SEvan Quan pr_debug("featuremask = 0x%llx\n", featuremask); 944e098bc96SEvan Quan 945e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 946e098bc96SEvan Quan if (ret < 0) { 947e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 948e098bc96SEvan Quan return ret; 949e098bc96SEvan Quan } 950e098bc96SEvan Quan 951e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 952e098bc96SEvan Quan ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask); 953e098bc96SEvan Quan if (ret) { 954e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 955e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 956e098bc96SEvan Quan return -EINVAL; 957e098bc96SEvan Quan } 958e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->set_ppfeature_status) { 959e098bc96SEvan Quan ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 960e098bc96SEvan Quan if (ret) { 961e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 962e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 963e098bc96SEvan Quan return -EINVAL; 964e098bc96SEvan Quan } 965e098bc96SEvan Quan } 966e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 967e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 968e098bc96SEvan Quan 969e098bc96SEvan Quan return count; 970e098bc96SEvan Quan } 971e098bc96SEvan Quan 972e098bc96SEvan Quan static ssize_t amdgpu_get_pp_features(struct device *dev, 973e098bc96SEvan Quan struct device_attribute *attr, 974e098bc96SEvan Quan char *buf) 975e098bc96SEvan Quan { 976e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 9771348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 978e098bc96SEvan Quan ssize_t size; 979e098bc96SEvan Quan int ret; 980e098bc96SEvan Quan 98153b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 982e098bc96SEvan Quan return -EPERM; 983e098bc96SEvan Quan 984e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 985e098bc96SEvan Quan if (ret < 0) { 986e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 987e098bc96SEvan Quan return ret; 988e098bc96SEvan Quan } 989e098bc96SEvan Quan 990e098bc96SEvan Quan if (is_support_sw_smu(adev)) 991e098bc96SEvan Quan size = smu_sys_get_pp_feature_mask(&adev->smu, buf); 992e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_ppfeature_status) 993e098bc96SEvan Quan size = amdgpu_dpm_get_ppfeature_status(adev, buf); 994e098bc96SEvan Quan else 995e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 996e098bc96SEvan Quan 997e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 998e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 999e098bc96SEvan Quan 1000e098bc96SEvan Quan return size; 1001e098bc96SEvan Quan } 1002e098bc96SEvan Quan 1003e098bc96SEvan Quan /** 1004e098bc96SEvan Quan * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 1005e098bc96SEvan Quan * 1006e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting what power levels 1007e098bc96SEvan Quan * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 1008e098bc96SEvan Quan * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 1009e098bc96SEvan Quan * this. 1010e098bc96SEvan Quan * 1011e098bc96SEvan Quan * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 1012e098bc96SEvan Quan * Vega10 and later ASICs. 1013e098bc96SEvan Quan * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 1014e098bc96SEvan Quan * 1015e098bc96SEvan Quan * Reading back the files will show you the available power levels within 1016e098bc96SEvan Quan * the power state and the clock information for those levels. 1017e098bc96SEvan Quan * 1018e098bc96SEvan Quan * To manually adjust these states, first select manual using 1019e098bc96SEvan Quan * power_dpm_force_performance_level. 1020e098bc96SEvan Quan * Secondly, enter a new value for each level by inputing a string that 1021e098bc96SEvan Quan * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 1022e098bc96SEvan Quan * E.g., 1023e098bc96SEvan Quan * 1024e098bc96SEvan Quan * .. code-block:: bash 1025e098bc96SEvan Quan * 1026e098bc96SEvan Quan * echo "4 5 6" > pp_dpm_sclk 1027e098bc96SEvan Quan * 1028e098bc96SEvan Quan * will enable sclk levels 4, 5, and 6. 1029e098bc96SEvan Quan * 1030e098bc96SEvan Quan * NOTE: change to the dcefclk max dpm level is not supported now 1031e098bc96SEvan Quan */ 1032e098bc96SEvan Quan 1033e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1034e098bc96SEvan Quan struct device_attribute *attr, 1035e098bc96SEvan Quan char *buf) 1036e098bc96SEvan Quan { 1037e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 10381348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1039e098bc96SEvan Quan ssize_t size; 1040e098bc96SEvan Quan int ret; 1041e098bc96SEvan Quan 104253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1043e098bc96SEvan Quan return -EPERM; 1044e098bc96SEvan Quan 1045e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1046e098bc96SEvan Quan if (ret < 0) { 1047e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1048e098bc96SEvan Quan return ret; 1049e098bc96SEvan Quan } 1050e098bc96SEvan Quan 1051e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1052e098bc96SEvan Quan size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf); 1053e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->print_clock_levels) 1054e098bc96SEvan Quan size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf); 1055e098bc96SEvan Quan else 1056e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1057e098bc96SEvan Quan 1058e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1059e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1060e098bc96SEvan Quan 1061e098bc96SEvan Quan return size; 1062e098bc96SEvan Quan } 1063e098bc96SEvan Quan 1064e098bc96SEvan Quan /* 1065e098bc96SEvan Quan * Worst case: 32 bits individually specified, in octal at 12 characters 1066e098bc96SEvan Quan * per line (+1 for \n). 1067e098bc96SEvan Quan */ 1068e098bc96SEvan Quan #define AMDGPU_MASK_BUF_MAX (32 * 13) 1069e098bc96SEvan Quan 1070e098bc96SEvan Quan static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1071e098bc96SEvan Quan { 1072e098bc96SEvan Quan int ret; 1073e098bc96SEvan Quan long level; 1074e098bc96SEvan Quan char *sub_str = NULL; 1075e098bc96SEvan Quan char *tmp; 1076e098bc96SEvan Quan char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1077e098bc96SEvan Quan const char delimiter[3] = {' ', '\n', '\0'}; 1078e098bc96SEvan Quan size_t bytes; 1079e098bc96SEvan Quan 1080e098bc96SEvan Quan *mask = 0; 1081e098bc96SEvan Quan 1082e098bc96SEvan Quan bytes = min(count, sizeof(buf_cpy) - 1); 1083e098bc96SEvan Quan memcpy(buf_cpy, buf, bytes); 1084e098bc96SEvan Quan buf_cpy[bytes] = '\0'; 1085e098bc96SEvan Quan tmp = buf_cpy; 1086e098bc96SEvan Quan while (tmp[0]) { 1087e098bc96SEvan Quan sub_str = strsep(&tmp, delimiter); 1088e098bc96SEvan Quan if (strlen(sub_str)) { 1089e098bc96SEvan Quan ret = kstrtol(sub_str, 0, &level); 1090e098bc96SEvan Quan if (ret) 1091e098bc96SEvan Quan return -EINVAL; 1092e098bc96SEvan Quan *mask |= 1 << level; 1093e098bc96SEvan Quan } else 1094e098bc96SEvan Quan break; 1095e098bc96SEvan Quan } 1096e098bc96SEvan Quan 1097e098bc96SEvan Quan return 0; 1098e098bc96SEvan Quan } 1099e098bc96SEvan Quan 1100e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1101e098bc96SEvan Quan struct device_attribute *attr, 1102e098bc96SEvan Quan const char *buf, 1103e098bc96SEvan Quan size_t count) 1104e098bc96SEvan Quan { 1105e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 11061348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1107e098bc96SEvan Quan int ret; 1108e098bc96SEvan Quan uint32_t mask = 0; 1109e098bc96SEvan Quan 111053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1111e098bc96SEvan Quan return -EPERM; 1112e098bc96SEvan Quan 1113e098bc96SEvan Quan ret = amdgpu_read_mask(buf, count, &mask); 1114e098bc96SEvan Quan if (ret) 1115e098bc96SEvan Quan return ret; 1116e098bc96SEvan Quan 1117e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1118e098bc96SEvan Quan if (ret < 0) { 1119e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1120e098bc96SEvan Quan return ret; 1121e098bc96SEvan Quan } 1122e098bc96SEvan Quan 1123e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1124e098bc96SEvan Quan ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask); 1125e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->force_clock_level) 1126e098bc96SEvan Quan ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); 1127e098bc96SEvan Quan 1128e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1129e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1130e098bc96SEvan Quan 1131e098bc96SEvan Quan if (ret) 1132e098bc96SEvan Quan return -EINVAL; 1133e098bc96SEvan Quan 1134e098bc96SEvan Quan return count; 1135e098bc96SEvan Quan } 1136e098bc96SEvan Quan 1137e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1138e098bc96SEvan Quan struct device_attribute *attr, 1139e098bc96SEvan Quan char *buf) 1140e098bc96SEvan Quan { 1141e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 11421348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1143e098bc96SEvan Quan ssize_t size; 1144e098bc96SEvan Quan int ret; 1145e098bc96SEvan Quan 114653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1147e098bc96SEvan Quan return -EPERM; 1148e098bc96SEvan Quan 1149e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1150e098bc96SEvan Quan if (ret < 0) { 1151e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1152e098bc96SEvan Quan return ret; 1153e098bc96SEvan Quan } 1154e098bc96SEvan Quan 1155e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1156e098bc96SEvan Quan size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf); 1157e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->print_clock_levels) 1158e098bc96SEvan Quan size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf); 1159e098bc96SEvan Quan else 1160e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1161e098bc96SEvan Quan 1162e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1163e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1164e098bc96SEvan Quan 1165e098bc96SEvan Quan return size; 1166e098bc96SEvan Quan } 1167e098bc96SEvan Quan 1168e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1169e098bc96SEvan Quan struct device_attribute *attr, 1170e098bc96SEvan Quan const char *buf, 1171e098bc96SEvan Quan size_t count) 1172e098bc96SEvan Quan { 1173e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 11741348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1175e098bc96SEvan Quan uint32_t mask = 0; 1176e098bc96SEvan Quan int ret; 1177e098bc96SEvan Quan 117853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1179e098bc96SEvan Quan return -EPERM; 1180e098bc96SEvan Quan 1181e098bc96SEvan Quan ret = amdgpu_read_mask(buf, count, &mask); 1182e098bc96SEvan Quan if (ret) 1183e098bc96SEvan Quan return ret; 1184e098bc96SEvan Quan 1185e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1186e098bc96SEvan Quan if (ret < 0) { 1187e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1188e098bc96SEvan Quan return ret; 1189e098bc96SEvan Quan } 1190e098bc96SEvan Quan 1191e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1192e098bc96SEvan Quan ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask); 1193e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->force_clock_level) 1194e098bc96SEvan Quan ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); 1195e098bc96SEvan Quan 1196e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1197e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1198e098bc96SEvan Quan 1199e098bc96SEvan Quan if (ret) 1200e098bc96SEvan Quan return -EINVAL; 1201e098bc96SEvan Quan 1202e098bc96SEvan Quan return count; 1203e098bc96SEvan Quan } 1204e098bc96SEvan Quan 1205e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1206e098bc96SEvan Quan struct device_attribute *attr, 1207e098bc96SEvan Quan char *buf) 1208e098bc96SEvan Quan { 1209e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 12101348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1211e098bc96SEvan Quan ssize_t size; 1212e098bc96SEvan Quan int ret; 1213e098bc96SEvan Quan 121453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1215e098bc96SEvan Quan return -EPERM; 1216e098bc96SEvan Quan 1217e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1218e098bc96SEvan Quan if (ret < 0) { 1219e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1220e098bc96SEvan Quan return ret; 1221e098bc96SEvan Quan } 1222e098bc96SEvan Quan 1223e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1224e098bc96SEvan Quan size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf); 1225e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->print_clock_levels) 1226e098bc96SEvan Quan size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf); 1227e098bc96SEvan Quan else 1228e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1229e098bc96SEvan Quan 1230e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1231e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1232e098bc96SEvan Quan 1233e098bc96SEvan Quan return size; 1234e098bc96SEvan Quan } 1235e098bc96SEvan Quan 1236e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1237e098bc96SEvan Quan struct device_attribute *attr, 1238e098bc96SEvan Quan const char *buf, 1239e098bc96SEvan Quan size_t count) 1240e098bc96SEvan Quan { 1241e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 12421348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1243e098bc96SEvan Quan int ret; 1244e098bc96SEvan Quan uint32_t mask = 0; 1245e098bc96SEvan Quan 124653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1247e098bc96SEvan Quan return -EPERM; 1248e098bc96SEvan Quan 1249e098bc96SEvan Quan ret = amdgpu_read_mask(buf, count, &mask); 1250e098bc96SEvan Quan if (ret) 1251e098bc96SEvan Quan return ret; 1252e098bc96SEvan Quan 1253e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1254e098bc96SEvan Quan if (ret < 0) { 1255e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1256e098bc96SEvan Quan return ret; 1257e098bc96SEvan Quan } 1258e098bc96SEvan Quan 1259e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1260e098bc96SEvan Quan ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask); 1261e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->force_clock_level) 1262e098bc96SEvan Quan ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask); 1263e098bc96SEvan Quan else 1264e098bc96SEvan Quan ret = 0; 1265e098bc96SEvan Quan 1266e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1267e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1268e098bc96SEvan Quan 1269e098bc96SEvan Quan if (ret) 1270e098bc96SEvan Quan return -EINVAL; 1271e098bc96SEvan Quan 1272e098bc96SEvan Quan return count; 1273e098bc96SEvan Quan } 1274e098bc96SEvan Quan 1275e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1276e098bc96SEvan Quan struct device_attribute *attr, 1277e098bc96SEvan Quan char *buf) 1278e098bc96SEvan Quan { 1279e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 12801348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1281e098bc96SEvan Quan ssize_t size; 1282e098bc96SEvan Quan int ret; 1283e098bc96SEvan Quan 128453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1285e098bc96SEvan Quan return -EPERM; 1286e098bc96SEvan Quan 1287e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1288e098bc96SEvan Quan if (ret < 0) { 1289e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1290e098bc96SEvan Quan return ret; 1291e098bc96SEvan Quan } 1292e098bc96SEvan Quan 1293e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1294e098bc96SEvan Quan size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf); 1295e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->print_clock_levels) 1296e098bc96SEvan Quan size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf); 1297e098bc96SEvan Quan else 1298e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1299e098bc96SEvan Quan 1300e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1301e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1302e098bc96SEvan Quan 1303e098bc96SEvan Quan return size; 1304e098bc96SEvan Quan } 1305e098bc96SEvan Quan 1306e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1307e098bc96SEvan Quan struct device_attribute *attr, 1308e098bc96SEvan Quan const char *buf, 1309e098bc96SEvan Quan size_t count) 1310e098bc96SEvan Quan { 1311e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 13121348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1313e098bc96SEvan Quan int ret; 1314e098bc96SEvan Quan uint32_t mask = 0; 1315e098bc96SEvan Quan 131653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1317e098bc96SEvan Quan return -EPERM; 1318e098bc96SEvan Quan 1319e098bc96SEvan Quan ret = amdgpu_read_mask(buf, count, &mask); 1320e098bc96SEvan Quan if (ret) 1321e098bc96SEvan Quan return ret; 1322e098bc96SEvan Quan 1323e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1324e098bc96SEvan Quan if (ret < 0) { 1325e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1326e098bc96SEvan Quan return ret; 1327e098bc96SEvan Quan } 1328e098bc96SEvan Quan 1329e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1330e098bc96SEvan Quan ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask); 1331e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->force_clock_level) 1332e098bc96SEvan Quan ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask); 1333e098bc96SEvan Quan else 1334e098bc96SEvan Quan ret = 0; 1335e098bc96SEvan Quan 1336e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1337e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1338e098bc96SEvan Quan 1339e098bc96SEvan Quan if (ret) 1340e098bc96SEvan Quan return -EINVAL; 1341e098bc96SEvan Quan 1342e098bc96SEvan Quan return count; 1343e098bc96SEvan Quan } 1344e098bc96SEvan Quan 1345e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1346e098bc96SEvan Quan struct device_attribute *attr, 1347e098bc96SEvan Quan char *buf) 1348e098bc96SEvan Quan { 1349e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 13501348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1351e098bc96SEvan Quan ssize_t size; 1352e098bc96SEvan Quan int ret; 1353e098bc96SEvan Quan 135453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1355e098bc96SEvan Quan return -EPERM; 1356e098bc96SEvan Quan 1357e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1358e098bc96SEvan Quan if (ret < 0) { 1359e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1360e098bc96SEvan Quan return ret; 1361e098bc96SEvan Quan } 1362e098bc96SEvan Quan 1363e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1364e098bc96SEvan Quan size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf); 1365e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->print_clock_levels) 1366e098bc96SEvan Quan size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf); 1367e098bc96SEvan Quan else 1368e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1369e098bc96SEvan Quan 1370e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1371e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1372e098bc96SEvan Quan 1373e098bc96SEvan Quan return size; 1374e098bc96SEvan Quan } 1375e098bc96SEvan Quan 1376e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1377e098bc96SEvan Quan struct device_attribute *attr, 1378e098bc96SEvan Quan const char *buf, 1379e098bc96SEvan Quan size_t count) 1380e098bc96SEvan Quan { 1381e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 13821348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1383e098bc96SEvan Quan int ret; 1384e098bc96SEvan Quan uint32_t mask = 0; 1385e098bc96SEvan Quan 138653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1387e098bc96SEvan Quan return -EPERM; 1388e098bc96SEvan Quan 1389e098bc96SEvan Quan ret = amdgpu_read_mask(buf, count, &mask); 1390e098bc96SEvan Quan if (ret) 1391e098bc96SEvan Quan return ret; 1392e098bc96SEvan Quan 1393e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1394e098bc96SEvan Quan if (ret < 0) { 1395e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1396e098bc96SEvan Quan return ret; 1397e098bc96SEvan Quan } 1398e098bc96SEvan Quan 1399e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1400e098bc96SEvan Quan ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask); 1401e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->force_clock_level) 1402e098bc96SEvan Quan ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask); 1403e098bc96SEvan Quan else 1404e098bc96SEvan Quan ret = 0; 1405e098bc96SEvan Quan 1406e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1407e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1408e098bc96SEvan Quan 1409e098bc96SEvan Quan if (ret) 1410e098bc96SEvan Quan return -EINVAL; 1411e098bc96SEvan Quan 1412e098bc96SEvan Quan return count; 1413e098bc96SEvan Quan } 1414e098bc96SEvan Quan 1415e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1416e098bc96SEvan Quan struct device_attribute *attr, 1417e098bc96SEvan Quan char *buf) 1418e098bc96SEvan Quan { 1419e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 14201348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1421e098bc96SEvan Quan ssize_t size; 1422e098bc96SEvan Quan int ret; 1423e098bc96SEvan Quan 142453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1425e098bc96SEvan Quan return -EPERM; 1426e098bc96SEvan Quan 1427e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1428e098bc96SEvan Quan if (ret < 0) { 1429e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1430e098bc96SEvan Quan return ret; 1431e098bc96SEvan Quan } 1432e098bc96SEvan Quan 1433e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1434e098bc96SEvan Quan size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf); 1435e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->print_clock_levels) 1436e098bc96SEvan Quan size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf); 1437e098bc96SEvan Quan else 1438e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1439e098bc96SEvan Quan 1440e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1441e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1442e098bc96SEvan Quan 1443e098bc96SEvan Quan return size; 1444e098bc96SEvan Quan } 1445e098bc96SEvan Quan 1446e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1447e098bc96SEvan Quan struct device_attribute *attr, 1448e098bc96SEvan Quan const char *buf, 1449e098bc96SEvan Quan size_t count) 1450e098bc96SEvan Quan { 1451e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 14521348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1453e098bc96SEvan Quan int ret; 1454e098bc96SEvan Quan uint32_t mask = 0; 1455e098bc96SEvan Quan 145653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1457e098bc96SEvan Quan return -EPERM; 1458e098bc96SEvan Quan 1459e098bc96SEvan Quan ret = amdgpu_read_mask(buf, count, &mask); 1460e098bc96SEvan Quan if (ret) 1461e098bc96SEvan Quan return ret; 1462e098bc96SEvan Quan 1463e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1464e098bc96SEvan Quan if (ret < 0) { 1465e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1466e098bc96SEvan Quan return ret; 1467e098bc96SEvan Quan } 1468e098bc96SEvan Quan 1469e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1470e098bc96SEvan Quan ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask); 1471e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->force_clock_level) 1472e098bc96SEvan Quan ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); 1473e098bc96SEvan Quan else 1474e098bc96SEvan Quan ret = 0; 1475e098bc96SEvan Quan 1476e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1477e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1478e098bc96SEvan Quan 1479e098bc96SEvan Quan if (ret) 1480e098bc96SEvan Quan return -EINVAL; 1481e098bc96SEvan Quan 1482e098bc96SEvan Quan return count; 1483e098bc96SEvan Quan } 1484e098bc96SEvan Quan 1485e098bc96SEvan Quan static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1486e098bc96SEvan Quan struct device_attribute *attr, 1487e098bc96SEvan Quan char *buf) 1488e098bc96SEvan Quan { 1489e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 14901348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1491e098bc96SEvan Quan uint32_t value = 0; 1492e098bc96SEvan Quan int ret; 1493e098bc96SEvan Quan 149453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1495e098bc96SEvan Quan return -EPERM; 1496e098bc96SEvan Quan 1497e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1498e098bc96SEvan Quan if (ret < 0) { 1499e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1500e098bc96SEvan Quan return ret; 1501e098bc96SEvan Quan } 1502e098bc96SEvan Quan 1503e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1504*75145aabSAlex Deucher value = 0; 1505e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_sclk_od) 1506e098bc96SEvan Quan value = amdgpu_dpm_get_sclk_od(adev); 1507e098bc96SEvan Quan 1508e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1509e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1510e098bc96SEvan Quan 1511e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", value); 1512e098bc96SEvan Quan } 1513e098bc96SEvan Quan 1514e098bc96SEvan Quan static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1515e098bc96SEvan Quan struct device_attribute *attr, 1516e098bc96SEvan Quan const char *buf, 1517e098bc96SEvan Quan size_t count) 1518e098bc96SEvan Quan { 1519e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 15201348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1521e098bc96SEvan Quan int ret; 1522e098bc96SEvan Quan long int value; 1523e098bc96SEvan Quan 152453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1525e098bc96SEvan Quan return -EPERM; 1526e098bc96SEvan Quan 1527e098bc96SEvan Quan ret = kstrtol(buf, 0, &value); 1528e098bc96SEvan Quan 1529e098bc96SEvan Quan if (ret) 1530e098bc96SEvan Quan return -EINVAL; 1531e098bc96SEvan Quan 1532e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1533e098bc96SEvan Quan if (ret < 0) { 1534e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1535e098bc96SEvan Quan return ret; 1536e098bc96SEvan Quan } 1537e098bc96SEvan Quan 1538e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 1539*75145aabSAlex Deucher value = 0; 1540e098bc96SEvan Quan } else { 1541e098bc96SEvan Quan if (adev->powerplay.pp_funcs->set_sclk_od) 1542e098bc96SEvan Quan amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1543e098bc96SEvan Quan 1544e098bc96SEvan Quan if (adev->powerplay.pp_funcs->dispatch_tasks) { 1545e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 1546e098bc96SEvan Quan } else { 1547e098bc96SEvan Quan adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1548e098bc96SEvan Quan amdgpu_pm_compute_clocks(adev); 1549e098bc96SEvan Quan } 1550e098bc96SEvan Quan } 1551e098bc96SEvan Quan 1552e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1553e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1554e098bc96SEvan Quan 1555e098bc96SEvan Quan return count; 1556e098bc96SEvan Quan } 1557e098bc96SEvan Quan 1558e098bc96SEvan Quan static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1559e098bc96SEvan Quan struct device_attribute *attr, 1560e098bc96SEvan Quan char *buf) 1561e098bc96SEvan Quan { 1562e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 15631348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1564e098bc96SEvan Quan uint32_t value = 0; 1565e098bc96SEvan Quan int ret; 1566e098bc96SEvan Quan 156753b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1568e098bc96SEvan Quan return -EPERM; 1569e098bc96SEvan Quan 1570e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1571e098bc96SEvan Quan if (ret < 0) { 1572e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1573e098bc96SEvan Quan return ret; 1574e098bc96SEvan Quan } 1575e098bc96SEvan Quan 1576e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1577*75145aabSAlex Deucher value = 0; 1578e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_mclk_od) 1579e098bc96SEvan Quan value = amdgpu_dpm_get_mclk_od(adev); 1580e098bc96SEvan Quan 1581e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1582e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1583e098bc96SEvan Quan 1584e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", value); 1585e098bc96SEvan Quan } 1586e098bc96SEvan Quan 1587e098bc96SEvan Quan static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1588e098bc96SEvan Quan struct device_attribute *attr, 1589e098bc96SEvan Quan const char *buf, 1590e098bc96SEvan Quan size_t count) 1591e098bc96SEvan Quan { 1592e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 15931348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1594e098bc96SEvan Quan int ret; 1595e098bc96SEvan Quan long int value; 1596e098bc96SEvan Quan 159753b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1598e098bc96SEvan Quan return -EPERM; 1599e098bc96SEvan Quan 1600e098bc96SEvan Quan ret = kstrtol(buf, 0, &value); 1601e098bc96SEvan Quan 1602e098bc96SEvan Quan if (ret) 1603e098bc96SEvan Quan return -EINVAL; 1604e098bc96SEvan Quan 1605e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1606e098bc96SEvan Quan if (ret < 0) { 1607e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1608e098bc96SEvan Quan return ret; 1609e098bc96SEvan Quan } 1610e098bc96SEvan Quan 1611e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 1612*75145aabSAlex Deucher value = 0; 1613e098bc96SEvan Quan } else { 1614e098bc96SEvan Quan if (adev->powerplay.pp_funcs->set_mclk_od) 1615e098bc96SEvan Quan amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1616e098bc96SEvan Quan 1617e098bc96SEvan Quan if (adev->powerplay.pp_funcs->dispatch_tasks) { 1618e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 1619e098bc96SEvan Quan } else { 1620e098bc96SEvan Quan adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1621e098bc96SEvan Quan amdgpu_pm_compute_clocks(adev); 1622e098bc96SEvan Quan } 1623e098bc96SEvan Quan } 1624e098bc96SEvan Quan 1625e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1626e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1627e098bc96SEvan Quan 1628e098bc96SEvan Quan return count; 1629e098bc96SEvan Quan } 1630e098bc96SEvan Quan 1631e098bc96SEvan Quan /** 1632e098bc96SEvan Quan * DOC: pp_power_profile_mode 1633e098bc96SEvan Quan * 1634e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting the heuristics 1635e098bc96SEvan Quan * related to switching between power levels in a power state. The file 1636e098bc96SEvan Quan * pp_power_profile_mode is used for this. 1637e098bc96SEvan Quan * 1638e098bc96SEvan Quan * Reading this file outputs a list of all of the predefined power profiles 1639e098bc96SEvan Quan * and the relevant heuristics settings for that profile. 1640e098bc96SEvan Quan * 1641e098bc96SEvan Quan * To select a profile or create a custom profile, first select manual using 1642e098bc96SEvan Quan * power_dpm_force_performance_level. Writing the number of a predefined 1643e098bc96SEvan Quan * profile to pp_power_profile_mode will enable those heuristics. To 1644e098bc96SEvan Quan * create a custom set of heuristics, write a string of numbers to the file 1645e098bc96SEvan Quan * starting with the number of the custom profile along with a setting 1646e098bc96SEvan Quan * for each heuristic parameter. Due to differences across asic families 1647e098bc96SEvan Quan * the heuristic parameters vary from family to family. 1648e098bc96SEvan Quan * 1649e098bc96SEvan Quan */ 1650e098bc96SEvan Quan 1651e098bc96SEvan Quan static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1652e098bc96SEvan Quan struct device_attribute *attr, 1653e098bc96SEvan Quan char *buf) 1654e098bc96SEvan Quan { 1655e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 16561348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1657e098bc96SEvan Quan ssize_t size; 1658e098bc96SEvan Quan int ret; 1659e098bc96SEvan Quan 166053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1661e098bc96SEvan Quan return -EPERM; 1662e098bc96SEvan Quan 1663e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1664e098bc96SEvan Quan if (ret < 0) { 1665e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1666e098bc96SEvan Quan return ret; 1667e098bc96SEvan Quan } 1668e098bc96SEvan Quan 1669e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1670e098bc96SEvan Quan size = smu_get_power_profile_mode(&adev->smu, buf); 1671e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_power_profile_mode) 1672e098bc96SEvan Quan size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1673e098bc96SEvan Quan else 1674e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1675e098bc96SEvan Quan 1676e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1677e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1678e098bc96SEvan Quan 1679e098bc96SEvan Quan return size; 1680e098bc96SEvan Quan } 1681e098bc96SEvan Quan 1682e098bc96SEvan Quan 1683e098bc96SEvan Quan static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1684e098bc96SEvan Quan struct device_attribute *attr, 1685e098bc96SEvan Quan const char *buf, 1686e098bc96SEvan Quan size_t count) 1687e098bc96SEvan Quan { 1688e098bc96SEvan Quan int ret; 1689e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 16901348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1691e098bc96SEvan Quan uint32_t parameter_size = 0; 1692e098bc96SEvan Quan long parameter[64]; 1693e098bc96SEvan Quan char *sub_str, buf_cpy[128]; 1694e098bc96SEvan Quan char *tmp_str; 1695e098bc96SEvan Quan uint32_t i = 0; 1696e098bc96SEvan Quan char tmp[2]; 1697e098bc96SEvan Quan long int profile_mode = 0; 1698e098bc96SEvan Quan const char delimiter[3] = {' ', '\n', '\0'}; 1699e098bc96SEvan Quan 170053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1701e098bc96SEvan Quan return -EPERM; 1702e098bc96SEvan Quan 1703e098bc96SEvan Quan tmp[0] = *(buf); 1704e098bc96SEvan Quan tmp[1] = '\0'; 1705e098bc96SEvan Quan ret = kstrtol(tmp, 0, &profile_mode); 1706e098bc96SEvan Quan if (ret) 1707e098bc96SEvan Quan return -EINVAL; 1708e098bc96SEvan Quan 1709e098bc96SEvan Quan if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1710e098bc96SEvan Quan if (count < 2 || count > 127) 1711e098bc96SEvan Quan return -EINVAL; 1712e098bc96SEvan Quan while (isspace(*++buf)) 1713e098bc96SEvan Quan i++; 1714e098bc96SEvan Quan memcpy(buf_cpy, buf, count-i); 1715e098bc96SEvan Quan tmp_str = buf_cpy; 1716e098bc96SEvan Quan while (tmp_str[0]) { 1717e098bc96SEvan Quan sub_str = strsep(&tmp_str, delimiter); 1718e098bc96SEvan Quan ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1719e098bc96SEvan Quan if (ret) 1720e098bc96SEvan Quan return -EINVAL; 1721e098bc96SEvan Quan parameter_size++; 1722e098bc96SEvan Quan while (isspace(*tmp_str)) 1723e098bc96SEvan Quan tmp_str++; 1724e098bc96SEvan Quan } 1725e098bc96SEvan Quan } 1726e098bc96SEvan Quan parameter[parameter_size] = profile_mode; 1727e098bc96SEvan Quan 1728e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1729e098bc96SEvan Quan if (ret < 0) { 1730e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1731e098bc96SEvan Quan return ret; 1732e098bc96SEvan Quan } 1733e098bc96SEvan Quan 1734e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1735e098bc96SEvan Quan ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true); 1736e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->set_power_profile_mode) 1737e098bc96SEvan Quan ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1738e098bc96SEvan Quan 1739e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1740e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1741e098bc96SEvan Quan 1742e098bc96SEvan Quan if (!ret) 1743e098bc96SEvan Quan return count; 1744e098bc96SEvan Quan 1745e098bc96SEvan Quan return -EINVAL; 1746e098bc96SEvan Quan } 1747e098bc96SEvan Quan 1748e098bc96SEvan Quan /** 1749e098bc96SEvan Quan * DOC: gpu_busy_percent 1750e098bc96SEvan Quan * 1751e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for reading how busy the GPU 1752e098bc96SEvan Quan * is as a percentage. The file gpu_busy_percent is used for this. 1753e098bc96SEvan Quan * The SMU firmware computes a percentage of load based on the 1754e098bc96SEvan Quan * aggregate activity level in the IP cores. 1755e098bc96SEvan Quan */ 1756e098bc96SEvan Quan static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1757e098bc96SEvan Quan struct device_attribute *attr, 1758e098bc96SEvan Quan char *buf) 1759e098bc96SEvan Quan { 1760e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 17611348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1762e098bc96SEvan Quan int r, value, size = sizeof(value); 1763e098bc96SEvan Quan 176453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1765e098bc96SEvan Quan return -EPERM; 1766e098bc96SEvan Quan 1767e098bc96SEvan Quan r = pm_runtime_get_sync(ddev->dev); 1768e098bc96SEvan Quan if (r < 0) { 1769e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1770e098bc96SEvan Quan return r; 1771e098bc96SEvan Quan } 1772e098bc96SEvan Quan 1773e098bc96SEvan Quan /* read the IP busy sensor */ 1774e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, 1775e098bc96SEvan Quan (void *)&value, &size); 1776e098bc96SEvan Quan 1777e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1778e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1779e098bc96SEvan Quan 1780e098bc96SEvan Quan if (r) 1781e098bc96SEvan Quan return r; 1782e098bc96SEvan Quan 1783e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", value); 1784e098bc96SEvan Quan } 1785e098bc96SEvan Quan 1786e098bc96SEvan Quan /** 1787e098bc96SEvan Quan * DOC: mem_busy_percent 1788e098bc96SEvan Quan * 1789e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1790e098bc96SEvan Quan * is as a percentage. The file mem_busy_percent is used for this. 1791e098bc96SEvan Quan * The SMU firmware computes a percentage of load based on the 1792e098bc96SEvan Quan * aggregate activity level in the IP cores. 1793e098bc96SEvan Quan */ 1794e098bc96SEvan Quan static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1795e098bc96SEvan Quan struct device_attribute *attr, 1796e098bc96SEvan Quan char *buf) 1797e098bc96SEvan Quan { 1798e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 17991348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1800e098bc96SEvan Quan int r, value, size = sizeof(value); 1801e098bc96SEvan Quan 180253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1803e098bc96SEvan Quan return -EPERM; 1804e098bc96SEvan Quan 1805e098bc96SEvan Quan r = pm_runtime_get_sync(ddev->dev); 1806e098bc96SEvan Quan if (r < 0) { 1807e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1808e098bc96SEvan Quan return r; 1809e098bc96SEvan Quan } 1810e098bc96SEvan Quan 1811e098bc96SEvan Quan /* read the IP busy sensor */ 1812e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, 1813e098bc96SEvan Quan (void *)&value, &size); 1814e098bc96SEvan Quan 1815e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1816e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1817e098bc96SEvan Quan 1818e098bc96SEvan Quan if (r) 1819e098bc96SEvan Quan return r; 1820e098bc96SEvan Quan 1821e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", value); 1822e098bc96SEvan Quan } 1823e098bc96SEvan Quan 1824e098bc96SEvan Quan /** 1825e098bc96SEvan Quan * DOC: pcie_bw 1826e098bc96SEvan Quan * 1827e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for estimating how much data 1828e098bc96SEvan Quan * has been received and sent by the GPU in the last second through PCIe. 1829e098bc96SEvan Quan * The file pcie_bw is used for this. 1830e098bc96SEvan Quan * The Perf counters count the number of received and sent messages and return 1831e098bc96SEvan Quan * those values, as well as the maximum payload size of a PCIe packet (mps). 1832e098bc96SEvan Quan * Note that it is not possible to easily and quickly obtain the size of each 1833e098bc96SEvan Quan * packet transmitted, so we output the max payload size (mps) to allow for 1834e098bc96SEvan Quan * quick estimation of the PCIe bandwidth usage 1835e098bc96SEvan Quan */ 1836e098bc96SEvan Quan static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1837e098bc96SEvan Quan struct device_attribute *attr, 1838e098bc96SEvan Quan char *buf) 1839e098bc96SEvan Quan { 1840e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 18411348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1842e098bc96SEvan Quan uint64_t count0 = 0, count1 = 0; 1843e098bc96SEvan Quan int ret; 1844e098bc96SEvan Quan 184553b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1846e098bc96SEvan Quan return -EPERM; 1847e098bc96SEvan Quan 1848e098bc96SEvan Quan if (adev->flags & AMD_IS_APU) 1849e098bc96SEvan Quan return -ENODATA; 1850e098bc96SEvan Quan 1851e098bc96SEvan Quan if (!adev->asic_funcs->get_pcie_usage) 1852e098bc96SEvan Quan return -ENODATA; 1853e098bc96SEvan Quan 1854e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1855e098bc96SEvan Quan if (ret < 0) { 1856e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1857e098bc96SEvan Quan return ret; 1858e098bc96SEvan Quan } 1859e098bc96SEvan Quan 1860e098bc96SEvan Quan amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1861e098bc96SEvan Quan 1862e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1863e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1864e098bc96SEvan Quan 1865e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n", 1866e098bc96SEvan Quan count0, count1, pcie_get_mps(adev->pdev)); 1867e098bc96SEvan Quan } 1868e098bc96SEvan Quan 1869e098bc96SEvan Quan /** 1870e098bc96SEvan Quan * DOC: unique_id 1871e098bc96SEvan Quan * 1872e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1873e098bc96SEvan Quan * The file unique_id is used for this. 1874e098bc96SEvan Quan * This will provide a Unique ID that will persist from machine to machine 1875e098bc96SEvan Quan * 1876e098bc96SEvan Quan * NOTE: This will only work for GFX9 and newer. This file will be absent 1877e098bc96SEvan Quan * on unsupported ASICs (GFX8 and older) 1878e098bc96SEvan Quan */ 1879e098bc96SEvan Quan static ssize_t amdgpu_get_unique_id(struct device *dev, 1880e098bc96SEvan Quan struct device_attribute *attr, 1881e098bc96SEvan Quan char *buf) 1882e098bc96SEvan Quan { 1883e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 18841348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1885e098bc96SEvan Quan 188653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1887e098bc96SEvan Quan return -EPERM; 1888e098bc96SEvan Quan 1889e098bc96SEvan Quan if (adev->unique_id) 1890e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id); 1891e098bc96SEvan Quan 1892e098bc96SEvan Quan return 0; 1893e098bc96SEvan Quan } 1894e098bc96SEvan Quan 1895e098bc96SEvan Quan /** 1896e098bc96SEvan Quan * DOC: thermal_throttling_logging 1897e098bc96SEvan Quan * 1898e098bc96SEvan Quan * Thermal throttling pulls down the clock frequency and thus the performance. 1899e098bc96SEvan Quan * It's an useful mechanism to protect the chip from overheating. Since it 1900e098bc96SEvan Quan * impacts performance, the user controls whether it is enabled and if so, 1901e098bc96SEvan Quan * the log frequency. 1902e098bc96SEvan Quan * 1903e098bc96SEvan Quan * Reading back the file shows you the status(enabled or disabled) and 1904e098bc96SEvan Quan * the interval(in seconds) between each thermal logging. 1905e098bc96SEvan Quan * 1906e098bc96SEvan Quan * Writing an integer to the file, sets a new logging interval, in seconds. 1907e098bc96SEvan Quan * The value should be between 1 and 3600. If the value is less than 1, 1908e098bc96SEvan Quan * thermal logging is disabled. Values greater than 3600 are ignored. 1909e098bc96SEvan Quan */ 1910e098bc96SEvan Quan static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1911e098bc96SEvan Quan struct device_attribute *attr, 1912e098bc96SEvan Quan char *buf) 1913e098bc96SEvan Quan { 1914e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 19151348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1916e098bc96SEvan Quan 1917e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%s: thermal throttling logging %s, with interval %d seconds\n", 19184a580877SLuben Tuikov adev_to_drm(adev)->unique, 1919e098bc96SEvan Quan atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1920e098bc96SEvan Quan adev->throttling_logging_rs.interval / HZ + 1); 1921e098bc96SEvan Quan } 1922e098bc96SEvan Quan 1923e098bc96SEvan Quan static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1924e098bc96SEvan Quan struct device_attribute *attr, 1925e098bc96SEvan Quan const char *buf, 1926e098bc96SEvan Quan size_t count) 1927e098bc96SEvan Quan { 1928e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 19291348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1930e098bc96SEvan Quan long throttling_logging_interval; 1931e098bc96SEvan Quan unsigned long flags; 1932e098bc96SEvan Quan int ret = 0; 1933e098bc96SEvan Quan 1934e098bc96SEvan Quan ret = kstrtol(buf, 0, &throttling_logging_interval); 1935e098bc96SEvan Quan if (ret) 1936e098bc96SEvan Quan return ret; 1937e098bc96SEvan Quan 1938e098bc96SEvan Quan if (throttling_logging_interval > 3600) 1939e098bc96SEvan Quan return -EINVAL; 1940e098bc96SEvan Quan 1941e098bc96SEvan Quan if (throttling_logging_interval > 0) { 1942e098bc96SEvan Quan raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1943e098bc96SEvan Quan /* 1944e098bc96SEvan Quan * Reset the ratelimit timer internals. 1945e098bc96SEvan Quan * This can effectively restart the timer. 1946e098bc96SEvan Quan */ 1947e098bc96SEvan Quan adev->throttling_logging_rs.interval = 1948e098bc96SEvan Quan (throttling_logging_interval - 1) * HZ; 1949e098bc96SEvan Quan adev->throttling_logging_rs.begin = 0; 1950e098bc96SEvan Quan adev->throttling_logging_rs.printed = 0; 1951e098bc96SEvan Quan adev->throttling_logging_rs.missed = 0; 1952e098bc96SEvan Quan raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1953e098bc96SEvan Quan 1954e098bc96SEvan Quan atomic_set(&adev->throttling_logging_enabled, 1); 1955e098bc96SEvan Quan } else { 1956e098bc96SEvan Quan atomic_set(&adev->throttling_logging_enabled, 0); 1957e098bc96SEvan Quan } 1958e098bc96SEvan Quan 1959e098bc96SEvan Quan return count; 1960e098bc96SEvan Quan } 1961e098bc96SEvan Quan 1962e098bc96SEvan Quan /** 1963e098bc96SEvan Quan * DOC: gpu_metrics 1964e098bc96SEvan Quan * 1965e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for retrieving current gpu 1966e098bc96SEvan Quan * metrics data. The file gpu_metrics is used for this. Reading the 1967e098bc96SEvan Quan * file will dump all the current gpu metrics data. 1968e098bc96SEvan Quan * 1969e098bc96SEvan Quan * These data include temperature, frequency, engines utilization, 1970e098bc96SEvan Quan * power consume, throttler status, fan speed and cpu core statistics( 1971e098bc96SEvan Quan * available for APU only). That's it will give a snapshot of all sensors 1972e098bc96SEvan Quan * at the same time. 1973e098bc96SEvan Quan */ 1974e098bc96SEvan Quan static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1975e098bc96SEvan Quan struct device_attribute *attr, 1976e098bc96SEvan Quan char *buf) 1977e098bc96SEvan Quan { 1978e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 19791348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1980e098bc96SEvan Quan void *gpu_metrics; 1981e098bc96SEvan Quan ssize_t size = 0; 1982e098bc96SEvan Quan int ret; 1983e098bc96SEvan Quan 198453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1985e098bc96SEvan Quan return -EPERM; 1986e098bc96SEvan Quan 1987e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1988e098bc96SEvan Quan if (ret < 0) { 1989e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1990e098bc96SEvan Quan return ret; 1991e098bc96SEvan Quan } 1992e098bc96SEvan Quan 1993e098bc96SEvan Quan if (is_support_sw_smu(adev)) 1994e098bc96SEvan Quan size = smu_sys_get_gpu_metrics(&adev->smu, &gpu_metrics); 1995e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_gpu_metrics) 1996e098bc96SEvan Quan size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1997e098bc96SEvan Quan 1998e098bc96SEvan Quan if (size <= 0) 1999e098bc96SEvan Quan goto out; 2000e098bc96SEvan Quan 2001e098bc96SEvan Quan if (size >= PAGE_SIZE) 2002e098bc96SEvan Quan size = PAGE_SIZE - 1; 2003e098bc96SEvan Quan 2004e098bc96SEvan Quan memcpy(buf, gpu_metrics, size); 2005e098bc96SEvan Quan 2006e098bc96SEvan Quan out: 2007e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 2008e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 2009e098bc96SEvan Quan 2010e098bc96SEvan Quan return size; 2011e098bc96SEvan Quan } 2012e098bc96SEvan Quan 2013e098bc96SEvan Quan static struct amdgpu_device_attr amdgpu_device_attrs[] = { 2014e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2015e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC), 2016e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), 2017e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), 2018e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), 2019e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC), 2020e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2021e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2022e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2023e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2024e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC), 2025e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC), 2026e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 2027e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 2028e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC), 2029e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC), 2030e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC), 2031e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC), 2032e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 2033e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC), 2034e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC), 2035e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC), 2036e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC), 2037e098bc96SEvan Quan }; 2038e098bc96SEvan Quan 2039e098bc96SEvan Quan static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2040e098bc96SEvan Quan uint32_t mask, enum amdgpu_device_attr_states *states) 2041e098bc96SEvan Quan { 2042e098bc96SEvan Quan struct device_attribute *dev_attr = &attr->dev_attr; 2043e098bc96SEvan Quan const char *attr_name = dev_attr->attr.name; 2044e098bc96SEvan Quan struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 2045e098bc96SEvan Quan enum amd_asic_type asic_type = adev->asic_type; 2046e098bc96SEvan Quan 2047e098bc96SEvan Quan if (!(attr->flags & mask)) { 2048e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2049e098bc96SEvan Quan return 0; 2050e098bc96SEvan Quan } 2051e098bc96SEvan Quan 2052e098bc96SEvan Quan #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) 2053e098bc96SEvan Quan 2054e098bc96SEvan Quan if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 2055e098bc96SEvan Quan if (asic_type < CHIP_VEGA10) 2056e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2057e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2058e098bc96SEvan Quan if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS) 2059e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2060e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 2061e098bc96SEvan Quan if (asic_type < CHIP_VEGA20) 2062e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2063e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { 2064e098bc96SEvan Quan if (asic_type == CHIP_ARCTURUS) 2065e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2066e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) { 2067e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2068e098bc96SEvan Quan if ((is_support_sw_smu(adev) && adev->smu.od_enabled) || 2069e098bc96SEvan Quan (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 2070e098bc96SEvan Quan *states = ATTR_STATE_SUPPORTED; 2071e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(mem_busy_percent)) { 2072e098bc96SEvan Quan if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10) 2073e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2074e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pcie_bw)) { 2075e098bc96SEvan Quan /* PCIe Perf counters won't work on APU nodes */ 2076e098bc96SEvan Quan if (adev->flags & AMD_IS_APU) 2077e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2078e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(unique_id)) { 2079e098bc96SEvan Quan if (asic_type != CHIP_VEGA10 && 2080e098bc96SEvan Quan asic_type != CHIP_VEGA20 && 2081e098bc96SEvan Quan asic_type != CHIP_ARCTURUS) 2082e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2083e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_features)) { 2084e098bc96SEvan Quan if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10) 2085e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2086e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2087e098bc96SEvan Quan if (asic_type < CHIP_VEGA12) 2088e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 2089e098bc96SEvan Quan } 2090e098bc96SEvan Quan 2091e098bc96SEvan Quan if (asic_type == CHIP_ARCTURUS) { 2092e098bc96SEvan Quan /* Arcturus does not support standalone mclk/socclk/fclk level setting */ 2093e098bc96SEvan Quan if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2094e098bc96SEvan Quan DEVICE_ATTR_IS(pp_dpm_socclk) || 2095e098bc96SEvan Quan DEVICE_ATTR_IS(pp_dpm_fclk)) { 2096e098bc96SEvan Quan dev_attr->attr.mode &= ~S_IWUGO; 2097e098bc96SEvan Quan dev_attr->store = NULL; 2098e098bc96SEvan Quan } 2099e098bc96SEvan Quan } 2100e098bc96SEvan Quan 2101e098bc96SEvan Quan #undef DEVICE_ATTR_IS 2102e098bc96SEvan Quan 2103e098bc96SEvan Quan return 0; 2104e098bc96SEvan Quan } 2105e098bc96SEvan Quan 2106e098bc96SEvan Quan 2107e098bc96SEvan Quan static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2108e098bc96SEvan Quan struct amdgpu_device_attr *attr, 2109e098bc96SEvan Quan uint32_t mask, struct list_head *attr_list) 2110e098bc96SEvan Quan { 2111e098bc96SEvan Quan int ret = 0; 2112e098bc96SEvan Quan struct device_attribute *dev_attr = &attr->dev_attr; 2113e098bc96SEvan Quan const char *name = dev_attr->attr.name; 2114e098bc96SEvan Quan enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2115e098bc96SEvan Quan struct amdgpu_device_attr_entry *attr_entry; 2116e098bc96SEvan Quan 2117e098bc96SEvan Quan int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2118e098bc96SEvan Quan uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2119e098bc96SEvan Quan 2120e098bc96SEvan Quan BUG_ON(!attr); 2121e098bc96SEvan Quan 2122e098bc96SEvan Quan attr_update = attr->attr_update ? attr_update : default_attr_update; 2123e098bc96SEvan Quan 2124e098bc96SEvan Quan ret = attr_update(adev, attr, mask, &attr_states); 2125e098bc96SEvan Quan if (ret) { 2126e098bc96SEvan Quan dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2127e098bc96SEvan Quan name, ret); 2128e098bc96SEvan Quan return ret; 2129e098bc96SEvan Quan } 2130e098bc96SEvan Quan 2131e098bc96SEvan Quan if (attr_states == ATTR_STATE_UNSUPPORTED) 2132e098bc96SEvan Quan return 0; 2133e098bc96SEvan Quan 2134e098bc96SEvan Quan ret = device_create_file(adev->dev, dev_attr); 2135e098bc96SEvan Quan if (ret) { 2136e098bc96SEvan Quan dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2137e098bc96SEvan Quan name, ret); 2138e098bc96SEvan Quan } 2139e098bc96SEvan Quan 2140e098bc96SEvan Quan attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2141e098bc96SEvan Quan if (!attr_entry) 2142e098bc96SEvan Quan return -ENOMEM; 2143e098bc96SEvan Quan 2144e098bc96SEvan Quan attr_entry->attr = attr; 2145e098bc96SEvan Quan INIT_LIST_HEAD(&attr_entry->entry); 2146e098bc96SEvan Quan 2147e098bc96SEvan Quan list_add_tail(&attr_entry->entry, attr_list); 2148e098bc96SEvan Quan 2149e098bc96SEvan Quan return ret; 2150e098bc96SEvan Quan } 2151e098bc96SEvan Quan 2152e098bc96SEvan Quan static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2153e098bc96SEvan Quan { 2154e098bc96SEvan Quan struct device_attribute *dev_attr = &attr->dev_attr; 2155e098bc96SEvan Quan 2156e098bc96SEvan Quan device_remove_file(adev->dev, dev_attr); 2157e098bc96SEvan Quan } 2158e098bc96SEvan Quan 2159e098bc96SEvan Quan static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2160e098bc96SEvan Quan struct list_head *attr_list); 2161e098bc96SEvan Quan 2162e098bc96SEvan Quan static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2163e098bc96SEvan Quan struct amdgpu_device_attr *attrs, 2164e098bc96SEvan Quan uint32_t counts, 2165e098bc96SEvan Quan uint32_t mask, 2166e098bc96SEvan Quan struct list_head *attr_list) 2167e098bc96SEvan Quan { 2168e098bc96SEvan Quan int ret = 0; 2169e098bc96SEvan Quan uint32_t i = 0; 2170e098bc96SEvan Quan 2171e098bc96SEvan Quan for (i = 0; i < counts; i++) { 2172e098bc96SEvan Quan ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2173e098bc96SEvan Quan if (ret) 2174e098bc96SEvan Quan goto failed; 2175e098bc96SEvan Quan } 2176e098bc96SEvan Quan 2177e098bc96SEvan Quan return 0; 2178e098bc96SEvan Quan 2179e098bc96SEvan Quan failed: 2180e098bc96SEvan Quan amdgpu_device_attr_remove_groups(adev, attr_list); 2181e098bc96SEvan Quan 2182e098bc96SEvan Quan return ret; 2183e098bc96SEvan Quan } 2184e098bc96SEvan Quan 2185e098bc96SEvan Quan static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2186e098bc96SEvan Quan struct list_head *attr_list) 2187e098bc96SEvan Quan { 2188e098bc96SEvan Quan struct amdgpu_device_attr_entry *entry, *entry_tmp; 2189e098bc96SEvan Quan 2190e098bc96SEvan Quan if (list_empty(attr_list)) 2191e098bc96SEvan Quan return ; 2192e098bc96SEvan Quan 2193e098bc96SEvan Quan list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2194e098bc96SEvan Quan amdgpu_device_attr_remove(adev, entry->attr); 2195e098bc96SEvan Quan list_del(&entry->entry); 2196e098bc96SEvan Quan kfree(entry); 2197e098bc96SEvan Quan } 2198e098bc96SEvan Quan } 2199e098bc96SEvan Quan 2200e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2201e098bc96SEvan Quan struct device_attribute *attr, 2202e098bc96SEvan Quan char *buf) 2203e098bc96SEvan Quan { 2204e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2205e098bc96SEvan Quan int channel = to_sensor_dev_attr(attr)->index; 2206e098bc96SEvan Quan int r, temp = 0, size = sizeof(temp); 2207e098bc96SEvan Quan 220853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2209e098bc96SEvan Quan return -EPERM; 2210e098bc96SEvan Quan 2211e098bc96SEvan Quan if (channel >= PP_TEMP_MAX) 2212e098bc96SEvan Quan return -EINVAL; 2213e098bc96SEvan Quan 22144a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2215e098bc96SEvan Quan if (r < 0) { 22164a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2217e098bc96SEvan Quan return r; 2218e098bc96SEvan Quan } 2219e098bc96SEvan Quan 2220e098bc96SEvan Quan switch (channel) { 2221e098bc96SEvan Quan case PP_TEMP_JUNCTION: 2222e098bc96SEvan Quan /* get current junction temperature */ 2223e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2224e098bc96SEvan Quan (void *)&temp, &size); 2225e098bc96SEvan Quan break; 2226e098bc96SEvan Quan case PP_TEMP_EDGE: 2227e098bc96SEvan Quan /* get current edge temperature */ 2228e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2229e098bc96SEvan Quan (void *)&temp, &size); 2230e098bc96SEvan Quan break; 2231e098bc96SEvan Quan case PP_TEMP_MEM: 2232e098bc96SEvan Quan /* get current memory temperature */ 2233e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2234e098bc96SEvan Quan (void *)&temp, &size); 2235e098bc96SEvan Quan break; 2236e098bc96SEvan Quan default: 2237e098bc96SEvan Quan r = -EINVAL; 2238e098bc96SEvan Quan break; 2239e098bc96SEvan Quan } 2240e098bc96SEvan Quan 22414a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 22424a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2243e098bc96SEvan Quan 2244e098bc96SEvan Quan if (r) 2245e098bc96SEvan Quan return r; 2246e098bc96SEvan Quan 2247e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", temp); 2248e098bc96SEvan Quan } 2249e098bc96SEvan Quan 2250e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2251e098bc96SEvan Quan struct device_attribute *attr, 2252e098bc96SEvan Quan char *buf) 2253e098bc96SEvan Quan { 2254e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2255e098bc96SEvan Quan int hyst = to_sensor_dev_attr(attr)->index; 2256e098bc96SEvan Quan int temp; 2257e098bc96SEvan Quan 2258e098bc96SEvan Quan if (hyst) 2259e098bc96SEvan Quan temp = adev->pm.dpm.thermal.min_temp; 2260e098bc96SEvan Quan else 2261e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_temp; 2262e098bc96SEvan Quan 2263e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", temp); 2264e098bc96SEvan Quan } 2265e098bc96SEvan Quan 2266e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2267e098bc96SEvan Quan struct device_attribute *attr, 2268e098bc96SEvan Quan char *buf) 2269e098bc96SEvan Quan { 2270e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2271e098bc96SEvan Quan int hyst = to_sensor_dev_attr(attr)->index; 2272e098bc96SEvan Quan int temp; 2273e098bc96SEvan Quan 2274e098bc96SEvan Quan if (hyst) 2275e098bc96SEvan Quan temp = adev->pm.dpm.thermal.min_hotspot_temp; 2276e098bc96SEvan Quan else 2277e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2278e098bc96SEvan Quan 2279e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", temp); 2280e098bc96SEvan Quan } 2281e098bc96SEvan Quan 2282e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2283e098bc96SEvan Quan struct device_attribute *attr, 2284e098bc96SEvan Quan char *buf) 2285e098bc96SEvan Quan { 2286e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2287e098bc96SEvan Quan int hyst = to_sensor_dev_attr(attr)->index; 2288e098bc96SEvan Quan int temp; 2289e098bc96SEvan Quan 2290e098bc96SEvan Quan if (hyst) 2291e098bc96SEvan Quan temp = adev->pm.dpm.thermal.min_mem_temp; 2292e098bc96SEvan Quan else 2293e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2294e098bc96SEvan Quan 2295e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", temp); 2296e098bc96SEvan Quan } 2297e098bc96SEvan Quan 2298e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2299e098bc96SEvan Quan struct device_attribute *attr, 2300e098bc96SEvan Quan char *buf) 2301e098bc96SEvan Quan { 2302e098bc96SEvan Quan int channel = to_sensor_dev_attr(attr)->index; 2303e098bc96SEvan Quan 2304e098bc96SEvan Quan if (channel >= PP_TEMP_MAX) 2305e098bc96SEvan Quan return -EINVAL; 2306e098bc96SEvan Quan 2307e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label); 2308e098bc96SEvan Quan } 2309e098bc96SEvan Quan 2310e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2311e098bc96SEvan Quan struct device_attribute *attr, 2312e098bc96SEvan Quan char *buf) 2313e098bc96SEvan Quan { 2314e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2315e098bc96SEvan Quan int channel = to_sensor_dev_attr(attr)->index; 2316e098bc96SEvan Quan int temp = 0; 2317e098bc96SEvan Quan 2318e098bc96SEvan Quan if (channel >= PP_TEMP_MAX) 2319e098bc96SEvan Quan return -EINVAL; 2320e098bc96SEvan Quan 2321e098bc96SEvan Quan switch (channel) { 2322e098bc96SEvan Quan case PP_TEMP_JUNCTION: 2323e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2324e098bc96SEvan Quan break; 2325e098bc96SEvan Quan case PP_TEMP_EDGE: 2326e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2327e098bc96SEvan Quan break; 2328e098bc96SEvan Quan case PP_TEMP_MEM: 2329e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2330e098bc96SEvan Quan break; 2331e098bc96SEvan Quan } 2332e098bc96SEvan Quan 2333e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", temp); 2334e098bc96SEvan Quan } 2335e098bc96SEvan Quan 2336e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2337e098bc96SEvan Quan struct device_attribute *attr, 2338e098bc96SEvan Quan char *buf) 2339e098bc96SEvan Quan { 2340e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2341e098bc96SEvan Quan u32 pwm_mode = 0; 2342e098bc96SEvan Quan int ret; 2343e098bc96SEvan Quan 234453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2345e098bc96SEvan Quan return -EPERM; 2346e098bc96SEvan Quan 23474a580877SLuben Tuikov ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2348e098bc96SEvan Quan if (ret < 0) { 23494a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2350e098bc96SEvan Quan return ret; 2351e098bc96SEvan Quan } 2352e098bc96SEvan Quan 2353e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 2354e098bc96SEvan Quan pwm_mode = smu_get_fan_control_mode(&adev->smu); 2355e098bc96SEvan Quan } else { 2356e098bc96SEvan Quan if (!adev->powerplay.pp_funcs->get_fan_control_mode) { 23574a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 23584a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2359e098bc96SEvan Quan return -EINVAL; 2360e098bc96SEvan Quan } 2361e098bc96SEvan Quan 2362e098bc96SEvan Quan pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 2363e098bc96SEvan Quan } 2364e098bc96SEvan Quan 23654a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 23664a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2367e098bc96SEvan Quan 2368e098bc96SEvan Quan return sprintf(buf, "%i\n", pwm_mode); 2369e098bc96SEvan Quan } 2370e098bc96SEvan Quan 2371e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2372e098bc96SEvan Quan struct device_attribute *attr, 2373e098bc96SEvan Quan const char *buf, 2374e098bc96SEvan Quan size_t count) 2375e098bc96SEvan Quan { 2376e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2377e098bc96SEvan Quan int err, ret; 2378e098bc96SEvan Quan int value; 2379e098bc96SEvan Quan 238053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2381e098bc96SEvan Quan return -EPERM; 2382e098bc96SEvan Quan 2383e098bc96SEvan Quan err = kstrtoint(buf, 10, &value); 2384e098bc96SEvan Quan if (err) 2385e098bc96SEvan Quan return err; 2386e098bc96SEvan Quan 23874a580877SLuben Tuikov ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2388e098bc96SEvan Quan if (ret < 0) { 23894a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2390e098bc96SEvan Quan return ret; 2391e098bc96SEvan Quan } 2392e098bc96SEvan Quan 2393e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 2394e098bc96SEvan Quan smu_set_fan_control_mode(&adev->smu, value); 2395e098bc96SEvan Quan } else { 2396e098bc96SEvan Quan if (!adev->powerplay.pp_funcs->set_fan_control_mode) { 23974a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 23984a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2399e098bc96SEvan Quan return -EINVAL; 2400e098bc96SEvan Quan } 2401e098bc96SEvan Quan 2402e098bc96SEvan Quan amdgpu_dpm_set_fan_control_mode(adev, value); 2403e098bc96SEvan Quan } 2404e098bc96SEvan Quan 24054a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24064a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2407e098bc96SEvan Quan 2408e098bc96SEvan Quan return count; 2409e098bc96SEvan Quan } 2410e098bc96SEvan Quan 2411e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2412e098bc96SEvan Quan struct device_attribute *attr, 2413e098bc96SEvan Quan char *buf) 2414e098bc96SEvan Quan { 2415e098bc96SEvan Quan return sprintf(buf, "%i\n", 0); 2416e098bc96SEvan Quan } 2417e098bc96SEvan Quan 2418e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2419e098bc96SEvan Quan struct device_attribute *attr, 2420e098bc96SEvan Quan char *buf) 2421e098bc96SEvan Quan { 2422e098bc96SEvan Quan return sprintf(buf, "%i\n", 255); 2423e098bc96SEvan Quan } 2424e098bc96SEvan Quan 2425e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2426e098bc96SEvan Quan struct device_attribute *attr, 2427e098bc96SEvan Quan const char *buf, size_t count) 2428e098bc96SEvan Quan { 2429e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2430e098bc96SEvan Quan int err; 2431e098bc96SEvan Quan u32 value; 2432e098bc96SEvan Quan u32 pwm_mode; 2433e098bc96SEvan Quan 243453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2435e098bc96SEvan Quan return -EPERM; 2436e098bc96SEvan Quan 24374a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2438e098bc96SEvan Quan if (err < 0) { 24394a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2440e098bc96SEvan Quan return err; 2441e098bc96SEvan Quan } 2442e098bc96SEvan Quan 2443e098bc96SEvan Quan if (is_support_sw_smu(adev)) 2444e098bc96SEvan Quan pwm_mode = smu_get_fan_control_mode(&adev->smu); 2445e098bc96SEvan Quan else 2446e098bc96SEvan Quan pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 2447e098bc96SEvan Quan 2448e098bc96SEvan Quan if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2449e098bc96SEvan Quan pr_info("manual fan speed control should be enabled first\n"); 24504a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24514a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2452e098bc96SEvan Quan return -EINVAL; 2453e098bc96SEvan Quan } 2454e098bc96SEvan Quan 2455e098bc96SEvan Quan err = kstrtou32(buf, 10, &value); 2456e098bc96SEvan Quan if (err) { 24574a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24584a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2459e098bc96SEvan Quan return err; 2460e098bc96SEvan Quan } 2461e098bc96SEvan Quan 2462e098bc96SEvan Quan value = (value * 100) / 255; 2463e098bc96SEvan Quan 2464e098bc96SEvan Quan if (is_support_sw_smu(adev)) 2465e098bc96SEvan Quan err = smu_set_fan_speed_percent(&adev->smu, value); 2466e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->set_fan_speed_percent) 2467e098bc96SEvan Quan err = amdgpu_dpm_set_fan_speed_percent(adev, value); 2468e098bc96SEvan Quan else 2469e098bc96SEvan Quan err = -EINVAL; 2470e098bc96SEvan Quan 24714a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24724a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2473e098bc96SEvan Quan 2474e098bc96SEvan Quan if (err) 2475e098bc96SEvan Quan return err; 2476e098bc96SEvan Quan 2477e098bc96SEvan Quan return count; 2478e098bc96SEvan Quan } 2479e098bc96SEvan Quan 2480e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2481e098bc96SEvan Quan struct device_attribute *attr, 2482e098bc96SEvan Quan char *buf) 2483e098bc96SEvan Quan { 2484e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2485e098bc96SEvan Quan int err; 2486e098bc96SEvan Quan u32 speed = 0; 2487e098bc96SEvan Quan 248853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2489e098bc96SEvan Quan return -EPERM; 2490e098bc96SEvan Quan 24914a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2492e098bc96SEvan Quan if (err < 0) { 24934a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2494e098bc96SEvan Quan return err; 2495e098bc96SEvan Quan } 2496e098bc96SEvan Quan 2497e098bc96SEvan Quan if (is_support_sw_smu(adev)) 2498e098bc96SEvan Quan err = smu_get_fan_speed_percent(&adev->smu, &speed); 2499e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_fan_speed_percent) 2500e098bc96SEvan Quan err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); 2501e098bc96SEvan Quan else 2502e098bc96SEvan Quan err = -EINVAL; 2503e098bc96SEvan Quan 25044a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 25054a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2506e098bc96SEvan Quan 2507e098bc96SEvan Quan if (err) 2508e098bc96SEvan Quan return err; 2509e098bc96SEvan Quan 2510e098bc96SEvan Quan speed = (speed * 255) / 100; 2511e098bc96SEvan Quan 2512e098bc96SEvan Quan return sprintf(buf, "%i\n", speed); 2513e098bc96SEvan Quan } 2514e098bc96SEvan Quan 2515e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2516e098bc96SEvan Quan struct device_attribute *attr, 2517e098bc96SEvan Quan char *buf) 2518e098bc96SEvan Quan { 2519e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2520e098bc96SEvan Quan int err; 2521e098bc96SEvan Quan u32 speed = 0; 2522e098bc96SEvan Quan 252353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2524e098bc96SEvan Quan return -EPERM; 2525e098bc96SEvan Quan 25264a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2527e098bc96SEvan Quan if (err < 0) { 25284a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2529e098bc96SEvan Quan return err; 2530e098bc96SEvan Quan } 2531e098bc96SEvan Quan 2532e098bc96SEvan Quan if (is_support_sw_smu(adev)) 2533e098bc96SEvan Quan err = smu_get_fan_speed_rpm(&adev->smu, &speed); 2534e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) 2535e098bc96SEvan Quan err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2536e098bc96SEvan Quan else 2537e098bc96SEvan Quan err = -EINVAL; 2538e098bc96SEvan Quan 25394a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 25404a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2541e098bc96SEvan Quan 2542e098bc96SEvan Quan if (err) 2543e098bc96SEvan Quan return err; 2544e098bc96SEvan Quan 2545e098bc96SEvan Quan return sprintf(buf, "%i\n", speed); 2546e098bc96SEvan Quan } 2547e098bc96SEvan Quan 2548e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2549e098bc96SEvan Quan struct device_attribute *attr, 2550e098bc96SEvan Quan char *buf) 2551e098bc96SEvan Quan { 2552e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2553e098bc96SEvan Quan u32 min_rpm = 0; 2554e098bc96SEvan Quan u32 size = sizeof(min_rpm); 2555e098bc96SEvan Quan int r; 2556e098bc96SEvan Quan 255753b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2558e098bc96SEvan Quan return -EPERM; 2559e098bc96SEvan Quan 25604a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2561e098bc96SEvan Quan if (r < 0) { 25624a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2563e098bc96SEvan Quan return r; 2564e098bc96SEvan Quan } 2565e098bc96SEvan Quan 2566e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2567e098bc96SEvan Quan (void *)&min_rpm, &size); 2568e098bc96SEvan Quan 25694a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 25704a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2571e098bc96SEvan Quan 2572e098bc96SEvan Quan if (r) 2573e098bc96SEvan Quan return r; 2574e098bc96SEvan Quan 2575e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm); 2576e098bc96SEvan Quan } 2577e098bc96SEvan Quan 2578e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2579e098bc96SEvan Quan struct device_attribute *attr, 2580e098bc96SEvan Quan char *buf) 2581e098bc96SEvan Quan { 2582e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2583e098bc96SEvan Quan u32 max_rpm = 0; 2584e098bc96SEvan Quan u32 size = sizeof(max_rpm); 2585e098bc96SEvan Quan int r; 2586e098bc96SEvan Quan 258753b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2588e098bc96SEvan Quan return -EPERM; 2589e098bc96SEvan Quan 25904a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2591e098bc96SEvan Quan if (r < 0) { 25924a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2593e098bc96SEvan Quan return r; 2594e098bc96SEvan Quan } 2595e098bc96SEvan Quan 2596e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2597e098bc96SEvan Quan (void *)&max_rpm, &size); 2598e098bc96SEvan Quan 25994a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 26004a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2601e098bc96SEvan Quan 2602e098bc96SEvan Quan if (r) 2603e098bc96SEvan Quan return r; 2604e098bc96SEvan Quan 2605e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm); 2606e098bc96SEvan Quan } 2607e098bc96SEvan Quan 2608e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2609e098bc96SEvan Quan struct device_attribute *attr, 2610e098bc96SEvan Quan char *buf) 2611e098bc96SEvan Quan { 2612e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2613e098bc96SEvan Quan int err; 2614e098bc96SEvan Quan u32 rpm = 0; 2615e098bc96SEvan Quan 261653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2617e098bc96SEvan Quan return -EPERM; 2618e098bc96SEvan Quan 26194a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2620e098bc96SEvan Quan if (err < 0) { 26214a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2622e098bc96SEvan Quan return err; 2623e098bc96SEvan Quan } 2624e098bc96SEvan Quan 2625e098bc96SEvan Quan if (is_support_sw_smu(adev)) 2626e098bc96SEvan Quan err = smu_get_fan_speed_rpm(&adev->smu, &rpm); 2627e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) 2628e098bc96SEvan Quan err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2629e098bc96SEvan Quan else 2630e098bc96SEvan Quan err = -EINVAL; 2631e098bc96SEvan Quan 26324a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 26334a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2634e098bc96SEvan Quan 2635e098bc96SEvan Quan if (err) 2636e098bc96SEvan Quan return err; 2637e098bc96SEvan Quan 2638e098bc96SEvan Quan return sprintf(buf, "%i\n", rpm); 2639e098bc96SEvan Quan } 2640e098bc96SEvan Quan 2641e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2642e098bc96SEvan Quan struct device_attribute *attr, 2643e098bc96SEvan Quan const char *buf, size_t count) 2644e098bc96SEvan Quan { 2645e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2646e098bc96SEvan Quan int err; 2647e098bc96SEvan Quan u32 value; 2648e098bc96SEvan Quan u32 pwm_mode; 2649e098bc96SEvan Quan 265053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2651e098bc96SEvan Quan return -EPERM; 2652e098bc96SEvan Quan 26534a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2654e098bc96SEvan Quan if (err < 0) { 26554a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2656e098bc96SEvan Quan return err; 2657e098bc96SEvan Quan } 2658e098bc96SEvan Quan 2659e098bc96SEvan Quan if (is_support_sw_smu(adev)) 2660e098bc96SEvan Quan pwm_mode = smu_get_fan_control_mode(&adev->smu); 2661e098bc96SEvan Quan else 2662e098bc96SEvan Quan pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 2663e098bc96SEvan Quan 2664e098bc96SEvan Quan if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 26654a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 26664a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2667e098bc96SEvan Quan return -ENODATA; 2668e098bc96SEvan Quan } 2669e098bc96SEvan Quan 2670e098bc96SEvan Quan err = kstrtou32(buf, 10, &value); 2671e098bc96SEvan Quan if (err) { 26724a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 26734a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2674e098bc96SEvan Quan return err; 2675e098bc96SEvan Quan } 2676e098bc96SEvan Quan 2677e098bc96SEvan Quan if (is_support_sw_smu(adev)) 2678e098bc96SEvan Quan err = smu_set_fan_speed_rpm(&adev->smu, value); 2679e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) 2680e098bc96SEvan Quan err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2681e098bc96SEvan Quan else 2682e098bc96SEvan Quan err = -EINVAL; 2683e098bc96SEvan Quan 26844a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 26854a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2686e098bc96SEvan Quan 2687e098bc96SEvan Quan if (err) 2688e098bc96SEvan Quan return err; 2689e098bc96SEvan Quan 2690e098bc96SEvan Quan return count; 2691e098bc96SEvan Quan } 2692e098bc96SEvan Quan 2693e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2694e098bc96SEvan Quan struct device_attribute *attr, 2695e098bc96SEvan Quan char *buf) 2696e098bc96SEvan Quan { 2697e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2698e098bc96SEvan Quan u32 pwm_mode = 0; 2699e098bc96SEvan Quan int ret; 2700e098bc96SEvan Quan 270153b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2702e098bc96SEvan Quan return -EPERM; 2703e098bc96SEvan Quan 27044a580877SLuben Tuikov ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2705e098bc96SEvan Quan if (ret < 0) { 27064a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2707e098bc96SEvan Quan return ret; 2708e098bc96SEvan Quan } 2709e098bc96SEvan Quan 2710e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 2711e098bc96SEvan Quan pwm_mode = smu_get_fan_control_mode(&adev->smu); 2712e098bc96SEvan Quan } else { 2713e098bc96SEvan Quan if (!adev->powerplay.pp_funcs->get_fan_control_mode) { 27144a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 27154a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2716e098bc96SEvan Quan return -EINVAL; 2717e098bc96SEvan Quan } 2718e098bc96SEvan Quan 2719e098bc96SEvan Quan pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 2720e098bc96SEvan Quan } 2721e098bc96SEvan Quan 27224a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 27234a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2724e098bc96SEvan Quan 2725e098bc96SEvan Quan return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2726e098bc96SEvan Quan } 2727e098bc96SEvan Quan 2728e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2729e098bc96SEvan Quan struct device_attribute *attr, 2730e098bc96SEvan Quan const char *buf, 2731e098bc96SEvan Quan size_t count) 2732e098bc96SEvan Quan { 2733e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2734e098bc96SEvan Quan int err; 2735e098bc96SEvan Quan int value; 2736e098bc96SEvan Quan u32 pwm_mode; 2737e098bc96SEvan Quan 273853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2739e098bc96SEvan Quan return -EPERM; 2740e098bc96SEvan Quan 2741e098bc96SEvan Quan err = kstrtoint(buf, 10, &value); 2742e098bc96SEvan Quan if (err) 2743e098bc96SEvan Quan return err; 2744e098bc96SEvan Quan 2745e098bc96SEvan Quan if (value == 0) 2746e098bc96SEvan Quan pwm_mode = AMD_FAN_CTRL_AUTO; 2747e098bc96SEvan Quan else if (value == 1) 2748e098bc96SEvan Quan pwm_mode = AMD_FAN_CTRL_MANUAL; 2749e098bc96SEvan Quan else 2750e098bc96SEvan Quan return -EINVAL; 2751e098bc96SEvan Quan 27524a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2753e098bc96SEvan Quan if (err < 0) { 27544a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2755e098bc96SEvan Quan return err; 2756e098bc96SEvan Quan } 2757e098bc96SEvan Quan 2758e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 2759e098bc96SEvan Quan smu_set_fan_control_mode(&adev->smu, pwm_mode); 2760e098bc96SEvan Quan } else { 2761e098bc96SEvan Quan if (!adev->powerplay.pp_funcs->set_fan_control_mode) { 27624a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 27634a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2764e098bc96SEvan Quan return -EINVAL; 2765e098bc96SEvan Quan } 2766e098bc96SEvan Quan amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2767e098bc96SEvan Quan } 2768e098bc96SEvan Quan 27694a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 27704a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2771e098bc96SEvan Quan 2772e098bc96SEvan Quan return count; 2773e098bc96SEvan Quan } 2774e098bc96SEvan Quan 2775e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 2776e098bc96SEvan Quan struct device_attribute *attr, 2777e098bc96SEvan Quan char *buf) 2778e098bc96SEvan Quan { 2779e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2780e098bc96SEvan Quan u32 vddgfx; 2781e098bc96SEvan Quan int r, size = sizeof(vddgfx); 2782e098bc96SEvan Quan 278353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2784e098bc96SEvan Quan return -EPERM; 2785e098bc96SEvan Quan 27864a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2787e098bc96SEvan Quan if (r < 0) { 27884a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2789e098bc96SEvan Quan return r; 2790e098bc96SEvan Quan } 2791e098bc96SEvan Quan 2792e098bc96SEvan Quan /* get the voltage */ 2793e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, 2794e098bc96SEvan Quan (void *)&vddgfx, &size); 2795e098bc96SEvan Quan 27964a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 27974a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2798e098bc96SEvan Quan 2799e098bc96SEvan Quan if (r) 2800e098bc96SEvan Quan return r; 2801e098bc96SEvan Quan 2802e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx); 2803e098bc96SEvan Quan } 2804e098bc96SEvan Quan 2805e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 2806e098bc96SEvan Quan struct device_attribute *attr, 2807e098bc96SEvan Quan char *buf) 2808e098bc96SEvan Quan { 2809e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "vddgfx\n"); 2810e098bc96SEvan Quan } 2811e098bc96SEvan Quan 2812e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 2813e098bc96SEvan Quan struct device_attribute *attr, 2814e098bc96SEvan Quan char *buf) 2815e098bc96SEvan Quan { 2816e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2817e098bc96SEvan Quan u32 vddnb; 2818e098bc96SEvan Quan int r, size = sizeof(vddnb); 2819e098bc96SEvan Quan 282053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2821e098bc96SEvan Quan return -EPERM; 2822e098bc96SEvan Quan 2823e098bc96SEvan Quan /* only APUs have vddnb */ 2824e098bc96SEvan Quan if (!(adev->flags & AMD_IS_APU)) 2825e098bc96SEvan Quan return -EINVAL; 2826e098bc96SEvan Quan 28274a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2828e098bc96SEvan Quan if (r < 0) { 28294a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2830e098bc96SEvan Quan return r; 2831e098bc96SEvan Quan } 2832e098bc96SEvan Quan 2833e098bc96SEvan Quan /* get the voltage */ 2834e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, 2835e098bc96SEvan Quan (void *)&vddnb, &size); 2836e098bc96SEvan Quan 28374a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 28384a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2839e098bc96SEvan Quan 2840e098bc96SEvan Quan if (r) 2841e098bc96SEvan Quan return r; 2842e098bc96SEvan Quan 2843e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%d\n", vddnb); 2844e098bc96SEvan Quan } 2845e098bc96SEvan Quan 2846e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 2847e098bc96SEvan Quan struct device_attribute *attr, 2848e098bc96SEvan Quan char *buf) 2849e098bc96SEvan Quan { 2850e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "vddnb\n"); 2851e098bc96SEvan Quan } 2852e098bc96SEvan Quan 2853e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 2854e098bc96SEvan Quan struct device_attribute *attr, 2855e098bc96SEvan Quan char *buf) 2856e098bc96SEvan Quan { 2857e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2858e098bc96SEvan Quan u32 query = 0; 2859e098bc96SEvan Quan int r, size = sizeof(u32); 2860e098bc96SEvan Quan unsigned uw; 2861e098bc96SEvan Quan 286253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2863e098bc96SEvan Quan return -EPERM; 2864e098bc96SEvan Quan 28654a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2866e098bc96SEvan Quan if (r < 0) { 28674a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2868e098bc96SEvan Quan return r; 2869e098bc96SEvan Quan } 2870e098bc96SEvan Quan 2871e098bc96SEvan Quan /* get the voltage */ 2872e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, 2873e098bc96SEvan Quan (void *)&query, &size); 2874e098bc96SEvan Quan 28754a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 28764a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2877e098bc96SEvan Quan 2878e098bc96SEvan Quan if (r) 2879e098bc96SEvan Quan return r; 2880e098bc96SEvan Quan 2881e098bc96SEvan Quan /* convert to microwatts */ 2882e098bc96SEvan Quan uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 2883e098bc96SEvan Quan 2884e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%u\n", uw); 2885e098bc96SEvan Quan } 2886e098bc96SEvan Quan 2887e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 2888e098bc96SEvan Quan struct device_attribute *attr, 2889e098bc96SEvan Quan char *buf) 2890e098bc96SEvan Quan { 2891e098bc96SEvan Quan return sprintf(buf, "%i\n", 0); 2892e098bc96SEvan Quan } 2893e098bc96SEvan Quan 2894e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 2895e098bc96SEvan Quan struct device_attribute *attr, 2896e098bc96SEvan Quan char *buf) 2897e098bc96SEvan Quan { 2898e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2899e098bc96SEvan Quan uint32_t limit = 0; 2900e098bc96SEvan Quan ssize_t size; 2901e098bc96SEvan Quan int r; 2902e098bc96SEvan Quan 290353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2904e098bc96SEvan Quan return -EPERM; 2905e098bc96SEvan Quan 29064a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2907e098bc96SEvan Quan if (r < 0) { 29084a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2909e098bc96SEvan Quan return r; 2910e098bc96SEvan Quan } 2911e098bc96SEvan Quan 2912e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 2913e098bc96SEvan Quan smu_get_power_limit(&adev->smu, &limit, true); 2914e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 2915e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { 2916e098bc96SEvan Quan adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true); 2917e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 2918e098bc96SEvan Quan } else { 2919e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 2920e098bc96SEvan Quan } 2921e098bc96SEvan Quan 29224a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 29234a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2924e098bc96SEvan Quan 2925e098bc96SEvan Quan return size; 2926e098bc96SEvan Quan } 2927e098bc96SEvan Quan 2928e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 2929e098bc96SEvan Quan struct device_attribute *attr, 2930e098bc96SEvan Quan char *buf) 2931e098bc96SEvan Quan { 2932e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2933e098bc96SEvan Quan uint32_t limit = 0; 2934e098bc96SEvan Quan ssize_t size; 2935e098bc96SEvan Quan int r; 2936e098bc96SEvan Quan 293753b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2938e098bc96SEvan Quan return -EPERM; 2939e098bc96SEvan Quan 29404a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2941e098bc96SEvan Quan if (r < 0) { 29424a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2943e098bc96SEvan Quan return r; 2944e098bc96SEvan Quan } 2945e098bc96SEvan Quan 2946e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 2947e098bc96SEvan Quan smu_get_power_limit(&adev->smu, &limit, false); 2948e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 2949e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { 2950e098bc96SEvan Quan adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false); 2951e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 2952e098bc96SEvan Quan } else { 2953e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 2954e098bc96SEvan Quan } 2955e098bc96SEvan Quan 29564a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 29574a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2958e098bc96SEvan Quan 2959e098bc96SEvan Quan return size; 2960e098bc96SEvan Quan } 2961e098bc96SEvan Quan 2962e098bc96SEvan Quan 2963e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 2964e098bc96SEvan Quan struct device_attribute *attr, 2965e098bc96SEvan Quan const char *buf, 2966e098bc96SEvan Quan size_t count) 2967e098bc96SEvan Quan { 2968e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2969e098bc96SEvan Quan int err; 2970e098bc96SEvan Quan u32 value; 2971e098bc96SEvan Quan 297253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2973e098bc96SEvan Quan return -EPERM; 2974e098bc96SEvan Quan 2975e098bc96SEvan Quan if (amdgpu_sriov_vf(adev)) 2976e098bc96SEvan Quan return -EINVAL; 2977e098bc96SEvan Quan 2978e098bc96SEvan Quan err = kstrtou32(buf, 10, &value); 2979e098bc96SEvan Quan if (err) 2980e098bc96SEvan Quan return err; 2981e098bc96SEvan Quan 2982e098bc96SEvan Quan value = value / 1000000; /* convert to Watt */ 2983e098bc96SEvan Quan 2984e098bc96SEvan Quan 29854a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2986e098bc96SEvan Quan if (err < 0) { 29874a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2988e098bc96SEvan Quan return err; 2989e098bc96SEvan Quan } 2990e098bc96SEvan Quan 2991e098bc96SEvan Quan if (is_support_sw_smu(adev)) 2992e098bc96SEvan Quan err = smu_set_power_limit(&adev->smu, value); 2993e098bc96SEvan Quan else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) 2994e098bc96SEvan Quan err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value); 2995e098bc96SEvan Quan else 2996e098bc96SEvan Quan err = -EINVAL; 2997e098bc96SEvan Quan 29984a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 29994a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3000e098bc96SEvan Quan 3001e098bc96SEvan Quan if (err) 3002e098bc96SEvan Quan return err; 3003e098bc96SEvan Quan 3004e098bc96SEvan Quan return count; 3005e098bc96SEvan Quan } 3006e098bc96SEvan Quan 3007e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 3008e098bc96SEvan Quan struct device_attribute *attr, 3009e098bc96SEvan Quan char *buf) 3010e098bc96SEvan Quan { 3011e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 3012e098bc96SEvan Quan uint32_t sclk; 3013e098bc96SEvan Quan int r, size = sizeof(sclk); 3014e098bc96SEvan Quan 301553b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 3016e098bc96SEvan Quan return -EPERM; 3017e098bc96SEvan Quan 30184a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3019e098bc96SEvan Quan if (r < 0) { 30204a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3021e098bc96SEvan Quan return r; 3022e098bc96SEvan Quan } 3023e098bc96SEvan Quan 3024e098bc96SEvan Quan /* get the sclk */ 3025e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 3026e098bc96SEvan Quan (void *)&sclk, &size); 3027e098bc96SEvan Quan 30284a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 30294a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3030e098bc96SEvan Quan 3031e098bc96SEvan Quan if (r) 3032e098bc96SEvan Quan return r; 3033e098bc96SEvan Quan 3034e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%u\n", sclk * 10 * 1000); 3035e098bc96SEvan Quan } 3036e098bc96SEvan Quan 3037e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 3038e098bc96SEvan Quan struct device_attribute *attr, 3039e098bc96SEvan Quan char *buf) 3040e098bc96SEvan Quan { 3041e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "sclk\n"); 3042e098bc96SEvan Quan } 3043e098bc96SEvan Quan 3044e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 3045e098bc96SEvan Quan struct device_attribute *attr, 3046e098bc96SEvan Quan char *buf) 3047e098bc96SEvan Quan { 3048e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 3049e098bc96SEvan Quan uint32_t mclk; 3050e098bc96SEvan Quan int r, size = sizeof(mclk); 3051e098bc96SEvan Quan 305253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 3053e098bc96SEvan Quan return -EPERM; 3054e098bc96SEvan Quan 30554a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3056e098bc96SEvan Quan if (r < 0) { 30574a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3058e098bc96SEvan Quan return r; 3059e098bc96SEvan Quan } 3060e098bc96SEvan Quan 3061e098bc96SEvan Quan /* get the sclk */ 3062e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 3063e098bc96SEvan Quan (void *)&mclk, &size); 3064e098bc96SEvan Quan 30654a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 30664a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3067e098bc96SEvan Quan 3068e098bc96SEvan Quan if (r) 3069e098bc96SEvan Quan return r; 3070e098bc96SEvan Quan 3071e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "%u\n", mclk * 10 * 1000); 3072e098bc96SEvan Quan } 3073e098bc96SEvan Quan 3074e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 3075e098bc96SEvan Quan struct device_attribute *attr, 3076e098bc96SEvan Quan char *buf) 3077e098bc96SEvan Quan { 3078e098bc96SEvan Quan return snprintf(buf, PAGE_SIZE, "mclk\n"); 3079e098bc96SEvan Quan } 3080e098bc96SEvan Quan 3081e098bc96SEvan Quan /** 3082e098bc96SEvan Quan * DOC: hwmon 3083e098bc96SEvan Quan * 3084e098bc96SEvan Quan * The amdgpu driver exposes the following sensor interfaces: 3085e098bc96SEvan Quan * 3086e098bc96SEvan Quan * - GPU temperature (via the on-die sensor) 3087e098bc96SEvan Quan * 3088e098bc96SEvan Quan * - GPU voltage 3089e098bc96SEvan Quan * 3090e098bc96SEvan Quan * - Northbridge voltage (APUs only) 3091e098bc96SEvan Quan * 3092e098bc96SEvan Quan * - GPU power 3093e098bc96SEvan Quan * 3094e098bc96SEvan Quan * - GPU fan 3095e098bc96SEvan Quan * 3096e098bc96SEvan Quan * - GPU gfx/compute engine clock 3097e098bc96SEvan Quan * 3098e098bc96SEvan Quan * - GPU memory clock (dGPU only) 3099e098bc96SEvan Quan * 3100e098bc96SEvan Quan * hwmon interfaces for GPU temperature: 3101e098bc96SEvan Quan * 3102e098bc96SEvan Quan * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3103e098bc96SEvan Quan * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3104e098bc96SEvan Quan * 3105e098bc96SEvan Quan * - temp[1-3]_label: temperature channel label 3106e098bc96SEvan Quan * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3107e098bc96SEvan Quan * 3108e098bc96SEvan Quan * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3109e098bc96SEvan Quan * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3110e098bc96SEvan Quan * 3111e098bc96SEvan Quan * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3112e098bc96SEvan Quan * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3113e098bc96SEvan Quan * 3114e098bc96SEvan Quan * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3115e098bc96SEvan Quan * - these are supported on SOC15 dGPUs only 3116e098bc96SEvan Quan * 3117e098bc96SEvan Quan * hwmon interfaces for GPU voltage: 3118e098bc96SEvan Quan * 3119e098bc96SEvan Quan * - in0_input: the voltage on the GPU in millivolts 3120e098bc96SEvan Quan * 3121e098bc96SEvan Quan * - in1_input: the voltage on the Northbridge in millivolts 3122e098bc96SEvan Quan * 3123e098bc96SEvan Quan * hwmon interfaces for GPU power: 3124e098bc96SEvan Quan * 3125e098bc96SEvan Quan * - power1_average: average power used by the GPU in microWatts 3126e098bc96SEvan Quan * 3127e098bc96SEvan Quan * - power1_cap_min: minimum cap supported in microWatts 3128e098bc96SEvan Quan * 3129e098bc96SEvan Quan * - power1_cap_max: maximum cap supported in microWatts 3130e098bc96SEvan Quan * 3131e098bc96SEvan Quan * - power1_cap: selected power cap in microWatts 3132e098bc96SEvan Quan * 3133e098bc96SEvan Quan * hwmon interfaces for GPU fan: 3134e098bc96SEvan Quan * 3135e098bc96SEvan Quan * - pwm1: pulse width modulation fan level (0-255) 3136e098bc96SEvan Quan * 3137e098bc96SEvan Quan * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3138e098bc96SEvan Quan * 3139e098bc96SEvan Quan * - pwm1_min: pulse width modulation fan control minimum level (0) 3140e098bc96SEvan Quan * 3141e098bc96SEvan Quan * - pwm1_max: pulse width modulation fan control maximum level (255) 3142e098bc96SEvan Quan * 3143e098bc96SEvan Quan * - fan1_min: an minimum value Unit: revolution/min (RPM) 3144e098bc96SEvan Quan * 3145e098bc96SEvan Quan * - fan1_max: an maxmum value Unit: revolution/max (RPM) 3146e098bc96SEvan Quan * 3147e098bc96SEvan Quan * - fan1_input: fan speed in RPM 3148e098bc96SEvan Quan * 3149e098bc96SEvan Quan * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3150e098bc96SEvan Quan * 3151e098bc96SEvan Quan * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3152e098bc96SEvan Quan * 3153e098bc96SEvan Quan * hwmon interfaces for GPU clocks: 3154e098bc96SEvan Quan * 3155e098bc96SEvan Quan * - freq1_input: the gfx/compute clock in hertz 3156e098bc96SEvan Quan * 3157e098bc96SEvan Quan * - freq2_input: the memory clock in hertz 3158e098bc96SEvan Quan * 3159e098bc96SEvan Quan * You can use hwmon tools like sensors to view this information on your system. 3160e098bc96SEvan Quan * 3161e098bc96SEvan Quan */ 3162e098bc96SEvan Quan 3163e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3164e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3165e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3166e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3167e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3168e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3169e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3170e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3171e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3172e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3173e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3174e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3175e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3176e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3177e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3178e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3179e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3180e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3181e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3182e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3183e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3184e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3185e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3186e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3187e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3188e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3189e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3190e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3191e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3192e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3193e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3194e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3195e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3196e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3197e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3198e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3199e098bc96SEvan Quan 3200e098bc96SEvan Quan static struct attribute *hwmon_attributes[] = { 3201e098bc96SEvan Quan &sensor_dev_attr_temp1_input.dev_attr.attr, 3202e098bc96SEvan Quan &sensor_dev_attr_temp1_crit.dev_attr.attr, 3203e098bc96SEvan Quan &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3204e098bc96SEvan Quan &sensor_dev_attr_temp2_input.dev_attr.attr, 3205e098bc96SEvan Quan &sensor_dev_attr_temp2_crit.dev_attr.attr, 3206e098bc96SEvan Quan &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3207e098bc96SEvan Quan &sensor_dev_attr_temp3_input.dev_attr.attr, 3208e098bc96SEvan Quan &sensor_dev_attr_temp3_crit.dev_attr.attr, 3209e098bc96SEvan Quan &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3210e098bc96SEvan Quan &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3211e098bc96SEvan Quan &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3212e098bc96SEvan Quan &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3213e098bc96SEvan Quan &sensor_dev_attr_temp1_label.dev_attr.attr, 3214e098bc96SEvan Quan &sensor_dev_attr_temp2_label.dev_attr.attr, 3215e098bc96SEvan Quan &sensor_dev_attr_temp3_label.dev_attr.attr, 3216e098bc96SEvan Quan &sensor_dev_attr_pwm1.dev_attr.attr, 3217e098bc96SEvan Quan &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3218e098bc96SEvan Quan &sensor_dev_attr_pwm1_min.dev_attr.attr, 3219e098bc96SEvan Quan &sensor_dev_attr_pwm1_max.dev_attr.attr, 3220e098bc96SEvan Quan &sensor_dev_attr_fan1_input.dev_attr.attr, 3221e098bc96SEvan Quan &sensor_dev_attr_fan1_min.dev_attr.attr, 3222e098bc96SEvan Quan &sensor_dev_attr_fan1_max.dev_attr.attr, 3223e098bc96SEvan Quan &sensor_dev_attr_fan1_target.dev_attr.attr, 3224e098bc96SEvan Quan &sensor_dev_attr_fan1_enable.dev_attr.attr, 3225e098bc96SEvan Quan &sensor_dev_attr_in0_input.dev_attr.attr, 3226e098bc96SEvan Quan &sensor_dev_attr_in0_label.dev_attr.attr, 3227e098bc96SEvan Quan &sensor_dev_attr_in1_input.dev_attr.attr, 3228e098bc96SEvan Quan &sensor_dev_attr_in1_label.dev_attr.attr, 3229e098bc96SEvan Quan &sensor_dev_attr_power1_average.dev_attr.attr, 3230e098bc96SEvan Quan &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3231e098bc96SEvan Quan &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3232e098bc96SEvan Quan &sensor_dev_attr_power1_cap.dev_attr.attr, 3233e098bc96SEvan Quan &sensor_dev_attr_freq1_input.dev_attr.attr, 3234e098bc96SEvan Quan &sensor_dev_attr_freq1_label.dev_attr.attr, 3235e098bc96SEvan Quan &sensor_dev_attr_freq2_input.dev_attr.attr, 3236e098bc96SEvan Quan &sensor_dev_attr_freq2_label.dev_attr.attr, 3237e098bc96SEvan Quan NULL 3238e098bc96SEvan Quan }; 3239e098bc96SEvan Quan 3240e098bc96SEvan Quan static umode_t hwmon_attributes_visible(struct kobject *kobj, 3241e098bc96SEvan Quan struct attribute *attr, int index) 3242e098bc96SEvan Quan { 3243e098bc96SEvan Quan struct device *dev = kobj_to_dev(kobj); 3244e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 3245e098bc96SEvan Quan umode_t effective_mode = attr->mode; 3246e098bc96SEvan Quan 3247e098bc96SEvan Quan /* under multi-vf mode, the hwmon attributes are all not supported */ 3248e098bc96SEvan Quan if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 3249e098bc96SEvan Quan return 0; 3250e098bc96SEvan Quan 3251e098bc96SEvan Quan /* there is no fan under pp one vf mode */ 3252e098bc96SEvan Quan if (amdgpu_sriov_is_pp_one_vf(adev) && 3253e098bc96SEvan Quan (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3254e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3255e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3256e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3257e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3258e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3259e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3260e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3261e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3262e098bc96SEvan Quan return 0; 3263e098bc96SEvan Quan 3264e098bc96SEvan Quan /* Skip fan attributes if fan is not present */ 3265e098bc96SEvan Quan if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3266e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3267e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3268e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3269e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3270e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3271e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3272e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3273e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3274e098bc96SEvan Quan return 0; 3275e098bc96SEvan Quan 3276e098bc96SEvan Quan /* Skip fan attributes on APU */ 3277e098bc96SEvan Quan if ((adev->flags & AMD_IS_APU) && 3278e098bc96SEvan Quan (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3279e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3280e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3281e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3282e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3283e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3284e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3285e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3286e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3287e098bc96SEvan Quan return 0; 3288e098bc96SEvan Quan 3289e098bc96SEvan Quan /* Skip crit temp on APU */ 3290e098bc96SEvan Quan if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) && 3291e098bc96SEvan Quan (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3292e098bc96SEvan Quan attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3293e098bc96SEvan Quan return 0; 3294e098bc96SEvan Quan 3295e098bc96SEvan Quan /* Skip limit attributes if DPM is not enabled */ 3296e098bc96SEvan Quan if (!adev->pm.dpm_enabled && 3297e098bc96SEvan Quan (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3298e098bc96SEvan Quan attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3299e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3300e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3301e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3302e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3303e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3304e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3305e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3306e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3307e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3308e098bc96SEvan Quan return 0; 3309e098bc96SEvan Quan 3310e098bc96SEvan Quan if (!is_support_sw_smu(adev)) { 3311e098bc96SEvan Quan /* mask fan attributes if we have no bindings for this asic to expose */ 3312e098bc96SEvan Quan if ((!adev->powerplay.pp_funcs->get_fan_speed_percent && 3313e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3314e098bc96SEvan Quan (!adev->powerplay.pp_funcs->get_fan_control_mode && 3315e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3316e098bc96SEvan Quan effective_mode &= ~S_IRUGO; 3317e098bc96SEvan Quan 3318e098bc96SEvan Quan if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && 3319e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3320e098bc96SEvan Quan (!adev->powerplay.pp_funcs->set_fan_control_mode && 3321e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3322e098bc96SEvan Quan effective_mode &= ~S_IWUSR; 3323e098bc96SEvan Quan } 3324e098bc96SEvan Quan 3325e098bc96SEvan Quan if (((adev->flags & AMD_IS_APU) || 3326d0eb1b5cSAlex Deucher adev->family == AMDGPU_FAMILY_SI) && /* not implemented yet */ 3327367deb67SAlex Deucher (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3328e098bc96SEvan Quan attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr|| 3329e098bc96SEvan Quan attr == &sensor_dev_attr_power1_cap.dev_attr.attr)) 3330e098bc96SEvan Quan return 0; 3331e098bc96SEvan Quan 3332367deb67SAlex Deucher if (((adev->family == AMDGPU_FAMILY_SI) || 3333367deb67SAlex Deucher ((adev->flags & AMD_IS_APU) && 3334367deb67SAlex Deucher (adev->asic_type < CHIP_RENOIR))) && /* not implemented yet */ 3335367deb67SAlex Deucher (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3336367deb67SAlex Deucher return 0; 3337367deb67SAlex Deucher 3338e098bc96SEvan Quan if (!is_support_sw_smu(adev)) { 3339e098bc96SEvan Quan /* hide max/min values if we can't both query and manage the fan */ 3340e098bc96SEvan Quan if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && 3341e098bc96SEvan Quan !adev->powerplay.pp_funcs->get_fan_speed_percent) && 3342e098bc96SEvan Quan (!adev->powerplay.pp_funcs->set_fan_speed_rpm && 3343e098bc96SEvan Quan !adev->powerplay.pp_funcs->get_fan_speed_rpm) && 3344e098bc96SEvan Quan (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3345e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3346e098bc96SEvan Quan return 0; 3347e098bc96SEvan Quan 3348e098bc96SEvan Quan if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm && 3349e098bc96SEvan Quan !adev->powerplay.pp_funcs->get_fan_speed_rpm) && 3350e098bc96SEvan Quan (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3351e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3352e098bc96SEvan Quan return 0; 3353e098bc96SEvan Quan } 3354e098bc96SEvan Quan 3355e098bc96SEvan Quan if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3356e098bc96SEvan Quan adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */ 3357e098bc96SEvan Quan (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3358e098bc96SEvan Quan attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3359e098bc96SEvan Quan return 0; 3360e098bc96SEvan Quan 3361e098bc96SEvan Quan /* only APUs have vddnb */ 3362e098bc96SEvan Quan if (!(adev->flags & AMD_IS_APU) && 3363e098bc96SEvan Quan (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3364e098bc96SEvan Quan attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3365e098bc96SEvan Quan return 0; 3366e098bc96SEvan Quan 3367e098bc96SEvan Quan /* no mclk on APUs */ 3368e098bc96SEvan Quan if ((adev->flags & AMD_IS_APU) && 3369e098bc96SEvan Quan (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3370e098bc96SEvan Quan attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3371e098bc96SEvan Quan return 0; 3372e098bc96SEvan Quan 3373e098bc96SEvan Quan /* only SOC15 dGPUs support hotspot and mem temperatures */ 3374e098bc96SEvan Quan if (((adev->flags & AMD_IS_APU) || 3375e098bc96SEvan Quan adev->asic_type < CHIP_VEGA10) && 3376e098bc96SEvan Quan (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3377e098bc96SEvan Quan attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3378e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_crit.dev_attr.attr || 3379e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3380e098bc96SEvan Quan attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3381e098bc96SEvan Quan attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3382e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr || 3383e098bc96SEvan Quan attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3384e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3385e098bc96SEvan Quan attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3386e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_label.dev_attr.attr)) 3387e098bc96SEvan Quan return 0; 3388e098bc96SEvan Quan 3389e098bc96SEvan Quan return effective_mode; 3390e098bc96SEvan Quan } 3391e098bc96SEvan Quan 3392e098bc96SEvan Quan static const struct attribute_group hwmon_attrgroup = { 3393e098bc96SEvan Quan .attrs = hwmon_attributes, 3394e098bc96SEvan Quan .is_visible = hwmon_attributes_visible, 3395e098bc96SEvan Quan }; 3396e098bc96SEvan Quan 3397e098bc96SEvan Quan static const struct attribute_group *hwmon_groups[] = { 3398e098bc96SEvan Quan &hwmon_attrgroup, 3399e098bc96SEvan Quan NULL 3400e098bc96SEvan Quan }; 3401e098bc96SEvan Quan 3402e098bc96SEvan Quan int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 3403e098bc96SEvan Quan { 3404e098bc96SEvan Quan int ret; 3405e098bc96SEvan Quan uint32_t mask = 0; 3406e098bc96SEvan Quan 3407e098bc96SEvan Quan if (adev->pm.sysfs_initialized) 3408e098bc96SEvan Quan return 0; 3409e098bc96SEvan Quan 3410e098bc96SEvan Quan if (adev->pm.dpm_enabled == 0) 3411e098bc96SEvan Quan return 0; 3412e098bc96SEvan Quan 3413e098bc96SEvan Quan INIT_LIST_HEAD(&adev->pm.pm_attr_list); 3414e098bc96SEvan Quan 3415e098bc96SEvan Quan adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 3416e098bc96SEvan Quan DRIVER_NAME, adev, 3417e098bc96SEvan Quan hwmon_groups); 3418e098bc96SEvan Quan if (IS_ERR(adev->pm.int_hwmon_dev)) { 3419e098bc96SEvan Quan ret = PTR_ERR(adev->pm.int_hwmon_dev); 3420e098bc96SEvan Quan dev_err(adev->dev, 3421e098bc96SEvan Quan "Unable to register hwmon device: %d\n", ret); 3422e098bc96SEvan Quan return ret; 3423e098bc96SEvan Quan } 3424e098bc96SEvan Quan 3425e098bc96SEvan Quan switch (amdgpu_virt_get_sriov_vf_mode(adev)) { 3426e098bc96SEvan Quan case SRIOV_VF_MODE_ONE_VF: 3427e098bc96SEvan Quan mask = ATTR_FLAG_ONEVF; 3428e098bc96SEvan Quan break; 3429e098bc96SEvan Quan case SRIOV_VF_MODE_MULTI_VF: 3430e098bc96SEvan Quan mask = 0; 3431e098bc96SEvan Quan break; 3432e098bc96SEvan Quan case SRIOV_VF_MODE_BARE_METAL: 3433e098bc96SEvan Quan default: 3434e098bc96SEvan Quan mask = ATTR_FLAG_MASK_ALL; 3435e098bc96SEvan Quan break; 3436e098bc96SEvan Quan } 3437e098bc96SEvan Quan 3438e098bc96SEvan Quan ret = amdgpu_device_attr_create_groups(adev, 3439e098bc96SEvan Quan amdgpu_device_attrs, 3440e098bc96SEvan Quan ARRAY_SIZE(amdgpu_device_attrs), 3441e098bc96SEvan Quan mask, 3442e098bc96SEvan Quan &adev->pm.pm_attr_list); 3443e098bc96SEvan Quan if (ret) 3444e098bc96SEvan Quan return ret; 3445e098bc96SEvan Quan 3446e098bc96SEvan Quan adev->pm.sysfs_initialized = true; 3447e098bc96SEvan Quan 3448e098bc96SEvan Quan return 0; 3449e098bc96SEvan Quan } 3450e098bc96SEvan Quan 3451e098bc96SEvan Quan void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 3452e098bc96SEvan Quan { 3453e098bc96SEvan Quan if (adev->pm.dpm_enabled == 0) 3454e098bc96SEvan Quan return; 3455e098bc96SEvan Quan 3456e098bc96SEvan Quan if (adev->pm.int_hwmon_dev) 3457e098bc96SEvan Quan hwmon_device_unregister(adev->pm.int_hwmon_dev); 3458e098bc96SEvan Quan 3459e098bc96SEvan Quan amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 3460e098bc96SEvan Quan } 3461e098bc96SEvan Quan 3462e098bc96SEvan Quan /* 3463e098bc96SEvan Quan * Debugfs info 3464e098bc96SEvan Quan */ 3465e098bc96SEvan Quan #if defined(CONFIG_DEBUG_FS) 3466e098bc96SEvan Quan 3467e098bc96SEvan Quan static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 3468e098bc96SEvan Quan { 3469e098bc96SEvan Quan uint32_t value; 3470e098bc96SEvan Quan uint64_t value64; 3471e098bc96SEvan Quan uint32_t query = 0; 3472e098bc96SEvan Quan int size; 3473e098bc96SEvan Quan 3474e098bc96SEvan Quan /* GPU Clocks */ 3475e098bc96SEvan Quan size = sizeof(value); 3476e098bc96SEvan Quan seq_printf(m, "GFX Clocks and Power:\n"); 3477e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 3478e098bc96SEvan Quan seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 3479e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 3480e098bc96SEvan Quan seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 3481e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 3482e098bc96SEvan Quan seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 3483e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 3484e098bc96SEvan Quan seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 3485e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 3486e098bc96SEvan Quan seq_printf(m, "\t%u mV (VDDGFX)\n", value); 3487e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 3488e098bc96SEvan Quan seq_printf(m, "\t%u mV (VDDNB)\n", value); 3489e098bc96SEvan Quan size = sizeof(uint32_t); 3490e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) 3491e098bc96SEvan Quan seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); 3492e098bc96SEvan Quan size = sizeof(value); 3493e098bc96SEvan Quan seq_printf(m, "\n"); 3494e098bc96SEvan Quan 3495e098bc96SEvan Quan /* GPU Temp */ 3496e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 3497e098bc96SEvan Quan seq_printf(m, "GPU Temperature: %u C\n", value/1000); 3498e098bc96SEvan Quan 3499e098bc96SEvan Quan /* GPU Load */ 3500e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 3501e098bc96SEvan Quan seq_printf(m, "GPU Load: %u %%\n", value); 3502e098bc96SEvan Quan /* MEM Load */ 3503e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 3504e098bc96SEvan Quan seq_printf(m, "MEM Load: %u %%\n", value); 3505e098bc96SEvan Quan 3506e098bc96SEvan Quan seq_printf(m, "\n"); 3507e098bc96SEvan Quan 3508e098bc96SEvan Quan /* SMC feature mask */ 3509e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 3510e098bc96SEvan Quan seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 3511e098bc96SEvan Quan 3512e098bc96SEvan Quan if (adev->asic_type > CHIP_VEGA20) { 3513e098bc96SEvan Quan /* VCN clocks */ 3514e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 3515e098bc96SEvan Quan if (!value) { 3516e098bc96SEvan Quan seq_printf(m, "VCN: Disabled\n"); 3517e098bc96SEvan Quan } else { 3518e098bc96SEvan Quan seq_printf(m, "VCN: Enabled\n"); 3519e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3520e098bc96SEvan Quan seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3521e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3522e098bc96SEvan Quan seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3523e098bc96SEvan Quan } 3524e098bc96SEvan Quan } 3525e098bc96SEvan Quan seq_printf(m, "\n"); 3526e098bc96SEvan Quan } else { 3527e098bc96SEvan Quan /* UVD clocks */ 3528e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 3529e098bc96SEvan Quan if (!value) { 3530e098bc96SEvan Quan seq_printf(m, "UVD: Disabled\n"); 3531e098bc96SEvan Quan } else { 3532e098bc96SEvan Quan seq_printf(m, "UVD: Enabled\n"); 3533e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3534e098bc96SEvan Quan seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3535e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3536e098bc96SEvan Quan seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3537e098bc96SEvan Quan } 3538e098bc96SEvan Quan } 3539e098bc96SEvan Quan seq_printf(m, "\n"); 3540e098bc96SEvan Quan 3541e098bc96SEvan Quan /* VCE clocks */ 3542e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 3543e098bc96SEvan Quan if (!value) { 3544e098bc96SEvan Quan seq_printf(m, "VCE: Disabled\n"); 3545e098bc96SEvan Quan } else { 3546e098bc96SEvan Quan seq_printf(m, "VCE: Enabled\n"); 3547e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 3548e098bc96SEvan Quan seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 3549e098bc96SEvan Quan } 3550e098bc96SEvan Quan } 3551e098bc96SEvan Quan } 3552e098bc96SEvan Quan 3553e098bc96SEvan Quan return 0; 3554e098bc96SEvan Quan } 3555e098bc96SEvan Quan 3556e098bc96SEvan Quan static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags) 3557e098bc96SEvan Quan { 3558e098bc96SEvan Quan int i; 3559e098bc96SEvan Quan 3560e098bc96SEvan Quan for (i = 0; clocks[i].flag; i++) 3561e098bc96SEvan Quan seq_printf(m, "\t%s: %s\n", clocks[i].name, 3562e098bc96SEvan Quan (flags & clocks[i].flag) ? "On" : "Off"); 3563e098bc96SEvan Quan } 3564e098bc96SEvan Quan 3565e098bc96SEvan Quan static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) 3566e098bc96SEvan Quan { 3567e098bc96SEvan Quan struct drm_info_node *node = (struct drm_info_node *) m->private; 3568e098bc96SEvan Quan struct drm_device *dev = node->minor->dev; 35691348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 3570e098bc96SEvan Quan u32 flags = 0; 3571e098bc96SEvan Quan int r; 3572e098bc96SEvan Quan 357353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 3574e098bc96SEvan Quan return -EPERM; 3575e098bc96SEvan Quan 3576e098bc96SEvan Quan r = pm_runtime_get_sync(dev->dev); 3577e098bc96SEvan Quan if (r < 0) { 3578e098bc96SEvan Quan pm_runtime_put_autosuspend(dev->dev); 3579e098bc96SEvan Quan return r; 3580e098bc96SEvan Quan } 3581e098bc96SEvan Quan 3582e098bc96SEvan Quan if (!adev->pm.dpm_enabled) { 3583e098bc96SEvan Quan seq_printf(m, "dpm not enabled\n"); 3584e098bc96SEvan Quan pm_runtime_mark_last_busy(dev->dev); 3585e098bc96SEvan Quan pm_runtime_put_autosuspend(dev->dev); 3586e098bc96SEvan Quan return 0; 3587e098bc96SEvan Quan } 3588e098bc96SEvan Quan 3589e098bc96SEvan Quan if (!is_support_sw_smu(adev) && 3590e098bc96SEvan Quan adev->powerplay.pp_funcs->debugfs_print_current_performance_level) { 3591e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 3592e098bc96SEvan Quan if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) 3593e098bc96SEvan Quan adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m); 3594e098bc96SEvan Quan else 3595e098bc96SEvan Quan seq_printf(m, "Debugfs support not implemented for this asic\n"); 3596e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 3597e098bc96SEvan Quan r = 0; 3598e098bc96SEvan Quan } else { 3599e098bc96SEvan Quan r = amdgpu_debugfs_pm_info_pp(m, adev); 3600e098bc96SEvan Quan } 3601e098bc96SEvan Quan if (r) 3602e098bc96SEvan Quan goto out; 3603e098bc96SEvan Quan 3604e098bc96SEvan Quan amdgpu_device_ip_get_clockgating_state(adev, &flags); 3605e098bc96SEvan Quan 3606e098bc96SEvan Quan seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); 3607e098bc96SEvan Quan amdgpu_parse_cg_state(m, flags); 3608e098bc96SEvan Quan seq_printf(m, "\n"); 3609e098bc96SEvan Quan 3610e098bc96SEvan Quan out: 3611e098bc96SEvan Quan pm_runtime_mark_last_busy(dev->dev); 3612e098bc96SEvan Quan pm_runtime_put_autosuspend(dev->dev); 3613e098bc96SEvan Quan 3614e098bc96SEvan Quan return r; 3615e098bc96SEvan Quan } 3616e098bc96SEvan Quan 3617e098bc96SEvan Quan static const struct drm_info_list amdgpu_pm_info_list[] = { 3618e098bc96SEvan Quan {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL}, 3619e098bc96SEvan Quan }; 3620e098bc96SEvan Quan #endif 3621e098bc96SEvan Quan 3622e098bc96SEvan Quan int amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 3623e098bc96SEvan Quan { 3624e098bc96SEvan Quan #if defined(CONFIG_DEBUG_FS) 3625e098bc96SEvan Quan return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list)); 3626e098bc96SEvan Quan #else 3627e098bc96SEvan Quan return 0; 3628e098bc96SEvan Quan #endif 3629e098bc96SEvan Quan } 3630