1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2017 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan * Authors: Rafał Miłecki <zajec5@gmail.com> 23e098bc96SEvan Quan * Alex Deucher <alexdeucher@gmail.com> 24e098bc96SEvan Quan */ 25e098bc96SEvan Quan 26e098bc96SEvan Quan #include "amdgpu.h" 27e098bc96SEvan Quan #include "amdgpu_drv.h" 28e098bc96SEvan Quan #include "amdgpu_pm.h" 29e098bc96SEvan Quan #include "amdgpu_dpm.h" 30e098bc96SEvan Quan #include "atom.h" 31e098bc96SEvan Quan #include <linux/pci.h> 32e098bc96SEvan Quan #include <linux/hwmon.h> 33e098bc96SEvan Quan #include <linux/hwmon-sysfs.h> 34e098bc96SEvan Quan #include <linux/nospec.h> 35e098bc96SEvan Quan #include <linux/pm_runtime.h> 36517cb957SHuang Rui #include <asm/processor.h> 37e098bc96SEvan Quan #include "hwmgr.h" 38e098bc96SEvan Quan 39e098bc96SEvan Quan static const struct cg_flag_name clocks[] = { 40adf16996SJinzhou.Su {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 41e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 42e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 43e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 44e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 45e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 46e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 47e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 48e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 49e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 50e098bc96SEvan Quan {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 51e098bc96SEvan Quan {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 52e098bc96SEvan Quan {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 53e098bc96SEvan Quan {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 54e098bc96SEvan Quan {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 55e098bc96SEvan Quan {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 56e098bc96SEvan Quan {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 57e098bc96SEvan Quan {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 58e098bc96SEvan Quan {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 59e098bc96SEvan Quan {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 60e098bc96SEvan Quan {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 61e098bc96SEvan Quan {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 62e098bc96SEvan Quan {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 63e098bc96SEvan Quan {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 64e098bc96SEvan Quan {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 6571037bfcSKevin Wang {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 6671037bfcSKevin Wang {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 6771037bfcSKevin Wang {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 6871037bfcSKevin Wang {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 6971037bfcSKevin Wang {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 70e098bc96SEvan Quan 71e098bc96SEvan Quan {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 72e098bc96SEvan Quan {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 73e098bc96SEvan Quan {0, NULL}, 74e098bc96SEvan Quan }; 75e098bc96SEvan Quan 76e098bc96SEvan Quan static const struct hwmon_temp_label { 77e098bc96SEvan Quan enum PP_HWMON_TEMP channel; 78e098bc96SEvan Quan const char *label; 79e098bc96SEvan Quan } temp_label[] = { 80e098bc96SEvan Quan {PP_TEMP_EDGE, "edge"}, 81e098bc96SEvan Quan {PP_TEMP_JUNCTION, "junction"}, 82e098bc96SEvan Quan {PP_TEMP_MEM, "mem"}, 83e098bc96SEvan Quan }; 84e098bc96SEvan Quan 85e098bc96SEvan Quan /** 86e098bc96SEvan Quan * DOC: power_dpm_state 87e098bc96SEvan Quan * 88e098bc96SEvan Quan * The power_dpm_state file is a legacy interface and is only provided for 89e098bc96SEvan Quan * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 90e098bc96SEvan Quan * certain power related parameters. The file power_dpm_state is used for this. 91e098bc96SEvan Quan * It accepts the following arguments: 92e098bc96SEvan Quan * 93e098bc96SEvan Quan * - battery 94e098bc96SEvan Quan * 95e098bc96SEvan Quan * - balanced 96e098bc96SEvan Quan * 97e098bc96SEvan Quan * - performance 98e098bc96SEvan Quan * 99e098bc96SEvan Quan * battery 100e098bc96SEvan Quan * 101e098bc96SEvan Quan * On older GPUs, the vbios provided a special power state for battery 102e098bc96SEvan Quan * operation. Selecting battery switched to this state. This is no 103e098bc96SEvan Quan * longer provided on newer GPUs so the option does nothing in that case. 104e098bc96SEvan Quan * 105e098bc96SEvan Quan * balanced 106e098bc96SEvan Quan * 107e098bc96SEvan Quan * On older GPUs, the vbios provided a special power state for balanced 108e098bc96SEvan Quan * operation. Selecting balanced switched to this state. This is no 109e098bc96SEvan Quan * longer provided on newer GPUs so the option does nothing in that case. 110e098bc96SEvan Quan * 111e098bc96SEvan Quan * performance 112e098bc96SEvan Quan * 113e098bc96SEvan Quan * On older GPUs, the vbios provided a special power state for performance 114e098bc96SEvan Quan * operation. Selecting performance switched to this state. This is no 115e098bc96SEvan Quan * longer provided on newer GPUs so the option does nothing in that case. 116e098bc96SEvan Quan * 117e098bc96SEvan Quan */ 118e098bc96SEvan Quan 119e098bc96SEvan Quan static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 120e098bc96SEvan Quan struct device_attribute *attr, 121e098bc96SEvan Quan char *buf) 122e098bc96SEvan Quan { 123e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 1241348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1258dfc8c53SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 126e098bc96SEvan Quan enum amd_pm_state_type pm; 127e098bc96SEvan Quan int ret; 128e098bc96SEvan Quan 12953b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 130e098bc96SEvan Quan return -EPERM; 131d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 132d2ae842dSAlex Deucher return -EPERM; 133e098bc96SEvan Quan 134e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 135e098bc96SEvan Quan if (ret < 0) { 136e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 137e098bc96SEvan Quan return ret; 138e098bc96SEvan Quan } 139e098bc96SEvan Quan 1408dfc8c53SDarren Powell if (pp_funcs->get_current_power_state) { 141e098bc96SEvan Quan pm = amdgpu_dpm_get_current_power_state(adev); 142e098bc96SEvan Quan } else { 143e098bc96SEvan Quan pm = adev->pm.dpm.user_state; 144e098bc96SEvan Quan } 145e098bc96SEvan Quan 146e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 147e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 148e098bc96SEvan Quan 149a9ca9bb3STian Tao return sysfs_emit(buf, "%s\n", 150e098bc96SEvan Quan (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 151e098bc96SEvan Quan (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 152e098bc96SEvan Quan } 153e098bc96SEvan Quan 154e098bc96SEvan Quan static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 155e098bc96SEvan Quan struct device_attribute *attr, 156e098bc96SEvan Quan const char *buf, 157e098bc96SEvan Quan size_t count) 158e098bc96SEvan Quan { 159e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 1601348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 161e098bc96SEvan Quan enum amd_pm_state_type state; 162e098bc96SEvan Quan int ret; 163e098bc96SEvan Quan 16453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 165e098bc96SEvan Quan return -EPERM; 166d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 167d2ae842dSAlex Deucher return -EPERM; 168e098bc96SEvan Quan 169e098bc96SEvan Quan if (strncmp("battery", buf, strlen("battery")) == 0) 170e098bc96SEvan Quan state = POWER_STATE_TYPE_BATTERY; 171e098bc96SEvan Quan else if (strncmp("balanced", buf, strlen("balanced")) == 0) 172e098bc96SEvan Quan state = POWER_STATE_TYPE_BALANCED; 173e098bc96SEvan Quan else if (strncmp("performance", buf, strlen("performance")) == 0) 174e098bc96SEvan Quan state = POWER_STATE_TYPE_PERFORMANCE; 175e098bc96SEvan Quan else 176e098bc96SEvan Quan return -EINVAL; 177e098bc96SEvan Quan 178e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 179e098bc96SEvan Quan if (ret < 0) { 180e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 181e098bc96SEvan Quan return ret; 182e098bc96SEvan Quan } 183e098bc96SEvan Quan 184e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 185e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 186e098bc96SEvan Quan adev->pm.dpm.user_state = state; 187e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 188e098bc96SEvan Quan } else if (adev->powerplay.pp_funcs->dispatch_tasks) { 189e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state); 190e098bc96SEvan Quan } else { 191e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 192e098bc96SEvan Quan adev->pm.dpm.user_state = state; 193e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 194e098bc96SEvan Quan 195e098bc96SEvan Quan amdgpu_pm_compute_clocks(adev); 196e098bc96SEvan Quan } 197e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 198e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 199e098bc96SEvan Quan 200e098bc96SEvan Quan return count; 201e098bc96SEvan Quan } 202e098bc96SEvan Quan 203e098bc96SEvan Quan 204e098bc96SEvan Quan /** 205e098bc96SEvan Quan * DOC: power_dpm_force_performance_level 206e098bc96SEvan Quan * 207e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting certain power 208e098bc96SEvan Quan * related parameters. The file power_dpm_force_performance_level is 209e098bc96SEvan Quan * used for this. It accepts the following arguments: 210e098bc96SEvan Quan * 211e098bc96SEvan Quan * - auto 212e098bc96SEvan Quan * 213e098bc96SEvan Quan * - low 214e098bc96SEvan Quan * 215e098bc96SEvan Quan * - high 216e098bc96SEvan Quan * 217e098bc96SEvan Quan * - manual 218e098bc96SEvan Quan * 219e098bc96SEvan Quan * - profile_standard 220e098bc96SEvan Quan * 221e098bc96SEvan Quan * - profile_min_sclk 222e098bc96SEvan Quan * 223e098bc96SEvan Quan * - profile_min_mclk 224e098bc96SEvan Quan * 225e098bc96SEvan Quan * - profile_peak 226e098bc96SEvan Quan * 227e098bc96SEvan Quan * auto 228e098bc96SEvan Quan * 229e098bc96SEvan Quan * When auto is selected, the driver will attempt to dynamically select 230e098bc96SEvan Quan * the optimal power profile for current conditions in the driver. 231e098bc96SEvan Quan * 232e098bc96SEvan Quan * low 233e098bc96SEvan Quan * 234e098bc96SEvan Quan * When low is selected, the clocks are forced to the lowest power state. 235e098bc96SEvan Quan * 236e098bc96SEvan Quan * high 237e098bc96SEvan Quan * 238e098bc96SEvan Quan * When high is selected, the clocks are forced to the highest power state. 239e098bc96SEvan Quan * 240e098bc96SEvan Quan * manual 241e098bc96SEvan Quan * 242e098bc96SEvan Quan * When manual is selected, the user can manually adjust which power states 243e098bc96SEvan Quan * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 244e098bc96SEvan Quan * and pp_dpm_pcie files and adjust the power state transition heuristics 245e098bc96SEvan Quan * via the pp_power_profile_mode sysfs file. 246e098bc96SEvan Quan * 247e098bc96SEvan Quan * profile_standard 248e098bc96SEvan Quan * profile_min_sclk 249e098bc96SEvan Quan * profile_min_mclk 250e098bc96SEvan Quan * profile_peak 251e098bc96SEvan Quan * 252e098bc96SEvan Quan * When the profiling modes are selected, clock and power gating are 253e098bc96SEvan Quan * disabled and the clocks are set for different profiling cases. This 254e098bc96SEvan Quan * mode is recommended for profiling specific work loads where you do 255e098bc96SEvan Quan * not want clock or power gating for clock fluctuation to interfere 256e098bc96SEvan Quan * with your results. profile_standard sets the clocks to a fixed clock 257e098bc96SEvan Quan * level which varies from asic to asic. profile_min_sclk forces the sclk 258e098bc96SEvan Quan * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 259e098bc96SEvan Quan * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 260e098bc96SEvan Quan * 261e098bc96SEvan Quan */ 262e098bc96SEvan Quan 263e098bc96SEvan Quan static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 264e098bc96SEvan Quan struct device_attribute *attr, 265e098bc96SEvan Quan char *buf) 266e098bc96SEvan Quan { 267e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 2681348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 269e098bc96SEvan Quan enum amd_dpm_forced_level level = 0xff; 270e098bc96SEvan Quan int ret; 271e098bc96SEvan Quan 27253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 273e098bc96SEvan Quan return -EPERM; 274d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 275d2ae842dSAlex Deucher return -EPERM; 276e098bc96SEvan Quan 277e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 278e098bc96SEvan Quan if (ret < 0) { 279e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 280e098bc96SEvan Quan return ret; 281e098bc96SEvan Quan } 282e098bc96SEvan Quan 2834df144f8SDarren Powell if (adev->powerplay.pp_funcs->get_performance_level) 284e098bc96SEvan Quan level = amdgpu_dpm_get_performance_level(adev); 285e098bc96SEvan Quan else 286e098bc96SEvan Quan level = adev->pm.dpm.forced_level; 287e098bc96SEvan Quan 288e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 289e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 290e098bc96SEvan Quan 291a9ca9bb3STian Tao return sysfs_emit(buf, "%s\n", 292e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 293e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 294e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 295e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 296e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 297e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 298e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 299e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 3006be64246SLijo Lazar (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 301e098bc96SEvan Quan "unknown"); 302e098bc96SEvan Quan } 303e098bc96SEvan Quan 304e098bc96SEvan Quan static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 305e098bc96SEvan Quan struct device_attribute *attr, 306e098bc96SEvan Quan const char *buf, 307e098bc96SEvan Quan size_t count) 308e098bc96SEvan Quan { 309e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 3101348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 3118dfc8c53SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 312e098bc96SEvan Quan enum amd_dpm_forced_level level; 313e098bc96SEvan Quan enum amd_dpm_forced_level current_level = 0xff; 314e098bc96SEvan Quan int ret = 0; 315e098bc96SEvan Quan 31653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 317e098bc96SEvan Quan return -EPERM; 318d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 319d2ae842dSAlex Deucher return -EPERM; 320e098bc96SEvan Quan 321e098bc96SEvan Quan if (strncmp("low", buf, strlen("low")) == 0) { 322e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_LOW; 323e098bc96SEvan Quan } else if (strncmp("high", buf, strlen("high")) == 0) { 324e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_HIGH; 325e098bc96SEvan Quan } else if (strncmp("auto", buf, strlen("auto")) == 0) { 326e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_AUTO; 327e098bc96SEvan Quan } else if (strncmp("manual", buf, strlen("manual")) == 0) { 328e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_MANUAL; 329e098bc96SEvan Quan } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 330e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 331e098bc96SEvan Quan } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 332e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 333e098bc96SEvan Quan } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 334e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 335e098bc96SEvan Quan } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 336e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 337e098bc96SEvan Quan } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 338e098bc96SEvan Quan level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 3396be64246SLijo Lazar } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 3406be64246SLijo Lazar level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 341e098bc96SEvan Quan } else { 342e098bc96SEvan Quan return -EINVAL; 343e098bc96SEvan Quan } 344e098bc96SEvan Quan 345e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 346e098bc96SEvan Quan if (ret < 0) { 347e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 348e098bc96SEvan Quan return ret; 349e098bc96SEvan Quan } 350e098bc96SEvan Quan 3518dfc8c53SDarren Powell if (pp_funcs->get_performance_level) 352e098bc96SEvan Quan current_level = amdgpu_dpm_get_performance_level(adev); 353e098bc96SEvan Quan 354e098bc96SEvan Quan if (current_level == level) { 355e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 356e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 357e098bc96SEvan Quan return count; 358e098bc96SEvan Quan } 359e098bc96SEvan Quan 360e098bc96SEvan Quan if (adev->asic_type == CHIP_RAVEN) { 361e098bc96SEvan Quan if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { 362e098bc96SEvan Quan if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL) 363e098bc96SEvan Quan amdgpu_gfx_off_ctrl(adev, false); 364e098bc96SEvan Quan else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL) 365e098bc96SEvan Quan amdgpu_gfx_off_ctrl(adev, true); 366e098bc96SEvan Quan } 367e098bc96SEvan Quan } 368e098bc96SEvan Quan 369e098bc96SEvan Quan /* profile_exit setting is valid only when current mode is in profile mode */ 370e098bc96SEvan Quan if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 371e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 372e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 373e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) && 374e098bc96SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) { 375e098bc96SEvan Quan pr_err("Currently not in any profile mode!\n"); 376e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 377e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 378e098bc96SEvan Quan return -EINVAL; 379e098bc96SEvan Quan } 380e098bc96SEvan Quan 3818f4828d0SDarren Powell if (pp_funcs->force_performance_level) { 382e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 383e098bc96SEvan Quan if (adev->pm.dpm.thermal_active) { 384e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 385e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 386e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 387e098bc96SEvan Quan return -EINVAL; 388e098bc96SEvan Quan } 389e098bc96SEvan Quan ret = amdgpu_dpm_force_performance_level(adev, level); 390e098bc96SEvan Quan if (ret) { 391e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 392e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 393e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 394e098bc96SEvan Quan return -EINVAL; 395e098bc96SEvan Quan } else { 396e098bc96SEvan Quan adev->pm.dpm.forced_level = level; 397e098bc96SEvan Quan } 398e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 399e098bc96SEvan Quan } 400e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 401e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 402e098bc96SEvan Quan 403e098bc96SEvan Quan return count; 404e098bc96SEvan Quan } 405e098bc96SEvan Quan 406e098bc96SEvan Quan static ssize_t amdgpu_get_pp_num_states(struct device *dev, 407e098bc96SEvan Quan struct device_attribute *attr, 408e098bc96SEvan Quan char *buf) 409e098bc96SEvan Quan { 410e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 4111348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 4128dfc8c53SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 413e098bc96SEvan Quan struct pp_states_info data; 414e098bc96SEvan Quan int i, buf_len, ret; 415e098bc96SEvan Quan 41653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 417e098bc96SEvan Quan return -EPERM; 418d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 419d2ae842dSAlex Deucher return -EPERM; 420e098bc96SEvan Quan 421e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 422e098bc96SEvan Quan if (ret < 0) { 423e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 424e098bc96SEvan Quan return ret; 425e098bc96SEvan Quan } 426e098bc96SEvan Quan 4278dfc8c53SDarren Powell if (pp_funcs->get_pp_num_states) { 428e098bc96SEvan Quan amdgpu_dpm_get_pp_num_states(adev, &data); 429e098bc96SEvan Quan } else { 430e098bc96SEvan Quan memset(&data, 0, sizeof(data)); 431e098bc96SEvan Quan } 432e098bc96SEvan Quan 433e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 434e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 435e098bc96SEvan Quan 436e098bc96SEvan Quan buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums); 437e098bc96SEvan Quan for (i = 0; i < data.nums; i++) 438e098bc96SEvan Quan buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i, 439e098bc96SEvan Quan (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 440e098bc96SEvan Quan (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 441e098bc96SEvan Quan (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 442e098bc96SEvan Quan (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 443e098bc96SEvan Quan 444e098bc96SEvan Quan return buf_len; 445e098bc96SEvan Quan } 446e098bc96SEvan Quan 447e098bc96SEvan Quan static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 448e098bc96SEvan Quan struct device_attribute *attr, 449e098bc96SEvan Quan char *buf) 450e098bc96SEvan Quan { 451e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 4521348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 4538dfc8c53SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 454e098bc96SEvan Quan struct pp_states_info data; 455e098bc96SEvan Quan enum amd_pm_state_type pm = 0; 456e098bc96SEvan Quan int i = 0, ret = 0; 457e098bc96SEvan Quan 45853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 459e098bc96SEvan Quan return -EPERM; 460d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 461d2ae842dSAlex Deucher return -EPERM; 462e098bc96SEvan Quan 463e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 464e098bc96SEvan Quan if (ret < 0) { 465e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 466e098bc96SEvan Quan return ret; 467e098bc96SEvan Quan } 468e098bc96SEvan Quan 4698dfc8c53SDarren Powell if (pp_funcs->get_current_power_state 4708dfc8c53SDarren Powell && pp_funcs->get_pp_num_states) { 471e098bc96SEvan Quan pm = amdgpu_dpm_get_current_power_state(adev); 472e098bc96SEvan Quan amdgpu_dpm_get_pp_num_states(adev, &data); 473e098bc96SEvan Quan } 474e098bc96SEvan Quan 475e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 476e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 477e098bc96SEvan Quan 478e098bc96SEvan Quan for (i = 0; i < data.nums; i++) { 479e098bc96SEvan Quan if (pm == data.states[i]) 480e098bc96SEvan Quan break; 481e098bc96SEvan Quan } 482e098bc96SEvan Quan 483e098bc96SEvan Quan if (i == data.nums) 484e098bc96SEvan Quan i = -EINVAL; 485e098bc96SEvan Quan 486a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", i); 487e098bc96SEvan Quan } 488e098bc96SEvan Quan 489e098bc96SEvan Quan static ssize_t amdgpu_get_pp_force_state(struct device *dev, 490e098bc96SEvan Quan struct device_attribute *attr, 491e098bc96SEvan Quan char *buf) 492e098bc96SEvan Quan { 493e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 4941348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 495e098bc96SEvan Quan 49653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 497e098bc96SEvan Quan return -EPERM; 498d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 499d2ae842dSAlex Deucher return -EPERM; 500e098bc96SEvan Quan 501e098bc96SEvan Quan if (adev->pp_force_state_enabled) 502e098bc96SEvan Quan return amdgpu_get_pp_cur_state(dev, attr, buf); 503e098bc96SEvan Quan else 504a9ca9bb3STian Tao return sysfs_emit(buf, "\n"); 505e098bc96SEvan Quan } 506e098bc96SEvan Quan 507e098bc96SEvan Quan static ssize_t amdgpu_set_pp_force_state(struct device *dev, 508e098bc96SEvan Quan struct device_attribute *attr, 509e098bc96SEvan Quan const char *buf, 510e098bc96SEvan Quan size_t count) 511e098bc96SEvan Quan { 512e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 5131348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 514e098bc96SEvan Quan enum amd_pm_state_type state = 0; 515e098bc96SEvan Quan unsigned long idx; 516e098bc96SEvan Quan int ret; 517e098bc96SEvan Quan 51853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 519e098bc96SEvan Quan return -EPERM; 520d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 521d2ae842dSAlex Deucher return -EPERM; 522e098bc96SEvan Quan 523e098bc96SEvan Quan if (strlen(buf) == 1) 524e098bc96SEvan Quan adev->pp_force_state_enabled = false; 525e098bc96SEvan Quan else if (is_support_sw_smu(adev)) 526e098bc96SEvan Quan adev->pp_force_state_enabled = false; 527e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->dispatch_tasks && 528e098bc96SEvan Quan adev->powerplay.pp_funcs->get_pp_num_states) { 529e098bc96SEvan Quan struct pp_states_info data; 530e098bc96SEvan Quan 531e098bc96SEvan Quan ret = kstrtoul(buf, 0, &idx); 532e098bc96SEvan Quan if (ret || idx >= ARRAY_SIZE(data.states)) 533e098bc96SEvan Quan return -EINVAL; 534e098bc96SEvan Quan 535e098bc96SEvan Quan idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 536e098bc96SEvan Quan 537e098bc96SEvan Quan amdgpu_dpm_get_pp_num_states(adev, &data); 538e098bc96SEvan Quan state = data.states[idx]; 539e098bc96SEvan Quan 540e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 541e098bc96SEvan Quan if (ret < 0) { 542e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 543e098bc96SEvan Quan return ret; 544e098bc96SEvan Quan } 545e098bc96SEvan Quan 546e098bc96SEvan Quan /* only set user selected power states */ 547e098bc96SEvan Quan if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 548e098bc96SEvan Quan state != POWER_STATE_TYPE_DEFAULT) { 549e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, 550e098bc96SEvan Quan AMD_PP_TASK_ENABLE_USER_STATE, &state); 551e098bc96SEvan Quan adev->pp_force_state_enabled = true; 552e098bc96SEvan Quan } 553e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 554e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 555e098bc96SEvan Quan } 556e098bc96SEvan Quan 557e098bc96SEvan Quan return count; 558e098bc96SEvan Quan } 559e098bc96SEvan Quan 560e098bc96SEvan Quan /** 561e098bc96SEvan Quan * DOC: pp_table 562e098bc96SEvan Quan * 563e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for uploading new powerplay 564e098bc96SEvan Quan * tables. The file pp_table is used for this. Reading the file 565e098bc96SEvan Quan * will dump the current power play table. Writing to the file 566e098bc96SEvan Quan * will attempt to upload a new powerplay table and re-initialize 567e098bc96SEvan Quan * powerplay using that new table. 568e098bc96SEvan Quan * 569e098bc96SEvan Quan */ 570e098bc96SEvan Quan 571e098bc96SEvan Quan static ssize_t amdgpu_get_pp_table(struct device *dev, 572e098bc96SEvan Quan struct device_attribute *attr, 573e098bc96SEvan Quan char *buf) 574e098bc96SEvan Quan { 575e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 5761348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 577e098bc96SEvan Quan char *table = NULL; 578e098bc96SEvan Quan int size, ret; 579e098bc96SEvan Quan 58053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 581e098bc96SEvan Quan return -EPERM; 582d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 583d2ae842dSAlex Deucher return -EPERM; 584e098bc96SEvan Quan 585e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 586e098bc96SEvan Quan if (ret < 0) { 587e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 588e098bc96SEvan Quan return ret; 589e098bc96SEvan Quan } 590e098bc96SEvan Quan 5918dfc8c53SDarren Powell if (adev->powerplay.pp_funcs->get_pp_table) { 592e098bc96SEvan Quan size = amdgpu_dpm_get_pp_table(adev, &table); 593e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 594e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 595e098bc96SEvan Quan if (size < 0) 596e098bc96SEvan Quan return size; 597e098bc96SEvan Quan } else { 598e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 599e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 600e098bc96SEvan Quan return 0; 601e098bc96SEvan Quan } 602e098bc96SEvan Quan 603e098bc96SEvan Quan if (size >= PAGE_SIZE) 604e098bc96SEvan Quan size = PAGE_SIZE - 1; 605e098bc96SEvan Quan 606e098bc96SEvan Quan memcpy(buf, table, size); 607e098bc96SEvan Quan 608e098bc96SEvan Quan return size; 609e098bc96SEvan Quan } 610e098bc96SEvan Quan 611e098bc96SEvan Quan static ssize_t amdgpu_set_pp_table(struct device *dev, 612e098bc96SEvan Quan struct device_attribute *attr, 613e098bc96SEvan Quan const char *buf, 614e098bc96SEvan Quan size_t count) 615e098bc96SEvan Quan { 616e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 6171348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 618e098bc96SEvan Quan int ret = 0; 619e098bc96SEvan Quan 62053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 621e098bc96SEvan Quan return -EPERM; 622d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 623d2ae842dSAlex Deucher return -EPERM; 624e098bc96SEvan Quan 625e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 626e098bc96SEvan Quan if (ret < 0) { 627e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 628e098bc96SEvan Quan return ret; 629e098bc96SEvan Quan } 630e098bc96SEvan Quan 6318f4828d0SDarren Powell ret = amdgpu_dpm_set_pp_table(adev, buf, count); 632e098bc96SEvan Quan if (ret) { 633e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 634e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 635e098bc96SEvan Quan return ret; 636e098bc96SEvan Quan } 637e098bc96SEvan Quan 638e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 639e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 640e098bc96SEvan Quan 641e098bc96SEvan Quan return count; 642e098bc96SEvan Quan } 643e098bc96SEvan Quan 644e098bc96SEvan Quan /** 645e098bc96SEvan Quan * DOC: pp_od_clk_voltage 646e098bc96SEvan Quan * 647e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 648e098bc96SEvan Quan * in each power level within a power state. The pp_od_clk_voltage is used for 649e098bc96SEvan Quan * this. 650e098bc96SEvan Quan * 651e098bc96SEvan Quan * Note that the actual memory controller clock rate are exposed, not 652e098bc96SEvan Quan * the effective memory clock of the DRAMs. To translate it, use the 653e098bc96SEvan Quan * following formula: 654e098bc96SEvan Quan * 655e098bc96SEvan Quan * Clock conversion (Mhz): 656e098bc96SEvan Quan * 657e098bc96SEvan Quan * HBM: effective_memory_clock = memory_controller_clock * 1 658e098bc96SEvan Quan * 659e098bc96SEvan Quan * G5: effective_memory_clock = memory_controller_clock * 1 660e098bc96SEvan Quan * 661e098bc96SEvan Quan * G6: effective_memory_clock = memory_controller_clock * 2 662e098bc96SEvan Quan * 663e098bc96SEvan Quan * DRAM data rate (MT/s): 664e098bc96SEvan Quan * 665e098bc96SEvan Quan * HBM: effective_memory_clock * 2 = data_rate 666e098bc96SEvan Quan * 667e098bc96SEvan Quan * G5: effective_memory_clock * 4 = data_rate 668e098bc96SEvan Quan * 669e098bc96SEvan Quan * G6: effective_memory_clock * 8 = data_rate 670e098bc96SEvan Quan * 671e098bc96SEvan Quan * Bandwidth (MB/s): 672e098bc96SEvan Quan * 673e098bc96SEvan Quan * data_rate * vram_bit_width / 8 = memory_bandwidth 674e098bc96SEvan Quan * 675e098bc96SEvan Quan * Some examples: 676e098bc96SEvan Quan * 677e098bc96SEvan Quan * G5 on RX460: 678e098bc96SEvan Quan * 679e098bc96SEvan Quan * memory_controller_clock = 1750 Mhz 680e098bc96SEvan Quan * 681e098bc96SEvan Quan * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 682e098bc96SEvan Quan * 683e098bc96SEvan Quan * data rate = 1750 * 4 = 7000 MT/s 684e098bc96SEvan Quan * 685e098bc96SEvan Quan * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 686e098bc96SEvan Quan * 687e098bc96SEvan Quan * G6 on RX5700: 688e098bc96SEvan Quan * 689e098bc96SEvan Quan * memory_controller_clock = 875 Mhz 690e098bc96SEvan Quan * 691e098bc96SEvan Quan * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 692e098bc96SEvan Quan * 693e098bc96SEvan Quan * data rate = 1750 * 8 = 14000 MT/s 694e098bc96SEvan Quan * 695e098bc96SEvan Quan * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 696e098bc96SEvan Quan * 697e098bc96SEvan Quan * < For Vega10 and previous ASICs > 698e098bc96SEvan Quan * 699e098bc96SEvan Quan * Reading the file will display: 700e098bc96SEvan Quan * 701e098bc96SEvan Quan * - a list of engine clock levels and voltages labeled OD_SCLK 702e098bc96SEvan Quan * 703e098bc96SEvan Quan * - a list of memory clock levels and voltages labeled OD_MCLK 704e098bc96SEvan Quan * 705e098bc96SEvan Quan * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 706e098bc96SEvan Quan * 707e098bc96SEvan Quan * To manually adjust these settings, first select manual using 708e098bc96SEvan Quan * power_dpm_force_performance_level. Enter a new value for each 709e098bc96SEvan Quan * level by writing a string that contains "s/m level clock voltage" to 710e098bc96SEvan Quan * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 711e098bc96SEvan Quan * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 712e098bc96SEvan Quan * 810 mV. When you have edited all of the states as needed, write 713e098bc96SEvan Quan * "c" (commit) to the file to commit your changes. If you want to reset to the 714e098bc96SEvan Quan * default power levels, write "r" (reset) to the file to reset them. 715e098bc96SEvan Quan * 716e098bc96SEvan Quan * 717e098bc96SEvan Quan * < For Vega20 and newer ASICs > 718e098bc96SEvan Quan * 719e098bc96SEvan Quan * Reading the file will display: 720e098bc96SEvan Quan * 721e098bc96SEvan Quan * - minimum and maximum engine clock labeled OD_SCLK 722e098bc96SEvan Quan * 72337a58f69SEvan Quan * - minimum(not available for Vega20 and Navi1x) and maximum memory 72437a58f69SEvan Quan * clock labeled OD_MCLK 725e098bc96SEvan Quan * 726e098bc96SEvan Quan * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 727e098bc96SEvan Quan * They can be used to calibrate the sclk voltage curve. 728e098bc96SEvan Quan * 729a2b6df4fSEvan Quan * - voltage offset(in mV) applied on target voltage calculation. 730a2b6df4fSEvan Quan * This is available for Sienna Cichlid, Navy Flounder and Dimgrey 731a2b6df4fSEvan Quan * Cavefish. For these ASICs, the target voltage calculation can be 732a2b6df4fSEvan Quan * illustrated by "voltage = voltage calculated from v/f curve + 733a2b6df4fSEvan Quan * overdrive vddgfx offset" 734a2b6df4fSEvan Quan * 735e098bc96SEvan Quan * - a list of valid ranges for sclk, mclk, and voltage curve points 736e098bc96SEvan Quan * labeled OD_RANGE 737e098bc96SEvan Quan * 738e098bc96SEvan Quan * To manually adjust these settings: 739e098bc96SEvan Quan * 740e098bc96SEvan Quan * - First select manual using power_dpm_force_performance_level 741e098bc96SEvan Quan * 742e098bc96SEvan Quan * - For clock frequency setting, enter a new value by writing a 743e098bc96SEvan Quan * string that contains "s/m index clock" to the file. The index 744e098bc96SEvan Quan * should be 0 if to set minimum clock. And 1 if to set maximum 745e098bc96SEvan Quan * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 746e098bc96SEvan Quan * "m 1 800" will update maximum mclk to be 800Mhz. 747e098bc96SEvan Quan * 748e098bc96SEvan Quan * For sclk voltage curve, enter the new values by writing a 749e098bc96SEvan Quan * string that contains "vc point clock voltage" to the file. The 750e098bc96SEvan Quan * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will 751e098bc96SEvan Quan * update point1 with clock set as 300Mhz and voltage as 752e098bc96SEvan Quan * 600mV. "vc 2 1000 1000" will update point3 with clock set 753e098bc96SEvan Quan * as 1000Mhz and voltage 1000mV. 754e098bc96SEvan Quan * 755a2b6df4fSEvan Quan * To update the voltage offset applied for gfxclk/voltage calculation, 756a2b6df4fSEvan Quan * enter the new value by writing a string that contains "vo offset". 757a2b6df4fSEvan Quan * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. 758a2b6df4fSEvan Quan * And the offset can be a positive or negative value. 759a2b6df4fSEvan Quan * 760e098bc96SEvan Quan * - When you have edited all of the states as needed, write "c" (commit) 761e098bc96SEvan Quan * to the file to commit your changes 762e098bc96SEvan Quan * 763e098bc96SEvan Quan * - If you want to reset to the default power levels, write "r" (reset) 764e098bc96SEvan Quan * to the file to reset them 765e098bc96SEvan Quan * 766e098bc96SEvan Quan */ 767e098bc96SEvan Quan 768e098bc96SEvan Quan static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 769e098bc96SEvan Quan struct device_attribute *attr, 770e098bc96SEvan Quan const char *buf, 771e098bc96SEvan Quan size_t count) 772e098bc96SEvan Quan { 773e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 7741348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 775e098bc96SEvan Quan int ret; 776e098bc96SEvan Quan uint32_t parameter_size = 0; 777e098bc96SEvan Quan long parameter[64]; 778e098bc96SEvan Quan char buf_cpy[128]; 779e098bc96SEvan Quan char *tmp_str; 780e098bc96SEvan Quan char *sub_str; 781e098bc96SEvan Quan const char delimiter[3] = {' ', '\n', '\0'}; 782e098bc96SEvan Quan uint32_t type; 783e098bc96SEvan Quan 78453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 785e098bc96SEvan Quan return -EPERM; 786d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 787d2ae842dSAlex Deucher return -EPERM; 788e098bc96SEvan Quan 789e098bc96SEvan Quan if (count > 127) 790e098bc96SEvan Quan return -EINVAL; 791e098bc96SEvan Quan 792e098bc96SEvan Quan if (*buf == 's') 793e098bc96SEvan Quan type = PP_OD_EDIT_SCLK_VDDC_TABLE; 7940d90d0ddSHuang Rui else if (*buf == 'p') 7950d90d0ddSHuang Rui type = PP_OD_EDIT_CCLK_VDDC_TABLE; 796e098bc96SEvan Quan else if (*buf == 'm') 797e098bc96SEvan Quan type = PP_OD_EDIT_MCLK_VDDC_TABLE; 798e098bc96SEvan Quan else if(*buf == 'r') 799e098bc96SEvan Quan type = PP_OD_RESTORE_DEFAULT_TABLE; 800e098bc96SEvan Quan else if (*buf == 'c') 801e098bc96SEvan Quan type = PP_OD_COMMIT_DPM_TABLE; 802e098bc96SEvan Quan else if (!strncmp(buf, "vc", 2)) 803e098bc96SEvan Quan type = PP_OD_EDIT_VDDC_CURVE; 804a2b6df4fSEvan Quan else if (!strncmp(buf, "vo", 2)) 805a2b6df4fSEvan Quan type = PP_OD_EDIT_VDDGFX_OFFSET; 806e098bc96SEvan Quan else 807e098bc96SEvan Quan return -EINVAL; 808e098bc96SEvan Quan 809e098bc96SEvan Quan memcpy(buf_cpy, buf, count+1); 810e098bc96SEvan Quan 811e098bc96SEvan Quan tmp_str = buf_cpy; 812e098bc96SEvan Quan 813a2b6df4fSEvan Quan if ((type == PP_OD_EDIT_VDDC_CURVE) || 814a2b6df4fSEvan Quan (type == PP_OD_EDIT_VDDGFX_OFFSET)) 815e098bc96SEvan Quan tmp_str++; 816e098bc96SEvan Quan while (isspace(*++tmp_str)); 817e098bc96SEvan Quan 818ce7c1d04SEvan Quan while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 819aec1d870SMatt Coffin if (strlen(sub_str) == 0) 820aec1d870SMatt Coffin continue; 821e098bc96SEvan Quan ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 822e098bc96SEvan Quan if (ret) 823e098bc96SEvan Quan return -EINVAL; 824e098bc96SEvan Quan parameter_size++; 825e098bc96SEvan Quan 826e098bc96SEvan Quan while (isspace(*tmp_str)) 827e098bc96SEvan Quan tmp_str++; 828e098bc96SEvan Quan } 829e098bc96SEvan Quan 830e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 831e098bc96SEvan Quan if (ret < 0) { 832e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 833e098bc96SEvan Quan return ret; 834e098bc96SEvan Quan } 835e098bc96SEvan Quan 83612a6727dSXiaojian Du if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) { 83712a6727dSXiaojian Du ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type, 83812a6727dSXiaojian Du parameter, 83912a6727dSXiaojian Du parameter_size); 84012a6727dSXiaojian Du if (ret) { 84112a6727dSXiaojian Du pm_runtime_mark_last_busy(ddev->dev); 84212a6727dSXiaojian Du pm_runtime_put_autosuspend(ddev->dev); 84312a6727dSXiaojian Du return -EINVAL; 84412a6727dSXiaojian Du } 84512a6727dSXiaojian Du } 84612a6727dSXiaojian Du 847e098bc96SEvan Quan if (adev->powerplay.pp_funcs->odn_edit_dpm_table) { 848e098bc96SEvan Quan ret = amdgpu_dpm_odn_edit_dpm_table(adev, type, 849e098bc96SEvan Quan parameter, parameter_size); 850e098bc96SEvan Quan if (ret) { 851e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 852e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 853e098bc96SEvan Quan return -EINVAL; 854e098bc96SEvan Quan } 855e098bc96SEvan Quan } 856e098bc96SEvan Quan 857e098bc96SEvan Quan if (type == PP_OD_COMMIT_DPM_TABLE) { 858e098bc96SEvan Quan if (adev->powerplay.pp_funcs->dispatch_tasks) { 859e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, 860e098bc96SEvan Quan AMD_PP_TASK_READJUST_POWER_STATE, 861e098bc96SEvan Quan NULL); 862e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 863e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 864e098bc96SEvan Quan return count; 865e098bc96SEvan Quan } else { 866e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 867e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 868e098bc96SEvan Quan return -EINVAL; 869e098bc96SEvan Quan } 870e098bc96SEvan Quan } 8718f4828d0SDarren Powell 872e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 873e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 874e098bc96SEvan Quan 875e098bc96SEvan Quan return count; 876e098bc96SEvan Quan } 877e098bc96SEvan Quan 878e098bc96SEvan Quan static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 879e098bc96SEvan Quan struct device_attribute *attr, 880e098bc96SEvan Quan char *buf) 881e098bc96SEvan Quan { 882e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 8831348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 884e098bc96SEvan Quan ssize_t size; 885e098bc96SEvan Quan int ret; 886e098bc96SEvan Quan 88753b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 888e098bc96SEvan Quan return -EPERM; 889d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 890d2ae842dSAlex Deucher return -EPERM; 891e098bc96SEvan Quan 892e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 893e098bc96SEvan Quan if (ret < 0) { 894e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 895e098bc96SEvan Quan return ret; 896e098bc96SEvan Quan } 897e098bc96SEvan Quan 8988f4828d0SDarren Powell if (adev->powerplay.pp_funcs->print_clock_levels) { 899e098bc96SEvan Quan size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 900e098bc96SEvan Quan size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size); 901e098bc96SEvan Quan size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size); 9028f4828d0SDarren Powell size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf+size); 903e098bc96SEvan Quan size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size); 9048f4828d0SDarren Powell size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size); 905e098bc96SEvan Quan } else { 906e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 907e098bc96SEvan Quan } 908e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 909e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 910e098bc96SEvan Quan 911e098bc96SEvan Quan return size; 912e098bc96SEvan Quan } 913e098bc96SEvan Quan 914e098bc96SEvan Quan /** 915e098bc96SEvan Quan * DOC: pp_features 916e098bc96SEvan Quan * 917e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting what powerplay 918e098bc96SEvan Quan * features to be enabled. The file pp_features is used for this. And 919e098bc96SEvan Quan * this is only available for Vega10 and later dGPUs. 920e098bc96SEvan Quan * 921e098bc96SEvan Quan * Reading back the file will show you the followings: 922e098bc96SEvan Quan * - Current ppfeature masks 923e098bc96SEvan Quan * - List of the all supported powerplay features with their naming, 924e098bc96SEvan Quan * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 925e098bc96SEvan Quan * 926e098bc96SEvan Quan * To manually enable or disable a specific feature, just set or clear 927e098bc96SEvan Quan * the corresponding bit from original ppfeature masks and input the 928e098bc96SEvan Quan * new ppfeature masks. 929e098bc96SEvan Quan */ 930e098bc96SEvan Quan static ssize_t amdgpu_set_pp_features(struct device *dev, 931e098bc96SEvan Quan struct device_attribute *attr, 932e098bc96SEvan Quan const char *buf, 933e098bc96SEvan Quan size_t count) 934e098bc96SEvan Quan { 935e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 9361348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 937e098bc96SEvan Quan uint64_t featuremask; 938e098bc96SEvan Quan int ret; 939e098bc96SEvan Quan 94053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 941e098bc96SEvan Quan return -EPERM; 942d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 943d2ae842dSAlex Deucher return -EPERM; 944e098bc96SEvan Quan 945e098bc96SEvan Quan ret = kstrtou64(buf, 0, &featuremask); 946e098bc96SEvan Quan if (ret) 947e098bc96SEvan Quan return -EINVAL; 948e098bc96SEvan Quan 949e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 950e098bc96SEvan Quan if (ret < 0) { 951e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 952e098bc96SEvan Quan return ret; 953e098bc96SEvan Quan } 954e098bc96SEvan Quan 955c6ce68e6SEvan Quan if (adev->powerplay.pp_funcs->set_ppfeature_status) { 956e098bc96SEvan Quan ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 957e098bc96SEvan Quan if (ret) { 958e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 959e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 960e098bc96SEvan Quan return -EINVAL; 961e098bc96SEvan Quan } 962e098bc96SEvan Quan } 963e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 964e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 965e098bc96SEvan Quan 966e098bc96SEvan Quan return count; 967e098bc96SEvan Quan } 968e098bc96SEvan Quan 969e098bc96SEvan Quan static ssize_t amdgpu_get_pp_features(struct device *dev, 970e098bc96SEvan Quan struct device_attribute *attr, 971e098bc96SEvan Quan char *buf) 972e098bc96SEvan Quan { 973e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 9741348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 975e098bc96SEvan Quan ssize_t size; 976e098bc96SEvan Quan int ret; 977e098bc96SEvan Quan 97853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 979e098bc96SEvan Quan return -EPERM; 980d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 981d2ae842dSAlex Deucher return -EPERM; 982e098bc96SEvan Quan 983e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 984e098bc96SEvan Quan if (ret < 0) { 985e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 986e098bc96SEvan Quan return ret; 987e098bc96SEvan Quan } 988e098bc96SEvan Quan 9898dfc8c53SDarren Powell if (adev->powerplay.pp_funcs->get_ppfeature_status) 990e098bc96SEvan Quan size = amdgpu_dpm_get_ppfeature_status(adev, buf); 991e098bc96SEvan Quan else 992e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 993e098bc96SEvan Quan 994e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 995e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 996e098bc96SEvan Quan 997e098bc96SEvan Quan return size; 998e098bc96SEvan Quan } 999e098bc96SEvan Quan 1000e098bc96SEvan Quan /** 1001e098bc96SEvan Quan * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 1002e098bc96SEvan Quan * 1003e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting what power levels 1004e098bc96SEvan Quan * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 1005e098bc96SEvan Quan * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 1006e098bc96SEvan Quan * this. 1007e098bc96SEvan Quan * 1008e098bc96SEvan Quan * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 1009e098bc96SEvan Quan * Vega10 and later ASICs. 1010e098bc96SEvan Quan * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 1011e098bc96SEvan Quan * 1012e098bc96SEvan Quan * Reading back the files will show you the available power levels within 1013e098bc96SEvan Quan * the power state and the clock information for those levels. 1014e098bc96SEvan Quan * 1015e098bc96SEvan Quan * To manually adjust these states, first select manual using 1016e098bc96SEvan Quan * power_dpm_force_performance_level. 1017e098bc96SEvan Quan * Secondly, enter a new value for each level by inputing a string that 1018e098bc96SEvan Quan * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 1019e098bc96SEvan Quan * E.g., 1020e098bc96SEvan Quan * 1021e098bc96SEvan Quan * .. code-block:: bash 1022e098bc96SEvan Quan * 1023e098bc96SEvan Quan * echo "4 5 6" > pp_dpm_sclk 1024e098bc96SEvan Quan * 1025e098bc96SEvan Quan * will enable sclk levels 4, 5, and 6. 1026e098bc96SEvan Quan * 1027e098bc96SEvan Quan * NOTE: change to the dcefclk max dpm level is not supported now 1028e098bc96SEvan Quan */ 1029e098bc96SEvan Quan 10302ea092e5SDarren Powell static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 10312ea092e5SDarren Powell enum pp_clock_type type, 1032e098bc96SEvan Quan char *buf) 1033e098bc96SEvan Quan { 1034e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 10351348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1036e098bc96SEvan Quan ssize_t size; 1037e098bc96SEvan Quan int ret; 1038e098bc96SEvan Quan 103953b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1040e098bc96SEvan Quan return -EPERM; 1041d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1042d2ae842dSAlex Deucher return -EPERM; 1043e098bc96SEvan Quan 1044e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1045e098bc96SEvan Quan if (ret < 0) { 1046e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1047e098bc96SEvan Quan return ret; 1048e098bc96SEvan Quan } 1049e098bc96SEvan Quan 10502ea092e5SDarren Powell if (adev->powerplay.pp_funcs->print_clock_levels) 10512ea092e5SDarren Powell size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1052e098bc96SEvan Quan else 1053e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1054e098bc96SEvan Quan 1055e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1056e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1057e098bc96SEvan Quan 1058e098bc96SEvan Quan return size; 1059e098bc96SEvan Quan } 1060e098bc96SEvan Quan 1061e098bc96SEvan Quan /* 1062e098bc96SEvan Quan * Worst case: 32 bits individually specified, in octal at 12 characters 1063e098bc96SEvan Quan * per line (+1 for \n). 1064e098bc96SEvan Quan */ 1065e098bc96SEvan Quan #define AMDGPU_MASK_BUF_MAX (32 * 13) 1066e098bc96SEvan Quan 1067e098bc96SEvan Quan static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1068e098bc96SEvan Quan { 1069e098bc96SEvan Quan int ret; 1070c915ef89SDan Carpenter unsigned long level; 1071e098bc96SEvan Quan char *sub_str = NULL; 1072e098bc96SEvan Quan char *tmp; 1073e098bc96SEvan Quan char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1074e098bc96SEvan Quan const char delimiter[3] = {' ', '\n', '\0'}; 1075e098bc96SEvan Quan size_t bytes; 1076e098bc96SEvan Quan 1077e098bc96SEvan Quan *mask = 0; 1078e098bc96SEvan Quan 1079e098bc96SEvan Quan bytes = min(count, sizeof(buf_cpy) - 1); 1080e098bc96SEvan Quan memcpy(buf_cpy, buf, bytes); 1081e098bc96SEvan Quan buf_cpy[bytes] = '\0'; 1082e098bc96SEvan Quan tmp = buf_cpy; 1083ce7c1d04SEvan Quan while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1084e098bc96SEvan Quan if (strlen(sub_str)) { 1085c915ef89SDan Carpenter ret = kstrtoul(sub_str, 0, &level); 1086c915ef89SDan Carpenter if (ret || level > 31) 1087e098bc96SEvan Quan return -EINVAL; 1088e098bc96SEvan Quan *mask |= 1 << level; 1089e098bc96SEvan Quan } else 1090e098bc96SEvan Quan break; 1091e098bc96SEvan Quan } 1092e098bc96SEvan Quan 1093e098bc96SEvan Quan return 0; 1094e098bc96SEvan Quan } 1095e098bc96SEvan Quan 10962ea092e5SDarren Powell static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 10972ea092e5SDarren Powell enum pp_clock_type type, 1098e098bc96SEvan Quan const char *buf, 1099e098bc96SEvan Quan size_t count) 1100e098bc96SEvan Quan { 1101e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 11021348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1103e098bc96SEvan Quan int ret; 1104e098bc96SEvan Quan uint32_t mask = 0; 1105e098bc96SEvan Quan 110653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1107e098bc96SEvan Quan return -EPERM; 1108d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1109d2ae842dSAlex Deucher return -EPERM; 1110e098bc96SEvan Quan 1111e098bc96SEvan Quan ret = amdgpu_read_mask(buf, count, &mask); 1112e098bc96SEvan Quan if (ret) 1113e098bc96SEvan Quan return ret; 1114e098bc96SEvan Quan 1115e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1116e098bc96SEvan Quan if (ret < 0) { 1117e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1118e098bc96SEvan Quan return ret; 1119e098bc96SEvan Quan } 1120e098bc96SEvan Quan 11212ea092e5SDarren Powell if (adev->powerplay.pp_funcs->force_clock_level) 11222ea092e5SDarren Powell ret = amdgpu_dpm_force_clock_level(adev, type, mask); 11232ea092e5SDarren Powell else 11242ea092e5SDarren Powell ret = 0; 1125e098bc96SEvan Quan 1126e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1127e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1128e098bc96SEvan Quan 1129e098bc96SEvan Quan if (ret) 1130e098bc96SEvan Quan return -EINVAL; 1131e098bc96SEvan Quan 1132e098bc96SEvan Quan return count; 1133e098bc96SEvan Quan } 1134e098bc96SEvan Quan 11352ea092e5SDarren Powell static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 11362ea092e5SDarren Powell struct device_attribute *attr, 11372ea092e5SDarren Powell char *buf) 11382ea092e5SDarren Powell { 11392ea092e5SDarren Powell return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 11402ea092e5SDarren Powell } 11412ea092e5SDarren Powell 11422ea092e5SDarren Powell static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 11432ea092e5SDarren Powell struct device_attribute *attr, 11442ea092e5SDarren Powell const char *buf, 11452ea092e5SDarren Powell size_t count) 11462ea092e5SDarren Powell { 11472ea092e5SDarren Powell return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 11482ea092e5SDarren Powell } 11492ea092e5SDarren Powell 1150e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1151e098bc96SEvan Quan struct device_attribute *attr, 1152e098bc96SEvan Quan char *buf) 1153e098bc96SEvan Quan { 11542ea092e5SDarren Powell return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1155e098bc96SEvan Quan } 1156e098bc96SEvan Quan 1157e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1158e098bc96SEvan Quan struct device_attribute *attr, 1159e098bc96SEvan Quan const char *buf, 1160e098bc96SEvan Quan size_t count) 1161e098bc96SEvan Quan { 11622ea092e5SDarren Powell return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1163e098bc96SEvan Quan } 1164e098bc96SEvan Quan 1165e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1166e098bc96SEvan Quan struct device_attribute *attr, 1167e098bc96SEvan Quan char *buf) 1168e098bc96SEvan Quan { 11692ea092e5SDarren Powell return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1170e098bc96SEvan Quan } 1171e098bc96SEvan Quan 1172e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1173e098bc96SEvan Quan struct device_attribute *attr, 1174e098bc96SEvan Quan const char *buf, 1175e098bc96SEvan Quan size_t count) 1176e098bc96SEvan Quan { 11772ea092e5SDarren Powell return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1178e098bc96SEvan Quan } 1179e098bc96SEvan Quan 1180e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1181e098bc96SEvan Quan struct device_attribute *attr, 1182e098bc96SEvan Quan char *buf) 1183e098bc96SEvan Quan { 11842ea092e5SDarren Powell return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1185e098bc96SEvan Quan } 1186e098bc96SEvan Quan 1187e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1188e098bc96SEvan Quan struct device_attribute *attr, 1189e098bc96SEvan Quan const char *buf, 1190e098bc96SEvan Quan size_t count) 1191e098bc96SEvan Quan { 11922ea092e5SDarren Powell return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1193e098bc96SEvan Quan } 1194e098bc96SEvan Quan 11959577b0ecSXiaojian Du static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 11969577b0ecSXiaojian Du struct device_attribute *attr, 11979577b0ecSXiaojian Du char *buf) 11989577b0ecSXiaojian Du { 11992ea092e5SDarren Powell return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 12009577b0ecSXiaojian Du } 12019577b0ecSXiaojian Du 12029577b0ecSXiaojian Du static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 12039577b0ecSXiaojian Du struct device_attribute *attr, 12049577b0ecSXiaojian Du const char *buf, 12059577b0ecSXiaojian Du size_t count) 12069577b0ecSXiaojian Du { 12072ea092e5SDarren Powell return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 12089577b0ecSXiaojian Du } 12099577b0ecSXiaojian Du 12109577b0ecSXiaojian Du static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 12119577b0ecSXiaojian Du struct device_attribute *attr, 12129577b0ecSXiaojian Du char *buf) 12139577b0ecSXiaojian Du { 12142ea092e5SDarren Powell return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 12159577b0ecSXiaojian Du } 12169577b0ecSXiaojian Du 12179577b0ecSXiaojian Du static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 12189577b0ecSXiaojian Du struct device_attribute *attr, 12199577b0ecSXiaojian Du const char *buf, 12209577b0ecSXiaojian Du size_t count) 12219577b0ecSXiaojian Du { 12222ea092e5SDarren Powell return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 12239577b0ecSXiaojian Du } 12249577b0ecSXiaojian Du 1225e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1226e098bc96SEvan Quan struct device_attribute *attr, 1227e098bc96SEvan Quan char *buf) 1228e098bc96SEvan Quan { 12292ea092e5SDarren Powell return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1230e098bc96SEvan Quan } 1231e098bc96SEvan Quan 1232e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1233e098bc96SEvan Quan struct device_attribute *attr, 1234e098bc96SEvan Quan const char *buf, 1235e098bc96SEvan Quan size_t count) 1236e098bc96SEvan Quan { 12372ea092e5SDarren Powell return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1238e098bc96SEvan Quan } 1239e098bc96SEvan Quan 1240e098bc96SEvan Quan static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1241e098bc96SEvan Quan struct device_attribute *attr, 1242e098bc96SEvan Quan char *buf) 1243e098bc96SEvan Quan { 12442ea092e5SDarren Powell return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1245e098bc96SEvan Quan } 1246e098bc96SEvan Quan 1247e098bc96SEvan Quan static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1248e098bc96SEvan Quan struct device_attribute *attr, 1249e098bc96SEvan Quan const char *buf, 1250e098bc96SEvan Quan size_t count) 1251e098bc96SEvan Quan { 12522ea092e5SDarren Powell return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1253e098bc96SEvan Quan } 1254e098bc96SEvan Quan 1255e098bc96SEvan Quan static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1256e098bc96SEvan Quan struct device_attribute *attr, 1257e098bc96SEvan Quan char *buf) 1258e098bc96SEvan Quan { 1259e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 12601348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1261e098bc96SEvan Quan uint32_t value = 0; 1262e098bc96SEvan Quan int ret; 1263e098bc96SEvan Quan 126453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1265e098bc96SEvan Quan return -EPERM; 1266d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1267d2ae842dSAlex Deucher return -EPERM; 1268e098bc96SEvan Quan 1269e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1270e098bc96SEvan Quan if (ret < 0) { 1271e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1272e098bc96SEvan Quan return ret; 1273e098bc96SEvan Quan } 1274e098bc96SEvan Quan 1275e098bc96SEvan Quan if (is_support_sw_smu(adev)) 127675145aabSAlex Deucher value = 0; 1277e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_sclk_od) 1278e098bc96SEvan Quan value = amdgpu_dpm_get_sclk_od(adev); 1279e098bc96SEvan Quan 1280e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1281e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1282e098bc96SEvan Quan 1283a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", value); 1284e098bc96SEvan Quan } 1285e098bc96SEvan Quan 1286e098bc96SEvan Quan static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1287e098bc96SEvan Quan struct device_attribute *attr, 1288e098bc96SEvan Quan const char *buf, 1289e098bc96SEvan Quan size_t count) 1290e098bc96SEvan Quan { 1291e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 12921348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1293e098bc96SEvan Quan int ret; 1294e098bc96SEvan Quan long int value; 1295e098bc96SEvan Quan 129653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1297e098bc96SEvan Quan return -EPERM; 1298d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1299d2ae842dSAlex Deucher return -EPERM; 1300e098bc96SEvan Quan 1301e098bc96SEvan Quan ret = kstrtol(buf, 0, &value); 1302e098bc96SEvan Quan 1303e098bc96SEvan Quan if (ret) 1304e098bc96SEvan Quan return -EINVAL; 1305e098bc96SEvan Quan 1306e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1307e098bc96SEvan Quan if (ret < 0) { 1308e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1309e098bc96SEvan Quan return ret; 1310e098bc96SEvan Quan } 1311e098bc96SEvan Quan 1312e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 131375145aabSAlex Deucher value = 0; 1314e098bc96SEvan Quan } else { 1315e098bc96SEvan Quan if (adev->powerplay.pp_funcs->set_sclk_od) 1316e098bc96SEvan Quan amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1317e098bc96SEvan Quan 1318e098bc96SEvan Quan if (adev->powerplay.pp_funcs->dispatch_tasks) { 1319e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 1320e098bc96SEvan Quan } else { 1321e098bc96SEvan Quan adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1322e098bc96SEvan Quan amdgpu_pm_compute_clocks(adev); 1323e098bc96SEvan Quan } 1324e098bc96SEvan Quan } 1325e098bc96SEvan Quan 1326e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1327e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1328e098bc96SEvan Quan 1329e098bc96SEvan Quan return count; 1330e098bc96SEvan Quan } 1331e098bc96SEvan Quan 1332e098bc96SEvan Quan static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1333e098bc96SEvan Quan struct device_attribute *attr, 1334e098bc96SEvan Quan char *buf) 1335e098bc96SEvan Quan { 1336e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 13371348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1338e098bc96SEvan Quan uint32_t value = 0; 1339e098bc96SEvan Quan int ret; 1340e098bc96SEvan Quan 134153b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1342e098bc96SEvan Quan return -EPERM; 1343d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1344d2ae842dSAlex Deucher return -EPERM; 1345e098bc96SEvan Quan 1346e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1347e098bc96SEvan Quan if (ret < 0) { 1348e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1349e098bc96SEvan Quan return ret; 1350e098bc96SEvan Quan } 1351e098bc96SEvan Quan 1352e098bc96SEvan Quan if (is_support_sw_smu(adev)) 135375145aabSAlex Deucher value = 0; 1354e098bc96SEvan Quan else if (adev->powerplay.pp_funcs->get_mclk_od) 1355e098bc96SEvan Quan value = amdgpu_dpm_get_mclk_od(adev); 1356e098bc96SEvan Quan 1357e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1358e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1359e098bc96SEvan Quan 1360a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", value); 1361e098bc96SEvan Quan } 1362e098bc96SEvan Quan 1363e098bc96SEvan Quan static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1364e098bc96SEvan Quan struct device_attribute *attr, 1365e098bc96SEvan Quan const char *buf, 1366e098bc96SEvan Quan size_t count) 1367e098bc96SEvan Quan { 1368e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 13691348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1370e098bc96SEvan Quan int ret; 1371e098bc96SEvan Quan long int value; 1372e098bc96SEvan Quan 137353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1374e098bc96SEvan Quan return -EPERM; 1375d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1376d2ae842dSAlex Deucher return -EPERM; 1377e098bc96SEvan Quan 1378e098bc96SEvan Quan ret = kstrtol(buf, 0, &value); 1379e098bc96SEvan Quan 1380e098bc96SEvan Quan if (ret) 1381e098bc96SEvan Quan return -EINVAL; 1382e098bc96SEvan Quan 1383e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1384e098bc96SEvan Quan if (ret < 0) { 1385e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1386e098bc96SEvan Quan return ret; 1387e098bc96SEvan Quan } 1388e098bc96SEvan Quan 1389e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 139075145aabSAlex Deucher value = 0; 1391e098bc96SEvan Quan } else { 1392e098bc96SEvan Quan if (adev->powerplay.pp_funcs->set_mclk_od) 1393e098bc96SEvan Quan amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1394e098bc96SEvan Quan 1395e098bc96SEvan Quan if (adev->powerplay.pp_funcs->dispatch_tasks) { 1396e098bc96SEvan Quan amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 1397e098bc96SEvan Quan } else { 1398e098bc96SEvan Quan adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1399e098bc96SEvan Quan amdgpu_pm_compute_clocks(adev); 1400e098bc96SEvan Quan } 1401e098bc96SEvan Quan } 1402e098bc96SEvan Quan 1403e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1404e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1405e098bc96SEvan Quan 1406e098bc96SEvan Quan return count; 1407e098bc96SEvan Quan } 1408e098bc96SEvan Quan 1409e098bc96SEvan Quan /** 1410e098bc96SEvan Quan * DOC: pp_power_profile_mode 1411e098bc96SEvan Quan * 1412e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for adjusting the heuristics 1413e098bc96SEvan Quan * related to switching between power levels in a power state. The file 1414e098bc96SEvan Quan * pp_power_profile_mode is used for this. 1415e098bc96SEvan Quan * 1416e098bc96SEvan Quan * Reading this file outputs a list of all of the predefined power profiles 1417e098bc96SEvan Quan * and the relevant heuristics settings for that profile. 1418e098bc96SEvan Quan * 1419e098bc96SEvan Quan * To select a profile or create a custom profile, first select manual using 1420e098bc96SEvan Quan * power_dpm_force_performance_level. Writing the number of a predefined 1421e098bc96SEvan Quan * profile to pp_power_profile_mode will enable those heuristics. To 1422e098bc96SEvan Quan * create a custom set of heuristics, write a string of numbers to the file 1423e098bc96SEvan Quan * starting with the number of the custom profile along with a setting 1424e098bc96SEvan Quan * for each heuristic parameter. Due to differences across asic families 1425e098bc96SEvan Quan * the heuristic parameters vary from family to family. 1426e098bc96SEvan Quan * 1427e098bc96SEvan Quan */ 1428e098bc96SEvan Quan 1429e098bc96SEvan Quan static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1430e098bc96SEvan Quan struct device_attribute *attr, 1431e098bc96SEvan Quan char *buf) 1432e098bc96SEvan Quan { 1433e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 14341348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1435e098bc96SEvan Quan ssize_t size; 1436e098bc96SEvan Quan int ret; 1437e098bc96SEvan Quan 143853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1439e098bc96SEvan Quan return -EPERM; 1440d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1441d2ae842dSAlex Deucher return -EPERM; 1442e098bc96SEvan Quan 1443e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1444e098bc96SEvan Quan if (ret < 0) { 1445e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1446e098bc96SEvan Quan return ret; 1447e098bc96SEvan Quan } 1448e098bc96SEvan Quan 14492ea092e5SDarren Powell if (adev->powerplay.pp_funcs->get_power_profile_mode) 1450e098bc96SEvan Quan size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1451e098bc96SEvan Quan else 1452e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 1453e098bc96SEvan Quan 1454e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1455e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1456e098bc96SEvan Quan 1457e098bc96SEvan Quan return size; 1458e098bc96SEvan Quan } 1459e098bc96SEvan Quan 1460e098bc96SEvan Quan 1461e098bc96SEvan Quan static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1462e098bc96SEvan Quan struct device_attribute *attr, 1463e098bc96SEvan Quan const char *buf, 1464e098bc96SEvan Quan size_t count) 1465e098bc96SEvan Quan { 1466e098bc96SEvan Quan int ret; 1467e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 14681348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1469e098bc96SEvan Quan uint32_t parameter_size = 0; 1470e098bc96SEvan Quan long parameter[64]; 1471e098bc96SEvan Quan char *sub_str, buf_cpy[128]; 1472e098bc96SEvan Quan char *tmp_str; 1473e098bc96SEvan Quan uint32_t i = 0; 1474e098bc96SEvan Quan char tmp[2]; 1475e098bc96SEvan Quan long int profile_mode = 0; 1476e098bc96SEvan Quan const char delimiter[3] = {' ', '\n', '\0'}; 1477e098bc96SEvan Quan 147853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1479e098bc96SEvan Quan return -EPERM; 1480d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1481d2ae842dSAlex Deucher return -EPERM; 1482e098bc96SEvan Quan 1483e098bc96SEvan Quan tmp[0] = *(buf); 1484e098bc96SEvan Quan tmp[1] = '\0'; 1485e098bc96SEvan Quan ret = kstrtol(tmp, 0, &profile_mode); 1486e098bc96SEvan Quan if (ret) 1487e098bc96SEvan Quan return -EINVAL; 1488e098bc96SEvan Quan 1489e098bc96SEvan Quan if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1490e098bc96SEvan Quan if (count < 2 || count > 127) 1491e098bc96SEvan Quan return -EINVAL; 1492e098bc96SEvan Quan while (isspace(*++buf)) 1493e098bc96SEvan Quan i++; 1494e098bc96SEvan Quan memcpy(buf_cpy, buf, count-i); 1495e098bc96SEvan Quan tmp_str = buf_cpy; 1496ce7c1d04SEvan Quan while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1497c2efbc3fSEvan Quan if (strlen(sub_str) == 0) 1498c2efbc3fSEvan Quan continue; 1499e098bc96SEvan Quan ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1500e098bc96SEvan Quan if (ret) 1501e098bc96SEvan Quan return -EINVAL; 1502e098bc96SEvan Quan parameter_size++; 1503e098bc96SEvan Quan while (isspace(*tmp_str)) 1504e098bc96SEvan Quan tmp_str++; 1505e098bc96SEvan Quan } 1506e098bc96SEvan Quan } 1507e098bc96SEvan Quan parameter[parameter_size] = profile_mode; 1508e098bc96SEvan Quan 1509e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1510e098bc96SEvan Quan if (ret < 0) { 1511e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1512e098bc96SEvan Quan return ret; 1513e098bc96SEvan Quan } 1514e098bc96SEvan Quan 15152ea092e5SDarren Powell if (adev->powerplay.pp_funcs->set_power_profile_mode) 1516e098bc96SEvan Quan ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1517e098bc96SEvan Quan 1518e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1519e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1520e098bc96SEvan Quan 1521e098bc96SEvan Quan if (!ret) 1522e098bc96SEvan Quan return count; 1523e098bc96SEvan Quan 1524e098bc96SEvan Quan return -EINVAL; 1525e098bc96SEvan Quan } 1526e098bc96SEvan Quan 1527e098bc96SEvan Quan /** 1528e098bc96SEvan Quan * DOC: gpu_busy_percent 1529e098bc96SEvan Quan * 1530e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for reading how busy the GPU 1531e098bc96SEvan Quan * is as a percentage. The file gpu_busy_percent is used for this. 1532e098bc96SEvan Quan * The SMU firmware computes a percentage of load based on the 1533e098bc96SEvan Quan * aggregate activity level in the IP cores. 1534e098bc96SEvan Quan */ 1535e098bc96SEvan Quan static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1536e098bc96SEvan Quan struct device_attribute *attr, 1537e098bc96SEvan Quan char *buf) 1538e098bc96SEvan Quan { 1539e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 15401348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1541e098bc96SEvan Quan int r, value, size = sizeof(value); 1542e098bc96SEvan Quan 154353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1544e098bc96SEvan Quan return -EPERM; 1545d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1546d2ae842dSAlex Deucher return -EPERM; 1547e098bc96SEvan Quan 1548e098bc96SEvan Quan r = pm_runtime_get_sync(ddev->dev); 1549e098bc96SEvan Quan if (r < 0) { 1550e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1551e098bc96SEvan Quan return r; 1552e098bc96SEvan Quan } 1553e098bc96SEvan Quan 1554e098bc96SEvan Quan /* read the IP busy sensor */ 1555e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, 1556e098bc96SEvan Quan (void *)&value, &size); 1557e098bc96SEvan Quan 1558e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1559e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1560e098bc96SEvan Quan 1561e098bc96SEvan Quan if (r) 1562e098bc96SEvan Quan return r; 1563e098bc96SEvan Quan 1564a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", value); 1565e098bc96SEvan Quan } 1566e098bc96SEvan Quan 1567e098bc96SEvan Quan /** 1568e098bc96SEvan Quan * DOC: mem_busy_percent 1569e098bc96SEvan Quan * 1570e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1571e098bc96SEvan Quan * is as a percentage. The file mem_busy_percent is used for this. 1572e098bc96SEvan Quan * The SMU firmware computes a percentage of load based on the 1573e098bc96SEvan Quan * aggregate activity level in the IP cores. 1574e098bc96SEvan Quan */ 1575e098bc96SEvan Quan static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1576e098bc96SEvan Quan struct device_attribute *attr, 1577e098bc96SEvan Quan char *buf) 1578e098bc96SEvan Quan { 1579e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 15801348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1581e098bc96SEvan Quan int r, value, size = sizeof(value); 1582e098bc96SEvan Quan 158353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1584e098bc96SEvan Quan return -EPERM; 1585d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1586d2ae842dSAlex Deucher return -EPERM; 1587e098bc96SEvan Quan 1588e098bc96SEvan Quan r = pm_runtime_get_sync(ddev->dev); 1589e098bc96SEvan Quan if (r < 0) { 1590e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1591e098bc96SEvan Quan return r; 1592e098bc96SEvan Quan } 1593e098bc96SEvan Quan 1594e098bc96SEvan Quan /* read the IP busy sensor */ 1595e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, 1596e098bc96SEvan Quan (void *)&value, &size); 1597e098bc96SEvan Quan 1598e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1599e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1600e098bc96SEvan Quan 1601e098bc96SEvan Quan if (r) 1602e098bc96SEvan Quan return r; 1603e098bc96SEvan Quan 1604a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", value); 1605e098bc96SEvan Quan } 1606e098bc96SEvan Quan 1607e098bc96SEvan Quan /** 1608e098bc96SEvan Quan * DOC: pcie_bw 1609e098bc96SEvan Quan * 1610e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for estimating how much data 1611e098bc96SEvan Quan * has been received and sent by the GPU in the last second through PCIe. 1612e098bc96SEvan Quan * The file pcie_bw is used for this. 1613e098bc96SEvan Quan * The Perf counters count the number of received and sent messages and return 1614e098bc96SEvan Quan * those values, as well as the maximum payload size of a PCIe packet (mps). 1615e098bc96SEvan Quan * Note that it is not possible to easily and quickly obtain the size of each 1616e098bc96SEvan Quan * packet transmitted, so we output the max payload size (mps) to allow for 1617e098bc96SEvan Quan * quick estimation of the PCIe bandwidth usage 1618e098bc96SEvan Quan */ 1619e098bc96SEvan Quan static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1620e098bc96SEvan Quan struct device_attribute *attr, 1621e098bc96SEvan Quan char *buf) 1622e098bc96SEvan Quan { 1623e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 16241348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1625e098bc96SEvan Quan uint64_t count0 = 0, count1 = 0; 1626e098bc96SEvan Quan int ret; 1627e098bc96SEvan Quan 162853b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1629e098bc96SEvan Quan return -EPERM; 1630d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1631d2ae842dSAlex Deucher return -EPERM; 1632e098bc96SEvan Quan 1633e098bc96SEvan Quan if (adev->flags & AMD_IS_APU) 1634e098bc96SEvan Quan return -ENODATA; 1635e098bc96SEvan Quan 1636e098bc96SEvan Quan if (!adev->asic_funcs->get_pcie_usage) 1637e098bc96SEvan Quan return -ENODATA; 1638e098bc96SEvan Quan 1639e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1640e098bc96SEvan Quan if (ret < 0) { 1641e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1642e098bc96SEvan Quan return ret; 1643e098bc96SEvan Quan } 1644e098bc96SEvan Quan 1645e098bc96SEvan Quan amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1646e098bc96SEvan Quan 1647e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1648e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1649e098bc96SEvan Quan 1650a9ca9bb3STian Tao return sysfs_emit(buf, "%llu %llu %i\n", 1651e098bc96SEvan Quan count0, count1, pcie_get_mps(adev->pdev)); 1652e098bc96SEvan Quan } 1653e098bc96SEvan Quan 1654e098bc96SEvan Quan /** 1655e098bc96SEvan Quan * DOC: unique_id 1656e098bc96SEvan Quan * 1657e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1658e098bc96SEvan Quan * The file unique_id is used for this. 1659e098bc96SEvan Quan * This will provide a Unique ID that will persist from machine to machine 1660e098bc96SEvan Quan * 1661e098bc96SEvan Quan * NOTE: This will only work for GFX9 and newer. This file will be absent 1662e098bc96SEvan Quan * on unsupported ASICs (GFX8 and older) 1663e098bc96SEvan Quan */ 1664e098bc96SEvan Quan static ssize_t amdgpu_get_unique_id(struct device *dev, 1665e098bc96SEvan Quan struct device_attribute *attr, 1666e098bc96SEvan Quan char *buf) 1667e098bc96SEvan Quan { 1668e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 16691348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1670e098bc96SEvan Quan 167153b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1672e098bc96SEvan Quan return -EPERM; 1673d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1674d2ae842dSAlex Deucher return -EPERM; 1675e098bc96SEvan Quan 1676e098bc96SEvan Quan if (adev->unique_id) 1677a9ca9bb3STian Tao return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1678e098bc96SEvan Quan 1679e098bc96SEvan Quan return 0; 1680e098bc96SEvan Quan } 1681e098bc96SEvan Quan 1682e098bc96SEvan Quan /** 1683e098bc96SEvan Quan * DOC: thermal_throttling_logging 1684e098bc96SEvan Quan * 1685e098bc96SEvan Quan * Thermal throttling pulls down the clock frequency and thus the performance. 1686e098bc96SEvan Quan * It's an useful mechanism to protect the chip from overheating. Since it 1687e098bc96SEvan Quan * impacts performance, the user controls whether it is enabled and if so, 1688e098bc96SEvan Quan * the log frequency. 1689e098bc96SEvan Quan * 1690e098bc96SEvan Quan * Reading back the file shows you the status(enabled or disabled) and 1691e098bc96SEvan Quan * the interval(in seconds) between each thermal logging. 1692e098bc96SEvan Quan * 1693e098bc96SEvan Quan * Writing an integer to the file, sets a new logging interval, in seconds. 1694e098bc96SEvan Quan * The value should be between 1 and 3600. If the value is less than 1, 1695e098bc96SEvan Quan * thermal logging is disabled. Values greater than 3600 are ignored. 1696e098bc96SEvan Quan */ 1697e098bc96SEvan Quan static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1698e098bc96SEvan Quan struct device_attribute *attr, 1699e098bc96SEvan Quan char *buf) 1700e098bc96SEvan Quan { 1701e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 17021348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1703e098bc96SEvan Quan 1704a9ca9bb3STian Tao return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 17054a580877SLuben Tuikov adev_to_drm(adev)->unique, 1706e098bc96SEvan Quan atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1707e098bc96SEvan Quan adev->throttling_logging_rs.interval / HZ + 1); 1708e098bc96SEvan Quan } 1709e098bc96SEvan Quan 1710e098bc96SEvan Quan static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1711e098bc96SEvan Quan struct device_attribute *attr, 1712e098bc96SEvan Quan const char *buf, 1713e098bc96SEvan Quan size_t count) 1714e098bc96SEvan Quan { 1715e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 17161348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1717e098bc96SEvan Quan long throttling_logging_interval; 1718e098bc96SEvan Quan unsigned long flags; 1719e098bc96SEvan Quan int ret = 0; 1720e098bc96SEvan Quan 1721e098bc96SEvan Quan ret = kstrtol(buf, 0, &throttling_logging_interval); 1722e098bc96SEvan Quan if (ret) 1723e098bc96SEvan Quan return ret; 1724e098bc96SEvan Quan 1725e098bc96SEvan Quan if (throttling_logging_interval > 3600) 1726e098bc96SEvan Quan return -EINVAL; 1727e098bc96SEvan Quan 1728e098bc96SEvan Quan if (throttling_logging_interval > 0) { 1729e098bc96SEvan Quan raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1730e098bc96SEvan Quan /* 1731e098bc96SEvan Quan * Reset the ratelimit timer internals. 1732e098bc96SEvan Quan * This can effectively restart the timer. 1733e098bc96SEvan Quan */ 1734e098bc96SEvan Quan adev->throttling_logging_rs.interval = 1735e098bc96SEvan Quan (throttling_logging_interval - 1) * HZ; 1736e098bc96SEvan Quan adev->throttling_logging_rs.begin = 0; 1737e098bc96SEvan Quan adev->throttling_logging_rs.printed = 0; 1738e098bc96SEvan Quan adev->throttling_logging_rs.missed = 0; 1739e098bc96SEvan Quan raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1740e098bc96SEvan Quan 1741e098bc96SEvan Quan atomic_set(&adev->throttling_logging_enabled, 1); 1742e098bc96SEvan Quan } else { 1743e098bc96SEvan Quan atomic_set(&adev->throttling_logging_enabled, 0); 1744e098bc96SEvan Quan } 1745e098bc96SEvan Quan 1746e098bc96SEvan Quan return count; 1747e098bc96SEvan Quan } 1748e098bc96SEvan Quan 1749e098bc96SEvan Quan /** 1750e098bc96SEvan Quan * DOC: gpu_metrics 1751e098bc96SEvan Quan * 1752e098bc96SEvan Quan * The amdgpu driver provides a sysfs API for retrieving current gpu 1753e098bc96SEvan Quan * metrics data. The file gpu_metrics is used for this. Reading the 1754e098bc96SEvan Quan * file will dump all the current gpu metrics data. 1755e098bc96SEvan Quan * 1756e098bc96SEvan Quan * These data include temperature, frequency, engines utilization, 1757e098bc96SEvan Quan * power consume, throttler status, fan speed and cpu core statistics( 1758e098bc96SEvan Quan * available for APU only). That's it will give a snapshot of all sensors 1759e098bc96SEvan Quan * at the same time. 1760e098bc96SEvan Quan */ 1761e098bc96SEvan Quan static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1762e098bc96SEvan Quan struct device_attribute *attr, 1763e098bc96SEvan Quan char *buf) 1764e098bc96SEvan Quan { 1765e098bc96SEvan Quan struct drm_device *ddev = dev_get_drvdata(dev); 17661348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(ddev); 1767e098bc96SEvan Quan void *gpu_metrics; 1768e098bc96SEvan Quan ssize_t size = 0; 1769e098bc96SEvan Quan int ret; 1770e098bc96SEvan Quan 177153b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 1772e098bc96SEvan Quan return -EPERM; 1773d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 1774d2ae842dSAlex Deucher return -EPERM; 1775e098bc96SEvan Quan 1776e098bc96SEvan Quan ret = pm_runtime_get_sync(ddev->dev); 1777e098bc96SEvan Quan if (ret < 0) { 1778e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1779e098bc96SEvan Quan return ret; 1780e098bc96SEvan Quan } 1781e098bc96SEvan Quan 17822ea092e5SDarren Powell if (adev->powerplay.pp_funcs->get_gpu_metrics) 1783e098bc96SEvan Quan size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1784e098bc96SEvan Quan 1785e098bc96SEvan Quan if (size <= 0) 1786e098bc96SEvan Quan goto out; 1787e098bc96SEvan Quan 1788e098bc96SEvan Quan if (size >= PAGE_SIZE) 1789e098bc96SEvan Quan size = PAGE_SIZE - 1; 1790e098bc96SEvan Quan 1791e098bc96SEvan Quan memcpy(buf, gpu_metrics, size); 1792e098bc96SEvan Quan 1793e098bc96SEvan Quan out: 1794e098bc96SEvan Quan pm_runtime_mark_last_busy(ddev->dev); 1795e098bc96SEvan Quan pm_runtime_put_autosuspend(ddev->dev); 1796e098bc96SEvan Quan 1797e098bc96SEvan Quan return size; 1798e098bc96SEvan Quan } 1799e098bc96SEvan Quan 1800e098bc96SEvan Quan static struct amdgpu_device_attr amdgpu_device_attrs[] = { 1801e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 18024215a119SHorace Chen AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1803e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC), 1804e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC), 1805e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC), 1806e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC), 1807e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1808e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1809e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1810e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 18119577b0ecSXiaojian Du AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 18129577b0ecSXiaojian Du AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1813e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC), 1814e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC), 1815e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 1816e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 1817e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC), 1818e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC), 1819e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC), 1820e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC), 1821e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 1822e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC), 1823e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC), 1824e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC), 1825e098bc96SEvan Quan AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC), 1826e098bc96SEvan Quan }; 1827e098bc96SEvan Quan 1828e098bc96SEvan Quan static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1829e098bc96SEvan Quan uint32_t mask, enum amdgpu_device_attr_states *states) 1830e098bc96SEvan Quan { 1831e098bc96SEvan Quan struct device_attribute *dev_attr = &attr->dev_attr; 1832e098bc96SEvan Quan const char *attr_name = dev_attr->attr.name; 1833e098bc96SEvan Quan struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 1834e098bc96SEvan Quan enum amd_asic_type asic_type = adev->asic_type; 1835e098bc96SEvan Quan 1836e098bc96SEvan Quan if (!(attr->flags & mask)) { 1837e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1838e098bc96SEvan Quan return 0; 1839e098bc96SEvan Quan } 1840e098bc96SEvan Quan 1841e098bc96SEvan Quan #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) 1842e098bc96SEvan Quan 1843e098bc96SEvan Quan if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 1844e098bc96SEvan Quan if (asic_type < CHIP_VEGA10) 1845e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1846e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 18470133840fSKent Russell if (asic_type < CHIP_VEGA10 || 18480133840fSKent Russell asic_type == CHIP_ARCTURUS || 18490133840fSKent Russell asic_type == CHIP_ALDEBARAN) 1850e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1851e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 1852e098bc96SEvan Quan if (asic_type < CHIP_VEGA20) 1853e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1854e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) { 1855e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1856e098bc96SEvan Quan if ((is_support_sw_smu(adev) && adev->smu.od_enabled) || 1857e017fb66SXiaojian Du (is_support_sw_smu(adev) && adev->smu.is_apu) || 1858e098bc96SEvan Quan (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 1859e098bc96SEvan Quan *states = ATTR_STATE_SUPPORTED; 1860e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(mem_busy_percent)) { 1861e098bc96SEvan Quan if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10) 1862e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1863e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pcie_bw)) { 1864e098bc96SEvan Quan /* PCIe Perf counters won't work on APU nodes */ 1865e098bc96SEvan Quan if (adev->flags & AMD_IS_APU) 1866e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1867e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(unique_id)) { 1868e098bc96SEvan Quan if (asic_type != CHIP_VEGA10 && 1869e098bc96SEvan Quan asic_type != CHIP_VEGA20 && 1870e098bc96SEvan Quan asic_type != CHIP_ARCTURUS) 1871e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1872e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(pp_features)) { 1873e098bc96SEvan Quan if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10) 1874e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 1875e098bc96SEvan Quan } else if (DEVICE_ATTR_IS(gpu_metrics)) { 1876e098bc96SEvan Quan if (asic_type < CHIP_VEGA12) 1877e098bc96SEvan Quan *states = ATTR_STATE_UNSUPPORTED; 18789577b0ecSXiaojian Du } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 18799577b0ecSXiaojian Du if (!(asic_type == CHIP_VANGOGH)) 18809577b0ecSXiaojian Du *states = ATTR_STATE_UNSUPPORTED; 18819577b0ecSXiaojian Du } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 18829577b0ecSXiaojian Du if (!(asic_type == CHIP_VANGOGH)) 18839577b0ecSXiaojian Du *states = ATTR_STATE_UNSUPPORTED; 1884e098bc96SEvan Quan } 1885e098bc96SEvan Quan 1886e098bc96SEvan Quan if (asic_type == CHIP_ARCTURUS) { 1887e098bc96SEvan Quan /* Arcturus does not support standalone mclk/socclk/fclk level setting */ 1888e098bc96SEvan Quan if (DEVICE_ATTR_IS(pp_dpm_mclk) || 1889e098bc96SEvan Quan DEVICE_ATTR_IS(pp_dpm_socclk) || 1890e098bc96SEvan Quan DEVICE_ATTR_IS(pp_dpm_fclk)) { 1891e098bc96SEvan Quan dev_attr->attr.mode &= ~S_IWUGO; 1892e098bc96SEvan Quan dev_attr->store = NULL; 1893e098bc96SEvan Quan } 1894e098bc96SEvan Quan } 1895e098bc96SEvan Quan 1896ede14a1bSDarren Powell if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 1897ede14a1bSDarren Powell /* SMU MP1 does not support dcefclk level setting */ 1898ede14a1bSDarren Powell if (asic_type >= CHIP_NAVI10) { 1899ede14a1bSDarren Powell dev_attr->attr.mode &= ~S_IWUGO; 1900ede14a1bSDarren Powell dev_attr->store = NULL; 1901ede14a1bSDarren Powell } 1902ede14a1bSDarren Powell } 1903ede14a1bSDarren Powell 1904e098bc96SEvan Quan #undef DEVICE_ATTR_IS 1905e098bc96SEvan Quan 1906e098bc96SEvan Quan return 0; 1907e098bc96SEvan Quan } 1908e098bc96SEvan Quan 1909e098bc96SEvan Quan 1910e098bc96SEvan Quan static int amdgpu_device_attr_create(struct amdgpu_device *adev, 1911e098bc96SEvan Quan struct amdgpu_device_attr *attr, 1912e098bc96SEvan Quan uint32_t mask, struct list_head *attr_list) 1913e098bc96SEvan Quan { 1914e098bc96SEvan Quan int ret = 0; 1915e098bc96SEvan Quan struct device_attribute *dev_attr = &attr->dev_attr; 1916e098bc96SEvan Quan const char *name = dev_attr->attr.name; 1917e098bc96SEvan Quan enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 1918e098bc96SEvan Quan struct amdgpu_device_attr_entry *attr_entry; 1919e098bc96SEvan Quan 1920e098bc96SEvan Quan int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1921e098bc96SEvan Quan uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 1922e098bc96SEvan Quan 1923e098bc96SEvan Quan BUG_ON(!attr); 1924e098bc96SEvan Quan 1925e098bc96SEvan Quan attr_update = attr->attr_update ? attr_update : default_attr_update; 1926e098bc96SEvan Quan 1927e098bc96SEvan Quan ret = attr_update(adev, attr, mask, &attr_states); 1928e098bc96SEvan Quan if (ret) { 1929e098bc96SEvan Quan dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 1930e098bc96SEvan Quan name, ret); 1931e098bc96SEvan Quan return ret; 1932e098bc96SEvan Quan } 1933e098bc96SEvan Quan 1934e098bc96SEvan Quan if (attr_states == ATTR_STATE_UNSUPPORTED) 1935e098bc96SEvan Quan return 0; 1936e098bc96SEvan Quan 1937e098bc96SEvan Quan ret = device_create_file(adev->dev, dev_attr); 1938e098bc96SEvan Quan if (ret) { 1939e098bc96SEvan Quan dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 1940e098bc96SEvan Quan name, ret); 1941e098bc96SEvan Quan } 1942e098bc96SEvan Quan 1943e098bc96SEvan Quan attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 1944e098bc96SEvan Quan if (!attr_entry) 1945e098bc96SEvan Quan return -ENOMEM; 1946e098bc96SEvan Quan 1947e098bc96SEvan Quan attr_entry->attr = attr; 1948e098bc96SEvan Quan INIT_LIST_HEAD(&attr_entry->entry); 1949e098bc96SEvan Quan 1950e098bc96SEvan Quan list_add_tail(&attr_entry->entry, attr_list); 1951e098bc96SEvan Quan 1952e098bc96SEvan Quan return ret; 1953e098bc96SEvan Quan } 1954e098bc96SEvan Quan 1955e098bc96SEvan Quan static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 1956e098bc96SEvan Quan { 1957e098bc96SEvan Quan struct device_attribute *dev_attr = &attr->dev_attr; 1958e098bc96SEvan Quan 1959e098bc96SEvan Quan device_remove_file(adev->dev, dev_attr); 1960e098bc96SEvan Quan } 1961e098bc96SEvan Quan 1962e098bc96SEvan Quan static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 1963e098bc96SEvan Quan struct list_head *attr_list); 1964e098bc96SEvan Quan 1965e098bc96SEvan Quan static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 1966e098bc96SEvan Quan struct amdgpu_device_attr *attrs, 1967e098bc96SEvan Quan uint32_t counts, 1968e098bc96SEvan Quan uint32_t mask, 1969e098bc96SEvan Quan struct list_head *attr_list) 1970e098bc96SEvan Quan { 1971e098bc96SEvan Quan int ret = 0; 1972e098bc96SEvan Quan uint32_t i = 0; 1973e098bc96SEvan Quan 1974e098bc96SEvan Quan for (i = 0; i < counts; i++) { 1975e098bc96SEvan Quan ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 1976e098bc96SEvan Quan if (ret) 1977e098bc96SEvan Quan goto failed; 1978e098bc96SEvan Quan } 1979e098bc96SEvan Quan 1980e098bc96SEvan Quan return 0; 1981e098bc96SEvan Quan 1982e098bc96SEvan Quan failed: 1983e098bc96SEvan Quan amdgpu_device_attr_remove_groups(adev, attr_list); 1984e098bc96SEvan Quan 1985e098bc96SEvan Quan return ret; 1986e098bc96SEvan Quan } 1987e098bc96SEvan Quan 1988e098bc96SEvan Quan static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 1989e098bc96SEvan Quan struct list_head *attr_list) 1990e098bc96SEvan Quan { 1991e098bc96SEvan Quan struct amdgpu_device_attr_entry *entry, *entry_tmp; 1992e098bc96SEvan Quan 1993e098bc96SEvan Quan if (list_empty(attr_list)) 1994e098bc96SEvan Quan return ; 1995e098bc96SEvan Quan 1996e098bc96SEvan Quan list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 1997e098bc96SEvan Quan amdgpu_device_attr_remove(adev, entry->attr); 1998e098bc96SEvan Quan list_del(&entry->entry); 1999e098bc96SEvan Quan kfree(entry); 2000e098bc96SEvan Quan } 2001e098bc96SEvan Quan } 2002e098bc96SEvan Quan 2003e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2004e098bc96SEvan Quan struct device_attribute *attr, 2005e098bc96SEvan Quan char *buf) 2006e098bc96SEvan Quan { 2007e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2008e098bc96SEvan Quan int channel = to_sensor_dev_attr(attr)->index; 2009e098bc96SEvan Quan int r, temp = 0, size = sizeof(temp); 2010e098bc96SEvan Quan 201153b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2012e098bc96SEvan Quan return -EPERM; 2013d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2014d2ae842dSAlex Deucher return -EPERM; 2015e098bc96SEvan Quan 2016e098bc96SEvan Quan if (channel >= PP_TEMP_MAX) 2017e098bc96SEvan Quan return -EINVAL; 2018e098bc96SEvan Quan 20194a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2020e098bc96SEvan Quan if (r < 0) { 20214a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2022e098bc96SEvan Quan return r; 2023e098bc96SEvan Quan } 2024e098bc96SEvan Quan 2025e098bc96SEvan Quan switch (channel) { 2026e098bc96SEvan Quan case PP_TEMP_JUNCTION: 2027e098bc96SEvan Quan /* get current junction temperature */ 2028e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2029e098bc96SEvan Quan (void *)&temp, &size); 2030e098bc96SEvan Quan break; 2031e098bc96SEvan Quan case PP_TEMP_EDGE: 2032e098bc96SEvan Quan /* get current edge temperature */ 2033e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2034e098bc96SEvan Quan (void *)&temp, &size); 2035e098bc96SEvan Quan break; 2036e098bc96SEvan Quan case PP_TEMP_MEM: 2037e098bc96SEvan Quan /* get current memory temperature */ 2038e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2039e098bc96SEvan Quan (void *)&temp, &size); 2040e098bc96SEvan Quan break; 2041e098bc96SEvan Quan default: 2042e098bc96SEvan Quan r = -EINVAL; 2043e098bc96SEvan Quan break; 2044e098bc96SEvan Quan } 2045e098bc96SEvan Quan 20464a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 20474a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2048e098bc96SEvan Quan 2049e098bc96SEvan Quan if (r) 2050e098bc96SEvan Quan return r; 2051e098bc96SEvan Quan 2052a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", temp); 2053e098bc96SEvan Quan } 2054e098bc96SEvan Quan 2055e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2056e098bc96SEvan Quan struct device_attribute *attr, 2057e098bc96SEvan Quan char *buf) 2058e098bc96SEvan Quan { 2059e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2060e098bc96SEvan Quan int hyst = to_sensor_dev_attr(attr)->index; 2061e098bc96SEvan Quan int temp; 2062e098bc96SEvan Quan 2063e098bc96SEvan Quan if (hyst) 2064e098bc96SEvan Quan temp = adev->pm.dpm.thermal.min_temp; 2065e098bc96SEvan Quan else 2066e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_temp; 2067e098bc96SEvan Quan 2068a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", temp); 2069e098bc96SEvan Quan } 2070e098bc96SEvan Quan 2071e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2072e098bc96SEvan Quan struct device_attribute *attr, 2073e098bc96SEvan Quan char *buf) 2074e098bc96SEvan Quan { 2075e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2076e098bc96SEvan Quan int hyst = to_sensor_dev_attr(attr)->index; 2077e098bc96SEvan Quan int temp; 2078e098bc96SEvan Quan 2079e098bc96SEvan Quan if (hyst) 2080e098bc96SEvan Quan temp = adev->pm.dpm.thermal.min_hotspot_temp; 2081e098bc96SEvan Quan else 2082e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2083e098bc96SEvan Quan 2084a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", temp); 2085e098bc96SEvan Quan } 2086e098bc96SEvan Quan 2087e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2088e098bc96SEvan Quan struct device_attribute *attr, 2089e098bc96SEvan Quan char *buf) 2090e098bc96SEvan Quan { 2091e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2092e098bc96SEvan Quan int hyst = to_sensor_dev_attr(attr)->index; 2093e098bc96SEvan Quan int temp; 2094e098bc96SEvan Quan 2095e098bc96SEvan Quan if (hyst) 2096e098bc96SEvan Quan temp = adev->pm.dpm.thermal.min_mem_temp; 2097e098bc96SEvan Quan else 2098e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2099e098bc96SEvan Quan 2100a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", temp); 2101e098bc96SEvan Quan } 2102e098bc96SEvan Quan 2103e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2104e098bc96SEvan Quan struct device_attribute *attr, 2105e098bc96SEvan Quan char *buf) 2106e098bc96SEvan Quan { 2107e098bc96SEvan Quan int channel = to_sensor_dev_attr(attr)->index; 2108e098bc96SEvan Quan 2109e098bc96SEvan Quan if (channel >= PP_TEMP_MAX) 2110e098bc96SEvan Quan return -EINVAL; 2111e098bc96SEvan Quan 2112a9ca9bb3STian Tao return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2113e098bc96SEvan Quan } 2114e098bc96SEvan Quan 2115e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2116e098bc96SEvan Quan struct device_attribute *attr, 2117e098bc96SEvan Quan char *buf) 2118e098bc96SEvan Quan { 2119e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2120e098bc96SEvan Quan int channel = to_sensor_dev_attr(attr)->index; 2121e098bc96SEvan Quan int temp = 0; 2122e098bc96SEvan Quan 2123e098bc96SEvan Quan if (channel >= PP_TEMP_MAX) 2124e098bc96SEvan Quan return -EINVAL; 2125e098bc96SEvan Quan 2126e098bc96SEvan Quan switch (channel) { 2127e098bc96SEvan Quan case PP_TEMP_JUNCTION: 2128e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2129e098bc96SEvan Quan break; 2130e098bc96SEvan Quan case PP_TEMP_EDGE: 2131e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2132e098bc96SEvan Quan break; 2133e098bc96SEvan Quan case PP_TEMP_MEM: 2134e098bc96SEvan Quan temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2135e098bc96SEvan Quan break; 2136e098bc96SEvan Quan } 2137e098bc96SEvan Quan 2138a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", temp); 2139e098bc96SEvan Quan } 2140e098bc96SEvan Quan 2141e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2142e098bc96SEvan Quan struct device_attribute *attr, 2143e098bc96SEvan Quan char *buf) 2144e098bc96SEvan Quan { 2145e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2146e098bc96SEvan Quan u32 pwm_mode = 0; 2147e098bc96SEvan Quan int ret; 2148e098bc96SEvan Quan 214953b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2150e098bc96SEvan Quan return -EPERM; 2151d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2152d2ae842dSAlex Deucher return -EPERM; 2153e098bc96SEvan Quan 21544a580877SLuben Tuikov ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2155e098bc96SEvan Quan if (ret < 0) { 21564a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2157e098bc96SEvan Quan return ret; 2158e098bc96SEvan Quan } 2159e098bc96SEvan Quan 2160e098bc96SEvan Quan if (!adev->powerplay.pp_funcs->get_fan_control_mode) { 21614a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 21624a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2163e098bc96SEvan Quan return -EINVAL; 2164e098bc96SEvan Quan } 2165e098bc96SEvan Quan 2166e098bc96SEvan Quan pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 2167e098bc96SEvan Quan 21684a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 21694a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2170e098bc96SEvan Quan 2171f46587bcSDarren Powell return sprintf(buf, "%u\n", pwm_mode); 2172e098bc96SEvan Quan } 2173e098bc96SEvan Quan 2174e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2175e098bc96SEvan Quan struct device_attribute *attr, 2176e098bc96SEvan Quan const char *buf, 2177e098bc96SEvan Quan size_t count) 2178e098bc96SEvan Quan { 2179e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2180e098bc96SEvan Quan int err, ret; 2181e098bc96SEvan Quan int value; 2182e098bc96SEvan Quan 218353b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2184e098bc96SEvan Quan return -EPERM; 2185d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2186d2ae842dSAlex Deucher return -EPERM; 2187e098bc96SEvan Quan 2188e098bc96SEvan Quan err = kstrtoint(buf, 10, &value); 2189e098bc96SEvan Quan if (err) 2190e098bc96SEvan Quan return err; 2191e098bc96SEvan Quan 21924a580877SLuben Tuikov ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2193e098bc96SEvan Quan if (ret < 0) { 21944a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2195e098bc96SEvan Quan return ret; 2196e098bc96SEvan Quan } 2197e098bc96SEvan Quan 2198e098bc96SEvan Quan if (!adev->powerplay.pp_funcs->set_fan_control_mode) { 21994a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 22004a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2201e098bc96SEvan Quan return -EINVAL; 2202e098bc96SEvan Quan } 2203e098bc96SEvan Quan 2204e098bc96SEvan Quan amdgpu_dpm_set_fan_control_mode(adev, value); 2205e098bc96SEvan Quan 22064a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 22074a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2208e098bc96SEvan Quan 2209e098bc96SEvan Quan return count; 2210e098bc96SEvan Quan } 2211e098bc96SEvan Quan 2212e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2213e098bc96SEvan Quan struct device_attribute *attr, 2214e098bc96SEvan Quan char *buf) 2215e098bc96SEvan Quan { 2216e098bc96SEvan Quan return sprintf(buf, "%i\n", 0); 2217e098bc96SEvan Quan } 2218e098bc96SEvan Quan 2219e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2220e098bc96SEvan Quan struct device_attribute *attr, 2221e098bc96SEvan Quan char *buf) 2222e098bc96SEvan Quan { 2223e098bc96SEvan Quan return sprintf(buf, "%i\n", 255); 2224e098bc96SEvan Quan } 2225e098bc96SEvan Quan 2226e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2227e098bc96SEvan Quan struct device_attribute *attr, 2228e098bc96SEvan Quan const char *buf, size_t count) 2229e098bc96SEvan Quan { 2230e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2231e098bc96SEvan Quan int err; 2232e098bc96SEvan Quan u32 value; 2233e098bc96SEvan Quan u32 pwm_mode; 2234e098bc96SEvan Quan 223553b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2236e098bc96SEvan Quan return -EPERM; 2237d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2238d2ae842dSAlex Deucher return -EPERM; 2239e098bc96SEvan Quan 22404a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2241e098bc96SEvan Quan if (err < 0) { 22424a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2243e098bc96SEvan Quan return err; 2244e098bc96SEvan Quan } 2245e098bc96SEvan Quan 2246e098bc96SEvan Quan pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 2247e098bc96SEvan Quan if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2248e098bc96SEvan Quan pr_info("manual fan speed control should be enabled first\n"); 22494a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 22504a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2251e098bc96SEvan Quan return -EINVAL; 2252e098bc96SEvan Quan } 2253e098bc96SEvan Quan 2254e098bc96SEvan Quan err = kstrtou32(buf, 10, &value); 2255e098bc96SEvan Quan if (err) { 22564a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 22574a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2258e098bc96SEvan Quan return err; 2259e098bc96SEvan Quan } 2260e098bc96SEvan Quan 2261e098bc96SEvan Quan value = (value * 100) / 255; 2262e098bc96SEvan Quan 2263f46587bcSDarren Powell if (adev->powerplay.pp_funcs->set_fan_speed_percent) 2264e098bc96SEvan Quan err = amdgpu_dpm_set_fan_speed_percent(adev, value); 2265e098bc96SEvan Quan else 2266e098bc96SEvan Quan err = -EINVAL; 2267e098bc96SEvan Quan 22684a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 22694a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2270e098bc96SEvan Quan 2271e098bc96SEvan Quan if (err) 2272e098bc96SEvan Quan return err; 2273e098bc96SEvan Quan 2274e098bc96SEvan Quan return count; 2275e098bc96SEvan Quan } 2276e098bc96SEvan Quan 2277e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2278e098bc96SEvan Quan struct device_attribute *attr, 2279e098bc96SEvan Quan char *buf) 2280e098bc96SEvan Quan { 2281e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2282e098bc96SEvan Quan int err; 2283e098bc96SEvan Quan u32 speed = 0; 2284e098bc96SEvan Quan 228553b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2286e098bc96SEvan Quan return -EPERM; 2287d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2288d2ae842dSAlex Deucher return -EPERM; 2289e098bc96SEvan Quan 22904a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2291e098bc96SEvan Quan if (err < 0) { 22924a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2293e098bc96SEvan Quan return err; 2294e098bc96SEvan Quan } 2295e098bc96SEvan Quan 2296f46587bcSDarren Powell if (adev->powerplay.pp_funcs->get_fan_speed_percent) 2297e098bc96SEvan Quan err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); 2298e098bc96SEvan Quan else 2299e098bc96SEvan Quan err = -EINVAL; 2300e098bc96SEvan Quan 23014a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 23024a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2303e098bc96SEvan Quan 2304e098bc96SEvan Quan if (err) 2305e098bc96SEvan Quan return err; 2306e098bc96SEvan Quan 2307e098bc96SEvan Quan speed = (speed * 255) / 100; 2308e098bc96SEvan Quan 2309e098bc96SEvan Quan return sprintf(buf, "%i\n", speed); 2310e098bc96SEvan Quan } 2311e098bc96SEvan Quan 2312e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2313e098bc96SEvan Quan struct device_attribute *attr, 2314e098bc96SEvan Quan char *buf) 2315e098bc96SEvan Quan { 2316e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2317e098bc96SEvan Quan int err; 2318e098bc96SEvan Quan u32 speed = 0; 2319e098bc96SEvan Quan 232053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2321e098bc96SEvan Quan return -EPERM; 2322d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2323d2ae842dSAlex Deucher return -EPERM; 2324e098bc96SEvan Quan 23254a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2326e098bc96SEvan Quan if (err < 0) { 23274a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2328e098bc96SEvan Quan return err; 2329e098bc96SEvan Quan } 2330e098bc96SEvan Quan 2331f46587bcSDarren Powell if (adev->powerplay.pp_funcs->get_fan_speed_rpm) 2332e098bc96SEvan Quan err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2333e098bc96SEvan Quan else 2334e098bc96SEvan Quan err = -EINVAL; 2335e098bc96SEvan Quan 23364a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 23374a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2338e098bc96SEvan Quan 2339e098bc96SEvan Quan if (err) 2340e098bc96SEvan Quan return err; 2341e098bc96SEvan Quan 2342e098bc96SEvan Quan return sprintf(buf, "%i\n", speed); 2343e098bc96SEvan Quan } 2344e098bc96SEvan Quan 2345e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2346e098bc96SEvan Quan struct device_attribute *attr, 2347e098bc96SEvan Quan char *buf) 2348e098bc96SEvan Quan { 2349e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2350e098bc96SEvan Quan u32 min_rpm = 0; 2351e098bc96SEvan Quan u32 size = sizeof(min_rpm); 2352e098bc96SEvan Quan int r; 2353e098bc96SEvan Quan 235453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2355e098bc96SEvan Quan return -EPERM; 2356d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2357d2ae842dSAlex Deucher return -EPERM; 2358e098bc96SEvan Quan 23594a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2360e098bc96SEvan Quan if (r < 0) { 23614a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2362e098bc96SEvan Quan return r; 2363e098bc96SEvan Quan } 2364e098bc96SEvan Quan 2365e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2366e098bc96SEvan Quan (void *)&min_rpm, &size); 2367e098bc96SEvan Quan 23684a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 23694a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2370e098bc96SEvan Quan 2371e098bc96SEvan Quan if (r) 2372e098bc96SEvan Quan return r; 2373e098bc96SEvan Quan 2374a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", min_rpm); 2375e098bc96SEvan Quan } 2376e098bc96SEvan Quan 2377e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2378e098bc96SEvan Quan struct device_attribute *attr, 2379e098bc96SEvan Quan char *buf) 2380e098bc96SEvan Quan { 2381e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2382e098bc96SEvan Quan u32 max_rpm = 0; 2383e098bc96SEvan Quan u32 size = sizeof(max_rpm); 2384e098bc96SEvan Quan int r; 2385e098bc96SEvan Quan 238653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2387e098bc96SEvan Quan return -EPERM; 2388d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2389d2ae842dSAlex Deucher return -EPERM; 2390e098bc96SEvan Quan 23914a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2392e098bc96SEvan Quan if (r < 0) { 23934a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2394e098bc96SEvan Quan return r; 2395e098bc96SEvan Quan } 2396e098bc96SEvan Quan 2397e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2398e098bc96SEvan Quan (void *)&max_rpm, &size); 2399e098bc96SEvan Quan 24004a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24014a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2402e098bc96SEvan Quan 2403e098bc96SEvan Quan if (r) 2404e098bc96SEvan Quan return r; 2405e098bc96SEvan Quan 2406a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", max_rpm); 2407e098bc96SEvan Quan } 2408e098bc96SEvan Quan 2409e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2410e098bc96SEvan Quan struct device_attribute *attr, 2411e098bc96SEvan Quan char *buf) 2412e098bc96SEvan Quan { 2413e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2414e098bc96SEvan Quan int err; 2415e098bc96SEvan Quan u32 rpm = 0; 2416e098bc96SEvan Quan 241753b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2418e098bc96SEvan Quan return -EPERM; 2419d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2420d2ae842dSAlex Deucher return -EPERM; 2421e098bc96SEvan Quan 24224a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2423e098bc96SEvan Quan if (err < 0) { 24244a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2425e098bc96SEvan Quan return err; 2426e098bc96SEvan Quan } 2427e098bc96SEvan Quan 2428f46587bcSDarren Powell if (adev->powerplay.pp_funcs->get_fan_speed_rpm) 2429e098bc96SEvan Quan err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2430e098bc96SEvan Quan else 2431e098bc96SEvan Quan err = -EINVAL; 2432e098bc96SEvan Quan 24334a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24344a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2435e098bc96SEvan Quan 2436e098bc96SEvan Quan if (err) 2437e098bc96SEvan Quan return err; 2438e098bc96SEvan Quan 2439e098bc96SEvan Quan return sprintf(buf, "%i\n", rpm); 2440e098bc96SEvan Quan } 2441e098bc96SEvan Quan 2442e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2443e098bc96SEvan Quan struct device_attribute *attr, 2444e098bc96SEvan Quan const char *buf, size_t count) 2445e098bc96SEvan Quan { 2446e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2447e098bc96SEvan Quan int err; 2448e098bc96SEvan Quan u32 value; 2449e098bc96SEvan Quan u32 pwm_mode; 2450e098bc96SEvan Quan 245153b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2452e098bc96SEvan Quan return -EPERM; 2453d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2454d2ae842dSAlex Deucher return -EPERM; 2455e098bc96SEvan Quan 24564a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2457e098bc96SEvan Quan if (err < 0) { 24584a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2459e098bc96SEvan Quan return err; 2460e098bc96SEvan Quan } 2461e098bc96SEvan Quan 2462e098bc96SEvan Quan pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 2463e098bc96SEvan Quan 2464e098bc96SEvan Quan if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 24654a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24664a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2467e098bc96SEvan Quan return -ENODATA; 2468e098bc96SEvan Quan } 2469e098bc96SEvan Quan 2470e098bc96SEvan Quan err = kstrtou32(buf, 10, &value); 2471e098bc96SEvan Quan if (err) { 24724a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24734a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2474e098bc96SEvan Quan return err; 2475e098bc96SEvan Quan } 2476e098bc96SEvan Quan 2477f46587bcSDarren Powell if (adev->powerplay.pp_funcs->set_fan_speed_rpm) 2478e098bc96SEvan Quan err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2479e098bc96SEvan Quan else 2480e098bc96SEvan Quan err = -EINVAL; 2481e098bc96SEvan Quan 24824a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 24834a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2484e098bc96SEvan Quan 2485e098bc96SEvan Quan if (err) 2486e098bc96SEvan Quan return err; 2487e098bc96SEvan Quan 2488e098bc96SEvan Quan return count; 2489e098bc96SEvan Quan } 2490e098bc96SEvan Quan 2491e098bc96SEvan Quan static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2492e098bc96SEvan Quan struct device_attribute *attr, 2493e098bc96SEvan Quan char *buf) 2494e098bc96SEvan Quan { 2495e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2496e098bc96SEvan Quan u32 pwm_mode = 0; 2497e098bc96SEvan Quan int ret; 2498e098bc96SEvan Quan 249953b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2500e098bc96SEvan Quan return -EPERM; 2501d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2502d2ae842dSAlex Deucher return -EPERM; 2503e098bc96SEvan Quan 25044a580877SLuben Tuikov ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2505e098bc96SEvan Quan if (ret < 0) { 25064a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2507e098bc96SEvan Quan return ret; 2508e098bc96SEvan Quan } 2509e098bc96SEvan Quan 2510e098bc96SEvan Quan if (!adev->powerplay.pp_funcs->get_fan_control_mode) { 25114a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 25124a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2513e098bc96SEvan Quan return -EINVAL; 2514e098bc96SEvan Quan } 2515e098bc96SEvan Quan 2516e098bc96SEvan Quan pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 2517e098bc96SEvan Quan 25184a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 25194a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2520e098bc96SEvan Quan 2521e098bc96SEvan Quan return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2522e098bc96SEvan Quan } 2523e098bc96SEvan Quan 2524e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2525e098bc96SEvan Quan struct device_attribute *attr, 2526e098bc96SEvan Quan const char *buf, 2527e098bc96SEvan Quan size_t count) 2528e098bc96SEvan Quan { 2529e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2530e098bc96SEvan Quan int err; 2531e098bc96SEvan Quan int value; 2532e098bc96SEvan Quan u32 pwm_mode; 2533e098bc96SEvan Quan 253453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2535e098bc96SEvan Quan return -EPERM; 2536d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2537d2ae842dSAlex Deucher return -EPERM; 2538e098bc96SEvan Quan 2539e098bc96SEvan Quan err = kstrtoint(buf, 10, &value); 2540e098bc96SEvan Quan if (err) 2541e098bc96SEvan Quan return err; 2542e098bc96SEvan Quan 2543e098bc96SEvan Quan if (value == 0) 2544e098bc96SEvan Quan pwm_mode = AMD_FAN_CTRL_AUTO; 2545e098bc96SEvan Quan else if (value == 1) 2546e098bc96SEvan Quan pwm_mode = AMD_FAN_CTRL_MANUAL; 2547e098bc96SEvan Quan else 2548e098bc96SEvan Quan return -EINVAL; 2549e098bc96SEvan Quan 25504a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2551e098bc96SEvan Quan if (err < 0) { 25524a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2553e098bc96SEvan Quan return err; 2554e098bc96SEvan Quan } 2555e098bc96SEvan Quan 2556e098bc96SEvan Quan if (!adev->powerplay.pp_funcs->set_fan_control_mode) { 25574a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 25584a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2559e098bc96SEvan Quan return -EINVAL; 2560e098bc96SEvan Quan } 2561e098bc96SEvan Quan amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2562e098bc96SEvan Quan 25634a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 25644a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2565e098bc96SEvan Quan 2566e098bc96SEvan Quan return count; 2567e098bc96SEvan Quan } 2568e098bc96SEvan Quan 2569e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 2570e098bc96SEvan Quan struct device_attribute *attr, 2571e098bc96SEvan Quan char *buf) 2572e098bc96SEvan Quan { 2573e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2574e098bc96SEvan Quan u32 vddgfx; 2575e098bc96SEvan Quan int r, size = sizeof(vddgfx); 2576e098bc96SEvan Quan 257753b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2578e098bc96SEvan Quan return -EPERM; 2579d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2580d2ae842dSAlex Deucher return -EPERM; 2581e098bc96SEvan Quan 25824a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2583e098bc96SEvan Quan if (r < 0) { 25844a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2585e098bc96SEvan Quan return r; 2586e098bc96SEvan Quan } 2587e098bc96SEvan Quan 2588e098bc96SEvan Quan /* get the voltage */ 2589e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, 2590e098bc96SEvan Quan (void *)&vddgfx, &size); 2591e098bc96SEvan Quan 25924a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 25934a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2594e098bc96SEvan Quan 2595e098bc96SEvan Quan if (r) 2596e098bc96SEvan Quan return r; 2597e098bc96SEvan Quan 2598a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", vddgfx); 2599e098bc96SEvan Quan } 2600e098bc96SEvan Quan 2601e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 2602e098bc96SEvan Quan struct device_attribute *attr, 2603e098bc96SEvan Quan char *buf) 2604e098bc96SEvan Quan { 2605a9ca9bb3STian Tao return sysfs_emit(buf, "vddgfx\n"); 2606e098bc96SEvan Quan } 2607e098bc96SEvan Quan 2608e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 2609e098bc96SEvan Quan struct device_attribute *attr, 2610e098bc96SEvan Quan char *buf) 2611e098bc96SEvan Quan { 2612e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2613e098bc96SEvan Quan u32 vddnb; 2614e098bc96SEvan Quan int r, size = sizeof(vddnb); 2615e098bc96SEvan Quan 261653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2617e098bc96SEvan Quan return -EPERM; 2618d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2619d2ae842dSAlex Deucher return -EPERM; 2620e098bc96SEvan Quan 2621e098bc96SEvan Quan /* only APUs have vddnb */ 2622e098bc96SEvan Quan if (!(adev->flags & AMD_IS_APU)) 2623e098bc96SEvan Quan return -EINVAL; 2624e098bc96SEvan Quan 26254a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2626e098bc96SEvan Quan if (r < 0) { 26274a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2628e098bc96SEvan Quan return r; 2629e098bc96SEvan Quan } 2630e098bc96SEvan Quan 2631e098bc96SEvan Quan /* get the voltage */ 2632e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, 2633e098bc96SEvan Quan (void *)&vddnb, &size); 2634e098bc96SEvan Quan 26354a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 26364a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2637e098bc96SEvan Quan 2638e098bc96SEvan Quan if (r) 2639e098bc96SEvan Quan return r; 2640e098bc96SEvan Quan 2641a9ca9bb3STian Tao return sysfs_emit(buf, "%d\n", vddnb); 2642e098bc96SEvan Quan } 2643e098bc96SEvan Quan 2644e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 2645e098bc96SEvan Quan struct device_attribute *attr, 2646e098bc96SEvan Quan char *buf) 2647e098bc96SEvan Quan { 2648a9ca9bb3STian Tao return sysfs_emit(buf, "vddnb\n"); 2649e098bc96SEvan Quan } 2650e098bc96SEvan Quan 2651e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 2652e098bc96SEvan Quan struct device_attribute *attr, 2653e098bc96SEvan Quan char *buf) 2654e098bc96SEvan Quan { 2655e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2656e098bc96SEvan Quan u32 query = 0; 2657e098bc96SEvan Quan int r, size = sizeof(u32); 2658e098bc96SEvan Quan unsigned uw; 2659e098bc96SEvan Quan 266053b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2661e098bc96SEvan Quan return -EPERM; 2662d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2663d2ae842dSAlex Deucher return -EPERM; 2664e098bc96SEvan Quan 26654a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2666e098bc96SEvan Quan if (r < 0) { 26674a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2668e098bc96SEvan Quan return r; 2669e098bc96SEvan Quan } 2670e098bc96SEvan Quan 2671e098bc96SEvan Quan /* get the voltage */ 2672e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, 2673e098bc96SEvan Quan (void *)&query, &size); 2674e098bc96SEvan Quan 26754a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 26764a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2677e098bc96SEvan Quan 2678e098bc96SEvan Quan if (r) 2679e098bc96SEvan Quan return r; 2680e098bc96SEvan Quan 2681e098bc96SEvan Quan /* convert to microwatts */ 2682e098bc96SEvan Quan uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 2683e098bc96SEvan Quan 2684a9ca9bb3STian Tao return sysfs_emit(buf, "%u\n", uw); 2685e098bc96SEvan Quan } 2686e098bc96SEvan Quan 2687e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 2688e098bc96SEvan Quan struct device_attribute *attr, 2689e098bc96SEvan Quan char *buf) 2690e098bc96SEvan Quan { 2691e098bc96SEvan Quan return sprintf(buf, "%i\n", 0); 2692e098bc96SEvan Quan } 2693e098bc96SEvan Quan 2694e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 2695e098bc96SEvan Quan struct device_attribute *attr, 2696e098bc96SEvan Quan char *buf) 2697e098bc96SEvan Quan { 2698e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 26998dfc8c53SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 2700ae07970aSXiaomeng Hou int limit_type = to_sensor_dev_attr(attr)->index; 2701ae07970aSXiaomeng Hou uint32_t limit = limit_type << 24; 27026e58941cSEric Huang uint32_t max_limit = 0; 2703e098bc96SEvan Quan ssize_t size; 2704e098bc96SEvan Quan int r; 2705e098bc96SEvan Quan 270653b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2707e098bc96SEvan Quan return -EPERM; 2708d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2709d2ae842dSAlex Deucher return -EPERM; 2710e098bc96SEvan Quan 27114a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2712e098bc96SEvan Quan if (r < 0) { 27134a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2714e098bc96SEvan Quan return r; 2715e098bc96SEvan Quan } 2716e098bc96SEvan Quan 2717e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 271852d720b1SXiaomeng Hou smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX); 2719e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 27208dfc8c53SDarren Powell } else if (pp_funcs && pp_funcs->get_power_limit) { 27216e58941cSEric Huang pp_funcs->get_power_limit(adev->powerplay.pp_handle, 27226e58941cSEric Huang &limit, &max_limit, true); 27236e58941cSEric Huang size = snprintf(buf, PAGE_SIZE, "%u\n", max_limit * 1000000); 2724e098bc96SEvan Quan } else { 2725e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 2726e098bc96SEvan Quan } 2727e098bc96SEvan Quan 27284a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 27294a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2730e098bc96SEvan Quan 2731e098bc96SEvan Quan return size; 2732e098bc96SEvan Quan } 2733e098bc96SEvan Quan 2734e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 2735e098bc96SEvan Quan struct device_attribute *attr, 2736e098bc96SEvan Quan char *buf) 2737e098bc96SEvan Quan { 2738e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 27398dfc8c53SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 2740ae07970aSXiaomeng Hou int limit_type = to_sensor_dev_attr(attr)->index; 2741ae07970aSXiaomeng Hou uint32_t limit = limit_type << 24; 2742e098bc96SEvan Quan ssize_t size; 2743e098bc96SEvan Quan int r; 2744e098bc96SEvan Quan 274553b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2746e098bc96SEvan Quan return -EPERM; 2747d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2748d2ae842dSAlex Deucher return -EPERM; 2749e098bc96SEvan Quan 27504a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2751e098bc96SEvan Quan if (r < 0) { 27524a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2753e098bc96SEvan Quan return r; 2754e098bc96SEvan Quan } 2755e098bc96SEvan Quan 2756e098bc96SEvan Quan if (is_support_sw_smu(adev)) { 275752d720b1SXiaomeng Hou smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT); 2758e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 27598dfc8c53SDarren Powell } else if (pp_funcs && pp_funcs->get_power_limit) { 27606e58941cSEric Huang pp_funcs->get_power_limit(adev->powerplay.pp_handle, 27616e58941cSEric Huang &limit, NULL, false); 2762e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 2763e098bc96SEvan Quan } else { 2764e098bc96SEvan Quan size = snprintf(buf, PAGE_SIZE, "\n"); 2765e098bc96SEvan Quan } 2766e098bc96SEvan Quan 27674a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 27684a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2769e098bc96SEvan Quan 2770e098bc96SEvan Quan return size; 2771e098bc96SEvan Quan } 2772e098bc96SEvan Quan 27736e58941cSEric Huang static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 27746e58941cSEric Huang struct device_attribute *attr, 27756e58941cSEric Huang char *buf) 27766e58941cSEric Huang { 27776e58941cSEric Huang struct amdgpu_device *adev = dev_get_drvdata(dev); 27786e58941cSEric Huang const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 27796e58941cSEric Huang int limit_type = to_sensor_dev_attr(attr)->index; 27806e58941cSEric Huang uint32_t limit = limit_type << 24; 27816e58941cSEric Huang ssize_t size; 27826e58941cSEric Huang int r; 27836e58941cSEric Huang 27846e58941cSEric Huang if (amdgpu_in_reset(adev)) 27856e58941cSEric Huang return -EPERM; 2786d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2787d2ae842dSAlex Deucher return -EPERM; 27886e58941cSEric Huang 27896e58941cSEric Huang r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 27906e58941cSEric Huang if (r < 0) { 27916e58941cSEric Huang pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 27926e58941cSEric Huang return r; 27936e58941cSEric Huang } 27946e58941cSEric Huang 27956e58941cSEric Huang if (is_support_sw_smu(adev)) { 27966e58941cSEric Huang smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT); 27976e58941cSEric Huang size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 27986e58941cSEric Huang } else if (pp_funcs && pp_funcs->get_power_limit) { 27996e58941cSEric Huang pp_funcs->get_power_limit(adev->powerplay.pp_handle, 28006e58941cSEric Huang &limit, NULL, true); 28016e58941cSEric Huang size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 28026e58941cSEric Huang } else { 28036e58941cSEric Huang size = snprintf(buf, PAGE_SIZE, "\n"); 28046e58941cSEric Huang } 28056e58941cSEric Huang 28066e58941cSEric Huang pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 28076e58941cSEric Huang pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 28086e58941cSEric Huang 28096e58941cSEric Huang return size; 28106e58941cSEric Huang } 2811ae07970aSXiaomeng Hou static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 2812ae07970aSXiaomeng Hou struct device_attribute *attr, 2813ae07970aSXiaomeng Hou char *buf) 2814ae07970aSXiaomeng Hou { 2815ae07970aSXiaomeng Hou int limit_type = to_sensor_dev_attr(attr)->index; 2816ae07970aSXiaomeng Hou 2817a9ca9bb3STian Tao return sysfs_emit(buf, "%s\n", 2818ae07970aSXiaomeng Hou limit_type == SMU_FAST_PPT_LIMIT ? "fastPPT" : "slowPPT"); 2819ae07970aSXiaomeng Hou } 2820e098bc96SEvan Quan 2821e098bc96SEvan Quan static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 2822e098bc96SEvan Quan struct device_attribute *attr, 2823e098bc96SEvan Quan const char *buf, 2824e098bc96SEvan Quan size_t count) 2825e098bc96SEvan Quan { 2826e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 28278dfc8c53SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 2828ae07970aSXiaomeng Hou int limit_type = to_sensor_dev_attr(attr)->index; 2829e098bc96SEvan Quan int err; 2830e098bc96SEvan Quan u32 value; 2831e098bc96SEvan Quan 283253b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2833e098bc96SEvan Quan return -EPERM; 2834d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2835d2ae842dSAlex Deucher return -EPERM; 2836e098bc96SEvan Quan 2837e098bc96SEvan Quan if (amdgpu_sriov_vf(adev)) 2838e098bc96SEvan Quan return -EINVAL; 2839e098bc96SEvan Quan 2840e098bc96SEvan Quan err = kstrtou32(buf, 10, &value); 2841e098bc96SEvan Quan if (err) 2842e098bc96SEvan Quan return err; 2843e098bc96SEvan Quan 2844e098bc96SEvan Quan value = value / 1000000; /* convert to Watt */ 2845ae07970aSXiaomeng Hou value |= limit_type << 24; 2846e098bc96SEvan Quan 28474a580877SLuben Tuikov err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2848e098bc96SEvan Quan if (err < 0) { 28494a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2850e098bc96SEvan Quan return err; 2851e098bc96SEvan Quan } 2852e098bc96SEvan Quan 28538dfc8c53SDarren Powell if (pp_funcs && pp_funcs->set_power_limit) 28548dfc8c53SDarren Powell err = pp_funcs->set_power_limit(adev->powerplay.pp_handle, value); 2855e098bc96SEvan Quan else 2856e098bc96SEvan Quan err = -EINVAL; 2857e098bc96SEvan Quan 28584a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 28594a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2860e098bc96SEvan Quan 2861e098bc96SEvan Quan if (err) 2862e098bc96SEvan Quan return err; 2863e098bc96SEvan Quan 2864e098bc96SEvan Quan return count; 2865e098bc96SEvan Quan } 2866e098bc96SEvan Quan 2867e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 2868e098bc96SEvan Quan struct device_attribute *attr, 2869e098bc96SEvan Quan char *buf) 2870e098bc96SEvan Quan { 2871e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2872e098bc96SEvan Quan uint32_t sclk; 2873e098bc96SEvan Quan int r, size = sizeof(sclk); 2874e098bc96SEvan Quan 287553b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2876e098bc96SEvan Quan return -EPERM; 2877d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2878d2ae842dSAlex Deucher return -EPERM; 2879e098bc96SEvan Quan 28804a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2881e098bc96SEvan Quan if (r < 0) { 28824a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2883e098bc96SEvan Quan return r; 2884e098bc96SEvan Quan } 2885e098bc96SEvan Quan 2886e098bc96SEvan Quan /* get the sclk */ 2887e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 2888e098bc96SEvan Quan (void *)&sclk, &size); 2889e098bc96SEvan Quan 28904a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 28914a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2892e098bc96SEvan Quan 2893e098bc96SEvan Quan if (r) 2894e098bc96SEvan Quan return r; 2895e098bc96SEvan Quan 2896a9ca9bb3STian Tao return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 2897e098bc96SEvan Quan } 2898e098bc96SEvan Quan 2899e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 2900e098bc96SEvan Quan struct device_attribute *attr, 2901e098bc96SEvan Quan char *buf) 2902e098bc96SEvan Quan { 2903a9ca9bb3STian Tao return sysfs_emit(buf, "sclk\n"); 2904e098bc96SEvan Quan } 2905e098bc96SEvan Quan 2906e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 2907e098bc96SEvan Quan struct device_attribute *attr, 2908e098bc96SEvan Quan char *buf) 2909e098bc96SEvan Quan { 2910e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 2911e098bc96SEvan Quan uint32_t mclk; 2912e098bc96SEvan Quan int r, size = sizeof(mclk); 2913e098bc96SEvan Quan 291453b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 2915e098bc96SEvan Quan return -EPERM; 2916d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 2917d2ae842dSAlex Deucher return -EPERM; 2918e098bc96SEvan Quan 29194a580877SLuben Tuikov r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2920e098bc96SEvan Quan if (r < 0) { 29214a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2922e098bc96SEvan Quan return r; 2923e098bc96SEvan Quan } 2924e098bc96SEvan Quan 2925e098bc96SEvan Quan /* get the sclk */ 2926e098bc96SEvan Quan r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 2927e098bc96SEvan Quan (void *)&mclk, &size); 2928e098bc96SEvan Quan 29294a580877SLuben Tuikov pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 29304a580877SLuben Tuikov pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2931e098bc96SEvan Quan 2932e098bc96SEvan Quan if (r) 2933e098bc96SEvan Quan return r; 2934e098bc96SEvan Quan 2935a9ca9bb3STian Tao return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 2936e098bc96SEvan Quan } 2937e098bc96SEvan Quan 2938e098bc96SEvan Quan static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 2939e098bc96SEvan Quan struct device_attribute *attr, 2940e098bc96SEvan Quan char *buf) 2941e098bc96SEvan Quan { 2942a9ca9bb3STian Tao return sysfs_emit(buf, "mclk\n"); 2943e098bc96SEvan Quan } 2944e098bc96SEvan Quan 2945e098bc96SEvan Quan /** 2946e098bc96SEvan Quan * DOC: hwmon 2947e098bc96SEvan Quan * 2948e098bc96SEvan Quan * The amdgpu driver exposes the following sensor interfaces: 2949e098bc96SEvan Quan * 2950e098bc96SEvan Quan * - GPU temperature (via the on-die sensor) 2951e098bc96SEvan Quan * 2952e098bc96SEvan Quan * - GPU voltage 2953e098bc96SEvan Quan * 2954e098bc96SEvan Quan * - Northbridge voltage (APUs only) 2955e098bc96SEvan Quan * 2956e098bc96SEvan Quan * - GPU power 2957e098bc96SEvan Quan * 2958e098bc96SEvan Quan * - GPU fan 2959e098bc96SEvan Quan * 2960e098bc96SEvan Quan * - GPU gfx/compute engine clock 2961e098bc96SEvan Quan * 2962e098bc96SEvan Quan * - GPU memory clock (dGPU only) 2963e098bc96SEvan Quan * 2964e098bc96SEvan Quan * hwmon interfaces for GPU temperature: 2965e098bc96SEvan Quan * 2966e098bc96SEvan Quan * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 2967e098bc96SEvan Quan * - temp2_input and temp3_input are supported on SOC15 dGPUs only 2968e098bc96SEvan Quan * 2969e098bc96SEvan Quan * - temp[1-3]_label: temperature channel label 2970e098bc96SEvan Quan * - temp2_label and temp3_label are supported on SOC15 dGPUs only 2971e098bc96SEvan Quan * 2972e098bc96SEvan Quan * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 2973e098bc96SEvan Quan * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 2974e098bc96SEvan Quan * 2975e098bc96SEvan Quan * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 2976e098bc96SEvan Quan * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 2977e098bc96SEvan Quan * 2978e098bc96SEvan Quan * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 2979e098bc96SEvan Quan * - these are supported on SOC15 dGPUs only 2980e098bc96SEvan Quan * 2981e098bc96SEvan Quan * hwmon interfaces for GPU voltage: 2982e098bc96SEvan Quan * 2983e098bc96SEvan Quan * - in0_input: the voltage on the GPU in millivolts 2984e098bc96SEvan Quan * 2985e098bc96SEvan Quan * - in1_input: the voltage on the Northbridge in millivolts 2986e098bc96SEvan Quan * 2987e098bc96SEvan Quan * hwmon interfaces for GPU power: 2988e098bc96SEvan Quan * 2989e098bc96SEvan Quan * - power1_average: average power used by the GPU in microWatts 2990e098bc96SEvan Quan * 2991e098bc96SEvan Quan * - power1_cap_min: minimum cap supported in microWatts 2992e098bc96SEvan Quan * 2993e098bc96SEvan Quan * - power1_cap_max: maximum cap supported in microWatts 2994e098bc96SEvan Quan * 2995e098bc96SEvan Quan * - power1_cap: selected power cap in microWatts 2996e098bc96SEvan Quan * 2997e098bc96SEvan Quan * hwmon interfaces for GPU fan: 2998e098bc96SEvan Quan * 2999e098bc96SEvan Quan * - pwm1: pulse width modulation fan level (0-255) 3000e098bc96SEvan Quan * 3001e098bc96SEvan Quan * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3002e098bc96SEvan Quan * 3003e098bc96SEvan Quan * - pwm1_min: pulse width modulation fan control minimum level (0) 3004e098bc96SEvan Quan * 3005e098bc96SEvan Quan * - pwm1_max: pulse width modulation fan control maximum level (255) 3006e098bc96SEvan Quan * 3007e5527d8cSBhaskar Chowdhury * - fan1_min: a minimum value Unit: revolution/min (RPM) 3008e098bc96SEvan Quan * 3009e5527d8cSBhaskar Chowdhury * - fan1_max: a maximum value Unit: revolution/max (RPM) 3010e098bc96SEvan Quan * 3011e098bc96SEvan Quan * - fan1_input: fan speed in RPM 3012e098bc96SEvan Quan * 3013e098bc96SEvan Quan * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3014e098bc96SEvan Quan * 3015e098bc96SEvan Quan * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3016e098bc96SEvan Quan * 3017e098bc96SEvan Quan * hwmon interfaces for GPU clocks: 3018e098bc96SEvan Quan * 3019e098bc96SEvan Quan * - freq1_input: the gfx/compute clock in hertz 3020e098bc96SEvan Quan * 3021e098bc96SEvan Quan * - freq2_input: the memory clock in hertz 3022e098bc96SEvan Quan * 3023e098bc96SEvan Quan * You can use hwmon tools like sensors to view this information on your system. 3024e098bc96SEvan Quan * 3025e098bc96SEvan Quan */ 3026e098bc96SEvan Quan 3027e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3028e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3029e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3030e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3031e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3032e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3033e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3034e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3035e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3036e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3037e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3038e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3039e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3040e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3041e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3042e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3043e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3044e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3045e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3046e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3047e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3048e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3049e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3050e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3051e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3052e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3053e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3054e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3055e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3056e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3057e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3058e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 30596e58941cSEric Huang static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3060ae07970aSXiaomeng Hou static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3061ae07970aSXiaomeng Hou static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3062ae07970aSXiaomeng Hou static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3063ae07970aSXiaomeng Hou static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3064ae07970aSXiaomeng Hou static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 30656e58941cSEric Huang static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3066ae07970aSXiaomeng Hou static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3067e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3068e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3069e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3070e098bc96SEvan Quan static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3071e098bc96SEvan Quan 3072e098bc96SEvan Quan static struct attribute *hwmon_attributes[] = { 3073e098bc96SEvan Quan &sensor_dev_attr_temp1_input.dev_attr.attr, 3074e098bc96SEvan Quan &sensor_dev_attr_temp1_crit.dev_attr.attr, 3075e098bc96SEvan Quan &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3076e098bc96SEvan Quan &sensor_dev_attr_temp2_input.dev_attr.attr, 3077e098bc96SEvan Quan &sensor_dev_attr_temp2_crit.dev_attr.attr, 3078e098bc96SEvan Quan &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3079e098bc96SEvan Quan &sensor_dev_attr_temp3_input.dev_attr.attr, 3080e098bc96SEvan Quan &sensor_dev_attr_temp3_crit.dev_attr.attr, 3081e098bc96SEvan Quan &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3082e098bc96SEvan Quan &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3083e098bc96SEvan Quan &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3084e098bc96SEvan Quan &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3085e098bc96SEvan Quan &sensor_dev_attr_temp1_label.dev_attr.attr, 3086e098bc96SEvan Quan &sensor_dev_attr_temp2_label.dev_attr.attr, 3087e098bc96SEvan Quan &sensor_dev_attr_temp3_label.dev_attr.attr, 3088e098bc96SEvan Quan &sensor_dev_attr_pwm1.dev_attr.attr, 3089e098bc96SEvan Quan &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3090e098bc96SEvan Quan &sensor_dev_attr_pwm1_min.dev_attr.attr, 3091e098bc96SEvan Quan &sensor_dev_attr_pwm1_max.dev_attr.attr, 3092e098bc96SEvan Quan &sensor_dev_attr_fan1_input.dev_attr.attr, 3093e098bc96SEvan Quan &sensor_dev_attr_fan1_min.dev_attr.attr, 3094e098bc96SEvan Quan &sensor_dev_attr_fan1_max.dev_attr.attr, 3095e098bc96SEvan Quan &sensor_dev_attr_fan1_target.dev_attr.attr, 3096e098bc96SEvan Quan &sensor_dev_attr_fan1_enable.dev_attr.attr, 3097e098bc96SEvan Quan &sensor_dev_attr_in0_input.dev_attr.attr, 3098e098bc96SEvan Quan &sensor_dev_attr_in0_label.dev_attr.attr, 3099e098bc96SEvan Quan &sensor_dev_attr_in1_input.dev_attr.attr, 3100e098bc96SEvan Quan &sensor_dev_attr_in1_label.dev_attr.attr, 3101e098bc96SEvan Quan &sensor_dev_attr_power1_average.dev_attr.attr, 3102e098bc96SEvan Quan &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3103e098bc96SEvan Quan &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3104e098bc96SEvan Quan &sensor_dev_attr_power1_cap.dev_attr.attr, 31056e58941cSEric Huang &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3106ae07970aSXiaomeng Hou &sensor_dev_attr_power1_label.dev_attr.attr, 3107ae07970aSXiaomeng Hou &sensor_dev_attr_power2_average.dev_attr.attr, 3108ae07970aSXiaomeng Hou &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3109ae07970aSXiaomeng Hou &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3110ae07970aSXiaomeng Hou &sensor_dev_attr_power2_cap.dev_attr.attr, 31116e58941cSEric Huang &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3112ae07970aSXiaomeng Hou &sensor_dev_attr_power2_label.dev_attr.attr, 3113e098bc96SEvan Quan &sensor_dev_attr_freq1_input.dev_attr.attr, 3114e098bc96SEvan Quan &sensor_dev_attr_freq1_label.dev_attr.attr, 3115e098bc96SEvan Quan &sensor_dev_attr_freq2_input.dev_attr.attr, 3116e098bc96SEvan Quan &sensor_dev_attr_freq2_label.dev_attr.attr, 3117e098bc96SEvan Quan NULL 3118e098bc96SEvan Quan }; 3119e098bc96SEvan Quan 3120e098bc96SEvan Quan static umode_t hwmon_attributes_visible(struct kobject *kobj, 3121e098bc96SEvan Quan struct attribute *attr, int index) 3122e098bc96SEvan Quan { 3123e098bc96SEvan Quan struct device *dev = kobj_to_dev(kobj); 3124e098bc96SEvan Quan struct amdgpu_device *adev = dev_get_drvdata(dev); 3125e098bc96SEvan Quan umode_t effective_mode = attr->mode; 3126e098bc96SEvan Quan 3127e098bc96SEvan Quan /* under multi-vf mode, the hwmon attributes are all not supported */ 3128e098bc96SEvan Quan if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 3129e098bc96SEvan Quan return 0; 3130e098bc96SEvan Quan 3131e098bc96SEvan Quan /* there is no fan under pp one vf mode */ 3132e098bc96SEvan Quan if (amdgpu_sriov_is_pp_one_vf(adev) && 3133e098bc96SEvan Quan (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3134e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3135e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3136e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3137e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3138e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3139e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3140e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3141e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3142e098bc96SEvan Quan return 0; 3143e098bc96SEvan Quan 3144e098bc96SEvan Quan /* Skip fan attributes if fan is not present */ 3145e098bc96SEvan Quan if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3146e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3147e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3148e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3149e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3150e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3151e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3152e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3153e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3154e098bc96SEvan Quan return 0; 3155e098bc96SEvan Quan 3156e098bc96SEvan Quan /* Skip fan attributes on APU */ 3157e098bc96SEvan Quan if ((adev->flags & AMD_IS_APU) && 3158e098bc96SEvan Quan (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3159e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3160e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3161e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3162e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3163e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3164e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3165e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3166e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3167e098bc96SEvan Quan return 0; 3168e098bc96SEvan Quan 3169e098bc96SEvan Quan /* Skip crit temp on APU */ 3170e098bc96SEvan Quan if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) && 3171e098bc96SEvan Quan (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3172e098bc96SEvan Quan attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3173e098bc96SEvan Quan return 0; 3174e098bc96SEvan Quan 3175e098bc96SEvan Quan /* Skip limit attributes if DPM is not enabled */ 3176e098bc96SEvan Quan if (!adev->pm.dpm_enabled && 3177e098bc96SEvan Quan (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3178e098bc96SEvan Quan attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3179e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3180e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3181e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3182e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3183e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3184e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3185e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3186e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3187e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3188e098bc96SEvan Quan return 0; 3189e098bc96SEvan Quan 3190e098bc96SEvan Quan if (!is_support_sw_smu(adev)) { 3191e098bc96SEvan Quan /* mask fan attributes if we have no bindings for this asic to expose */ 3192e098bc96SEvan Quan if ((!adev->powerplay.pp_funcs->get_fan_speed_percent && 3193e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3194e098bc96SEvan Quan (!adev->powerplay.pp_funcs->get_fan_control_mode && 3195e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3196e098bc96SEvan Quan effective_mode &= ~S_IRUGO; 3197e098bc96SEvan Quan 3198e098bc96SEvan Quan if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && 3199e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3200e098bc96SEvan Quan (!adev->powerplay.pp_funcs->set_fan_control_mode && 3201e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3202e098bc96SEvan Quan effective_mode &= ~S_IWUSR; 3203e098bc96SEvan Quan } 3204e098bc96SEvan Quan 3205ae07970aSXiaomeng Hou if (((adev->family == AMDGPU_FAMILY_SI) || 3206ae07970aSXiaomeng Hou ((adev->flags & AMD_IS_APU) && 3207ae07970aSXiaomeng Hou (adev->asic_type != CHIP_VANGOGH))) && /* not implemented yet */ 3208367deb67SAlex Deucher (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3209e098bc96SEvan Quan attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr|| 32106e58941cSEric Huang attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 32116e58941cSEric Huang attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3212e098bc96SEvan Quan return 0; 3213e098bc96SEvan Quan 3214367deb67SAlex Deucher if (((adev->family == AMDGPU_FAMILY_SI) || 3215367deb67SAlex Deucher ((adev->flags & AMD_IS_APU) && 3216367deb67SAlex Deucher (adev->asic_type < CHIP_RENOIR))) && /* not implemented yet */ 3217367deb67SAlex Deucher (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3218367deb67SAlex Deucher return 0; 3219367deb67SAlex Deucher 3220e098bc96SEvan Quan if (!is_support_sw_smu(adev)) { 3221e098bc96SEvan Quan /* hide max/min values if we can't both query and manage the fan */ 3222e098bc96SEvan Quan if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && 3223e098bc96SEvan Quan !adev->powerplay.pp_funcs->get_fan_speed_percent) && 3224e098bc96SEvan Quan (!adev->powerplay.pp_funcs->set_fan_speed_rpm && 3225e098bc96SEvan Quan !adev->powerplay.pp_funcs->get_fan_speed_rpm) && 3226e098bc96SEvan Quan (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3227e098bc96SEvan Quan attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3228e098bc96SEvan Quan return 0; 3229e098bc96SEvan Quan 3230e098bc96SEvan Quan if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm && 3231e098bc96SEvan Quan !adev->powerplay.pp_funcs->get_fan_speed_rpm) && 3232e098bc96SEvan Quan (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3233e098bc96SEvan Quan attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3234e098bc96SEvan Quan return 0; 3235e098bc96SEvan Quan } 3236e098bc96SEvan Quan 3237e098bc96SEvan Quan if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3238e098bc96SEvan Quan adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */ 3239e098bc96SEvan Quan (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3240e098bc96SEvan Quan attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3241e098bc96SEvan Quan return 0; 3242e098bc96SEvan Quan 3243e098bc96SEvan Quan /* only APUs have vddnb */ 3244e098bc96SEvan Quan if (!(adev->flags & AMD_IS_APU) && 3245e098bc96SEvan Quan (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3246e098bc96SEvan Quan attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3247e098bc96SEvan Quan return 0; 3248e098bc96SEvan Quan 3249e098bc96SEvan Quan /* no mclk on APUs */ 3250e098bc96SEvan Quan if ((adev->flags & AMD_IS_APU) && 3251e098bc96SEvan Quan (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3252e098bc96SEvan Quan attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3253e098bc96SEvan Quan return 0; 3254e098bc96SEvan Quan 3255e098bc96SEvan Quan /* only SOC15 dGPUs support hotspot and mem temperatures */ 3256e098bc96SEvan Quan if (((adev->flags & AMD_IS_APU) || 3257e098bc96SEvan Quan adev->asic_type < CHIP_VEGA10) && 3258e098bc96SEvan Quan (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3259e098bc96SEvan Quan attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3260e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_crit.dev_attr.attr || 3261e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3262e098bc96SEvan Quan attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3263e098bc96SEvan Quan attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3264e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr || 3265e098bc96SEvan Quan attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3266e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3267e098bc96SEvan Quan attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3268e098bc96SEvan Quan attr == &sensor_dev_attr_temp3_label.dev_attr.attr)) 3269e098bc96SEvan Quan return 0; 3270e098bc96SEvan Quan 3271ae07970aSXiaomeng Hou /* only Vangogh has fast PPT limit and power labels */ 3272ae07970aSXiaomeng Hou if (!(adev->asic_type == CHIP_VANGOGH) && 3273ae07970aSXiaomeng Hou (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3274ae07970aSXiaomeng Hou attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3275ae07970aSXiaomeng Hou attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3276ae07970aSXiaomeng Hou attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 32776e58941cSEric Huang attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3278ae07970aSXiaomeng Hou attr == &sensor_dev_attr_power2_label.dev_attr.attr || 3279ae07970aSXiaomeng Hou attr == &sensor_dev_attr_power1_label.dev_attr.attr)) 3280ae07970aSXiaomeng Hou return 0; 3281ae07970aSXiaomeng Hou 3282e098bc96SEvan Quan return effective_mode; 3283e098bc96SEvan Quan } 3284e098bc96SEvan Quan 3285e098bc96SEvan Quan static const struct attribute_group hwmon_attrgroup = { 3286e098bc96SEvan Quan .attrs = hwmon_attributes, 3287e098bc96SEvan Quan .is_visible = hwmon_attributes_visible, 3288e098bc96SEvan Quan }; 3289e098bc96SEvan Quan 3290e098bc96SEvan Quan static const struct attribute_group *hwmon_groups[] = { 3291e098bc96SEvan Quan &hwmon_attrgroup, 3292e098bc96SEvan Quan NULL 3293e098bc96SEvan Quan }; 3294e098bc96SEvan Quan 3295e098bc96SEvan Quan int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 3296e098bc96SEvan Quan { 3297e098bc96SEvan Quan int ret; 3298e098bc96SEvan Quan uint32_t mask = 0; 3299e098bc96SEvan Quan 3300e098bc96SEvan Quan if (adev->pm.sysfs_initialized) 3301e098bc96SEvan Quan return 0; 3302e098bc96SEvan Quan 3303e098bc96SEvan Quan if (adev->pm.dpm_enabled == 0) 3304e098bc96SEvan Quan return 0; 3305e098bc96SEvan Quan 3306e098bc96SEvan Quan INIT_LIST_HEAD(&adev->pm.pm_attr_list); 3307e098bc96SEvan Quan 3308e098bc96SEvan Quan adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 3309e098bc96SEvan Quan DRIVER_NAME, adev, 3310e098bc96SEvan Quan hwmon_groups); 3311e098bc96SEvan Quan if (IS_ERR(adev->pm.int_hwmon_dev)) { 3312e098bc96SEvan Quan ret = PTR_ERR(adev->pm.int_hwmon_dev); 3313e098bc96SEvan Quan dev_err(adev->dev, 3314e098bc96SEvan Quan "Unable to register hwmon device: %d\n", ret); 3315e098bc96SEvan Quan return ret; 3316e098bc96SEvan Quan } 3317e098bc96SEvan Quan 3318e098bc96SEvan Quan switch (amdgpu_virt_get_sriov_vf_mode(adev)) { 3319e098bc96SEvan Quan case SRIOV_VF_MODE_ONE_VF: 3320e098bc96SEvan Quan mask = ATTR_FLAG_ONEVF; 3321e098bc96SEvan Quan break; 3322e098bc96SEvan Quan case SRIOV_VF_MODE_MULTI_VF: 3323e098bc96SEvan Quan mask = 0; 3324e098bc96SEvan Quan break; 3325e098bc96SEvan Quan case SRIOV_VF_MODE_BARE_METAL: 3326e098bc96SEvan Quan default: 3327e098bc96SEvan Quan mask = ATTR_FLAG_MASK_ALL; 3328e098bc96SEvan Quan break; 3329e098bc96SEvan Quan } 3330e098bc96SEvan Quan 3331e098bc96SEvan Quan ret = amdgpu_device_attr_create_groups(adev, 3332e098bc96SEvan Quan amdgpu_device_attrs, 3333e098bc96SEvan Quan ARRAY_SIZE(amdgpu_device_attrs), 3334e098bc96SEvan Quan mask, 3335e098bc96SEvan Quan &adev->pm.pm_attr_list); 3336e098bc96SEvan Quan if (ret) 3337e098bc96SEvan Quan return ret; 3338e098bc96SEvan Quan 3339e098bc96SEvan Quan adev->pm.sysfs_initialized = true; 3340e098bc96SEvan Quan 3341e098bc96SEvan Quan return 0; 3342e098bc96SEvan Quan } 3343e098bc96SEvan Quan 3344e098bc96SEvan Quan void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 3345e098bc96SEvan Quan { 3346e098bc96SEvan Quan if (adev->pm.dpm_enabled == 0) 3347e098bc96SEvan Quan return; 3348e098bc96SEvan Quan 3349e098bc96SEvan Quan if (adev->pm.int_hwmon_dev) 3350e098bc96SEvan Quan hwmon_device_unregister(adev->pm.int_hwmon_dev); 3351e098bc96SEvan Quan 3352e098bc96SEvan Quan amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 3353e098bc96SEvan Quan } 3354e098bc96SEvan Quan 3355e098bc96SEvan Quan /* 3356e098bc96SEvan Quan * Debugfs info 3357e098bc96SEvan Quan */ 3358e098bc96SEvan Quan #if defined(CONFIG_DEBUG_FS) 3359e098bc96SEvan Quan 3360517cb957SHuang Rui static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 3361517cb957SHuang Rui struct amdgpu_device *adev) { 3362517cb957SHuang Rui uint16_t *p_val; 3363517cb957SHuang Rui uint32_t size; 3364517cb957SHuang Rui int i; 3365517cb957SHuang Rui 3366517cb957SHuang Rui if (is_support_cclk_dpm(adev)) { 33674aef0ebcSHuang Rui p_val = kcalloc(adev->smu.cpu_core_num, sizeof(uint16_t), 3368517cb957SHuang Rui GFP_KERNEL); 3369517cb957SHuang Rui 3370517cb957SHuang Rui if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 3371517cb957SHuang Rui (void *)p_val, &size)) { 33724aef0ebcSHuang Rui for (i = 0; i < adev->smu.cpu_core_num; i++) 3373517cb957SHuang Rui seq_printf(m, "\t%u MHz (CPU%d)\n", 3374517cb957SHuang Rui *(p_val + i), i); 3375517cb957SHuang Rui } 3376517cb957SHuang Rui 3377517cb957SHuang Rui kfree(p_val); 3378517cb957SHuang Rui } 3379517cb957SHuang Rui } 3380517cb957SHuang Rui 3381e098bc96SEvan Quan static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 3382e098bc96SEvan Quan { 3383e098bc96SEvan Quan uint32_t value; 3384800c53d6SXiaojian Du uint64_t value64 = 0; 3385e098bc96SEvan Quan uint32_t query = 0; 3386e098bc96SEvan Quan int size; 3387e098bc96SEvan Quan 3388e098bc96SEvan Quan /* GPU Clocks */ 3389e098bc96SEvan Quan size = sizeof(value); 3390e098bc96SEvan Quan seq_printf(m, "GFX Clocks and Power:\n"); 3391517cb957SHuang Rui 3392517cb957SHuang Rui amdgpu_debugfs_prints_cpu_info(m, adev); 3393517cb957SHuang Rui 3394e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 3395e098bc96SEvan Quan seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 3396e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 3397e098bc96SEvan Quan seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 3398e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 3399e098bc96SEvan Quan seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 3400e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 3401e098bc96SEvan Quan seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 3402e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 3403e098bc96SEvan Quan seq_printf(m, "\t%u mV (VDDGFX)\n", value); 3404e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 3405e098bc96SEvan Quan seq_printf(m, "\t%u mV (VDDNB)\n", value); 3406e098bc96SEvan Quan size = sizeof(uint32_t); 3407e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) 3408e098bc96SEvan Quan seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); 3409e098bc96SEvan Quan size = sizeof(value); 3410e098bc96SEvan Quan seq_printf(m, "\n"); 3411e098bc96SEvan Quan 3412e098bc96SEvan Quan /* GPU Temp */ 3413e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 3414e098bc96SEvan Quan seq_printf(m, "GPU Temperature: %u C\n", value/1000); 3415e098bc96SEvan Quan 3416e098bc96SEvan Quan /* GPU Load */ 3417e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 3418e098bc96SEvan Quan seq_printf(m, "GPU Load: %u %%\n", value); 3419e098bc96SEvan Quan /* MEM Load */ 3420e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 3421e098bc96SEvan Quan seq_printf(m, "MEM Load: %u %%\n", value); 3422e098bc96SEvan Quan 3423e098bc96SEvan Quan seq_printf(m, "\n"); 3424e098bc96SEvan Quan 3425e098bc96SEvan Quan /* SMC feature mask */ 3426e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 3427e098bc96SEvan Quan seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 3428e098bc96SEvan Quan 3429e098bc96SEvan Quan if (adev->asic_type > CHIP_VEGA20) { 3430e098bc96SEvan Quan /* VCN clocks */ 3431e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 3432e098bc96SEvan Quan if (!value) { 3433e098bc96SEvan Quan seq_printf(m, "VCN: Disabled\n"); 3434e098bc96SEvan Quan } else { 3435e098bc96SEvan Quan seq_printf(m, "VCN: Enabled\n"); 3436e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3437e098bc96SEvan Quan seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3438e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3439e098bc96SEvan Quan seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3440e098bc96SEvan Quan } 3441e098bc96SEvan Quan } 3442e098bc96SEvan Quan seq_printf(m, "\n"); 3443e098bc96SEvan Quan } else { 3444e098bc96SEvan Quan /* UVD clocks */ 3445e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 3446e098bc96SEvan Quan if (!value) { 3447e098bc96SEvan Quan seq_printf(m, "UVD: Disabled\n"); 3448e098bc96SEvan Quan } else { 3449e098bc96SEvan Quan seq_printf(m, "UVD: Enabled\n"); 3450e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3451e098bc96SEvan Quan seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3452e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3453e098bc96SEvan Quan seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3454e098bc96SEvan Quan } 3455e098bc96SEvan Quan } 3456e098bc96SEvan Quan seq_printf(m, "\n"); 3457e098bc96SEvan Quan 3458e098bc96SEvan Quan /* VCE clocks */ 3459e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 3460e098bc96SEvan Quan if (!value) { 3461e098bc96SEvan Quan seq_printf(m, "VCE: Disabled\n"); 3462e098bc96SEvan Quan } else { 3463e098bc96SEvan Quan seq_printf(m, "VCE: Enabled\n"); 3464e098bc96SEvan Quan if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 3465e098bc96SEvan Quan seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 3466e098bc96SEvan Quan } 3467e098bc96SEvan Quan } 3468e098bc96SEvan Quan } 3469e098bc96SEvan Quan 3470e098bc96SEvan Quan return 0; 3471e098bc96SEvan Quan } 3472e098bc96SEvan Quan 3473e098bc96SEvan Quan static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags) 3474e098bc96SEvan Quan { 3475e098bc96SEvan Quan int i; 3476e098bc96SEvan Quan 3477e098bc96SEvan Quan for (i = 0; clocks[i].flag; i++) 3478e098bc96SEvan Quan seq_printf(m, "\t%s: %s\n", clocks[i].name, 3479e098bc96SEvan Quan (flags & clocks[i].flag) ? "On" : "Off"); 3480e098bc96SEvan Quan } 3481e098bc96SEvan Quan 3482373720f7SNirmoy Das static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 3483e098bc96SEvan Quan { 3484373720f7SNirmoy Das struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3485373720f7SNirmoy Das struct drm_device *dev = adev_to_drm(adev); 3486e098bc96SEvan Quan u32 flags = 0; 3487e098bc96SEvan Quan int r; 3488e098bc96SEvan Quan 348953b3f8f4SDennis Li if (amdgpu_in_reset(adev)) 3490e098bc96SEvan Quan return -EPERM; 3491d2ae842dSAlex Deucher if (adev->in_suspend && !adev->in_runpm) 3492d2ae842dSAlex Deucher return -EPERM; 3493e098bc96SEvan Quan 3494e098bc96SEvan Quan r = pm_runtime_get_sync(dev->dev); 3495e098bc96SEvan Quan if (r < 0) { 3496e098bc96SEvan Quan pm_runtime_put_autosuspend(dev->dev); 3497e098bc96SEvan Quan return r; 3498e098bc96SEvan Quan } 3499e098bc96SEvan Quan 3500e098bc96SEvan Quan if (!adev->pm.dpm_enabled) { 3501e098bc96SEvan Quan seq_printf(m, "dpm not enabled\n"); 3502e098bc96SEvan Quan pm_runtime_mark_last_busy(dev->dev); 3503e098bc96SEvan Quan pm_runtime_put_autosuspend(dev->dev); 3504e098bc96SEvan Quan return 0; 3505e098bc96SEvan Quan } 3506e098bc96SEvan Quan 3507e098bc96SEvan Quan if (!is_support_sw_smu(adev) && 3508e098bc96SEvan Quan adev->powerplay.pp_funcs->debugfs_print_current_performance_level) { 3509e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 3510e098bc96SEvan Quan if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) 3511e098bc96SEvan Quan adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m); 3512e098bc96SEvan Quan else 3513e098bc96SEvan Quan seq_printf(m, "Debugfs support not implemented for this asic\n"); 3514e098bc96SEvan Quan mutex_unlock(&adev->pm.mutex); 3515e098bc96SEvan Quan r = 0; 3516e098bc96SEvan Quan } else { 3517e098bc96SEvan Quan r = amdgpu_debugfs_pm_info_pp(m, adev); 3518e098bc96SEvan Quan } 3519e098bc96SEvan Quan if (r) 3520e098bc96SEvan Quan goto out; 3521e098bc96SEvan Quan 3522e098bc96SEvan Quan amdgpu_device_ip_get_clockgating_state(adev, &flags); 3523e098bc96SEvan Quan 3524e098bc96SEvan Quan seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); 3525e098bc96SEvan Quan amdgpu_parse_cg_state(m, flags); 3526e098bc96SEvan Quan seq_printf(m, "\n"); 3527e098bc96SEvan Quan 3528e098bc96SEvan Quan out: 3529e098bc96SEvan Quan pm_runtime_mark_last_busy(dev->dev); 3530e098bc96SEvan Quan pm_runtime_put_autosuspend(dev->dev); 3531e098bc96SEvan Quan 3532e098bc96SEvan Quan return r; 3533e098bc96SEvan Quan } 3534e098bc96SEvan Quan 3535373720f7SNirmoy Das DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 3536373720f7SNirmoy Das 3537*27ebf21fSLijo Lazar /* 3538*27ebf21fSLijo Lazar * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 3539*27ebf21fSLijo Lazar * 3540*27ebf21fSLijo Lazar * Reads debug memory region allocated to PMFW 3541*27ebf21fSLijo Lazar */ 3542*27ebf21fSLijo Lazar static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 3543*27ebf21fSLijo Lazar size_t size, loff_t *pos) 3544*27ebf21fSLijo Lazar { 3545*27ebf21fSLijo Lazar struct amdgpu_device *adev = file_inode(f)->i_private; 3546*27ebf21fSLijo Lazar const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 3547*27ebf21fSLijo Lazar void *pp_handle = adev->powerplay.pp_handle; 3548*27ebf21fSLijo Lazar size_t smu_prv_buf_size; 3549*27ebf21fSLijo Lazar void *smu_prv_buf; 3550*27ebf21fSLijo Lazar 3551*27ebf21fSLijo Lazar if (amdgpu_in_reset(adev)) 3552*27ebf21fSLijo Lazar return -EPERM; 3553*27ebf21fSLijo Lazar if (adev->in_suspend && !adev->in_runpm) 3554*27ebf21fSLijo Lazar return -EPERM; 3555*27ebf21fSLijo Lazar 3556*27ebf21fSLijo Lazar if (pp_funcs && pp_funcs->get_smu_prv_buf_details) 3557*27ebf21fSLijo Lazar pp_funcs->get_smu_prv_buf_details(pp_handle, &smu_prv_buf, 3558*27ebf21fSLijo Lazar &smu_prv_buf_size); 3559*27ebf21fSLijo Lazar else 3560*27ebf21fSLijo Lazar return -ENOSYS; 3561*27ebf21fSLijo Lazar 3562*27ebf21fSLijo Lazar if (!smu_prv_buf || !smu_prv_buf_size) 3563*27ebf21fSLijo Lazar return -EINVAL; 3564*27ebf21fSLijo Lazar 3565*27ebf21fSLijo Lazar return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 3566*27ebf21fSLijo Lazar smu_prv_buf_size); 3567*27ebf21fSLijo Lazar } 3568*27ebf21fSLijo Lazar 3569*27ebf21fSLijo Lazar static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 3570*27ebf21fSLijo Lazar .owner = THIS_MODULE, 3571*27ebf21fSLijo Lazar .open = simple_open, 3572*27ebf21fSLijo Lazar .read = amdgpu_pm_prv_buffer_read, 3573*27ebf21fSLijo Lazar .llseek = default_llseek, 3574*27ebf21fSLijo Lazar }; 3575*27ebf21fSLijo Lazar 3576e098bc96SEvan Quan #endif 3577e098bc96SEvan Quan 3578373720f7SNirmoy Das void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 3579e098bc96SEvan Quan { 3580e098bc96SEvan Quan #if defined(CONFIG_DEBUG_FS) 3581373720f7SNirmoy Das struct drm_minor *minor = adev_to_drm(adev)->primary; 3582373720f7SNirmoy Das struct dentry *root = minor->debugfs_root; 3583373720f7SNirmoy Das 3584373720f7SNirmoy Das debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 3585373720f7SNirmoy Das &amdgpu_debugfs_pm_info_fops); 3586373720f7SNirmoy Das 3587*27ebf21fSLijo Lazar if (adev->pm.smu_prv_buffer_size > 0) 3588*27ebf21fSLijo Lazar debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 3589*27ebf21fSLijo Lazar adev, 3590*27ebf21fSLijo Lazar &amdgpu_debugfs_pm_prv_buffer_fops, 3591*27ebf21fSLijo Lazar adev->pm.smu_prv_buffer_size); 3592e098bc96SEvan Quan #endif 3593e098bc96SEvan Quan } 3594