1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include "amdgpu.h" 26 #include "amdgpu_atombios.h" 27 #include "amdgpu_i2c.h" 28 #include "amdgpu_dpm.h" 29 #include "atom.h" 30 #include "amd_pcie.h" 31 #include "amdgpu_display.h" 32 #include "hwmgr.h" 33 #include <linux/power_supply.h> 34 #include "amdgpu_smu.h" 35 36 #define amdgpu_dpm_enable_bapm(adev, e) \ 37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 38 39 #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev)) 40 41 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 42 { 43 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 44 int ret = 0; 45 46 if (!pp_funcs->get_sclk) 47 return 0; 48 49 mutex_lock(&adev->pm.mutex); 50 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, 51 low); 52 mutex_unlock(&adev->pm.mutex); 53 54 return ret; 55 } 56 57 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) 58 { 59 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 60 int ret = 0; 61 62 if (!pp_funcs->get_mclk) 63 return 0; 64 65 mutex_lock(&adev->pm.mutex); 66 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, 67 low); 68 mutex_unlock(&adev->pm.mutex); 69 70 return ret; 71 } 72 73 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, 74 uint32_t block_type, 75 bool gate, 76 int inst) 77 { 78 int ret = 0; 79 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 80 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; 81 bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; 82 83 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && 84 (!is_vcn || adev->vcn.num_vcn_inst == 1)) { 85 dev_dbg(adev->dev, "IP block%d already in the target %s state!", 86 block_type, gate ? "gate" : "ungate"); 87 return 0; 88 } 89 90 mutex_lock(&adev->pm.mutex); 91 92 switch (block_type) { 93 case AMD_IP_BLOCK_TYPE_UVD: 94 case AMD_IP_BLOCK_TYPE_VCE: 95 case AMD_IP_BLOCK_TYPE_GFX: 96 case AMD_IP_BLOCK_TYPE_SDMA: 97 case AMD_IP_BLOCK_TYPE_JPEG: 98 case AMD_IP_BLOCK_TYPE_GMC: 99 case AMD_IP_BLOCK_TYPE_ACP: 100 case AMD_IP_BLOCK_TYPE_VPE: 101 case AMD_IP_BLOCK_TYPE_ISP: 102 if (pp_funcs && pp_funcs->set_powergating_by_smu) 103 ret = (pp_funcs->set_powergating_by_smu( 104 (adev)->powerplay.pp_handle, block_type, gate, 0)); 105 break; 106 case AMD_IP_BLOCK_TYPE_VCN: 107 if (pp_funcs && pp_funcs->set_powergating_by_smu) 108 ret = (pp_funcs->set_powergating_by_smu( 109 (adev)->powerplay.pp_handle, block_type, gate, inst)); 110 break; 111 default: 112 break; 113 } 114 115 if (!ret) 116 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); 117 118 mutex_unlock(&adev->pm.mutex); 119 120 return ret; 121 } 122 123 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) 124 { 125 struct smu_context *smu = adev->powerplay.pp_handle; 126 int ret = -EOPNOTSUPP; 127 128 mutex_lock(&adev->pm.mutex); 129 ret = smu_set_gfx_power_up_by_imu(smu); 130 mutex_unlock(&adev->pm.mutex); 131 132 msleep(10); 133 134 return ret; 135 } 136 137 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) 138 { 139 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 140 void *pp_handle = adev->powerplay.pp_handle; 141 int ret = 0; 142 143 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 144 return -ENOENT; 145 146 mutex_lock(&adev->pm.mutex); 147 148 /* enter BACO state */ 149 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 150 151 mutex_unlock(&adev->pm.mutex); 152 153 return ret; 154 } 155 156 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) 157 { 158 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 159 void *pp_handle = adev->powerplay.pp_handle; 160 int ret = 0; 161 162 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 163 return -ENOENT; 164 165 mutex_lock(&adev->pm.mutex); 166 167 /* exit BACO state */ 168 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 169 170 mutex_unlock(&adev->pm.mutex); 171 172 return ret; 173 } 174 175 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 176 enum pp_mp1_state mp1_state) 177 { 178 int ret = 0; 179 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 180 181 if (mp1_state == PP_MP1_STATE_FLR) { 182 /* VF lost access to SMU */ 183 if (amdgpu_sriov_vf(adev)) 184 adev->pm.dpm_enabled = false; 185 } else if (pp_funcs && pp_funcs->set_mp1_state) { 186 mutex_lock(&adev->pm.mutex); 187 188 ret = pp_funcs->set_mp1_state( 189 adev->powerplay.pp_handle, 190 mp1_state); 191 192 mutex_unlock(&adev->pm.mutex); 193 } 194 195 return ret; 196 } 197 198 int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en) 199 { 200 int ret = 0; 201 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 202 203 if (pp_funcs && pp_funcs->notify_rlc_state) { 204 mutex_lock(&adev->pm.mutex); 205 206 ret = pp_funcs->notify_rlc_state( 207 adev->powerplay.pp_handle, 208 en); 209 210 mutex_unlock(&adev->pm.mutex); 211 } 212 213 return ret; 214 } 215 216 int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) 217 { 218 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 219 void *pp_handle = adev->powerplay.pp_handle; 220 int ret; 221 222 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) 223 return 0; 224 /* Don't use baco for reset in S3. 225 * This is a workaround for some platforms 226 * where entering BACO during suspend 227 * seems to cause reboots or hangs. 228 * This might be related to the fact that BACO controls 229 * power to the whole GPU including devices like audio and USB. 230 * Powering down/up everything may adversely affect these other 231 * devices. Needs more investigation. 232 */ 233 if (adev->in_s3) 234 return 0; 235 236 mutex_lock(&adev->pm.mutex); 237 238 ret = pp_funcs->get_asic_baco_capability(pp_handle); 239 240 mutex_unlock(&adev->pm.mutex); 241 242 return ret; 243 } 244 245 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) 246 { 247 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 248 void *pp_handle = adev->powerplay.pp_handle; 249 int ret = 0; 250 251 if (!pp_funcs || !pp_funcs->asic_reset_mode_2) 252 return -ENOENT; 253 254 mutex_lock(&adev->pm.mutex); 255 256 ret = pp_funcs->asic_reset_mode_2(pp_handle); 257 258 mutex_unlock(&adev->pm.mutex); 259 260 return ret; 261 } 262 263 int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) 264 { 265 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 266 void *pp_handle = adev->powerplay.pp_handle; 267 int ret = 0; 268 269 if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) 270 return -ENOENT; 271 272 mutex_lock(&adev->pm.mutex); 273 274 ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); 275 276 mutex_unlock(&adev->pm.mutex); 277 278 return ret; 279 } 280 281 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) 282 { 283 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 284 void *pp_handle = adev->powerplay.pp_handle; 285 int ret = 0; 286 287 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 288 return -ENOENT; 289 290 mutex_lock(&adev->pm.mutex); 291 292 /* enter BACO state */ 293 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 294 if (ret) 295 goto out; 296 297 /* exit BACO state */ 298 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 299 300 out: 301 mutex_unlock(&adev->pm.mutex); 302 return ret; 303 } 304 305 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 306 { 307 struct smu_context *smu = adev->powerplay.pp_handle; 308 bool support_mode1_reset = false; 309 310 if (is_support_sw_smu(adev)) { 311 mutex_lock(&adev->pm.mutex); 312 support_mode1_reset = smu_mode1_reset_is_support(smu); 313 mutex_unlock(&adev->pm.mutex); 314 } 315 316 return support_mode1_reset; 317 } 318 319 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) 320 { 321 struct smu_context *smu = adev->powerplay.pp_handle; 322 int ret = -EOPNOTSUPP; 323 324 if (is_support_sw_smu(adev)) { 325 mutex_lock(&adev->pm.mutex); 326 ret = smu_mode1_reset(smu); 327 mutex_unlock(&adev->pm.mutex); 328 } 329 330 return ret; 331 } 332 333 bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) 334 { 335 struct smu_context *smu = adev->powerplay.pp_handle; 336 bool support_link_reset = false; 337 338 if (is_support_sw_smu(adev)) { 339 mutex_lock(&adev->pm.mutex); 340 support_link_reset = smu_link_reset_is_support(smu); 341 mutex_unlock(&adev->pm.mutex); 342 } 343 344 return support_link_reset; 345 } 346 347 int amdgpu_dpm_link_reset(struct amdgpu_device *adev) 348 { 349 struct smu_context *smu = adev->powerplay.pp_handle; 350 int ret = -EOPNOTSUPP; 351 352 if (is_support_sw_smu(adev)) { 353 mutex_lock(&adev->pm.mutex); 354 ret = smu_link_reset(smu); 355 mutex_unlock(&adev->pm.mutex); 356 } 357 358 return ret; 359 } 360 361 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 362 enum PP_SMC_POWER_PROFILE type, 363 bool en) 364 { 365 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 366 int ret = 0; 367 368 if (amdgpu_sriov_vf(adev)) 369 return 0; 370 371 if (pp_funcs && pp_funcs->switch_power_profile) { 372 mutex_lock(&adev->pm.mutex); 373 ret = pp_funcs->switch_power_profile( 374 adev->powerplay.pp_handle, type, en); 375 mutex_unlock(&adev->pm.mutex); 376 } 377 378 return ret; 379 } 380 381 int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, 382 bool pause) 383 { 384 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 385 int ret = 0; 386 387 if (amdgpu_sriov_vf(adev)) 388 return 0; 389 390 if (pp_funcs && pp_funcs->pause_power_profile) { 391 mutex_lock(&adev->pm.mutex); 392 ret = pp_funcs->pause_power_profile( 393 adev->powerplay.pp_handle, pause); 394 mutex_unlock(&adev->pm.mutex); 395 } 396 397 return ret; 398 } 399 400 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 401 uint32_t pstate) 402 { 403 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 404 int ret = 0; 405 406 if (pp_funcs && pp_funcs->set_xgmi_pstate) { 407 mutex_lock(&adev->pm.mutex); 408 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, 409 pstate); 410 mutex_unlock(&adev->pm.mutex); 411 } 412 413 return ret; 414 } 415 416 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 417 uint32_t cstate) 418 { 419 int ret = 0; 420 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 421 void *pp_handle = adev->powerplay.pp_handle; 422 423 if (pp_funcs && pp_funcs->set_df_cstate) { 424 mutex_lock(&adev->pm.mutex); 425 ret = pp_funcs->set_df_cstate(pp_handle, cstate); 426 mutex_unlock(&adev->pm.mutex); 427 } 428 429 return ret; 430 } 431 432 ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, 433 enum pp_pm_policy p_type, char *buf) 434 { 435 struct smu_context *smu = adev->powerplay.pp_handle; 436 int ret = -EOPNOTSUPP; 437 438 if (is_support_sw_smu(adev)) { 439 mutex_lock(&adev->pm.mutex); 440 ret = smu_get_pm_policy_info(smu, p_type, buf); 441 mutex_unlock(&adev->pm.mutex); 442 } 443 444 return ret; 445 } 446 447 int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, 448 int policy_level) 449 { 450 struct smu_context *smu = adev->powerplay.pp_handle; 451 int ret = -EOPNOTSUPP; 452 453 if (is_support_sw_smu(adev)) { 454 mutex_lock(&adev->pm.mutex); 455 ret = smu_set_pm_policy(smu, policy_type, policy_level); 456 mutex_unlock(&adev->pm.mutex); 457 } 458 459 return ret; 460 } 461 462 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) 463 { 464 void *pp_handle = adev->powerplay.pp_handle; 465 const struct amd_pm_funcs *pp_funcs = 466 adev->powerplay.pp_funcs; 467 int ret = 0; 468 469 if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { 470 mutex_lock(&adev->pm.mutex); 471 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); 472 mutex_unlock(&adev->pm.mutex); 473 } 474 475 return ret; 476 } 477 478 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 479 uint32_t msg_id) 480 { 481 void *pp_handle = adev->powerplay.pp_handle; 482 const struct amd_pm_funcs *pp_funcs = 483 adev->powerplay.pp_funcs; 484 int ret = 0; 485 486 if (pp_funcs && pp_funcs->set_clockgating_by_smu) { 487 mutex_lock(&adev->pm.mutex); 488 ret = pp_funcs->set_clockgating_by_smu(pp_handle, 489 msg_id); 490 mutex_unlock(&adev->pm.mutex); 491 } 492 493 return ret; 494 } 495 496 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 497 bool acquire) 498 { 499 void *pp_handle = adev->powerplay.pp_handle; 500 const struct amd_pm_funcs *pp_funcs = 501 adev->powerplay.pp_funcs; 502 int ret = -EOPNOTSUPP; 503 504 if (pp_funcs && pp_funcs->smu_i2c_bus_access) { 505 mutex_lock(&adev->pm.mutex); 506 ret = pp_funcs->smu_i2c_bus_access(pp_handle, 507 acquire); 508 mutex_unlock(&adev->pm.mutex); 509 } 510 511 return ret; 512 } 513 514 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) 515 { 516 if (adev->pm.dpm_enabled) { 517 mutex_lock(&adev->pm.mutex); 518 if (power_supply_is_system_supplied() > 0) 519 adev->pm.ac_power = true; 520 else 521 adev->pm.ac_power = false; 522 523 if (adev->powerplay.pp_funcs && 524 adev->powerplay.pp_funcs->enable_bapm) 525 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); 526 527 if (is_support_sw_smu(adev)) 528 smu_set_ac_dc(adev->powerplay.pp_handle); 529 530 mutex_unlock(&adev->pm.mutex); 531 } 532 } 533 534 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 535 void *data, uint32_t *size) 536 { 537 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 538 int ret = -EINVAL; 539 540 if (!data || !size) 541 return -EINVAL; 542 543 if (pp_funcs && pp_funcs->read_sensor) { 544 mutex_lock(&adev->pm.mutex); 545 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, 546 sensor, 547 data, 548 size); 549 mutex_unlock(&adev->pm.mutex); 550 } 551 552 return ret; 553 } 554 555 int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) 556 { 557 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 558 int ret = -EOPNOTSUPP; 559 560 if (pp_funcs && pp_funcs->get_apu_thermal_limit) { 561 mutex_lock(&adev->pm.mutex); 562 ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); 563 mutex_unlock(&adev->pm.mutex); 564 } 565 566 return ret; 567 } 568 569 int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) 570 { 571 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 572 int ret = -EOPNOTSUPP; 573 574 if (pp_funcs && pp_funcs->set_apu_thermal_limit) { 575 mutex_lock(&adev->pm.mutex); 576 ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); 577 mutex_unlock(&adev->pm.mutex); 578 } 579 580 return ret; 581 } 582 583 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) 584 { 585 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 586 int i; 587 588 if (!adev->pm.dpm_enabled) 589 return; 590 591 if (!pp_funcs->pm_compute_clocks) 592 return; 593 594 if (adev->mode_info.num_crtc) 595 amdgpu_display_bandwidth_update(adev); 596 597 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 598 struct amdgpu_ring *ring = adev->rings[i]; 599 if (ring && ring->sched.ready) 600 amdgpu_fence_wait_empty(ring); 601 } 602 603 mutex_lock(&adev->pm.mutex); 604 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); 605 mutex_unlock(&adev->pm.mutex); 606 } 607 608 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 609 { 610 int ret = 0; 611 612 if (adev->family == AMDGPU_FAMILY_SI) { 613 mutex_lock(&adev->pm.mutex); 614 if (enable) { 615 adev->pm.dpm.uvd_active = true; 616 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; 617 } else { 618 adev->pm.dpm.uvd_active = false; 619 } 620 mutex_unlock(&adev->pm.mutex); 621 622 amdgpu_dpm_compute_clocks(adev); 623 return; 624 } 625 626 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, 0); 627 if (ret) 628 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", 629 enable ? "enable" : "disable", ret); 630 } 631 632 void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst) 633 { 634 int ret = 0; 635 636 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, inst); 637 if (ret) 638 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", 639 enable ? "enable" : "disable", ret); 640 } 641 642 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 643 { 644 int ret = 0; 645 646 if (adev->family == AMDGPU_FAMILY_SI) { 647 mutex_lock(&adev->pm.mutex); 648 if (enable) { 649 adev->pm.dpm.vce_active = true; 650 /* XXX select vce level based on ring/task */ 651 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; 652 } else { 653 adev->pm.dpm.vce_active = false; 654 } 655 mutex_unlock(&adev->pm.mutex); 656 657 amdgpu_dpm_compute_clocks(adev); 658 return; 659 } 660 661 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable, 0); 662 if (ret) 663 DRM_ERROR("Dpm %s vce failed, ret = %d. \n", 664 enable ? "enable" : "disable", ret); 665 } 666 667 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) 668 { 669 int ret = 0; 670 671 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable, 0); 672 if (ret) 673 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n", 674 enable ? "enable" : "disable", ret); 675 } 676 677 void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) 678 { 679 int ret = 0; 680 681 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable, 0); 682 if (ret) 683 DRM_ERROR("Dpm %s vpe failed, ret = %d.\n", 684 enable ? "enable" : "disable", ret); 685 } 686 687 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) 688 { 689 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 690 int r = 0; 691 692 if (!pp_funcs || !pp_funcs->load_firmware || 693 (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) 694 return 0; 695 696 mutex_lock(&adev->pm.mutex); 697 r = pp_funcs->load_firmware(adev->powerplay.pp_handle); 698 if (r) { 699 pr_err("smu firmware loading failed\n"); 700 goto out; 701 } 702 703 if (smu_version) 704 *smu_version = adev->pm.fw_version; 705 706 out: 707 mutex_unlock(&adev->pm.mutex); 708 return r; 709 } 710 711 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) 712 { 713 int ret = 0; 714 715 if (is_support_sw_smu(adev)) { 716 mutex_lock(&adev->pm.mutex); 717 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, 718 enable); 719 mutex_unlock(&adev->pm.mutex); 720 } 721 722 return ret; 723 } 724 725 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) 726 { 727 struct smu_context *smu = adev->powerplay.pp_handle; 728 int ret = 0; 729 730 if (!is_support_sw_smu(adev)) 731 return -EOPNOTSUPP; 732 733 mutex_lock(&adev->pm.mutex); 734 ret = smu_send_hbm_bad_pages_num(smu, size); 735 mutex_unlock(&adev->pm.mutex); 736 737 return ret; 738 } 739 740 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) 741 { 742 struct smu_context *smu = adev->powerplay.pp_handle; 743 int ret = 0; 744 745 if (!is_support_sw_smu(adev)) 746 return -EOPNOTSUPP; 747 748 mutex_lock(&adev->pm.mutex); 749 ret = smu_send_hbm_bad_channel_flag(smu, size); 750 mutex_unlock(&adev->pm.mutex); 751 752 return ret; 753 } 754 755 int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) 756 { 757 struct smu_context *smu = adev->powerplay.pp_handle; 758 int ret; 759 760 if (!is_support_sw_smu(adev)) 761 return -EOPNOTSUPP; 762 763 mutex_lock(&adev->pm.mutex); 764 ret = smu_send_rma_reason(smu); 765 mutex_unlock(&adev->pm.mutex); 766 767 if (adev->cper.enabled) 768 if (amdgpu_cper_generate_bp_threshold_record(adev)) 769 dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); 770 771 return ret; 772 } 773 774 /** 775 * amdgpu_dpm_reset_sdma_is_supported - Check if SDMA reset is supported 776 * @adev: amdgpu_device pointer 777 * 778 * This function checks if the SMU supports resetting the SDMA engine. 779 * It returns false if the hardware does not support software SMU or 780 * if the feature is not supported. 781 */ 782 bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) 783 { 784 struct smu_context *smu = adev->powerplay.pp_handle; 785 bool ret; 786 787 if (!is_support_sw_smu(adev)) 788 return false; 789 790 mutex_lock(&adev->pm.mutex); 791 ret = smu_reset_sdma_is_supported(smu); 792 mutex_unlock(&adev->pm.mutex); 793 794 return ret; 795 } 796 797 int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) 798 { 799 struct smu_context *smu = adev->powerplay.pp_handle; 800 int ret; 801 802 if (!is_support_sw_smu(adev)) 803 return -EOPNOTSUPP; 804 805 mutex_lock(&adev->pm.mutex); 806 ret = smu_reset_sdma(smu, inst_mask); 807 mutex_unlock(&adev->pm.mutex); 808 809 return ret; 810 } 811 812 int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) 813 { 814 struct smu_context *smu = adev->powerplay.pp_handle; 815 int ret; 816 817 if (!is_support_sw_smu(adev)) 818 return -EOPNOTSUPP; 819 820 mutex_lock(&adev->pm.mutex); 821 ret = smu_reset_vcn(smu, inst_mask); 822 mutex_unlock(&adev->pm.mutex); 823 824 return ret; 825 } 826 827 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 828 enum pp_clock_type type, 829 uint32_t *min, 830 uint32_t *max) 831 { 832 int ret = 0; 833 834 if (type != PP_SCLK) 835 return -EINVAL; 836 837 if (!is_support_sw_smu(adev)) 838 return -EOPNOTSUPP; 839 840 mutex_lock(&adev->pm.mutex); 841 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, 842 SMU_SCLK, 843 min, 844 max); 845 mutex_unlock(&adev->pm.mutex); 846 847 return ret; 848 } 849 850 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 851 enum pp_clock_type type, 852 uint32_t min, 853 uint32_t max) 854 { 855 struct smu_context *smu = adev->powerplay.pp_handle; 856 857 if (!is_support_sw_smu(adev)) 858 return -EOPNOTSUPP; 859 860 guard(mutex)(&adev->pm.mutex); 861 862 return smu_set_soft_freq_range(smu, 863 type, 864 min, 865 max); 866 } 867 868 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) 869 { 870 struct smu_context *smu = adev->powerplay.pp_handle; 871 int ret = 0; 872 873 if (!is_support_sw_smu(adev)) 874 return 0; 875 876 mutex_lock(&adev->pm.mutex); 877 ret = smu_write_watermarks_table(smu); 878 mutex_unlock(&adev->pm.mutex); 879 880 return ret; 881 } 882 883 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, 884 enum smu_event_type event, 885 uint64_t event_arg) 886 { 887 struct smu_context *smu = adev->powerplay.pp_handle; 888 int ret = 0; 889 890 if (!is_support_sw_smu(adev)) 891 return -EOPNOTSUPP; 892 893 mutex_lock(&adev->pm.mutex); 894 ret = smu_wait_for_event(smu, event, event_arg); 895 mutex_unlock(&adev->pm.mutex); 896 897 return ret; 898 } 899 900 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) 901 { 902 struct smu_context *smu = adev->powerplay.pp_handle; 903 int ret = 0; 904 905 if (!is_support_sw_smu(adev)) 906 return -EOPNOTSUPP; 907 908 mutex_lock(&adev->pm.mutex); 909 ret = smu_set_residency_gfxoff(smu, value); 910 mutex_unlock(&adev->pm.mutex); 911 912 return ret; 913 } 914 915 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) 916 { 917 struct smu_context *smu = adev->powerplay.pp_handle; 918 int ret = 0; 919 920 if (!is_support_sw_smu(adev)) 921 return -EOPNOTSUPP; 922 923 mutex_lock(&adev->pm.mutex); 924 ret = smu_get_residency_gfxoff(smu, value); 925 mutex_unlock(&adev->pm.mutex); 926 927 return ret; 928 } 929 930 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) 931 { 932 struct smu_context *smu = adev->powerplay.pp_handle; 933 int ret = 0; 934 935 if (!is_support_sw_smu(adev)) 936 return -EOPNOTSUPP; 937 938 mutex_lock(&adev->pm.mutex); 939 ret = smu_get_entrycount_gfxoff(smu, value); 940 mutex_unlock(&adev->pm.mutex); 941 942 return ret; 943 } 944 945 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 946 { 947 struct smu_context *smu = adev->powerplay.pp_handle; 948 int ret = 0; 949 950 if (!is_support_sw_smu(adev)) 951 return -EOPNOTSUPP; 952 953 mutex_lock(&adev->pm.mutex); 954 ret = smu_get_status_gfxoff(smu, value); 955 mutex_unlock(&adev->pm.mutex); 956 957 return ret; 958 } 959 960 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) 961 { 962 struct smu_context *smu = adev->powerplay.pp_handle; 963 964 if (!is_support_sw_smu(adev)) 965 return 0; 966 967 return atomic64_read(&smu->throttle_int_counter); 968 } 969 970 /* amdgpu_dpm_gfx_state_change - Handle gfx power state change set 971 * @adev: amdgpu_device pointer 972 * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry) 973 * 974 */ 975 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 976 enum gfx_change_state state) 977 { 978 mutex_lock(&adev->pm.mutex); 979 if (adev->powerplay.pp_funcs && 980 adev->powerplay.pp_funcs->gfx_state_change_set) 981 ((adev)->powerplay.pp_funcs->gfx_state_change_set( 982 (adev)->powerplay.pp_handle, state)); 983 mutex_unlock(&adev->pm.mutex); 984 } 985 986 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 987 void *umc_ecc) 988 { 989 struct smu_context *smu = adev->powerplay.pp_handle; 990 int ret = 0; 991 992 if (!is_support_sw_smu(adev)) 993 return -EOPNOTSUPP; 994 995 mutex_lock(&adev->pm.mutex); 996 ret = smu_get_ecc_info(smu, umc_ecc); 997 mutex_unlock(&adev->pm.mutex); 998 999 return ret; 1000 } 1001 1002 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 1003 uint32_t idx) 1004 { 1005 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1006 struct amd_vce_state *vstate = NULL; 1007 1008 if (!pp_funcs->get_vce_clock_state) 1009 return NULL; 1010 1011 mutex_lock(&adev->pm.mutex); 1012 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, 1013 idx); 1014 mutex_unlock(&adev->pm.mutex); 1015 1016 return vstate; 1017 } 1018 1019 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, 1020 enum amd_pm_state_type *state) 1021 { 1022 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1023 1024 mutex_lock(&adev->pm.mutex); 1025 1026 if (!pp_funcs->get_current_power_state) { 1027 *state = adev->pm.dpm.user_state; 1028 goto out; 1029 } 1030 1031 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); 1032 if (*state < POWER_STATE_TYPE_DEFAULT || 1033 *state > POWER_STATE_TYPE_INTERNAL_3DPERF) 1034 *state = adev->pm.dpm.user_state; 1035 1036 out: 1037 mutex_unlock(&adev->pm.mutex); 1038 } 1039 1040 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 1041 enum amd_pm_state_type state) 1042 { 1043 mutex_lock(&adev->pm.mutex); 1044 adev->pm.dpm.user_state = state; 1045 mutex_unlock(&adev->pm.mutex); 1046 1047 if (is_support_sw_smu(adev)) 1048 return; 1049 1050 if (amdgpu_dpm_dispatch_task(adev, 1051 AMD_PP_TASK_ENABLE_USER_STATE, 1052 &state) == -EOPNOTSUPP) 1053 amdgpu_dpm_compute_clocks(adev); 1054 } 1055 1056 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) 1057 { 1058 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1059 enum amd_dpm_forced_level level; 1060 1061 if (!pp_funcs) 1062 return AMD_DPM_FORCED_LEVEL_AUTO; 1063 1064 mutex_lock(&adev->pm.mutex); 1065 if (pp_funcs->get_performance_level) 1066 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); 1067 else 1068 level = adev->pm.dpm.forced_level; 1069 mutex_unlock(&adev->pm.mutex); 1070 1071 return level; 1072 } 1073 1074 static void amdgpu_dpm_enter_umd_state(struct amdgpu_device *adev) 1075 { 1076 /* enter UMD Pstate */ 1077 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX, 1078 AMD_PG_STATE_UNGATE); 1079 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX, 1080 AMD_CG_STATE_UNGATE); 1081 } 1082 1083 static void amdgpu_dpm_exit_umd_state(struct amdgpu_device *adev) 1084 { 1085 /* exit UMD Pstate */ 1086 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX, 1087 AMD_CG_STATE_GATE); 1088 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX, 1089 AMD_PG_STATE_GATE); 1090 } 1091 1092 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 1093 enum amd_dpm_forced_level level) 1094 { 1095 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1096 enum amd_dpm_forced_level current_level; 1097 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1098 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1099 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1100 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1101 1102 if (!pp_funcs || !pp_funcs->force_performance_level) 1103 return 0; 1104 1105 if (adev->pm.dpm.thermal_active) 1106 return -EINVAL; 1107 1108 current_level = amdgpu_dpm_get_performance_level(adev); 1109 if (current_level == level) 1110 return 0; 1111 1112 if (!(current_level & profile_mode_mask) && 1113 (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) 1114 return -EINVAL; 1115 1116 if (adev->asic_type == CHIP_RAVEN) { 1117 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { 1118 if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1119 level == AMD_DPM_FORCED_LEVEL_MANUAL) 1120 amdgpu_gfx_off_ctrl(adev, false); 1121 else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && 1122 level != AMD_DPM_FORCED_LEVEL_MANUAL) 1123 amdgpu_gfx_off_ctrl(adev, true); 1124 } 1125 } 1126 1127 if (!(current_level & profile_mode_mask) && (level & profile_mode_mask)) 1128 amdgpu_dpm_enter_umd_state(adev); 1129 else if ((current_level & profile_mode_mask) && 1130 !(level & profile_mode_mask)) 1131 amdgpu_dpm_exit_umd_state(adev); 1132 1133 mutex_lock(&adev->pm.mutex); 1134 1135 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, 1136 level)) { 1137 mutex_unlock(&adev->pm.mutex); 1138 /* If new level failed, retain the umd state as before */ 1139 if (!(current_level & profile_mode_mask) && 1140 (level & profile_mode_mask)) 1141 amdgpu_dpm_exit_umd_state(adev); 1142 else if ((current_level & profile_mode_mask) && 1143 !(level & profile_mode_mask)) 1144 amdgpu_dpm_enter_umd_state(adev); 1145 1146 return -EINVAL; 1147 } 1148 1149 adev->pm.dpm.forced_level = level; 1150 1151 mutex_unlock(&adev->pm.mutex); 1152 1153 return 0; 1154 } 1155 1156 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 1157 struct pp_states_info *states) 1158 { 1159 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1160 int ret = 0; 1161 1162 if (!pp_funcs->get_pp_num_states) 1163 return -EOPNOTSUPP; 1164 1165 mutex_lock(&adev->pm.mutex); 1166 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, 1167 states); 1168 mutex_unlock(&adev->pm.mutex); 1169 1170 return ret; 1171 } 1172 1173 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 1174 enum amd_pp_task task_id, 1175 enum amd_pm_state_type *user_state) 1176 { 1177 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1178 int ret = 0; 1179 1180 if (!pp_funcs->dispatch_tasks) 1181 return -EOPNOTSUPP; 1182 1183 mutex_lock(&adev->pm.mutex); 1184 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, 1185 task_id, 1186 user_state); 1187 mutex_unlock(&adev->pm.mutex); 1188 1189 return ret; 1190 } 1191 1192 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) 1193 { 1194 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1195 int ret = 0; 1196 1197 if (!pp_funcs->get_pp_table) 1198 return 0; 1199 1200 mutex_lock(&adev->pm.mutex); 1201 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, 1202 table); 1203 mutex_unlock(&adev->pm.mutex); 1204 1205 return ret; 1206 } 1207 1208 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 1209 uint32_t type, 1210 long *input, 1211 uint32_t size) 1212 { 1213 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1214 int ret = 0; 1215 1216 if (!pp_funcs->set_fine_grain_clk_vol) 1217 return 0; 1218 1219 mutex_lock(&adev->pm.mutex); 1220 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, 1221 type, 1222 input, 1223 size); 1224 mutex_unlock(&adev->pm.mutex); 1225 1226 return ret; 1227 } 1228 1229 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 1230 uint32_t type, 1231 long *input, 1232 uint32_t size) 1233 { 1234 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1235 int ret = 0; 1236 1237 if (!pp_funcs->odn_edit_dpm_table) 1238 return 0; 1239 1240 mutex_lock(&adev->pm.mutex); 1241 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, 1242 type, 1243 input, 1244 size); 1245 mutex_unlock(&adev->pm.mutex); 1246 1247 return ret; 1248 } 1249 1250 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 1251 enum pp_clock_type type, 1252 char *buf) 1253 { 1254 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1255 int ret = 0; 1256 1257 if (!pp_funcs->print_clock_levels) 1258 return 0; 1259 1260 mutex_lock(&adev->pm.mutex); 1261 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, 1262 type, 1263 buf); 1264 mutex_unlock(&adev->pm.mutex); 1265 1266 return ret; 1267 } 1268 1269 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, 1270 enum pp_clock_type type, 1271 char *buf, 1272 int *offset) 1273 { 1274 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1275 int ret = 0; 1276 1277 if (!pp_funcs->emit_clock_levels) 1278 return -ENOENT; 1279 1280 mutex_lock(&adev->pm.mutex); 1281 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, 1282 type, 1283 buf, 1284 offset); 1285 mutex_unlock(&adev->pm.mutex); 1286 1287 return ret; 1288 } 1289 1290 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 1291 uint64_t ppfeature_masks) 1292 { 1293 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1294 int ret = 0; 1295 1296 if (!pp_funcs->set_ppfeature_status) 1297 return 0; 1298 1299 mutex_lock(&adev->pm.mutex); 1300 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, 1301 ppfeature_masks); 1302 mutex_unlock(&adev->pm.mutex); 1303 1304 return ret; 1305 } 1306 1307 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) 1308 { 1309 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1310 int ret = 0; 1311 1312 if (!pp_funcs->get_ppfeature_status) 1313 return 0; 1314 1315 mutex_lock(&adev->pm.mutex); 1316 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, 1317 buf); 1318 mutex_unlock(&adev->pm.mutex); 1319 1320 return ret; 1321 } 1322 1323 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 1324 enum pp_clock_type type, 1325 uint32_t mask) 1326 { 1327 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1328 int ret = 0; 1329 1330 if (!pp_funcs->force_clock_level) 1331 return 0; 1332 1333 mutex_lock(&adev->pm.mutex); 1334 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, 1335 type, 1336 mask); 1337 mutex_unlock(&adev->pm.mutex); 1338 1339 return ret; 1340 } 1341 1342 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) 1343 { 1344 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1345 int ret = 0; 1346 1347 if (!pp_funcs->get_sclk_od) 1348 return -EOPNOTSUPP; 1349 1350 mutex_lock(&adev->pm.mutex); 1351 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); 1352 mutex_unlock(&adev->pm.mutex); 1353 1354 return ret; 1355 } 1356 1357 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) 1358 { 1359 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1360 1361 if (is_support_sw_smu(adev)) 1362 return -EOPNOTSUPP; 1363 1364 mutex_lock(&adev->pm.mutex); 1365 if (pp_funcs->set_sclk_od) 1366 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); 1367 mutex_unlock(&adev->pm.mutex); 1368 1369 if (amdgpu_dpm_dispatch_task(adev, 1370 AMD_PP_TASK_READJUST_POWER_STATE, 1371 NULL) == -EOPNOTSUPP) { 1372 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1373 amdgpu_dpm_compute_clocks(adev); 1374 } 1375 1376 return 0; 1377 } 1378 1379 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) 1380 { 1381 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1382 int ret = 0; 1383 1384 if (!pp_funcs->get_mclk_od) 1385 return -EOPNOTSUPP; 1386 1387 mutex_lock(&adev->pm.mutex); 1388 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); 1389 mutex_unlock(&adev->pm.mutex); 1390 1391 return ret; 1392 } 1393 1394 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) 1395 { 1396 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1397 1398 if (is_support_sw_smu(adev)) 1399 return -EOPNOTSUPP; 1400 1401 mutex_lock(&adev->pm.mutex); 1402 if (pp_funcs->set_mclk_od) 1403 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); 1404 mutex_unlock(&adev->pm.mutex); 1405 1406 if (amdgpu_dpm_dispatch_task(adev, 1407 AMD_PP_TASK_READJUST_POWER_STATE, 1408 NULL) == -EOPNOTSUPP) { 1409 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1410 amdgpu_dpm_compute_clocks(adev); 1411 } 1412 1413 return 0; 1414 } 1415 1416 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 1417 char *buf) 1418 { 1419 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1420 int ret = 0; 1421 1422 if (!pp_funcs->get_power_profile_mode) 1423 return -EOPNOTSUPP; 1424 1425 mutex_lock(&adev->pm.mutex); 1426 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, 1427 buf); 1428 mutex_unlock(&adev->pm.mutex); 1429 1430 return ret; 1431 } 1432 1433 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 1434 long *input, uint32_t size) 1435 { 1436 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1437 int ret = 0; 1438 1439 if (!pp_funcs->set_power_profile_mode) 1440 return 0; 1441 1442 mutex_lock(&adev->pm.mutex); 1443 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, 1444 input, 1445 size); 1446 mutex_unlock(&adev->pm.mutex); 1447 1448 return ret; 1449 } 1450 1451 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) 1452 { 1453 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1454 int ret = 0; 1455 1456 if (!pp_funcs->get_gpu_metrics) 1457 return 0; 1458 1459 mutex_lock(&adev->pm.mutex); 1460 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, 1461 table); 1462 mutex_unlock(&adev->pm.mutex); 1463 1464 return ret; 1465 } 1466 1467 ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, 1468 size_t size) 1469 { 1470 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1471 int ret = 0; 1472 1473 if (!pp_funcs->get_pm_metrics) 1474 return -EOPNOTSUPP; 1475 1476 mutex_lock(&adev->pm.mutex); 1477 ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, 1478 size); 1479 mutex_unlock(&adev->pm.mutex); 1480 1481 return ret; 1482 } 1483 1484 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 1485 uint32_t *fan_mode) 1486 { 1487 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1488 int ret = 0; 1489 1490 if (!pp_funcs->get_fan_control_mode) 1491 return -EOPNOTSUPP; 1492 1493 mutex_lock(&adev->pm.mutex); 1494 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, 1495 fan_mode); 1496 mutex_unlock(&adev->pm.mutex); 1497 1498 return ret; 1499 } 1500 1501 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 1502 uint32_t speed) 1503 { 1504 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1505 int ret = 0; 1506 1507 if (!pp_funcs->set_fan_speed_pwm) 1508 return -EOPNOTSUPP; 1509 1510 mutex_lock(&adev->pm.mutex); 1511 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, 1512 speed); 1513 mutex_unlock(&adev->pm.mutex); 1514 1515 return ret; 1516 } 1517 1518 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 1519 uint32_t *speed) 1520 { 1521 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1522 int ret = 0; 1523 1524 if (!pp_funcs->get_fan_speed_pwm) 1525 return -EOPNOTSUPP; 1526 1527 mutex_lock(&adev->pm.mutex); 1528 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, 1529 speed); 1530 mutex_unlock(&adev->pm.mutex); 1531 1532 return ret; 1533 } 1534 1535 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 1536 uint32_t *speed) 1537 { 1538 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1539 int ret = 0; 1540 1541 if (!pp_funcs->get_fan_speed_rpm) 1542 return -EOPNOTSUPP; 1543 1544 mutex_lock(&adev->pm.mutex); 1545 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, 1546 speed); 1547 mutex_unlock(&adev->pm.mutex); 1548 1549 return ret; 1550 } 1551 1552 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 1553 uint32_t speed) 1554 { 1555 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1556 int ret = 0; 1557 1558 if (!pp_funcs->set_fan_speed_rpm) 1559 return -EOPNOTSUPP; 1560 1561 mutex_lock(&adev->pm.mutex); 1562 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, 1563 speed); 1564 mutex_unlock(&adev->pm.mutex); 1565 1566 return ret; 1567 } 1568 1569 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 1570 uint32_t mode) 1571 { 1572 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1573 int ret = 0; 1574 1575 if (!pp_funcs->set_fan_control_mode) 1576 return -EOPNOTSUPP; 1577 1578 mutex_lock(&adev->pm.mutex); 1579 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, 1580 mode); 1581 mutex_unlock(&adev->pm.mutex); 1582 1583 return ret; 1584 } 1585 1586 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 1587 uint32_t *limit, 1588 enum pp_power_limit_level pp_limit_level, 1589 enum pp_power_type power_type) 1590 { 1591 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1592 int ret = 0; 1593 1594 if (!pp_funcs->get_power_limit) 1595 return -ENODATA; 1596 1597 mutex_lock(&adev->pm.mutex); 1598 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, 1599 limit, 1600 pp_limit_level, 1601 power_type); 1602 mutex_unlock(&adev->pm.mutex); 1603 1604 return ret; 1605 } 1606 1607 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 1608 uint32_t limit) 1609 { 1610 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1611 int ret = 0; 1612 1613 if (!pp_funcs->set_power_limit) 1614 return -EINVAL; 1615 1616 mutex_lock(&adev->pm.mutex); 1617 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, 1618 limit); 1619 mutex_unlock(&adev->pm.mutex); 1620 1621 return ret; 1622 } 1623 1624 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) 1625 { 1626 bool cclk_dpm_supported = false; 1627 1628 if (!is_support_sw_smu(adev)) 1629 return false; 1630 1631 mutex_lock(&adev->pm.mutex); 1632 cclk_dpm_supported = is_support_cclk_dpm(adev); 1633 mutex_unlock(&adev->pm.mutex); 1634 1635 return (int)cclk_dpm_supported; 1636 } 1637 1638 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 1639 struct seq_file *m) 1640 { 1641 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1642 1643 if (!pp_funcs->debugfs_print_current_performance_level) 1644 return -EOPNOTSUPP; 1645 1646 mutex_lock(&adev->pm.mutex); 1647 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, 1648 m); 1649 mutex_unlock(&adev->pm.mutex); 1650 1651 return 0; 1652 } 1653 1654 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 1655 void **addr, 1656 size_t *size) 1657 { 1658 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1659 int ret = 0; 1660 1661 if (!pp_funcs->get_smu_prv_buf_details) 1662 return -ENOSYS; 1663 1664 mutex_lock(&adev->pm.mutex); 1665 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, 1666 addr, 1667 size); 1668 mutex_unlock(&adev->pm.mutex); 1669 1670 return ret; 1671 } 1672 1673 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) 1674 { 1675 if (is_support_sw_smu(adev)) { 1676 struct smu_context *smu = adev->powerplay.pp_handle; 1677 1678 return (smu->od_enabled || smu->is_apu); 1679 } else { 1680 struct pp_hwmgr *hwmgr; 1681 1682 /* 1683 * dpm on some legacy asics don't carry od_enabled member 1684 * as its pp_handle is casted directly from adev. 1685 */ 1686 if (amdgpu_dpm_is_legacy_dpm(adev)) 1687 return false; 1688 1689 hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle; 1690 1691 return hwmgr->od_enabled; 1692 } 1693 } 1694 1695 int amdgpu_dpm_is_overdrive_enabled(struct amdgpu_device *adev) 1696 { 1697 if (is_support_sw_smu(adev)) { 1698 struct smu_context *smu = adev->powerplay.pp_handle; 1699 1700 return smu->od_enabled; 1701 } else { 1702 struct pp_hwmgr *hwmgr; 1703 1704 /* 1705 * dpm on some legacy asics don't carry od_enabled member 1706 * as its pp_handle is casted directly from adev. 1707 */ 1708 if (amdgpu_dpm_is_legacy_dpm(adev)) 1709 return false; 1710 1711 hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle; 1712 1713 return hwmgr->od_enabled; 1714 } 1715 } 1716 1717 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 1718 const char *buf, 1719 size_t size) 1720 { 1721 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1722 int ret = 0; 1723 1724 if (!pp_funcs->set_pp_table) 1725 return -EOPNOTSUPP; 1726 1727 mutex_lock(&adev->pm.mutex); 1728 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, 1729 buf, 1730 size); 1731 mutex_unlock(&adev->pm.mutex); 1732 1733 return ret; 1734 } 1735 1736 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) 1737 { 1738 struct smu_context *smu = adev->powerplay.pp_handle; 1739 1740 if (!is_support_sw_smu(adev)) 1741 return INT_MAX; 1742 1743 return smu->cpu_core_num; 1744 } 1745 1746 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) 1747 { 1748 if (!is_support_sw_smu(adev)) 1749 return; 1750 1751 amdgpu_smu_stb_debug_fs_init(adev); 1752 } 1753 1754 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 1755 const struct amd_pp_display_configuration *input) 1756 { 1757 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1758 int ret = 0; 1759 1760 if (!pp_funcs->display_configuration_change) 1761 return 0; 1762 1763 mutex_lock(&adev->pm.mutex); 1764 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, 1765 input); 1766 mutex_unlock(&adev->pm.mutex); 1767 1768 return ret; 1769 } 1770 1771 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 1772 enum amd_pp_clock_type type, 1773 struct amd_pp_clocks *clocks) 1774 { 1775 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1776 int ret = 0; 1777 1778 if (!pp_funcs->get_clock_by_type) 1779 return 0; 1780 1781 mutex_lock(&adev->pm.mutex); 1782 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, 1783 type, 1784 clocks); 1785 mutex_unlock(&adev->pm.mutex); 1786 1787 return ret; 1788 } 1789 1790 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 1791 struct amd_pp_simple_clock_info *clocks) 1792 { 1793 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1794 int ret = 0; 1795 1796 if (!pp_funcs->get_display_mode_validation_clocks) 1797 return 0; 1798 1799 mutex_lock(&adev->pm.mutex); 1800 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, 1801 clocks); 1802 mutex_unlock(&adev->pm.mutex); 1803 1804 return ret; 1805 } 1806 1807 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 1808 enum amd_pp_clock_type type, 1809 struct pp_clock_levels_with_latency *clocks) 1810 { 1811 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1812 int ret = 0; 1813 1814 if (!pp_funcs->get_clock_by_type_with_latency) 1815 return 0; 1816 1817 mutex_lock(&adev->pm.mutex); 1818 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, 1819 type, 1820 clocks); 1821 mutex_unlock(&adev->pm.mutex); 1822 1823 return ret; 1824 } 1825 1826 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 1827 enum amd_pp_clock_type type, 1828 struct pp_clock_levels_with_voltage *clocks) 1829 { 1830 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1831 int ret = 0; 1832 1833 if (!pp_funcs->get_clock_by_type_with_voltage) 1834 return 0; 1835 1836 mutex_lock(&adev->pm.mutex); 1837 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, 1838 type, 1839 clocks); 1840 mutex_unlock(&adev->pm.mutex); 1841 1842 return ret; 1843 } 1844 1845 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 1846 void *clock_ranges) 1847 { 1848 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1849 int ret = 0; 1850 1851 if (!pp_funcs->set_watermarks_for_clocks_ranges) 1852 return -EOPNOTSUPP; 1853 1854 mutex_lock(&adev->pm.mutex); 1855 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, 1856 clock_ranges); 1857 mutex_unlock(&adev->pm.mutex); 1858 1859 return ret; 1860 } 1861 1862 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 1863 struct pp_display_clock_request *clock) 1864 { 1865 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1866 int ret = 0; 1867 1868 if (!pp_funcs->display_clock_voltage_request) 1869 return -EOPNOTSUPP; 1870 1871 mutex_lock(&adev->pm.mutex); 1872 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, 1873 clock); 1874 mutex_unlock(&adev->pm.mutex); 1875 1876 return ret; 1877 } 1878 1879 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 1880 struct amd_pp_clock_info *clocks) 1881 { 1882 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1883 int ret = 0; 1884 1885 if (!pp_funcs->get_current_clocks) 1886 return -EOPNOTSUPP; 1887 1888 mutex_lock(&adev->pm.mutex); 1889 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, 1890 clocks); 1891 mutex_unlock(&adev->pm.mutex); 1892 1893 return ret; 1894 } 1895 1896 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) 1897 { 1898 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1899 1900 if (!pp_funcs->notify_smu_enable_pwe) 1901 return; 1902 1903 mutex_lock(&adev->pm.mutex); 1904 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); 1905 mutex_unlock(&adev->pm.mutex); 1906 } 1907 1908 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 1909 uint32_t count) 1910 { 1911 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1912 int ret = 0; 1913 1914 if (!pp_funcs->set_active_display_count) 1915 return -EOPNOTSUPP; 1916 1917 mutex_lock(&adev->pm.mutex); 1918 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, 1919 count); 1920 mutex_unlock(&adev->pm.mutex); 1921 1922 return ret; 1923 } 1924 1925 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 1926 uint32_t clock) 1927 { 1928 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1929 int ret = 0; 1930 1931 if (!pp_funcs->set_min_deep_sleep_dcefclk) 1932 return -EOPNOTSUPP; 1933 1934 mutex_lock(&adev->pm.mutex); 1935 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, 1936 clock); 1937 mutex_unlock(&adev->pm.mutex); 1938 1939 return ret; 1940 } 1941 1942 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 1943 uint32_t clock) 1944 { 1945 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1946 1947 if (!pp_funcs->set_hard_min_dcefclk_by_freq) 1948 return; 1949 1950 mutex_lock(&adev->pm.mutex); 1951 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, 1952 clock); 1953 mutex_unlock(&adev->pm.mutex); 1954 } 1955 1956 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 1957 uint32_t clock) 1958 { 1959 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1960 1961 if (!pp_funcs->set_hard_min_fclk_by_freq) 1962 return; 1963 1964 mutex_lock(&adev->pm.mutex); 1965 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, 1966 clock); 1967 mutex_unlock(&adev->pm.mutex); 1968 } 1969 1970 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 1971 bool disable_memory_clock_switch) 1972 { 1973 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1974 int ret = 0; 1975 1976 if (!pp_funcs->display_disable_memory_clock_switch) 1977 return 0; 1978 1979 mutex_lock(&adev->pm.mutex); 1980 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, 1981 disable_memory_clock_switch); 1982 mutex_unlock(&adev->pm.mutex); 1983 1984 return ret; 1985 } 1986 1987 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 1988 struct pp_smu_nv_clock_table *max_clocks) 1989 { 1990 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1991 int ret = 0; 1992 1993 if (!pp_funcs->get_max_sustainable_clocks_by_dc) 1994 return -EOPNOTSUPP; 1995 1996 mutex_lock(&adev->pm.mutex); 1997 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, 1998 max_clocks); 1999 mutex_unlock(&adev->pm.mutex); 2000 2001 return ret; 2002 } 2003 2004 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 2005 unsigned int *clock_values_in_khz, 2006 unsigned int *num_states) 2007 { 2008 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 2009 int ret = 0; 2010 2011 if (!pp_funcs->get_uclk_dpm_states) 2012 return -EOPNOTSUPP; 2013 2014 mutex_lock(&adev->pm.mutex); 2015 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, 2016 clock_values_in_khz, 2017 num_states); 2018 mutex_unlock(&adev->pm.mutex); 2019 2020 return ret; 2021 } 2022 2023 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 2024 struct dpm_clocks *clock_table) 2025 { 2026 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 2027 int ret = 0; 2028 2029 if (!pp_funcs->get_dpm_clock_table) 2030 return -EOPNOTSUPP; 2031 2032 mutex_lock(&adev->pm.mutex); 2033 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, 2034 clock_table); 2035 mutex_unlock(&adev->pm.mutex); 2036 2037 return ret; 2038 } 2039 2040 /** 2041 * amdgpu_dpm_get_xcp_metrics - Retrieve metrics for a specific compute 2042 * partition 2043 * @adev: Pointer to the device. 2044 * @xcp_id: Identifier of the XCP for which metrics are to be retrieved. 2045 * @table: Pointer to a buffer where the metrics will be stored. If NULL, the 2046 * function returns the size of the metrics structure. 2047 * 2048 * This function retrieves metrics for a specific XCP, including details such as 2049 * VCN/JPEG activity, clock frequencies, and other performance metrics. If the 2050 * table parameter is NULL, the function returns the size of the metrics 2051 * structure without populating it. 2052 * 2053 * Return: Size of the metrics structure on success, or a negative error code on failure. 2054 */ 2055 ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, 2056 void *table) 2057 { 2058 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 2059 int ret = 0; 2060 2061 if (!pp_funcs->get_xcp_metrics) 2062 return 0; 2063 2064 mutex_lock(&adev->pm.mutex); 2065 ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, 2066 table); 2067 mutex_unlock(&adev->pm.mutex); 2068 2069 return ret; 2070 } 2071