1 #ifndef YELLOW_CARP_OFFSET_H 2 #define YELLOW_CARP_OFFSET_H 3 4 5 #define MAX_INSTANCE 7 6 #define MAX_SEGMENT 6 7 8 9 struct IP_BASE_INSTANCE 10 { 11 unsigned int segment[MAX_SEGMENT]; 12 } __maybe_unused; 13 14 struct IP_BASE 15 { 16 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 17 } __maybe_unused; 18 19 20 static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } }, 21 { { 0, 0, 0, 0, 0, 0 } }, 22 { { 0, 0, 0, 0, 0, 0 } }, 23 { { 0, 0, 0, 0, 0, 0 } }, 24 { { 0, 0, 0, 0, 0, 0 } }, 25 { { 0, 0, 0, 0, 0, 0 } }, 26 { { 0, 0, 0, 0, 0, 0 } } } }; 27 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } }, 28 { { 0, 0, 0, 0, 0, 0 } }, 29 { { 0, 0, 0, 0, 0, 0 } }, 30 { { 0, 0, 0, 0, 0, 0 } }, 31 { { 0, 0, 0, 0, 0, 0 } }, 32 { { 0, 0, 0, 0, 0, 0 } }, 33 { { 0, 0, 0, 0, 0, 0 } } } }; 34 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, 35 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, 36 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, 37 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, 38 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, 39 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, 40 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } }; 41 static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0x00000260, 0x00000280, 0x0240B400, 0x02413C00, 0x02416000 } }, 42 { { 0, 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0, 0 } }, 45 { { 0, 0, 0, 0, 0, 0 } }, 46 { { 0, 0, 0, 0, 0, 0 } }, 47 { { 0, 0, 0, 0, 0, 0 } } } }; 48 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 49 { { 0, 0, 0, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0, 0 } }, 51 { { 0, 0, 0, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0, 0 } } } }; 55 static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 56 { { 0, 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0, 0 } } } }; 62 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x02447800, 0x00C00000, 0x03640000, 0 } }, 63 { { 0, 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0, 0 } }, 65 { { 0, 0, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0, 0 } } } }; 69 static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0, 0 } }, 73 { { 0, 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0, 0 } } } }; 76 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0, 0 } } } }; 83 static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0, 0 } } } }; 90 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0, 0 } } } }; 97 static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0, 0 } } } }; 104 static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0, 0 } } } }; 111 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } } } }; 118 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0, 0 } } } }; 125 static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, 126 { { 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0 } } } }; 132 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, 133 { { 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0, 0 } } } }; 139 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0, 0 } } } }; 146 static const struct IP_BASE PCIE_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } }, 147 { { 0x02411C00, 0x04480000, 0, 0, 0, 0 } }, 148 { { 0x02412000, 0x044C0000, 0, 0, 0, 0 } }, 149 { { 0x02412400, 0x04500000, 0, 0, 0, 0 } }, 150 { { 0, 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0, 0 } } } }; 153 static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0, 0 } } } }; 160 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } }, 161 { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0, 0 } }, 164 { { 0, 0, 0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0, 0 } } } }; 167 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0, 0 } }, 169 { { 0, 0, 0, 0, 0, 0 } }, 170 { { 0, 0, 0, 0, 0, 0 } }, 171 { { 0, 0, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0, 0 } }, 173 { { 0, 0, 0, 0, 0, 0 } } } }; 174 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0x02425C00, 0, 0 } }, 175 { { 0x00094000, 0x000D4000, 0x02426000, 0x02426400, 0, 0 } }, 176 { { 0, 0, 0, 0, 0, 0 } }, 177 { { 0, 0, 0, 0, 0, 0 } }, 178 { { 0, 0, 0, 0, 0, 0 } }, 179 { { 0, 0, 0, 0, 0, 0 } }, 180 { { 0, 0, 0, 0, 0, 0 } } } }; 181 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0, 0 } }, 184 { { 0, 0, 0, 0, 0, 0 } }, 185 { { 0, 0, 0, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0, 0 } } } }; 188 189 190 #define ACP_BASE__INST0_SEG0 0x02403800 191 #define ACP_BASE__INST0_SEG1 0x00480000 192 #define ACP_BASE__INST0_SEG2 0 193 #define ACP_BASE__INST0_SEG3 0 194 #define ACP_BASE__INST0_SEG4 0 195 #define ACP_BASE__INST0_SEG5 0 196 197 #define ACP_BASE__INST1_SEG0 0 198 #define ACP_BASE__INST1_SEG1 0 199 #define ACP_BASE__INST1_SEG2 0 200 #define ACP_BASE__INST1_SEG3 0 201 #define ACP_BASE__INST1_SEG4 0 202 #define ACP_BASE__INST1_SEG5 0 203 204 #define ACP_BASE__INST2_SEG0 0 205 #define ACP_BASE__INST2_SEG1 0 206 #define ACP_BASE__INST2_SEG2 0 207 #define ACP_BASE__INST2_SEG3 0 208 #define ACP_BASE__INST2_SEG4 0 209 #define ACP_BASE__INST2_SEG5 0 210 211 #define ACP_BASE__INST3_SEG0 0 212 #define ACP_BASE__INST3_SEG1 0 213 #define ACP_BASE__INST3_SEG2 0 214 #define ACP_BASE__INST3_SEG3 0 215 #define ACP_BASE__INST3_SEG4 0 216 #define ACP_BASE__INST3_SEG5 0 217 218 #define ACP_BASE__INST4_SEG0 0 219 #define ACP_BASE__INST4_SEG1 0 220 #define ACP_BASE__INST4_SEG2 0 221 #define ACP_BASE__INST4_SEG3 0 222 #define ACP_BASE__INST4_SEG4 0 223 #define ACP_BASE__INST4_SEG5 0 224 225 #define ACP_BASE__INST5_SEG0 0 226 #define ACP_BASE__INST5_SEG1 0 227 #define ACP_BASE__INST5_SEG2 0 228 #define ACP_BASE__INST5_SEG3 0 229 #define ACP_BASE__INST5_SEG4 0 230 #define ACP_BASE__INST5_SEG5 0 231 232 #define ACP_BASE__INST6_SEG0 0 233 #define ACP_BASE__INST6_SEG1 0 234 #define ACP_BASE__INST6_SEG2 0 235 #define ACP_BASE__INST6_SEG3 0 236 #define ACP_BASE__INST6_SEG4 0 237 #define ACP_BASE__INST6_SEG5 0 238 239 #define ATHUB_BASE__INST0_SEG0 0x00000C00 240 #define ATHUB_BASE__INST0_SEG1 0x00013300 241 #define ATHUB_BASE__INST0_SEG2 0x02408C00 242 #define ATHUB_BASE__INST0_SEG3 0 243 #define ATHUB_BASE__INST0_SEG4 0 244 #define ATHUB_BASE__INST0_SEG5 0 245 246 #define ATHUB_BASE__INST1_SEG0 0 247 #define ATHUB_BASE__INST1_SEG1 0 248 #define ATHUB_BASE__INST1_SEG2 0 249 #define ATHUB_BASE__INST1_SEG3 0 250 #define ATHUB_BASE__INST1_SEG4 0 251 #define ATHUB_BASE__INST1_SEG5 0 252 253 #define ATHUB_BASE__INST2_SEG0 0 254 #define ATHUB_BASE__INST2_SEG1 0 255 #define ATHUB_BASE__INST2_SEG2 0 256 #define ATHUB_BASE__INST2_SEG3 0 257 #define ATHUB_BASE__INST2_SEG4 0 258 #define ATHUB_BASE__INST2_SEG5 0 259 260 #define ATHUB_BASE__INST3_SEG0 0 261 #define ATHUB_BASE__INST3_SEG1 0 262 #define ATHUB_BASE__INST3_SEG2 0 263 #define ATHUB_BASE__INST3_SEG3 0 264 #define ATHUB_BASE__INST3_SEG4 0 265 #define ATHUB_BASE__INST3_SEG5 0 266 267 #define ATHUB_BASE__INST4_SEG0 0 268 #define ATHUB_BASE__INST4_SEG1 0 269 #define ATHUB_BASE__INST4_SEG2 0 270 #define ATHUB_BASE__INST4_SEG3 0 271 #define ATHUB_BASE__INST4_SEG4 0 272 #define ATHUB_BASE__INST4_SEG5 0 273 274 #define ATHUB_BASE__INST5_SEG0 0 275 #define ATHUB_BASE__INST5_SEG1 0 276 #define ATHUB_BASE__INST5_SEG2 0 277 #define ATHUB_BASE__INST5_SEG3 0 278 #define ATHUB_BASE__INST5_SEG4 0 279 #define ATHUB_BASE__INST5_SEG5 0 280 281 #define ATHUB_BASE__INST6_SEG0 0 282 #define ATHUB_BASE__INST6_SEG1 0 283 #define ATHUB_BASE__INST6_SEG2 0 284 #define ATHUB_BASE__INST6_SEG3 0 285 #define ATHUB_BASE__INST6_SEG4 0 286 #define ATHUB_BASE__INST6_SEG5 0 287 288 #define CLK_BASE__INST0_SEG0 0x00016C00 289 #define CLK_BASE__INST0_SEG1 0x02401800 290 #define CLK_BASE__INST0_SEG2 0 291 #define CLK_BASE__INST0_SEG3 0 292 #define CLK_BASE__INST0_SEG4 0 293 #define CLK_BASE__INST0_SEG5 0 294 295 #define CLK_BASE__INST1_SEG0 0x00016E00 296 #define CLK_BASE__INST1_SEG1 0x02401C00 297 #define CLK_BASE__INST1_SEG2 0 298 #define CLK_BASE__INST1_SEG3 0 299 #define CLK_BASE__INST1_SEG4 0 300 #define CLK_BASE__INST1_SEG5 0 301 302 #define CLK_BASE__INST2_SEG0 0x00017000 303 #define CLK_BASE__INST2_SEG1 0x02402000 304 #define CLK_BASE__INST2_SEG2 0 305 #define CLK_BASE__INST2_SEG3 0 306 #define CLK_BASE__INST2_SEG4 0 307 #define CLK_BASE__INST2_SEG5 0 308 309 #define CLK_BASE__INST3_SEG0 0x00017200 310 #define CLK_BASE__INST3_SEG1 0x02402400 311 #define CLK_BASE__INST3_SEG2 0 312 #define CLK_BASE__INST3_SEG3 0 313 #define CLK_BASE__INST3_SEG4 0 314 #define CLK_BASE__INST3_SEG5 0 315 316 #define CLK_BASE__INST4_SEG0 0x0001B000 317 #define CLK_BASE__INST4_SEG1 0x0242D800 318 #define CLK_BASE__INST4_SEG2 0 319 #define CLK_BASE__INST4_SEG3 0 320 #define CLK_BASE__INST4_SEG4 0 321 #define CLK_BASE__INST4_SEG5 0 322 323 #define CLK_BASE__INST5_SEG0 0x0001B200 324 #define CLK_BASE__INST5_SEG1 0x0242DC00 325 #define CLK_BASE__INST5_SEG2 0 326 #define CLK_BASE__INST5_SEG3 0 327 #define CLK_BASE__INST5_SEG4 0 328 #define CLK_BASE__INST5_SEG5 0 329 330 #define CLK_BASE__INST6_SEG0 0x0001B400 331 #define CLK_BASE__INST6_SEG1 0x0242E000 332 #define CLK_BASE__INST6_SEG2 0 333 #define CLK_BASE__INST6_SEG3 0 334 #define CLK_BASE__INST6_SEG4 0 335 #define CLK_BASE__INST6_SEG5 0 336 337 #define DBGU_IO_BASE__INST0_SEG0 0x000001E0 338 #define DBGU_IO_BASE__INST0_SEG1 0x00000260 339 #define DBGU_IO_BASE__INST0_SEG2 0x00000280 340 #define DBGU_IO_BASE__INST0_SEG3 0x0240B400 341 #define DBGU_IO_BASE__INST0_SEG4 0x02413C00 342 #define DBGU_IO_BASE__INST0_SEG5 0x02416000 343 344 #define DBGU_IO_BASE__INST1_SEG0 0 345 #define DBGU_IO_BASE__INST1_SEG1 0 346 #define DBGU_IO_BASE__INST1_SEG2 0 347 #define DBGU_IO_BASE__INST1_SEG3 0 348 #define DBGU_IO_BASE__INST1_SEG4 0 349 #define DBGU_IO_BASE__INST1_SEG5 0 350 351 #define DBGU_IO_BASE__INST2_SEG0 0 352 #define DBGU_IO_BASE__INST2_SEG1 0 353 #define DBGU_IO_BASE__INST2_SEG2 0 354 #define DBGU_IO_BASE__INST2_SEG3 0 355 #define DBGU_IO_BASE__INST2_SEG4 0 356 #define DBGU_IO_BASE__INST2_SEG5 0 357 358 #define DBGU_IO_BASE__INST3_SEG0 0 359 #define DBGU_IO_BASE__INST3_SEG1 0 360 #define DBGU_IO_BASE__INST3_SEG2 0 361 #define DBGU_IO_BASE__INST3_SEG3 0 362 #define DBGU_IO_BASE__INST3_SEG4 0 363 #define DBGU_IO_BASE__INST3_SEG5 0 364 365 #define DBGU_IO_BASE__INST4_SEG0 0 366 #define DBGU_IO_BASE__INST4_SEG1 0 367 #define DBGU_IO_BASE__INST4_SEG2 0 368 #define DBGU_IO_BASE__INST4_SEG3 0 369 #define DBGU_IO_BASE__INST4_SEG4 0 370 #define DBGU_IO_BASE__INST4_SEG5 0 371 372 #define DBGU_IO_BASE__INST5_SEG0 0 373 #define DBGU_IO_BASE__INST5_SEG1 0 374 #define DBGU_IO_BASE__INST5_SEG2 0 375 #define DBGU_IO_BASE__INST5_SEG3 0 376 #define DBGU_IO_BASE__INST5_SEG4 0 377 #define DBGU_IO_BASE__INST5_SEG5 0 378 379 #define DBGU_IO_BASE__INST6_SEG0 0 380 #define DBGU_IO_BASE__INST6_SEG1 0 381 #define DBGU_IO_BASE__INST6_SEG2 0 382 #define DBGU_IO_BASE__INST6_SEG3 0 383 #define DBGU_IO_BASE__INST6_SEG4 0 384 #define DBGU_IO_BASE__INST6_SEG5 0 385 386 #define DCN_BASE__INST0_SEG0 0x00000012 387 #define DCN_BASE__INST0_SEG1 0x000000C0 388 #define DCN_BASE__INST0_SEG2 0x000034C0 389 #define DCN_BASE__INST0_SEG3 0x00009000 390 #define DCN_BASE__INST0_SEG4 0x02403C00 391 #define DCN_BASE__INST0_SEG5 0 392 393 #define DCN_BASE__INST1_SEG0 0 394 #define DCN_BASE__INST1_SEG1 0 395 #define DCN_BASE__INST1_SEG2 0 396 #define DCN_BASE__INST1_SEG3 0 397 #define DCN_BASE__INST1_SEG4 0 398 #define DCN_BASE__INST1_SEG5 0 399 400 #define DCN_BASE__INST2_SEG0 0 401 #define DCN_BASE__INST2_SEG1 0 402 #define DCN_BASE__INST2_SEG2 0 403 #define DCN_BASE__INST2_SEG3 0 404 #define DCN_BASE__INST2_SEG4 0 405 #define DCN_BASE__INST2_SEG5 0 406 407 #define DCN_BASE__INST3_SEG0 0 408 #define DCN_BASE__INST3_SEG1 0 409 #define DCN_BASE__INST3_SEG2 0 410 #define DCN_BASE__INST3_SEG3 0 411 #define DCN_BASE__INST3_SEG4 0 412 #define DCN_BASE__INST3_SEG5 0 413 414 #define DCN_BASE__INST4_SEG0 0 415 #define DCN_BASE__INST4_SEG1 0 416 #define DCN_BASE__INST4_SEG2 0 417 #define DCN_BASE__INST4_SEG3 0 418 #define DCN_BASE__INST4_SEG4 0 419 #define DCN_BASE__INST4_SEG5 0 420 421 #define DCN_BASE__INST5_SEG0 0 422 #define DCN_BASE__INST5_SEG1 0 423 #define DCN_BASE__INST5_SEG2 0 424 #define DCN_BASE__INST5_SEG3 0 425 #define DCN_BASE__INST5_SEG4 0 426 #define DCN_BASE__INST5_SEG5 0 427 428 #define DCN_BASE__INST6_SEG0 0 429 #define DCN_BASE__INST6_SEG1 0 430 #define DCN_BASE__INST6_SEG2 0 431 #define DCN_BASE__INST6_SEG3 0 432 #define DCN_BASE__INST6_SEG4 0 433 #define DCN_BASE__INST6_SEG5 0 434 435 #define DPCS_BASE__INST0_SEG0 0x00000012 436 #define DPCS_BASE__INST0_SEG1 0x000000C0 437 #define DPCS_BASE__INST0_SEG2 0x000034C0 438 #define DPCS_BASE__INST0_SEG3 0x00009000 439 #define DPCS_BASE__INST0_SEG4 0x02403C00 440 #define DPCS_BASE__INST0_SEG5 0 441 442 #define DPCS_BASE__INST1_SEG0 0 443 #define DPCS_BASE__INST1_SEG1 0 444 #define DPCS_BASE__INST1_SEG2 0 445 #define DPCS_BASE__INST1_SEG3 0 446 #define DPCS_BASE__INST1_SEG4 0 447 #define DPCS_BASE__INST1_SEG5 0 448 449 #define DPCS_BASE__INST2_SEG0 0 450 #define DPCS_BASE__INST2_SEG1 0 451 #define DPCS_BASE__INST2_SEG2 0 452 #define DPCS_BASE__INST2_SEG3 0 453 #define DPCS_BASE__INST2_SEG4 0 454 #define DPCS_BASE__INST2_SEG5 0 455 456 #define DPCS_BASE__INST3_SEG0 0 457 #define DPCS_BASE__INST3_SEG1 0 458 #define DPCS_BASE__INST3_SEG2 0 459 #define DPCS_BASE__INST3_SEG3 0 460 #define DPCS_BASE__INST3_SEG4 0 461 #define DPCS_BASE__INST3_SEG5 0 462 463 #define DPCS_BASE__INST4_SEG0 0 464 #define DPCS_BASE__INST4_SEG1 0 465 #define DPCS_BASE__INST4_SEG2 0 466 #define DPCS_BASE__INST4_SEG3 0 467 #define DPCS_BASE__INST4_SEG4 0 468 #define DPCS_BASE__INST4_SEG5 0 469 470 #define DPCS_BASE__INST5_SEG0 0 471 #define DPCS_BASE__INST5_SEG1 0 472 #define DPCS_BASE__INST5_SEG2 0 473 #define DPCS_BASE__INST5_SEG3 0 474 #define DPCS_BASE__INST5_SEG4 0 475 #define DPCS_BASE__INST5_SEG5 0 476 477 #define DPCS_BASE__INST6_SEG0 0 478 #define DPCS_BASE__INST6_SEG1 0 479 #define DPCS_BASE__INST6_SEG2 0 480 #define DPCS_BASE__INST6_SEG3 0 481 #define DPCS_BASE__INST6_SEG4 0 482 #define DPCS_BASE__INST6_SEG5 0 483 484 #define DF_BASE__INST0_SEG0 0x00007000 485 #define DF_BASE__INST0_SEG1 0x0240B800 486 #define DF_BASE__INST0_SEG2 0x02447800 487 #define DF_BASE__INST0_SEG3 0x00C00000 488 #define DF_BASE__INST0_SEG4 0x03640000 489 #define DF_BASE__INST0_SEG5 0 490 491 #define DF_BASE__INST1_SEG0 0 492 #define DF_BASE__INST1_SEG1 0 493 #define DF_BASE__INST1_SEG2 0 494 #define DF_BASE__INST1_SEG3 0 495 #define DF_BASE__INST1_SEG4 0 496 #define DF_BASE__INST1_SEG5 0 497 498 #define DF_BASE__INST2_SEG0 0 499 #define DF_BASE__INST2_SEG1 0 500 #define DF_BASE__INST2_SEG2 0 501 #define DF_BASE__INST2_SEG3 0 502 #define DF_BASE__INST2_SEG4 0 503 #define DF_BASE__INST2_SEG5 0 504 505 #define DF_BASE__INST3_SEG0 0 506 #define DF_BASE__INST3_SEG1 0 507 #define DF_BASE__INST3_SEG2 0 508 #define DF_BASE__INST3_SEG3 0 509 #define DF_BASE__INST3_SEG4 0 510 #define DF_BASE__INST3_SEG5 0 511 512 #define DF_BASE__INST4_SEG0 0 513 #define DF_BASE__INST4_SEG1 0 514 #define DF_BASE__INST4_SEG2 0 515 #define DF_BASE__INST4_SEG3 0 516 #define DF_BASE__INST4_SEG4 0 517 #define DF_BASE__INST4_SEG5 0 518 519 #define DF_BASE__INST5_SEG0 0 520 #define DF_BASE__INST5_SEG1 0 521 #define DF_BASE__INST5_SEG2 0 522 #define DF_BASE__INST5_SEG3 0 523 #define DF_BASE__INST5_SEG4 0 524 #define DF_BASE__INST5_SEG5 0 525 526 #define DF_BASE__INST6_SEG0 0 527 #define DF_BASE__INST6_SEG1 0 528 #define DF_BASE__INST6_SEG2 0 529 #define DF_BASE__INST6_SEG3 0 530 #define DF_BASE__INST6_SEG4 0 531 #define DF_BASE__INST6_SEG5 0 532 533 #define FCH_BASE__INST0_SEG0 0x0240C000 534 #define FCH_BASE__INST0_SEG1 0x00B40000 535 #define FCH_BASE__INST0_SEG2 0x11000000 536 #define FCH_BASE__INST0_SEG3 0 537 #define FCH_BASE__INST0_SEG4 0 538 #define FCH_BASE__INST0_SEG5 0 539 540 #define FCH_BASE__INST1_SEG0 0 541 #define FCH_BASE__INST1_SEG1 0 542 #define FCH_BASE__INST1_SEG2 0 543 #define FCH_BASE__INST1_SEG3 0 544 #define FCH_BASE__INST1_SEG4 0 545 #define FCH_BASE__INST1_SEG5 0 546 547 #define FCH_BASE__INST2_SEG0 0 548 #define FCH_BASE__INST2_SEG1 0 549 #define FCH_BASE__INST2_SEG2 0 550 #define FCH_BASE__INST2_SEG3 0 551 #define FCH_BASE__INST2_SEG4 0 552 #define FCH_BASE__INST2_SEG5 0 553 554 #define FCH_BASE__INST3_SEG0 0 555 #define FCH_BASE__INST3_SEG1 0 556 #define FCH_BASE__INST3_SEG2 0 557 #define FCH_BASE__INST3_SEG3 0 558 #define FCH_BASE__INST3_SEG4 0 559 #define FCH_BASE__INST3_SEG5 0 560 561 #define FCH_BASE__INST4_SEG0 0 562 #define FCH_BASE__INST4_SEG1 0 563 #define FCH_BASE__INST4_SEG2 0 564 #define FCH_BASE__INST4_SEG3 0 565 #define FCH_BASE__INST4_SEG4 0 566 #define FCH_BASE__INST4_SEG5 0 567 568 #define FCH_BASE__INST5_SEG0 0 569 #define FCH_BASE__INST5_SEG1 0 570 #define FCH_BASE__INST5_SEG2 0 571 #define FCH_BASE__INST5_SEG3 0 572 #define FCH_BASE__INST5_SEG4 0 573 #define FCH_BASE__INST5_SEG5 0 574 575 #define FCH_BASE__INST6_SEG0 0 576 #define FCH_BASE__INST6_SEG1 0 577 #define FCH_BASE__INST6_SEG2 0 578 #define FCH_BASE__INST6_SEG3 0 579 #define FCH_BASE__INST6_SEG4 0 580 #define FCH_BASE__INST6_SEG5 0 581 582 #define FUSE_BASE__INST0_SEG0 0x00017400 583 #define FUSE_BASE__INST0_SEG1 0x02401400 584 #define FUSE_BASE__INST0_SEG2 0 585 #define FUSE_BASE__INST0_SEG3 0 586 #define FUSE_BASE__INST0_SEG4 0 587 #define FUSE_BASE__INST0_SEG5 0 588 589 #define FUSE_BASE__INST1_SEG0 0 590 #define FUSE_BASE__INST1_SEG1 0 591 #define FUSE_BASE__INST1_SEG2 0 592 #define FUSE_BASE__INST1_SEG3 0 593 #define FUSE_BASE__INST1_SEG4 0 594 #define FUSE_BASE__INST1_SEG5 0 595 596 #define FUSE_BASE__INST2_SEG0 0 597 #define FUSE_BASE__INST2_SEG1 0 598 #define FUSE_BASE__INST2_SEG2 0 599 #define FUSE_BASE__INST2_SEG3 0 600 #define FUSE_BASE__INST2_SEG4 0 601 #define FUSE_BASE__INST2_SEG5 0 602 603 #define FUSE_BASE__INST3_SEG0 0 604 #define FUSE_BASE__INST3_SEG1 0 605 #define FUSE_BASE__INST3_SEG2 0 606 #define FUSE_BASE__INST3_SEG3 0 607 #define FUSE_BASE__INST3_SEG4 0 608 #define FUSE_BASE__INST3_SEG5 0 609 610 #define FUSE_BASE__INST4_SEG0 0 611 #define FUSE_BASE__INST4_SEG1 0 612 #define FUSE_BASE__INST4_SEG2 0 613 #define FUSE_BASE__INST4_SEG3 0 614 #define FUSE_BASE__INST4_SEG4 0 615 #define FUSE_BASE__INST4_SEG5 0 616 617 #define FUSE_BASE__INST5_SEG0 0 618 #define FUSE_BASE__INST5_SEG1 0 619 #define FUSE_BASE__INST5_SEG2 0 620 #define FUSE_BASE__INST5_SEG3 0 621 #define FUSE_BASE__INST5_SEG4 0 622 #define FUSE_BASE__INST5_SEG5 0 623 624 #define FUSE_BASE__INST6_SEG0 0 625 #define FUSE_BASE__INST6_SEG1 0 626 #define FUSE_BASE__INST6_SEG2 0 627 #define FUSE_BASE__INST6_SEG3 0 628 #define FUSE_BASE__INST6_SEG4 0 629 #define FUSE_BASE__INST6_SEG5 0 630 631 #define GC_BASE__INST0_SEG0 0x00001260 632 #define GC_BASE__INST0_SEG1 0x0000A000 633 #define GC_BASE__INST0_SEG2 0x02402C00 634 #define GC_BASE__INST0_SEG3 0 635 #define GC_BASE__INST0_SEG4 0 636 #define GC_BASE__INST0_SEG5 0 637 638 #define GC_BASE__INST1_SEG0 0 639 #define GC_BASE__INST1_SEG1 0 640 #define GC_BASE__INST1_SEG2 0 641 #define GC_BASE__INST1_SEG3 0 642 #define GC_BASE__INST1_SEG4 0 643 #define GC_BASE__INST1_SEG5 0 644 645 #define GC_BASE__INST2_SEG0 0 646 #define GC_BASE__INST2_SEG1 0 647 #define GC_BASE__INST2_SEG2 0 648 #define GC_BASE__INST2_SEG3 0 649 #define GC_BASE__INST2_SEG4 0 650 #define GC_BASE__INST2_SEG5 0 651 652 #define GC_BASE__INST3_SEG0 0 653 #define GC_BASE__INST3_SEG1 0 654 #define GC_BASE__INST3_SEG2 0 655 #define GC_BASE__INST3_SEG3 0 656 #define GC_BASE__INST3_SEG4 0 657 #define GC_BASE__INST3_SEG5 0 658 659 #define GC_BASE__INST4_SEG0 0 660 #define GC_BASE__INST4_SEG1 0 661 #define GC_BASE__INST4_SEG2 0 662 #define GC_BASE__INST4_SEG3 0 663 #define GC_BASE__INST4_SEG4 0 664 #define GC_BASE__INST4_SEG5 0 665 666 #define GC_BASE__INST5_SEG0 0 667 #define GC_BASE__INST5_SEG1 0 668 #define GC_BASE__INST5_SEG2 0 669 #define GC_BASE__INST5_SEG3 0 670 #define GC_BASE__INST5_SEG4 0 671 #define GC_BASE__INST5_SEG5 0 672 673 #define GC_BASE__INST6_SEG0 0 674 #define GC_BASE__INST6_SEG1 0 675 #define GC_BASE__INST6_SEG2 0 676 #define GC_BASE__INST6_SEG3 0 677 #define GC_BASE__INST6_SEG4 0 678 #define GC_BASE__INST6_SEG5 0 679 680 #define HDP_BASE__INST0_SEG0 0x00000F20 681 #define HDP_BASE__INST0_SEG1 0x0240A400 682 #define HDP_BASE__INST0_SEG2 0 683 #define HDP_BASE__INST0_SEG3 0 684 #define HDP_BASE__INST0_SEG4 0 685 #define HDP_BASE__INST0_SEG5 0 686 687 #define HDP_BASE__INST1_SEG0 0 688 #define HDP_BASE__INST1_SEG1 0 689 #define HDP_BASE__INST1_SEG2 0 690 #define HDP_BASE__INST1_SEG3 0 691 #define HDP_BASE__INST1_SEG4 0 692 #define HDP_BASE__INST1_SEG5 0 693 694 #define HDP_BASE__INST2_SEG0 0 695 #define HDP_BASE__INST2_SEG1 0 696 #define HDP_BASE__INST2_SEG2 0 697 #define HDP_BASE__INST2_SEG3 0 698 #define HDP_BASE__INST2_SEG4 0 699 #define HDP_BASE__INST2_SEG5 0 700 701 #define HDP_BASE__INST3_SEG0 0 702 #define HDP_BASE__INST3_SEG1 0 703 #define HDP_BASE__INST3_SEG2 0 704 #define HDP_BASE__INST3_SEG3 0 705 #define HDP_BASE__INST3_SEG4 0 706 #define HDP_BASE__INST3_SEG5 0 707 708 #define HDP_BASE__INST4_SEG0 0 709 #define HDP_BASE__INST4_SEG1 0 710 #define HDP_BASE__INST4_SEG2 0 711 #define HDP_BASE__INST4_SEG3 0 712 #define HDP_BASE__INST4_SEG4 0 713 #define HDP_BASE__INST4_SEG5 0 714 715 #define HDP_BASE__INST5_SEG0 0 716 #define HDP_BASE__INST5_SEG1 0 717 #define HDP_BASE__INST5_SEG2 0 718 #define HDP_BASE__INST5_SEG3 0 719 #define HDP_BASE__INST5_SEG4 0 720 #define HDP_BASE__INST5_SEG5 0 721 722 #define HDP_BASE__INST6_SEG0 0 723 #define HDP_BASE__INST6_SEG1 0 724 #define HDP_BASE__INST6_SEG2 0 725 #define HDP_BASE__INST6_SEG3 0 726 #define HDP_BASE__INST6_SEG4 0 727 #define HDP_BASE__INST6_SEG5 0 728 729 #define IOHC0_BASE__INST0_SEG0 0x00010000 730 #define IOHC0_BASE__INST0_SEG1 0x02406000 731 #define IOHC0_BASE__INST0_SEG2 0x04EC0000 732 #define IOHC0_BASE__INST0_SEG3 0 733 #define IOHC0_BASE__INST0_SEG4 0 734 #define IOHC0_BASE__INST0_SEG5 0 735 736 #define IOHC0_BASE__INST1_SEG0 0 737 #define IOHC0_BASE__INST1_SEG1 0 738 #define IOHC0_BASE__INST1_SEG2 0 739 #define IOHC0_BASE__INST1_SEG3 0 740 #define IOHC0_BASE__INST1_SEG4 0 741 #define IOHC0_BASE__INST1_SEG5 0 742 743 #define IOHC0_BASE__INST2_SEG0 0 744 #define IOHC0_BASE__INST2_SEG1 0 745 #define IOHC0_BASE__INST2_SEG2 0 746 #define IOHC0_BASE__INST2_SEG3 0 747 #define IOHC0_BASE__INST2_SEG4 0 748 #define IOHC0_BASE__INST2_SEG5 0 749 750 #define IOHC0_BASE__INST3_SEG0 0 751 #define IOHC0_BASE__INST3_SEG1 0 752 #define IOHC0_BASE__INST3_SEG2 0 753 #define IOHC0_BASE__INST3_SEG3 0 754 #define IOHC0_BASE__INST3_SEG4 0 755 #define IOHC0_BASE__INST3_SEG5 0 756 757 #define IOHC0_BASE__INST4_SEG0 0 758 #define IOHC0_BASE__INST4_SEG1 0 759 #define IOHC0_BASE__INST4_SEG2 0 760 #define IOHC0_BASE__INST4_SEG3 0 761 #define IOHC0_BASE__INST4_SEG4 0 762 #define IOHC0_BASE__INST4_SEG5 0 763 764 #define IOHC0_BASE__INST5_SEG0 0 765 #define IOHC0_BASE__INST5_SEG1 0 766 #define IOHC0_BASE__INST5_SEG2 0 767 #define IOHC0_BASE__INST5_SEG3 0 768 #define IOHC0_BASE__INST5_SEG4 0 769 #define IOHC0_BASE__INST5_SEG5 0 770 771 #define IOHC0_BASE__INST6_SEG0 0 772 #define IOHC0_BASE__INST6_SEG1 0 773 #define IOHC0_BASE__INST6_SEG2 0 774 #define IOHC0_BASE__INST6_SEG3 0 775 #define IOHC0_BASE__INST6_SEG4 0 776 #define IOHC0_BASE__INST6_SEG5 0 777 778 #define MMHUB_BASE__INST0_SEG0 0x00013200 779 #define MMHUB_BASE__INST0_SEG1 0x0001A000 780 #define MMHUB_BASE__INST0_SEG2 0x02408800 781 #define MMHUB_BASE__INST0_SEG3 0 782 #define MMHUB_BASE__INST0_SEG4 0 783 #define MMHUB_BASE__INST0_SEG5 0 784 785 #define MMHUB_BASE__INST1_SEG0 0 786 #define MMHUB_BASE__INST1_SEG1 0 787 #define MMHUB_BASE__INST1_SEG2 0 788 #define MMHUB_BASE__INST1_SEG3 0 789 #define MMHUB_BASE__INST1_SEG4 0 790 #define MMHUB_BASE__INST1_SEG5 0 791 792 #define MMHUB_BASE__INST2_SEG0 0 793 #define MMHUB_BASE__INST2_SEG1 0 794 #define MMHUB_BASE__INST2_SEG2 0 795 #define MMHUB_BASE__INST2_SEG3 0 796 #define MMHUB_BASE__INST2_SEG4 0 797 #define MMHUB_BASE__INST2_SEG5 0 798 799 #define MMHUB_BASE__INST3_SEG0 0 800 #define MMHUB_BASE__INST3_SEG1 0 801 #define MMHUB_BASE__INST3_SEG2 0 802 #define MMHUB_BASE__INST3_SEG3 0 803 #define MMHUB_BASE__INST3_SEG4 0 804 #define MMHUB_BASE__INST3_SEG5 0 805 806 #define MMHUB_BASE__INST4_SEG0 0 807 #define MMHUB_BASE__INST4_SEG1 0 808 #define MMHUB_BASE__INST4_SEG2 0 809 #define MMHUB_BASE__INST4_SEG3 0 810 #define MMHUB_BASE__INST4_SEG4 0 811 #define MMHUB_BASE__INST4_SEG5 0 812 813 #define MMHUB_BASE__INST5_SEG0 0 814 #define MMHUB_BASE__INST5_SEG1 0 815 #define MMHUB_BASE__INST5_SEG2 0 816 #define MMHUB_BASE__INST5_SEG3 0 817 #define MMHUB_BASE__INST5_SEG4 0 818 #define MMHUB_BASE__INST5_SEG5 0 819 820 #define MMHUB_BASE__INST6_SEG0 0 821 #define MMHUB_BASE__INST6_SEG1 0 822 #define MMHUB_BASE__INST6_SEG2 0 823 #define MMHUB_BASE__INST6_SEG3 0 824 #define MMHUB_BASE__INST6_SEG4 0 825 #define MMHUB_BASE__INST6_SEG5 0 826 827 #define MP0_BASE__INST0_SEG0 0x00016000 828 #define MP0_BASE__INST0_SEG1 0x0243FC00 829 #define MP0_BASE__INST0_SEG2 0x00DC0000 830 #define MP0_BASE__INST0_SEG3 0x00E00000 831 #define MP0_BASE__INST0_SEG4 0x00E40000 832 #define MP0_BASE__INST0_SEG5 0 833 834 #define MP0_BASE__INST1_SEG0 0 835 #define MP0_BASE__INST1_SEG1 0 836 #define MP0_BASE__INST1_SEG2 0 837 #define MP0_BASE__INST1_SEG3 0 838 #define MP0_BASE__INST1_SEG4 0 839 #define MP0_BASE__INST1_SEG5 0 840 841 #define MP0_BASE__INST2_SEG0 0 842 #define MP0_BASE__INST2_SEG1 0 843 #define MP0_BASE__INST2_SEG2 0 844 #define MP0_BASE__INST2_SEG3 0 845 #define MP0_BASE__INST2_SEG4 0 846 #define MP0_BASE__INST2_SEG5 0 847 848 #define MP0_BASE__INST3_SEG0 0 849 #define MP0_BASE__INST3_SEG1 0 850 #define MP0_BASE__INST3_SEG2 0 851 #define MP0_BASE__INST3_SEG3 0 852 #define MP0_BASE__INST3_SEG4 0 853 #define MP0_BASE__INST3_SEG5 0 854 855 #define MP0_BASE__INST4_SEG0 0 856 #define MP0_BASE__INST4_SEG1 0 857 #define MP0_BASE__INST4_SEG2 0 858 #define MP0_BASE__INST4_SEG3 0 859 #define MP0_BASE__INST4_SEG4 0 860 #define MP0_BASE__INST4_SEG5 0 861 862 #define MP0_BASE__INST5_SEG0 0 863 #define MP0_BASE__INST5_SEG1 0 864 #define MP0_BASE__INST5_SEG2 0 865 #define MP0_BASE__INST5_SEG3 0 866 #define MP0_BASE__INST5_SEG4 0 867 #define MP0_BASE__INST5_SEG5 0 868 869 #define MP0_BASE__INST6_SEG0 0 870 #define MP0_BASE__INST6_SEG1 0 871 #define MP0_BASE__INST6_SEG2 0 872 #define MP0_BASE__INST6_SEG3 0 873 #define MP0_BASE__INST6_SEG4 0 874 #define MP0_BASE__INST6_SEG5 0 875 876 #define MP1_BASE__INST0_SEG0 0x00016000 877 #define MP1_BASE__INST0_SEG1 0x0243FC00 878 #define MP1_BASE__INST0_SEG2 0x00DC0000 879 #define MP1_BASE__INST0_SEG3 0x00E00000 880 #define MP1_BASE__INST0_SEG4 0x00E40000 881 #define MP1_BASE__INST0_SEG5 0 882 883 #define MP1_BASE__INST1_SEG0 0 884 #define MP1_BASE__INST1_SEG1 0 885 #define MP1_BASE__INST1_SEG2 0 886 #define MP1_BASE__INST1_SEG3 0 887 #define MP1_BASE__INST1_SEG4 0 888 #define MP1_BASE__INST1_SEG5 0 889 890 #define MP1_BASE__INST2_SEG0 0 891 #define MP1_BASE__INST2_SEG1 0 892 #define MP1_BASE__INST2_SEG2 0 893 #define MP1_BASE__INST2_SEG3 0 894 #define MP1_BASE__INST2_SEG4 0 895 #define MP1_BASE__INST2_SEG5 0 896 897 #define MP1_BASE__INST3_SEG0 0 898 #define MP1_BASE__INST3_SEG1 0 899 #define MP1_BASE__INST3_SEG2 0 900 #define MP1_BASE__INST3_SEG3 0 901 #define MP1_BASE__INST3_SEG4 0 902 #define MP1_BASE__INST3_SEG5 0 903 904 #define MP1_BASE__INST4_SEG0 0 905 #define MP1_BASE__INST4_SEG1 0 906 #define MP1_BASE__INST4_SEG2 0 907 #define MP1_BASE__INST4_SEG3 0 908 #define MP1_BASE__INST4_SEG4 0 909 #define MP1_BASE__INST4_SEG5 0 910 911 #define MP1_BASE__INST5_SEG0 0 912 #define MP1_BASE__INST5_SEG1 0 913 #define MP1_BASE__INST5_SEG2 0 914 #define MP1_BASE__INST5_SEG3 0 915 #define MP1_BASE__INST5_SEG4 0 916 #define MP1_BASE__INST5_SEG5 0 917 918 #define MP1_BASE__INST6_SEG0 0 919 #define MP1_BASE__INST6_SEG1 0 920 #define MP1_BASE__INST6_SEG2 0 921 #define MP1_BASE__INST6_SEG3 0 922 #define MP1_BASE__INST6_SEG4 0 923 #define MP1_BASE__INST6_SEG5 0 924 925 #define MP2_BASE__INST0_SEG0 0x00016000 926 #define MP2_BASE__INST0_SEG1 0x0243FC00 927 #define MP2_BASE__INST0_SEG2 0x00DC0000 928 #define MP2_BASE__INST0_SEG3 0x00E00000 929 #define MP2_BASE__INST0_SEG4 0x00E40000 930 #define MP2_BASE__INST0_SEG5 0 931 932 #define MP2_BASE__INST1_SEG0 0 933 #define MP2_BASE__INST1_SEG1 0 934 #define MP2_BASE__INST1_SEG2 0 935 #define MP2_BASE__INST1_SEG3 0 936 #define MP2_BASE__INST1_SEG4 0 937 #define MP2_BASE__INST1_SEG5 0 938 939 #define MP2_BASE__INST2_SEG0 0 940 #define MP2_BASE__INST2_SEG1 0 941 #define MP2_BASE__INST2_SEG2 0 942 #define MP2_BASE__INST2_SEG3 0 943 #define MP2_BASE__INST2_SEG4 0 944 #define MP2_BASE__INST2_SEG5 0 945 946 #define MP2_BASE__INST3_SEG0 0 947 #define MP2_BASE__INST3_SEG1 0 948 #define MP2_BASE__INST3_SEG2 0 949 #define MP2_BASE__INST3_SEG3 0 950 #define MP2_BASE__INST3_SEG4 0 951 #define MP2_BASE__INST3_SEG5 0 952 953 #define MP2_BASE__INST4_SEG0 0 954 #define MP2_BASE__INST4_SEG1 0 955 #define MP2_BASE__INST4_SEG2 0 956 #define MP2_BASE__INST4_SEG3 0 957 #define MP2_BASE__INST4_SEG4 0 958 #define MP2_BASE__INST4_SEG5 0 959 960 #define MP2_BASE__INST5_SEG0 0 961 #define MP2_BASE__INST5_SEG1 0 962 #define MP2_BASE__INST5_SEG2 0 963 #define MP2_BASE__INST5_SEG3 0 964 #define MP2_BASE__INST5_SEG4 0 965 #define MP2_BASE__INST5_SEG5 0 966 967 #define MP2_BASE__INST6_SEG0 0 968 #define MP2_BASE__INST6_SEG1 0 969 #define MP2_BASE__INST6_SEG2 0 970 #define MP2_BASE__INST6_SEG3 0 971 #define MP2_BASE__INST6_SEG4 0 972 #define MP2_BASE__INST6_SEG5 0 973 974 #define NBIO_BASE__INST0_SEG0 0x00000000 975 #define NBIO_BASE__INST0_SEG1 0x00000014 976 #define NBIO_BASE__INST0_SEG2 0x00000D20 977 #define NBIO_BASE__INST0_SEG3 0x00010400 978 #define NBIO_BASE__INST0_SEG4 0x0241B000 979 #define NBIO_BASE__INST0_SEG5 0x04040000 980 981 #define NBIO_BASE__INST1_SEG0 0 982 #define NBIO_BASE__INST1_SEG1 0 983 #define NBIO_BASE__INST1_SEG2 0 984 #define NBIO_BASE__INST1_SEG3 0 985 #define NBIO_BASE__INST1_SEG4 0 986 #define NBIO_BASE__INST1_SEG5 0 987 988 #define NBIO_BASE__INST2_SEG0 0 989 #define NBIO_BASE__INST2_SEG1 0 990 #define NBIO_BASE__INST2_SEG2 0 991 #define NBIO_BASE__INST2_SEG3 0 992 #define NBIO_BASE__INST2_SEG4 0 993 #define NBIO_BASE__INST2_SEG5 0 994 995 #define NBIO_BASE__INST3_SEG0 0 996 #define NBIO_BASE__INST3_SEG1 0 997 #define NBIO_BASE__INST3_SEG2 0 998 #define NBIO_BASE__INST3_SEG3 0 999 #define NBIO_BASE__INST3_SEG4 0 1000 #define NBIO_BASE__INST3_SEG5 0 1001 1002 #define NBIO_BASE__INST4_SEG0 0 1003 #define NBIO_BASE__INST4_SEG1 0 1004 #define NBIO_BASE__INST4_SEG2 0 1005 #define NBIO_BASE__INST4_SEG3 0 1006 #define NBIO_BASE__INST4_SEG4 0 1007 #define NBIO_BASE__INST4_SEG5 0 1008 1009 #define NBIO_BASE__INST5_SEG0 0 1010 #define NBIO_BASE__INST5_SEG1 0 1011 #define NBIO_BASE__INST5_SEG2 0 1012 #define NBIO_BASE__INST5_SEG3 0 1013 #define NBIO_BASE__INST5_SEG4 0 1014 #define NBIO_BASE__INST5_SEG5 0 1015 1016 #define NBIO_BASE__INST6_SEG0 0 1017 #define NBIO_BASE__INST6_SEG1 0 1018 #define NBIO_BASE__INST6_SEG2 0 1019 #define NBIO_BASE__INST6_SEG3 0 1020 #define NBIO_BASE__INST6_SEG4 0 1021 #define NBIO_BASE__INST6_SEG5 0 1022 1023 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 1024 #define OSSSYS_BASE__INST0_SEG1 0x0240A000 1025 #define OSSSYS_BASE__INST0_SEG2 0 1026 #define OSSSYS_BASE__INST0_SEG3 0 1027 #define OSSSYS_BASE__INST0_SEG4 0 1028 #define OSSSYS_BASE__INST0_SEG5 0 1029 1030 #define OSSSYS_BASE__INST1_SEG0 0 1031 #define OSSSYS_BASE__INST1_SEG1 0 1032 #define OSSSYS_BASE__INST1_SEG2 0 1033 #define OSSSYS_BASE__INST1_SEG3 0 1034 #define OSSSYS_BASE__INST1_SEG4 0 1035 #define OSSSYS_BASE__INST1_SEG5 0 1036 1037 #define OSSSYS_BASE__INST2_SEG0 0 1038 #define OSSSYS_BASE__INST2_SEG1 0 1039 #define OSSSYS_BASE__INST2_SEG2 0 1040 #define OSSSYS_BASE__INST2_SEG3 0 1041 #define OSSSYS_BASE__INST2_SEG4 0 1042 #define OSSSYS_BASE__INST2_SEG5 0 1043 1044 #define OSSSYS_BASE__INST3_SEG0 0 1045 #define OSSSYS_BASE__INST3_SEG1 0 1046 #define OSSSYS_BASE__INST3_SEG2 0 1047 #define OSSSYS_BASE__INST3_SEG3 0 1048 #define OSSSYS_BASE__INST3_SEG4 0 1049 #define OSSSYS_BASE__INST3_SEG5 0 1050 1051 #define OSSSYS_BASE__INST4_SEG0 0 1052 #define OSSSYS_BASE__INST4_SEG1 0 1053 #define OSSSYS_BASE__INST4_SEG2 0 1054 #define OSSSYS_BASE__INST4_SEG3 0 1055 #define OSSSYS_BASE__INST4_SEG4 0 1056 #define OSSSYS_BASE__INST4_SEG5 0 1057 1058 #define OSSSYS_BASE__INST5_SEG0 0 1059 #define OSSSYS_BASE__INST5_SEG1 0 1060 #define OSSSYS_BASE__INST5_SEG2 0 1061 #define OSSSYS_BASE__INST5_SEG3 0 1062 #define OSSSYS_BASE__INST5_SEG4 0 1063 #define OSSSYS_BASE__INST5_SEG5 0 1064 1065 #define OSSSYS_BASE__INST6_SEG0 0 1066 #define OSSSYS_BASE__INST6_SEG1 0 1067 #define OSSSYS_BASE__INST6_SEG2 0 1068 #define OSSSYS_BASE__INST6_SEG3 0 1069 #define OSSSYS_BASE__INST6_SEG4 0 1070 #define OSSSYS_BASE__INST6_SEG5 0 1071 1072 #define PCIE_BASE__INST0_SEG0 0x02411800 1073 #define PCIE_BASE__INST0_SEG1 0x04440000 1074 #define PCIE_BASE__INST0_SEG2 0 1075 #define PCIE_BASE__INST0_SEG3 0 1076 #define PCIE_BASE__INST0_SEG4 0 1077 #define PCIE_BASE__INST0_SEG5 0 1078 1079 #define PCIE_BASE__INST1_SEG0 0x02411C00 1080 #define PCIE_BASE__INST1_SEG1 0x04480000 1081 #define PCIE_BASE__INST1_SEG2 0 1082 #define PCIE_BASE__INST1_SEG3 0 1083 #define PCIE_BASE__INST1_SEG4 0 1084 #define PCIE_BASE__INST1_SEG5 0 1085 1086 #define PCIE_BASE__INST2_SEG0 0x02412000 1087 #define PCIE_BASE__INST2_SEG1 0x044C0000 1088 #define PCIE_BASE__INST2_SEG2 0 1089 #define PCIE_BASE__INST2_SEG3 0 1090 #define PCIE_BASE__INST2_SEG4 0 1091 #define PCIE_BASE__INST2_SEG5 0 1092 1093 #define PCIE_BASE__INST3_SEG0 0x02412400 1094 #define PCIE_BASE__INST3_SEG1 0x04500000 1095 #define PCIE_BASE__INST3_SEG2 0 1096 #define PCIE_BASE__INST3_SEG3 0 1097 #define PCIE_BASE__INST3_SEG4 0 1098 #define PCIE_BASE__INST3_SEG5 0 1099 1100 #define PCIE_BASE__INST4_SEG0 0 1101 #define PCIE_BASE__INST4_SEG1 0 1102 #define PCIE_BASE__INST4_SEG2 0 1103 #define PCIE_BASE__INST4_SEG3 0 1104 #define PCIE_BASE__INST4_SEG4 0 1105 #define PCIE_BASE__INST4_SEG5 0 1106 1107 #define PCIE_BASE__INST5_SEG0 0 1108 #define PCIE_BASE__INST5_SEG1 0 1109 #define PCIE_BASE__INST5_SEG2 0 1110 #define PCIE_BASE__INST5_SEG3 0 1111 #define PCIE_BASE__INST5_SEG4 0 1112 #define PCIE_BASE__INST5_SEG5 0 1113 1114 #define PCIE_BASE__INST6_SEG0 0 1115 #define PCIE_BASE__INST6_SEG1 0 1116 #define PCIE_BASE__INST6_SEG2 0 1117 #define PCIE_BASE__INST6_SEG3 0 1118 #define PCIE_BASE__INST6_SEG4 0 1119 #define PCIE_BASE__INST6_SEG5 0 1120 1121 #define SDMA0_BASE__INST0_SEG0 0x00001260 1122 #define SDMA0_BASE__INST0_SEG1 0x0000A000 1123 #define SDMA0_BASE__INST0_SEG2 0x02402C00 1124 #define SDMA0_BASE__INST0_SEG3 0 1125 #define SDMA0_BASE__INST0_SEG4 0 1126 #define SDMA0_BASE__INST0_SEG5 0 1127 1128 #define SDMA0_BASE__INST1_SEG0 0 1129 #define SDMA0_BASE__INST1_SEG1 0 1130 #define SDMA0_BASE__INST1_SEG2 0 1131 #define SDMA0_BASE__INST1_SEG3 0 1132 #define SDMA0_BASE__INST1_SEG4 0 1133 #define SDMA0_BASE__INST1_SEG5 0 1134 1135 #define SDMA0_BASE__INST2_SEG0 0 1136 #define SDMA0_BASE__INST2_SEG1 0 1137 #define SDMA0_BASE__INST2_SEG2 0 1138 #define SDMA0_BASE__INST2_SEG3 0 1139 #define SDMA0_BASE__INST2_SEG4 0 1140 #define SDMA0_BASE__INST2_SEG5 0 1141 1142 #define SDMA0_BASE__INST3_SEG0 0 1143 #define SDMA0_BASE__INST3_SEG1 0 1144 #define SDMA0_BASE__INST3_SEG2 0 1145 #define SDMA0_BASE__INST3_SEG3 0 1146 #define SDMA0_BASE__INST3_SEG4 0 1147 #define SDMA0_BASE__INST3_SEG5 0 1148 1149 #define SDMA0_BASE__INST4_SEG0 0 1150 #define SDMA0_BASE__INST4_SEG1 0 1151 #define SDMA0_BASE__INST4_SEG2 0 1152 #define SDMA0_BASE__INST4_SEG3 0 1153 #define SDMA0_BASE__INST4_SEG4 0 1154 #define SDMA0_BASE__INST4_SEG5 0 1155 1156 #define SDMA0_BASE__INST5_SEG0 0 1157 #define SDMA0_BASE__INST5_SEG1 0 1158 #define SDMA0_BASE__INST5_SEG2 0 1159 #define SDMA0_BASE__INST5_SEG3 0 1160 #define SDMA0_BASE__INST5_SEG4 0 1161 #define SDMA0_BASE__INST5_SEG5 0 1162 1163 #define SDMA0_BASE__INST6_SEG0 0 1164 #define SDMA0_BASE__INST6_SEG1 0 1165 #define SDMA0_BASE__INST6_SEG2 0 1166 #define SDMA0_BASE__INST6_SEG3 0 1167 #define SDMA0_BASE__INST6_SEG4 0 1168 #define SDMA0_BASE__INST6_SEG5 0 1169 1170 #define SMUIO_BASE__INST0_SEG0 0x00016800 1171 #define SMUIO_BASE__INST0_SEG1 0x00016A00 1172 #define SMUIO_BASE__INST0_SEG2 0x02401000 1173 #define SMUIO_BASE__INST0_SEG3 0x00440000 1174 #define SMUIO_BASE__INST0_SEG4 0 1175 #define SMUIO_BASE__INST0_SEG5 0 1176 1177 #define SMUIO_BASE__INST1_SEG0 0x0001BC00 1178 #define SMUIO_BASE__INST1_SEG1 0x0242D400 1179 #define SMUIO_BASE__INST1_SEG2 0 1180 #define SMUIO_BASE__INST1_SEG3 0 1181 #define SMUIO_BASE__INST1_SEG4 0 1182 #define SMUIO_BASE__INST1_SEG5 0 1183 1184 #define SMUIO_BASE__INST2_SEG0 0 1185 #define SMUIO_BASE__INST2_SEG1 0 1186 #define SMUIO_BASE__INST2_SEG2 0 1187 #define SMUIO_BASE__INST2_SEG3 0 1188 #define SMUIO_BASE__INST2_SEG4 0 1189 #define SMUIO_BASE__INST2_SEG5 0 1190 1191 #define SMUIO_BASE__INST3_SEG0 0 1192 #define SMUIO_BASE__INST3_SEG1 0 1193 #define SMUIO_BASE__INST3_SEG2 0 1194 #define SMUIO_BASE__INST3_SEG3 0 1195 #define SMUIO_BASE__INST3_SEG4 0 1196 #define SMUIO_BASE__INST3_SEG5 0 1197 1198 #define SMUIO_BASE__INST4_SEG0 0 1199 #define SMUIO_BASE__INST4_SEG1 0 1200 #define SMUIO_BASE__INST4_SEG2 0 1201 #define SMUIO_BASE__INST4_SEG3 0 1202 #define SMUIO_BASE__INST4_SEG4 0 1203 #define SMUIO_BASE__INST4_SEG5 0 1204 1205 #define SMUIO_BASE__INST5_SEG0 0 1206 #define SMUIO_BASE__INST5_SEG1 0 1207 #define SMUIO_BASE__INST5_SEG2 0 1208 #define SMUIO_BASE__INST5_SEG3 0 1209 #define SMUIO_BASE__INST5_SEG4 0 1210 #define SMUIO_BASE__INST5_SEG5 0 1211 1212 #define SMUIO_BASE__INST6_SEG0 0 1213 #define SMUIO_BASE__INST6_SEG1 0 1214 #define SMUIO_BASE__INST6_SEG2 0 1215 #define SMUIO_BASE__INST6_SEG3 0 1216 #define SMUIO_BASE__INST6_SEG4 0 1217 #define SMUIO_BASE__INST6_SEG5 0 1218 1219 #define THM_BASE__INST0_SEG0 0x00016600 1220 #define THM_BASE__INST0_SEG1 0x02400C00 1221 #define THM_BASE__INST0_SEG2 0 1222 #define THM_BASE__INST0_SEG3 0 1223 #define THM_BASE__INST0_SEG4 0 1224 #define THM_BASE__INST0_SEG5 0 1225 1226 #define THM_BASE__INST1_SEG0 0 1227 #define THM_BASE__INST1_SEG1 0 1228 #define THM_BASE__INST1_SEG2 0 1229 #define THM_BASE__INST1_SEG3 0 1230 #define THM_BASE__INST1_SEG4 0 1231 #define THM_BASE__INST1_SEG5 0 1232 1233 #define THM_BASE__INST2_SEG0 0 1234 #define THM_BASE__INST2_SEG1 0 1235 #define THM_BASE__INST2_SEG2 0 1236 #define THM_BASE__INST2_SEG3 0 1237 #define THM_BASE__INST2_SEG4 0 1238 #define THM_BASE__INST2_SEG5 0 1239 1240 #define THM_BASE__INST3_SEG0 0 1241 #define THM_BASE__INST3_SEG1 0 1242 #define THM_BASE__INST3_SEG2 0 1243 #define THM_BASE__INST3_SEG3 0 1244 #define THM_BASE__INST3_SEG4 0 1245 #define THM_BASE__INST3_SEG5 0 1246 1247 #define THM_BASE__INST4_SEG0 0 1248 #define THM_BASE__INST4_SEG1 0 1249 #define THM_BASE__INST4_SEG2 0 1250 #define THM_BASE__INST4_SEG3 0 1251 #define THM_BASE__INST4_SEG4 0 1252 #define THM_BASE__INST4_SEG5 0 1253 1254 #define THM_BASE__INST5_SEG0 0 1255 #define THM_BASE__INST5_SEG1 0 1256 #define THM_BASE__INST5_SEG2 0 1257 #define THM_BASE__INST5_SEG3 0 1258 #define THM_BASE__INST5_SEG4 0 1259 #define THM_BASE__INST5_SEG5 0 1260 1261 #define THM_BASE__INST6_SEG0 0 1262 #define THM_BASE__INST6_SEG1 0 1263 #define THM_BASE__INST6_SEG2 0 1264 #define THM_BASE__INST6_SEG3 0 1265 #define THM_BASE__INST6_SEG4 0 1266 #define THM_BASE__INST6_SEG5 0 1267 1268 #define UMC_BASE__INST0_SEG0 0x00014000 1269 #define UMC_BASE__INST0_SEG1 0x00054000 1270 #define UMC_BASE__INST0_SEG2 0x02425800 1271 #define UMC_BASE__INST0_SEG3 0x02425C00 1272 #define UMC_BASE__INST0_SEG4 0 1273 #define UMC_BASE__INST0_SEG5 0 1274 1275 #define UMC_BASE__INST1_SEG0 0x00094000 1276 #define UMC_BASE__INST1_SEG1 0x000D4000 1277 #define UMC_BASE__INST1_SEG2 0x02426000 1278 #define UMC_BASE__INST1_SEG3 0x02426400 1279 #define UMC_BASE__INST1_SEG4 0 1280 #define UMC_BASE__INST1_SEG5 0 1281 1282 #define UMC_BASE__INST2_SEG0 0 1283 #define UMC_BASE__INST2_SEG1 0 1284 #define UMC_BASE__INST2_SEG2 0 1285 #define UMC_BASE__INST2_SEG3 0 1286 #define UMC_BASE__INST2_SEG4 0 1287 #define UMC_BASE__INST2_SEG5 0 1288 1289 #define UMC_BASE__INST3_SEG0 0 1290 #define UMC_BASE__INST3_SEG1 0 1291 #define UMC_BASE__INST3_SEG2 0 1292 #define UMC_BASE__INST3_SEG3 0 1293 #define UMC_BASE__INST3_SEG4 0 1294 #define UMC_BASE__INST3_SEG5 0 1295 1296 #define UMC_BASE__INST4_SEG0 0 1297 #define UMC_BASE__INST4_SEG1 0 1298 #define UMC_BASE__INST4_SEG2 0 1299 #define UMC_BASE__INST4_SEG3 0 1300 #define UMC_BASE__INST4_SEG4 0 1301 #define UMC_BASE__INST4_SEG5 0 1302 1303 #define UMC_BASE__INST5_SEG0 0 1304 #define UMC_BASE__INST5_SEG1 0 1305 #define UMC_BASE__INST5_SEG2 0 1306 #define UMC_BASE__INST5_SEG3 0 1307 #define UMC_BASE__INST5_SEG4 0 1308 #define UMC_BASE__INST5_SEG5 0 1309 1310 #define UMC_BASE__INST6_SEG0 0 1311 #define UMC_BASE__INST6_SEG1 0 1312 #define UMC_BASE__INST6_SEG2 0 1313 #define UMC_BASE__INST6_SEG3 0 1314 #define UMC_BASE__INST6_SEG4 0 1315 #define UMC_BASE__INST6_SEG5 0 1316 1317 #define VCN_BASE__INST0_SEG0 0x00007800 1318 #define VCN_BASE__INST0_SEG1 0x00007E00 1319 #define VCN_BASE__INST0_SEG2 0x02403000 1320 #define VCN_BASE__INST0_SEG3 0 1321 #define VCN_BASE__INST0_SEG4 0 1322 #define VCN_BASE__INST0_SEG5 0 1323 1324 #define VCN_BASE__INST1_SEG0 0 1325 #define VCN_BASE__INST1_SEG1 0 1326 #define VCN_BASE__INST1_SEG2 0 1327 #define VCN_BASE__INST1_SEG3 0 1328 #define VCN_BASE__INST1_SEG4 0 1329 #define VCN_BASE__INST1_SEG5 0 1330 1331 #define VCN_BASE__INST2_SEG0 0 1332 #define VCN_BASE__INST2_SEG1 0 1333 #define VCN_BASE__INST2_SEG2 0 1334 #define VCN_BASE__INST2_SEG3 0 1335 #define VCN_BASE__INST2_SEG4 0 1336 #define VCN_BASE__INST2_SEG5 0 1337 1338 #define VCN_BASE__INST3_SEG0 0 1339 #define VCN_BASE__INST3_SEG1 0 1340 #define VCN_BASE__INST3_SEG2 0 1341 #define VCN_BASE__INST3_SEG3 0 1342 #define VCN_BASE__INST3_SEG4 0 1343 #define VCN_BASE__INST3_SEG5 0 1344 1345 #define VCN_BASE__INST4_SEG0 0 1346 #define VCN_BASE__INST4_SEG1 0 1347 #define VCN_BASE__INST4_SEG2 0 1348 #define VCN_BASE__INST4_SEG3 0 1349 #define VCN_BASE__INST4_SEG4 0 1350 #define VCN_BASE__INST4_SEG5 0 1351 1352 #define VCN_BASE__INST5_SEG0 0 1353 #define VCN_BASE__INST5_SEG1 0 1354 #define VCN_BASE__INST5_SEG2 0 1355 #define VCN_BASE__INST5_SEG3 0 1356 #define VCN_BASE__INST5_SEG4 0 1357 #define VCN_BASE__INST5_SEG5 0 1358 1359 #define VCN_BASE__INST6_SEG0 0 1360 #define VCN_BASE__INST6_SEG1 0 1361 #define VCN_BASE__INST6_SEG2 0 1362 #define VCN_BASE__INST6_SEG3 0 1363 #define VCN_BASE__INST6_SEG4 0 1364 #define VCN_BASE__INST6_SEG5 0 1365 1366 #endif 1367