1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef V12_STRUCTS_H_ 25 #define V12_STRUCTS_H_ 26 27 struct v12_gfx_mqd { 28 uint32_t shadow_base_lo; // offset: 0 (0x0) 29 uint32_t shadow_base_hi; // offset: 1 (0x1) 30 uint32_t reserved_2; // offset: 2 (0x2) 31 uint32_t reserved_3; // offset: 3 (0x3) 32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4) 33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5) 34 uint32_t shadow_initialized; // offset: 6 (0x6) 35 uint32_t ib_vmid; // offset: 7 (0x7) 36 uint32_t reserved_8; // offset: 8 (0x8) 37 uint32_t reserved_9; // offset: 9 (0x9) 38 uint32_t reserved_10; // offset: 10 (0xA) 39 uint32_t reserved_11; // offset: 11 (0xB) 40 uint32_t reserved_12; // offset: 12 (0xC) 41 uint32_t reserved_13; // offset: 13 (0xD) 42 uint32_t reserved_14; // offset: 14 (0xE) 43 uint32_t reserved_15; // offset: 15 (0xF) 44 uint32_t reserved_16; // offset: 16 (0x10) 45 uint32_t reserved_17; // offset: 17 (0x11) 46 uint32_t reserved_18; // offset: 18 (0x12) 47 uint32_t reserved_19; // offset: 19 (0x13) 48 uint32_t reserved_20; // offset: 20 (0x14) 49 uint32_t reserved_21; // offset: 21 (0x15) 50 uint32_t reserved_22; // offset: 22 (0x16) 51 uint32_t reserved_23; // offset: 23 (0x17) 52 uint32_t reserved_24; // offset: 24 (0x18) 53 uint32_t reserved_25; // offset: 25 (0x19) 54 uint32_t reserved_26; // offset: 26 (0x1A) 55 uint32_t reserved_27; // offset: 27 (0x1B) 56 uint32_t reserved_28; // offset: 28 (0x1C) 57 uint32_t reserved_29; // offset: 29 (0x1D) 58 uint32_t reserved_30; // offset: 30 (0x1E) 59 uint32_t reserved_31; // offset: 31 (0x1F) 60 uint32_t reserved_32; // offset: 32 (0x20) 61 uint32_t reserved_33; // offset: 33 (0x21) 62 uint32_t reserved_34; // offset: 34 (0x22) 63 uint32_t reserved_35; // offset: 35 (0x23) 64 uint32_t reserved_36; // offset: 36 (0x24) 65 uint32_t reserved_37; // offset: 37 (0x25) 66 uint32_t reserved_38; // offset: 38 (0x26) 67 uint32_t reserved_39; // offset: 39 (0x27) 68 uint32_t reserved_40; // offset: 40 (0x28) 69 uint32_t reserved_41; // offset: 41 (0x29) 70 uint32_t reserved_42; // offset: 42 (0x2A) 71 uint32_t reserved_43; // offset: 43 (0x2B) 72 uint32_t reserved_44; // offset: 44 (0x2C) 73 uint32_t reserved_45; // offset: 45 (0x2D) 74 uint32_t reserved_46; // offset: 46 (0x2E) 75 uint32_t reserved_47; // offset: 47 (0x2F) 76 uint32_t reserved_48; // offset: 48 (0x30) 77 uint32_t reserved_49; // offset: 49 (0x31) 78 uint32_t reserved_50; // offset: 50 (0x32) 79 uint32_t reserved_51; // offset: 51 (0x33) 80 uint32_t reserved_52; // offset: 52 (0x34) 81 uint32_t reserved_53; // offset: 53 (0x35) 82 uint32_t reserved_54; // offset: 54 (0x36) 83 uint32_t reserved_55; // offset: 55 (0x37) 84 uint32_t reserved_56; // offset: 56 (0x38) 85 uint32_t reserved_57; // offset: 57 (0x39) 86 uint32_t reserved_58; // offset: 58 (0x3A) 87 uint32_t reserved_59; // offset: 59 (0x3B) 88 uint32_t reserved_60; // offset: 60 (0x3C) 89 uint32_t reserved_61; // offset: 61 (0x3D) 90 uint32_t reserved_62; // offset: 62 (0x3E) 91 uint32_t reserved_63; // offset: 63 (0x3F) 92 uint32_t reserved_64; // offset: 64 (0x40) 93 uint32_t reserved_65; // offset: 65 (0x41) 94 uint32_t reserved_66; // offset: 66 (0x42) 95 uint32_t reserved_67; // offset: 67 (0x43) 96 uint32_t reserved_68; // offset: 68 (0x44) 97 uint32_t reserved_69; // offset: 69 (0x45) 98 uint32_t reserved_70; // offset: 70 (0x46) 99 uint32_t reserved_71; // offset: 71 (0x47) 100 uint32_t reserved_72; // offset: 72 (0x48) 101 uint32_t reserved_73; // offset: 73 (0x49) 102 uint32_t reserved_74; // offset: 74 (0x4A) 103 uint32_t reserved_75; // offset: 75 (0x4B) 104 uint32_t reserved_76; // offset: 76 (0x4C) 105 uint32_t reserved_77; // offset: 77 (0x4D) 106 uint32_t reserved_78; // offset: 78 (0x4E) 107 uint32_t reserved_79; // offset: 79 (0x4F) 108 uint32_t reserved_80; // offset: 80 (0x50) 109 uint32_t reserved_81; // offset: 81 (0x51) 110 uint32_t reserved_82; // offset: 82 (0x52) 111 uint32_t reserved_83; // offset: 83 (0x53) 112 uint32_t checksum_lo; // offset: 84 (0x54) 113 uint32_t checksum_hi; // offset: 85 (0x55) 114 uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56) 115 uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57) 116 uint32_t reserved_88; // offset: 88 (0x58) 117 uint32_t reserved_89; // offset: 89 (0x59) 118 uint32_t reserved_90; // offset: 90 (0x5A) 119 uint32_t reserved_91; // offset: 91 (0x5B) 120 uint32_t cp_mqd_query_wave_count; // offset: 92 (0x5C) 121 uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93 (0x5D) 122 uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94 (0x5E) 123 uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95 (0x5F) 124 uint32_t reserved_96; // offset: 96 (0x60) 125 uint32_t reserved_97; // offset: 97 (0x61) 126 uint32_t reserved_98; // offset: 98 (0x62) 127 uint32_t reserved_99; // offset: 99 (0x63) 128 uint32_t reserved_100; // offset: 100 (0x64) 129 uint32_t reserved_101; // offset: 101 (0x65) 130 uint32_t reserved_102; // offset: 102 (0x66) 131 uint32_t reserved_103; // offset: 103 (0x67) 132 uint32_t task_shader_control_buf_addr_lo; // offset: 104 (0x68) 133 uint32_t task_shader_control_buf_addr_hi; // offset: 105 (0x69) 134 uint32_t task_shader_read_rptr_lo; // offset: 106 (0x6A) 135 uint32_t task_shader_read_rptr_hi; // offset: 107 (0x6B) 136 uint32_t task_shader_num_entries; // offset: 108 (0x6C) 137 uint32_t task_shader_num_entries_bits; // offset: 109 (0x6D) 138 uint32_t task_shader_ring_buffer_addr_lo; // offset: 110 (0x6E) 139 uint32_t task_shader_ring_buffer_addr_hi; // offset: 111 (0x6F) 140 uint32_t reserved_112; // offset: 112 (0x70) 141 uint32_t reserved_113; // offset: 113 (0x71) 142 uint32_t reserved_114; // offset: 114 (0x72) 143 uint32_t reserved_115; // offset: 115 (0x73) 144 uint32_t reserved_116; // offset: 116 (0x74) 145 uint32_t reserved_117; // offset: 117 (0x75) 146 uint32_t reserved_118; // offset: 118 (0x76) 147 uint32_t reserved_119; // offset: 119 (0x77) 148 uint32_t reserved_120; // offset: 120 (0x78) 149 uint32_t reserved_121; // offset: 121 (0x79) 150 uint32_t reserved_122; // offset: 122 (0x7A) 151 uint32_t reserved_123; // offset: 123 (0x7B) 152 uint32_t reserved_124; // offset: 124 (0x7C) 153 uint32_t reserved_125; // offset: 125 (0x7D) 154 uint32_t reserved_126; // offset: 126 (0x7E) 155 uint32_t reserved_127; // offset: 127 (0x7F) 156 uint32_t cp_mqd_base_addr; // offset: 128 (0x80) 157 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) 158 uint32_t cp_gfx_hqd_active; // offset: 130 (0x82) 159 uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83) 160 uint32_t reserved_132; // offset: 132 (0x84) 161 uint32_t reserved_133; // offset: 133 (0x85) 162 uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86) 163 uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87) 164 uint32_t cp_gfx_hqd_base; // offset: 136 (0x88) 165 uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89) 166 uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A) 167 uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B) 168 uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C) 169 uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D) 170 uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E) 171 uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F) 172 uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90) 173 uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91) 174 uint32_t reserved_146; // offset: 146 (0x92) 175 uint32_t reserved_147; // offset: 147 (0x93) 176 uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94) 177 uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95) 178 uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96) 179 uint32_t reserved_151; // offset: 151 (0x97) 180 uint32_t reserved_152; // offset: 152 (0x98) 181 uint32_t reserved_153; // offset: 153 (0x99) 182 uint32_t reserved_154; // offset: 154 (0x9A) 183 uint32_t reserved_155; // offset: 155 (0x9B) 184 uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C) 185 uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D) 186 uint32_t reserved_158; // offset: 158 (0x9E) 187 uint32_t reserved_159; // offset: 159 (0x9F) 188 uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0) 189 uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1) 190 uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2) 191 uint32_t reserved_163; // offset: 163 (0xA3) 192 uint32_t reserved_164; // offset: 164 (0xA4) 193 uint32_t reserved_165; // offset: 165 (0xA5) 194 uint32_t reserved_166; // offset: 166 (0xA6) 195 uint32_t reserved_167; // offset: 167 (0xA7) 196 uint32_t reserved_168; // offset: 168 (0xA8) 197 uint32_t reserved_169; // offset: 169 (0xA9) 198 uint32_t reserved_170; // offset: 170 (0xAA) 199 uint32_t reserved_171; // offset: 171 (0xAB) 200 uint32_t reserved_172; // offset: 172 (0xAC) 201 uint32_t reserved_173; // offset: 173 (0xAD) 202 uint32_t reserved_174; // offset: 174 (0xAE) 203 uint32_t reserved_175; // offset: 175 (0xAF) 204 uint32_t reserved_176; // offset: 176 (0xB0) 205 uint32_t reserved_177; // offset: 177 (0xB1) 206 uint32_t reserved_178; // offset: 178 (0xB2) 207 uint32_t reserved_179; // offset: 179 (0xB3) 208 uint32_t reserved_180; // offset: 180 (0xB4) 209 uint32_t reserved_181; // offset: 181 (0xB5) 210 uint32_t reserved_182; // offset: 182 (0xB6) 211 uint32_t reserved_183; // offset: 183 (0xB7) 212 uint32_t reserved_184; // offset: 184 (0xB8) 213 uint32_t reserved_185; // offset: 185 (0xB9) 214 uint32_t reserved_186; // offset: 186 (0xBA) 215 uint32_t reserved_187; // offset: 187 (0xBB) 216 uint32_t reserved_188; // offset: 188 (0xBC) 217 uint32_t reserved_189; // offset: 189 (0xBD) 218 uint32_t reserved_190; // offset: 190 (0xBE) 219 uint32_t reserved_191; // offset: 191 (0xBF) 220 uint32_t reserved_192; // offset: 192 (0xC0) 221 uint32_t reserved_193; // offset: 193 (0xC1) 222 uint32_t reserved_194; // offset: 194 (0xC2) 223 uint32_t reserved_195; // offset: 195 (0xC3) 224 uint32_t reserved_196; // offset: 196 (0xC4) 225 uint32_t reserved_197; // offset: 197 (0xC5) 226 uint32_t reserved_198; // offset: 198 (0xC6) 227 uint32_t reserved_199; // offset: 199 (0xC7) 228 uint32_t reserved_200; // offset: 200 (0xC8) 229 uint32_t reserved_201; // offset: 201 (0xC9) 230 uint32_t reserved_202; // offset: 202 (0xCA) 231 uint32_t reserved_203; // offset: 203 (0xCB) 232 uint32_t reserved_204; // offset: 204 (0xCC) 233 uint32_t reserved_205; // offset: 205 (0xCD) 234 uint32_t reserved_206; // offset: 206 (0xCE) 235 uint32_t reserved_207; // offset: 207 (0xCF) 236 uint32_t reserved_208; // offset: 208 (0xD0) 237 uint32_t reserved_209; // offset: 209 (0xD1) 238 uint32_t reserved_210; // offset: 210 (0xD2) 239 uint32_t reserved_211; // offset: 211 (0xD3) 240 uint32_t reserved_212; // offset: 212 (0xD4) 241 uint32_t reserved_213; // offset: 213 (0xD5) 242 uint32_t reserved_214; // offset: 214 (0xD6) 243 uint32_t reserved_215; // offset: 215 (0xD7) 244 uint32_t reserved_216; // offset: 216 (0xD8) 245 uint32_t reserved_217; // offset: 217 (0xD9) 246 uint32_t reserved_218; // offset: 218 (0xDA) 247 uint32_t reserved_219; // offset: 219 (0xDB) 248 uint32_t reserved_220; // offset: 220 (0xDC) 249 uint32_t reserved_221; // offset: 221 (0xDD) 250 uint32_t reserved_222; // offset: 222 (0xDE) 251 uint32_t reserved_223; // offset: 223 (0xDF) 252 uint32_t reserved_224; // offset: 224 (0xE0) 253 uint32_t reserved_225; // offset: 225 (0xE1) 254 uint32_t reserved_226; // offset: 226 (0xE2) 255 uint32_t reserved_227; // offset: 227 (0xE3) 256 uint32_t reserved_228; // offset: 228 (0xE4) 257 uint32_t reserved_229; // offset: 229 (0xE5) 258 uint32_t reserved_230; // offset: 230 (0xE6) 259 uint32_t reserved_231; // offset: 231 (0xE7) 260 uint32_t reserved_232; // offset: 232 (0xE8) 261 uint32_t reserved_233; // offset: 233 (0xE9) 262 uint32_t reserved_234; // offset: 234 (0xEA) 263 uint32_t reserved_235; // offset: 235 (0xEB) 264 uint32_t reserved_236; // offset: 236 (0xEC) 265 uint32_t reserved_237; // offset: 237 (0xED) 266 uint32_t reserved_238; // offset: 238 (0xEE) 267 uint32_t reserved_239; // offset: 239 (0xEF) 268 uint32_t reserved_240; // offset: 240 (0xF0) 269 uint32_t reserved_241; // offset: 241 (0xF1) 270 uint32_t reserved_242; // offset: 242 (0xF2) 271 uint32_t reserved_243; // offset: 243 (0xF3) 272 uint32_t reserved_244; // offset: 244 (0xF4) 273 uint32_t reserved_245; // offset: 245 (0xF5) 274 uint32_t reserved_246; // offset: 246 (0xF6) 275 uint32_t reserved_247; // offset: 247 (0xF7) 276 uint32_t reserved_248; // offset: 248 (0xF8) 277 uint32_t reserved_249; // offset: 249 (0xF9) 278 uint32_t reserved_250; // offset: 250 (0xFA) 279 uint32_t reserved_251; // offset: 251 (0xFB) 280 uint32_t reserved_252; // offset: 252 (0xFC) 281 uint32_t reserved_253; // offset: 253 (0xFD) 282 uint32_t reserved_254; // offset: 254 (0xFE) 283 uint32_t reserved_255; // offset: 255 (0xFF) 284 uint32_t reserved_256; // offset: 256 (0x100) 285 uint32_t reserved_257; // offset: 257 (0x101) 286 uint32_t reserved_258; // offset: 258 (0x102) 287 uint32_t reserved_259; // offset: 259 (0x103) 288 uint32_t reserved_260; // offset: 260 (0x104) 289 uint32_t reserved_261; // offset: 261 (0x105) 290 uint32_t reserved_262; // offset: 262 (0x106) 291 uint32_t reserved_263; // offset: 263 (0x107) 292 uint32_t reserved_264; // offset: 264 (0x108) 293 uint32_t reserved_265; // offset: 265 (0x109) 294 uint32_t reserved_266; // offset: 266 (0x10A) 295 uint32_t reserved_267; // offset: 267 (0x10B) 296 uint32_t reserved_268; // offset: 268 (0x10C) 297 uint32_t reserved_269; // offset: 269 (0x10D) 298 uint32_t reserved_270; // offset: 270 (0x10E) 299 uint32_t reserved_271; // offset: 271 (0x10F) 300 uint32_t dfwx_flags; // offset: 272 (0x110) 301 uint32_t dfwx_slot; // offset: 273 (0x111) 302 uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112) 303 uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113) 304 uint32_t reserved_276; // offset: 276 (0x114) 305 uint32_t reserved_277; // offset: 277 (0x115) 306 uint32_t reserved_278; // offset: 278 (0x116) 307 uint32_t reserved_279; // offset: 279 (0x117) 308 uint32_t reserved_280; // offset: 280 (0x118) 309 uint32_t reserved_281; // offset: 281 (0x119) 310 uint32_t reserved_282; // offset: 282 (0x11A) 311 uint32_t reserved_283; // offset: 283 (0x11B) 312 uint32_t reserved_284; // offset: 284 (0x11C) 313 uint32_t reserved_285; // offset: 285 (0x11D) 314 uint32_t reserved_286; // offset: 286 (0x11E) 315 uint32_t reserved_287; // offset: 287 (0x11F) 316 uint32_t reserved_288; // offset: 288 (0x120) 317 uint32_t reserved_289; // offset: 289 (0x121) 318 uint32_t reserved_290; // offset: 290 (0x122) 319 uint32_t reserved_291; // offset: 291 (0x123) 320 uint32_t reserved_292; // offset: 292 (0x124) 321 uint32_t reserved_293; // offset: 293 (0x125) 322 uint32_t reserved_294; // offset: 294 (0x126) 323 uint32_t reserved_295; // offset: 295 (0x127) 324 uint32_t reserved_296; // offset: 296 (0x128) 325 uint32_t reserved_297; // offset: 297 (0x129) 326 uint32_t reserved_298; // offset: 298 (0x12A) 327 uint32_t reserved_299; // offset: 299 (0x12B) 328 uint32_t reserved_300; // offset: 300 (0x12C) 329 uint32_t reserved_301; // offset: 301 (0x12D) 330 uint32_t reserved_302; // offset: 302 (0x12E) 331 uint32_t reserved_303; // offset: 303 (0x12F) 332 uint32_t reserved_304; // offset: 304 (0x130) 333 uint32_t reserved_305; // offset: 305 (0x131) 334 uint32_t reserved_306; // offset: 306 (0x132) 335 uint32_t reserved_307; // offset: 307 (0x133) 336 uint32_t reserved_308; // offset: 308 (0x134) 337 uint32_t reserved_309; // offset: 309 (0x135) 338 uint32_t reserved_310; // offset: 310 (0x136) 339 uint32_t reserved_311; // offset: 311 (0x137) 340 uint32_t reserved_312; // offset: 312 (0x138) 341 uint32_t reserved_313; // offset: 313 (0x139) 342 uint32_t reserved_314; // offset: 314 (0x13A) 343 uint32_t reserved_315; // offset: 315 (0x13B) 344 uint32_t reserved_316; // offset: 316 (0x13C) 345 uint32_t reserved_317; // offset: 317 (0x13D) 346 uint32_t reserved_318; // offset: 318 (0x13E) 347 uint32_t reserved_319; // offset: 319 (0x13F) 348 uint32_t reserved_320; // offset: 320 (0x140) 349 uint32_t reserved_321; // offset: 321 (0x141) 350 uint32_t reserved_322; // offset: 322 (0x142) 351 uint32_t reserved_323; // offset: 323 (0x143) 352 uint32_t reserved_324; // offset: 324 (0x144) 353 uint32_t reserved_325; // offset: 325 (0x145) 354 uint32_t reserved_326; // offset: 326 (0x146) 355 uint32_t reserved_327; // offset: 327 (0x147) 356 uint32_t reserved_328; // offset: 328 (0x148) 357 uint32_t reserved_329; // offset: 329 (0x149) 358 uint32_t reserved_330; // offset: 330 (0x14A) 359 uint32_t reserved_331; // offset: 331 (0x14B) 360 uint32_t reserved_332; // offset: 332 (0x14C) 361 uint32_t reserved_333; // offset: 333 (0x14D) 362 uint32_t reserved_334; // offset: 334 (0x14E) 363 uint32_t reserved_335; // offset: 335 (0x14F) 364 uint32_t reserved_336; // offset: 336 (0x150) 365 uint32_t reserved_337; // offset: 337 (0x151) 366 uint32_t reserved_338; // offset: 338 (0x152) 367 uint32_t reserved_339; // offset: 339 (0x153) 368 uint32_t reserved_340; // offset: 340 (0x154) 369 uint32_t reserved_341; // offset: 341 (0x155) 370 uint32_t reserved_342; // offset: 342 (0x156) 371 uint32_t reserved_343; // offset: 343 (0x157) 372 uint32_t reserved_344; // offset: 344 (0x158) 373 uint32_t reserved_345; // offset: 345 (0x159) 374 uint32_t reserved_346; // offset: 346 (0x15A) 375 uint32_t reserved_347; // offset: 347 (0x15B) 376 uint32_t reserved_348; // offset: 348 (0x15C) 377 uint32_t reserved_349; // offset: 349 (0x15D) 378 uint32_t reserved_350; // offset: 350 (0x15E) 379 uint32_t reserved_351; // offset: 351 (0x15F) 380 uint32_t reserved_352; // offset: 352 (0x160) 381 uint32_t reserved_353; // offset: 353 (0x161) 382 uint32_t reserved_354; // offset: 354 (0x162) 383 uint32_t reserved_355; // offset: 355 (0x163) 384 uint32_t reserved_356; // offset: 356 (0x164) 385 uint32_t reserved_357; // offset: 357 (0x165) 386 uint32_t reserved_358; // offset: 358 (0x166) 387 uint32_t reserved_359; // offset: 359 (0x167) 388 uint32_t reserved_360; // offset: 360 (0x168) 389 uint32_t reserved_361; // offset: 361 (0x169) 390 uint32_t reserved_362; // offset: 362 (0x16A) 391 uint32_t reserved_363; // offset: 363 (0x16B) 392 uint32_t reserved_364; // offset: 364 (0x16C) 393 uint32_t reserved_365; // offset: 365 (0x16D) 394 uint32_t reserved_366; // offset: 366 (0x16E) 395 uint32_t reserved_367; // offset: 367 (0x16F) 396 uint32_t reserved_368; // offset: 368 (0x170) 397 uint32_t reserved_369; // offset: 369 (0x171) 398 uint32_t reserved_370; // offset: 370 (0x172) 399 uint32_t reserved_371; // offset: 371 (0x173) 400 uint32_t reserved_372; // offset: 372 (0x174) 401 uint32_t reserved_373; // offset: 373 (0x175) 402 uint32_t reserved_374; // offset: 374 (0x176) 403 uint32_t reserved_375; // offset: 375 (0x177) 404 uint32_t reserved_376; // offset: 376 (0x178) 405 uint32_t reserved_377; // offset: 377 (0x179) 406 uint32_t reserved_378; // offset: 378 (0x17A) 407 uint32_t reserved_379; // offset: 379 (0x17B) 408 uint32_t reserved_380; // offset: 380 (0x17C) 409 uint32_t reserved_381; // offset: 381 (0x17D) 410 uint32_t reserved_382; // offset: 382 (0x17E) 411 uint32_t reserved_383; // offset: 383 (0x17F) 412 uint32_t reserved_384; // offset: 384 (0x180) 413 uint32_t reserved_385; // offset: 385 (0x181) 414 uint32_t reserved_386; // offset: 386 (0x182) 415 uint32_t reserved_387; // offset: 387 (0x183) 416 uint32_t reserved_388; // offset: 388 (0x184) 417 uint32_t reserved_389; // offset: 389 (0x185) 418 uint32_t reserved_390; // offset: 390 (0x186) 419 uint32_t reserved_391; // offset: 391 (0x187) 420 uint32_t reserved_392; // offset: 392 (0x188) 421 uint32_t reserved_393; // offset: 393 (0x189) 422 uint32_t reserved_394; // offset: 394 (0x18A) 423 uint32_t reserved_395; // offset: 395 (0x18B) 424 uint32_t reserved_396; // offset: 396 (0x18C) 425 uint32_t reserved_397; // offset: 397 (0x18D) 426 uint32_t reserved_398; // offset: 398 (0x18E) 427 uint32_t reserved_399; // offset: 399 (0x18F) 428 uint32_t reserved_400; // offset: 400 (0x190) 429 uint32_t reserved_401; // offset: 401 (0x191) 430 uint32_t reserved_402; // offset: 402 (0x192) 431 uint32_t reserved_403; // offset: 403 (0x193) 432 uint32_t reserved_404; // offset: 404 (0x194) 433 uint32_t reserved_405; // offset: 405 (0x195) 434 uint32_t reserved_406; // offset: 406 (0x196) 435 uint32_t reserved_407; // offset: 407 (0x197) 436 uint32_t reserved_408; // offset: 408 (0x198) 437 uint32_t reserved_409; // offset: 409 (0x199) 438 uint32_t reserved_410; // offset: 410 (0x19A) 439 uint32_t reserved_411; // offset: 411 (0x19B) 440 uint32_t reserved_412; // offset: 412 (0x19C) 441 uint32_t reserved_413; // offset: 413 (0x19D) 442 uint32_t reserved_414; // offset: 414 (0x19E) 443 uint32_t reserved_415; // offset: 415 (0x19F) 444 uint32_t reserved_416; // offset: 416 (0x1A0) 445 uint32_t reserved_417; // offset: 417 (0x1A1) 446 uint32_t reserved_418; // offset: 418 (0x1A2) 447 uint32_t reserved_419; // offset: 419 (0x1A3) 448 uint32_t reserved_420; // offset: 420 (0x1A4) 449 uint32_t reserved_421; // offset: 421 (0x1A5) 450 uint32_t reserved_422; // offset: 422 (0x1A6) 451 uint32_t reserved_423; // offset: 423 (0x1A7) 452 uint32_t reserved_424; // offset: 424 (0x1A8) 453 uint32_t reserved_425; // offset: 425 (0x1A9) 454 uint32_t reserved_426; // offset: 426 (0x1AA) 455 uint32_t reserved_427; // offset: 427 (0x1AB) 456 uint32_t reserved_428; // offset: 428 (0x1AC) 457 uint32_t reserved_429; // offset: 429 (0x1AD) 458 uint32_t reserved_430; // offset: 430 (0x1AE) 459 uint32_t reserved_431; // offset: 431 (0x1AF) 460 uint32_t reserved_432; // offset: 432 (0x1B0) 461 uint32_t reserved_433; // offset: 433 (0x1B1) 462 uint32_t reserved_434; // offset: 434 (0x1B2) 463 uint32_t reserved_435; // offset: 435 (0x1B3) 464 uint32_t reserved_436; // offset: 436 (0x1B4) 465 uint32_t reserved_437; // offset: 437 (0x1B5) 466 uint32_t reserved_438; // offset: 438 (0x1B6) 467 uint32_t reserved_439; // offset: 439 (0x1B7) 468 uint32_t reserved_440; // offset: 440 (0x1B8) 469 uint32_t reserved_441; // offset: 441 (0x1B9) 470 uint32_t reserved_442; // offset: 442 (0x1BA) 471 uint32_t reserved_443; // offset: 443 (0x1BB) 472 uint32_t reserved_444; // offset: 444 (0x1BC) 473 uint32_t reserved_445; // offset: 445 (0x1BD) 474 uint32_t reserved_446; // offset: 446 (0x1BE) 475 uint32_t reserved_447; // offset: 447 (0x1BF) 476 uint32_t reserved_448; // offset: 448 (0x1C0) 477 uint32_t reserved_449; // offset: 449 (0x1C1) 478 uint32_t reserved_450; // offset: 450 (0x1C2) 479 uint32_t reserved_451; // offset: 451 (0x1C3) 480 uint32_t reserved_452; // offset: 452 (0x1C4) 481 uint32_t reserved_453; // offset: 453 (0x1C5) 482 uint32_t reserved_454; // offset: 454 (0x1C6) 483 uint32_t reserved_455; // offset: 455 (0x1C7) 484 uint32_t reserved_456; // offset: 456 (0x1C8) 485 uint32_t reserved_457; // offset: 457 (0x1C9) 486 uint32_t reserved_458; // offset: 458 (0x1CA) 487 uint32_t reserved_459; // offset: 459 (0x1CB) 488 uint32_t reserved_460; // offset: 460 (0x1CC) 489 uint32_t reserved_461; // offset: 461 (0x1CD) 490 uint32_t reserved_462; // offset: 462 (0x1CE) 491 uint32_t reserved_463; // offset: 463 (0x1CF) 492 uint32_t reserved_464; // offset: 464 (0x1D0) 493 uint32_t reserved_465; // offset: 465 (0x1D1) 494 uint32_t reserved_466; // offset: 466 (0x1D2) 495 uint32_t reserved_467; // offset: 467 (0x1D3) 496 uint32_t reserved_468; // offset: 468 (0x1D4) 497 uint32_t reserved_469; // offset: 469 (0x1D5) 498 uint32_t reserved_470; // offset: 470 (0x1D6) 499 uint32_t reserved_471; // offset: 471 (0x1D7) 500 uint32_t reserved_472; // offset: 472 (0x1D8) 501 uint32_t reserved_473; // offset: 473 (0x1D9) 502 uint32_t reserved_474; // offset: 474 (0x1DA) 503 uint32_t reserved_475; // offset: 475 (0x1DB) 504 uint32_t reserved_476; // offset: 476 (0x1DC) 505 uint32_t reserved_477; // offset: 477 (0x1DD) 506 uint32_t reserved_478; // offset: 478 (0x1DE) 507 uint32_t reserved_479; // offset: 479 (0x1DF) 508 uint32_t reserved_480; // offset: 480 (0x1E0) 509 uint32_t reserved_481; // offset: 481 (0x1E1) 510 uint32_t reserved_482; // offset: 482 (0x1E2) 511 uint32_t reserved_483; // offset: 483 (0x1E3) 512 uint32_t reserved_484; // offset: 484 (0x1E4) 513 uint32_t reserved_485; // offset: 485 (0x1E5) 514 uint32_t reserved_486; // offset: 486 (0x1E6) 515 uint32_t reserved_487; // offset: 487 (0x1E7) 516 uint32_t reserved_488; // offset: 488 (0x1E8) 517 uint32_t reserved_489; // offset: 489 (0x1E9) 518 uint32_t reserved_490; // offset: 490 (0x1EA) 519 uint32_t reserved_491; // offset: 491 (0x1EB) 520 uint32_t reserved_492; // offset: 492 (0x1EC) 521 uint32_t reserved_493; // offset: 493 (0x1ED) 522 uint32_t reserved_494; // offset: 494 (0x1EE) 523 uint32_t reserved_495; // offset: 495 (0x1EF) 524 uint32_t reserved_496; // offset: 496 (0x1F0) 525 uint32_t reserved_497; // offset: 497 (0x1F1) 526 uint32_t reserved_498; // offset: 498 (0x1F2) 527 uint32_t reserved_499; // offset: 499 (0x1F3) 528 uint32_t reserved_500; // offset: 500 (0x1F4) 529 uint32_t reserved_501; // offset: 501 (0x1F5) 530 uint32_t reserved_502; // offset: 502 (0x1F6) 531 uint32_t reserved_503; // offset: 503 (0x1F7) 532 uint32_t reserved_504; // offset: 504 (0x1F8) 533 uint32_t reserved_505; // offset: 505 (0x1F9) 534 uint32_t reserved_506; // offset: 506 (0x1FA) 535 uint32_t reserved_507; // offset: 507 (0x1FB) 536 uint32_t reserved_508; // offset: 508 (0x1FC) 537 uint32_t reserved_509; // offset: 509 (0x1FD) 538 uint32_t fence_address_lo; // offset: 510 (0x1FE) 539 uint32_t fence_address_hi; // offset: 511 (0x1FF) 540 }; 541 542 struct v12_sdma_mqd { 543 uint32_t sdmax_rlcx_rb_cntl; // offset: 0 (0x0) 544 uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1) 545 uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2) 546 uint32_t sdmax_rlcx_rb_rptr; // offset: 3 (0x3) 547 uint32_t sdmax_rlcx_rb_rptr_hi; // offset: 4 (0x4) 548 uint32_t sdmax_rlcx_rb_wptr; // offset: 5 (0x5) 549 uint32_t sdmax_rlcx_rb_wptr_hi; // offset: 6 (0x6) 550 uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 7 (0x7) 551 uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 8 (0x8) 552 uint32_t sdmax_rlcx_ib_cntl; // offset: 9 (0x9) 553 uint32_t sdmax_rlcx_ib_rptr; // offset: 10 (0xA) 554 uint32_t sdmax_rlcx_ib_offset; // offset: 11 (0xB) 555 uint32_t sdmax_rlcx_ib_base_lo; // offset: 12 (0xC) 556 uint32_t sdmax_rlcx_ib_base_hi; // offset: 13 (0xD) 557 uint32_t sdmax_rlcx_ib_size; // offset: 14 (0xE) 558 uint32_t sdmax_rlcx_doorbell; // offset: 15 (0xF) 559 uint32_t sdmax_rlcx_doorbell_log; // offset: 16 (0x10) 560 uint32_t sdmax_rlcx_doorbell_offset; // offset: 17 (0x11) 561 uint32_t sdmax_rlcx_csa_addr_lo; // offset: 18 (0x12) 562 uint32_t sdmax_rlcx_csa_addr_hi; // offset: 19 (0x13) 563 uint32_t sdmax_rlcx_sched_cntl; // offset: 20 (0x14) 564 uint32_t sdmax_rlcx_ib_sub_remain; // offset: 21 (0x15) 565 uint32_t sdmax_rlcx_preempt; // offset: 22 (0x16) 566 uint32_t sdmax_rlcx_dummy_reg; // offset: 23 (0x17) 567 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 24 (0x18) 568 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 25 (0x19) 569 uint32_t sdmax_rlcx_rb_aql_cntl; // offset: 26 (0x1A) 570 uint32_t sdmax_rlcx_minor_ptr_update; // offset: 27 (0x1B) 571 uint32_t sdmax_rlcx_mcu_dbg0; // offset: 28 (0x1C) 572 uint32_t sdmax_rlcx_mcu_dbg1; // offset: 29 (0x1D) 573 uint32_t sdmax_rlcx_context_switch_status; // offset: 30 (0x1E) 574 uint32_t sdmax_rlcx_midcmd_cntl; // offset: 31 (0x1F) 575 uint32_t sdmax_rlcx_midcmd_data0; // offset: 32 (0x20) 576 uint32_t sdmax_rlcx_midcmd_data1; // offset: 33 (0x21) 577 uint32_t sdmax_rlcx_midcmd_data2; // offset: 34 (0x22) 578 uint32_t sdmax_rlcx_midcmd_data3; // offset: 35 (0x23) 579 uint32_t sdmax_rlcx_midcmd_data4; // offset: 36 (0x24) 580 uint32_t sdmax_rlcx_midcmd_data5; // offset: 37 (0x25) 581 uint32_t sdmax_rlcx_midcmd_data6; // offset: 38 (0x26) 582 uint32_t sdmax_rlcx_midcmd_data7; // offset: 39 (0x27) 583 uint32_t sdmax_rlcx_midcmd_data8; // offset: 40 (0x28) 584 uint32_t sdmax_rlcx_midcmd_data9; // offset: 41 (0x29) 585 uint32_t sdmax_rlcx_midcmd_data10; // offset: 42 (0x2A) 586 uint32_t sdmax_rlcx_wait_unsatisfied_thd; // offset: 43 (0x2B) 587 uint32_t sdmax_rlcx_mqd_base_addr_lo; // offset: 44 (0x2C) 588 uint32_t sdmax_rlcx_mqd_base_addr_hi; // offset: 45 (0x2D) 589 uint32_t sdmax_rlcx_mqd_control; // offset: 46 (0x2E) 590 uint32_t reserved_47; // offset: 47 (0x2F) 591 uint32_t reserved_48; // offset: 48 (0x30) 592 uint32_t reserved_49; // offset: 49 (0x31) 593 uint32_t reserved_50; // offset: 50 (0x32) 594 uint32_t reserved_51; // offset: 51 (0x33) 595 uint32_t reserved_52; // offset: 52 (0x34) 596 uint32_t reserved_53; // offset: 53 (0x35) 597 uint32_t reserved_54; // offset: 54 (0x36) 598 uint32_t reserved_55; // offset: 55 (0x37) 599 uint32_t reserved_56; // offset: 56 (0x38) 600 uint32_t reserved_57; // offset: 57 (0x39) 601 uint32_t reserved_58; // offset: 58 (0x3A) 602 uint32_t reserved_59; // offset: 59 (0x3B) 603 uint32_t reserved_60; // offset: 60 (0x3C) 604 uint32_t reserved_61; // offset: 61 (0x3D) 605 uint32_t reserved_62; // offset: 62 (0x3E) 606 uint32_t reserved_63; // offset: 63 (0x3F) 607 uint32_t reserved_64; // offset: 64 (0x40) 608 uint32_t reserved_65; // offset: 65 (0x41) 609 uint32_t reserved_66; // offset: 66 (0x42) 610 uint32_t reserved_67; // offset: 67 (0x43) 611 uint32_t reserved_68; // offset: 68 (0x44) 612 uint32_t reserved_69; // offset: 69 (0x45) 613 uint32_t reserved_70; // offset: 70 (0x46) 614 uint32_t reserved_71; // offset: 0 (0x47) 615 uint32_t reserved_72; // offset: 1 (0x48) 616 uint32_t reserved_73; // offset: 2 (0x49) 617 uint32_t reserved_74; // offset: 3 (0x4A) 618 uint32_t reserved_75; // offset: 4 (0x4B) 619 uint32_t reserved_76; // offset: 5 (0x4C) 620 uint32_t reserved_77; // offset: 6 (0x4D) 621 uint32_t reserved_78; // offset: 7 (0x4E) 622 uint32_t reserved_79; // offset: 79 (0x4F) 623 uint32_t reserved_80; // offset: 80 (0x50) 624 uint32_t reserved_81; // offset: 81 (0x51) 625 uint32_t reserved_82; // offset: 82 (0x52) 626 uint32_t reserved_83; // offset: 83 (0x53) 627 uint32_t reserved_84; // offset: 84 (0x54) 628 uint32_t reserved_85; // offset: 85 (0x55) 629 uint32_t reserved_86; // offset: 86 (0x56) 630 uint32_t reserved_87; // offset: 87 (0x57) 631 uint32_t reserved_88; // offset: 88 (0x58) 632 uint32_t reserved_89; // offset: 89 (0x59) 633 uint32_t reserved_90; // offset: 90 (0x5A) 634 uint32_t reserved_91; // offset: 91 (0x5B) 635 uint32_t reserved_92; // offset: 92 (0x5C) 636 uint32_t reserved_93; // offset: 93 (0x5D) 637 uint32_t reserved_94; // offset: 94 (0x5E) 638 uint32_t reserved_95; // offset: 95 (0x5F) 639 uint32_t reserved_96; // offset: 96 (0x60) 640 uint32_t reserved_97; // offset: 97 (0x61) 641 uint32_t reserved_98; // offset: 98 (0x62) 642 uint32_t reserved_99; // offset: 99 (0x63) 643 uint32_t reserved_100; // offset: 100 (0x64) 644 uint32_t reserved_101; // offset: 101 (0x65) 645 uint32_t reserved_102; // offset: 102 (0x66) 646 uint32_t reserved_103; // offset: 103 (0x67) 647 uint32_t reserved_104; // offset: 104 (0x68) 648 uint32_t reserved_105; // offset: 105 (0x69) 649 uint32_t reserved_106; // offset: 106 (0x6A) 650 uint32_t reserved_107; // offset: 107 (0x6B) 651 uint32_t reserved_108; // offset: 108 (0x6C) 652 uint32_t reserved_109; // offset: 109 (0x6D) 653 uint32_t reserved_110; // offset: 110 (0x6E) 654 uint32_t reserved_111; // offset: 111 (0x6F) 655 uint32_t reserved_112; // offset: 112 (0x70) 656 uint32_t reserved_113; // offset: 113 (0x71) 657 uint32_t reserved_114; // offset: 114 (0x72) 658 uint32_t reserved_115; // offset: 115 (0x73) 659 uint32_t reserved_116; // offset: 116 (0x74) 660 uint32_t reserved_117; // offset: 117 (0x75) 661 uint32_t reserved_118; // offset: 118 (0x76) 662 uint32_t reserved_119; // offset: 119 (0x77) 663 uint32_t reserved_120; // offset: 120 (0x78) 664 uint32_t reserved_121; // offset: 121 (0x79) 665 uint32_t reserved_122; // offset: 122 (0x7A) 666 uint32_t reserved_123; // offset: 123 (0x7B) 667 uint32_t reserved_124; // offset: 124 (0x7C) 668 uint32_t reserved_125; // offset: 125 (0x7D) 669 /* reserved_126,127: repurposed for driver-internal use */ 670 uint32_t sdma_engine_id; 671 uint32_t sdma_queue_id; 672 }; 673 674 struct v12_compute_mqd { 675 uint32_t header; // offset: 0 (0x0) 676 uint32_t compute_dispatch_initiator; // offset: 1 (0x1) 677 uint32_t compute_dim_x; // offset: 2 (0x2) 678 uint32_t compute_dim_y; // offset: 3 (0x3) 679 uint32_t compute_dim_z; // offset: 4 (0x4) 680 uint32_t compute_start_x; // offset: 5 (0x5) 681 uint32_t compute_start_y; // offset: 6 (0x6) 682 uint32_t compute_start_z; // offset: 7 (0x7) 683 uint32_t compute_num_thread_x; // offset: 8 (0x8) 684 uint32_t compute_num_thread_y; // offset: 9 (0x9) 685 uint32_t compute_num_thread_z; // offset: 10 (0xA) 686 uint32_t compute_pipelinestat_enable; // offset: 11 (0xB) 687 uint32_t compute_perfcount_enable; // offset: 12 (0xC) 688 uint32_t compute_pgm_lo; // offset: 13 (0xD) 689 uint32_t compute_pgm_hi; // offset: 14 (0xE) 690 uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF) 691 uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10) 692 uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11) 693 uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12) 694 uint32_t compute_pgm_rsrc1; // offset: 19 (0x13) 695 uint32_t compute_pgm_rsrc2; // offset: 20 (0x14) 696 uint32_t compute_vmid; // offset: 21 (0x15) 697 uint32_t compute_resource_limits; // offset: 22 (0x16) 698 uint32_t compute_static_thread_mgmt_se0; // offset: 23 (0x17) 699 uint32_t compute_static_thread_mgmt_se1; // offset: 24 (0x18) 700 uint32_t compute_tmpring_size; // offset: 25 (0x19) 701 uint32_t compute_static_thread_mgmt_se2; // offset: 26 (0x1A) 702 uint32_t compute_static_thread_mgmt_se3; // offset: 27 (0x1B) 703 uint32_t compute_restart_x; // offset: 28 (0x1C) 704 uint32_t compute_restart_y; // offset: 29 (0x1D) 705 uint32_t compute_restart_z; // offset: 30 (0x1E) 706 uint32_t compute_thread_trace_enable; // offset: 31 (0x1F) 707 uint32_t compute_misc_reserved; // offset: 32 (0x20) 708 uint32_t compute_dispatch_id; // offset: 33 (0x21) 709 uint32_t compute_threadgroup_id; // offset: 34 (0x22) 710 uint32_t compute_req_ctrl; // offset: 35 (0x23) 711 uint32_t reserved_36; // offset: 36 (0x24) 712 uint32_t compute_user_accum_0; // offset: 37 (0x25) 713 uint32_t compute_user_accum_1; // offset: 38 (0x26) 714 uint32_t compute_user_accum_2; // offset: 39 (0x27) 715 uint32_t compute_user_accum_3; // offset: 40 (0x28) 716 uint32_t compute_pgm_rsrc3; // offset: 41 (0x29) 717 uint32_t compute_ddid_index; // offset: 42 (0x2A) 718 uint32_t compute_shader_chksum; // offset: 43 (0x2B) 719 uint32_t compute_static_thread_mgmt_se4; // offset: 44 (0x2C) 720 uint32_t compute_static_thread_mgmt_se5; // offset: 45 (0x2D) 721 uint32_t compute_static_thread_mgmt_se6; // offset: 46 (0x2E) 722 uint32_t compute_static_thread_mgmt_se7; // offset: 47 (0x2F) 723 uint32_t compute_dispatch_interleave; // offset: 48 (0x30) 724 uint32_t compute_relaunch; // offset: 49 (0x31) 725 uint32_t compute_wave_restore_addr_lo; // offset: 50 (0x32) 726 uint32_t compute_wave_restore_addr_hi; // offset: 51 (0x33) 727 uint32_t compute_wave_restore_control; // offset: 52 (0x34) 728 uint32_t reserved_53; // offset: 53 (0x35) 729 uint32_t reserved_54; // offset: 54 (0x36) 730 uint32_t reserved_55; // offset: 55 (0x37) 731 uint32_t reserved_56; // offset: 56 (0x38) 732 uint32_t reserved_57; // offset: 57 (0x39) 733 uint32_t reserved_58; // offset: 58 (0x3A) 734 uint32_t compute_static_thread_mgmt_se8; // offset: 59 (0x3B) 735 uint32_t reserved_60; // offset: 60 (0x3C) 736 uint32_t reserved_61; // offset: 61 (0x3D) 737 uint32_t reserved_62; // offset: 62 (0x3E) 738 uint32_t reserved_63; // offset: 63 (0x3F) 739 uint32_t reserved_64; // offset: 64 (0x40) 740 uint32_t compute_user_data_0; // offset: 65 (0x41) 741 uint32_t compute_user_data_1; // offset: 66 (0x42) 742 uint32_t compute_user_data_2; // offset: 67 (0x43) 743 uint32_t compute_user_data_3; // offset: 68 (0x44) 744 uint32_t compute_user_data_4; // offset: 69 (0x45) 745 uint32_t compute_user_data_5; // offset: 70 (0x46) 746 uint32_t compute_user_data_6; // offset: 71 (0x47) 747 uint32_t compute_user_data_7; // offset: 72 (0x48) 748 uint32_t compute_user_data_8; // offset: 73 (0x49) 749 uint32_t compute_user_data_9; // offset: 74 (0x4A) 750 uint32_t compute_user_data_10; // offset: 75 (0x4B) 751 uint32_t compute_user_data_11; // offset: 76 (0x4C) 752 uint32_t compute_user_data_12; // offset: 77 (0x4D) 753 uint32_t compute_user_data_13; // offset: 78 (0x4E) 754 uint32_t compute_user_data_14; // offset: 79 (0x4F) 755 uint32_t compute_user_data_15; // offset: 80 (0x50) 756 uint32_t cp_compute_csinvoc_count_lo; // offset: 81 (0x51) 757 uint32_t cp_compute_csinvoc_count_hi; // offset: 82 (0x52) 758 uint32_t reserved_83; // offset: 83 (0x53) 759 uint32_t reserved_84; // offset: 84 (0x54) 760 uint32_t reserved_85; // offset: 85 (0x55) 761 uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56) 762 uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57) 763 uint32_t cp_mqd_connect_start_time_lo; // offset: 88 (0x58) 764 uint32_t cp_mqd_connect_start_time_hi; // offset: 89 (0x59) 765 uint32_t cp_mqd_connect_end_time_lo; // offset: 90 (0x5A) 766 uint32_t cp_mqd_connect_end_time_hi; // offset: 91 (0x5B) 767 uint32_t cp_mqd_connect_end_wf_count; // offset: 92 (0x5C) 768 uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93 (0x5D) 769 uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94 (0x5E) 770 uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95 (0x5F) 771 uint32_t cp_mqd_readindex_lo; // offset: 96 (0x60) 772 uint32_t cp_mqd_readindex_hi; // offset: 97 (0x61) 773 uint32_t cp_mqd_save_start_time_lo; // offset: 98 (0x62) 774 uint32_t cp_mqd_save_start_time_hi; // offset: 99 (0x63) 775 uint32_t cp_mqd_save_end_time_lo; // offset: 100 (0x64) 776 uint32_t cp_mqd_save_end_time_hi; // offset: 101 (0x65) 777 uint32_t cp_mqd_restore_start_time_lo; // offset: 102 (0x66) 778 uint32_t cp_mqd_restore_start_time_hi; // offset: 103 (0x67) 779 uint32_t cp_mqd_restore_end_time_lo; // offset: 104 (0x68) 780 uint32_t cp_mqd_restore_end_time_hi; // offset: 105 (0x69) 781 uint32_t disable_queue; // offset: 106 (0x6A) 782 uint32_t reserved_107; // offset: 107 (0x6B) 783 uint32_t reserved_108; // offset: 108 (0x6C) 784 uint32_t reserved_109; // offset: 109 (0x6D) 785 uint32_t reserved_110; // offset: 110 (0x6E) 786 uint32_t reserved_111; // offset: 111 (0x6F) 787 uint32_t reserved_112; // offset: 112 (0x70) 788 uint32_t reserved_113; // offset: 113 (0x71) 789 uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72) 790 uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73) 791 uint32_t cp_packet_id_lo; // offset: 116 (0x74) 792 uint32_t cp_packet_id_hi; // offset: 117 (0x75) 793 uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76) 794 uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77) 795 uint32_t reserved_120; // offset: 120 (0x78) 796 uint32_t reserved_121; // offset: 121 (0x79) 797 uint32_t reserved_122; // offset: 122 (0x7A) 798 uint32_t reserved_123; // offset: 123 (0x7B) 799 uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C) 800 uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D) 801 uint32_t reserved_126; // offset: 126 (0x7E) 802 uint32_t reserved_127; // offset: 127 (0x7F) 803 uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80) 804 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) 805 uint32_t cp_hqd_active; // offset: 130 (0x82) 806 uint32_t cp_hqd_vmid; // offset: 131 (0x83) 807 uint32_t cp_hqd_persistent_state; // offset: 132 (0x84) 808 uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85) 809 uint32_t cp_hqd_queue_priority; // offset: 134 (0x86) 810 uint32_t cp_hqd_quantum; // offset: 135 (0x87) 811 uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) 812 uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) 813 uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A) 814 uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B) 815 uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C) 816 uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D) 817 uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) 818 uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F) 819 uint32_t reserved_144; // offset: 144 (0x90) 820 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) 821 uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92) 822 uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93) 823 uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94) 824 uint32_t cp_hqd_ib_control; // offset: 149 (0x95) 825 uint32_t cp_hqd_iq_timer; // offset: 150 (0x96) 826 uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97) 827 uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98) 828 uint32_t cp_hqd_dma_offload; // offset: 153 (0x99) 829 uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A) 830 uint32_t cp_hqd_msg_type; // offset: 155 (0x9B) 831 uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C) 832 uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D) 833 uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E) 834 uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F) 835 uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0) 836 uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1) 837 uint32_t cp_mqd_control; // offset: 162 (0xA2) 838 uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3) 839 uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4) 840 uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5) 841 uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6) 842 uint32_t cp_hqd_eop_control; // offset: 167 (0xA7) 843 uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8) 844 uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9) 845 uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA) 846 uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB) 847 uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC) 848 uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD) 849 uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE) 850 uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF) 851 uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0) 852 uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1) 853 uint32_t reserved_178; // offset: 178 (0xB2) 854 uint32_t cp_hqd_error; // offset: 179 (0xB3) 855 uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4) 856 uint32_t cp_hqd_aql_control; // offset: 181 (0xB5) 857 uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6) 858 uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7) 859 uint32_t reserved_184; // offset: 184 (0xB8) 860 uint32_t reserved_185; // offset: 185 (0xB9) 861 uint32_t reserved_186; // offset: 186 (0xBA) 862 uint32_t reserved_187; // offset: 187 (0xBB) 863 uint32_t reserved_188; // offset: 188 (0xBC) 864 uint32_t reserved_189; // offset: 189 (0xBD) 865 uint32_t reserved_190; // offset: 190 (0xBE) 866 uint32_t reserved_191; // offset: 191 (0xBF) 867 uint32_t iqtimer_pkt_header; // offset: 192 (0xC0) 868 uint32_t iqtimer_pkt_dw0; // offset: 193 (0xC1) 869 uint32_t iqtimer_pkt_dw1; // offset: 194 (0xC2) 870 uint32_t iqtimer_pkt_dw2; // offset: 195 (0xC3) 871 uint32_t iqtimer_pkt_dw3; // offset: 196 (0xC4) 872 uint32_t iqtimer_pkt_dw4; // offset: 197 (0xC5) 873 uint32_t iqtimer_pkt_dw5; // offset: 198 (0xC6) 874 uint32_t iqtimer_pkt_dw6; // offset: 199 (0xC7) 875 uint32_t iqtimer_pkt_dw7; // offset: 200 (0xC8) 876 uint32_t iqtimer_pkt_dw8; // offset: 201 (0xC9) 877 uint32_t iqtimer_pkt_dw9; // offset: 202 (0xCA) 878 uint32_t iqtimer_pkt_dw10; // offset: 203 (0xCB) 879 uint32_t iqtimer_pkt_dw11; // offset: 204 (0xCC) 880 uint32_t iqtimer_pkt_dw12; // offset: 205 (0xCD) 881 uint32_t iqtimer_pkt_dw13; // offset: 206 (0xCE) 882 uint32_t iqtimer_pkt_dw14; // offset: 207 (0xCF) 883 uint32_t iqtimer_pkt_dw15; // offset: 208 (0xD0) 884 uint32_t iqtimer_pkt_dw16; // offset: 209 (0xD1) 885 uint32_t iqtimer_pkt_dw17; // offset: 210 (0xD2) 886 uint32_t iqtimer_pkt_dw18; // offset: 211 (0xD3) 887 uint32_t iqtimer_pkt_dw19; // offset: 212 (0xD4) 888 uint32_t iqtimer_pkt_dw20; // offset: 213 (0xD5) 889 uint32_t iqtimer_pkt_dw21; // offset: 214 (0xD6) 890 uint32_t iqtimer_pkt_dw22; // offset: 215 (0xD7) 891 uint32_t iqtimer_pkt_dw23; // offset: 216 (0xD8) 892 uint32_t iqtimer_pkt_dw24; // offset: 217 (0xD9) 893 uint32_t iqtimer_pkt_dw25; // offset: 218 (0xDA) 894 uint32_t iqtimer_pkt_dw26; // offset: 219 (0xDB) 895 uint32_t iqtimer_pkt_dw27; // offset: 220 (0xDC) 896 uint32_t iqtimer_pkt_dw28; // offset: 221 (0xDD) 897 uint32_t iqtimer_pkt_dw29; // offset: 222 (0xDE) 898 uint32_t iqtimer_pkt_dw30; // offset: 223 (0xDF) 899 uint32_t iqtimer_pkt_dw31; // offset: 224 (0xE0) 900 uint32_t reserved_225; // offset: 225 (0xE1) 901 uint32_t reserved_226; // offset: 226 (0xE2) 902 uint32_t reserved_227; // offset: 227 (0xE3) 903 uint32_t set_resources_header; // offset: 228 (0xE4) 904 uint32_t set_resources_dw1; // offset: 229 (0xE5) 905 uint32_t set_resources_dw2; // offset: 230 (0xE6) 906 uint32_t set_resources_dw3; // offset: 231 (0xE7) 907 uint32_t set_resources_dw4; // offset: 232 (0xE8) 908 uint32_t set_resources_dw5; // offset: 233 (0xE9) 909 uint32_t set_resources_dw6; // offset: 234 (0xEA) 910 uint32_t set_resources_dw7; // offset: 235 (0xEB) 911 uint32_t reserved_236; // offset: 236 (0xEC) 912 uint32_t reserved_237; // offset: 237 (0xED) 913 uint32_t reserved_238; // offset: 238 (0xEE) 914 uint32_t reserved_239; // offset: 239 (0xEF) 915 uint32_t queue_doorbell_id0; // offset: 240 (0xF0) 916 uint32_t queue_doorbell_id1; // offset: 241 (0xF1) 917 uint32_t queue_doorbell_id2; // offset: 242 (0xF2) 918 uint32_t queue_doorbell_id3; // offset: 243 (0xF3) 919 uint32_t queue_doorbell_id4; // offset: 244 (0xF4) 920 uint32_t queue_doorbell_id5; // offset: 245 (0xF5) 921 uint32_t queue_doorbell_id6; // offset: 246 (0xF6) 922 uint32_t queue_doorbell_id7; // offset: 247 (0xF7) 923 uint32_t queue_doorbell_id8; // offset: 248 (0xF8) 924 uint32_t queue_doorbell_id9; // offset: 249 (0xF9) 925 uint32_t queue_doorbell_id10; // offset: 250 (0xFA) 926 uint32_t queue_doorbell_id11; // offset: 251 (0xFB) 927 uint32_t queue_doorbell_id12; // offset: 252 (0xFC) 928 uint32_t queue_doorbell_id13; // offset: 253 (0xFD) 929 uint32_t queue_doorbell_id14; // offset: 254 (0xFE) 930 uint32_t queue_doorbell_id15; // offset: 255 (0xFF) 931 uint32_t control_buf_addr_lo; // offset: 256 (0x100) 932 uint32_t control_buf_addr_hi; // offset: 257 (0x101) 933 uint32_t control_buf_wptr_lo; // offset: 258 (0x102) 934 uint32_t control_buf_wptr_hi; // offset: 259 (0x103) 935 uint32_t control_buf_dptr_lo; // offset: 260 (0x104) 936 uint32_t control_buf_dptr_hi; // offset: 261 (0x105) 937 uint32_t control_buf_num_entries; // offset: 262 (0x106) 938 uint32_t draw_ring_addr_lo; // offset: 263 (0x107) 939 uint32_t draw_ring_addr_hi; // offset: 264 (0x108) 940 uint32_t reserved_265; // offset: 265 (0x109) 941 uint32_t reserved_266; // offset: 266 (0x10A) 942 uint32_t reserved_267; // offset: 267 (0x10B) 943 uint32_t reserved_268; // offset: 268 (0x10C) 944 uint32_t reserved_269; // offset: 269 (0x10D) 945 uint32_t reserved_270; // offset: 270 (0x10E) 946 uint32_t reserved_271; // offset: 271 (0x10F) 947 uint32_t dfwx_flags; // offset: 272 (0x110) 948 uint32_t dfwx_slot; // offset: 273 (0x111) 949 uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112) 950 uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113) 951 uint32_t reserved_276; // offset: 276 (0x114) 952 uint32_t reserved_277; // offset: 277 (0x115) 953 uint32_t reserved_278; // offset: 278 (0x116) 954 uint32_t reserved_279; // offset: 279 (0x117) 955 uint32_t reserved_280; // offset: 280 (0x118) 956 uint32_t reserved_281; // offset: 281 (0x119) 957 uint32_t reserved_282; // offset: 282 (0x11A) 958 uint32_t reserved_283; // offset: 283 (0x11B) 959 uint32_t reserved_284; // offset: 284 (0x11C) 960 uint32_t reserved_285; // offset: 285 (0x11D) 961 uint32_t reserved_286; // offset: 286 (0x11E) 962 uint32_t reserved_287; // offset: 287 (0x11F) 963 uint32_t reserved_288; // offset: 288 (0x120) 964 uint32_t reserved_289; // offset: 289 (0x121) 965 uint32_t reserved_290; // offset: 290 (0x122) 966 uint32_t reserved_291; // offset: 291 (0x123) 967 uint32_t reserved_292; // offset: 292 (0x124) 968 uint32_t reserved_293; // offset: 293 (0x125) 969 uint32_t reserved_294; // offset: 294 (0x126) 970 uint32_t reserved_295; // offset: 295 (0x127) 971 uint32_t reserved_296; // offset: 296 (0x128) 972 uint32_t reserved_297; // offset: 297 (0x129) 973 uint32_t reserved_298; // offset: 298 (0x12A) 974 uint32_t reserved_299; // offset: 299 (0x12B) 975 uint32_t reserved_300; // offset: 300 (0x12C) 976 uint32_t reserved_301; // offset: 301 (0x12D) 977 uint32_t reserved_302; // offset: 302 (0x12E) 978 uint32_t reserved_303; // offset: 303 (0x12F) 979 uint32_t reserved_304; // offset: 304 (0x130) 980 uint32_t reserved_305; // offset: 305 (0x131) 981 uint32_t reserved_306; // offset: 306 (0x132) 982 uint32_t reserved_307; // offset: 307 (0x133) 983 uint32_t reserved_308; // offset: 308 (0x134) 984 uint32_t reserved_309; // offset: 309 (0x135) 985 uint32_t reserved_310; // offset: 310 (0x136) 986 uint32_t reserved_311; // offset: 311 (0x137) 987 uint32_t reserved_312; // offset: 312 (0x138) 988 uint32_t reserved_313; // offset: 313 (0x139) 989 uint32_t reserved_314; // offset: 314 (0x13A) 990 uint32_t reserved_315; // offset: 315 (0x13B) 991 uint32_t reserved_316; // offset: 316 (0x13C) 992 uint32_t reserved_317; // offset: 317 (0x13D) 993 uint32_t reserved_318; // offset: 318 (0x13E) 994 uint32_t reserved_319; // offset: 319 (0x13F) 995 uint32_t reserved_320; // offset: 320 (0x140) 996 uint32_t reserved_321; // offset: 321 (0x141) 997 uint32_t reserved_322; // offset: 322 (0x142) 998 uint32_t reserved_323; // offset: 323 (0x143) 999 uint32_t reserved_324; // offset: 324 (0x144) 1000 uint32_t reserved_325; // offset: 325 (0x145) 1001 uint32_t reserved_326; // offset: 326 (0x146) 1002 uint32_t reserved_327; // offset: 327 (0x147) 1003 uint32_t reserved_328; // offset: 328 (0x148) 1004 uint32_t reserved_329; // offset: 329 (0x149) 1005 uint32_t reserved_330; // offset: 330 (0x14A) 1006 uint32_t reserved_331; // offset: 331 (0x14B) 1007 uint32_t reserved_332; // offset: 332 (0x14C) 1008 uint32_t reserved_333; // offset: 333 (0x14D) 1009 uint32_t reserved_334; // offset: 334 (0x14E) 1010 uint32_t reserved_335; // offset: 335 (0x14F) 1011 uint32_t reserved_336; // offset: 336 (0x150) 1012 uint32_t reserved_337; // offset: 337 (0x151) 1013 uint32_t reserved_338; // offset: 338 (0x152) 1014 uint32_t reserved_339; // offset: 339 (0x153) 1015 uint32_t reserved_340; // offset: 340 (0x154) 1016 uint32_t reserved_341; // offset: 341 (0x155) 1017 uint32_t reserved_342; // offset: 342 (0x156) 1018 uint32_t reserved_343; // offset: 343 (0x157) 1019 uint32_t reserved_344; // offset: 344 (0x158) 1020 uint32_t reserved_345; // offset: 345 (0x159) 1021 uint32_t reserved_346; // offset: 346 (0x15A) 1022 uint32_t reserved_347; // offset: 347 (0x15B) 1023 uint32_t reserved_348; // offset: 348 (0x15C) 1024 uint32_t reserved_349; // offset: 349 (0x15D) 1025 uint32_t reserved_350; // offset: 350 (0x15E) 1026 uint32_t reserved_351; // offset: 351 (0x15F) 1027 uint32_t reserved_352; // offset: 352 (0x160) 1028 uint32_t reserved_353; // offset: 353 (0x161) 1029 uint32_t reserved_354; // offset: 354 (0x162) 1030 uint32_t reserved_355; // offset: 355 (0x163) 1031 uint32_t reserved_356; // offset: 356 (0x164) 1032 uint32_t reserved_357; // offset: 357 (0x165) 1033 uint32_t reserved_358; // offset: 358 (0x166) 1034 uint32_t reserved_359; // offset: 359 (0x167) 1035 uint32_t reserved_360; // offset: 360 (0x168) 1036 uint32_t reserved_361; // offset: 361 (0x169) 1037 uint32_t reserved_362; // offset: 362 (0x16A) 1038 uint32_t reserved_363; // offset: 363 (0x16B) 1039 uint32_t reserved_364; // offset: 364 (0x16C) 1040 uint32_t reserved_365; // offset: 365 (0x16D) 1041 uint32_t reserved_366; // offset: 366 (0x16E) 1042 uint32_t reserved_367; // offset: 367 (0x16F) 1043 uint32_t reserved_368; // offset: 368 (0x170) 1044 uint32_t reserved_369; // offset: 369 (0x171) 1045 uint32_t reserved_370; // offset: 370 (0x172) 1046 uint32_t reserved_371; // offset: 371 (0x173) 1047 uint32_t reserved_372; // offset: 372 (0x174) 1048 uint32_t reserved_373; // offset: 373 (0x175) 1049 uint32_t reserved_374; // offset: 374 (0x176) 1050 uint32_t reserved_375; // offset: 375 (0x177) 1051 uint32_t reserved_376; // offset: 376 (0x178) 1052 uint32_t reserved_377; // offset: 377 (0x179) 1053 uint32_t reserved_378; // offset: 378 (0x17A) 1054 uint32_t reserved_379; // offset: 379 (0x17B) 1055 uint32_t reserved_380; // offset: 380 (0x17C) 1056 uint32_t reserved_381; // offset: 381 (0x17D) 1057 uint32_t reserved_382; // offset: 382 (0x17E) 1058 uint32_t reserved_383; // offset: 383 (0x17F) 1059 uint32_t reserved_384; // offset: 384 (0x180) 1060 uint32_t reserved_385; // offset: 385 (0x181) 1061 uint32_t reserved_386; // offset: 386 (0x182) 1062 uint32_t reserved_387; // offset: 387 (0x183) 1063 uint32_t reserved_388; // offset: 388 (0x184) 1064 uint32_t reserved_389; // offset: 389 (0x185) 1065 uint32_t reserved_390; // offset: 390 (0x186) 1066 uint32_t reserved_391; // offset: 391 (0x187) 1067 uint32_t reserved_392; // offset: 392 (0x188) 1068 uint32_t reserved_393; // offset: 393 (0x189) 1069 uint32_t reserved_394; // offset: 394 (0x18A) 1070 uint32_t reserved_395; // offset: 395 (0x18B) 1071 uint32_t reserved_396; // offset: 396 (0x18C) 1072 uint32_t reserved_397; // offset: 397 (0x18D) 1073 uint32_t reserved_398; // offset: 398 (0x18E) 1074 uint32_t reserved_399; // offset: 399 (0x18F) 1075 uint32_t reserved_400; // offset: 400 (0x190) 1076 uint32_t reserved_401; // offset: 401 (0x191) 1077 uint32_t reserved_402; // offset: 402 (0x192) 1078 uint32_t reserved_403; // offset: 403 (0x193) 1079 uint32_t reserved_404; // offset: 404 (0x194) 1080 uint32_t reserved_405; // offset: 405 (0x195) 1081 uint32_t reserved_406; // offset: 406 (0x196) 1082 uint32_t reserved_407; // offset: 407 (0x197) 1083 uint32_t reserved_408; // offset: 408 (0x198) 1084 uint32_t reserved_409; // offset: 409 (0x199) 1085 uint32_t reserved_410; // offset: 410 (0x19A) 1086 uint32_t reserved_411; // offset: 411 (0x19B) 1087 uint32_t reserved_412; // offset: 412 (0x19C) 1088 uint32_t reserved_413; // offset: 413 (0x19D) 1089 uint32_t reserved_414; // offset: 414 (0x19E) 1090 uint32_t reserved_415; // offset: 415 (0x19F) 1091 uint32_t reserved_416; // offset: 416 (0x1A0) 1092 uint32_t reserved_417; // offset: 417 (0x1A1) 1093 uint32_t reserved_418; // offset: 418 (0x1A2) 1094 uint32_t reserved_419; // offset: 419 (0x1A3) 1095 uint32_t reserved_420; // offset: 420 (0x1A4) 1096 uint32_t reserved_421; // offset: 421 (0x1A5) 1097 uint32_t reserved_422; // offset: 422 (0x1A6) 1098 uint32_t reserved_423; // offset: 423 (0x1A7) 1099 uint32_t reserved_424; // offset: 424 (0x1A8) 1100 uint32_t reserved_425; // offset: 425 (0x1A9) 1101 uint32_t reserved_426; // offset: 426 (0x1AA) 1102 uint32_t reserved_427; // offset: 427 (0x1AB) 1103 uint32_t reserved_428; // offset: 428 (0x1AC) 1104 uint32_t reserved_429; // offset: 429 (0x1AD) 1105 uint32_t reserved_430; // offset: 430 (0x1AE) 1106 uint32_t reserved_431; // offset: 431 (0x1AF) 1107 uint32_t reserved_432; // offset: 432 (0x1B0) 1108 uint32_t reserved_433; // offset: 433 (0x1B1) 1109 uint32_t reserved_434; // offset: 434 (0x1B2) 1110 uint32_t reserved_435; // offset: 435 (0x1B3) 1111 uint32_t reserved_436; // offset: 436 (0x1B4) 1112 uint32_t reserved_437; // offset: 437 (0x1B5) 1113 uint32_t reserved_438; // offset: 438 (0x1B6) 1114 uint32_t reserved_439; // offset: 439 (0x1B7) 1115 uint32_t reserved_440; // offset: 440 (0x1B8) 1116 uint32_t reserved_441; // offset: 441 (0x1B9) 1117 uint32_t reserved_442; // offset: 442 (0x1BA) 1118 uint32_t reserved_443; // offset: 443 (0x1BB) 1119 uint32_t reserved_444; // offset: 444 (0x1BC) 1120 uint32_t reserved_445; // offset: 445 (0x1BD) 1121 uint32_t fence_address_lo; // offset: 446 (0x1BE) 1122 uint32_t fence_address_hi; // offset: 447 (0x1BF) 1123 uint32_t gws_0_val; // offset: 448 (0x1C0) 1124 uint32_t gws_1_val; // offset: 449 (0x1C1) 1125 uint32_t gws_2_val; // offset: 450 (0x1C2) 1126 uint32_t gws_3_val; // offset: 451 (0x1C3) 1127 uint32_t gws_4_val; // offset: 452 (0x1C4) 1128 uint32_t gws_5_val; // offset: 453 (0x1C5) 1129 uint32_t gws_6_val; // offset: 454 (0x1C6) 1130 uint32_t gws_7_val; // offset: 455 (0x1C7) 1131 uint32_t gws_8_val; // offset: 456 (0x1C8) 1132 uint32_t gws_9_val; // offset: 457 (0x1C9) 1133 uint32_t gws_10_val; // offset: 458 (0x1CA) 1134 uint32_t gws_11_val; // offset: 459 (0x1CB) 1135 uint32_t gws_12_val; // offset: 460 (0x1CC) 1136 uint32_t gws_13_val; // offset: 461 (0x1CD) 1137 uint32_t gws_14_val; // offset: 462 (0x1CE) 1138 uint32_t gws_15_val; // offset: 463 (0x1CF) 1139 uint32_t gws_16_val; // offset: 464 (0x1D0) 1140 uint32_t gws_17_val; // offset: 465 (0x1D1) 1141 uint32_t gws_18_val; // offset: 466 (0x1D2) 1142 uint32_t gws_19_val; // offset: 467 (0x1D3) 1143 uint32_t gws_20_val; // offset: 468 (0x1D4) 1144 uint32_t gws_21_val; // offset: 469 (0x1D5) 1145 uint32_t gws_22_val; // offset: 470 (0x1D6) 1146 uint32_t gws_23_val; // offset: 471 (0x1D7) 1147 uint32_t gws_24_val; // offset: 472 (0x1D8) 1148 uint32_t gws_25_val; // offset: 473 (0x1D9) 1149 uint32_t gws_26_val; // offset: 474 (0x1DA) 1150 uint32_t gws_27_val; // offset: 475 (0x1DB) 1151 uint32_t gws_28_val; // offset: 476 (0x1DC) 1152 uint32_t gws_29_val; // offset: 477 (0x1DD) 1153 uint32_t gws_30_val; // offset: 478 (0x1DE) 1154 uint32_t gws_31_val; // offset: 479 (0x1DF) 1155 uint32_t gws_32_val; // offset: 480 (0x1E0) 1156 uint32_t gws_33_val; // offset: 481 (0x1E1) 1157 uint32_t gws_34_val; // offset: 482 (0x1E2) 1158 uint32_t gws_35_val; // offset: 483 (0x1E3) 1159 uint32_t gws_36_val; // offset: 484 (0x1E4) 1160 uint32_t gws_37_val; // offset: 485 (0x1E5) 1161 uint32_t gws_38_val; // offset: 486 (0x1E6) 1162 uint32_t gws_39_val; // offset: 487 (0x1E7) 1163 uint32_t gws_40_val; // offset: 488 (0x1E8) 1164 uint32_t gws_41_val; // offset: 489 (0x1E9) 1165 uint32_t gws_42_val; // offset: 490 (0x1EA) 1166 uint32_t gws_43_val; // offset: 491 (0x1EB) 1167 uint32_t gws_44_val; // offset: 492 (0x1EC) 1168 uint32_t gws_45_val; // offset: 493 (0x1ED) 1169 uint32_t gws_46_val; // offset: 494 (0x1EE) 1170 uint32_t gws_47_val; // offset: 495 (0x1EF) 1171 uint32_t gws_48_val; // offset: 496 (0x1F0) 1172 uint32_t gws_49_val; // offset: 497 (0x1F1) 1173 uint32_t gws_50_val; // offset: 498 (0x1F2) 1174 uint32_t gws_51_val; // offset: 499 (0x1F3) 1175 uint32_t gws_52_val; // offset: 500 (0x1F4) 1176 uint32_t gws_53_val; // offset: 501 (0x1F5) 1177 uint32_t gws_54_val; // offset: 502 (0x1F6) 1178 uint32_t gws_55_val; // offset: 503 (0x1F7) 1179 uint32_t gws_56_val; // offset: 504 (0x1F8) 1180 uint32_t gws_57_val; // offset: 505 (0x1F9) 1181 uint32_t gws_58_val; // offset: 506 (0x1FA) 1182 uint32_t gws_59_val; // offset: 507 (0x1FB) 1183 uint32_t gws_60_val; // offset: 508 (0x1FC) 1184 uint32_t gws_61_val; // offset: 509 (0x1FD) 1185 uint32_t gws_62_val; // offset: 510 (0x1FE) 1186 uint32_t gws_63_val; // offset: 511 (0x1FF) 1187 }; 1188 1189 struct v12_1_compute_mqd { 1190 uint32_t header; // offset: 0 (0x0) 1191 uint32_t compute_dispatch_initiator; // offset: 1 (0x1) 1192 uint32_t compute_dim_x; // offset: 2 (0x2) 1193 uint32_t compute_dim_y; // offset: 3 (0x3) 1194 uint32_t compute_dim_z; // offset: 4 (0x4) 1195 uint32_t compute_start_x; // offset: 5 (0x5) 1196 uint32_t compute_start_y; // offset: 6 (0x6) 1197 uint32_t compute_start_z; // offset: 7 (0x7) 1198 uint32_t compute_num_thread_x; // offset: 8 (0x8) 1199 uint32_t compute_num_thread_y; // offset: 9 (0x9) 1200 uint32_t compute_num_thread_z; // offset: 10 (0xA) 1201 uint32_t compute_pipelinestat_enable; // offset: 11 (0xB) 1202 uint32_t compute_perfcount_enable; // offset: 12 (0xC) 1203 uint32_t compute_pgm_lo; // offset: 13 (0xD) 1204 uint32_t compute_pgm_hi; // offset: 14 (0xE) 1205 uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF) 1206 uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10) 1207 uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11) 1208 uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12) 1209 uint32_t compute_pgm_rsrc1; // offset: 19 (0x13) 1210 uint32_t compute_pgm_rsrc2; // offset: 20 (0x14) 1211 uint32_t compute_vmid; // offset: 21 (0x15) 1212 uint32_t compute_resource_limits; // offset: 22 (0x16) 1213 uint32_t compute_tmpring_size; // offset: 23 (0x17) 1214 uint32_t compute_restart_x; // offset: 24 (0x18) 1215 uint32_t compute_restart_y; // offset: 25 (0x19) 1216 uint32_t compute_restart_z; // offset: 26 (0x1A) 1217 uint32_t compute_thread_trace_enable; // offset: 27 (0x1B) 1218 uint32_t compute_misc_reserved; // offset: 28 (0x1C) 1219 uint32_t compute_dispatch_id; // offset: 29 (0x1D) 1220 uint32_t compute_threadgroup_id; // offset: 30 (0x1E) 1221 uint32_t compute_req_ctrl; // offset: 31 (0x1F) 1222 uint32_t compute_user_accum_0; // offset: 32 (0x20) 1223 uint32_t compute_user_accum_1; // offset: 33 (0x21) 1224 uint32_t compute_user_accum_2; // offset: 34 (0x22) 1225 uint32_t compute_user_accum_3; // offset: 35 (0x23) 1226 uint32_t compute_pgm_rsrc3; // offset: 36 (0x24) 1227 uint32_t compute_ddid_index; // offset: 37 (0x25) 1228 uint32_t compute_shader_chksum; // offset: 38 (0x26) 1229 uint32_t compute_dispatch_interleave; // offset: 39 (0x27) 1230 uint32_t compute_current_logical_xcc_id; // offset: 40 (0x28) 1231 uint32_t compute_restart_cg_tg_id; // offset: 41 (0x29) 1232 uint32_t compute_tg_chunk_size; // offset: 42 (0x2A) 1233 uint32_t compute_restore_tg_chunk_size; // offset: 43 (0x2B) 1234 uint32_t reserved_44; // offset: 44 (0x2C) 1235 uint32_t reserved_45; // offset: 45 (0x2D) 1236 uint32_t compute_prescaled_dim_x; // offset: 46 (0x2E) 1237 uint32_t compute_prescaled_dim_y; // offset: 47 (0x2F) 1238 uint32_t compute_prescaled_dim_z; // offset: 48 (0x30) 1239 uint32_t compute_static_thread_mgmt_se0; // offset: 49 (0x31) 1240 uint32_t compute_static_thread_mgmt_se1; // offset: 50 (0x32) 1241 uint32_t compute_static_thread_mgmt_se2; // offset: 51 (0x33) 1242 uint32_t compute_static_thread_mgmt_se3; // offset: 52 (0x34) 1243 uint32_t compute_static_thread_mgmt_se4; // offset: 53 (0x35) 1244 uint32_t compute_static_thread_mgmt_se5; // offset: 54 (0x36) 1245 uint32_t compute_static_thread_mgmt_se6; // offset: 55 (0x37) 1246 uint32_t compute_static_thread_mgmt_se7; // offset: 56 (0x38) 1247 uint32_t compute_static_thread_mgmt_se8; // offset: 57 (0x39) 1248 uint32_t reserved_58; // offset: 58 (0x3A) 1249 uint32_t reserved_59; // offset: 59 (0x3B) 1250 uint32_t reserved_60; // offset: 60 (0x3C) 1251 uint32_t reserved_61; // offset: 61 (0x3D) 1252 uint32_t reserved_62; // offset: 62 (0x3E) 1253 uint32_t reserved_63; // offset: 63 (0x3F) 1254 uint32_t tg_counter_id; // offset: 64 (0x40) 1255 uint32_t compute_user_data_0; // offset: 65 (0x41) 1256 uint32_t compute_user_data_1; // offset: 66 (0x42) 1257 uint32_t compute_user_data_2; // offset: 67 (0x43) 1258 uint32_t compute_user_data_3; // offset: 68 (0x44) 1259 uint32_t compute_user_data_4; // offset: 69 (0x45) 1260 uint32_t compute_user_data_5; // offset: 70 (0x46) 1261 uint32_t compute_user_data_6; // offset: 71 (0x47) 1262 uint32_t compute_user_data_7; // offset: 72 (0x48) 1263 uint32_t compute_user_data_8; // offset: 73 (0x49) 1264 uint32_t compute_user_data_9; // offset: 74 (0x4A) 1265 uint32_t compute_user_data_10; // offset: 75 (0x4B) 1266 uint32_t compute_user_data_11; // offset: 76 (0x4C) 1267 uint32_t compute_user_data_12; // offset: 77 (0x4D) 1268 uint32_t compute_user_data_13; // offset: 78 (0x4E) 1269 uint32_t compute_user_data_14; // offset: 79 (0x4F) 1270 uint32_t compute_user_data_15; // offset: 80 (0x50) 1271 uint32_t compute_user_data_16; // offset: 81 (0x51) 1272 uint32_t compute_user_data_17; // offset: 82 (0x52) 1273 uint32_t compute_user_data_18; // offset: 83 (0x53) 1274 uint32_t compute_user_data_19; // offset: 84 (0x54) 1275 uint32_t compute_user_data_20; // offset: 85 (0x55) 1276 uint32_t compute_user_data_21; // offset: 86 (0x56) 1277 uint32_t compute_user_data_22; // offset: 87 (0x57) 1278 uint32_t compute_user_data_23; // offset: 88 (0x58) 1279 uint32_t compute_user_data_24; // offset: 89 (0x59) 1280 uint32_t compute_user_data_25; // offset: 90 (0x5A) 1281 uint32_t compute_user_data_26; // offset: 91 (0x5B) 1282 uint32_t compute_user_data_27; // offset: 92 (0x5C) 1283 uint32_t compute_user_data_28; // offset: 93 (0x5D) 1284 uint32_t compute_user_data_29; // offset: 94 (0x5E) 1285 uint32_t compute_user_data_30; // offset: 95 (0x5F) 1286 uint32_t compute_user_data_31; // offset: 96 (0x60) 1287 uint32_t cp_compute_csinvoc_count_lo; // offset: 97 (0x61) 1288 uint32_t cp_compute_csinvoc_count_hi; // offset: 98 (0x62) 1289 uint32_t reserved_99; // offset: 99 (0x63) 1290 uint32_t reserved_100; // offset: 100 (0x64) 1291 uint32_t reserved_101; // offset: 101 (0x65) 1292 uint32_t reserved_102; // offset: 102 (0x66) 1293 uint32_t reserved_103; // offset: 103 (0x67) 1294 uint32_t reserved_104; // offset: 104 (0x68) 1295 uint32_t reserved_105; // offset: 105 (0x69) 1296 uint32_t reserved_106; // offset: 106 (0x6A) 1297 uint32_t reserved_107; // offset: 107 (0x6B) 1298 uint32_t reserved_108; // offset: 108 (0x6C) 1299 uint32_t reserved_109; // offset: 109 (0x6D) 1300 uint32_t compute_relaunch; // offset: 110 (0x6E) 1301 uint32_t compute_wave_restore_addr_lo; // offset: 111 (0x6F) 1302 uint32_t compute_wave_restore_addr_hi; // offset: 112 (0x70) 1303 uint32_t compute_relaunch2; // offset: 113 (0x71) 1304 uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72) 1305 uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73) 1306 uint32_t cp_packet_id_lo; // offset: 116 (0x74) 1307 uint32_t cp_packet_id_hi; // offset: 117 (0x75) 1308 uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76) 1309 uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77) 1310 uint32_t reserved_120; // offset: 120 (0x78) 1311 uint32_t reserved_121; // offset: 121 (0x79) 1312 uint32_t reserved_122; // offset: 122 (0x7A) 1313 uint32_t reserved_123; // offset: 123 (0x7B) 1314 uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C) 1315 uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D) 1316 uint32_t reserved_126; // offset: 126 (0x7E) 1317 uint32_t reserved_127; // offset: 127 (0x7F) 1318 uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80) 1319 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) 1320 uint32_t cp_hqd_active; // offset: 130 (0x82) 1321 uint32_t cp_hqd_vmid; // offset: 131 (0x83) 1322 uint32_t cp_hqd_persistent_state; // offset: 132 (0x84) 1323 uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85) 1324 uint32_t cp_hqd_queue_priority; // offset: 134 (0x86) 1325 uint32_t cp_hqd_quantum; // offset: 135 (0x87) 1326 uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) 1327 uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) 1328 uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A) 1329 uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B) 1330 uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C) 1331 uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D) 1332 uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) 1333 uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F) 1334 uint32_t reserved_144; // offset: 144 (0x90) 1335 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) 1336 uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92) 1337 uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93) 1338 uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94) 1339 uint32_t cp_hqd_ib_control; // offset: 149 (0x95) 1340 uint32_t cp_hqd_iq_timer; // offset: 150 (0x96) 1341 uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97) 1342 uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98) 1343 uint32_t cp_hqd_dma_offload; // offset: 153 (0x99) 1344 uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A) 1345 uint32_t cp_hqd_msg_type; // offset: 155 (0x9B) 1346 uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C) 1347 uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D) 1348 uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E) 1349 uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F) 1350 uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0) 1351 uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1) 1352 uint32_t cp_mqd_control; // offset: 162 (0xA2) 1353 uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3) 1354 uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4) 1355 uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5) 1356 uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6) 1357 uint32_t cp_hqd_eop_control; // offset: 167 (0xA7) 1358 uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8) 1359 uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9) 1360 uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA) 1361 uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB) 1362 uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC) 1363 uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD) 1364 uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE) 1365 uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF) 1366 uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0) 1367 uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1) 1368 uint32_t reserved_178; // offset: 178 (0xB2) 1369 uint32_t cp_hqd_error; // offset: 179 (0xB3) 1370 uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4) 1371 uint32_t cp_hqd_aql_control; // offset: 181 (0xB5) 1372 uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6) 1373 uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7) 1374 uint32_t cp_hqd_suspend_cntl_stack_offset; // offset: 184 (0xB8) 1375 uint32_t cp_hqd_suspend_cntl_stack_dw_cnt; // offset: 185 (0xB9) 1376 uint32_t cp_hqd_suspend_wg_state_offset; // offset: 186 (0xBA) 1377 uint32_t cp_hqd_ddid_rptr; // offset: 187 (0xBB) 1378 uint32_t cp_hqd_ddid_wptr; // offset: 188 (0xBC) 1379 uint32_t cp_hqd_ddid_inflight_count; // offset: 189 (0xBD) 1380 uint32_t cp_hqd_ddid_delta_rpt_count; // offset: 190 (0xBE) 1381 uint32_t cp_hqd_dequeue_status; // offset: 191 (0xBF) 1382 uint32_t cp_hqd_aql_control_1; // offset: 192 (0xC0) 1383 uint32_t cp_hqd_aql_dispatch_id; // offset: 193 (0xC1) 1384 uint32_t cp_hqd_aql_dispatch_id_hi; // offset: 194 (0xC2) 1385 uint32_t cp_hqd_kd_base; // offset: 195 (0xC3) 1386 uint32_t cp_hqd_kd_base_hi; // offset: 196 (0xC4) 1387 uint32_t cp_hqd_kd_cntl; // offset: 197 (0xC5) 1388 uint32_t reserved_198; // offset: 198 (0xC6) 1389 uint32_t reserved_199; // offset: 199 (0xC7) 1390 uint32_t reserved_200; // offset: 200 (0xC8) 1391 uint32_t reserved_201; // offset: 201 (0xC9) 1392 uint32_t reserved_202; // offset: 202 (0xCA) 1393 uint32_t reserved_203; // offset: 203 (0xCB) 1394 uint32_t reserved_204; // offset: 204 (0xCC) 1395 uint32_t reserved_205; // offset: 205 (0xCD) 1396 uint32_t reserved_206; // offset: 206 (0xCE) 1397 uint32_t reserved_207; // offset: 207 (0xCF) 1398 uint32_t reserved_208; // offset: 208 (0xD0) 1399 uint32_t reserved_209; // offset: 209 (0xD1) 1400 uint32_t reserved_210; // offset: 210 (0xD2) 1401 uint32_t reserved_211; // offset: 211 (0xD3) 1402 uint32_t reserved_212; // offset: 212 (0xD4) 1403 uint32_t reserved_213; // offset: 213 (0xD5) 1404 uint32_t reserved_214; // offset: 214 (0xD6) 1405 uint32_t reserved_215; // offset: 215 (0xD7) 1406 uint32_t reserved_216; // offset: 216 (0xD8) 1407 uint32_t reserved_217; // offset: 217 (0xD9) 1408 uint32_t reserved_218; // offset: 218 (0xDA) 1409 uint32_t reserved_219; // offset: 219 (0xDB) 1410 uint32_t reserved_220; // offset: 220 (0xDC) 1411 uint32_t reserved_221; // offset: 221 (0xDD) 1412 uint32_t reserved_222; // offset: 222 (0xDE) 1413 uint32_t reserved_223; // offset: 223 (0xDF) 1414 uint32_t reserved_224; // offset: 224 (0xE0) 1415 uint32_t pm4_target_xcc_in_xcp; // offset: 225 (0xE1) 1416 uint32_t cp_mqd_stride_size; // offset: 226 (0xE2) 1417 uint32_t xcc_sync_counter; // offset: 227 (0xE3) 1418 uint32_t set_resources_header; // offset: 228 (0xE4) 1419 uint32_t set_resources_dw1; // offset: 229 (0xE5) 1420 uint32_t set_resources_dw2; // offset: 230 (0xE6) 1421 uint32_t set_resources_dw3; // offset: 231 (0xE7) 1422 uint32_t set_resources_dw4; // offset: 232 (0xE8) 1423 uint32_t set_resources_dw5; // offset: 233 (0xE9) 1424 uint32_t set_resources_dw6; // offset: 234 (0xEA) 1425 uint32_t set_resources_dw7; // offset: 235 (0xEB) 1426 uint32_t reserved_236; // offset: 236 (0xEC) 1427 uint32_t reserved_237; // offset: 237 (0xED) 1428 uint32_t reserved_238; // offset: 238 (0xEE) 1429 uint32_t reserved_239; // offset: 239 (0xEF) 1430 uint32_t reserved_240; // offset: 240 (0xF0) 1431 uint32_t reserved_241; // offset: 241 (0xF1) 1432 uint32_t reserved_242; // offset: 242 (0xF2) 1433 uint32_t reserved_243; // offset: 243 (0xF3) 1434 uint32_t reserved_244; // offset: 244 (0xF4) 1435 uint32_t reserved_245; // offset: 245 (0xF5) 1436 uint32_t reserved_246; // offset: 246 (0xF6) 1437 uint32_t reserved_247; // offset: 247 (0xF7) 1438 uint32_t reserved_248; // offset: 248 (0xF8) 1439 uint32_t reserved_249; // offset: 249 (0xF9) 1440 uint32_t reserved_250; // offset: 250 (0xFA) 1441 uint32_t reserved_251; // offset: 251 (0xFB) 1442 uint32_t reserved_252; // offset: 252 (0xFC) 1443 uint32_t reserved_253; // offset: 253 (0xFD) 1444 uint32_t reserved_254; // offset: 254 (0xFE) 1445 uint32_t reserved_255; // offset: 255 (0xFF) 1446 uint32_t control_buf_addr_lo; // offset: 256 (0x100) 1447 uint32_t control_buf_addr_hi; // offset: 257 (0x101) 1448 uint32_t control_buf_wptr_lo; // offset: 258 (0x102) 1449 uint32_t control_buf_wptr_hi; // offset: 259 (0x103) 1450 uint32_t control_buf_dptr_lo; // offset: 260 (0x104) 1451 uint32_t control_buf_dptr_hi; // offset: 261 (0x105) 1452 uint32_t draw_ring_addr_lo; // offset: 262 (0x106) 1453 uint32_t draw_ring_addr_hi; // offset: 263 (0x107) 1454 uint32_t control_buf_num_entries; // offset: 264 (0x108) 1455 uint32_t reserved_265; // offset: 265 (0x109) 1456 uint32_t reserved_266; // offset: 266 (0x10A) 1457 uint32_t reserved_267; // offset: 267 (0x10B) 1458 uint32_t reserved_268; // offset: 268 (0x10C) 1459 uint32_t reserved_269; // offset: 269 (0x10D) 1460 uint32_t reserved_270; // offset: 270 (0x10E) 1461 uint32_t reserved_271; // offset: 271 (0x10F) 1462 uint32_t dfwx_flags; // offset: 272 (0x110) 1463 uint32_t dfwx_slot; // offset: 273 (0x111) 1464 uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112) 1465 uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113) 1466 uint32_t dfwx_queue_connect_addr_lo; // offset: 276 (0x114) 1467 uint32_t dfwx_queue_connect_addr_hi; // offset: 277 (0x115) 1468 uint32_t reserved_278; // offset: 278 (0x116) 1469 uint32_t reserved_279; // offset: 279 (0x117) 1470 uint32_t reserved_280; // offset: 280 (0x118) 1471 uint32_t reserved_281; // offset: 281 (0x119) 1472 uint32_t reserved_282; // offset: 282 (0x11A) 1473 uint32_t reserved_283; // offset: 283 (0x11B) 1474 uint32_t reserved_284; // offset: 284 (0x11C) 1475 uint32_t reserved_285; // offset: 285 (0x11D) 1476 uint32_t reserved_286; // offset: 286 (0x11E) 1477 uint32_t reserved_287; // offset: 287 (0x11F) 1478 uint32_t cp_mqd_query_time_lo; // offset: 288 (0x120) 1479 uint32_t cp_mqd_query_time_hi; // offset: 289 (0x121) 1480 uint32_t cp_mqd_connect_start_time_lo; // offset: 290 (0x122) 1481 uint32_t cp_mqd_connect_start_time_hi; // offset: 291 (0x123) 1482 uint32_t cp_mqd_connect_end_time_lo; // offset: 292 (0x124) 1483 uint32_t cp_mqd_connect_end_time_hi; // offset: 293 (0x125) 1484 uint32_t cp_mqd_connect_end_wf_count; // offset: 294 (0x126) 1485 uint32_t cp_mqd_connect_end_pq_rptr; // offset: 295 (0x127) 1486 uint32_t cp_mqd_connect_end_pq_wptr; // offset: 296 (0x128) 1487 uint32_t cp_mqd_connect_end_ib_rptr; // offset: 297 (0x129) 1488 uint32_t cp_mqd_readindex_lo; // offset: 298 (0x12A) 1489 uint32_t cp_mqd_readindex_hi; // offset: 299 (0x12B) 1490 uint32_t cp_mqd_save_start_time_lo; // offset: 300 (0x12C) 1491 uint32_t cp_mqd_save_start_time_hi; // offset: 301 (0x12D) 1492 uint32_t cp_mqd_save_end_time_lo; // offset: 302 (0x12E) 1493 uint32_t cp_mqd_save_end_time_hi; // offset: 303 (0x12F) 1494 uint32_t cp_mqd_restore_start_time_lo; // offset: 304 (0x130) 1495 uint32_t cp_mqd_restore_start_time_hi; // offset: 305 (0x131) 1496 uint32_t cp_mqd_restore_end_time_lo; // offset: 306 (0x132) 1497 uint32_t cp_mqd_restore_end_time_hi; // offset: 307 (0x133) 1498 uint32_t disable_queue; // offset: 308 (0x134) 1499 uint32_t reserved_309; // offset: 309 (0x135) 1500 uint32_t reserved_310; // offset: 310 (0x136) 1501 uint32_t reserved_311; // offset: 311 (0x137) 1502 uint32_t reserved_312; // offset: 312 (0x138) 1503 uint32_t reserved_313; // offset: 313 (0x139) 1504 uint32_t reserved_314; // offset: 314 (0x13A) 1505 uint32_t reserved_315; // offset: 315 (0x13B) 1506 uint32_t reserved_316; // offset: 316 (0x13C) 1507 uint32_t reserved_317; // offset: 317 (0x13D) 1508 uint32_t reserved_318; // offset: 318 (0x13E) 1509 uint32_t reserved_319; // offset: 319 (0x13F) 1510 uint32_t reserved_320; // offset: 320 (0x140) 1511 uint32_t reserved_321; // offset: 321 (0x141) 1512 uint32_t reserved_322; // offset: 322 (0x142) 1513 uint32_t reserved_323; // offset: 323 (0x143) 1514 uint32_t reserved_324; // offset: 324 (0x144) 1515 uint32_t reserved_325; // offset: 325 (0x145) 1516 uint32_t reserved_326; // offset: 326 (0x146) 1517 uint32_t reserved_327; // offset: 327 (0x147) 1518 uint32_t reserved_328; // offset: 328 (0x148) 1519 uint32_t reserved_329; // offset: 329 (0x149) 1520 uint32_t reserved_330; // offset: 330 (0x14A) 1521 uint32_t reserved_331; // offset: 331 (0x14B) 1522 uint32_t reserved_332; // offset: 332 (0x14C) 1523 uint32_t reserved_333; // offset: 333 (0x14D) 1524 uint32_t reserved_334; // offset: 334 (0x14E) 1525 uint32_t reserved_335; // offset: 335 (0x14F) 1526 uint32_t reserved_336; // offset: 336 (0x150) 1527 uint32_t reserved_337; // offset: 337 (0x151) 1528 uint32_t reserved_338; // offset: 338 (0x152) 1529 uint32_t reserved_339; // offset: 339 (0x153) 1530 uint32_t reserved_340; // offset: 340 (0x154) 1531 uint32_t reserved_341; // offset: 341 (0x155) 1532 uint32_t reserved_342; // offset: 342 (0x156) 1533 uint32_t reserved_343; // offset: 343 (0x157) 1534 uint32_t reserved_344; // offset: 344 (0x158) 1535 uint32_t reserved_345; // offset: 345 (0x159) 1536 uint32_t reserved_346; // offset: 346 (0x15A) 1537 uint32_t reserved_347; // offset: 347 (0x15B) 1538 uint32_t reserved_348; // offset: 348 (0x15C) 1539 uint32_t reserved_349; // offset: 349 (0x15D) 1540 uint32_t reserved_350; // offset: 350 (0x15E) 1541 uint32_t reserved_351; // offset: 351 (0x15F) 1542 uint32_t reserved_352; // offset: 352 (0x160) 1543 uint32_t reserved_353; // offset: 353 (0x161) 1544 uint32_t reserved_354; // offset: 354 (0x162) 1545 uint32_t reserved_355; // offset: 355 (0x163) 1546 uint32_t reserved_356; // offset: 356 (0x164) 1547 uint32_t reserved_357; // offset: 357 (0x165) 1548 uint32_t reserved_358; // offset: 358 (0x166) 1549 uint32_t reserved_359; // offset: 359 (0x167) 1550 uint32_t reserved_360; // offset: 360 (0x168) 1551 uint32_t reserved_361; // offset: 361 (0x169) 1552 uint32_t reserved_362; // offset: 362 (0x16A) 1553 uint32_t reserved_363; // offset: 363 (0x16B) 1554 uint32_t reserved_364; // offset: 364 (0x16C) 1555 uint32_t reserved_365; // offset: 365 (0x16D) 1556 uint32_t reserved_366; // offset: 366 (0x16E) 1557 uint32_t reserved_367; // offset: 367 (0x16F) 1558 uint32_t reserved_368; // offset: 368 (0x170) 1559 uint32_t reserved_369; // offset: 369 (0x171) 1560 uint32_t reserved_370; // offset: 370 (0x172) 1561 uint32_t reserved_371; // offset: 371 (0x173) 1562 uint32_t reserved_372; // offset: 372 (0x174) 1563 uint32_t reserved_373; // offset: 373 (0x175) 1564 uint32_t reserved_374; // offset: 374 (0x176) 1565 uint32_t reserved_375; // offset: 375 (0x177) 1566 uint32_t reserved_376; // offset: 376 (0x178) 1567 uint32_t reserved_377; // offset: 377 (0x179) 1568 uint32_t reserved_378; // offset: 378 (0x17A) 1569 uint32_t reserved_379; // offset: 379 (0x17B) 1570 uint32_t reserved_380; // offset: 380 (0x17C) 1571 uint32_t reserved_381; // offset: 381 (0x17D) 1572 uint32_t reserved_382; // offset: 382 (0x17E) 1573 uint32_t reserved_383; // offset: 383 (0x17F) 1574 uint32_t iqtimer_pkt_header; // offset: 384 (0x180) 1575 uint32_t iqtimer_pkt_dw0; // offset: 385 (0x181) 1576 uint32_t iqtimer_pkt_dw1; // offset: 386 (0x182) 1577 uint32_t iqtimer_pkt_dw2; // offset: 387 (0x183) 1578 uint32_t iqtimer_pkt_dw3; // offset: 388 (0x184) 1579 uint32_t iqtimer_pkt_dw4; // offset: 389 (0x185) 1580 uint32_t iqtimer_pkt_dw5; // offset: 390 (0x186) 1581 uint32_t iqtimer_pkt_dw6; // offset: 391 (0x187) 1582 uint32_t iqtimer_pkt_dw7; // offset: 392 (0x188) 1583 uint32_t iqtimer_pkt_dw8; // offset: 393 (0x189) 1584 uint32_t iqtimer_pkt_dw9; // offset: 394 (0x18A) 1585 uint32_t iqtimer_pkt_dw10; // offset: 395 (0x18B) 1586 uint32_t iqtimer_pkt_dw11; // offset: 396 (0x18C) 1587 uint32_t iqtimer_pkt_dw12; // offset: 397 (0x18D) 1588 uint32_t iqtimer_pkt_dw13; // offset: 398 (0x18E) 1589 uint32_t iqtimer_pkt_dw14; // offset: 399 (0x18F) 1590 uint32_t iqtimer_pkt_dw15; // offset: 400 (0x190) 1591 uint32_t iqtimer_pkt_dw16; // offset: 401 (0x191) 1592 uint32_t iqtimer_pkt_dw17; // offset: 402 (0x192) 1593 uint32_t iqtimer_pkt_dw18; // offset: 403 (0x193) 1594 uint32_t iqtimer_pkt_dw19; // offset: 404 (0x194) 1595 uint32_t iqtimer_pkt_dw20; // offset: 405 (0x195) 1596 uint32_t iqtimer_pkt_dw21; // offset: 406 (0x196) 1597 uint32_t iqtimer_pkt_dw22; // offset: 407 (0x197) 1598 uint32_t iqtimer_pkt_dw23; // offset: 408 (0x198) 1599 uint32_t iqtimer_pkt_dw24; // offset: 409 (0x199) 1600 uint32_t iqtimer_pkt_dw25; // offset: 410 (0x19A) 1601 uint32_t iqtimer_pkt_dw26; // offset: 411 (0x19B) 1602 uint32_t iqtimer_pkt_dw27; // offset: 412 (0x19C) 1603 uint32_t iqtimer_pkt_dw28; // offset: 413 (0x19D) 1604 uint32_t iqtimer_pkt_dw29; // offset: 414 (0x19E) 1605 uint32_t iqtimer_pkt_dw30; // offset: 415 (0x19F) 1606 uint32_t iqtimer_pkt_dw31; // offset: 416 (0x1A0) 1607 uint32_t reserved_417; // offset: 417 (0x1A1) 1608 uint32_t reserved_418; // offset: 418 (0x1A2) 1609 uint32_t reserved_419; // offset: 419 (0x1A3) 1610 uint32_t reserved_420; // offset: 420 (0x1A4) 1611 uint32_t reserved_421; // offset: 421 (0x1A5) 1612 uint32_t reserved_422; // offset: 422 (0x1A6) 1613 uint32_t reserved_423; // offset: 423 (0x1A7) 1614 uint32_t reserved_424; // offset: 424 (0x1A8) 1615 uint32_t reserved_425; // offset: 425 (0x1A9) 1616 uint32_t reserved_426; // offset: 426 (0x1AA) 1617 uint32_t reserved_427; // offset: 427 (0x1AB) 1618 uint32_t reserved_428; // offset: 428 (0x1AC) 1619 uint32_t reserved_429; // offset: 429 (0x1AD) 1620 uint32_t reserved_430; // offset: 430 (0x1AE) 1621 uint32_t reserved_431; // offset: 431 (0x1AF) 1622 uint32_t reserved_432; // offset: 432 (0x1B0) 1623 uint32_t reserved_433; // offset: 433 (0x1B1) 1624 uint32_t reserved_434; // offset: 434 (0x1B2) 1625 uint32_t reserved_435; // offset: 435 (0x1B3) 1626 uint32_t reserved_436; // offset: 436 (0x1B4) 1627 uint32_t reserved_437; // offset: 437 (0x1B5) 1628 uint32_t reserved_438; // offset: 438 (0x1B6) 1629 uint32_t reserved_439; // offset: 439 (0x1B7) 1630 uint32_t reserved_440; // offset: 440 (0x1B8) 1631 uint32_t reserved_441; // offset: 441 (0x1B9) 1632 uint32_t reserved_442; // offset: 442 (0x1BA) 1633 uint32_t reserved_443; // offset: 443 (0x1BB) 1634 uint32_t reserved_444; // offset: 444 (0x1BC) 1635 uint32_t reserved_445; // offset: 445 (0x1BD) 1636 uint32_t reserved_446; // offset: 446 (0x1BE) 1637 uint32_t reserved_447; // offset: 447 (0x1BF) 1638 uint32_t reserved_448; // offset: 448 (0x1C0) 1639 uint32_t reserved_449; // offset: 449 (0x1C1) 1640 uint32_t reserved_450; // offset: 450 (0x1C2) 1641 uint32_t reserved_451; // offset: 451 (0x1C3) 1642 uint32_t reserved_452; // offset: 452 (0x1C4) 1643 uint32_t reserved_453; // offset: 453 (0x1C5) 1644 uint32_t reserved_454; // offset: 454 (0x1C6) 1645 uint32_t reserved_455; // offset: 455 (0x1C7) 1646 uint32_t reserved_456; // offset: 456 (0x1C8) 1647 uint32_t reserved_457; // offset: 457 (0x1C9) 1648 uint32_t reserved_458; // offset: 458 (0x1CA) 1649 uint32_t reserved_459; // offset: 459 (0x1CB) 1650 uint32_t reserved_460; // offset: 460 (0x1CC) 1651 uint32_t reserved_461; // offset: 461 (0x1CD) 1652 uint32_t reserved_462; // offset: 462 (0x1CE) 1653 uint32_t reserved_463; // offset: 463 (0x1CF) 1654 uint32_t reserved_464; // offset: 464 (0x1D0) 1655 uint32_t reserved_465; // offset: 465 (0x1D1) 1656 uint32_t reserved_466; // offset: 466 (0x1D2) 1657 uint32_t reserved_467; // offset: 467 (0x1D3) 1658 uint32_t reserved_468; // offset: 468 (0x1D4) 1659 uint32_t reserved_469; // offset: 469 (0x1D5) 1660 uint32_t reserved_470; // offset: 470 (0x1D6) 1661 uint32_t reserved_471; // offset: 471 (0x1D7) 1662 uint32_t reserved_472; // offset: 472 (0x1D8) 1663 uint32_t reserved_473; // offset: 473 (0x1D9) 1664 uint32_t reserved_474; // offset: 474 (0x1DA) 1665 uint32_t reserved_475; // offset: 475 (0x1DB) 1666 uint32_t reserved_476; // offset: 476 (0x1DC) 1667 uint32_t reserved_477; // offset: 477 (0x1DD) 1668 uint32_t reserved_478; // offset: 478 (0x1DE) 1669 uint32_t reserved_479; // offset: 479 (0x1DF) 1670 uint32_t reserved_480; // offset: 480 (0x1E0) 1671 uint32_t reserved_481; // offset: 481 (0x1E1) 1672 uint32_t reserved_482; // offset: 482 (0x1E2) 1673 uint32_t reserved_483; // offset: 483 (0x1E3) 1674 uint32_t reserved_484; // offset: 484 (0x1E4) 1675 uint32_t reserved_485; // offset: 485 (0x1E5) 1676 uint32_t reserved_486; // offset: 486 (0x1E6) 1677 uint32_t reserved_487; // offset: 487 (0x1E7) 1678 uint32_t reserved_488; // offset: 488 (0x1E8) 1679 uint32_t reserved_489; // offset: 489 (0x1E9) 1680 uint32_t reserved_490; // offset: 490 (0x1EA) 1681 uint32_t reserved_491; // offset: 491 (0x1EB) 1682 uint32_t reserved_492; // offset: 492 (0x1EC) 1683 uint32_t reserved_493; // offset: 493 (0x1ED) 1684 uint32_t reserved_494; // offset: 494 (0x1EE) 1685 uint32_t reserved_495; // offset: 495 (0x1EF) 1686 uint32_t reserved_496; // offset: 496 (0x1F0) 1687 uint32_t reserved_497; // offset: 497 (0x1F1) 1688 uint32_t reserved_498; // offset: 498 (0x1F2) 1689 uint32_t reserved_499; // offset: 499 (0x1F3) 1690 uint32_t reserved_500; // offset: 500 (0x1F4) 1691 uint32_t reserved_501; // offset: 501 (0x1F5) 1692 uint32_t reserved_502; // offset: 502 (0x1F6) 1693 uint32_t reserved_503; // offset: 503 (0x1F7) 1694 uint32_t reserved_504; // offset: 504 (0x1F8) 1695 uint32_t reserved_505; // offset: 505 (0x1F9) 1696 uint32_t reserved_506; // offset: 506 (0x1FA) 1697 uint32_t reserved_507; // offset: 507 (0x1FB) 1698 uint32_t reserved_508; // offset: 508 (0x1FC) 1699 uint32_t reserved_509; // offset: 509 (0x1FD) 1700 uint32_t reserved_510; // offset: 510 (0x1FE) 1701 uint32_t reserved_511; // offset: 511 (0x1FF) 1702 uint32_t reserved_512; // offset: 512 (0x200) 1703 uint32_t reserved_513; // offset: 513 (0x201) 1704 uint32_t reserved_514; // offset: 514 (0x202) 1705 uint32_t reserved_515; // offset: 515 (0x203) 1706 uint32_t reserved_516; // offset: 516 (0x204) 1707 uint32_t reserved_517; // offset: 517 (0x205) 1708 uint32_t reserved_518; // offset: 518 (0x206) 1709 uint32_t reserved_519; // offset: 519 (0x207) 1710 uint32_t reserved_520; // offset: 520 (0x208) 1711 uint32_t reserved_521; // offset: 521 (0x209) 1712 uint32_t reserved_522; // offset: 522 (0x20A) 1713 uint32_t reserved_523; // offset: 523 (0x20B) 1714 uint32_t reserved_524; // offset: 524 (0x20C) 1715 uint32_t reserved_525; // offset: 525 (0x20D) 1716 uint32_t reserved_526; // offset: 526 (0x20E) 1717 uint32_t reserved_527; // offset: 527 (0x20F) 1718 uint32_t reserved_528; // offset: 528 (0x210) 1719 uint32_t reserved_529; // offset: 529 (0x211) 1720 uint32_t reserved_530; // offset: 530 (0x212) 1721 uint32_t reserved_531; // offset: 531 (0x213) 1722 uint32_t reserved_532; // offset: 532 (0x214) 1723 uint32_t reserved_533; // offset: 533 (0x215) 1724 uint32_t reserved_534; // offset: 534 (0x216) 1725 uint32_t reserved_535; // offset: 535 (0x217) 1726 uint32_t reserved_536; // offset: 536 (0x218) 1727 uint32_t reserved_537; // offset: 537 (0x219) 1728 uint32_t reserved_538; // offset: 538 (0x21A) 1729 uint32_t reserved_539; // offset: 539 (0x21B) 1730 uint32_t reserved_540; // offset: 540 (0x21C) 1731 uint32_t reserved_541; // offset: 541 (0x21D) 1732 uint32_t reserved_542; // offset: 542 (0x21E) 1733 uint32_t reserved_543; // offset: 543 (0x21F) 1734 uint32_t reserved_544; // offset: 544 (0x220) 1735 uint32_t reserved_545; // offset: 545 (0x221) 1736 uint32_t reserved_546; // offset: 546 (0x222) 1737 uint32_t reserved_547; // offset: 547 (0x223) 1738 uint32_t reserved_548; // offset: 548 (0x224) 1739 uint32_t reserved_549; // offset: 549 (0x225) 1740 uint32_t reserved_550; // offset: 550 (0x226) 1741 uint32_t reserved_551; // offset: 551 (0x227) 1742 uint32_t reserved_552; // offset: 552 (0x228) 1743 uint32_t reserved_553; // offset: 553 (0x229) 1744 uint32_t reserved_554; // offset: 554 (0x22A) 1745 uint32_t reserved_555; // offset: 555 (0x22B) 1746 uint32_t reserved_556; // offset: 556 (0x22C) 1747 uint32_t reserved_557; // offset: 557 (0x22D) 1748 uint32_t reserved_558; // offset: 558 (0x22E) 1749 uint32_t reserved_559; // offset: 559 (0x22F) 1750 uint32_t reserved_560; // offset: 560 (0x230) 1751 uint32_t reserved_561; // offset: 561 (0x231) 1752 uint32_t reserved_562; // offset: 562 (0x232) 1753 uint32_t reserved_563; // offset: 563 (0x233) 1754 uint32_t reserved_564; // offset: 564 (0x234) 1755 uint32_t reserved_565; // offset: 565 (0x235) 1756 uint32_t reserved_566; // offset: 566 (0x236) 1757 uint32_t reserved_567; // offset: 567 (0x237) 1758 uint32_t reserved_568; // offset: 568 (0x238) 1759 uint32_t reserved_569; // offset: 569 (0x239) 1760 uint32_t reserved_570; // offset: 570 (0x23A) 1761 uint32_t reserved_571; // offset: 571 (0x23B) 1762 uint32_t reserved_572; // offset: 572 (0x23C) 1763 uint32_t reserved_573; // offset: 573 (0x23D) 1764 uint32_t reserved_574; // offset: 574 (0x23E) 1765 uint32_t reserved_575; // offset: 575 (0x23F) 1766 uint32_t reserved_576; // offset: 576 (0x240) 1767 uint32_t reserved_577; // offset: 577 (0x241) 1768 uint32_t reserved_578; // offset: 578 (0x242) 1769 uint32_t reserved_579; // offset: 579 (0x243) 1770 uint32_t reserved_580; // offset: 580 (0x244) 1771 uint32_t reserved_581; // offset: 581 (0x245) 1772 uint32_t reserved_582; // offset: 582 (0x246) 1773 uint32_t reserved_583; // offset: 583 (0x247) 1774 uint32_t reserved_584; // offset: 584 (0x248) 1775 uint32_t reserved_585; // offset: 585 (0x249) 1776 uint32_t reserved_586; // offset: 586 (0x24A) 1777 uint32_t reserved_587; // offset: 587 (0x24B) 1778 uint32_t reserved_588; // offset: 588 (0x24C) 1779 uint32_t reserved_589; // offset: 589 (0x24D) 1780 uint32_t reserved_590; // offset: 590 (0x24E) 1781 uint32_t reserved_591; // offset: 591 (0x24F) 1782 uint32_t reserved_592; // offset: 592 (0x250) 1783 uint32_t reserved_593; // offset: 593 (0x251) 1784 uint32_t reserved_594; // offset: 594 (0x252) 1785 uint32_t reserved_595; // offset: 595 (0x253) 1786 uint32_t reserved_596; // offset: 596 (0x254) 1787 uint32_t reserved_597; // offset: 597 (0x255) 1788 uint32_t reserved_598; // offset: 598 (0x256) 1789 uint32_t reserved_599; // offset: 599 (0x257) 1790 uint32_t reserved_600; // offset: 600 (0x258) 1791 uint32_t reserved_601; // offset: 601 (0x259) 1792 uint32_t reserved_602; // offset: 602 (0x25A) 1793 uint32_t reserved_603; // offset: 603 (0x25B) 1794 uint32_t reserved_604; // offset: 604 (0x25C) 1795 uint32_t reserved_605; // offset: 605 (0x25D) 1796 uint32_t reserved_606; // offset: 606 (0x25E) 1797 uint32_t reserved_607; // offset: 607 (0x25F) 1798 uint32_t reserved_608; // offset: 608 (0x260) 1799 uint32_t reserved_609; // offset: 609 (0x261) 1800 uint32_t reserved_610; // offset: 610 (0x262) 1801 uint32_t reserved_611; // offset: 611 (0x263) 1802 uint32_t reserved_612; // offset: 612 (0x264) 1803 uint32_t reserved_613; // offset: 613 (0x265) 1804 uint32_t reserved_614; // offset: 614 (0x266) 1805 uint32_t reserved_615; // offset: 615 (0x267) 1806 uint32_t reserved_616; // offset: 616 (0x268) 1807 uint32_t reserved_617; // offset: 617 (0x269) 1808 uint32_t reserved_618; // offset: 618 (0x26A) 1809 uint32_t reserved_619; // offset: 619 (0x26B) 1810 uint32_t reserved_620; // offset: 620 (0x26C) 1811 uint32_t reserved_621; // offset: 621 (0x26D) 1812 uint32_t reserved_622; // offset: 622 (0x26E) 1813 uint32_t reserved_623; // offset: 623 (0x26F) 1814 uint32_t reserved_624; // offset: 624 (0x270) 1815 uint32_t reserved_625; // offset: 625 (0x271) 1816 uint32_t reserved_626; // offset: 626 (0x272) 1817 uint32_t reserved_627; // offset: 627 (0x273) 1818 uint32_t reserved_628; // offset: 628 (0x274) 1819 uint32_t reserved_629; // offset: 629 (0x275) 1820 uint32_t reserved_630; // offset: 630 (0x276) 1821 uint32_t reserved_631; // offset: 631 (0x277) 1822 uint32_t reserved_632; // offset: 632 (0x278) 1823 uint32_t reserved_633; // offset: 633 (0x279) 1824 uint32_t reserved_634; // offset: 634 (0x27A) 1825 uint32_t reserved_635; // offset: 635 (0x27B) 1826 uint32_t reserved_636; // offset: 636 (0x27C) 1827 uint32_t reserved_637; // offset: 637 (0x27D) 1828 uint32_t reserved_638; // offset: 638 (0x27E) 1829 uint32_t reserved_639; // offset: 639 (0x27F) 1830 uint32_t reserved_640; // offset: 640 (0x280) 1831 uint32_t reserved_641; // offset: 641 (0x281) 1832 uint32_t reserved_642; // offset: 642 (0x282) 1833 uint32_t reserved_643; // offset: 643 (0x283) 1834 uint32_t reserved_644; // offset: 644 (0x284) 1835 uint32_t reserved_645; // offset: 645 (0x285) 1836 uint32_t reserved_646; // offset: 646 (0x286) 1837 uint32_t reserved_647; // offset: 647 (0x287) 1838 uint32_t reserved_648; // offset: 648 (0x288) 1839 uint32_t reserved_649; // offset: 649 (0x289) 1840 uint32_t reserved_650; // offset: 650 (0x28A) 1841 uint32_t reserved_651; // offset: 651 (0x28B) 1842 uint32_t reserved_652; // offset: 652 (0x28C) 1843 uint32_t reserved_653; // offset: 653 (0x28D) 1844 uint32_t reserved_654; // offset: 654 (0x28E) 1845 uint32_t reserved_655; // offset: 655 (0x28F) 1846 uint32_t reserved_656; // offset: 656 (0x290) 1847 uint32_t reserved_657; // offset: 657 (0x291) 1848 uint32_t reserved_658; // offset: 658 (0x292) 1849 uint32_t reserved_659; // offset: 659 (0x293) 1850 uint32_t reserved_660; // offset: 660 (0x294) 1851 uint32_t reserved_661; // offset: 661 (0x295) 1852 uint32_t reserved_662; // offset: 662 (0x296) 1853 uint32_t reserved_663; // offset: 663 (0x297) 1854 uint32_t reserved_664; // offset: 664 (0x298) 1855 uint32_t reserved_665; // offset: 665 (0x299) 1856 uint32_t reserved_666; // offset: 666 (0x29A) 1857 uint32_t reserved_667; // offset: 667 (0x29B) 1858 uint32_t reserved_668; // offset: 668 (0x29C) 1859 uint32_t reserved_669; // offset: 669 (0x29D) 1860 uint32_t reserved_670; // offset: 670 (0x29E) 1861 uint32_t reserved_671; // offset: 671 (0x29F) 1862 uint32_t reserved_672; // offset: 672 (0x2A0) 1863 uint32_t reserved_673; // offset: 673 (0x2A1) 1864 uint32_t reserved_674; // offset: 674 (0x2A2) 1865 uint32_t reserved_675; // offset: 675 (0x2A3) 1866 uint32_t reserved_676; // offset: 676 (0x2A4) 1867 uint32_t reserved_677; // offset: 677 (0x2A5) 1868 uint32_t reserved_678; // offset: 678 (0x2A6) 1869 uint32_t reserved_679; // offset: 679 (0x2A7) 1870 uint32_t reserved_680; // offset: 680 (0x2A8) 1871 uint32_t reserved_681; // offset: 681 (0x2A9) 1872 uint32_t reserved_682; // offset: 682 (0x2AA) 1873 uint32_t reserved_683; // offset: 683 (0x2AB) 1874 uint32_t reserved_684; // offset: 684 (0x2AC) 1875 uint32_t reserved_685; // offset: 685 (0x2AD) 1876 uint32_t reserved_686; // offset: 686 (0x2AE) 1877 uint32_t reserved_687; // offset: 687 (0x2AF) 1878 uint32_t reserved_688; // offset: 688 (0x2B0) 1879 uint32_t reserved_689; // offset: 689 (0x2B1) 1880 uint32_t reserved_690; // offset: 690 (0x2B2) 1881 uint32_t reserved_691; // offset: 691 (0x2B3) 1882 uint32_t reserved_692; // offset: 692 (0x2B4) 1883 uint32_t reserved_693; // offset: 693 (0x2B5) 1884 uint32_t reserved_694; // offset: 694 (0x2B6) 1885 uint32_t reserved_695; // offset: 695 (0x2B7) 1886 uint32_t reserved_696; // offset: 696 (0x2B8) 1887 uint32_t reserved_697; // offset: 697 (0x2B9) 1888 uint32_t reserved_698; // offset: 698 (0x2BA) 1889 uint32_t reserved_699; // offset: 699 (0x2BB) 1890 uint32_t reserved_700; // offset: 700 (0x2BC) 1891 uint32_t reserved_701; // offset: 701 (0x2BD) 1892 uint32_t reserved_702; // offset: 702 (0x2BE) 1893 uint32_t reserved_703; // offset: 703 (0x2BF) 1894 uint32_t reserved_704; // offset: 704 (0x2C0) 1895 uint32_t reserved_705; // offset: 705 (0x2C1) 1896 uint32_t reserved_706; // offset: 706 (0x2C2) 1897 uint32_t reserved_707; // offset: 707 (0x2C3) 1898 uint32_t reserved_708; // offset: 708 (0x2C4) 1899 uint32_t reserved_709; // offset: 709 (0x2C5) 1900 uint32_t reserved_710; // offset: 710 (0x2C6) 1901 uint32_t reserved_711; // offset: 711 (0x2C7) 1902 uint32_t reserved_712; // offset: 712 (0x2C8) 1903 uint32_t reserved_713; // offset: 713 (0x2C9) 1904 uint32_t reserved_714; // offset: 714 (0x2CA) 1905 uint32_t reserved_715; // offset: 715 (0x2CB) 1906 uint32_t reserved_716; // offset: 716 (0x2CC) 1907 uint32_t reserved_717; // offset: 717 (0x2CD) 1908 uint32_t reserved_718; // offset: 718 (0x2CE) 1909 uint32_t reserved_719; // offset: 719 (0x2CF) 1910 uint32_t reserved_720; // offset: 720 (0x2D0) 1911 uint32_t reserved_721; // offset: 721 (0x2D1) 1912 uint32_t reserved_722; // offset: 722 (0x2D2) 1913 uint32_t reserved_723; // offset: 723 (0x2D3) 1914 uint32_t reserved_724; // offset: 724 (0x2D4) 1915 uint32_t reserved_725; // offset: 725 (0x2D5) 1916 uint32_t reserved_726; // offset: 726 (0x2D6) 1917 uint32_t reserved_727; // offset: 727 (0x2D7) 1918 uint32_t reserved_728; // offset: 728 (0x2D8) 1919 uint32_t reserved_729; // offset: 729 (0x2D9) 1920 uint32_t reserved_730; // offset: 730 (0x2DA) 1921 uint32_t reserved_731; // offset: 731 (0x2DB) 1922 uint32_t reserved_732; // offset: 732 (0x2DC) 1923 uint32_t reserved_733; // offset: 733 (0x2DD) 1924 uint32_t reserved_734; // offset: 734 (0x2DE) 1925 uint32_t reserved_735; // offset: 735 (0x2DF) 1926 uint32_t reserved_736; // offset: 736 (0x2E0) 1927 uint32_t reserved_737; // offset: 737 (0x2E1) 1928 uint32_t reserved_738; // offset: 738 (0x2E2) 1929 uint32_t reserved_739; // offset: 739 (0x2E3) 1930 uint32_t reserved_740; // offset: 740 (0x2E4) 1931 uint32_t reserved_741; // offset: 741 (0x2E5) 1932 uint32_t reserved_742; // offset: 742 (0x2E6) 1933 uint32_t reserved_743; // offset: 743 (0x2E7) 1934 uint32_t reserved_744; // offset: 744 (0x2E8) 1935 uint32_t reserved_745; // offset: 745 (0x2E9) 1936 uint32_t reserved_746; // offset: 746 (0x2EA) 1937 uint32_t reserved_747; // offset: 747 (0x2EB) 1938 uint32_t reserved_748; // offset: 748 (0x2EC) 1939 uint32_t reserved_749; // offset: 749 (0x2ED) 1940 uint32_t reserved_750; // offset: 750 (0x2EE) 1941 uint32_t reserved_751; // offset: 751 (0x2EF) 1942 uint32_t reserved_752; // offset: 752 (0x2F0) 1943 uint32_t reserved_753; // offset: 753 (0x2F1) 1944 uint32_t reserved_754; // offset: 754 (0x2F2) 1945 uint32_t reserved_755; // offset: 755 (0x2F3) 1946 uint32_t reserved_756; // offset: 756 (0x2F4) 1947 uint32_t reserved_757; // offset: 757 (0x2F5) 1948 uint32_t reserved_758; // offset: 758 (0x2F6) 1949 uint32_t reserved_759; // offset: 759 (0x2F7) 1950 uint32_t reserved_760; // offset: 760 (0x2F8) 1951 uint32_t reserved_761; // offset: 761 (0x2F9) 1952 uint32_t reserved_762; // offset: 762 (0x2FA) 1953 uint32_t reserved_763; // offset: 763 (0x2FB) 1954 uint32_t reserved_764; // offset: 764 (0x2FC) 1955 uint32_t reserved_765; // offset: 765 (0x2FD) 1956 uint32_t reserved_766; // offset: 766 (0x2FE) 1957 uint32_t reserved_767; // offset: 767 (0x2FF) 1958 uint32_t reserved_768; // offset: 768 (0x300) 1959 uint32_t reserved_769; // offset: 769 (0x301) 1960 uint32_t reserved_770; // offset: 770 (0x302) 1961 uint32_t reserved_771; // offset: 771 (0x303) 1962 uint32_t reserved_772; // offset: 772 (0x304) 1963 uint32_t reserved_773; // offset: 773 (0x305) 1964 uint32_t reserved_774; // offset: 774 (0x306) 1965 uint32_t reserved_775; // offset: 775 (0x307) 1966 uint32_t reserved_776; // offset: 776 (0x308) 1967 uint32_t reserved_777; // offset: 777 (0x309) 1968 uint32_t reserved_778; // offset: 778 (0x30A) 1969 uint32_t reserved_779; // offset: 779 (0x30B) 1970 uint32_t reserved_780; // offset: 780 (0x30C) 1971 uint32_t reserved_781; // offset: 781 (0x30D) 1972 uint32_t reserved_782; // offset: 782 (0x30E) 1973 uint32_t reserved_783; // offset: 783 (0x30F) 1974 uint32_t reserved_784; // offset: 784 (0x310) 1975 uint32_t reserved_785; // offset: 785 (0x311) 1976 uint32_t reserved_786; // offset: 786 (0x312) 1977 uint32_t reserved_787; // offset: 787 (0x313) 1978 uint32_t reserved_788; // offset: 788 (0x314) 1979 uint32_t reserved_789; // offset: 789 (0x315) 1980 uint32_t reserved_790; // offset: 790 (0x316) 1981 uint32_t reserved_791; // offset: 791 (0x317) 1982 uint32_t reserved_792; // offset: 792 (0x318) 1983 uint32_t reserved_793; // offset: 793 (0x319) 1984 uint32_t reserved_794; // offset: 794 (0x31A) 1985 uint32_t reserved_795; // offset: 795 (0x31B) 1986 uint32_t reserved_796; // offset: 796 (0x31C) 1987 uint32_t reserved_797; // offset: 797 (0x31D) 1988 uint32_t reserved_798; // offset: 798 (0x31E) 1989 uint32_t reserved_799; // offset: 799 (0x31F) 1990 uint32_t reserved_800; // offset: 800 (0x320) 1991 uint32_t reserved_801; // offset: 801 (0x321) 1992 uint32_t reserved_802; // offset: 802 (0x322) 1993 uint32_t reserved_803; // offset: 803 (0x323) 1994 uint32_t reserved_804; // offset: 804 (0x324) 1995 uint32_t reserved_805; // offset: 805 (0x325) 1996 uint32_t reserved_806; // offset: 806 (0x326) 1997 uint32_t reserved_807; // offset: 807 (0x327) 1998 uint32_t reserved_808; // offset: 808 (0x328) 1999 uint32_t reserved_809; // offset: 809 (0x329) 2000 uint32_t reserved_810; // offset: 810 (0x32A) 2001 uint32_t reserved_811; // offset: 811 (0x32B) 2002 uint32_t reserved_812; // offset: 812 (0x32C) 2003 uint32_t reserved_813; // offset: 813 (0x32D) 2004 uint32_t reserved_814; // offset: 814 (0x32E) 2005 uint32_t reserved_815; // offset: 815 (0x32F) 2006 uint32_t reserved_816; // offset: 816 (0x330) 2007 uint32_t reserved_817; // offset: 817 (0x331) 2008 uint32_t reserved_818; // offset: 818 (0x332) 2009 uint32_t reserved_819; // offset: 819 (0x333) 2010 uint32_t reserved_820; // offset: 820 (0x334) 2011 uint32_t reserved_821; // offset: 821 (0x335) 2012 uint32_t reserved_822; // offset: 822 (0x336) 2013 uint32_t reserved_823; // offset: 823 (0x337) 2014 uint32_t reserved_824; // offset: 824 (0x338) 2015 uint32_t reserved_825; // offset: 825 (0x339) 2016 uint32_t reserved_826; // offset: 826 (0x33A) 2017 uint32_t reserved_827; // offset: 827 (0x33B) 2018 uint32_t reserved_828; // offset: 828 (0x33C) 2019 uint32_t reserved_829; // offset: 829 (0x33D) 2020 uint32_t reserved_830; // offset: 830 (0x33E) 2021 uint32_t reserved_831; // offset: 831 (0x33F) 2022 uint32_t reserved_832; // offset: 832 (0x340) 2023 uint32_t reserved_833; // offset: 833 (0x341) 2024 uint32_t reserved_834; // offset: 834 (0x342) 2025 uint32_t reserved_835; // offset: 835 (0x343) 2026 uint32_t reserved_836; // offset: 836 (0x344) 2027 uint32_t reserved_837; // offset: 837 (0x345) 2028 uint32_t reserved_838; // offset: 838 (0x346) 2029 uint32_t reserved_839; // offset: 839 (0x347) 2030 uint32_t reserved_840; // offset: 840 (0x348) 2031 uint32_t reserved_841; // offset: 841 (0x349) 2032 uint32_t reserved_842; // offset: 842 (0x34A) 2033 uint32_t reserved_843; // offset: 843 (0x34B) 2034 uint32_t reserved_844; // offset: 844 (0x34C) 2035 uint32_t reserved_845; // offset: 845 (0x34D) 2036 uint32_t reserved_846; // offset: 846 (0x34E) 2037 uint32_t reserved_847; // offset: 847 (0x34F) 2038 uint32_t reserved_848; // offset: 848 (0x350) 2039 uint32_t reserved_849; // offset: 849 (0x351) 2040 uint32_t reserved_850; // offset: 850 (0x352) 2041 uint32_t reserved_851; // offset: 851 (0x353) 2042 uint32_t reserved_852; // offset: 852 (0x354) 2043 uint32_t reserved_853; // offset: 853 (0x355) 2044 uint32_t reserved_854; // offset: 854 (0x356) 2045 uint32_t reserved_855; // offset: 855 (0x357) 2046 uint32_t reserved_856; // offset: 856 (0x358) 2047 uint32_t reserved_857; // offset: 857 (0x359) 2048 uint32_t reserved_858; // offset: 858 (0x35A) 2049 uint32_t reserved_859; // offset: 859 (0x35B) 2050 uint32_t reserved_860; // offset: 860 (0x35C) 2051 uint32_t reserved_861; // offset: 861 (0x35D) 2052 uint32_t reserved_862; // offset: 862 (0x35E) 2053 uint32_t reserved_863; // offset: 863 (0x35F) 2054 uint32_t reserved_864; // offset: 864 (0x360) 2055 uint32_t reserved_865; // offset: 865 (0x361) 2056 uint32_t reserved_866; // offset: 866 (0x362) 2057 uint32_t reserved_867; // offset: 867 (0x363) 2058 uint32_t reserved_868; // offset: 868 (0x364) 2059 uint32_t reserved_869; // offset: 869 (0x365) 2060 uint32_t reserved_870; // offset: 870 (0x366) 2061 uint32_t reserved_871; // offset: 871 (0x367) 2062 uint32_t reserved_872; // offset: 872 (0x368) 2063 uint32_t reserved_873; // offset: 873 (0x369) 2064 uint32_t reserved_874; // offset: 874 (0x36A) 2065 uint32_t reserved_875; // offset: 875 (0x36B) 2066 uint32_t reserved_876; // offset: 876 (0x36C) 2067 uint32_t reserved_877; // offset: 877 (0x36D) 2068 uint32_t reserved_878; // offset: 878 (0x36E) 2069 uint32_t reserved_879; // offset: 879 (0x36F) 2070 uint32_t reserved_880; // offset: 880 (0x370) 2071 uint32_t reserved_881; // offset: 881 (0x371) 2072 uint32_t reserved_882; // offset: 882 (0x372) 2073 uint32_t reserved_883; // offset: 883 (0x373) 2074 uint32_t reserved_884; // offset: 884 (0x374) 2075 uint32_t reserved_885; // offset: 885 (0x375) 2076 uint32_t reserved_886; // offset: 886 (0x376) 2077 uint32_t reserved_887; // offset: 887 (0x377) 2078 uint32_t reserved_888; // offset: 888 (0x378) 2079 uint32_t reserved_889; // offset: 889 (0x379) 2080 uint32_t reserved_890; // offset: 890 (0x37A) 2081 uint32_t reserved_891; // offset: 891 (0x37B) 2082 uint32_t reserved_892; // offset: 892 (0x37C) 2083 uint32_t reserved_893; // offset: 893 (0x37D) 2084 uint32_t reserved_894; // offset: 894 (0x37E) 2085 uint32_t reserved_895; // offset: 895 (0x37F) 2086 uint32_t reserved_896; // offset: 896 (0x380) 2087 uint32_t reserved_897; // offset: 897 (0x381) 2088 uint32_t reserved_898; // offset: 898 (0x382) 2089 uint32_t reserved_899; // offset: 899 (0x383) 2090 uint32_t reserved_900; // offset: 900 (0x384) 2091 uint32_t reserved_901; // offset: 901 (0x385) 2092 uint32_t reserved_902; // offset: 902 (0x386) 2093 uint32_t reserved_903; // offset: 903 (0x387) 2094 uint32_t reserved_904; // offset: 904 (0x388) 2095 uint32_t reserved_905; // offset: 905 (0x389) 2096 uint32_t reserved_906; // offset: 906 (0x38A) 2097 uint32_t reserved_907; // offset: 907 (0x38B) 2098 uint32_t reserved_908; // offset: 908 (0x38C) 2099 uint32_t reserved_909; // offset: 909 (0x38D) 2100 uint32_t reserved_910; // offset: 910 (0x38E) 2101 uint32_t reserved_911; // offset: 911 (0x38F) 2102 uint32_t reserved_912; // offset: 912 (0x390) 2103 uint32_t reserved_913; // offset: 913 (0x391) 2104 uint32_t reserved_914; // offset: 914 (0x392) 2105 uint32_t reserved_915; // offset: 915 (0x393) 2106 uint32_t reserved_916; // offset: 916 (0x394) 2107 uint32_t reserved_917; // offset: 917 (0x395) 2108 uint32_t reserved_918; // offset: 918 (0x396) 2109 uint32_t reserved_919; // offset: 919 (0x397) 2110 uint32_t reserved_920; // offset: 920 (0x398) 2111 uint32_t reserved_921; // offset: 921 (0x399) 2112 uint32_t reserved_922; // offset: 922 (0x39A) 2113 uint32_t reserved_923; // offset: 923 (0x39B) 2114 uint32_t reserved_924; // offset: 924 (0x39C) 2115 uint32_t reserved_925; // offset: 925 (0x39D) 2116 uint32_t reserved_926; // offset: 926 (0x39E) 2117 uint32_t reserved_927; // offset: 927 (0x39F) 2118 uint32_t reserved_928; // offset: 928 (0x3A0) 2119 uint32_t reserved_929; // offset: 929 (0x3A1) 2120 uint32_t reserved_930; // offset: 930 (0x3A2) 2121 uint32_t reserved_931; // offset: 931 (0x3A3) 2122 uint32_t reserved_932; // offset: 932 (0x3A4) 2123 uint32_t reserved_933; // offset: 933 (0x3A5) 2124 uint32_t reserved_934; // offset: 934 (0x3A6) 2125 uint32_t reserved_935; // offset: 935 (0x3A7) 2126 uint32_t reserved_936; // offset: 936 (0x3A8) 2127 uint32_t reserved_937; // offset: 937 (0x3A9) 2128 uint32_t reserved_938; // offset: 938 (0x3AA) 2129 uint32_t reserved_939; // offset: 939 (0x3AB) 2130 uint32_t reserved_940; // offset: 940 (0x3AC) 2131 uint32_t reserved_941; // offset: 941 (0x3AD) 2132 uint32_t reserved_942; // offset: 942 (0x3AE) 2133 uint32_t reserved_943; // offset: 943 (0x3AF) 2134 uint32_t reserved_944; // offset: 944 (0x3B0) 2135 uint32_t reserved_945; // offset: 945 (0x3B1) 2136 uint32_t reserved_946; // offset: 946 (0x3B2) 2137 uint32_t reserved_947; // offset: 947 (0x3B3) 2138 uint32_t reserved_948; // offset: 948 (0x3B4) 2139 uint32_t reserved_949; // offset: 949 (0x3B5) 2140 uint32_t reserved_950; // offset: 950 (0x3B6) 2141 uint32_t reserved_951; // offset: 951 (0x3B7) 2142 uint32_t reserved_952; // offset: 952 (0x3B8) 2143 uint32_t reserved_953; // offset: 953 (0x3B9) 2144 uint32_t reserved_954; // offset: 954 (0x3BA) 2145 uint32_t reserved_955; // offset: 955 (0x3BB) 2146 uint32_t reserved_956; // offset: 956 (0x3BC) 2147 uint32_t reserved_957; // offset: 957 (0x3BD) 2148 uint32_t reserved_958; // offset: 958 (0x3BE) 2149 uint32_t reserved_959; // offset: 959 (0x3BF) 2150 uint32_t reserved_960; // offset: 960 (0x3C0) 2151 uint32_t reserved_961; // offset: 961 (0x3C1) 2152 uint32_t reserved_962; // offset: 962 (0x3C2) 2153 uint32_t reserved_963; // offset: 963 (0x3C3) 2154 uint32_t reserved_964; // offset: 964 (0x3C4) 2155 uint32_t reserved_965; // offset: 965 (0x3C5) 2156 uint32_t reserved_966; // offset: 966 (0x3C6) 2157 uint32_t reserved_967; // offset: 967 (0x3C7) 2158 uint32_t reserved_968; // offset: 968 (0x3C8) 2159 uint32_t reserved_969; // offset: 969 (0x3C9) 2160 uint32_t reserved_970; // offset: 970 (0x3CA) 2161 uint32_t reserved_971; // offset: 971 (0x3CB) 2162 uint32_t reserved_972; // offset: 972 (0x3CC) 2163 uint32_t reserved_973; // offset: 973 (0x3CD) 2164 uint32_t reserved_974; // offset: 974 (0x3CE) 2165 uint32_t reserved_975; // offset: 975 (0x3CF) 2166 uint32_t reserved_976; // offset: 976 (0x3D0) 2167 uint32_t reserved_977; // offset: 977 (0x3D1) 2168 uint32_t reserved_978; // offset: 978 (0x3D2) 2169 uint32_t reserved_979; // offset: 979 (0x3D3) 2170 uint32_t reserved_980; // offset: 980 (0x3D4) 2171 uint32_t reserved_981; // offset: 981 (0x3D5) 2172 uint32_t reserved_982; // offset: 982 (0x3D6) 2173 uint32_t reserved_983; // offset: 983 (0x3D7) 2174 uint32_t reserved_984; // offset: 984 (0x3D8) 2175 uint32_t reserved_985; // offset: 985 (0x3D9) 2176 uint32_t reserved_986; // offset: 986 (0x3DA) 2177 uint32_t reserved_987; // offset: 987 (0x3DB) 2178 uint32_t reserved_988; // offset: 988 (0x3DC) 2179 uint32_t reserved_989; // offset: 989 (0x3DD) 2180 uint32_t reserved_990; // offset: 990 (0x3DE) 2181 uint32_t reserved_991; // offset: 991 (0x3DF) 2182 uint32_t reserved_992; // offset: 992 (0x3E0) 2183 uint32_t reserved_993; // offset: 993 (0x3E1) 2184 uint32_t reserved_994; // offset: 994 (0x3E2) 2185 uint32_t reserved_995; // offset: 995 (0x3E3) 2186 uint32_t reserved_996; // offset: 996 (0x3E4) 2187 uint32_t reserved_997; // offset: 997 (0x3E5) 2188 uint32_t reserved_998; // offset: 998 (0x3E6) 2189 uint32_t reserved_999; // offset: 999 (0x3E7) 2190 uint32_t reserved_1000; // offset: 1000 (0x3E8) 2191 uint32_t reserved_1001; // offset: 1001 (0x3E9) 2192 uint32_t reserved_1002; // offset: 1002 (0x3EA) 2193 uint32_t reserved_1003; // offset: 1003 (0x3EB) 2194 uint32_t reserved_1004; // offset: 1004 (0x3EC) 2195 uint32_t reserved_1005; // offset: 1005 (0x3ED) 2196 uint32_t reserved_1006; // offset: 1006 (0x3EE) 2197 uint32_t reserved_1007; // offset: 1007 (0x3EF) 2198 uint32_t reserved_1008; // offset: 1008 (0x3F0) 2199 uint32_t reserved_1009; // offset: 1009 (0x3F1) 2200 uint32_t reserved_1010; // offset: 1010 (0x3F2) 2201 uint32_t reserved_1011; // offset: 1011 (0x3F3) 2202 uint32_t reserved_1012; // offset: 1012 (0x3F4) 2203 uint32_t reserved_1013; // offset: 1013 (0x3F5) 2204 uint32_t reserved_1014; // offset: 1014 (0x3F6) 2205 uint32_t reserved_1015; // offset: 1015 (0x3F7) 2206 uint32_t reserved_1016; // offset: 1016 (0x3F8) 2207 uint32_t reserved_1017; // offset: 1017 (0x3F9) 2208 uint32_t reserved_1018; // offset: 1018 (0x3FA) 2209 uint32_t reserved_1019; // offset: 1019 (0x3FB) 2210 uint32_t reserved_1020; // offset: 1020 (0x3FC) 2211 uint32_t reserved_1021; // offset: 1021 (0x3FD) 2212 uint32_t reserved_1022; // offset: 1022 (0x3FE) 2213 uint32_t reserved_1023; // offset: 1023 (0x3FF) 2214 }; 2215 2216 struct v12_1_mes_mqd { 2217 uint32_t header; // offset: 0 (0x0) 2218 uint32_t compute_dispatch_initiator; // offset: 1 (0x1) 2219 uint32_t compute_dim_x; // offset: 2 (0x2) 2220 uint32_t compute_dim_y; // offset: 3 (0x3) 2221 uint32_t compute_dim_z; // offset: 4 (0x4) 2222 uint32_t compute_start_x; // offset: 5 (0x5) 2223 uint32_t compute_start_y; // offset: 6 (0x6) 2224 uint32_t compute_start_z; // offset: 7 (0x7) 2225 uint32_t compute_num_thread_x; // offset: 8 (0x8) 2226 uint32_t compute_num_thread_y; // offset: 9 (0x9) 2227 uint32_t compute_num_thread_z; // offset: 10 (0xA) 2228 uint32_t compute_pipelinestat_enable; // offset: 11 (0xB) 2229 uint32_t compute_perfcount_enable; // offset: 12 (0xC) 2230 uint32_t compute_pgm_lo; // offset: 13 (0xD) 2231 uint32_t compute_pgm_hi; // offset: 14 (0xE) 2232 uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF) 2233 uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10) 2234 uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11) 2235 uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12) 2236 uint32_t compute_pgm_rsrc1; // offset: 19 (0x13) 2237 uint32_t compute_pgm_rsrc2; // offset: 20 (0x14) 2238 uint32_t compute_vmid; // offset: 21 (0x15) 2239 uint32_t compute_resource_limits; // offset: 22 (0x16) 2240 uint32_t compute_tmpring_size; // offset: 23 (0x17) 2241 uint32_t compute_restart_x; // offset: 24 (0x18) 2242 uint32_t compute_restart_y; // offset: 25 (0x19) 2243 uint32_t compute_restart_z; // offset: 26 (0x1A) 2244 uint32_t compute_thread_trace_enable; // offset: 27 (0x1B) 2245 uint32_t compute_misc_reserved; // offset: 28 (0x1C) 2246 uint32_t compute_dispatch_id; // offset: 29 (0x1D) 2247 uint32_t compute_threadgroup_id; // offset: 30 (0x1E) 2248 uint32_t compute_req_ctrl; // offset: 31 (0x1F) 2249 uint32_t compute_user_accum_0; // offset: 32 (0x20) 2250 uint32_t compute_user_accum_1; // offset: 33 (0x21) 2251 uint32_t compute_user_accum_2; // offset: 34 (0x22) 2252 uint32_t compute_user_accum_3; // offset: 35 (0x23) 2253 uint32_t compute_pgm_rsrc3; // offset: 36 (0x24) 2254 uint32_t compute_ddid_index; // offset: 37 (0x25) 2255 uint32_t compute_shader_chksum; // offset: 38 (0x26) 2256 uint32_t compute_dispatch_interleave; // offset: 39 (0x27) 2257 uint32_t compute_current_logical_xcc_id; // offset: 40 (0x28) 2258 uint32_t compute_restart_cg_tg_id; // offset: 41 (0x29) 2259 uint32_t compute_tg_chunk_size; // offset: 42 (0x2A) 2260 uint32_t compute_restore_tg_chunk_size; // offset: 43 (0x2B) 2261 uint32_t compute_start_total_lo; // offset: 44 (0x2C) 2262 uint32_t compute_start_total_hi; // offset: 45 (0x2D) 2263 uint32_t compute_prescaled_dim_x; // offset: 46 (0x2E) 2264 uint32_t compute_prescaled_dim_y; // offset: 47 (0x2F) 2265 uint32_t compute_prescaled_dim_z; // offset: 48 (0x30) 2266 uint32_t compute_static_thread_mgmt_se0; // offset: 49 (0x31) 2267 uint32_t compute_static_thread_mgmt_se1; // offset: 50 (0x32) 2268 uint32_t compute_static_thread_mgmt_se2; // offset: 51 (0x33) 2269 uint32_t compute_static_thread_mgmt_se3; // offset: 52 (0x34) 2270 uint32_t compute_static_thread_mgmt_se4; // offset: 53 (0x35) 2271 uint32_t compute_static_thread_mgmt_se5; // offset: 54 (0x36) 2272 uint32_t compute_static_thread_mgmt_se6; // offset: 55 (0x37) 2273 uint32_t compute_static_thread_mgmt_se7; // offset: 56 (0x38) 2274 uint32_t compute_static_thread_mgmt_se8; // offset: 57 (0x39) 2275 uint32_t reserved_58; // offset: 58 (0x3A) 2276 uint32_t reserved_59; // offset: 59 (0x3B) 2277 uint32_t reserved_60; // offset: 60 (0x3C) 2278 uint32_t reserved_61; // offset: 61 (0x3D) 2279 uint32_t reserved_62; // offset: 62 (0x3E) 2280 uint32_t reserved_63; // offset: 63 (0x3F) 2281 uint32_t reserved_64; // offset: 64 (0x40) 2282 uint32_t compute_user_data_0; // offset: 65 (0x41) 2283 uint32_t compute_user_data_1; // offset: 66 (0x42) 2284 uint32_t compute_user_data_2; // offset: 67 (0x43) 2285 uint32_t compute_user_data_3; // offset: 68 (0x44) 2286 uint32_t compute_user_data_4; // offset: 69 (0x45) 2287 uint32_t compute_user_data_5; // offset: 70 (0x46) 2288 uint32_t compute_user_data_6; // offset: 71 (0x47) 2289 uint32_t compute_user_data_7; // offset: 72 (0x48) 2290 uint32_t compute_user_data_8; // offset: 73 (0x49) 2291 uint32_t compute_user_data_9; // offset: 74 (0x4A) 2292 uint32_t compute_user_data_10; // offset: 75 (0x4B) 2293 uint32_t compute_user_data_11; // offset: 76 (0x4C) 2294 uint32_t compute_user_data_12; // offset: 77 (0x4D) 2295 uint32_t compute_user_data_13; // offset: 78 (0x4E) 2296 uint32_t compute_user_data_14; // offset: 79 (0x4F) 2297 uint32_t compute_user_data_15; // offset: 80 (0x50) 2298 uint32_t compute_user_data_16; // offset: 81 (0x51) 2299 uint32_t compute_user_data_17; // offset: 82 (0x52) 2300 uint32_t compute_user_data_18; // offset: 83 (0x53) 2301 uint32_t compute_user_data_19; // offset: 84 (0x54) 2302 uint32_t compute_user_data_20; // offset: 85 (0x55) 2303 uint32_t compute_user_data_21; // offset: 86 (0x56) 2304 uint32_t compute_user_data_22; // offset: 87 (0x57) 2305 uint32_t compute_user_data_23; // offset: 88 (0x58) 2306 uint32_t compute_user_data_24; // offset: 89 (0x59) 2307 uint32_t compute_user_data_25; // offset: 90 (0x5A) 2308 uint32_t compute_user_data_26; // offset: 91 (0x5B) 2309 uint32_t compute_user_data_27; // offset: 92 (0x5C) 2310 uint32_t compute_user_data_28; // offset: 93 (0x5D) 2311 uint32_t compute_user_data_29; // offset: 94 (0x5E) 2312 uint32_t compute_user_data_30; // offset: 95 (0x5F) 2313 uint32_t compute_user_data_31; // offset: 96 (0x60) 2314 uint32_t reserved_97; // offset: 97 (0x61) 2315 uint32_t reserved_98; // offset: 98 (0x62) 2316 uint32_t reserved_99; // offset: 99 (0x63) 2317 uint32_t reserved_100; // offset: 100 (0x64) 2318 uint32_t reserved_101; // offset: 101 (0x65) 2319 uint32_t reserved_102; // offset: 102 (0x66) 2320 uint32_t reserved_103; // offset: 103 (0x67) 2321 uint32_t reserved_104; // offset: 104 (0x68) 2322 uint32_t reserved_105; // offset: 105 (0x69) 2323 uint32_t reserved_106; // offset: 106 (0x6A) 2324 uint32_t reserved_107; // offset: 107 (0x6B) 2325 uint32_t reserved_108; // offset: 108 (0x6C) 2326 uint32_t reserved_109; // offset: 109 (0x6D) 2327 uint32_t compute_relaunch; // offset: 110 (0x6E) 2328 uint32_t compute_wave_restore_addr_lo; // offset: 111 (0x6F) 2329 uint32_t compute_wave_restore_addr_hi; // offset: 112 (0x70) 2330 uint32_t compute_relaunch2; // offset: 113 (0x71) 2331 uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72) 2332 uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73) 2333 uint32_t cp_packet_id_lo; // offset: 116 (0x74) 2334 uint32_t cp_packet_id_hi; // offset: 117 (0x75) 2335 uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76) 2336 uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77) 2337 uint32_t reserved_120; // offset: 120 (0x78) 2338 uint32_t reserved_121; // offset: 121 (0x79) 2339 uint32_t reserved_122; // offset: 122 (0x7A) 2340 uint32_t reserved_123; // offset: 123 (0x7B) 2341 uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C) 2342 uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D) 2343 uint32_t reserved_126; // offset: 126 (0x7E) 2344 uint32_t reserved_127; // offset: 127 (0x7F) 2345 uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80) 2346 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) 2347 uint32_t cp_hqd_active; // offset: 130 (0x82) 2348 uint32_t cp_hqd_vmid; // offset: 131 (0x83) 2349 uint32_t cp_hqd_persistent_state; // offset: 132 (0x84) 2350 uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85) 2351 uint32_t cp_hqd_queue_priority; // offset: 134 (0x86) 2352 uint32_t cp_hqd_quantum; // offset: 135 (0x87) 2353 uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) 2354 uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) 2355 uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A) 2356 uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B) 2357 uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C) 2358 uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D) 2359 uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) 2360 uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F) 2361 uint32_t reserved_144; // offset: 144 (0x90) 2362 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) 2363 uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92) 2364 uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93) 2365 uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94) 2366 uint32_t cp_hqd_ib_control; // offset: 149 (0x95) 2367 uint32_t cp_hqd_iq_timer; // offset: 150 (0x96) 2368 uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97) 2369 uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98) 2370 uint32_t cp_hqd_dma_offload; // offset: 153 (0x99) 2371 uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A) 2372 uint32_t cp_hqd_msg_type; // offset: 155 (0x9B) 2373 uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C) 2374 uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D) 2375 uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E) 2376 uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F) 2377 uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0) 2378 uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1) 2379 uint32_t cp_mqd_control; // offset: 162 (0xA2) 2380 uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3) 2381 uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4) 2382 uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5) 2383 uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6) 2384 uint32_t cp_hqd_eop_control; // offset: 167 (0xA7) 2385 uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8) 2386 uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9) 2387 uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA) 2388 uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB) 2389 uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC) 2390 uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD) 2391 uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE) 2392 uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF) 2393 uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0) 2394 uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1) 2395 uint32_t reserved_178; // offset: 178 (0xB2) 2396 uint32_t cp_hqd_error; // offset: 179 (0xB3) 2397 uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4) 2398 uint32_t cp_hqd_aql_control; // offset: 181 (0xB5) 2399 uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6) 2400 uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7) 2401 uint32_t cp_hqd_gfx_control; // offset: 184 (0xB8) 2402 uint32_t cp_hqd_suspend_cntl_stack_dw_cnt; // offset: 185 (0xB9) 2403 uint32_t cp_hqd_suspend_wg_state_offset; // offset: 186 (0xBA) 2404 uint32_t cp_hqd_ddid_rptr; // offset: 187 (0xBB) 2405 uint32_t cp_hqd_ddid_wptr; // offset: 188 (0xBC) 2406 uint32_t cp_hqd_ddid_inflight_count; // offset: 189 (0xBD) 2407 uint32_t cp_hqd_ddid_delta_rpt_count; // offset: 190 (0xBE) 2408 uint32_t cp_hqd_dequeue_status; // offset: 191 (0xBF) 2409 uint32_t cp_hqd_aql_control_1; // offset: 192 (0xC0) 2410 uint32_t cp_hqd_aql_dispatch_id; // offset: 193 (0xC1) 2411 uint32_t cp_hqd_aql_dispatch_id_hi; // offset: 194 (0xC2) 2412 uint32_t cp_hqd_kd_base; // offset: 195 (0xC3) 2413 uint32_t cp_hqd_kd_base_hi; // offset: 196 (0xC4) 2414 uint32_t cp_hqd_kd_cntl; // offset: 197 (0xC5) 2415 uint32_t reserved_198; // offset: 198 (0xC6) 2416 uint32_t reserved_199; // offset: 199 (0xC7) 2417 uint32_t reserved_200; // offset: 200 (0xC8) 2418 uint32_t reserved_201; // offset: 201 (0xC9) 2419 uint32_t reserved_202; // offset: 202 (0xCA) 2420 uint32_t reserved_203; // offset: 203 (0xCB) 2421 uint32_t reserved_204; // offset: 204 (0xCC) 2422 uint32_t reserved_205; // offset: 205 (0xCD) 2423 uint32_t reserved_206; // offset: 206 (0xCE) 2424 uint32_t reserved_207; // offset: 207 (0xCF) 2425 uint32_t reserved_208; // offset: 208 (0xD0) 2426 uint32_t reserved_209; // offset: 209 (0xD1) 2427 uint32_t reserved_210; // offset: 210 (0xD2) 2428 uint32_t reserved_211; // offset: 211 (0xD3) 2429 uint32_t reserved_212; // offset: 212 (0xD4) 2430 uint32_t reserved_213; // offset: 213 (0xD5) 2431 uint32_t reserved_214; // offset: 214 (0xD6) 2432 uint32_t reserved_215; // offset: 215 (0xD7) 2433 uint32_t reserved_216; // offset: 216 (0xD8) 2434 uint32_t reserved_217; // offset: 217 (0xD9) 2435 uint32_t reserved_218; // offset: 218 (0xDA) 2436 uint32_t reserved_219; // offset: 219 (0xDB) 2437 uint32_t reserved_220; // offset: 220 (0xDC) 2438 uint32_t reserved_221; // offset: 221 (0xDD) 2439 uint32_t reserved_222; // offset: 222 (0xDE) 2440 uint32_t reserved_223; // offset: 223 (0xDF) 2441 uint32_t reserved_224; // offset: 224 (0xE0) 2442 uint32_t pm4_target_xcc_in_xcp; // offset: 225 (0xE1) 2443 uint32_t cp_mqd_stride_size; // offset: 226 (0xE2) 2444 uint32_t xcc_sync_counter; // offset: 227 (0xE3) 2445 uint32_t set_resources_header; // offset: 228 (0xE4) 2446 uint32_t set_resources_dw1; // offset: 229 (0xE5) 2447 uint32_t set_resources_dw2; // offset: 230 (0xE6) 2448 uint32_t set_resources_dw3; // offset: 231 (0xE7) 2449 uint32_t set_resources_dw4; // offset: 232 (0xE8) 2450 uint32_t set_resources_dw5; // offset: 233 (0xE9) 2451 uint32_t set_resources_dw6; // offset: 234 (0xEA) 2452 uint32_t set_resources_dw7; // offset: 235 (0xEB) 2453 uint32_t reserved_236; // offset: 236 (0xEC) 2454 uint32_t reserved_237; // offset: 237 (0xED) 2455 uint32_t reserved_238; // offset: 238 (0xEE) 2456 uint32_t reserved_239; // offset: 239 (0xEF) 2457 uint32_t reserved_240; // offset: 240 (0xF0) 2458 uint32_t reserved_241; // offset: 241 (0xF1) 2459 uint32_t reserved_242; // offset: 242 (0xF2) 2460 uint32_t reserved_243; // offset: 243 (0xF3) 2461 uint32_t reserved_244; // offset: 244 (0xF4) 2462 uint32_t reserved_245; // offset: 245 (0xF5) 2463 uint32_t reserved_246; // offset: 246 (0xF6) 2464 uint32_t reserved_247; // offset: 247 (0xF7) 2465 uint32_t reserved_248; // offset: 248 (0xF8) 2466 uint32_t reserved_249; // offset: 249 (0xF9) 2467 uint32_t reserved_250; // offset: 250 (0xFA) 2468 uint32_t reserved_251; // offset: 251 (0xFB) 2469 uint32_t reserved_252; // offset: 252 (0xFC) 2470 uint32_t reserved_253; // offset: 253 (0xFD) 2471 uint32_t reserved_254; // offset: 254 (0xFE) 2472 uint32_t reserved_255; // offset: 255 (0xFF) 2473 uint32_t control_buf_addr_lo; // offset: 256 (0x100) 2474 uint32_t control_buf_addr_hi; // offset: 257 (0x101) 2475 uint32_t control_buf_wptr_lo; // offset: 258 (0x102) 2476 uint32_t control_buf_wptr_hi; // offset: 259 (0x103) 2477 uint32_t control_buf_dptr_lo; // offset: 260 (0x104) 2478 uint32_t control_buf_dptr_hi; // offset: 261 (0x105) 2479 uint32_t draw_ring_addr_lo; // offset: 262 (0x106) 2480 uint32_t draw_ring_addr_hi; // offset: 263 (0x107) 2481 uint32_t control_buf_num_entries; // offset: 264 (0x108) 2482 uint32_t reserved_265; // offset: 265 (0x109) 2483 uint32_t reserved_266; // offset: 266 (0x10A) 2484 uint32_t reserved_267; // offset: 267 (0x10B) 2485 uint32_t reserved_268; // offset: 268 (0x10C) 2486 uint32_t reserved_269; // offset: 269 (0x10D) 2487 uint32_t reserved_270; // offset: 270 (0x10E) 2488 uint32_t reserved_271; // offset: 271 (0x10F) 2489 uint32_t dfwx_flags; // offset: 272 (0x110) 2490 uint32_t dfwx_slot; // offset: 273 (0x111) 2491 uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112) 2492 uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113) 2493 uint32_t dfwx_queue_connect_addr_lo; // offset: 276 (0x114) 2494 uint32_t dfwx_queue_connect_addr_hi; // offset: 277 (0x115) 2495 uint32_t reserved_278; // offset: 278 (0x116) 2496 uint32_t reserved_279; // offset: 279 (0x117) 2497 uint32_t reserved_280; // offset: 280 (0x118) 2498 uint32_t reserved_281; // offset: 281 (0x119) 2499 uint32_t reserved_282; // offset: 282 (0x11A) 2500 uint32_t reserved_283; // offset: 283 (0x11B) 2501 uint32_t reserved_284; // offset: 284 (0x11C) 2502 uint32_t reserved_285; // offset: 285 (0x11D) 2503 uint32_t reserved_286; // offset: 286 (0x11E) 2504 uint32_t reserved_287; // offset: 287 (0x11F) 2505 uint32_t cp_mqd_query_time_lo; // offset: 288 (0x120) 2506 uint32_t cp_mqd_query_time_hi; // offset: 289 (0x121) 2507 uint32_t cp_mqd_connect_start_time_lo; // offset: 290 (0x122) 2508 uint32_t cp_mqd_connect_start_time_hi; // offset: 291 (0x123) 2509 uint32_t cp_mqd_connect_end_time_lo; // offset: 292 (0x124) 2510 uint32_t cp_mqd_connect_end_time_hi; // offset: 293 (0x125) 2511 uint32_t cp_mqd_connect_end_wf_count; // offset: 294 (0x126) 2512 uint32_t cp_mqd_connect_end_pq_rptr; // offset: 295 (0x127) 2513 uint32_t cp_mqd_connect_end_pq_wptr; // offset: 296 (0x128) 2514 uint32_t cp_mqd_connect_end_ib_rptr; // offset: 297 (0x129) 2515 uint32_t cp_mqd_readindex_lo; // offset: 298 (0x12A) 2516 uint32_t cp_mqd_readindex_hi; // offset: 299 (0x12B) 2517 uint32_t cp_mqd_save_start_time_lo; // offset: 300 (0x12C) 2518 uint32_t cp_mqd_save_start_time_hi; // offset: 301 (0x12D) 2519 uint32_t cp_mqd_save_end_time_lo; // offset: 302 (0x12E) 2520 uint32_t cp_mqd_save_end_time_hi; // offset: 303 (0x12F) 2521 uint32_t cp_mqd_restore_start_time_lo; // offset: 304 (0x130) 2522 uint32_t cp_mqd_restore_start_time_hi; // offset: 305 (0x131) 2523 uint32_t cp_mqd_restore_end_time_lo; // offset: 306 (0x132) 2524 uint32_t cp_mqd_restore_end_time_hi; // offset: 307 (0x133) 2525 uint32_t disable_queue; // offset: 308 (0x134) 2526 uint32_t reserved_309; // offset: 309 (0x135) 2527 uint32_t reserved_310; // offset: 310 (0x136) 2528 uint32_t reserved_311; // offset: 311 (0x137) 2529 uint32_t reserved_312; // offset: 312 (0x138) 2530 uint32_t reserved_313; // offset: 313 (0x139) 2531 uint32_t reserved_314; // offset: 314 (0x13A) 2532 uint32_t reserved_315; // offset: 315 (0x13B) 2533 uint32_t reserved_316; // offset: 316 (0x13C) 2534 uint32_t reserved_317; // offset: 317 (0x13D) 2535 uint32_t tg_counter_id; // offset: 318 (0x13E) 2536 uint32_t cp_compute_csinvoc_count_lo; // offset: 319 (0x13F) 2537 uint32_t cp_compute_csinvoc_count_hi; // offset: 320 (0x140) 2538 uint32_t reserved_321; // offset: 321 (0x141) 2539 uint32_t reserved_322; // offset: 322 (0x142) 2540 uint32_t reserved_323; // offset: 323 (0x143) 2541 uint32_t reserved_324; // offset: 324 (0x144) 2542 uint32_t reserved_325; // offset: 325 (0x145) 2543 uint32_t reserved_326; // offset: 326 (0x146) 2544 uint32_t reserved_327; // offset: 327 (0x147) 2545 uint32_t reserved_328; // offset: 328 (0x148) 2546 uint32_t reserved_329; // offset: 329 (0x149) 2547 uint32_t reserved_330; // offset: 330 (0x14A) 2548 uint32_t reserved_331; // offset: 331 (0x14B) 2549 uint32_t reserved_332; // offset: 332 (0x14C) 2550 uint32_t reserved_333; // offset: 333 (0x14D) 2551 uint32_t reserved_334; // offset: 334 (0x14E) 2552 uint32_t reserved_335; // offset: 335 (0x14F) 2553 uint32_t reserved_336; // offset: 336 (0x150) 2554 uint32_t reserved_337; // offset: 337 (0x151) 2555 uint32_t reserved_338; // offset: 338 (0x152) 2556 uint32_t reserved_339; // offset: 339 (0x153) 2557 uint32_t reserved_340; // offset: 340 (0x154) 2558 uint32_t reserved_341; // offset: 341 (0x155) 2559 uint32_t reserved_342; // offset: 342 (0x156) 2560 uint32_t reserved_343; // offset: 343 (0x157) 2561 uint32_t reserved_344; // offset: 344 (0x158) 2562 uint32_t reserved_345; // offset: 345 (0x159) 2563 uint32_t reserved_346; // offset: 346 (0x15A) 2564 uint32_t reserved_347; // offset: 347 (0x15B) 2565 uint32_t reserved_348; // offset: 348 (0x15C) 2566 uint32_t reserved_349; // offset: 349 (0x15D) 2567 uint32_t reserved_350; // offset: 350 (0x15E) 2568 uint32_t reserved_351; // offset: 351 (0x15F) 2569 uint32_t reserved_352; // offset: 352 (0x160) 2570 uint32_t reserved_353; // offset: 353 (0x161) 2571 uint32_t reserved_354; // offset: 354 (0x162) 2572 uint32_t reserved_355; // offset: 355 (0x163) 2573 uint32_t reserved_356; // offset: 356 (0x164) 2574 uint32_t reserved_357; // offset: 357 (0x165) 2575 uint32_t reserved_358; // offset: 358 (0x166) 2576 uint32_t reserved_359; // offset: 359 (0x167) 2577 uint32_t reserved_360; // offset: 360 (0x168) 2578 uint32_t reserved_361; // offset: 361 (0x169) 2579 uint32_t reserved_362; // offset: 362 (0x16A) 2580 uint32_t reserved_363; // offset: 363 (0x16B) 2581 uint32_t reserved_364; // offset: 364 (0x16C) 2582 uint32_t reserved_365; // offset: 365 (0x16D) 2583 uint32_t reserved_366; // offset: 366 (0x16E) 2584 uint32_t reserved_367; // offset: 367 (0x16F) 2585 uint32_t reserved_368; // offset: 368 (0x170) 2586 uint32_t reserved_369; // offset: 369 (0x171) 2587 uint32_t reserved_370; // offset: 370 (0x172) 2588 uint32_t reserved_371; // offset: 371 (0x173) 2589 uint32_t reserved_372; // offset: 372 (0x174) 2590 uint32_t reserved_373; // offset: 373 (0x175) 2591 uint32_t reserved_374; // offset: 374 (0x176) 2592 uint32_t reserved_375; // offset: 375 (0x177) 2593 uint32_t reserved_376; // offset: 376 (0x178) 2594 uint32_t reserved_377; // offset: 377 (0x179) 2595 uint32_t reserved_378; // offset: 378 (0x17A) 2596 uint32_t reserved_379; // offset: 379 (0x17B) 2597 uint32_t reserved_380; // offset: 380 (0x17C) 2598 uint32_t reserved_381; // offset: 381 (0x17D) 2599 uint32_t reserved_382; // offset: 382 (0x17E) 2600 uint32_t reserved_383; // offset: 383 (0x17F) 2601 uint32_t iqtimer_pkt_header; // offset: 384 (0x180) 2602 uint32_t iqtimer_pkt_dw0; // offset: 385 (0x181) 2603 uint32_t iqtimer_pkt_dw1; // offset: 386 (0x182) 2604 uint32_t iqtimer_pkt_dw2; // offset: 387 (0x183) 2605 uint32_t iqtimer_pkt_dw3; // offset: 388 (0x184) 2606 uint32_t iqtimer_pkt_dw4; // offset: 389 (0x185) 2607 uint32_t iqtimer_pkt_dw5; // offset: 390 (0x186) 2608 uint32_t iqtimer_pkt_dw6; // offset: 391 (0x187) 2609 uint32_t iqtimer_pkt_dw7; // offset: 392 (0x188) 2610 uint32_t iqtimer_pkt_dw8; // offset: 393 (0x189) 2611 uint32_t iqtimer_pkt_dw9; // offset: 394 (0x18A) 2612 uint32_t iqtimer_pkt_dw10; // offset: 395 (0x18B) 2613 uint32_t iqtimer_pkt_dw11; // offset: 396 (0x18C) 2614 uint32_t iqtimer_pkt_dw12; // offset: 397 (0x18D) 2615 uint32_t iqtimer_pkt_dw13; // offset: 398 (0x18E) 2616 uint32_t iqtimer_pkt_dw14; // offset: 399 (0x18F) 2617 uint32_t iqtimer_pkt_dw15; // offset: 400 (0x190) 2618 uint32_t iqtimer_pkt_dw16; // offset: 401 (0x191) 2619 uint32_t iqtimer_pkt_dw17; // offset: 402 (0x192) 2620 uint32_t iqtimer_pkt_dw18; // offset: 403 (0x193) 2621 uint32_t iqtimer_pkt_dw19; // offset: 404 (0x194) 2622 uint32_t iqtimer_pkt_dw20; // offset: 405 (0x195) 2623 uint32_t iqtimer_pkt_dw21; // offset: 406 (0x196) 2624 uint32_t iqtimer_pkt_dw22; // offset: 407 (0x197) 2625 uint32_t iqtimer_pkt_dw23; // offset: 408 (0x198) 2626 uint32_t iqtimer_pkt_dw24; // offset: 409 (0x199) 2627 uint32_t iqtimer_pkt_dw25; // offset: 410 (0x19A) 2628 uint32_t iqtimer_pkt_dw26; // offset: 411 (0x19B) 2629 uint32_t iqtimer_pkt_dw27; // offset: 412 (0x19C) 2630 uint32_t iqtimer_pkt_dw28; // offset: 413 (0x19D) 2631 uint32_t iqtimer_pkt_dw29; // offset: 414 (0x19E) 2632 uint32_t iqtimer_pkt_dw30; // offset: 415 (0x19F) 2633 uint32_t iqtimer_pkt_dw31; // offset: 416 (0x1A0) 2634 uint32_t reserved_417; // offset: 417 (0x1A1) 2635 uint32_t reserved_418; // offset: 418 (0x1A2) 2636 uint32_t reserved_419; // offset: 419 (0x1A3) 2637 uint32_t reserved_420; // offset: 420 (0x1A4) 2638 uint32_t reserved_421; // offset: 421 (0x1A5) 2639 uint32_t reserved_422; // offset: 422 (0x1A6) 2640 uint32_t reserved_423; // offset: 423 (0x1A7) 2641 uint32_t reserved_424; // offset: 424 (0x1A8) 2642 uint32_t reserved_425; // offset: 425 (0x1A9) 2643 uint32_t reserved_426; // offset: 426 (0x1AA) 2644 uint32_t reserved_427; // offset: 427 (0x1AB) 2645 uint32_t reserved_428; // offset: 428 (0x1AC) 2646 uint32_t reserved_429; // offset: 429 (0x1AD) 2647 uint32_t reserved_430; // offset: 430 (0x1AE) 2648 uint32_t reserved_431; // offset: 431 (0x1AF) 2649 uint32_t reserved_432; // offset: 432 (0x1B0) 2650 uint32_t reserved_433; // offset: 433 (0x1B1) 2651 uint32_t reserved_434; // offset: 434 (0x1B2) 2652 uint32_t reserved_435; // offset: 435 (0x1B3) 2653 uint32_t reserved_436; // offset: 436 (0x1B4) 2654 uint32_t reserved_437; // offset: 437 (0x1B5) 2655 uint32_t reserved_438; // offset: 438 (0x1B6) 2656 uint32_t reserved_439; // offset: 439 (0x1B7) 2657 uint32_t reserved_440; // offset: 440 (0x1B8) 2658 uint32_t reserved_441; // offset: 441 (0x1B9) 2659 uint32_t reserved_442; // offset: 442 (0x1BA) 2660 uint32_t reserved_443; // offset: 443 (0x1BB) 2661 uint32_t reserved_444; // offset: 444 (0x1BC) 2662 uint32_t reserved_445; // offset: 445 (0x1BD) 2663 uint32_t reserved_446; // offset: 446 (0x1BE) 2664 uint32_t reserved_447; // offset: 447 (0x1BF) 2665 uint32_t reserved_448; // offset: 448 (0x1C0) 2666 uint32_t reserved_449; // offset: 449 (0x1C1) 2667 uint32_t reserved_450; // offset: 450 (0x1C2) 2668 uint32_t reserved_451; // offset: 451 (0x1C3) 2669 uint32_t reserved_452; // offset: 452 (0x1C4) 2670 uint32_t reserved_453; // offset: 453 (0x1C5) 2671 uint32_t reserved_454; // offset: 454 (0x1C6) 2672 uint32_t reserved_455; // offset: 455 (0x1C7) 2673 uint32_t reserved_456; // offset: 456 (0x1C8) 2674 uint32_t reserved_457; // offset: 457 (0x1C9) 2675 uint32_t reserved_458; // offset: 458 (0x1CA) 2676 uint32_t reserved_459; // offset: 459 (0x1CB) 2677 uint32_t reserved_460; // offset: 460 (0x1CC) 2678 uint32_t reserved_461; // offset: 461 (0x1CD) 2679 uint32_t reserved_462; // offset: 462 (0x1CE) 2680 uint32_t reserved_463; // offset: 463 (0x1CF) 2681 uint32_t reserved_464; // offset: 464 (0x1D0) 2682 uint32_t reserved_465; // offset: 465 (0x1D1) 2683 uint32_t reserved_466; // offset: 466 (0x1D2) 2684 uint32_t reserved_467; // offset: 467 (0x1D3) 2685 uint32_t reserved_468; // offset: 468 (0x1D4) 2686 uint32_t reserved_469; // offset: 469 (0x1D5) 2687 uint32_t reserved_470; // offset: 470 (0x1D6) 2688 uint32_t reserved_471; // offset: 471 (0x1D7) 2689 uint32_t reserved_472; // offset: 472 (0x1D8) 2690 uint32_t reserved_473; // offset: 473 (0x1D9) 2691 uint32_t reserved_474; // offset: 474 (0x1DA) 2692 uint32_t reserved_475; // offset: 475 (0x1DB) 2693 uint32_t reserved_476; // offset: 476 (0x1DC) 2694 uint32_t reserved_477; // offset: 477 (0x1DD) 2695 uint32_t reserved_478; // offset: 478 (0x1DE) 2696 uint32_t reserved_479; // offset: 479 (0x1DF) 2697 uint32_t reserved_480; // offset: 480 (0x1E0) 2698 uint32_t reserved_481; // offset: 481 (0x1E1) 2699 uint32_t reserved_482; // offset: 482 (0x1E2) 2700 uint32_t reserved_483; // offset: 483 (0x1E3) 2701 uint32_t reserved_484; // offset: 484 (0x1E4) 2702 uint32_t reserved_485; // offset: 485 (0x1E5) 2703 uint32_t reserved_486; // offset: 486 (0x1E6) 2704 uint32_t reserved_487; // offset: 487 (0x1E7) 2705 uint32_t reserved_488; // offset: 488 (0x1E8) 2706 uint32_t reserved_489; // offset: 489 (0x1E9) 2707 uint32_t reserved_490; // offset: 490 (0x1EA) 2708 uint32_t reserved_491; // offset: 491 (0x1EB) 2709 uint32_t reserved_492; // offset: 492 (0x1EC) 2710 uint32_t reserved_493; // offset: 493 (0x1ED) 2711 uint32_t reserved_494; // offset: 494 (0x1EE) 2712 uint32_t reserved_495; // offset: 495 (0x1EF) 2713 uint32_t reserved_496; // offset: 496 (0x1F0) 2714 uint32_t reserved_497; // offset: 497 (0x1F1) 2715 uint32_t reserved_498; // offset: 498 (0x1F2) 2716 uint32_t reserved_499; // offset: 499 (0x1F3) 2717 uint32_t reserved_500; // offset: 500 (0x1F4) 2718 uint32_t reserved_501; // offset: 501 (0x1F5) 2719 uint32_t reserved_502; // offset: 502 (0x1F6) 2720 uint32_t reserved_503; // offset: 503 (0x1F7) 2721 uint32_t reserved_504; // offset: 504 (0x1F8) 2722 uint32_t reserved_505; // offset: 505 (0x1F9) 2723 uint32_t reserved_506; // offset: 506 (0x1FA) 2724 uint32_t reserved_507; // offset: 507 (0x1FB) 2725 uint32_t reserved_508; // offset: 508 (0x1FC) 2726 uint32_t reserved_509; // offset: 509 (0x1FD) 2727 uint32_t reserved_510; // offset: 510 (0x1FE) 2728 uint32_t reserved_511; // offset: 511 (0x1FF) 2729 uint32_t reserved_512; // offset: 512 (0x200) 2730 uint32_t reserved_513; // offset: 513 (0x201) 2731 uint32_t reserved_514; // offset: 514 (0x202) 2732 uint32_t reserved_515; // offset: 515 (0x203) 2733 uint32_t reserved_516; // offset: 516 (0x204) 2734 uint32_t reserved_517; // offset: 517 (0x205) 2735 uint32_t reserved_518; // offset: 518 (0x206) 2736 uint32_t reserved_519; // offset: 519 (0x207) 2737 uint32_t reserved_520; // offset: 520 (0x208) 2738 uint32_t reserved_521; // offset: 521 (0x209) 2739 uint32_t reserved_522; // offset: 522 (0x20A) 2740 uint32_t reserved_523; // offset: 523 (0x20B) 2741 uint32_t reserved_524; // offset: 524 (0x20C) 2742 uint32_t reserved_525; // offset: 525 (0x20D) 2743 uint32_t reserved_526; // offset: 526 (0x20E) 2744 uint32_t reserved_527; // offset: 527 (0x20F) 2745 uint32_t reserved_528; // offset: 528 (0x210) 2746 uint32_t reserved_529; // offset: 529 (0x211) 2747 uint32_t reserved_530; // offset: 530 (0x212) 2748 uint32_t reserved_531; // offset: 531 (0x213) 2749 uint32_t reserved_532; // offset: 532 (0x214) 2750 uint32_t reserved_533; // offset: 533 (0x215) 2751 uint32_t reserved_534; // offset: 534 (0x216) 2752 uint32_t reserved_535; // offset: 535 (0x217) 2753 uint32_t reserved_536; // offset: 536 (0x218) 2754 uint32_t reserved_537; // offset: 537 (0x219) 2755 uint32_t reserved_538; // offset: 538 (0x21A) 2756 uint32_t reserved_539; // offset: 539 (0x21B) 2757 uint32_t reserved_540; // offset: 540 (0x21C) 2758 uint32_t reserved_541; // offset: 541 (0x21D) 2759 uint32_t reserved_542; // offset: 542 (0x21E) 2760 uint32_t reserved_543; // offset: 543 (0x21F) 2761 uint32_t reserved_544; // offset: 544 (0x220) 2762 uint32_t reserved_545; // offset: 545 (0x221) 2763 uint32_t reserved_546; // offset: 546 (0x222) 2764 uint32_t reserved_547; // offset: 547 (0x223) 2765 uint32_t reserved_548; // offset: 548 (0x224) 2766 uint32_t reserved_549; // offset: 549 (0x225) 2767 uint32_t reserved_550; // offset: 550 (0x226) 2768 uint32_t reserved_551; // offset: 551 (0x227) 2769 uint32_t reserved_552; // offset: 552 (0x228) 2770 uint32_t reserved_553; // offset: 553 (0x229) 2771 uint32_t reserved_554; // offset: 554 (0x22A) 2772 uint32_t reserved_555; // offset: 555 (0x22B) 2773 uint32_t reserved_556; // offset: 556 (0x22C) 2774 uint32_t reserved_557; // offset: 557 (0x22D) 2775 uint32_t reserved_558; // offset: 558 (0x22E) 2776 uint32_t reserved_559; // offset: 559 (0x22F) 2777 uint32_t reserved_560; // offset: 560 (0x230) 2778 uint32_t reserved_561; // offset: 561 (0x231) 2779 uint32_t reserved_562; // offset: 562 (0x232) 2780 uint32_t reserved_563; // offset: 563 (0x233) 2781 uint32_t reserved_564; // offset: 564 (0x234) 2782 uint32_t reserved_565; // offset: 565 (0x235) 2783 uint32_t reserved_566; // offset: 566 (0x236) 2784 uint32_t reserved_567; // offset: 567 (0x237) 2785 uint32_t reserved_568; // offset: 568 (0x238) 2786 uint32_t reserved_569; // offset: 569 (0x239) 2787 uint32_t reserved_570; // offset: 570 (0x23A) 2788 uint32_t reserved_571; // offset: 571 (0x23B) 2789 uint32_t reserved_572; // offset: 572 (0x23C) 2790 uint32_t reserved_573; // offset: 573 (0x23D) 2791 uint32_t reserved_574; // offset: 574 (0x23E) 2792 uint32_t reserved_575; // offset: 575 (0x23F) 2793 uint32_t reserved_576; // offset: 576 (0x240) 2794 uint32_t reserved_577; // offset: 577 (0x241) 2795 uint32_t reserved_578; // offset: 578 (0x242) 2796 uint32_t reserved_579; // offset: 579 (0x243) 2797 uint32_t reserved_580; // offset: 580 (0x244) 2798 uint32_t reserved_581; // offset: 581 (0x245) 2799 uint32_t reserved_582; // offset: 582 (0x246) 2800 uint32_t reserved_583; // offset: 583 (0x247) 2801 uint32_t reserved_584; // offset: 584 (0x248) 2802 uint32_t reserved_585; // offset: 585 (0x249) 2803 uint32_t reserved_586; // offset: 586 (0x24A) 2804 uint32_t reserved_587; // offset: 587 (0x24B) 2805 uint32_t reserved_588; // offset: 588 (0x24C) 2806 uint32_t reserved_589; // offset: 589 (0x24D) 2807 uint32_t reserved_590; // offset: 590 (0x24E) 2808 uint32_t reserved_591; // offset: 591 (0x24F) 2809 uint32_t reserved_592; // offset: 592 (0x250) 2810 uint32_t reserved_593; // offset: 593 (0x251) 2811 uint32_t reserved_594; // offset: 594 (0x252) 2812 uint32_t reserved_595; // offset: 595 (0x253) 2813 uint32_t reserved_596; // offset: 596 (0x254) 2814 uint32_t reserved_597; // offset: 597 (0x255) 2815 uint32_t reserved_598; // offset: 598 (0x256) 2816 uint32_t reserved_599; // offset: 599 (0x257) 2817 uint32_t reserved_600; // offset: 600 (0x258) 2818 uint32_t reserved_601; // offset: 601 (0x259) 2819 uint32_t reserved_602; // offset: 602 (0x25A) 2820 uint32_t reserved_603; // offset: 603 (0x25B) 2821 uint32_t reserved_604; // offset: 604 (0x25C) 2822 uint32_t reserved_605; // offset: 605 (0x25D) 2823 uint32_t reserved_606; // offset: 606 (0x25E) 2824 uint32_t reserved_607; // offset: 607 (0x25F) 2825 uint32_t reserved_608; // offset: 608 (0x260) 2826 uint32_t reserved_609; // offset: 609 (0x261) 2827 uint32_t reserved_610; // offset: 610 (0x262) 2828 uint32_t reserved_611; // offset: 611 (0x263) 2829 uint32_t reserved_612; // offset: 612 (0x264) 2830 uint32_t reserved_613; // offset: 613 (0x265) 2831 uint32_t reserved_614; // offset: 614 (0x266) 2832 uint32_t reserved_615; // offset: 615 (0x267) 2833 uint32_t reserved_616; // offset: 616 (0x268) 2834 uint32_t reserved_617; // offset: 617 (0x269) 2835 uint32_t reserved_618; // offset: 618 (0x26A) 2836 uint32_t reserved_619; // offset: 619 (0x26B) 2837 uint32_t reserved_620; // offset: 620 (0x26C) 2838 uint32_t reserved_621; // offset: 621 (0x26D) 2839 uint32_t reserved_622; // offset: 622 (0x26E) 2840 uint32_t reserved_623; // offset: 623 (0x26F) 2841 uint32_t reserved_624; // offset: 624 (0x270) 2842 uint32_t reserved_625; // offset: 625 (0x271) 2843 uint32_t reserved_626; // offset: 626 (0x272) 2844 uint32_t reserved_627; // offset: 627 (0x273) 2845 uint32_t reserved_628; // offset: 628 (0x274) 2846 uint32_t reserved_629; // offset: 629 (0x275) 2847 uint32_t reserved_630; // offset: 630 (0x276) 2848 uint32_t reserved_631; // offset: 631 (0x277) 2849 uint32_t reserved_632; // offset: 632 (0x278) 2850 uint32_t reserved_633; // offset: 633 (0x279) 2851 uint32_t reserved_634; // offset: 634 (0x27A) 2852 uint32_t reserved_635; // offset: 635 (0x27B) 2853 uint32_t reserved_636; // offset: 636 (0x27C) 2854 uint32_t reserved_637; // offset: 637 (0x27D) 2855 uint32_t reserved_638; // offset: 638 (0x27E) 2856 uint32_t reserved_639; // offset: 639 (0x27F) 2857 uint32_t reserved_640; // offset: 640 (0x280) 2858 uint32_t reserved_641; // offset: 641 (0x281) 2859 uint32_t reserved_642; // offset: 642 (0x282) 2860 uint32_t reserved_643; // offset: 643 (0x283) 2861 uint32_t reserved_644; // offset: 644 (0x284) 2862 uint32_t reserved_645; // offset: 645 (0x285) 2863 uint32_t reserved_646; // offset: 646 (0x286) 2864 uint32_t reserved_647; // offset: 647 (0x287) 2865 uint32_t reserved_648; // offset: 648 (0x288) 2866 uint32_t reserved_649; // offset: 649 (0x289) 2867 uint32_t reserved_650; // offset: 650 (0x28A) 2868 uint32_t reserved_651; // offset: 651 (0x28B) 2869 uint32_t reserved_652; // offset: 652 (0x28C) 2870 uint32_t reserved_653; // offset: 653 (0x28D) 2871 uint32_t reserved_654; // offset: 654 (0x28E) 2872 uint32_t reserved_655; // offset: 655 (0x28F) 2873 uint32_t reserved_656; // offset: 656 (0x290) 2874 uint32_t reserved_657; // offset: 657 (0x291) 2875 uint32_t reserved_658; // offset: 658 (0x292) 2876 uint32_t reserved_659; // offset: 659 (0x293) 2877 uint32_t reserved_660; // offset: 660 (0x294) 2878 uint32_t reserved_661; // offset: 661 (0x295) 2879 uint32_t reserved_662; // offset: 662 (0x296) 2880 uint32_t reserved_663; // offset: 663 (0x297) 2881 uint32_t reserved_664; // offset: 664 (0x298) 2882 uint32_t reserved_665; // offset: 665 (0x299) 2883 uint32_t reserved_666; // offset: 666 (0x29A) 2884 uint32_t reserved_667; // offset: 667 (0x29B) 2885 uint32_t reserved_668; // offset: 668 (0x29C) 2886 uint32_t reserved_669; // offset: 669 (0x29D) 2887 uint32_t reserved_670; // offset: 670 (0x29E) 2888 uint32_t reserved_671; // offset: 671 (0x29F) 2889 uint32_t reserved_672; // offset: 672 (0x2A0) 2890 uint32_t reserved_673; // offset: 673 (0x2A1) 2891 uint32_t reserved_674; // offset: 674 (0x2A2) 2892 uint32_t reserved_675; // offset: 675 (0x2A3) 2893 uint32_t reserved_676; // offset: 676 (0x2A4) 2894 uint32_t reserved_677; // offset: 677 (0x2A5) 2895 uint32_t reserved_678; // offset: 678 (0x2A6) 2896 uint32_t reserved_679; // offset: 679 (0x2A7) 2897 uint32_t reserved_680; // offset: 680 (0x2A8) 2898 uint32_t reserved_681; // offset: 681 (0x2A9) 2899 uint32_t reserved_682; // offset: 682 (0x2AA) 2900 uint32_t reserved_683; // offset: 683 (0x2AB) 2901 uint32_t reserved_684; // offset: 684 (0x2AC) 2902 uint32_t reserved_685; // offset: 685 (0x2AD) 2903 uint32_t reserved_686; // offset: 686 (0x2AE) 2904 uint32_t reserved_687; // offset: 687 (0x2AF) 2905 uint32_t reserved_688; // offset: 688 (0x2B0) 2906 uint32_t reserved_689; // offset: 689 (0x2B1) 2907 uint32_t reserved_690; // offset: 690 (0x2B2) 2908 uint32_t reserved_691; // offset: 691 (0x2B3) 2909 uint32_t reserved_692; // offset: 692 (0x2B4) 2910 uint32_t reserved_693; // offset: 693 (0x2B5) 2911 uint32_t reserved_694; // offset: 694 (0x2B6) 2912 uint32_t reserved_695; // offset: 695 (0x2B7) 2913 uint32_t reserved_696; // offset: 696 (0x2B8) 2914 uint32_t reserved_697; // offset: 697 (0x2B9) 2915 uint32_t reserved_698; // offset: 698 (0x2BA) 2916 uint32_t reserved_699; // offset: 699 (0x2BB) 2917 uint32_t reserved_700; // offset: 700 (0x2BC) 2918 uint32_t reserved_701; // offset: 701 (0x2BD) 2919 uint32_t reserved_702; // offset: 702 (0x2BE) 2920 uint32_t reserved_703; // offset: 703 (0x2BF) 2921 uint32_t reserved_704; // offset: 704 (0x2C0) 2922 uint32_t reserved_705; // offset: 705 (0x2C1) 2923 uint32_t reserved_706; // offset: 706 (0x2C2) 2924 uint32_t reserved_707; // offset: 707 (0x2C3) 2925 uint32_t reserved_708; // offset: 708 (0x2C4) 2926 uint32_t reserved_709; // offset: 709 (0x2C5) 2927 uint32_t reserved_710; // offset: 710 (0x2C6) 2928 uint32_t reserved_711; // offset: 711 (0x2C7) 2929 uint32_t reserved_712; // offset: 712 (0x2C8) 2930 uint32_t reserved_713; // offset: 713 (0x2C9) 2931 uint32_t reserved_714; // offset: 714 (0x2CA) 2932 uint32_t reserved_715; // offset: 715 (0x2CB) 2933 uint32_t reserved_716; // offset: 716 (0x2CC) 2934 uint32_t reserved_717; // offset: 717 (0x2CD) 2935 uint32_t reserved_718; // offset: 718 (0x2CE) 2936 uint32_t reserved_719; // offset: 719 (0x2CF) 2937 uint32_t reserved_720; // offset: 720 (0x2D0) 2938 uint32_t reserved_721; // offset: 721 (0x2D1) 2939 uint32_t reserved_722; // offset: 722 (0x2D2) 2940 uint32_t reserved_723; // offset: 723 (0x2D3) 2941 uint32_t reserved_724; // offset: 724 (0x2D4) 2942 uint32_t reserved_725; // offset: 725 (0x2D5) 2943 uint32_t reserved_726; // offset: 726 (0x2D6) 2944 uint32_t reserved_727; // offset: 727 (0x2D7) 2945 uint32_t reserved_728; // offset: 728 (0x2D8) 2946 uint32_t reserved_729; // offset: 729 (0x2D9) 2947 uint32_t reserved_730; // offset: 730 (0x2DA) 2948 uint32_t reserved_731; // offset: 731 (0x2DB) 2949 uint32_t reserved_732; // offset: 732 (0x2DC) 2950 uint32_t reserved_733; // offset: 733 (0x2DD) 2951 uint32_t reserved_734; // offset: 734 (0x2DE) 2952 uint32_t reserved_735; // offset: 735 (0x2DF) 2953 uint32_t reserved_736; // offset: 736 (0x2E0) 2954 uint32_t reserved_737; // offset: 737 (0x2E1) 2955 uint32_t reserved_738; // offset: 738 (0x2E2) 2956 uint32_t reserved_739; // offset: 739 (0x2E3) 2957 uint32_t reserved_740; // offset: 740 (0x2E4) 2958 uint32_t reserved_741; // offset: 741 (0x2E5) 2959 uint32_t reserved_742; // offset: 742 (0x2E6) 2960 uint32_t reserved_743; // offset: 743 (0x2E7) 2961 uint32_t reserved_744; // offset: 744 (0x2E8) 2962 uint32_t reserved_745; // offset: 745 (0x2E9) 2963 uint32_t reserved_746; // offset: 746 (0x2EA) 2964 uint32_t reserved_747; // offset: 747 (0x2EB) 2965 uint32_t reserved_748; // offset: 748 (0x2EC) 2966 uint32_t reserved_749; // offset: 749 (0x2ED) 2967 uint32_t reserved_750; // offset: 750 (0x2EE) 2968 uint32_t reserved_751; // offset: 751 (0x2EF) 2969 uint32_t reserved_752; // offset: 752 (0x2F0) 2970 uint32_t reserved_753; // offset: 753 (0x2F1) 2971 uint32_t reserved_754; // offset: 754 (0x2F2) 2972 uint32_t reserved_755; // offset: 755 (0x2F3) 2973 uint32_t reserved_756; // offset: 756 (0x2F4) 2974 uint32_t reserved_757; // offset: 757 (0x2F5) 2975 uint32_t reserved_758; // offset: 758 (0x2F6) 2976 uint32_t reserved_759; // offset: 759 (0x2F7) 2977 uint32_t reserved_760; // offset: 760 (0x2F8) 2978 uint32_t reserved_761; // offset: 761 (0x2F9) 2979 uint32_t reserved_762; // offset: 762 (0x2FA) 2980 uint32_t reserved_763; // offset: 763 (0x2FB) 2981 uint32_t reserved_764; // offset: 764 (0x2FC) 2982 uint32_t reserved_765; // offset: 765 (0x2FD) 2983 uint32_t reserved_766; // offset: 766 (0x2FE) 2984 uint32_t reserved_767; // offset: 767 (0x2FF) 2985 uint32_t reserved_768; // offset: 768 (0x300) 2986 uint32_t reserved_769; // offset: 769 (0x301) 2987 uint32_t reserved_770; // offset: 770 (0x302) 2988 uint32_t reserved_771; // offset: 771 (0x303) 2989 uint32_t reserved_772; // offset: 772 (0x304) 2990 uint32_t reserved_773; // offset: 773 (0x305) 2991 uint32_t reserved_774; // offset: 774 (0x306) 2992 uint32_t reserved_775; // offset: 775 (0x307) 2993 uint32_t reserved_776; // offset: 776 (0x308) 2994 uint32_t reserved_777; // offset: 777 (0x309) 2995 uint32_t reserved_778; // offset: 778 (0x30A) 2996 uint32_t reserved_779; // offset: 779 (0x30B) 2997 uint32_t reserved_780; // offset: 780 (0x30C) 2998 uint32_t reserved_781; // offset: 781 (0x30D) 2999 uint32_t reserved_782; // offset: 782 (0x30E) 3000 uint32_t reserved_783; // offset: 783 (0x30F) 3001 uint32_t reserved_784; // offset: 784 (0x310) 3002 uint32_t reserved_785; // offset: 785 (0x311) 3003 uint32_t reserved_786; // offset: 786 (0x312) 3004 uint32_t reserved_787; // offset: 787 (0x313) 3005 uint32_t reserved_788; // offset: 788 (0x314) 3006 uint32_t reserved_789; // offset: 789 (0x315) 3007 uint32_t reserved_790; // offset: 790 (0x316) 3008 uint32_t reserved_791; // offset: 791 (0x317) 3009 uint32_t reserved_792; // offset: 792 (0x318) 3010 uint32_t reserved_793; // offset: 793 (0x319) 3011 uint32_t reserved_794; // offset: 794 (0x31A) 3012 uint32_t reserved_795; // offset: 795 (0x31B) 3013 uint32_t reserved_796; // offset: 796 (0x31C) 3014 uint32_t reserved_797; // offset: 797 (0x31D) 3015 uint32_t reserved_798; // offset: 798 (0x31E) 3016 uint32_t reserved_799; // offset: 799 (0x31F) 3017 uint32_t reserved_800; // offset: 800 (0x320) 3018 uint32_t reserved_801; // offset: 801 (0x321) 3019 uint32_t reserved_802; // offset: 802 (0x322) 3020 uint32_t reserved_803; // offset: 803 (0x323) 3021 uint32_t reserved_804; // offset: 804 (0x324) 3022 uint32_t reserved_805; // offset: 805 (0x325) 3023 uint32_t reserved_806; // offset: 806 (0x326) 3024 uint32_t reserved_807; // offset: 807 (0x327) 3025 uint32_t reserved_808; // offset: 808 (0x328) 3026 uint32_t reserved_809; // offset: 809 (0x329) 3027 uint32_t reserved_810; // offset: 810 (0x32A) 3028 uint32_t reserved_811; // offset: 811 (0x32B) 3029 uint32_t reserved_812; // offset: 812 (0x32C) 3030 uint32_t reserved_813; // offset: 813 (0x32D) 3031 uint32_t reserved_814; // offset: 814 (0x32E) 3032 uint32_t reserved_815; // offset: 815 (0x32F) 3033 uint32_t reserved_816; // offset: 816 (0x330) 3034 uint32_t reserved_817; // offset: 817 (0x331) 3035 uint32_t reserved_818; // offset: 818 (0x332) 3036 uint32_t reserved_819; // offset: 819 (0x333) 3037 uint32_t reserved_820; // offset: 820 (0x334) 3038 uint32_t reserved_821; // offset: 821 (0x335) 3039 uint32_t reserved_822; // offset: 822 (0x336) 3040 uint32_t reserved_823; // offset: 823 (0x337) 3041 uint32_t reserved_824; // offset: 824 (0x338) 3042 uint32_t reserved_825; // offset: 825 (0x339) 3043 uint32_t reserved_826; // offset: 826 (0x33A) 3044 uint32_t reserved_827; // offset: 827 (0x33B) 3045 uint32_t reserved_828; // offset: 828 (0x33C) 3046 uint32_t reserved_829; // offset: 829 (0x33D) 3047 uint32_t reserved_830; // offset: 830 (0x33E) 3048 uint32_t reserved_831; // offset: 831 (0x33F) 3049 uint32_t reserved_832; // offset: 832 (0x340) 3050 uint32_t reserved_833; // offset: 833 (0x341) 3051 uint32_t reserved_834; // offset: 834 (0x342) 3052 uint32_t reserved_835; // offset: 835 (0x343) 3053 uint32_t reserved_836; // offset: 836 (0x344) 3054 uint32_t reserved_837; // offset: 837 (0x345) 3055 uint32_t reserved_838; // offset: 838 (0x346) 3056 uint32_t reserved_839; // offset: 839 (0x347) 3057 uint32_t reserved_840; // offset: 840 (0x348) 3058 uint32_t reserved_841; // offset: 841 (0x349) 3059 uint32_t reserved_842; // offset: 842 (0x34A) 3060 uint32_t reserved_843; // offset: 843 (0x34B) 3061 uint32_t reserved_844; // offset: 844 (0x34C) 3062 uint32_t reserved_845; // offset: 845 (0x34D) 3063 uint32_t reserved_846; // offset: 846 (0x34E) 3064 uint32_t reserved_847; // offset: 847 (0x34F) 3065 uint32_t reserved_848; // offset: 848 (0x350) 3066 uint32_t reserved_849; // offset: 849 (0x351) 3067 uint32_t reserved_850; // offset: 850 (0x352) 3068 uint32_t reserved_851; // offset: 851 (0x353) 3069 uint32_t reserved_852; // offset: 852 (0x354) 3070 uint32_t reserved_853; // offset: 853 (0x355) 3071 uint32_t reserved_854; // offset: 854 (0x356) 3072 uint32_t reserved_855; // offset: 855 (0x357) 3073 uint32_t reserved_856; // offset: 856 (0x358) 3074 uint32_t reserved_857; // offset: 857 (0x359) 3075 uint32_t reserved_858; // offset: 858 (0x35A) 3076 uint32_t reserved_859; // offset: 859 (0x35B) 3077 uint32_t reserved_860; // offset: 860 (0x35C) 3078 uint32_t reserved_861; // offset: 861 (0x35D) 3079 uint32_t reserved_862; // offset: 862 (0x35E) 3080 uint32_t reserved_863; // offset: 863 (0x35F) 3081 uint32_t reserved_864; // offset: 864 (0x360) 3082 uint32_t reserved_865; // offset: 865 (0x361) 3083 uint32_t reserved_866; // offset: 866 (0x362) 3084 uint32_t reserved_867; // offset: 867 (0x363) 3085 uint32_t reserved_868; // offset: 868 (0x364) 3086 uint32_t reserved_869; // offset: 869 (0x365) 3087 uint32_t reserved_870; // offset: 870 (0x366) 3088 uint32_t reserved_871; // offset: 871 (0x367) 3089 uint32_t reserved_872; // offset: 872 (0x368) 3090 uint32_t reserved_873; // offset: 873 (0x369) 3091 uint32_t reserved_874; // offset: 874 (0x36A) 3092 uint32_t reserved_875; // offset: 875 (0x36B) 3093 uint32_t reserved_876; // offset: 876 (0x36C) 3094 uint32_t reserved_877; // offset: 877 (0x36D) 3095 uint32_t reserved_878; // offset: 878 (0x36E) 3096 uint32_t reserved_879; // offset: 879 (0x36F) 3097 uint32_t reserved_880; // offset: 880 (0x370) 3098 uint32_t reserved_881; // offset: 881 (0x371) 3099 uint32_t reserved_882; // offset: 882 (0x372) 3100 uint32_t reserved_883; // offset: 883 (0x373) 3101 uint32_t reserved_884; // offset: 884 (0x374) 3102 uint32_t reserved_885; // offset: 885 (0x375) 3103 uint32_t reserved_886; // offset: 886 (0x376) 3104 uint32_t reserved_887; // offset: 887 (0x377) 3105 uint32_t reserved_888; // offset: 888 (0x378) 3106 uint32_t reserved_889; // offset: 889 (0x379) 3107 uint32_t reserved_890; // offset: 890 (0x37A) 3108 uint32_t reserved_891; // offset: 891 (0x37B) 3109 uint32_t reserved_892; // offset: 892 (0x37C) 3110 uint32_t reserved_893; // offset: 893 (0x37D) 3111 uint32_t reserved_894; // offset: 894 (0x37E) 3112 uint32_t reserved_895; // offset: 895 (0x37F) 3113 uint32_t reserved_896; // offset: 896 (0x380) 3114 uint32_t reserved_897; // offset: 897 (0x381) 3115 uint32_t reserved_898; // offset: 898 (0x382) 3116 uint32_t reserved_899; // offset: 899 (0x383) 3117 uint32_t reserved_900; // offset: 900 (0x384) 3118 uint32_t reserved_901; // offset: 901 (0x385) 3119 uint32_t reserved_902; // offset: 902 (0x386) 3120 uint32_t reserved_903; // offset: 903 (0x387) 3121 uint32_t reserved_904; // offset: 904 (0x388) 3122 uint32_t reserved_905; // offset: 905 (0x389) 3123 uint32_t reserved_906; // offset: 906 (0x38A) 3124 uint32_t reserved_907; // offset: 907 (0x38B) 3125 uint32_t reserved_908; // offset: 908 (0x38C) 3126 uint32_t reserved_909; // offset: 909 (0x38D) 3127 uint32_t reserved_910; // offset: 910 (0x38E) 3128 uint32_t reserved_911; // offset: 911 (0x38F) 3129 uint32_t reserved_912; // offset: 912 (0x390) 3130 uint32_t reserved_913; // offset: 913 (0x391) 3131 uint32_t reserved_914; // offset: 914 (0x392) 3132 uint32_t reserved_915; // offset: 915 (0x393) 3133 uint32_t reserved_916; // offset: 916 (0x394) 3134 uint32_t reserved_917; // offset: 917 (0x395) 3135 uint32_t reserved_918; // offset: 918 (0x396) 3136 uint32_t reserved_919; // offset: 919 (0x397) 3137 uint32_t reserved_920; // offset: 920 (0x398) 3138 uint32_t reserved_921; // offset: 921 (0x399) 3139 uint32_t reserved_922; // offset: 922 (0x39A) 3140 uint32_t reserved_923; // offset: 923 (0x39B) 3141 uint32_t reserved_924; // offset: 924 (0x39C) 3142 uint32_t reserved_925; // offset: 925 (0x39D) 3143 uint32_t reserved_926; // offset: 926 (0x39E) 3144 uint32_t reserved_927; // offset: 927 (0x39F) 3145 uint32_t reserved_928; // offset: 928 (0x3A0) 3146 uint32_t reserved_929; // offset: 929 (0x3A1) 3147 uint32_t reserved_930; // offset: 930 (0x3A2) 3148 uint32_t reserved_931; // offset: 931 (0x3A3) 3149 uint32_t reserved_932; // offset: 932 (0x3A4) 3150 uint32_t reserved_933; // offset: 933 (0x3A5) 3151 uint32_t reserved_934; // offset: 934 (0x3A6) 3152 uint32_t reserved_935; // offset: 935 (0x3A7) 3153 uint32_t reserved_936; // offset: 936 (0x3A8) 3154 uint32_t reserved_937; // offset: 937 (0x3A9) 3155 uint32_t reserved_938; // offset: 938 (0x3AA) 3156 uint32_t reserved_939; // offset: 939 (0x3AB) 3157 uint32_t reserved_940; // offset: 940 (0x3AC) 3158 uint32_t reserved_941; // offset: 941 (0x3AD) 3159 uint32_t reserved_942; // offset: 942 (0x3AE) 3160 uint32_t reserved_943; // offset: 943 (0x3AF) 3161 uint32_t reserved_944; // offset: 944 (0x3B0) 3162 uint32_t reserved_945; // offset: 945 (0x3B1) 3163 uint32_t reserved_946; // offset: 946 (0x3B2) 3164 uint32_t reserved_947; // offset: 947 (0x3B3) 3165 uint32_t reserved_948; // offset: 948 (0x3B4) 3166 uint32_t reserved_949; // offset: 949 (0x3B5) 3167 uint32_t reserved_950; // offset: 950 (0x3B6) 3168 uint32_t reserved_951; // offset: 951 (0x3B7) 3169 uint32_t reserved_952; // offset: 952 (0x3B8) 3170 uint32_t reserved_953; // offset: 953 (0x3B9) 3171 uint32_t reserved_954; // offset: 954 (0x3BA) 3172 uint32_t reserved_955; // offset: 955 (0x3BB) 3173 uint32_t reserved_956; // offset: 956 (0x3BC) 3174 uint32_t reserved_957; // offset: 957 (0x3BD) 3175 uint32_t reserved_958; // offset: 958 (0x3BE) 3176 uint32_t reserved_959; // offset: 959 (0x3BF) 3177 uint32_t reserved_960; // offset: 960 (0x3C0) 3178 uint32_t reserved_961; // offset: 961 (0x3C1) 3179 uint32_t reserved_962; // offset: 962 (0x3C2) 3180 uint32_t reserved_963; // offset: 963 (0x3C3) 3181 uint32_t reserved_964; // offset: 964 (0x3C4) 3182 uint32_t reserved_965; // offset: 965 (0x3C5) 3183 uint32_t reserved_966; // offset: 966 (0x3C6) 3184 uint32_t reserved_967; // offset: 967 (0x3C7) 3185 uint32_t reserved_968; // offset: 968 (0x3C8) 3186 uint32_t reserved_969; // offset: 969 (0x3C9) 3187 uint32_t reserved_970; // offset: 970 (0x3CA) 3188 uint32_t reserved_971; // offset: 971 (0x3CB) 3189 uint32_t reserved_972; // offset: 972 (0x3CC) 3190 uint32_t reserved_973; // offset: 973 (0x3CD) 3191 uint32_t reserved_974; // offset: 974 (0x3CE) 3192 uint32_t reserved_975; // offset: 975 (0x3CF) 3193 uint32_t reserved_976; // offset: 976 (0x3D0) 3194 uint32_t reserved_977; // offset: 977 (0x3D1) 3195 uint32_t reserved_978; // offset: 978 (0x3D2) 3196 uint32_t reserved_979; // offset: 979 (0x3D3) 3197 uint32_t reserved_980; // offset: 980 (0x3D4) 3198 uint32_t reserved_981; // offset: 981 (0x3D5) 3199 uint32_t reserved_982; // offset: 982 (0x3D6) 3200 uint32_t reserved_983; // offset: 983 (0x3D7) 3201 uint32_t reserved_984; // offset: 984 (0x3D8) 3202 uint32_t reserved_985; // offset: 985 (0x3D9) 3203 uint32_t reserved_986; // offset: 986 (0x3DA) 3204 uint32_t reserved_987; // offset: 987 (0x3DB) 3205 uint32_t reserved_988; // offset: 988 (0x3DC) 3206 uint32_t reserved_989; // offset: 989 (0x3DD) 3207 uint32_t reserved_990; // offset: 990 (0x3DE) 3208 uint32_t reserved_991; // offset: 991 (0x3DF) 3209 uint32_t reserved_992; // offset: 992 (0x3E0) 3210 uint32_t reserved_993; // offset: 993 (0x3E1) 3211 uint32_t reserved_994; // offset: 994 (0x3E2) 3212 uint32_t reserved_995; // offset: 995 (0x3E3) 3213 uint32_t reserved_996; // offset: 996 (0x3E4) 3214 uint32_t reserved_997; // offset: 997 (0x3E5) 3215 uint32_t reserved_998; // offset: 998 (0x3E6) 3216 uint32_t reserved_999; // offset: 999 (0x3E7) 3217 uint32_t reserved_1000; // offset: 1000 (0x3E8) 3218 uint32_t reserved_1001; // offset: 1001 (0x3E9) 3219 uint32_t reserved_1002; // offset: 1002 (0x3EA) 3220 uint32_t reserved_1003; // offset: 1003 (0x3EB) 3221 uint32_t reserved_1004; // offset: 1004 (0x3EC) 3222 uint32_t reserved_1005; // offset: 1005 (0x3ED) 3223 uint32_t reserved_1006; // offset: 1006 (0x3EE) 3224 uint32_t reserved_1007; // offset: 1007 (0x3EF) 3225 uint32_t reserved_1008; // offset: 1008 (0x3F0) 3226 uint32_t reserved_1009; // offset: 1009 (0x3F1) 3227 uint32_t reserved_1010; // offset: 1010 (0x3F2) 3228 uint32_t reserved_1011; // offset: 1011 (0x3F3) 3229 uint32_t reserved_1012; // offset: 1012 (0x3F4) 3230 uint32_t reserved_1013; // offset: 1013 (0x3F5) 3231 uint32_t reserved_1014; // offset: 1014 (0x3F6) 3232 uint32_t reserved_1015; // offset: 1015 (0x3F7) 3233 uint32_t reserved_1016; // offset: 1016 (0x3F8) 3234 uint32_t reserved_1017; // offset: 1017 (0x3F9) 3235 uint32_t reserved_1018; // offset: 1018 (0x3FA) 3236 uint32_t reserved_1019; // offset: 1019 (0x3FB) 3237 uint32_t reserved_1020; // offset: 1020 (0x3FC) 3238 uint32_t reserved_1021; // offset: 1021 (0x3FD) 3239 uint32_t reserved_1022; // offset: 1022 (0x3FE) 3240 uint32_t reserved_1023; // offset: 1023 (0x3FF) 3241 }; 3242 3243 #endif /* V11_STRUCTS_H_ */ 3244