1 /* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _navi14_ip_offset_HEADER 22 #define _navi14_ip_offset_HEADER 23 24 #define MAX_INSTANCE 7 25 #define MAX_SEGMENT 5 26 27 28 struct IP_BASE_INSTANCE { 29 unsigned int segment[MAX_SEGMENT]; 30 }; 31 32 struct IP_BASE { 33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 34 } __maybe_unused; 35 36 37 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, 38 { { 0, 0, 0, 0, 0 } }, 39 { { 0, 0, 0, 0, 0 } }, 40 { { 0, 0, 0, 0, 0 } }, 41 { { 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0 } } } }; 44 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, 45 { { 0x00016E00, 0x02401C00, 0, 0, 0 } }, 46 { { 0x00017000, 0x02402000, 0, 0, 0 } }, 47 { { 0x00017200, 0x02402400, 0, 0, 0 } }, 48 { { 0x0001B000, 0x0242D800, 0, 0, 0 } }, 49 { { 0x00017E00, 0x0240BC00, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0 } } } }; 51 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0 } }, 55 { { 0, 0, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0 } } } }; 58 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0 } } } }; 65 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, 66 { { 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0 } } } }; 72 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, 73 { { 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0 } } } }; 79 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0 } } } }; 86 static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, 87 { { 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0 } } } }; 93 static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0 } }, 97 { { 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0 } } } }; 100 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0 } } } }; 107 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0 } } } }; 114 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, 115 { { 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0 } } } }; 121 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, 122 { { 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0 } } } }; 128 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, 129 { { 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0 } } } }; 135 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0 } } } }; 142 static const struct IP_BASE PCIE0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, 143 { { 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0 } }, 146 { { 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0 } } } }; 149 static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, 150 { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, 151 { { 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0 } } } }; 156 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, 157 { { 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0 } }, 160 { { 0, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0 } } } }; 163 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, 164 { { 0, 0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0 } }, 167 { { 0, 0, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0 } }, 169 { { 0, 0, 0, 0, 0 } } } }; 170 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, 171 { { 0x00054000, 0x02425C00, 0, 0, 0 } }, 172 { { 0x00094000, 0x02426000, 0, 0, 0 } }, 173 { { 0x000D4000, 0x02426400, 0, 0, 0 } }, 174 { { 0, 0, 0, 0, 0 } }, 175 { { 0, 0, 0, 0, 0 } }, 176 { { 0, 0, 0, 0, 0 } } } }; 177 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, 178 { { 0, 0, 0, 0, 0 } }, 179 { { 0, 0, 0, 0, 0 } }, 180 { { 0, 0, 0, 0, 0 } }, 181 { { 0, 0, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0 } } } }; 184 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, 185 { { 0, 0, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0 } }, 188 { { 0, 0, 0, 0, 0 } }, 189 { { 0, 0, 0, 0, 0 } }, 190 { { 0, 0, 0, 0, 0 } } } }; 191 192 193 #define ATHUB_BASE__INST0_SEG0 0x00000C00 194 #define ATHUB_BASE__INST0_SEG1 0x02408C00 195 #define ATHUB_BASE__INST0_SEG2 0 196 #define ATHUB_BASE__INST0_SEG3 0 197 #define ATHUB_BASE__INST0_SEG4 0 198 199 #define ATHUB_BASE__INST1_SEG0 0 200 #define ATHUB_BASE__INST1_SEG1 0 201 #define ATHUB_BASE__INST1_SEG2 0 202 #define ATHUB_BASE__INST1_SEG3 0 203 #define ATHUB_BASE__INST1_SEG4 0 204 205 #define ATHUB_BASE__INST2_SEG0 0 206 #define ATHUB_BASE__INST2_SEG1 0 207 #define ATHUB_BASE__INST2_SEG2 0 208 #define ATHUB_BASE__INST2_SEG3 0 209 #define ATHUB_BASE__INST2_SEG4 0 210 211 #define ATHUB_BASE__INST3_SEG0 0 212 #define ATHUB_BASE__INST3_SEG1 0 213 #define ATHUB_BASE__INST3_SEG2 0 214 #define ATHUB_BASE__INST3_SEG3 0 215 #define ATHUB_BASE__INST3_SEG4 0 216 217 #define ATHUB_BASE__INST4_SEG0 0 218 #define ATHUB_BASE__INST4_SEG1 0 219 #define ATHUB_BASE__INST4_SEG2 0 220 #define ATHUB_BASE__INST4_SEG3 0 221 #define ATHUB_BASE__INST4_SEG4 0 222 223 #define ATHUB_BASE__INST5_SEG0 0 224 #define ATHUB_BASE__INST5_SEG1 0 225 #define ATHUB_BASE__INST5_SEG2 0 226 #define ATHUB_BASE__INST5_SEG3 0 227 #define ATHUB_BASE__INST5_SEG4 0 228 229 #define ATHUB_BASE__INST6_SEG0 0 230 #define ATHUB_BASE__INST6_SEG1 0 231 #define ATHUB_BASE__INST6_SEG2 0 232 #define ATHUB_BASE__INST6_SEG3 0 233 #define ATHUB_BASE__INST6_SEG4 0 234 235 #define CLK_BASE__INST0_SEG0 0x00016C00 236 #define CLK_BASE__INST0_SEG1 0x02401800 237 #define CLK_BASE__INST0_SEG2 0 238 #define CLK_BASE__INST0_SEG3 0 239 #define CLK_BASE__INST0_SEG4 0 240 241 #define CLK_BASE__INST1_SEG0 0x00016E00 242 #define CLK_BASE__INST1_SEG1 0x02401C00 243 #define CLK_BASE__INST1_SEG2 0 244 #define CLK_BASE__INST1_SEG3 0 245 #define CLK_BASE__INST1_SEG4 0 246 247 #define CLK_BASE__INST2_SEG0 0x00017000 248 #define CLK_BASE__INST2_SEG1 0x02402000 249 #define CLK_BASE__INST2_SEG2 0 250 #define CLK_BASE__INST2_SEG3 0 251 #define CLK_BASE__INST2_SEG4 0 252 253 #define CLK_BASE__INST3_SEG0 0x00017200 254 #define CLK_BASE__INST3_SEG1 0x02402400 255 #define CLK_BASE__INST3_SEG2 0 256 #define CLK_BASE__INST3_SEG3 0 257 #define CLK_BASE__INST3_SEG4 0 258 259 #define CLK_BASE__INST4_SEG0 0x0001B000 260 #define CLK_BASE__INST4_SEG1 0x0242D800 261 #define CLK_BASE__INST4_SEG2 0 262 #define CLK_BASE__INST4_SEG3 0 263 #define CLK_BASE__INST4_SEG4 0 264 265 #define CLK_BASE__INST5_SEG0 0x00017E00 266 #define CLK_BASE__INST5_SEG1 0x0240BC00 267 #define CLK_BASE__INST5_SEG2 0 268 #define CLK_BASE__INST5_SEG3 0 269 #define CLK_BASE__INST5_SEG4 0 270 271 #define CLK_BASE__INST6_SEG0 0 272 #define CLK_BASE__INST6_SEG1 0 273 #define CLK_BASE__INST6_SEG2 0 274 #define CLK_BASE__INST6_SEG3 0 275 #define CLK_BASE__INST6_SEG4 0 276 277 #define DF_BASE__INST0_SEG0 0x00007000 278 #define DF_BASE__INST0_SEG1 0x0240B800 279 #define DF_BASE__INST0_SEG2 0 280 #define DF_BASE__INST0_SEG3 0 281 #define DF_BASE__INST0_SEG4 0 282 283 #define DF_BASE__INST1_SEG0 0 284 #define DF_BASE__INST1_SEG1 0 285 #define DF_BASE__INST1_SEG2 0 286 #define DF_BASE__INST1_SEG3 0 287 #define DF_BASE__INST1_SEG4 0 288 289 #define DF_BASE__INST2_SEG0 0 290 #define DF_BASE__INST2_SEG1 0 291 #define DF_BASE__INST2_SEG2 0 292 #define DF_BASE__INST2_SEG3 0 293 #define DF_BASE__INST2_SEG4 0 294 295 #define DF_BASE__INST3_SEG0 0 296 #define DF_BASE__INST3_SEG1 0 297 #define DF_BASE__INST3_SEG2 0 298 #define DF_BASE__INST3_SEG3 0 299 #define DF_BASE__INST3_SEG4 0 300 301 #define DF_BASE__INST4_SEG0 0 302 #define DF_BASE__INST4_SEG1 0 303 #define DF_BASE__INST4_SEG2 0 304 #define DF_BASE__INST4_SEG3 0 305 #define DF_BASE__INST4_SEG4 0 306 307 #define DF_BASE__INST5_SEG0 0 308 #define DF_BASE__INST5_SEG1 0 309 #define DF_BASE__INST5_SEG2 0 310 #define DF_BASE__INST5_SEG3 0 311 #define DF_BASE__INST5_SEG4 0 312 313 #define DF_BASE__INST6_SEG0 0 314 #define DF_BASE__INST6_SEG1 0 315 #define DF_BASE__INST6_SEG2 0 316 #define DF_BASE__INST6_SEG3 0 317 #define DF_BASE__INST6_SEG4 0 318 319 #define DIO_BASE__INST0_SEG0 0x02404000 320 #define DIO_BASE__INST0_SEG1 0 321 #define DIO_BASE__INST0_SEG2 0 322 #define DIO_BASE__INST0_SEG3 0 323 #define DIO_BASE__INST0_SEG4 0 324 325 #define DIO_BASE__INST1_SEG0 0 326 #define DIO_BASE__INST1_SEG1 0 327 #define DIO_BASE__INST1_SEG2 0 328 #define DIO_BASE__INST1_SEG3 0 329 #define DIO_BASE__INST1_SEG4 0 330 331 #define DIO_BASE__INST2_SEG0 0 332 #define DIO_BASE__INST2_SEG1 0 333 #define DIO_BASE__INST2_SEG2 0 334 #define DIO_BASE__INST2_SEG3 0 335 #define DIO_BASE__INST2_SEG4 0 336 337 #define DIO_BASE__INST3_SEG0 0 338 #define DIO_BASE__INST3_SEG1 0 339 #define DIO_BASE__INST3_SEG2 0 340 #define DIO_BASE__INST3_SEG3 0 341 #define DIO_BASE__INST3_SEG4 0 342 343 #define DIO_BASE__INST4_SEG0 0 344 #define DIO_BASE__INST4_SEG1 0 345 #define DIO_BASE__INST4_SEG2 0 346 #define DIO_BASE__INST4_SEG3 0 347 #define DIO_BASE__INST4_SEG4 0 348 349 #define DIO_BASE__INST5_SEG0 0 350 #define DIO_BASE__INST5_SEG1 0 351 #define DIO_BASE__INST5_SEG2 0 352 #define DIO_BASE__INST5_SEG3 0 353 #define DIO_BASE__INST5_SEG4 0 354 355 #define DIO_BASE__INST6_SEG0 0 356 #define DIO_BASE__INST6_SEG1 0 357 #define DIO_BASE__INST6_SEG2 0 358 #define DIO_BASE__INST6_SEG3 0 359 #define DIO_BASE__INST6_SEG4 0 360 361 #define DMU_BASE__INST0_SEG0 0x00000012 362 #define DMU_BASE__INST0_SEG1 0x000000C0 363 #define DMU_BASE__INST0_SEG2 0x000034C0 364 #define DMU_BASE__INST0_SEG3 0x00009000 365 #define DMU_BASE__INST0_SEG4 0x02403C00 366 367 #define DMU_BASE__INST1_SEG0 0 368 #define DMU_BASE__INST1_SEG1 0 369 #define DMU_BASE__INST1_SEG2 0 370 #define DMU_BASE__INST1_SEG3 0 371 #define DMU_BASE__INST1_SEG4 0 372 373 #define DMU_BASE__INST2_SEG0 0 374 #define DMU_BASE__INST2_SEG1 0 375 #define DMU_BASE__INST2_SEG2 0 376 #define DMU_BASE__INST2_SEG3 0 377 #define DMU_BASE__INST2_SEG4 0 378 379 #define DMU_BASE__INST3_SEG0 0 380 #define DMU_BASE__INST3_SEG1 0 381 #define DMU_BASE__INST3_SEG2 0 382 #define DMU_BASE__INST3_SEG3 0 383 #define DMU_BASE__INST3_SEG4 0 384 385 #define DMU_BASE__INST4_SEG0 0 386 #define DMU_BASE__INST4_SEG1 0 387 #define DMU_BASE__INST4_SEG2 0 388 #define DMU_BASE__INST4_SEG3 0 389 #define DMU_BASE__INST4_SEG4 0 390 391 #define DMU_BASE__INST5_SEG0 0 392 #define DMU_BASE__INST5_SEG1 0 393 #define DMU_BASE__INST5_SEG2 0 394 #define DMU_BASE__INST5_SEG3 0 395 #define DMU_BASE__INST5_SEG4 0 396 397 #define DMU_BASE__INST6_SEG0 0 398 #define DMU_BASE__INST6_SEG1 0 399 #define DMU_BASE__INST6_SEG2 0 400 #define DMU_BASE__INST6_SEG3 0 401 #define DMU_BASE__INST6_SEG4 0 402 403 #define DPCS_BASE__INST0_SEG0 0x00000012 404 #define DPCS_BASE__INST0_SEG1 0x000000C0 405 #define DPCS_BASE__INST0_SEG2 0x000034C0 406 #define DPCS_BASE__INST0_SEG3 0x00009000 407 #define DPCS_BASE__INST0_SEG4 0x02403C00 408 409 #define DPCS_BASE__INST1_SEG0 0 410 #define DPCS_BASE__INST1_SEG1 0 411 #define DPCS_BASE__INST1_SEG2 0 412 #define DPCS_BASE__INST1_SEG3 0 413 #define DPCS_BASE__INST1_SEG4 0 414 415 #define DPCS_BASE__INST2_SEG0 0 416 #define DPCS_BASE__INST2_SEG1 0 417 #define DPCS_BASE__INST2_SEG2 0 418 #define DPCS_BASE__INST2_SEG3 0 419 #define DPCS_BASE__INST2_SEG4 0 420 421 #define DPCS_BASE__INST3_SEG0 0 422 #define DPCS_BASE__INST3_SEG1 0 423 #define DPCS_BASE__INST3_SEG2 0 424 #define DPCS_BASE__INST3_SEG3 0 425 #define DPCS_BASE__INST3_SEG4 0 426 427 #define DPCS_BASE__INST4_SEG0 0 428 #define DPCS_BASE__INST4_SEG1 0 429 #define DPCS_BASE__INST4_SEG2 0 430 #define DPCS_BASE__INST4_SEG3 0 431 #define DPCS_BASE__INST4_SEG4 0 432 433 #define DPCS_BASE__INST5_SEG0 0 434 #define DPCS_BASE__INST5_SEG1 0 435 #define DPCS_BASE__INST5_SEG2 0 436 #define DPCS_BASE__INST5_SEG3 0 437 #define DPCS_BASE__INST5_SEG4 0 438 439 #define DPCS_BASE__INST6_SEG0 0 440 #define DPCS_BASE__INST6_SEG1 0 441 #define DPCS_BASE__INST6_SEG2 0 442 #define DPCS_BASE__INST6_SEG3 0 443 #define DPCS_BASE__INST6_SEG4 0 444 445 #define FUSE_BASE__INST0_SEG0 0x00017400 446 #define FUSE_BASE__INST0_SEG1 0x02401400 447 #define FUSE_BASE__INST0_SEG2 0 448 #define FUSE_BASE__INST0_SEG3 0 449 #define FUSE_BASE__INST0_SEG4 0 450 451 #define FUSE_BASE__INST1_SEG0 0 452 #define FUSE_BASE__INST1_SEG1 0 453 #define FUSE_BASE__INST1_SEG2 0 454 #define FUSE_BASE__INST1_SEG3 0 455 #define FUSE_BASE__INST1_SEG4 0 456 457 #define FUSE_BASE__INST2_SEG0 0 458 #define FUSE_BASE__INST2_SEG1 0 459 #define FUSE_BASE__INST2_SEG2 0 460 #define FUSE_BASE__INST2_SEG3 0 461 #define FUSE_BASE__INST2_SEG4 0 462 463 #define FUSE_BASE__INST3_SEG0 0 464 #define FUSE_BASE__INST3_SEG1 0 465 #define FUSE_BASE__INST3_SEG2 0 466 #define FUSE_BASE__INST3_SEG3 0 467 #define FUSE_BASE__INST3_SEG4 0 468 469 #define FUSE_BASE__INST4_SEG0 0 470 #define FUSE_BASE__INST4_SEG1 0 471 #define FUSE_BASE__INST4_SEG2 0 472 #define FUSE_BASE__INST4_SEG3 0 473 #define FUSE_BASE__INST4_SEG4 0 474 475 #define FUSE_BASE__INST5_SEG0 0 476 #define FUSE_BASE__INST5_SEG1 0 477 #define FUSE_BASE__INST5_SEG2 0 478 #define FUSE_BASE__INST5_SEG3 0 479 #define FUSE_BASE__INST5_SEG4 0 480 481 #define FUSE_BASE__INST6_SEG0 0 482 #define FUSE_BASE__INST6_SEG1 0 483 #define FUSE_BASE__INST6_SEG2 0 484 #define FUSE_BASE__INST6_SEG3 0 485 #define FUSE_BASE__INST6_SEG4 0 486 487 #define GC_BASE__INST0_SEG0 0x00001260 488 #define GC_BASE__INST0_SEG1 0x0000A000 489 #define GC_BASE__INST0_SEG2 0x02402C00 490 #define GC_BASE__INST0_SEG3 0 491 #define GC_BASE__INST0_SEG4 0 492 493 #define GC_BASE__INST1_SEG0 0 494 #define GC_BASE__INST1_SEG1 0 495 #define GC_BASE__INST1_SEG2 0 496 #define GC_BASE__INST1_SEG3 0 497 #define GC_BASE__INST1_SEG4 0 498 499 #define GC_BASE__INST2_SEG0 0 500 #define GC_BASE__INST2_SEG1 0 501 #define GC_BASE__INST2_SEG2 0 502 #define GC_BASE__INST2_SEG3 0 503 #define GC_BASE__INST2_SEG4 0 504 505 #define GC_BASE__INST3_SEG0 0 506 #define GC_BASE__INST3_SEG1 0 507 #define GC_BASE__INST3_SEG2 0 508 #define GC_BASE__INST3_SEG3 0 509 #define GC_BASE__INST3_SEG4 0 510 511 #define GC_BASE__INST4_SEG0 0 512 #define GC_BASE__INST4_SEG1 0 513 #define GC_BASE__INST4_SEG2 0 514 #define GC_BASE__INST4_SEG3 0 515 #define GC_BASE__INST4_SEG4 0 516 517 #define GC_BASE__INST5_SEG0 0 518 #define GC_BASE__INST5_SEG1 0 519 #define GC_BASE__INST5_SEG2 0 520 #define GC_BASE__INST5_SEG3 0 521 #define GC_BASE__INST5_SEG4 0 522 523 #define GC_BASE__INST6_SEG0 0 524 #define GC_BASE__INST6_SEG1 0 525 #define GC_BASE__INST6_SEG2 0 526 #define GC_BASE__INST6_SEG3 0 527 #define GC_BASE__INST6_SEG4 0 528 529 #define HDA_BASE__INST0_SEG0 0x004C0000 530 #define HDA_BASE__INST0_SEG1 0x02404800 531 #define HDA_BASE__INST0_SEG2 0 532 #define HDA_BASE__INST0_SEG3 0 533 #define HDA_BASE__INST0_SEG4 0 534 535 #define HDA_BASE__INST1_SEG0 0 536 #define HDA_BASE__INST1_SEG1 0 537 #define HDA_BASE__INST1_SEG2 0 538 #define HDA_BASE__INST1_SEG3 0 539 #define HDA_BASE__INST1_SEG4 0 540 541 #define HDA_BASE__INST2_SEG0 0 542 #define HDA_BASE__INST2_SEG1 0 543 #define HDA_BASE__INST2_SEG2 0 544 #define HDA_BASE__INST2_SEG3 0 545 #define HDA_BASE__INST2_SEG4 0 546 547 #define HDA_BASE__INST3_SEG0 0 548 #define HDA_BASE__INST3_SEG1 0 549 #define HDA_BASE__INST3_SEG2 0 550 #define HDA_BASE__INST3_SEG3 0 551 #define HDA_BASE__INST3_SEG4 0 552 553 #define HDA_BASE__INST4_SEG0 0 554 #define HDA_BASE__INST4_SEG1 0 555 #define HDA_BASE__INST4_SEG2 0 556 #define HDA_BASE__INST4_SEG3 0 557 #define HDA_BASE__INST4_SEG4 0 558 559 #define HDA_BASE__INST5_SEG0 0 560 #define HDA_BASE__INST5_SEG1 0 561 #define HDA_BASE__INST5_SEG2 0 562 #define HDA_BASE__INST5_SEG3 0 563 #define HDA_BASE__INST5_SEG4 0 564 565 #define HDA_BASE__INST6_SEG0 0 566 #define HDA_BASE__INST6_SEG1 0 567 #define HDA_BASE__INST6_SEG2 0 568 #define HDA_BASE__INST6_SEG3 0 569 #define HDA_BASE__INST6_SEG4 0 570 571 #define HDP_BASE__INST0_SEG0 0x00000F20 572 #define HDP_BASE__INST0_SEG1 0x0240A400 573 #define HDP_BASE__INST0_SEG2 0 574 #define HDP_BASE__INST0_SEG3 0 575 #define HDP_BASE__INST0_SEG4 0 576 577 #define HDP_BASE__INST1_SEG0 0 578 #define HDP_BASE__INST1_SEG1 0 579 #define HDP_BASE__INST1_SEG2 0 580 #define HDP_BASE__INST1_SEG3 0 581 #define HDP_BASE__INST1_SEG4 0 582 583 #define HDP_BASE__INST2_SEG0 0 584 #define HDP_BASE__INST2_SEG1 0 585 #define HDP_BASE__INST2_SEG2 0 586 #define HDP_BASE__INST2_SEG3 0 587 #define HDP_BASE__INST2_SEG4 0 588 589 #define HDP_BASE__INST3_SEG0 0 590 #define HDP_BASE__INST3_SEG1 0 591 #define HDP_BASE__INST3_SEG2 0 592 #define HDP_BASE__INST3_SEG3 0 593 #define HDP_BASE__INST3_SEG4 0 594 595 #define HDP_BASE__INST4_SEG0 0 596 #define HDP_BASE__INST4_SEG1 0 597 #define HDP_BASE__INST4_SEG2 0 598 #define HDP_BASE__INST4_SEG3 0 599 #define HDP_BASE__INST4_SEG4 0 600 601 #define HDP_BASE__INST5_SEG0 0 602 #define HDP_BASE__INST5_SEG1 0 603 #define HDP_BASE__INST5_SEG2 0 604 #define HDP_BASE__INST5_SEG3 0 605 #define HDP_BASE__INST5_SEG4 0 606 607 #define HDP_BASE__INST6_SEG0 0 608 #define HDP_BASE__INST6_SEG1 0 609 #define HDP_BASE__INST6_SEG2 0 610 #define HDP_BASE__INST6_SEG3 0 611 #define HDP_BASE__INST6_SEG4 0 612 613 #define MMHUB_BASE__INST0_SEG0 0x0001A000 614 #define MMHUB_BASE__INST0_SEG1 0x02408800 615 #define MMHUB_BASE__INST0_SEG2 0 616 #define MMHUB_BASE__INST0_SEG3 0 617 #define MMHUB_BASE__INST0_SEG4 0 618 619 #define MMHUB_BASE__INST1_SEG0 0 620 #define MMHUB_BASE__INST1_SEG1 0 621 #define MMHUB_BASE__INST1_SEG2 0 622 #define MMHUB_BASE__INST1_SEG3 0 623 #define MMHUB_BASE__INST1_SEG4 0 624 625 #define MMHUB_BASE__INST2_SEG0 0 626 #define MMHUB_BASE__INST2_SEG1 0 627 #define MMHUB_BASE__INST2_SEG2 0 628 #define MMHUB_BASE__INST2_SEG3 0 629 #define MMHUB_BASE__INST2_SEG4 0 630 631 #define MMHUB_BASE__INST3_SEG0 0 632 #define MMHUB_BASE__INST3_SEG1 0 633 #define MMHUB_BASE__INST3_SEG2 0 634 #define MMHUB_BASE__INST3_SEG3 0 635 #define MMHUB_BASE__INST3_SEG4 0 636 637 #define MMHUB_BASE__INST4_SEG0 0 638 #define MMHUB_BASE__INST4_SEG1 0 639 #define MMHUB_BASE__INST4_SEG2 0 640 #define MMHUB_BASE__INST4_SEG3 0 641 #define MMHUB_BASE__INST4_SEG4 0 642 643 #define MMHUB_BASE__INST5_SEG0 0 644 #define MMHUB_BASE__INST5_SEG1 0 645 #define MMHUB_BASE__INST5_SEG2 0 646 #define MMHUB_BASE__INST5_SEG3 0 647 #define MMHUB_BASE__INST5_SEG4 0 648 649 #define MMHUB_BASE__INST6_SEG0 0 650 #define MMHUB_BASE__INST6_SEG1 0 651 #define MMHUB_BASE__INST6_SEG2 0 652 #define MMHUB_BASE__INST6_SEG3 0 653 #define MMHUB_BASE__INST6_SEG4 0 654 655 #define MP0_BASE__INST0_SEG0 0x00016000 656 #define MP0_BASE__INST0_SEG1 0x00DC0000 657 #define MP0_BASE__INST0_SEG2 0x00E00000 658 #define MP0_BASE__INST0_SEG3 0x00E40000 659 #define MP0_BASE__INST0_SEG4 0x0243FC00 660 661 #define MP0_BASE__INST1_SEG0 0 662 #define MP0_BASE__INST1_SEG1 0 663 #define MP0_BASE__INST1_SEG2 0 664 #define MP0_BASE__INST1_SEG3 0 665 #define MP0_BASE__INST1_SEG4 0 666 667 #define MP0_BASE__INST2_SEG0 0 668 #define MP0_BASE__INST2_SEG1 0 669 #define MP0_BASE__INST2_SEG2 0 670 #define MP0_BASE__INST2_SEG3 0 671 #define MP0_BASE__INST2_SEG4 0 672 673 #define MP0_BASE__INST3_SEG0 0 674 #define MP0_BASE__INST3_SEG1 0 675 #define MP0_BASE__INST3_SEG2 0 676 #define MP0_BASE__INST3_SEG3 0 677 #define MP0_BASE__INST3_SEG4 0 678 679 #define MP0_BASE__INST4_SEG0 0 680 #define MP0_BASE__INST4_SEG1 0 681 #define MP0_BASE__INST4_SEG2 0 682 #define MP0_BASE__INST4_SEG3 0 683 #define MP0_BASE__INST4_SEG4 0 684 685 #define MP0_BASE__INST5_SEG0 0 686 #define MP0_BASE__INST5_SEG1 0 687 #define MP0_BASE__INST5_SEG2 0 688 #define MP0_BASE__INST5_SEG3 0 689 #define MP0_BASE__INST5_SEG4 0 690 691 #define MP0_BASE__INST6_SEG0 0 692 #define MP0_BASE__INST6_SEG1 0 693 #define MP0_BASE__INST6_SEG2 0 694 #define MP0_BASE__INST6_SEG3 0 695 #define MP0_BASE__INST6_SEG4 0 696 697 #define MP1_BASE__INST0_SEG0 0x00016000 698 #define MP1_BASE__INST0_SEG1 0x00DC0000 699 #define MP1_BASE__INST0_SEG2 0x00E00000 700 #define MP1_BASE__INST0_SEG3 0x00E40000 701 #define MP1_BASE__INST0_SEG4 0x0243FC00 702 703 #define MP1_BASE__INST1_SEG0 0 704 #define MP1_BASE__INST1_SEG1 0 705 #define MP1_BASE__INST1_SEG2 0 706 #define MP1_BASE__INST1_SEG3 0 707 #define MP1_BASE__INST1_SEG4 0 708 709 #define MP1_BASE__INST2_SEG0 0 710 #define MP1_BASE__INST2_SEG1 0 711 #define MP1_BASE__INST2_SEG2 0 712 #define MP1_BASE__INST2_SEG3 0 713 #define MP1_BASE__INST2_SEG4 0 714 715 #define MP1_BASE__INST3_SEG0 0 716 #define MP1_BASE__INST3_SEG1 0 717 #define MP1_BASE__INST3_SEG2 0 718 #define MP1_BASE__INST3_SEG3 0 719 #define MP1_BASE__INST3_SEG4 0 720 721 #define MP1_BASE__INST4_SEG0 0 722 #define MP1_BASE__INST4_SEG1 0 723 #define MP1_BASE__INST4_SEG2 0 724 #define MP1_BASE__INST4_SEG3 0 725 #define MP1_BASE__INST4_SEG4 0 726 727 #define MP1_BASE__INST5_SEG0 0 728 #define MP1_BASE__INST5_SEG1 0 729 #define MP1_BASE__INST5_SEG2 0 730 #define MP1_BASE__INST5_SEG3 0 731 #define MP1_BASE__INST5_SEG4 0 732 733 #define MP1_BASE__INST6_SEG0 0 734 #define MP1_BASE__INST6_SEG1 0 735 #define MP1_BASE__INST6_SEG2 0 736 #define MP1_BASE__INST6_SEG3 0 737 #define MP1_BASE__INST6_SEG4 0 738 739 #define NBIF0_BASE__INST0_SEG0 0x00000000 740 #define NBIF0_BASE__INST0_SEG1 0x00000014 741 #define NBIF0_BASE__INST0_SEG2 0x00000D20 742 #define NBIF0_BASE__INST0_SEG3 0x00010400 743 #define NBIF0_BASE__INST0_SEG4 0x0241B000 744 745 #define NBIF0_BASE__INST1_SEG0 0 746 #define NBIF0_BASE__INST1_SEG1 0 747 #define NBIF0_BASE__INST1_SEG2 0 748 #define NBIF0_BASE__INST1_SEG3 0 749 #define NBIF0_BASE__INST1_SEG4 0 750 751 #define NBIF0_BASE__INST2_SEG0 0 752 #define NBIF0_BASE__INST2_SEG1 0 753 #define NBIF0_BASE__INST2_SEG2 0 754 #define NBIF0_BASE__INST2_SEG3 0 755 #define NBIF0_BASE__INST2_SEG4 0 756 757 #define NBIF0_BASE__INST3_SEG0 0 758 #define NBIF0_BASE__INST3_SEG1 0 759 #define NBIF0_BASE__INST3_SEG2 0 760 #define NBIF0_BASE__INST3_SEG3 0 761 #define NBIF0_BASE__INST3_SEG4 0 762 763 #define NBIF0_BASE__INST4_SEG0 0 764 #define NBIF0_BASE__INST4_SEG1 0 765 #define NBIF0_BASE__INST4_SEG2 0 766 #define NBIF0_BASE__INST4_SEG3 0 767 #define NBIF0_BASE__INST4_SEG4 0 768 769 #define NBIF0_BASE__INST5_SEG0 0 770 #define NBIF0_BASE__INST5_SEG1 0 771 #define NBIF0_BASE__INST5_SEG2 0 772 #define NBIF0_BASE__INST5_SEG3 0 773 #define NBIF0_BASE__INST5_SEG4 0 774 775 #define NBIF0_BASE__INST6_SEG0 0 776 #define NBIF0_BASE__INST6_SEG1 0 777 #define NBIF0_BASE__INST6_SEG2 0 778 #define NBIF0_BASE__INST6_SEG3 0 779 #define NBIF0_BASE__INST6_SEG4 0 780 781 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 782 #define OSSSYS_BASE__INST0_SEG1 0x0240A000 783 #define OSSSYS_BASE__INST0_SEG2 0 784 #define OSSSYS_BASE__INST0_SEG3 0 785 #define OSSSYS_BASE__INST0_SEG4 0 786 787 #define OSSSYS_BASE__INST1_SEG0 0 788 #define OSSSYS_BASE__INST1_SEG1 0 789 #define OSSSYS_BASE__INST1_SEG2 0 790 #define OSSSYS_BASE__INST1_SEG3 0 791 #define OSSSYS_BASE__INST1_SEG4 0 792 793 #define OSSSYS_BASE__INST2_SEG0 0 794 #define OSSSYS_BASE__INST2_SEG1 0 795 #define OSSSYS_BASE__INST2_SEG2 0 796 #define OSSSYS_BASE__INST2_SEG3 0 797 #define OSSSYS_BASE__INST2_SEG4 0 798 799 #define OSSSYS_BASE__INST3_SEG0 0 800 #define OSSSYS_BASE__INST3_SEG1 0 801 #define OSSSYS_BASE__INST3_SEG2 0 802 #define OSSSYS_BASE__INST3_SEG3 0 803 #define OSSSYS_BASE__INST3_SEG4 0 804 805 #define OSSSYS_BASE__INST4_SEG0 0 806 #define OSSSYS_BASE__INST4_SEG1 0 807 #define OSSSYS_BASE__INST4_SEG2 0 808 #define OSSSYS_BASE__INST4_SEG3 0 809 #define OSSSYS_BASE__INST4_SEG4 0 810 811 #define OSSSYS_BASE__INST5_SEG0 0 812 #define OSSSYS_BASE__INST5_SEG1 0 813 #define OSSSYS_BASE__INST5_SEG2 0 814 #define OSSSYS_BASE__INST5_SEG3 0 815 #define OSSSYS_BASE__INST5_SEG4 0 816 817 #define OSSSYS_BASE__INST6_SEG0 0 818 #define OSSSYS_BASE__INST6_SEG1 0 819 #define OSSSYS_BASE__INST6_SEG2 0 820 #define OSSSYS_BASE__INST6_SEG3 0 821 #define OSSSYS_BASE__INST6_SEG4 0 822 823 #define PCIE0_BASE__INST0_SEG0 0x00000000 824 #define PCIE0_BASE__INST0_SEG1 0x00000014 825 #define PCIE0_BASE__INST0_SEG2 0x00000D20 826 #define PCIE0_BASE__INST0_SEG3 0x00010400 827 #define PCIE0_BASE__INST0_SEG4 0x0241B000 828 829 #define PCIE0_BASE__INST1_SEG0 0 830 #define PCIE0_BASE__INST1_SEG1 0 831 #define PCIE0_BASE__INST1_SEG2 0 832 #define PCIE0_BASE__INST1_SEG3 0 833 #define PCIE0_BASE__INST1_SEG4 0 834 835 #define PCIE0_BASE__INST2_SEG0 0 836 #define PCIE0_BASE__INST2_SEG1 0 837 #define PCIE0_BASE__INST2_SEG2 0 838 #define PCIE0_BASE__INST2_SEG3 0 839 #define PCIE0_BASE__INST2_SEG4 0 840 841 #define PCIE0_BASE__INST3_SEG0 0 842 #define PCIE0_BASE__INST3_SEG1 0 843 #define PCIE0_BASE__INST3_SEG2 0 844 #define PCIE0_BASE__INST3_SEG3 0 845 #define PCIE0_BASE__INST3_SEG4 0 846 847 #define PCIE0_BASE__INST4_SEG0 0 848 #define PCIE0_BASE__INST4_SEG1 0 849 #define PCIE0_BASE__INST4_SEG2 0 850 #define PCIE0_BASE__INST4_SEG3 0 851 #define PCIE0_BASE__INST4_SEG4 0 852 853 #define PCIE0_BASE__INST5_SEG0 0 854 #define PCIE0_BASE__INST5_SEG1 0 855 #define PCIE0_BASE__INST5_SEG2 0 856 #define PCIE0_BASE__INST5_SEG3 0 857 #define PCIE0_BASE__INST5_SEG4 0 858 859 #define PCIE0_BASE__INST6_SEG0 0 860 #define PCIE0_BASE__INST6_SEG1 0 861 #define PCIE0_BASE__INST6_SEG2 0 862 #define PCIE0_BASE__INST6_SEG3 0 863 #define PCIE0_BASE__INST6_SEG4 0 864 865 #define SDMA_BASE__INST0_SEG0 0x00001260 866 #define SDMA_BASE__INST0_SEG1 0x0000A000 867 #define SDMA_BASE__INST0_SEG2 0x02402C00 868 #define SDMA_BASE__INST0_SEG3 0 869 #define SDMA_BASE__INST0_SEG4 0 870 871 #define SDMA_BASE__INST1_SEG0 0x00001260 872 #define SDMA_BASE__INST1_SEG1 0x0000A000 873 #define SDMA_BASE__INST1_SEG2 0x02402C00 874 #define SDMA_BASE__INST1_SEG3 0 875 #define SDMA_BASE__INST1_SEG4 0 876 877 #define SDMA_BASE__INST2_SEG0 0 878 #define SDMA_BASE__INST2_SEG1 0 879 #define SDMA_BASE__INST2_SEG2 0 880 #define SDMA_BASE__INST2_SEG3 0 881 #define SDMA_BASE__INST2_SEG4 0 882 883 #define SDMA_BASE__INST3_SEG0 0 884 #define SDMA_BASE__INST3_SEG1 0 885 #define SDMA_BASE__INST3_SEG2 0 886 #define SDMA_BASE__INST3_SEG3 0 887 #define SDMA_BASE__INST3_SEG4 0 888 889 #define SDMA_BASE__INST4_SEG0 0 890 #define SDMA_BASE__INST4_SEG1 0 891 #define SDMA_BASE__INST4_SEG2 0 892 #define SDMA_BASE__INST4_SEG3 0 893 #define SDMA_BASE__INST4_SEG4 0 894 895 #define SDMA_BASE__INST5_SEG0 0 896 #define SDMA_BASE__INST5_SEG1 0 897 #define SDMA_BASE__INST5_SEG2 0 898 #define SDMA_BASE__INST5_SEG3 0 899 #define SDMA_BASE__INST5_SEG4 0 900 901 #define SDMA_BASE__INST6_SEG0 0 902 #define SDMA_BASE__INST6_SEG1 0 903 #define SDMA_BASE__INST6_SEG2 0 904 #define SDMA_BASE__INST6_SEG3 0 905 #define SDMA_BASE__INST6_SEG4 0 906 907 #define SMUIO_BASE__INST0_SEG0 0x00016800 908 #define SMUIO_BASE__INST0_SEG1 0x00016A00 909 #define SMUIO_BASE__INST0_SEG2 0x00440000 910 #define SMUIO_BASE__INST0_SEG3 0x02401000 911 #define SMUIO_BASE__INST0_SEG4 0 912 913 #define SMUIO_BASE__INST1_SEG0 0 914 #define SMUIO_BASE__INST1_SEG1 0 915 #define SMUIO_BASE__INST1_SEG2 0 916 #define SMUIO_BASE__INST1_SEG3 0 917 #define SMUIO_BASE__INST1_SEG4 0 918 919 #define SMUIO_BASE__INST2_SEG0 0 920 #define SMUIO_BASE__INST2_SEG1 0 921 #define SMUIO_BASE__INST2_SEG2 0 922 #define SMUIO_BASE__INST2_SEG3 0 923 #define SMUIO_BASE__INST2_SEG4 0 924 925 #define SMUIO_BASE__INST3_SEG0 0 926 #define SMUIO_BASE__INST3_SEG1 0 927 #define SMUIO_BASE__INST3_SEG2 0 928 #define SMUIO_BASE__INST3_SEG3 0 929 #define SMUIO_BASE__INST3_SEG4 0 930 931 #define SMUIO_BASE__INST4_SEG0 0 932 #define SMUIO_BASE__INST4_SEG1 0 933 #define SMUIO_BASE__INST4_SEG2 0 934 #define SMUIO_BASE__INST4_SEG3 0 935 #define SMUIO_BASE__INST4_SEG4 0 936 937 #define SMUIO_BASE__INST5_SEG0 0 938 #define SMUIO_BASE__INST5_SEG1 0 939 #define SMUIO_BASE__INST5_SEG2 0 940 #define SMUIO_BASE__INST5_SEG3 0 941 #define SMUIO_BASE__INST5_SEG4 0 942 943 #define SMUIO_BASE__INST6_SEG0 0 944 #define SMUIO_BASE__INST6_SEG1 0 945 #define SMUIO_BASE__INST6_SEG2 0 946 #define SMUIO_BASE__INST6_SEG3 0 947 #define SMUIO_BASE__INST6_SEG4 0 948 949 #define THM_BASE__INST0_SEG0 0x00016600 950 #define THM_BASE__INST0_SEG1 0x02400C00 951 #define THM_BASE__INST0_SEG2 0 952 #define THM_BASE__INST0_SEG3 0 953 #define THM_BASE__INST0_SEG4 0 954 955 #define THM_BASE__INST1_SEG0 0 956 #define THM_BASE__INST1_SEG1 0 957 #define THM_BASE__INST1_SEG2 0 958 #define THM_BASE__INST1_SEG3 0 959 #define THM_BASE__INST1_SEG4 0 960 961 #define THM_BASE__INST2_SEG0 0 962 #define THM_BASE__INST2_SEG1 0 963 #define THM_BASE__INST2_SEG2 0 964 #define THM_BASE__INST2_SEG3 0 965 #define THM_BASE__INST2_SEG4 0 966 967 #define THM_BASE__INST3_SEG0 0 968 #define THM_BASE__INST3_SEG1 0 969 #define THM_BASE__INST3_SEG2 0 970 #define THM_BASE__INST3_SEG3 0 971 #define THM_BASE__INST3_SEG4 0 972 973 #define THM_BASE__INST4_SEG0 0 974 #define THM_BASE__INST4_SEG1 0 975 #define THM_BASE__INST4_SEG2 0 976 #define THM_BASE__INST4_SEG3 0 977 #define THM_BASE__INST4_SEG4 0 978 979 #define THM_BASE__INST5_SEG0 0 980 #define THM_BASE__INST5_SEG1 0 981 #define THM_BASE__INST5_SEG2 0 982 #define THM_BASE__INST5_SEG3 0 983 #define THM_BASE__INST5_SEG4 0 984 985 #define THM_BASE__INST6_SEG0 0 986 #define THM_BASE__INST6_SEG1 0 987 #define THM_BASE__INST6_SEG2 0 988 #define THM_BASE__INST6_SEG3 0 989 #define THM_BASE__INST6_SEG4 0 990 991 #define UMC_BASE__INST0_SEG0 0x00014000 992 #define UMC_BASE__INST0_SEG1 0x02425800 993 #define UMC_BASE__INST0_SEG2 0 994 #define UMC_BASE__INST0_SEG3 0 995 #define UMC_BASE__INST0_SEG4 0 996 997 #define UMC_BASE__INST1_SEG0 0x00054000 998 #define UMC_BASE__INST1_SEG1 0x02425C00 999 #define UMC_BASE__INST1_SEG2 0 1000 #define UMC_BASE__INST1_SEG3 0 1001 #define UMC_BASE__INST1_SEG4 0 1002 1003 #define UMC_BASE__INST2_SEG0 0x00094000 1004 #define UMC_BASE__INST2_SEG1 0x02426000 1005 #define UMC_BASE__INST2_SEG2 0 1006 #define UMC_BASE__INST2_SEG3 0 1007 #define UMC_BASE__INST2_SEG4 0 1008 1009 #define UMC_BASE__INST3_SEG0 0x000D4000 1010 #define UMC_BASE__INST3_SEG1 0x02426400 1011 #define UMC_BASE__INST3_SEG2 0 1012 #define UMC_BASE__INST3_SEG3 0 1013 #define UMC_BASE__INST3_SEG4 0 1014 1015 #define UMC_BASE__INST4_SEG0 0 1016 #define UMC_BASE__INST4_SEG1 0 1017 #define UMC_BASE__INST4_SEG2 0 1018 #define UMC_BASE__INST4_SEG3 0 1019 #define UMC_BASE__INST4_SEG4 0 1020 1021 #define UMC_BASE__INST5_SEG0 0 1022 #define UMC_BASE__INST5_SEG1 0 1023 #define UMC_BASE__INST5_SEG2 0 1024 #define UMC_BASE__INST5_SEG3 0 1025 #define UMC_BASE__INST5_SEG4 0 1026 1027 #define UMC_BASE__INST6_SEG0 0 1028 #define UMC_BASE__INST6_SEG1 0 1029 #define UMC_BASE__INST6_SEG2 0 1030 #define UMC_BASE__INST6_SEG3 0 1031 #define UMC_BASE__INST6_SEG4 0 1032 1033 #define USB0_BASE__INST0_SEG0 0x0242A800 1034 #define USB0_BASE__INST0_SEG1 0x05B00000 1035 #define USB0_BASE__INST0_SEG2 0 1036 #define USB0_BASE__INST0_SEG3 0 1037 #define USB0_BASE__INST0_SEG4 0 1038 1039 #define USB0_BASE__INST1_SEG0 0 1040 #define USB0_BASE__INST1_SEG1 0 1041 #define USB0_BASE__INST1_SEG2 0 1042 #define USB0_BASE__INST1_SEG3 0 1043 #define USB0_BASE__INST1_SEG4 0 1044 1045 #define USB0_BASE__INST2_SEG0 0 1046 #define USB0_BASE__INST2_SEG1 0 1047 #define USB0_BASE__INST2_SEG2 0 1048 #define USB0_BASE__INST2_SEG3 0 1049 #define USB0_BASE__INST2_SEG4 0 1050 1051 #define USB0_BASE__INST3_SEG0 0 1052 #define USB0_BASE__INST3_SEG1 0 1053 #define USB0_BASE__INST3_SEG2 0 1054 #define USB0_BASE__INST3_SEG3 0 1055 #define USB0_BASE__INST3_SEG4 0 1056 1057 #define USB0_BASE__INST4_SEG0 0 1058 #define USB0_BASE__INST4_SEG1 0 1059 #define USB0_BASE__INST4_SEG2 0 1060 #define USB0_BASE__INST4_SEG3 0 1061 #define USB0_BASE__INST4_SEG4 0 1062 1063 #define USB0_BASE__INST5_SEG0 0 1064 #define USB0_BASE__INST5_SEG1 0 1065 #define USB0_BASE__INST5_SEG2 0 1066 #define USB0_BASE__INST5_SEG3 0 1067 #define USB0_BASE__INST5_SEG4 0 1068 1069 #define USB0_BASE__INST6_SEG0 0 1070 #define USB0_BASE__INST6_SEG1 0 1071 #define USB0_BASE__INST6_SEG2 0 1072 #define USB0_BASE__INST6_SEG3 0 1073 #define USB0_BASE__INST6_SEG4 0 1074 1075 #define UVD0_BASE__INST0_SEG0 0x00007800 1076 #define UVD0_BASE__INST0_SEG1 0x00007E00 1077 #define UVD0_BASE__INST0_SEG2 0x02403000 1078 #define UVD0_BASE__INST0_SEG3 0 1079 #define UVD0_BASE__INST0_SEG4 0 1080 1081 #define UVD0_BASE__INST1_SEG0 0 1082 #define UVD0_BASE__INST1_SEG1 0 1083 #define UVD0_BASE__INST1_SEG2 0 1084 #define UVD0_BASE__INST1_SEG3 0 1085 #define UVD0_BASE__INST1_SEG4 0 1086 1087 #define UVD0_BASE__INST2_SEG0 0 1088 #define UVD0_BASE__INST2_SEG1 0 1089 #define UVD0_BASE__INST2_SEG2 0 1090 #define UVD0_BASE__INST2_SEG3 0 1091 #define UVD0_BASE__INST2_SEG4 0 1092 1093 #define UVD0_BASE__INST3_SEG0 0 1094 #define UVD0_BASE__INST3_SEG1 0 1095 #define UVD0_BASE__INST3_SEG2 0 1096 #define UVD0_BASE__INST3_SEG3 0 1097 #define UVD0_BASE__INST3_SEG4 0 1098 1099 #define UVD0_BASE__INST4_SEG0 0 1100 #define UVD0_BASE__INST4_SEG1 0 1101 #define UVD0_BASE__INST4_SEG2 0 1102 #define UVD0_BASE__INST4_SEG3 0 1103 #define UVD0_BASE__INST4_SEG4 0 1104 1105 #define UVD0_BASE__INST5_SEG0 0 1106 #define UVD0_BASE__INST5_SEG1 0 1107 #define UVD0_BASE__INST5_SEG2 0 1108 #define UVD0_BASE__INST5_SEG3 0 1109 #define UVD0_BASE__INST5_SEG4 0 1110 1111 #define UVD0_BASE__INST6_SEG0 0 1112 #define UVD0_BASE__INST6_SEG1 0 1113 #define UVD0_BASE__INST6_SEG2 0 1114 #define UVD0_BASE__INST6_SEG3 0 1115 #define UVD0_BASE__INST6_SEG4 0 1116 1117 #endif 1118