1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #if !defined (_navi10_ENUM_HEADER) 22 #define _navi10_ENUM_HEADER 23 24 #ifndef _DRIVER_BUILD 25 #ifndef GL_ZERO 26 #define GL__ZERO BLEND_ZERO 27 #define GL__ONE BLEND_ONE 28 #define GL__SRC_COLOR BLEND_SRC_COLOR 29 #define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR 30 #define GL__DST_COLOR BLEND_DST_COLOR 31 #define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR 32 #define GL__SRC_ALPHA BLEND_SRC_ALPHA 33 #define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA 34 #define GL__DST_ALPHA BLEND_DST_ALPHA 35 #define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA 36 #define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE 37 #define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR 38 #define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR 39 #define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA 40 #define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA 41 #endif 42 #endif 43 44 /******************************************************* 45 * GDS DATA_TYPE Enums 46 *******************************************************/ 47 48 #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H 49 #define ENUMS_GDS_PERFCOUNT_SELECT_H 50 typedef enum GDS_PERFCOUNT_SELECT { 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 52 GDS_PERF_SEL_DS_BANK_CONFL = 1, 53 GDS_PERF_SEL_WBUF_FLUSH = 2, 54 GDS_PERF_SEL_WR_COMP = 3, 55 GDS_PERF_SEL_WBUF_WR = 4, 56 GDS_PERF_SEL_RBUF_HIT = 5, 57 GDS_PERF_SEL_RBUF_MISS = 6, 58 GDS_PERF_SEL_SE0_SH0_NORET = 7, 59 GDS_PERF_SEL_SE0_SH0_RET = 8, 60 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, 61 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, 62 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, 63 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, 64 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, 65 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, 66 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, 67 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, 68 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, 69 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, 70 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, 71 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, 72 GDS_PERF_SEL_SE0_SH1_NORET = 21, 73 GDS_PERF_SEL_SE0_SH1_RET = 22, 74 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, 75 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, 76 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, 77 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, 78 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, 79 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, 80 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, 81 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, 82 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, 83 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, 84 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, 85 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, 86 GDS_PERF_SEL_SE1_SH0_NORET = 35, 87 GDS_PERF_SEL_SE1_SH0_RET = 36, 88 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, 89 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, 90 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, 91 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, 92 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, 93 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, 94 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, 95 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, 96 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, 97 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, 98 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, 99 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, 100 GDS_PERF_SEL_SE1_SH1_NORET = 49, 101 GDS_PERF_SEL_SE1_SH1_RET = 50, 102 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, 103 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, 104 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, 105 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, 106 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, 107 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, 108 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, 109 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, 110 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, 111 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, 112 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, 113 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, 114 GDS_PERF_SEL_SE2_SH0_NORET = 63, 115 GDS_PERF_SEL_SE2_SH0_RET = 64, 116 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65, 117 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66, 118 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67, 119 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68, 120 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69, 121 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70, 122 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71, 123 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72, 124 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73, 125 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74, 126 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75, 127 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76, 128 GDS_PERF_SEL_SE2_SH1_NORET = 77, 129 GDS_PERF_SEL_SE2_SH1_RET = 78, 130 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79, 131 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80, 132 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81, 133 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82, 134 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83, 135 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84, 136 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85, 137 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86, 138 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87, 139 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88, 140 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89, 141 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90, 142 GDS_PERF_SEL_SE3_SH0_NORET = 91, 143 GDS_PERF_SEL_SE3_SH0_RET = 92, 144 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93, 145 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94, 146 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95, 147 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96, 148 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97, 149 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98, 150 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99, 151 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100, 152 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101, 153 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102, 154 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103, 155 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104, 156 GDS_PERF_SEL_SE3_SH1_NORET = 105, 157 GDS_PERF_SEL_SE3_SH1_RET = 106, 158 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107, 159 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108, 160 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109, 161 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110, 162 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111, 163 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112, 164 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113, 165 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114, 166 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115, 167 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116, 168 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117, 169 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118, 170 GDS_PERF_SEL_GWS_RELEASED = 119, 171 GDS_PERF_SEL_GWS_BYPASS = 120, 172 } GDS_PERFCOUNT_SELECT; 173 #endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ 174 175 /******************************************************* 176 * Chip Enums 177 *******************************************************/ 178 179 /* 180 * GATCL1RequestType enum 181 */ 182 183 typedef enum GATCL1RequestType { 184 GATCL1_TYPE_NORMAL = 0x00000000, 185 GATCL1_TYPE_SHOOTDOWN = 0x00000001, 186 GATCL1_TYPE_BYPASS = 0x00000002, 187 } GATCL1RequestType; 188 189 /* 190 * UTCL1RequestType enum 191 */ 192 193 typedef enum UTCL1RequestType { 194 UTCL1_TYPE_NORMAL = 0x00000000, 195 UTCL1_TYPE_SHOOTDOWN = 0x00000001, 196 UTCL1_TYPE_BYPASS = 0x00000002, 197 } UTCL1RequestType; 198 199 /* 200 * UTCL1FaultType enum 201 */ 202 203 typedef enum UTCL1FaultType { 204 UTCL1_XNACK_SUCCESS = 0x00000000, 205 UTCL1_XNACK_RETRY = 0x00000001, 206 UTCL1_XNACK_PRT = 0x00000002, 207 UTCL1_XNACK_NO_RETRY = 0x00000003, 208 } UTCL1FaultType; 209 210 /* 211 * UTCL0RequestType enum 212 */ 213 214 typedef enum UTCL0RequestType { 215 UTCL0_TYPE_NORMAL = 0x00000000, 216 UTCL0_TYPE_SHOOTDOWN = 0x00000001, 217 UTCL0_TYPE_BYPASS = 0x00000002, 218 } UTCL0RequestType; 219 220 /* 221 * UTCL0FaultType enum 222 */ 223 224 typedef enum UTCL0FaultType { 225 UTCL0_XNACK_SUCCESS = 0x00000000, 226 UTCL0_XNACK_RETRY = 0x00000001, 227 UTCL0_XNACK_PRT = 0x00000002, 228 UTCL0_XNACK_NO_RETRY = 0x00000003, 229 } UTCL0FaultType; 230 231 /* 232 * VMEMCMD_RETURN_ORDER enum 233 */ 234 235 typedef enum VMEMCMD_RETURN_ORDER { 236 VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000, 237 VMEMCMD_RETURN_IN_ORDER = 0x00000001, 238 VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002, 239 } VMEMCMD_RETURN_ORDER; 240 241 /* 242 * GL0V_CACHE_POLICIES enum 243 */ 244 245 typedef enum GL0V_CACHE_POLICIES { 246 GL0V_CACHE_POLICY_MISS_LRU = 0x00000000, 247 GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001, 248 GL0V_CACHE_POLICY_HIT_LRU = 0x00000002, 249 GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003, 250 } GL0V_CACHE_POLICIES; 251 252 /* 253 * GL1_CACHE_POLICIES enum 254 */ 255 256 typedef enum GL1_CACHE_POLICIES { 257 GL1_CACHE_POLICY_MISS_LRU = 0x00000000, 258 GL1_CACHE_POLICY_MISS_EVICT = 0x00000001, 259 GL1_CACHE_POLICY_HIT_LRU = 0x00000002, 260 GL1_CACHE_POLICY_HIT_EVICT = 0x00000003, 261 } GL1_CACHE_POLICIES; 262 263 /* 264 * GL1_CACHE_STORE_POLICIES enum 265 */ 266 267 typedef enum GL1_CACHE_STORE_POLICIES { 268 GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000, 269 } GL1_CACHE_STORE_POLICIES; 270 271 /* 272 * TCC_CACHE_POLICIES enum 273 */ 274 275 typedef enum TCC_CACHE_POLICIES { 276 TCC_CACHE_POLICY_LRU = 0x00000000, 277 TCC_CACHE_POLICY_STREAM = 0x00000001, 278 } TCC_CACHE_POLICIES; 279 280 /* 281 * TCC_MTYPE enum 282 */ 283 284 typedef enum TCC_MTYPE { 285 MTYPE_NC = 0x00000000, 286 MTYPE_WC = 0x00000001, 287 MTYPE_CC = 0x00000002, 288 } TCC_MTYPE; 289 290 /* 291 * GL2_CACHE_POLICIES enum 292 */ 293 294 typedef enum GL2_CACHE_POLICIES { 295 GL2_CACHE_POLICY_LRU = 0x00000000, 296 GL2_CACHE_POLICY_STREAM = 0x00000001, 297 GL2_CACHE_POLICY_NOA = 0x00000002, 298 GL2_CACHE_POLICY_BYPASS = 0x00000003, 299 } GL2_CACHE_POLICIES; 300 301 /* 302 * MTYPE enum 303 */ 304 305 typedef enum MTYPE { 306 MTYPE_C_RW_US = 0x00000000, 307 MTYPE_RESERVED_1 = 0x00000001, 308 MTYPE_C_RO_S = 0x00000002, 309 MTYPE_UC = 0x00000003, 310 MTYPE_C_RW_S = 0x00000004, 311 MTYPE_RESERVED_5 = 0x00000005, 312 MTYPE_C_RO_US = 0x00000006, 313 MTYPE_RESERVED_7 = 0x00000007, 314 } MTYPE; 315 316 /* 317 * RMI_CID enum 318 */ 319 320 typedef enum RMI_CID { 321 RMI_CID_CC = 0x00000000, 322 RMI_CID_FC = 0x00000001, 323 RMI_CID_CM = 0x00000002, 324 RMI_CID_DC = 0x00000003, 325 RMI_CID_Z = 0x00000004, 326 RMI_CID_S = 0x00000005, 327 RMI_CID_TILE = 0x00000006, 328 RMI_CID_ZPCPSD = 0x00000007, 329 } RMI_CID; 330 331 /* 332 * WritePolicy enum 333 */ 334 335 typedef enum WritePolicy { 336 CACHE_LRU_WR = 0x00000000, 337 CACHE_STREAM = 0x00000001, 338 CACHE_BYPASS = 0x00000002, 339 UNCACHED_WR = 0x00000003, 340 } WritePolicy; 341 342 /* 343 * ReadPolicy enum 344 */ 345 346 typedef enum ReadPolicy { 347 CACHE_LRU_RD = 0x00000000, 348 CACHE_NOA = 0x00000001, 349 UNCACHED_RD = 0x00000002, 350 RESERVED_RDPOLICY = 0x00000003, 351 } ReadPolicy; 352 353 /* 354 * PERFMON_COUNTER_MODE enum 355 */ 356 357 typedef enum PERFMON_COUNTER_MODE { 358 PERFMON_COUNTER_MODE_ACCUM = 0x00000000, 359 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, 360 PERFMON_COUNTER_MODE_MAX = 0x00000002, 361 PERFMON_COUNTER_MODE_DIRTY = 0x00000003, 362 PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, 363 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, 364 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, 365 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, 366 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, 367 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009, 368 PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, 369 } PERFMON_COUNTER_MODE; 370 371 /* 372 * PERFMON_SPM_MODE enum 373 */ 374 375 typedef enum PERFMON_SPM_MODE { 376 PERFMON_SPM_MODE_OFF = 0x00000000, 377 PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, 378 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, 379 PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, 380 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, 381 PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, 382 PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, 383 PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, 384 PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, 385 PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, 386 PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, 387 } PERFMON_SPM_MODE; 388 389 /* 390 * SurfaceTiling enum 391 */ 392 393 typedef enum SurfaceTiling { 394 ARRAY_LINEAR = 0x00000000, 395 ARRAY_TILED = 0x00000001, 396 } SurfaceTiling; 397 398 /* 399 * SurfaceArray enum 400 */ 401 402 typedef enum SurfaceArray { 403 ARRAY_1D = 0x00000000, 404 ARRAY_2D = 0x00000001, 405 ARRAY_3D = 0x00000002, 406 ARRAY_3D_SLICE = 0x00000003, 407 } SurfaceArray; 408 409 /* 410 * ColorArray enum 411 */ 412 413 typedef enum ColorArray { 414 ARRAY_2D_ALT_COLOR = 0x00000000, 415 ARRAY_2D_COLOR = 0x00000001, 416 ARRAY_3D_SLICE_COLOR = 0x00000003, 417 } ColorArray; 418 419 /* 420 * DepthArray enum 421 */ 422 423 typedef enum DepthArray { 424 ARRAY_2D_ALT_DEPTH = 0x00000000, 425 ARRAY_2D_DEPTH = 0x00000001, 426 } DepthArray; 427 428 /* 429 * ENUM_NUM_SIMD_PER_CU enum 430 */ 431 432 typedef enum ENUM_NUM_SIMD_PER_CU { 433 NUM_SIMD_PER_CU = 0x00000002, 434 } ENUM_NUM_SIMD_PER_CU; 435 436 /* 437 * DSM_ENABLE_ERROR_INJECT enum 438 */ 439 440 typedef enum DSM_ENABLE_ERROR_INJECT { 441 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, 442 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, 443 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002, 444 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003, 445 } DSM_ENABLE_ERROR_INJECT; 446 447 /* 448 * DSM_SELECT_INJECT_DELAY enum 449 */ 450 451 typedef enum DSM_SELECT_INJECT_DELAY { 452 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, 453 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, 454 } DSM_SELECT_INJECT_DELAY; 455 456 /* 457 * DSM_DATA_SEL enum 458 */ 459 460 typedef enum DSM_DATA_SEL { 461 DSM_DATA_SEL_DISABLE = 0x00000000, 462 DSM_DATA_SEL_0 = 0x00000001, 463 DSM_DATA_SEL_1 = 0x00000002, 464 DSM_DATA_SEL_BOTH = 0x00000003, 465 } DSM_DATA_SEL; 466 467 /* 468 * DSM_SINGLE_WRITE enum 469 */ 470 471 typedef enum DSM_SINGLE_WRITE { 472 DSM_SINGLE_WRITE_DIS = 0x00000000, 473 DSM_SINGLE_WRITE_EN = 0x00000001, 474 } DSM_SINGLE_WRITE; 475 476 /* 477 * Hdp_SurfaceEndian enum 478 */ 479 480 typedef enum Hdp_SurfaceEndian { 481 HDP_ENDIAN_NONE = 0x00000000, 482 HDP_ENDIAN_8IN16 = 0x00000001, 483 HDP_ENDIAN_8IN32 = 0x00000002, 484 HDP_ENDIAN_8IN64 = 0x00000003, 485 } Hdp_SurfaceEndian; 486 487 /******************************************************* 488 * CNVC_CFG Enums 489 *******************************************************/ 490 491 /* 492 * CNVC_ENABLE enum 493 */ 494 495 typedef enum CNVC_ENABLE { 496 CNVC_DIS = 0x00000000, 497 CNVC_EN = 0x00000001, 498 } CNVC_ENABLE; 499 500 /* 501 * CNVC_BYPASS enum 502 */ 503 504 typedef enum CNVC_BYPASS { 505 CNVC_BYPASS_DISABLE = 0x00000000, 506 CNVC_BYPASS_EN = 0x00000001, 507 } CNVC_BYPASS; 508 509 /* 510 * CNVC_PENDING enum 511 */ 512 513 typedef enum CNVC_PENDING { 514 CNVC_NOT_PENDING = 0x00000000, 515 CNVC_YES_PENDING = 0x00000001, 516 } CNVC_PENDING; 517 518 /* 519 * DENORM_TRUNCATE enum 520 */ 521 522 typedef enum DENORM_TRUNCATE { 523 CNVC_ROUND = 0x00000000, 524 CNVC_TRUNCATE = 0x00000001, 525 } DENORM_TRUNCATE; 526 527 /* 528 * PIX_EXPAND_MODE enum 529 */ 530 531 typedef enum PIX_EXPAND_MODE { 532 PIX_DYNAMIC_EXPANSION = 0x00000000, 533 PIX_ZERO_EXPANSION = 0x00000001, 534 } PIX_EXPAND_MODE; 535 536 /* 537 * SURFACE_PIXEL_FORMAT enum 538 */ 539 540 typedef enum SURFACE_PIXEL_FORMAT { 541 ARGB1555 = 0x00000001, 542 RGBA5551 = 0x00000002, 543 RGB565 = 0x00000003, 544 BGR565 = 0x00000004, 545 ARGB4444 = 0x00000005, 546 RGBA4444 = 0x00000006, 547 ARGB8888 = 0x00000008, 548 RGBA8888 = 0x00000009, 549 ARGB2101010 = 0x0000000a, 550 RGBA1010102 = 0x0000000b, 551 AYCrCb8888 = 0x0000000c, 552 YCrCbA8888 = 0x0000000d, 553 ACrYCb8888 = 0x0000000e, 554 CrYCbA8888 = 0x0000000f, 555 ARGB16161616_10MSB = 0x00000010, 556 RGBA16161616_10MSB = 0x00000011, 557 ARGB16161616_10LSB = 0x00000012, 558 RGBA16161616_10LSB = 0x00000013, 559 ARGB16161616_12MSB = 0x00000014, 560 RGBA16161616_12MSB = 0x00000015, 561 ARGB16161616_12LSB = 0x00000016, 562 RGBA16161616_12LSB = 0x00000017, 563 ARGB16161616_FLOAT = 0x00000018, 564 RGBA16161616_FLOAT = 0x00000019, 565 ARGB16161616_UNORM = 0x0000001a, 566 RGBA16161616_UNORM = 0x0000001b, 567 ARGB16161616_SNORM = 0x0000001c, 568 RGBA16161616_SNORM = 0x0000001d, 569 AYCrCb16161616_10MSB = 0x00000020, 570 AYCrCb16161616_10LSB = 0x00000021, 571 YCrCbA16161616_10MSB = 0x00000022, 572 YCrCbA16161616_10LSB = 0x00000023, 573 ACrYCb16161616_10MSB = 0x00000024, 574 ACrYCb16161616_10LSB = 0x00000025, 575 CrYCbA16161616_10MSB = 0x00000026, 576 CrYCbA16161616_10LSB = 0x00000027, 577 AYCrCb16161616_12MSB = 0x00000028, 578 AYCrCb16161616_12LSB = 0x00000029, 579 YCrCbA16161616_12MSB = 0x0000002a, 580 YCrCbA16161616_12LSB = 0x0000002b, 581 ACrYCb16161616_12MSB = 0x0000002c, 582 ACrYCb16161616_12LSB = 0x0000002d, 583 CrYCbA16161616_12MSB = 0x0000002e, 584 CrYCbA16161616_12LSB = 0x0000002f, 585 Y8_CrCb88_420_PLANAR = 0x00000040, 586 Y8_CbCr88_420_PLANAR = 0x00000041, 587 Y10_CrCb1010_420_PLANAR = 0x00000042, 588 Y10_CbCr1010_420_PLANAR = 0x00000043, 589 Y12_CrCb1212_420_PLANAR = 0x00000044, 590 Y12_CbCr1212_420_PLANAR = 0x00000045, 591 YCrYCb8888_422_PACKED = 0x00000048, 592 YCbYCr8888_422_PACKED = 0x00000049, 593 CrYCbY8888_422_PACKED = 0x0000004a, 594 CbYCrY8888_422_PACKED = 0x0000004b, 595 YCrYCb10101010_422_PACKED = 0x0000004c, 596 YCbYCr10101010_422_PACKED = 0x0000004d, 597 CrYCbY10101010_422_PACKED = 0x0000004e, 598 CbYCrY10101010_422_PACKED = 0x0000004f, 599 YCrYCb12121212_422_PACKED = 0x00000050, 600 YCbYCr12121212_422_PACKED = 0x00000051, 601 CrYCbY12121212_422_PACKED = 0x00000052, 602 CbYCrY12121212_422_PACKED = 0x00000053, 603 RGB111110_FIX = 0x00000070, 604 BGR101111_FIX = 0x00000071, 605 ACrYCb2101010 = 0x00000072, 606 CrYCbA1010102 = 0x00000073, 607 RGB111110_FLOAT = 0x00000076, 608 BGR101111_FLOAT = 0x00000077, 609 MONO_8 = 0x00000078, 610 MONO_10MSB = 0x00000079, 611 MONO_10LSB = 0x0000007a, 612 MONO_12MSB = 0x0000007b, 613 MONO_12LSB = 0x0000007c, 614 MONO_16 = 0x0000007d, 615 } SURFACE_PIXEL_FORMAT; 616 617 /* 618 * XNORM enum 619 */ 620 621 typedef enum XNORM { 622 XNORM_A = 0x00000000, 623 XNORM_B = 0x00000001, 624 } XNORM; 625 626 /* 627 * COLOR_KEYER_MODE enum 628 */ 629 630 typedef enum COLOR_KEYER_MODE { 631 FORCE_00 = 0x00000000, 632 FORCE_FF = 0x00000001, 633 RANGE_00 = 0x00000002, 634 RANGE_FF = 0x00000003, 635 } COLOR_KEYER_MODE; 636 637 /******************************************************* 638 * CNVC_CUR Enums 639 *******************************************************/ 640 641 /* 642 * CUR_ENABLE enum 643 */ 644 645 typedef enum CUR_ENABLE { 646 CUR_DIS = 0x00000000, 647 CUR_EN = 0x00000001, 648 } CUR_ENABLE; 649 650 /* 651 * CUR_PENDING enum 652 */ 653 654 typedef enum CUR_PENDING { 655 CUR_NOT_PENDING = 0x00000000, 656 CUR_YES_PENDING = 0x00000001, 657 } CUR_PENDING; 658 659 /* 660 * CUR_EXPAND_MODE enum 661 */ 662 663 typedef enum CUR_EXPAND_MODE { 664 CUR_DYNAMIC_EXPANSION = 0x00000000, 665 CUR_ZERO_EXPANSION = 0x00000001, 666 } CUR_EXPAND_MODE; 667 668 /* 669 * CUR_ROM_EN enum 670 */ 671 672 typedef enum CUR_ROM_EN { 673 CUR_FP_NO_ROM = 0x00000000, 674 CUR_FP_USE_ROM = 0x00000001, 675 } CUR_ROM_EN; 676 677 /* 678 * CUR_MODE enum 679 */ 680 681 typedef enum CUR_MODE { 682 MONO_2BIT = 0x00000000, 683 COLOR_24BIT_1BIT_AND = 0x00000001, 684 COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, 685 COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, 686 COLOR_64BIT_FP_PREMULT = 0x00000004, 687 COLOR_64BIT_FP_UNPREMULT = 0x00000005, 688 } CUR_MODE; 689 690 /* 691 * CUR_INV_CLAMP enum 692 */ 693 694 typedef enum CUR_INV_CLAMP { 695 CUR_CLAMP_DIS = 0x00000000, 696 CUR_CLAMP_EN = 0x00000001, 697 } CUR_INV_CLAMP; 698 699 /******************************************************* 700 * DSCL Enums 701 *******************************************************/ 702 703 /* 704 * SCL_COEF_FILTER_TYPE_SEL enum 705 */ 706 707 typedef enum SCL_COEF_FILTER_TYPE_SEL { 708 SCL_COEF_LUMA_VERT_FILTER = 0x00000000, 709 SCL_COEF_LUMA_HORZ_FILTER = 0x00000001, 710 SCL_COEF_CHROMA_VERT_FILTER = 0x00000002, 711 SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003, 712 SCL_COEF_ALPHA_VERT_FILTER = 0x00000004, 713 SCL_COEF_ALPHA_HORZ_FILTER = 0x00000005, 714 } SCL_COEF_FILTER_TYPE_SEL; 715 716 /* 717 * DSCL_MODE_SEL enum 718 */ 719 720 typedef enum DSCL_MODE_SEL { 721 DSCL_MODE_SCALING_444_BYPASS = 0x00000000, 722 DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001, 723 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002, 724 DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003, 725 DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004, 726 DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005, 727 DSCL_MODE_DSCL_BYPASS = 0x00000006, 728 } DSCL_MODE_SEL; 729 730 /* 731 * SCL_AUTOCAL_MODE enum 732 */ 733 734 typedef enum SCL_AUTOCAL_MODE { 735 AUTOCAL_MODE_OFF = 0x00000000, 736 AUTOCAL_MODE_AUTOSCALE = 0x00000001, 737 AUTOCAL_MODE_AUTOCENTER = 0x00000002, 738 AUTOCAL_MODE_AUTOREPLICATE = 0x00000003, 739 } SCL_AUTOCAL_MODE; 740 741 /* 742 * SCL_COEF_RAM_SEL enum 743 */ 744 745 typedef enum SCL_COEF_RAM_SEL { 746 SCL_COEF_RAM_SEL_0 = 0x00000000, 747 SCL_COEF_RAM_SEL_1 = 0x00000001, 748 } SCL_COEF_RAM_SEL; 749 750 /* 751 * SCL_CHROMA_COEF enum 752 */ 753 754 typedef enum SCL_CHROMA_COEF { 755 SCL_CHROMA_COEF_LUMA = 0x00000000, 756 SCL_CHROMA_COEF_CHROMA = 0x00000001, 757 } SCL_CHROMA_COEF; 758 759 /* 760 * SCL_ALPHA_COEF enum 761 */ 762 763 typedef enum SCL_ALPHA_COEF { 764 SCL_ALPHA_COEF_LUMA = 0x00000000, 765 SCL_ALPHA_COEF_ALPHA = 0x00000001, 766 } SCL_ALPHA_COEF; 767 768 /* 769 * COEF_RAM_SELECT_RD enum 770 */ 771 772 typedef enum COEF_RAM_SELECT_RD { 773 COEF_RAM_SELECT_BACK = 0x00000000, 774 COEF_RAM_SELECT_CURRENT = 0x00000001, 775 } COEF_RAM_SELECT_RD; 776 777 /* 778 * SCL_2TAP_HARDCODE enum 779 */ 780 781 typedef enum SCL_2TAP_HARDCODE { 782 SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000, 783 SCL_COEF_2TAP_HARDCODE_ON = 0x00000001, 784 } SCL_2TAP_HARDCODE; 785 786 /* 787 * SCL_SHARP_EN enum 788 */ 789 790 typedef enum SCL_SHARP_EN { 791 SCL_SHARP_DISABLE = 0x00000000, 792 SCL_SHARP_ENABLE = 0x00000001, 793 } SCL_SHARP_EN; 794 795 /* 796 * SCL_BOUNDARY enum 797 */ 798 799 typedef enum SCL_BOUNDARY { 800 SCL_BOUNDARY_EDGE = 0x00000000, 801 SCL_BOUNDARY_BLACK = 0x00000001, 802 } SCL_BOUNDARY; 803 804 /* 805 * LB_INTERLEAVE_EN enum 806 */ 807 808 typedef enum LB_INTERLEAVE_EN { 809 LB_INTERLEAVE_DISABLE = 0x00000000, 810 LB_INTERLEAVE_ENABLE = 0x00000001, 811 } LB_INTERLEAVE_EN; 812 813 /* 814 * LB_ALPHA_EN enum 815 */ 816 817 typedef enum LB_ALPHA_EN { 818 LB_ALPHA_DISABLE = 0x00000000, 819 LB_ALPHA_ENABLE = 0x00000001, 820 } LB_ALPHA_EN; 821 822 /* 823 * OBUF_BYPASS_SEL enum 824 */ 825 826 typedef enum OBUF_BYPASS_SEL { 827 OBUF_BYPASS_DIS = 0x00000000, 828 OBUF_BYPASS_EN = 0x00000001, 829 } OBUF_BYPASS_SEL; 830 831 /* 832 * OBUF_USE_FULL_BUFFER_SEL enum 833 */ 834 835 typedef enum OBUF_USE_FULL_BUFFER_SEL { 836 OBUF_RECOUT = 0x00000000, 837 OBUF_FULL = 0x00000001, 838 } OBUF_USE_FULL_BUFFER_SEL; 839 840 /* 841 * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum 842 */ 843 844 typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL { 845 OBUF_FULL_RECOUT = 0x00000000, 846 OBUF_HALF_RECOUT = 0x00000001, 847 } OBUF_IS_HALF_RECOUT_WIDTH_SEL; 848 849 /******************************************************* 850 * CM Enums 851 *******************************************************/ 852 853 /* 854 * CM_BYPASS enum 855 */ 856 857 typedef enum CM_BYPASS { 858 NON_BYPASS = 0x00000000, 859 BYPASS_EN = 0x00000001, 860 } CM_BYPASS; 861 862 /* 863 * CM_EN enum 864 */ 865 866 typedef enum CM_EN { 867 CM_DISABLE = 0x00000000, 868 CM_ENABLE = 0x00000001, 869 } CM_EN; 870 871 /* 872 * CM_PENDING enum 873 */ 874 875 typedef enum CM_PENDING { 876 CM_NOT_PENDING = 0x00000000, 877 CM_YES_PENDING = 0x00000001, 878 } CM_PENDING; 879 880 /* 881 * CM_DATA_SIGNED enum 882 */ 883 884 typedef enum CM_DATA_SIGNED { 885 UNSIGNED = 0x00000000, 886 SIGNED = 0x00000001, 887 } CM_DATA_SIGNED; 888 889 /* 890 * CM_WRITE_BASE_ONLY enum 891 */ 892 893 typedef enum CM_WRITE_BASE_ONLY { 894 WRITE_BOTH = 0x00000000, 895 WRITE_BASE_ONLY = 0x00000001, 896 } CM_WRITE_BASE_ONLY; 897 898 /* 899 * CM_LUT_4_CONFIG_ENUM enum 900 */ 901 902 typedef enum CM_LUT_4_CONFIG_ENUM { 903 LUT_4CFG_NO_MEMORY = 0x00000000, 904 LUT_4CFG_ROM_A = 0x00000001, 905 LUT_4CFG_ROM_B = 0x00000002, 906 LUT_4CFG_MEMORY_A = 0x00000003, 907 LUT_4CFG_MEMORY_B = 0x00000004, 908 } CM_LUT_4_CONFIG_ENUM; 909 910 /* 911 * CM_LUT_2_CONFIG_ENUM enum 912 */ 913 914 typedef enum CM_LUT_2_CONFIG_ENUM { 915 LUT_2CFG_NO_MEMORY = 0x00000000, 916 LUT_2CFG_MEMORY_A = 0x00000001, 917 LUT_2CFG_MEMORY_B = 0x00000002, 918 } CM_LUT_2_CONFIG_ENUM; 919 920 /* 921 * CM_LUT_4_MODE_ENUM enum 922 */ 923 924 typedef enum CM_LUT_4_MODE_ENUM { 925 LUT_4_MODE_BYPASS = 0x00000000, 926 LUT_4_MODE_ROMA_LUT = 0x00000001, 927 LUT_4_MODE_ROMB_LUT = 0x00000002, 928 LUT_4_MODE_RAMA_LUT = 0x00000003, 929 LUT_4_MODE_RAMB_LUT = 0x00000004, 930 } CM_LUT_4_MODE_ENUM; 931 932 /* 933 * CM_LUT_2_MODE_ENUM enum 934 */ 935 936 typedef enum CM_LUT_2_MODE_ENUM { 937 LUT_2_MODE_BYPASS = 0x00000000, 938 LUT_2_MODE_RAMA_LUT = 0x00000001, 939 LUT_2_MODE_RAMB_LUT = 0x00000002, 940 } CM_LUT_2_MODE_ENUM; 941 942 /* 943 * CM_LUT_RAM_SEL enum 944 */ 945 946 typedef enum CM_LUT_RAM_SEL { 947 RAMA_ACCESS = 0x00000000, 948 RAMB_ACCESS = 0x00000001, 949 } CM_LUT_RAM_SEL; 950 951 /* 952 * CM_LUT_NUM_SEG enum 953 */ 954 955 typedef enum CM_LUT_NUM_SEG { 956 SEGMENTS_1 = 0x00000000, 957 SEGMENTS_2 = 0x00000001, 958 SEGMENTS_4 = 0x00000002, 959 SEGMENTS_8 = 0x00000003, 960 SEGMENTS_16 = 0x00000004, 961 SEGMENTS_32 = 0x00000005, 962 SEGMENTS_64 = 0x00000006, 963 SEGMENTS_128 = 0x00000007, 964 } CM_LUT_NUM_SEG; 965 966 /* 967 * CM_ICSC_MODE_ENUM enum 968 */ 969 970 typedef enum CM_ICSC_MODE_ENUM { 971 BYPASS_ICSC = 0x00000000, 972 COEF_ICSC = 0x00000001, 973 COEF_ICSC_B = 0x00000002, 974 } CM_ICSC_MODE_ENUM; 975 976 /* 977 * CM_GAMUT_REMAP_MODE_ENUM enum 978 */ 979 980 typedef enum CM_GAMUT_REMAP_MODE_ENUM { 981 BYPASS_GAMUT = 0x00000000, 982 GAMUT_COEF = 0x00000001, 983 GAMUT_COEF_B = 0x00000002, 984 } CM_GAMUT_REMAP_MODE_ENUM; 985 986 /* 987 * CM_COEF_FORMAT_ENUM enum 988 */ 989 990 typedef enum CM_COEF_FORMAT_ENUM { 991 FIX_S2_13 = 0x00000000, 992 FIX_S3_12 = 0x00000001, 993 } CM_COEF_FORMAT_ENUM; 994 995 /* 996 * CMC_LUT_2_CONFIG_ENUM enum 997 */ 998 999 typedef enum CMC_LUT_2_CONFIG_ENUM { 1000 CMC_LUT_2CFG_NO_MEMORY = 0x00000000, 1001 CMC_LUT_2CFG_MEMORY_A = 0x00000001, 1002 CMC_LUT_2CFG_MEMORY_B = 0x00000002, 1003 } CMC_LUT_2_CONFIG_ENUM; 1004 1005 /* 1006 * CMC_LUT_2_MODE_ENUM enum 1007 */ 1008 1009 typedef enum CMC_LUT_2_MODE_ENUM { 1010 CMC_LUT_2_MODE_BYPASS = 0x00000000, 1011 CMC_LUT_2_MODE_RAMA_LUT = 0x00000001, 1012 CMC_LUT_2_MODE_RAMB_LUT = 0x00000002, 1013 } CMC_LUT_2_MODE_ENUM; 1014 1015 /* 1016 * CMC_LUT_RAM_SEL enum 1017 */ 1018 1019 typedef enum CMC_LUT_RAM_SEL { 1020 CMC_RAMA_ACCESS = 0x00000000, 1021 CMC_RAMB_ACCESS = 0x00000001, 1022 } CMC_LUT_RAM_SEL; 1023 1024 /* 1025 * CMC_3DLUT_RAM_SEL enum 1026 */ 1027 1028 typedef enum CMC_3DLUT_RAM_SEL { 1029 CMC_RAM0_ACCESS = 0x00000000, 1030 CMC_RAM1_ACCESS = 0x00000001, 1031 CMC_RAM2_ACCESS = 0x00000002, 1032 CMC_RAM3_ACCESS = 0x00000003, 1033 } CMC_3DLUT_RAM_SEL; 1034 1035 /* 1036 * CMC_LUT_NUM_SEG enum 1037 */ 1038 1039 typedef enum CMC_LUT_NUM_SEG { 1040 CMC_SEGMENTS_1 = 0x00000000, 1041 CMC_SEGMENTS_2 = 0x00000001, 1042 CMC_SEGMENTS_4 = 0x00000002, 1043 CMC_SEGMENTS_8 = 0x00000003, 1044 CMC_SEGMENTS_16 = 0x00000004, 1045 CMC_SEGMENTS_32 = 0x00000005, 1046 CMC_SEGMENTS_64 = 0x00000006, 1047 CMC_SEGMENTS_128 = 0x00000007, 1048 } CMC_LUT_NUM_SEG; 1049 1050 /* 1051 * CMC_3DLUT_30BIT_ENUM enum 1052 */ 1053 1054 typedef enum CMC_3DLUT_30BIT_ENUM { 1055 CMC_3DLUT_36BIT = 0x00000000, 1056 CMC_3DLUT_30BIT = 0x00000001, 1057 } CMC_3DLUT_30BIT_ENUM; 1058 1059 /* 1060 * CMC_3DLUT_SIZE_ENUM enum 1061 */ 1062 1063 typedef enum CMC_3DLUT_SIZE_ENUM { 1064 CMC_3DLUT_17CUBE = 0x00000000, 1065 CMC_3DLUT_9CUBE = 0x00000001, 1066 } CMC_3DLUT_SIZE_ENUM; 1067 1068 /******************************************************* 1069 * DPP_TOP Enums 1070 *******************************************************/ 1071 1072 /* 1073 * TEST_CLK_SEL enum 1074 */ 1075 1076 typedef enum TEST_CLK_SEL { 1077 TEST_CLK_SEL_0 = 0x00000000, 1078 TEST_CLK_SEL_1 = 0x00000001, 1079 TEST_CLK_SEL_2 = 0x00000002, 1080 TEST_CLK_SEL_3 = 0x00000003, 1081 TEST_CLK_SEL_4 = 0x00000004, 1082 TEST_CLK_SEL_5 = 0x00000005, 1083 TEST_CLK_SEL_6 = 0x00000006, 1084 TEST_CLK_SEL_7 = 0x00000007, 1085 TEST_CLK_SEL_8 = 0x00000008, 1086 } TEST_CLK_SEL; 1087 1088 /* 1089 * CRC_SRC_SEL enum 1090 */ 1091 1092 typedef enum CRC_SRC_SEL { 1093 CRC_SRC_0 = 0x00000000, 1094 CRC_SRC_1 = 0x00000001, 1095 CRC_SRC_2 = 0x00000002, 1096 CRC_SRC_3 = 0x00000003, 1097 } CRC_SRC_SEL; 1098 1099 /* 1100 * CRC_IN_PIX_SEL enum 1101 */ 1102 1103 typedef enum CRC_IN_PIX_SEL { 1104 CRC_IN_PIX_0 = 0x00000000, 1105 CRC_IN_PIX_1 = 0x00000001, 1106 CRC_IN_PIX_2 = 0x00000002, 1107 CRC_IN_PIX_3 = 0x00000003, 1108 CRC_IN_PIX_4 = 0x00000004, 1109 CRC_IN_PIX_5 = 0x00000005, 1110 CRC_IN_PIX_6 = 0x00000006, 1111 CRC_IN_PIX_7 = 0x00000007, 1112 } CRC_IN_PIX_SEL; 1113 1114 /* 1115 * CRC_CUR_BITS_SEL enum 1116 */ 1117 1118 typedef enum CRC_CUR_BITS_SEL { 1119 CRC_CUR_BITS_0 = 0x00000000, 1120 CRC_CUR_BITS_1 = 0x00000001, 1121 } CRC_CUR_BITS_SEL; 1122 1123 /* 1124 * CRC_IN_CUR_SEL enum 1125 */ 1126 1127 typedef enum CRC_IN_CUR_SEL { 1128 CRC_IN_CUR_0 = 0x00000000, 1129 CRC_IN_CUR_1 = 0x00000001, 1130 } CRC_IN_CUR_SEL; 1131 1132 /* 1133 * CRC_CUR_SEL enum 1134 */ 1135 1136 typedef enum CRC_CUR_SEL { 1137 CRC_CUR_0 = 0x00000000, 1138 CRC_CUR_1 = 0x00000001, 1139 } CRC_CUR_SEL; 1140 1141 /* 1142 * CRC_STEREO_SEL enum 1143 */ 1144 1145 typedef enum CRC_STEREO_SEL { 1146 CRC_STEREO_0 = 0x00000000, 1147 CRC_STEREO_1 = 0x00000001, 1148 CRC_STEREO_2 = 0x00000002, 1149 CRC_STEREO_3 = 0x00000003, 1150 } CRC_STEREO_SEL; 1151 1152 /* 1153 * CRC_INTERLACE_SEL enum 1154 */ 1155 1156 typedef enum CRC_INTERLACE_SEL { 1157 CRC_INTERLACE_0 = 0x00000000, 1158 CRC_INTERLACE_1 = 0x00000001, 1159 CRC_INTERLACE_2 = 0x00000002, 1160 CRC_INTERLACE_3 = 0x00000003, 1161 } CRC_INTERLACE_SEL; 1162 1163 /******************************************************* 1164 * DC_PERFMON Enums 1165 *******************************************************/ 1166 1167 /* 1168 * PERFCOUNTER_CVALUE_SEL enum 1169 */ 1170 1171 typedef enum PERFCOUNTER_CVALUE_SEL { 1172 PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000, 1173 PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001, 1174 PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002, 1175 PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003, 1176 PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004, 1177 PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005, 1178 PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006, 1179 PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007, 1180 } PERFCOUNTER_CVALUE_SEL; 1181 1182 /* 1183 * PERFCOUNTER_INC_MODE enum 1184 */ 1185 1186 typedef enum PERFCOUNTER_INC_MODE { 1187 PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000, 1188 PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001, 1189 PERFCOUNTER_INC_MODE_LSB = 0x00000002, 1190 PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003, 1191 PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004, 1192 } PERFCOUNTER_INC_MODE; 1193 1194 /* 1195 * PERFCOUNTER_HW_CNTL_SEL enum 1196 */ 1197 1198 typedef enum PERFCOUNTER_HW_CNTL_SEL { 1199 PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000, 1200 PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001, 1201 } PERFCOUNTER_HW_CNTL_SEL; 1202 1203 /* 1204 * PERFCOUNTER_RUNEN_MODE enum 1205 */ 1206 1207 typedef enum PERFCOUNTER_RUNEN_MODE { 1208 PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000, 1209 PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001, 1210 } PERFCOUNTER_RUNEN_MODE; 1211 1212 /* 1213 * PERFCOUNTER_CNTOFF_START_DIS enum 1214 */ 1215 1216 typedef enum PERFCOUNTER_CNTOFF_START_DIS { 1217 PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000, 1218 PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001, 1219 } PERFCOUNTER_CNTOFF_START_DIS; 1220 1221 /* 1222 * PERFCOUNTER_RESTART_EN enum 1223 */ 1224 1225 typedef enum PERFCOUNTER_RESTART_EN { 1226 PERFCOUNTER_RESTART_DISABLE = 0x00000000, 1227 PERFCOUNTER_RESTART_ENABLE = 0x00000001, 1228 } PERFCOUNTER_RESTART_EN; 1229 1230 /* 1231 * PERFCOUNTER_INT_EN enum 1232 */ 1233 1234 typedef enum PERFCOUNTER_INT_EN { 1235 PERFCOUNTER_INT_DISABLE = 0x00000000, 1236 PERFCOUNTER_INT_ENABLE = 0x00000001, 1237 } PERFCOUNTER_INT_EN; 1238 1239 /* 1240 * PERFCOUNTER_OFF_MASK enum 1241 */ 1242 1243 typedef enum PERFCOUNTER_OFF_MASK { 1244 PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000, 1245 PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001, 1246 } PERFCOUNTER_OFF_MASK; 1247 1248 /* 1249 * PERFCOUNTER_ACTIVE enum 1250 */ 1251 1252 typedef enum PERFCOUNTER_ACTIVE { 1253 PERFCOUNTER_IS_IDLE = 0x00000000, 1254 PERFCOUNTER_IS_ACTIVE = 0x00000001, 1255 } PERFCOUNTER_ACTIVE; 1256 1257 /* 1258 * PERFCOUNTER_INT_TYPE enum 1259 */ 1260 1261 typedef enum PERFCOUNTER_INT_TYPE { 1262 PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000, 1263 PERFCOUNTER_INT_TYPE_PULSE = 0x00000001, 1264 } PERFCOUNTER_INT_TYPE; 1265 1266 /* 1267 * PERFCOUNTER_COUNTED_VALUE_TYPE enum 1268 */ 1269 1270 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { 1271 PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000, 1272 PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001, 1273 PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002, 1274 } PERFCOUNTER_COUNTED_VALUE_TYPE; 1275 1276 /* 1277 * PERFCOUNTER_HW_STOP1_SEL enum 1278 */ 1279 1280 typedef enum PERFCOUNTER_HW_STOP1_SEL { 1281 PERFCOUNTER_HW_STOP1_0 = 0x00000000, 1282 PERFCOUNTER_HW_STOP1_1 = 0x00000001, 1283 } PERFCOUNTER_HW_STOP1_SEL; 1284 1285 /* 1286 * PERFCOUNTER_HW_STOP2_SEL enum 1287 */ 1288 1289 typedef enum PERFCOUNTER_HW_STOP2_SEL { 1290 PERFCOUNTER_HW_STOP2_0 = 0x00000000, 1291 PERFCOUNTER_HW_STOP2_1 = 0x00000001, 1292 } PERFCOUNTER_HW_STOP2_SEL; 1293 1294 /* 1295 * PERFCOUNTER_CNTL_SEL enum 1296 */ 1297 1298 typedef enum PERFCOUNTER_CNTL_SEL { 1299 PERFCOUNTER_CNTL_SEL_0 = 0x00000000, 1300 PERFCOUNTER_CNTL_SEL_1 = 0x00000001, 1301 PERFCOUNTER_CNTL_SEL_2 = 0x00000002, 1302 PERFCOUNTER_CNTL_SEL_3 = 0x00000003, 1303 PERFCOUNTER_CNTL_SEL_4 = 0x00000004, 1304 PERFCOUNTER_CNTL_SEL_5 = 0x00000005, 1305 PERFCOUNTER_CNTL_SEL_6 = 0x00000006, 1306 PERFCOUNTER_CNTL_SEL_7 = 0x00000007, 1307 } PERFCOUNTER_CNTL_SEL; 1308 1309 /* 1310 * PERFCOUNTER_CNT0_STATE enum 1311 */ 1312 1313 typedef enum PERFCOUNTER_CNT0_STATE { 1314 PERFCOUNTER_CNT0_STATE_RESET = 0x00000000, 1315 PERFCOUNTER_CNT0_STATE_START = 0x00000001, 1316 PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002, 1317 PERFCOUNTER_CNT0_STATE_HW = 0x00000003, 1318 } PERFCOUNTER_CNT0_STATE; 1319 1320 /* 1321 * PERFCOUNTER_STATE_SEL0 enum 1322 */ 1323 1324 typedef enum PERFCOUNTER_STATE_SEL0 { 1325 PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000, 1326 PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001, 1327 } PERFCOUNTER_STATE_SEL0; 1328 1329 /* 1330 * PERFCOUNTER_CNT1_STATE enum 1331 */ 1332 1333 typedef enum PERFCOUNTER_CNT1_STATE { 1334 PERFCOUNTER_CNT1_STATE_RESET = 0x00000000, 1335 PERFCOUNTER_CNT1_STATE_START = 0x00000001, 1336 PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002, 1337 PERFCOUNTER_CNT1_STATE_HW = 0x00000003, 1338 } PERFCOUNTER_CNT1_STATE; 1339 1340 /* 1341 * PERFCOUNTER_STATE_SEL1 enum 1342 */ 1343 1344 typedef enum PERFCOUNTER_STATE_SEL1 { 1345 PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000, 1346 PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001, 1347 } PERFCOUNTER_STATE_SEL1; 1348 1349 /* 1350 * PERFCOUNTER_CNT2_STATE enum 1351 */ 1352 1353 typedef enum PERFCOUNTER_CNT2_STATE { 1354 PERFCOUNTER_CNT2_STATE_RESET = 0x00000000, 1355 PERFCOUNTER_CNT2_STATE_START = 0x00000001, 1356 PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002, 1357 PERFCOUNTER_CNT2_STATE_HW = 0x00000003, 1358 } PERFCOUNTER_CNT2_STATE; 1359 1360 /* 1361 * PERFCOUNTER_STATE_SEL2 enum 1362 */ 1363 1364 typedef enum PERFCOUNTER_STATE_SEL2 { 1365 PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000, 1366 PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001, 1367 } PERFCOUNTER_STATE_SEL2; 1368 1369 /* 1370 * PERFCOUNTER_CNT3_STATE enum 1371 */ 1372 1373 typedef enum PERFCOUNTER_CNT3_STATE { 1374 PERFCOUNTER_CNT3_STATE_RESET = 0x00000000, 1375 PERFCOUNTER_CNT3_STATE_START = 0x00000001, 1376 PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002, 1377 PERFCOUNTER_CNT3_STATE_HW = 0x00000003, 1378 } PERFCOUNTER_CNT3_STATE; 1379 1380 /* 1381 * PERFCOUNTER_STATE_SEL3 enum 1382 */ 1383 1384 typedef enum PERFCOUNTER_STATE_SEL3 { 1385 PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000, 1386 PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001, 1387 } PERFCOUNTER_STATE_SEL3; 1388 1389 /* 1390 * PERFCOUNTER_CNT4_STATE enum 1391 */ 1392 1393 typedef enum PERFCOUNTER_CNT4_STATE { 1394 PERFCOUNTER_CNT4_STATE_RESET = 0x00000000, 1395 PERFCOUNTER_CNT4_STATE_START = 0x00000001, 1396 PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002, 1397 PERFCOUNTER_CNT4_STATE_HW = 0x00000003, 1398 } PERFCOUNTER_CNT4_STATE; 1399 1400 /* 1401 * PERFCOUNTER_STATE_SEL4 enum 1402 */ 1403 1404 typedef enum PERFCOUNTER_STATE_SEL4 { 1405 PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000, 1406 PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001, 1407 } PERFCOUNTER_STATE_SEL4; 1408 1409 /* 1410 * PERFCOUNTER_CNT5_STATE enum 1411 */ 1412 1413 typedef enum PERFCOUNTER_CNT5_STATE { 1414 PERFCOUNTER_CNT5_STATE_RESET = 0x00000000, 1415 PERFCOUNTER_CNT5_STATE_START = 0x00000001, 1416 PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002, 1417 PERFCOUNTER_CNT5_STATE_HW = 0x00000003, 1418 } PERFCOUNTER_CNT5_STATE; 1419 1420 /* 1421 * PERFCOUNTER_STATE_SEL5 enum 1422 */ 1423 1424 typedef enum PERFCOUNTER_STATE_SEL5 { 1425 PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000, 1426 PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001, 1427 } PERFCOUNTER_STATE_SEL5; 1428 1429 /* 1430 * PERFCOUNTER_CNT6_STATE enum 1431 */ 1432 1433 typedef enum PERFCOUNTER_CNT6_STATE { 1434 PERFCOUNTER_CNT6_STATE_RESET = 0x00000000, 1435 PERFCOUNTER_CNT6_STATE_START = 0x00000001, 1436 PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002, 1437 PERFCOUNTER_CNT6_STATE_HW = 0x00000003, 1438 } PERFCOUNTER_CNT6_STATE; 1439 1440 /* 1441 * PERFCOUNTER_STATE_SEL6 enum 1442 */ 1443 1444 typedef enum PERFCOUNTER_STATE_SEL6 { 1445 PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000, 1446 PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001, 1447 } PERFCOUNTER_STATE_SEL6; 1448 1449 /* 1450 * PERFCOUNTER_CNT7_STATE enum 1451 */ 1452 1453 typedef enum PERFCOUNTER_CNT7_STATE { 1454 PERFCOUNTER_CNT7_STATE_RESET = 0x00000000, 1455 PERFCOUNTER_CNT7_STATE_START = 0x00000001, 1456 PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002, 1457 PERFCOUNTER_CNT7_STATE_HW = 0x00000003, 1458 } PERFCOUNTER_CNT7_STATE; 1459 1460 /* 1461 * PERFCOUNTER_STATE_SEL7 enum 1462 */ 1463 1464 typedef enum PERFCOUNTER_STATE_SEL7 { 1465 PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000, 1466 PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001, 1467 } PERFCOUNTER_STATE_SEL7; 1468 1469 /* 1470 * PERFMON_STATE enum 1471 */ 1472 1473 typedef enum PERFMON_STATE { 1474 PERFMON_STATE_RESET = 0x00000000, 1475 PERFMON_STATE_START = 0x00000001, 1476 PERFMON_STATE_FREEZE = 0x00000002, 1477 PERFMON_STATE_HW = 0x00000003, 1478 } PERFMON_STATE; 1479 1480 /* 1481 * PERFMON_CNTOFF_AND_OR enum 1482 */ 1483 1484 typedef enum PERFMON_CNTOFF_AND_OR { 1485 PERFMON_CNTOFF_OR = 0x00000000, 1486 PERFMON_CNTOFF_AND = 0x00000001, 1487 } PERFMON_CNTOFF_AND_OR; 1488 1489 /* 1490 * PERFMON_CNTOFF_INT_EN enum 1491 */ 1492 1493 typedef enum PERFMON_CNTOFF_INT_EN { 1494 PERFMON_CNTOFF_INT_DISABLE = 0x00000000, 1495 PERFMON_CNTOFF_INT_ENABLE = 0x00000001, 1496 } PERFMON_CNTOFF_INT_EN; 1497 1498 /* 1499 * PERFMON_CNTOFF_INT_TYPE enum 1500 */ 1501 1502 typedef enum PERFMON_CNTOFF_INT_TYPE { 1503 PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000, 1504 PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001, 1505 } PERFMON_CNTOFF_INT_TYPE; 1506 1507 /******************************************************* 1508 * HUBP Enums 1509 *******************************************************/ 1510 1511 /* 1512 * ROTATION_ANGLE enum 1513 */ 1514 1515 typedef enum ROTATION_ANGLE { 1516 ROTATE_0_DEGREES = 0x00000000, 1517 ROTATE_90_DEGREES = 0x00000001, 1518 ROTATE_180_DEGREES = 0x00000002, 1519 ROTATE_270_DEGREES = 0x00000003, 1520 } ROTATION_ANGLE; 1521 1522 /* 1523 * H_MIRROR_EN enum 1524 */ 1525 1526 typedef enum H_MIRROR_EN { 1527 HW_MIRRORING_DISABLE = 0x00000000, 1528 HW_MIRRORING_ENABLE = 0x00000001, 1529 } H_MIRROR_EN; 1530 1531 /* 1532 * NUM_PIPES enum 1533 */ 1534 1535 typedef enum NUM_PIPES { 1536 ONE_PIPE = 0x00000000, 1537 TWO_PIPES = 0x00000001, 1538 FOUR_PIPES = 0x00000002, 1539 EIGHT_PIPES = 0x00000003, 1540 SIXTEEN_PIPES = 0x00000004, 1541 THIRTY_TWO_PIPES = 0x00000005, 1542 SIXTY_FOUR_PIPES = 0x00000006, 1543 } NUM_PIPES; 1544 1545 /* 1546 * NUM_BANKS enum 1547 */ 1548 1549 typedef enum NUM_BANKS { 1550 ONE_BANK = 0x00000000, 1551 TWO_BANKS = 0x00000001, 1552 FOUR_BANKS = 0x00000002, 1553 EIGHT_BANKS = 0x00000003, 1554 SIXTEEN_BANKS = 0x00000004, 1555 } NUM_BANKS; 1556 1557 /* 1558 * SW_MODE enum 1559 */ 1560 1561 typedef enum SW_MODE { 1562 SWIZZLE_LINEAR = 0x00000000, 1563 SWIZZLE_4KB_S = 0x00000005, 1564 SWIZZLE_4KB_D = 0x00000006, 1565 SWIZZLE_64KB_S = 0x00000009, 1566 SWIZZLE_64KB_D = 0x0000000a, 1567 SWIZZLE_VAR_S = 0x0000000d, 1568 SWIZZLE_VAR_D = 0x0000000e, 1569 SWIZZLE_64KB_S_T = 0x00000011, 1570 SWIZZLE_64KB_D_T = 0x00000012, 1571 SWIZZLE_4KB_S_X = 0x00000015, 1572 SWIZZLE_4KB_D_X = 0x00000016, 1573 SWIZZLE_64KB_S_X = 0x00000019, 1574 SWIZZLE_64KB_D_X = 0x0000001a, 1575 SWIZZLE_64KB_R_X = 0x0000001b, 1576 SWIZZLE_VAR_S_X = 0x0000001d, 1577 SWIZZLE_VAR_D_X = 0x0000001e, 1578 } SW_MODE; 1579 1580 /* 1581 * PIPE_INTERLEAVE enum 1582 */ 1583 1584 typedef enum PIPE_INTERLEAVE { 1585 PIPE_INTERLEAVE_256B = 0x00000000, 1586 PIPE_INTERLEAVE_512B = 0x00000001, 1587 PIPE_INTERLEAVE_1KB = 0x00000002, 1588 } PIPE_INTERLEAVE; 1589 1590 /* 1591 * LEGACY_PIPE_INTERLEAVE enum 1592 */ 1593 1594 typedef enum LEGACY_PIPE_INTERLEAVE { 1595 LEGACY_PIPE_INTERLEAVE_256B = 0x00000000, 1596 LEGACY_PIPE_INTERLEAVE_512B = 0x00000001, 1597 } LEGACY_PIPE_INTERLEAVE; 1598 1599 /* 1600 * NUM_SE enum 1601 */ 1602 1603 typedef enum NUM_SE { 1604 ONE_SHADER_ENGIN = 0x00000000, 1605 TWO_SHADER_ENGINS = 0x00000001, 1606 FOUR_SHADER_ENGINS = 0x00000002, 1607 EIGHT_SHADER_ENGINS = 0x00000003, 1608 } NUM_SE; 1609 1610 /* 1611 * NUM_RB_PER_SE enum 1612 */ 1613 1614 typedef enum NUM_RB_PER_SE { 1615 ONE_RB_PER_SE = 0x00000000, 1616 TWO_RB_PER_SE = 0x00000001, 1617 FOUR_RB_PER_SE = 0x00000002, 1618 } NUM_RB_PER_SE; 1619 1620 /* 1621 * MAX_COMPRESSED_FRAGS enum 1622 */ 1623 1624 typedef enum MAX_COMPRESSED_FRAGS { 1625 ONE_FRAGMENT = 0x00000000, 1626 TWO_FRAGMENTS = 0x00000001, 1627 FOUR_FRAGMENTS = 0x00000002, 1628 EIGHT_FRAGMENTS = 0x00000003, 1629 } MAX_COMPRESSED_FRAGS; 1630 1631 /* 1632 * DIM_TYPE enum 1633 */ 1634 1635 typedef enum DIM_TYPE { 1636 DIM_TYPE_1D = 0x00000000, 1637 DIM_TYPE_2D = 0x00000001, 1638 DIM_TYPE_3D = 0x00000002, 1639 DIM_TYPE_RESERVED = 0x00000003, 1640 } DIM_TYPE; 1641 1642 /* 1643 * META_LINEAR enum 1644 */ 1645 1646 typedef enum META_LINEAR { 1647 META_SURF_TILED = 0x00000000, 1648 META_SURF_LINEAR = 0x00000001, 1649 } META_LINEAR; 1650 1651 /* 1652 * RB_ALIGNED enum 1653 */ 1654 1655 typedef enum RB_ALIGNED { 1656 RB_UNALIGNED_META_SURF = 0x00000000, 1657 RB_ALIGNED_META_SURF = 0x00000001, 1658 } RB_ALIGNED; 1659 1660 /* 1661 * PIPE_ALIGNED enum 1662 */ 1663 1664 typedef enum PIPE_ALIGNED { 1665 PIPE_UNALIGNED_SURF = 0x00000000, 1666 PIPE_ALIGNED_SURF = 0x00000001, 1667 } PIPE_ALIGNED; 1668 1669 /* 1670 * ARRAY_MODE enum 1671 */ 1672 1673 typedef enum ARRAY_MODE { 1674 AM_LINEAR_GENERAL = 0x00000000, 1675 AM_LINEAR_ALIGNED = 0x00000001, 1676 AM_1D_TILED_THIN1 = 0x00000002, 1677 AM_1D_TILED_THICK = 0x00000003, 1678 AM_2D_TILED_THIN1 = 0x00000004, 1679 AM_PRT_TILED_THIN1 = 0x00000005, 1680 AM_PRT_2D_TILED_THIN1 = 0x00000006, 1681 AM_2D_TILED_THICK = 0x00000007, 1682 AM_2D_TILED_XTHICK = 0x00000008, 1683 AM_PRT_TILED_THICK = 0x00000009, 1684 AM_PRT_2D_TILED_THICK = 0x0000000a, 1685 AM_PRT_3D_TILED_THIN1 = 0x0000000b, 1686 AM_3D_TILED_THIN1 = 0x0000000c, 1687 AM_3D_TILED_THICK = 0x0000000d, 1688 AM_3D_TILED_XTHICK = 0x0000000e, 1689 AM_PRT_3D_TILED_THICK = 0x0000000f, 1690 } ARRAY_MODE; 1691 1692 /* 1693 * PIPE_CONFIG enum 1694 */ 1695 1696 typedef enum PIPE_CONFIG { 1697 P2 = 0x00000000, 1698 P4_8x16 = 0x00000004, 1699 P4_16x16 = 0x00000005, 1700 P4_16x32 = 0x00000006, 1701 P4_32x32 = 0x00000007, 1702 P8_16x16_8x16 = 0x00000008, 1703 P8_16x32_8x16 = 0x00000009, 1704 P8_32x32_8x16 = 0x0000000a, 1705 P8_16x32_16x16 = 0x0000000b, 1706 P8_32x32_16x16 = 0x0000000c, 1707 P8_32x32_16x32 = 0x0000000d, 1708 P8_32x64_32x32 = 0x0000000e, 1709 P16_32x32_8x16 = 0x00000010, 1710 P16_32x32_16x16 = 0x00000011, 1711 P16_ADDR_SURF = 0x00000012, 1712 } PIPE_CONFIG; 1713 1714 /* 1715 * MICRO_TILE_MODE_NEW enum 1716 */ 1717 1718 typedef enum MICRO_TILE_MODE_NEW { 1719 DISPLAY_MICRO_TILING = 0x00000000, 1720 THIN_MICRO_TILING = 0x00000001, 1721 DEPTH_MICRO_TILING = 0x00000002, 1722 ROTATED_MICRO_TILING = 0x00000003, 1723 THICK_MICRO_TILING = 0x00000004, 1724 } MICRO_TILE_MODE_NEW; 1725 1726 /* 1727 * TILE_SPLIT enum 1728 */ 1729 1730 typedef enum TILE_SPLIT { 1731 SURF_TILE_SPLIT_64B = 0x00000000, 1732 SURF_TILE_SPLIT_128B = 0x00000001, 1733 SURF_TILE_SPLIT_256B = 0x00000002, 1734 SURF_TILE_SPLIT_512B = 0x00000003, 1735 SURF_TILE_SPLIT_1KB = 0x00000004, 1736 SURF_TILE_SPLIT_2KB = 0x00000005, 1737 SURF_TILE_SPLIT_4KB = 0x00000006, 1738 } TILE_SPLIT; 1739 1740 /* 1741 * BANK_WIDTH enum 1742 */ 1743 1744 typedef enum BANK_WIDTH { 1745 SURF_BANK_WIDTH_1 = 0x00000000, 1746 SURF_BANK_WIDTH_2 = 0x00000001, 1747 SURF_BANK_WIDTH_4 = 0x00000002, 1748 SURF_BANK_WIDTH_8 = 0x00000003, 1749 } BANK_WIDTH; 1750 1751 /* 1752 * BANK_HEIGHT enum 1753 */ 1754 1755 typedef enum BANK_HEIGHT { 1756 SURF_BANK_HEIGHT_1 = 0x00000000, 1757 SURF_BANK_HEIGHT_2 = 0x00000001, 1758 SURF_BANK_HEIGHT_4 = 0x00000002, 1759 SURF_BANK_HEIGHT_8 = 0x00000003, 1760 } BANK_HEIGHT; 1761 1762 /* 1763 * MACRO_TILE_ASPECT enum 1764 */ 1765 1766 typedef enum MACRO_TILE_ASPECT { 1767 SURF_MACRO_ASPECT_1 = 0x00000000, 1768 SURF_MACRO_ASPECT_2 = 0x00000001, 1769 SURF_MACRO_ASPECT_4 = 0x00000002, 1770 SURF_MACRO_ASPECT_8 = 0x00000003, 1771 } MACRO_TILE_ASPECT; 1772 1773 /* 1774 * LEGACY_NUM_BANKS enum 1775 */ 1776 1777 typedef enum LEGACY_NUM_BANKS { 1778 SURF_2_BANK = 0x00000000, 1779 SURF_4_BANK = 0x00000001, 1780 SURF_8_BANK = 0x00000002, 1781 SURF_16_BANK = 0x00000003, 1782 } LEGACY_NUM_BANKS; 1783 1784 /* 1785 * SWATH_HEIGHT enum 1786 */ 1787 1788 typedef enum SWATH_HEIGHT { 1789 SWATH_HEIGHT_1L = 0x00000000, 1790 SWATH_HEIGHT_2L = 0x00000001, 1791 SWATH_HEIGHT_4L = 0x00000002, 1792 SWATH_HEIGHT_8L = 0x00000003, 1793 SWATH_HEIGHT_16L = 0x00000004, 1794 } SWATH_HEIGHT; 1795 1796 /* 1797 * PTE_ROW_HEIGHT_LINEAR enum 1798 */ 1799 1800 typedef enum PTE_ROW_HEIGHT_LINEAR { 1801 PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000, 1802 PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001, 1803 PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002, 1804 PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003, 1805 PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004, 1806 PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005, 1807 PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006, 1808 PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007, 1809 } PTE_ROW_HEIGHT_LINEAR; 1810 1811 /* 1812 * CHUNK_SIZE enum 1813 */ 1814 1815 typedef enum CHUNK_SIZE { 1816 CHUNK_SIZE_1KB = 0x00000000, 1817 CHUNK_SIZE_2KB = 0x00000001, 1818 CHUNK_SIZE_4KB = 0x00000002, 1819 CHUNK_SIZE_8KB = 0x00000003, 1820 CHUNK_SIZE_16KB = 0x00000004, 1821 CHUNK_SIZE_32KB = 0x00000005, 1822 CHUNK_SIZE_64KB = 0x00000006, 1823 } CHUNK_SIZE; 1824 1825 /* 1826 * MIN_CHUNK_SIZE enum 1827 */ 1828 1829 typedef enum MIN_CHUNK_SIZE { 1830 NO_MIN_CHUNK_SIZE = 0x00000000, 1831 MIN_CHUNK_SIZE_256B = 0x00000001, 1832 MIN_CHUNK_SIZE_512B = 0x00000002, 1833 MIN_CHUNK_SIZE_1024B = 0x00000003, 1834 } MIN_CHUNK_SIZE; 1835 1836 /* 1837 * META_CHUNK_SIZE enum 1838 */ 1839 1840 typedef enum META_CHUNK_SIZE { 1841 META_CHUNK_SIZE_1KB = 0x00000000, 1842 META_CHUNK_SIZE_2KB = 0x00000001, 1843 META_CHUNK_SIZE_4KB = 0x00000002, 1844 META_CHUNK_SIZE_8KB = 0x00000003, 1845 } META_CHUNK_SIZE; 1846 1847 /* 1848 * MIN_META_CHUNK_SIZE enum 1849 */ 1850 1851 typedef enum MIN_META_CHUNK_SIZE { 1852 NO_MIN_META_CHUNK_SIZE = 0x00000000, 1853 MIN_META_CHUNK_SIZE_64B = 0x00000001, 1854 MIN_META_CHUNK_SIZE_128B = 0x00000002, 1855 MIN_META_CHUNK_SIZE_256B = 0x00000003, 1856 } MIN_META_CHUNK_SIZE; 1857 1858 /* 1859 * DPTE_GROUP_SIZE enum 1860 */ 1861 1862 typedef enum DPTE_GROUP_SIZE { 1863 DPTE_GROUP_SIZE_64B = 0x00000000, 1864 DPTE_GROUP_SIZE_128B = 0x00000001, 1865 DPTE_GROUP_SIZE_256B = 0x00000002, 1866 DPTE_GROUP_SIZE_512B = 0x00000003, 1867 DPTE_GROUP_SIZE_1024B = 0x00000004, 1868 DPTE_GROUP_SIZE_2048B = 0x00000005, 1869 DPTE_GROUP_SIZE_4096B = 0x00000006, 1870 DPTE_GROUP_SIZE_8192B = 0x00000007, 1871 } DPTE_GROUP_SIZE; 1872 1873 /* 1874 * MPTE_GROUP_SIZE enum 1875 */ 1876 1877 typedef enum MPTE_GROUP_SIZE { 1878 MPTE_GROUP_SIZE_64B = 0x00000000, 1879 MPTE_GROUP_SIZE_128B = 0x00000001, 1880 MPTE_GROUP_SIZE_256B = 0x00000002, 1881 MPTE_GROUP_SIZE_512B = 0x00000003, 1882 MPTE_GROUP_SIZE_1024B = 0x00000004, 1883 MPTE_GROUP_SIZE_2048B = 0x00000005, 1884 MPTE_GROUP_SIZE_4096B = 0x00000006, 1885 MPTE_GROUP_SIZE_8192B = 0x00000007, 1886 } MPTE_GROUP_SIZE; 1887 1888 /* 1889 * HUBP_BLANK_EN enum 1890 */ 1891 1892 typedef enum HUBP_BLANK_EN { 1893 HUBP_BLANK_SW_DEASSERT = 0x00000000, 1894 HUBP_BLANK_SW_ASSERT = 0x00000001, 1895 } HUBP_BLANK_EN; 1896 1897 /* 1898 * HUBP_DISABLE enum 1899 */ 1900 1901 typedef enum HUBP_DISABLE { 1902 HUBP_ENABLED = 0x00000000, 1903 HUBP_DISABLED = 0x00000001, 1904 } HUBP_DISABLE; 1905 1906 /* 1907 * HUBP_TTU_DISABLE enum 1908 */ 1909 1910 typedef enum HUBP_TTU_DISABLE { 1911 HUBP_TTU_ENABLED = 0x00000000, 1912 HUBP_TTU_DISABLED = 0x00000001, 1913 } HUBP_TTU_DISABLE; 1914 1915 /* 1916 * HUBP_NO_OUTSTANDING_REQ enum 1917 */ 1918 1919 typedef enum HUBP_NO_OUTSTANDING_REQ { 1920 OUTSTANDING_REQ = 0x00000000, 1921 NO_OUTSTANDING_REQ = 0x00000001, 1922 } HUBP_NO_OUTSTANDING_REQ; 1923 1924 /* 1925 * HUBP_IN_BLANK enum 1926 */ 1927 1928 typedef enum HUBP_IN_BLANK { 1929 HUBP_IN_ACTIVE = 0x00000000, 1930 HUBP_IN_VBLANK = 0x00000001, 1931 } HUBP_IN_BLANK; 1932 1933 /* 1934 * HUBP_VTG_SEL enum 1935 */ 1936 1937 typedef enum HUBP_VTG_SEL { 1938 VTG_SEL_0 = 0x00000000, 1939 VTG_SEL_1 = 0x00000001, 1940 VTG_SEL_2 = 0x00000002, 1941 VTG_SEL_3 = 0x00000003, 1942 VTG_SEL_4 = 0x00000004, 1943 VTG_SEL_5 = 0x00000005, 1944 } HUBP_VTG_SEL; 1945 1946 /* 1947 * HUBP_VREADY_AT_OR_AFTER_VSYNC enum 1948 */ 1949 1950 typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC { 1951 VREADY_BEFORE_VSYNC = 0x00000000, 1952 VREADY_AT_OR_AFTER_VSYNC = 0x00000001, 1953 } HUBP_VREADY_AT_OR_AFTER_VSYNC; 1954 1955 /* 1956 * VMPG_SIZE enum 1957 */ 1958 1959 typedef enum VMPG_SIZE { 1960 VMPG_SIZE_4KB = 0x00000000, 1961 VMPG_SIZE_64KB = 0x00000001, 1962 } VMPG_SIZE; 1963 1964 /* 1965 * HUBP_MEASURE_WIN_MODE_DCFCLK enum 1966 */ 1967 1968 typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK { 1969 HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000, 1970 HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001, 1971 HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002, 1972 HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003, 1973 } HUBP_MEASURE_WIN_MODE_DCFCLK; 1974 1975 /******************************************************* 1976 * HUBPREQ Enums 1977 *******************************************************/ 1978 1979 /* 1980 * SURFACE_TMZ enum 1981 */ 1982 1983 typedef enum SURFACE_TMZ { 1984 SURFACE_IS_NOT_TMZ = 0x00000000, 1985 SURFACE_IS_TMZ = 0x00000001, 1986 } SURFACE_TMZ; 1987 1988 /* 1989 * SURFACE_DCC enum 1990 */ 1991 1992 typedef enum SURFACE_DCC { 1993 SURFACE_IS_NOT_DCC = 0x00000000, 1994 SURFACE_IS_DCC = 0x00000001, 1995 } SURFACE_DCC; 1996 1997 /* 1998 * SURFACE_DCC_IND_64B enum 1999 */ 2000 2001 typedef enum SURFACE_DCC_IND_64B { 2002 SURFACE_DCC_IS_NOT_IND_64B = 0x00000000, 2003 SURFACE_DCC_IS_IND_64B = 0x00000001, 2004 } SURFACE_DCC_IND_64B; 2005 2006 /* 2007 * SURFACE_FLIP_TYPE enum 2008 */ 2009 2010 typedef enum SURFACE_FLIP_TYPE { 2011 SURFACE_V_FLIP = 0x00000000, 2012 SURFACE_I_FLIP = 0x00000001, 2013 } SURFACE_FLIP_TYPE; 2014 2015 /* 2016 * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum 2017 */ 2018 2019 typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC { 2020 FLIP_ANY_FRAME = 0x00000000, 2021 FLIP_LEFT_EYE = 0x00000001, 2022 FLIP_RIGHT_EYE = 0x00000002, 2023 SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003, 2024 } SURFACE_FLIP_MODE_FOR_STEREOSYNC; 2025 2026 /* 2027 * SURFACE_UPDATE_LOCK enum 2028 */ 2029 2030 typedef enum SURFACE_UPDATE_LOCK { 2031 SURFACE_UPDATE_IS_UNLOCKED = 0x00000000, 2032 SURFACE_UPDATE_IS_LOCKED = 0x00000001, 2033 } SURFACE_UPDATE_LOCK; 2034 2035 /* 2036 * SURFACE_FLIP_IN_STEREOSYNC enum 2037 */ 2038 2039 typedef enum SURFACE_FLIP_IN_STEREOSYNC { 2040 SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000, 2041 SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001, 2042 } SURFACE_FLIP_IN_STEREOSYNC; 2043 2044 /* 2045 * SURFACE_FLIP_STEREO_SELECT_DISABLE enum 2046 */ 2047 2048 typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE { 2049 SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000, 2050 SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001, 2051 } SURFACE_FLIP_STEREO_SELECT_DISABLE; 2052 2053 /* 2054 * SURFACE_FLIP_STEREO_SELECT_POLARITY enum 2055 */ 2056 2057 typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY { 2058 SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000, 2059 SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001, 2060 } SURFACE_FLIP_STEREO_SELECT_POLARITY; 2061 2062 /* 2063 * SURFACE_INUSE_RAED_NO_LATCH enum 2064 */ 2065 2066 typedef enum SURFACE_INUSE_RAED_NO_LATCH { 2067 SURFACE_INUSE_IS_LATCHED = 0x00000000, 2068 SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001, 2069 } SURFACE_INUSE_RAED_NO_LATCH; 2070 2071 /* 2072 * INT_MASK enum 2073 */ 2074 2075 typedef enum INT_MASK { 2076 INT_DISABLED = 0x00000000, 2077 INT_ENABLED = 0x00000001, 2078 } INT_MASK; 2079 2080 /* 2081 * SURFACE_FLIP_INT_TYPE enum 2082 */ 2083 2084 typedef enum SURFACE_FLIP_INT_TYPE { 2085 SURFACE_FLIP_INT_LEVEL = 0x00000000, 2086 SURFACE_FLIP_INT_PULSE = 0x00000001, 2087 } SURFACE_FLIP_INT_TYPE; 2088 2089 /* 2090 * SURFACE_FLIP_AWAY_INT_TYPE enum 2091 */ 2092 2093 typedef enum SURFACE_FLIP_AWAY_INT_TYPE { 2094 SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000, 2095 SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001, 2096 } SURFACE_FLIP_AWAY_INT_TYPE; 2097 2098 /* 2099 * SURFACE_FLIP_VUPDATE_SKIP_NUM enum 2100 */ 2101 2102 typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM { 2103 SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000, 2104 SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001, 2105 SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002, 2106 SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003, 2107 SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004, 2108 SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005, 2109 SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006, 2110 SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007, 2111 SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008, 2112 SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009, 2113 SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a, 2114 SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b, 2115 SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c, 2116 SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d, 2117 SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e, 2118 SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f, 2119 } SURFACE_FLIP_VUPDATE_SKIP_NUM; 2120 2121 /* 2122 * DFQ_SIZE enum 2123 */ 2124 2125 typedef enum DFQ_SIZE { 2126 DFQ_SIZE_0 = 0x00000000, 2127 DFQ_SIZE_1 = 0x00000001, 2128 DFQ_SIZE_2 = 0x00000002, 2129 DFQ_SIZE_3 = 0x00000003, 2130 DFQ_SIZE_4 = 0x00000004, 2131 DFQ_SIZE_5 = 0x00000005, 2132 DFQ_SIZE_6 = 0x00000006, 2133 DFQ_SIZE_7 = 0x00000007, 2134 } DFQ_SIZE; 2135 2136 /* 2137 * DFQ_MIN_FREE_ENTRIES enum 2138 */ 2139 2140 typedef enum DFQ_MIN_FREE_ENTRIES { 2141 DFQ_MIN_FREE_ENTRIES_0 = 0x00000000, 2142 DFQ_MIN_FREE_ENTRIES_1 = 0x00000001, 2143 DFQ_MIN_FREE_ENTRIES_2 = 0x00000002, 2144 DFQ_MIN_FREE_ENTRIES_3 = 0x00000003, 2145 DFQ_MIN_FREE_ENTRIES_4 = 0x00000004, 2146 DFQ_MIN_FREE_ENTRIES_5 = 0x00000005, 2147 DFQ_MIN_FREE_ENTRIES_6 = 0x00000006, 2148 DFQ_MIN_FREE_ENTRIES_7 = 0x00000007, 2149 } DFQ_MIN_FREE_ENTRIES; 2150 2151 /* 2152 * DFQ_NUM_ENTRIES enum 2153 */ 2154 2155 typedef enum DFQ_NUM_ENTRIES { 2156 DFQ_NUM_ENTRIES_0 = 0x00000000, 2157 DFQ_NUM_ENTRIES_1 = 0x00000001, 2158 DFQ_NUM_ENTRIES_2 = 0x00000002, 2159 DFQ_NUM_ENTRIES_3 = 0x00000003, 2160 DFQ_NUM_ENTRIES_4 = 0x00000004, 2161 DFQ_NUM_ENTRIES_5 = 0x00000005, 2162 DFQ_NUM_ENTRIES_6 = 0x00000006, 2163 DFQ_NUM_ENTRIES_7 = 0x00000007, 2164 DFQ_NUM_ENTRIES_8 = 0x00000008, 2165 } DFQ_NUM_ENTRIES; 2166 2167 /* 2168 * FLIP_RATE enum 2169 */ 2170 2171 typedef enum FLIP_RATE { 2172 FLIP_RATE_0 = 0x00000000, 2173 FLIP_RATE_1 = 0x00000001, 2174 FLIP_RATE_2 = 0x00000002, 2175 FLIP_RATE_3 = 0x00000003, 2176 FLIP_RATE_4 = 0x00000004, 2177 FLIP_RATE_5 = 0x00000005, 2178 FLIP_RATE_6 = 0x00000006, 2179 FLIP_RATE_7 = 0x00000007, 2180 } FLIP_RATE; 2181 2182 /******************************************************* 2183 * HUBPRET Enums 2184 *******************************************************/ 2185 2186 /* 2187 * DETILE_BUFFER_PACKER_ENABLE enum 2188 */ 2189 2190 typedef enum DETILE_BUFFER_PACKER_ENABLE { 2191 DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000, 2192 DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001, 2193 } DETILE_BUFFER_PACKER_ENABLE; 2194 2195 /* 2196 * CROSSBAR_FOR_ALPHA enum 2197 */ 2198 2199 typedef enum CROSSBAR_FOR_ALPHA { 2200 ALPHA_DATA_ON_ALPHA_PORT = 0x00000000, 2201 ALPHA_DATA_ON_Y_G_PORT = 0x00000001, 2202 ALPHA_DATA_ON_CB_B_PORT = 0x00000002, 2203 ALPHA_DATA_ON_CR_R_PORT = 0x00000003, 2204 } CROSSBAR_FOR_ALPHA; 2205 2206 /* 2207 * CROSSBAR_FOR_Y_G enum 2208 */ 2209 2210 typedef enum CROSSBAR_FOR_Y_G { 2211 Y_G_DATA_ON_ALPHA_PORT = 0x00000000, 2212 Y_G_DATA_ON_Y_G_PORT = 0x00000001, 2213 Y_G_DATA_ON_CB_B_PORT = 0x00000002, 2214 Y_G_DATA_ON_CR_R_PORT = 0x00000003, 2215 } CROSSBAR_FOR_Y_G; 2216 2217 /* 2218 * CROSSBAR_FOR_CB_B enum 2219 */ 2220 2221 typedef enum CROSSBAR_FOR_CB_B { 2222 CB_B_DATA_ON_ALPHA_PORT = 0x00000000, 2223 CB_B_DATA_ON_Y_G_PORT = 0x00000001, 2224 CB_B_DATA_ON_CB_B_PORT = 0x00000002, 2225 CB_B_DATA_ON_CR_R_PORT = 0x00000003, 2226 } CROSSBAR_FOR_CB_B; 2227 2228 /* 2229 * CROSSBAR_FOR_CR_R enum 2230 */ 2231 2232 typedef enum CROSSBAR_FOR_CR_R { 2233 CR_R_DATA_ON_ALPHA_PORT = 0x00000000, 2234 CR_R_DATA_ON_Y_G_PORT = 0x00000001, 2235 CR_R_DATA_ON_CB_B_PORT = 0x00000002, 2236 CR_R_DATA_ON_CR_R_PORT = 0x00000003, 2237 } CROSSBAR_FOR_CR_R; 2238 2239 /* 2240 * DET_MEM_PWR_LIGHT_SLEEP_MODE enum 2241 */ 2242 2243 typedef enum DET_MEM_PWR_LIGHT_SLEEP_MODE { 2244 DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, 2245 DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, 2246 DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, 2247 } DET_MEM_PWR_LIGHT_SLEEP_MODE; 2248 2249 /* 2250 * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum 2251 */ 2252 2253 typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE { 2254 PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, 2255 PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, 2256 } PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE; 2257 2258 /******************************************************* 2259 * CURSOR Enums 2260 *******************************************************/ 2261 2262 /* 2263 * CURSOR_ENABLE enum 2264 */ 2265 2266 typedef enum CURSOR_ENABLE { 2267 CURSOR_IS_DISABLE = 0x00000000, 2268 CURSOR_IS_ENABLE = 0x00000001, 2269 } CURSOR_ENABLE; 2270 2271 /* 2272 * CURSOR_2X_MAGNIFY enum 2273 */ 2274 2275 typedef enum CURSOR_2X_MAGNIFY { 2276 CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000, 2277 CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001, 2278 } CURSOR_2X_MAGNIFY; 2279 2280 /* 2281 * CURSOR_MODE enum 2282 */ 2283 2284 typedef enum CURSOR_MODE { 2285 CURSOR_MONO_2BIT = 0x00000000, 2286 CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001, 2287 CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, 2288 CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, 2289 CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004, 2290 CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005, 2291 } CURSOR_MODE; 2292 2293 /* 2294 * CURSOR_SURFACE_TMZ enum 2295 */ 2296 2297 typedef enum CURSOR_SURFACE_TMZ { 2298 CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000, 2299 CURSOR_SURFACE_IS_TMZ = 0x00000001, 2300 } CURSOR_SURFACE_TMZ; 2301 2302 /* 2303 * CURSOR_SNOOP enum 2304 */ 2305 2306 typedef enum CURSOR_SNOOP { 2307 CURSOR_IS_NOT_SNOOP = 0x00000000, 2308 CURSOR_IS_SNOOP = 0x00000001, 2309 } CURSOR_SNOOP; 2310 2311 /* 2312 * CURSOR_SYSTEM enum 2313 */ 2314 2315 typedef enum CURSOR_SYSTEM { 2316 CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000, 2317 CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001, 2318 } CURSOR_SYSTEM; 2319 2320 /* 2321 * CURSOR_PITCH enum 2322 */ 2323 2324 typedef enum CURSOR_PITCH { 2325 CURSOR_PITCH_64_PIXELS = 0x00000000, 2326 CURSOR_PITCH_128_PIXELS = 0x00000001, 2327 CURSOR_PITCH_256_PIXELS = 0x00000002, 2328 } CURSOR_PITCH; 2329 2330 /* 2331 * CURSOR_LINES_PER_CHUNK enum 2332 */ 2333 2334 typedef enum CURSOR_LINES_PER_CHUNK { 2335 CURSOR_LINE_PER_CHUNK_1 = 0x00000000, 2336 CURSOR_LINE_PER_CHUNK_2 = 0x00000001, 2337 CURSOR_LINE_PER_CHUNK_4 = 0x00000002, 2338 CURSOR_LINE_PER_CHUNK_8 = 0x00000003, 2339 CURSOR_LINE_PER_CHUNK_16 = 0x00000004, 2340 } CURSOR_LINES_PER_CHUNK; 2341 2342 /* 2343 * CURSOR_PERFMON_LATENCY_MEASURE_EN enum 2344 */ 2345 2346 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN { 2347 CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000, 2348 CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001, 2349 } CURSOR_PERFMON_LATENCY_MEASURE_EN; 2350 2351 /* 2352 * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum 2353 */ 2354 2355 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL { 2356 CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000, 2357 CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001, 2358 } CURSOR_PERFMON_LATENCY_MEASURE_SEL; 2359 2360 /* 2361 * CURSOR_STEREO_EN enum 2362 */ 2363 2364 typedef enum CURSOR_STEREO_EN { 2365 CURSOR_STEREO_IS_DISABLED = 0x00000000, 2366 CURSOR_STEREO_IS_ENABLED = 0x00000001, 2367 } CURSOR_STEREO_EN; 2368 2369 /* 2370 * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum 2371 */ 2372 2373 typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS { 2374 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000, 2375 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001, 2376 } CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS; 2377 2378 /* 2379 * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum 2380 */ 2381 2382 typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE { 2383 CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, 2384 CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, 2385 CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, 2386 } CROB_MEM_PWR_LIGHT_SLEEP_MODE; 2387 2388 /* 2389 * DMDATA_UPDATED enum 2390 */ 2391 2392 typedef enum DMDATA_UPDATED { 2393 DMDATA_NOT_UPDATED = 0x00000000, 2394 DMDATA_WAS_UPDATED = 0x00000001, 2395 } DMDATA_UPDATED; 2396 2397 /* 2398 * DMDATA_REPEAT enum 2399 */ 2400 2401 typedef enum DMDATA_REPEAT { 2402 DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000, 2403 DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001, 2404 } DMDATA_REPEAT; 2405 2406 /* 2407 * DMDATA_MODE enum 2408 */ 2409 2410 typedef enum DMDATA_MODE { 2411 DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000, 2412 DMDATA_HARDWARE_UPDATE_MODE = 0x00000001, 2413 } DMDATA_MODE; 2414 2415 /* 2416 * DMDATA_QOS_MODE enum 2417 */ 2418 2419 typedef enum DMDATA_QOS_MODE { 2420 DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000, 2421 DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001, 2422 } DMDATA_QOS_MODE; 2423 2424 /* 2425 * DMDATA_DONE enum 2426 */ 2427 2428 typedef enum DMDATA_DONE { 2429 DMDATA_NOT_SENT_TO_DIG = 0x00000000, 2430 DMDATA_SENT_TO_DIG = 0x00000001, 2431 } DMDATA_DONE; 2432 2433 /* 2434 * DMDATA_UNDERFLOW enum 2435 */ 2436 2437 typedef enum DMDATA_UNDERFLOW { 2438 DMDATA_NOT_UNDERFLOW = 0x00000000, 2439 DMDATA_UNDERFLOWED = 0x00000001, 2440 } DMDATA_UNDERFLOW; 2441 2442 /* 2443 * DMDATA_UNDERFLOW_CLEAR enum 2444 */ 2445 2446 typedef enum DMDATA_UNDERFLOW_CLEAR { 2447 DMDATA_DONT_CLEAR = 0x00000000, 2448 DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001, 2449 } DMDATA_UNDERFLOW_CLEAR; 2450 2451 /******************************************************* 2452 * HUBPXFC Enums 2453 *******************************************************/ 2454 2455 /* 2456 * HUBP_XFC_PIXEL_FORMAT_ENUM enum 2457 */ 2458 2459 typedef enum HUBP_XFC_PIXEL_FORMAT_ENUM { 2460 HUBP_XFC_PIXEL_IS_32BPP = 0x00000000, 2461 HUBP_XFC_PIXEL_IS_64BPP = 0x00000001, 2462 } HUBP_XFC_PIXEL_FORMAT_ENUM; 2463 2464 /* 2465 * HUBP_XFC_FRAME_MODE_ENUM enum 2466 */ 2467 2468 typedef enum HUBP_XFC_FRAME_MODE_ENUM { 2469 HUBP_XFC_PARTIAL_FRAME_MODE = 0x00000000, 2470 HUBP_XFC_FULL_FRAME_MODE = 0x00000001, 2471 } HUBP_XFC_FRAME_MODE_ENUM; 2472 2473 /* 2474 * HUBP_XFC_CHUNK_SIZE_ENUM enum 2475 */ 2476 2477 typedef enum HUBP_XFC_CHUNK_SIZE_ENUM { 2478 HUBP_XFC_CHUNK_SIZE_256B = 0x00000000, 2479 HUBP_XFC_CHUNK_SIZE_512B = 0x00000001, 2480 HUBP_XFC_CHUNK_SIZE_1KB = 0x00000002, 2481 HUBP_XFC_CHUNK_SIZE_2KB = 0x00000003, 2482 HUBP_XFC_CHUNK_SIZE_4KB = 0x00000004, 2483 HUBP_XFC_CHUNK_SIZE_8KB = 0x00000005, 2484 HUBP_XFC_CHUNK_SIZE_16KB = 0x00000006, 2485 HUBP_XFC_CHUNK_SIZE_32KB = 0x00000007, 2486 } HUBP_XFC_CHUNK_SIZE_ENUM; 2487 2488 /******************************************************* 2489 * XFC Enums 2490 *******************************************************/ 2491 2492 /* 2493 * MMHUBBUB_XFC_XFCMON_MODE_ENUM enum 2494 */ 2495 2496 typedef enum MMHUBBUB_XFC_XFCMON_MODE_ENUM { 2497 MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT = 0x00000000, 2498 MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS = 0x00000001, 2499 MMHUBBUB_XFC_XFCMON_MODE_PERIODS = 0x00000002, 2500 } MMHUBBUB_XFC_XFCMON_MODE_ENUM; 2501 2502 /* 2503 * MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM enum 2504 */ 2505 2506 typedef enum MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM { 2507 MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB = 0x00000000, 2508 MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB = 0x00000001, 2509 } MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM; 2510 2511 /******************************************************* 2512 * XFCP Enums 2513 *******************************************************/ 2514 2515 /* 2516 * MMHUBBUB_XFC_PIXEL_FORMAT_ENUM enum 2517 */ 2518 2519 typedef enum MMHUBBUB_XFC_PIXEL_FORMAT_ENUM { 2520 MMHUBBUB_XFC_PIXEL_IS_32BPP = 0x00000000, 2521 MMHUBBUB_XFC_PIXEL_IS_64BPP = 0x00000001, 2522 } MMHUBBUB_XFC_PIXEL_FORMAT_ENUM; 2523 2524 /* 2525 * MMHUBBUB_XFC_FRAME_MODE_ENUM enum 2526 */ 2527 2528 typedef enum MMHUBBUB_XFC_FRAME_MODE_ENUM { 2529 MMHUBBUB_XFC_PARTIAL_FRAME_MODE = 0x00000000, 2530 MMHUBBUB_XFC_FULL_FRAME_MODE = 0x00000001, 2531 } MMHUBBUB_XFC_FRAME_MODE_ENUM; 2532 2533 /******************************************************* 2534 * MPC_CFG Enums 2535 *******************************************************/ 2536 2537 /* 2538 * MPC_CFG_MPC_TEST_CLK_SEL enum 2539 */ 2540 2541 typedef enum MPC_CFG_MPC_TEST_CLK_SEL { 2542 MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000, 2543 MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001, 2544 MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002, 2545 MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003, 2546 } MPC_CFG_MPC_TEST_CLK_SEL; 2547 2548 /* 2549 * MPC_CRC_CALC_MODE enum 2550 */ 2551 2552 typedef enum MPC_CRC_CALC_MODE { 2553 MPC_CRC_ONE_SHOT_MODE = 0x00000000, 2554 MPC_CRC_CONTINUOUS_MODE = 0x00000001, 2555 } MPC_CRC_CALC_MODE; 2556 2557 /* 2558 * MPC_CRC_CALC_STEREO_MODE enum 2559 */ 2560 2561 typedef enum MPC_CRC_CALC_STEREO_MODE { 2562 MPC_CRC_STEREO_MODE_LEFT = 0x00000000, 2563 MPC_CRC_STEREO_MODE_RIGHT = 0x00000001, 2564 MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002, 2565 MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003, 2566 } MPC_CRC_CALC_STEREO_MODE; 2567 2568 /* 2569 * MPC_CRC_CALC_INTERLACE_MODE enum 2570 */ 2571 2572 typedef enum MPC_CRC_CALC_INTERLACE_MODE { 2573 MPC_CRC_INTERLACE_MODE_TOP = 0x00000000, 2574 MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, 2575 MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002, 2576 MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003, 2577 } MPC_CRC_CALC_INTERLACE_MODE; 2578 2579 /* 2580 * MPC_CRC_SOURCE_SELECT enum 2581 */ 2582 2583 typedef enum MPC_CRC_SOURCE_SELECT { 2584 MPC_CRC_SOURCE_SEL_DPP = 0x00000000, 2585 MPC_CRC_SOURCE_SEL_OPP = 0x00000001, 2586 MPC_CRC_SOURCE_SEL_DWB = 0x00000002, 2587 MPC_CRC_SOURCE_SEL_OTHER = 0x00000003, 2588 } MPC_CRC_SOURCE_SELECT; 2589 2590 /* 2591 * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum 2592 */ 2593 2594 typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET { 2595 MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2596 MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2597 } MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET; 2598 2599 /* 2600 * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum 2601 */ 2602 2603 typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET { 2604 MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2605 MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2606 } MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET; 2607 2608 /* 2609 * MPC_CFG_CFG_VUPDATE_LOCK_SET enum 2610 */ 2611 2612 typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET { 2613 MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2614 MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2615 } MPC_CFG_CFG_VUPDATE_LOCK_SET; 2616 2617 /* 2618 * MPC_CFG_ADR_VUPDATE_LOCK_SET enum 2619 */ 2620 2621 typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET { 2622 MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2623 MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2624 } MPC_CFG_ADR_VUPDATE_LOCK_SET; 2625 2626 /* 2627 * MPC_CFG_CUR_VUPDATE_LOCK_SET enum 2628 */ 2629 2630 typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET { 2631 MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2632 MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2633 } MPC_CFG_CUR_VUPDATE_LOCK_SET; 2634 2635 /* 2636 * MPC_OUT_RATE_CONTROL_DISABLE_SET enum 2637 */ 2638 2639 typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET { 2640 MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000, 2641 MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001, 2642 } MPC_OUT_RATE_CONTROL_DISABLE_SET; 2643 2644 /* 2645 * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum 2646 */ 2647 2648 typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE { 2649 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000, 2650 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001, 2651 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002, 2652 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003, 2653 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004, 2654 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005, 2655 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006, 2656 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007, 2657 } MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE; 2658 2659 /******************************************************* 2660 * MPC_OCSC Enums 2661 *******************************************************/ 2662 2663 /* 2664 * MPC_OCSC_COEF_FORMAT enum 2665 */ 2666 2667 typedef enum MPC_OCSC_COEF_FORMAT { 2668 MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000, 2669 MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001, 2670 } MPC_OCSC_COEF_FORMAT; 2671 2672 /* 2673 * MPC_OUT_CSC_MODE enum 2674 */ 2675 2676 typedef enum MPC_OUT_CSC_MODE { 2677 MPC_OUT_CSC_MODE_0 = 0x00000000, 2678 MPC_OUT_CSC_MODE_1 = 0x00000001, 2679 MPC_OUT_CSC_MODE_2 = 0x00000002, 2680 MPC_OUT_CSC_MODE_RSV = 0x00000003, 2681 } MPC_OUT_CSC_MODE; 2682 2683 /******************************************************* 2684 * MPCC Enums 2685 *******************************************************/ 2686 2687 /* 2688 * MPCC_CONTROL_MPCC_MODE enum 2689 */ 2690 2691 typedef enum MPCC_CONTROL_MPCC_MODE { 2692 MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000, 2693 MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001, 2694 MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002, 2695 MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003, 2696 } MPCC_CONTROL_MPCC_MODE; 2697 2698 /* 2699 * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum 2700 */ 2701 2702 typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE { 2703 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000, 2704 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001, 2705 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002, 2706 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003, 2707 } MPCC_CONTROL_MPCC_ALPHA_BLND_MODE; 2708 2709 /* 2710 * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum 2711 */ 2712 2713 typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE { 2714 MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000, 2715 MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001, 2716 } MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE; 2717 2718 /* 2719 * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum 2720 */ 2721 2722 typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY { 2723 MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000, 2724 MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001, 2725 } MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY; 2726 2727 /* 2728 * MPCC_SM_CONTROL_MPCC_SM_EN enum 2729 */ 2730 2731 typedef enum MPCC_SM_CONTROL_MPCC_SM_EN { 2732 MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000, 2733 MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001, 2734 } MPCC_SM_CONTROL_MPCC_SM_EN; 2735 2736 /* 2737 * MPCC_SM_CONTROL_MPCC_SM_MODE enum 2738 */ 2739 2740 typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE { 2741 MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000, 2742 MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002, 2743 MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004, 2744 MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006, 2745 } MPCC_SM_CONTROL_MPCC_SM_MODE; 2746 2747 /* 2748 * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum 2749 */ 2750 2751 typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT { 2752 MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000, 2753 MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001, 2754 } MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT; 2755 2756 /* 2757 * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum 2758 */ 2759 2760 typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT { 2761 MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000, 2762 MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001, 2763 } MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT; 2764 2765 /* 2766 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum 2767 */ 2768 2769 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL { 2770 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000, 2771 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001, 2772 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002, 2773 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003, 2774 } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL; 2775 2776 /* 2777 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum 2778 */ 2779 2780 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL { 2781 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000, 2782 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001, 2783 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002, 2784 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003, 2785 } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL; 2786 2787 /* 2788 * MPCC_STALL_STATUS_MPCC_STALL_INT_ACK enum 2789 */ 2790 2791 typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_ACK { 2792 MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0x00000000, 2793 MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 0x00000001, 2794 } MPCC_STALL_STATUS_MPCC_STALL_INT_ACK; 2795 2796 /* 2797 * MPCC_STALL_STATUS_MPCC_STALL_INT_MASK enum 2798 */ 2799 2800 typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_MASK { 2801 MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE = 0x00000000, 2802 MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE = 0x00000001, 2803 } MPCC_STALL_STATUS_MPCC_STALL_INT_MASK; 2804 2805 /* 2806 * MPCC_BG_COLOR_BPC enum 2807 */ 2808 2809 typedef enum MPCC_BG_COLOR_BPC { 2810 MPCC_BG_COLOR_BPC_8bit = 0x00000000, 2811 MPCC_BG_COLOR_BPC_9bit = 0x00000001, 2812 MPCC_BG_COLOR_BPC_10bit = 0x00000002, 2813 MPCC_BG_COLOR_BPC_11bit = 0x00000003, 2814 MPCC_BG_COLOR_BPC_12bit = 0x00000004, 2815 } MPCC_BG_COLOR_BPC; 2816 2817 /* 2818 * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum 2819 */ 2820 2821 typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE { 2822 MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000, 2823 MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001, 2824 } MPCC_CONTROL_MPCC_BOT_GAIN_MODE; 2825 2826 /******************************************************* 2827 * MPCC_OGAM Enums 2828 *******************************************************/ 2829 2830 /* 2831 * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum 2832 */ 2833 2834 typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL { 2835 MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000, 2836 MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001, 2837 } MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL; 2838 2839 /* 2840 * MPCC_OGAM_MODE_MPCC_OGAM_MODE enum 2841 */ 2842 2843 typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE { 2844 MPCC_OGAM_MODE_0 = 0x00000000, 2845 MPCC_OGAM_MODE_1 = 0x00000001, 2846 MPCC_OGAM_MODE_2 = 0x00000002, 2847 MPCC_OGAM_MODE_RSV = 0x00000003, 2848 } MPCC_OGAM_MODE_MPCC_OGAM_MODE; 2849 2850 /******************************************************* 2851 * DPG Enums 2852 *******************************************************/ 2853 2854 /* 2855 * ENUM_DPG_EN enum 2856 */ 2857 2858 typedef enum ENUM_DPG_EN { 2859 ENUM_DPG_DISABLE = 0x00000000, 2860 ENUM_DPG_ENABLE = 0x00000001, 2861 } ENUM_DPG_EN; 2862 2863 /* 2864 * ENUM_DPG_MODE enum 2865 */ 2866 2867 typedef enum ENUM_DPG_MODE { 2868 ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000, 2869 ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001, 2870 ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002, 2871 ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003, 2872 ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004, 2873 ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005, 2874 ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006, 2875 ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007, 2876 } ENUM_DPG_MODE; 2877 2878 /* 2879 * ENUM_DPG_DYNAMIC_RANGE enum 2880 */ 2881 2882 typedef enum ENUM_DPG_DYNAMIC_RANGE { 2883 ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000, 2884 ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001, 2885 } ENUM_DPG_DYNAMIC_RANGE; 2886 2887 /* 2888 * ENUM_DPG_BIT_DEPTH enum 2889 */ 2890 2891 typedef enum ENUM_DPG_BIT_DEPTH { 2892 ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000, 2893 ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001, 2894 ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002, 2895 ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003, 2896 } ENUM_DPG_BIT_DEPTH; 2897 2898 /* 2899 * ENUM_DPG_FIELD_POLARITY enum 2900 */ 2901 2902 typedef enum ENUM_DPG_FIELD_POLARITY { 2903 ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000, 2904 ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001, 2905 } ENUM_DPG_FIELD_POLARITY; 2906 2907 /******************************************************* 2908 * FMT Enums 2909 *******************************************************/ 2910 2911 /* 2912 * FMT_CONTROL_PIXEL_ENCODING enum 2913 */ 2914 2915 typedef enum FMT_CONTROL_PIXEL_ENCODING { 2916 FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000, 2917 FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001, 2918 FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002, 2919 FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003, 2920 } FMT_CONTROL_PIXEL_ENCODING; 2921 2922 /* 2923 * FMT_CONTROL_SUBSAMPLING_MODE enum 2924 */ 2925 2926 typedef enum FMT_CONTROL_SUBSAMPLING_MODE { 2927 FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000, 2928 FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001, 2929 FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002, 2930 FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003, 2931 } FMT_CONTROL_SUBSAMPLING_MODE; 2932 2933 /* 2934 * FMT_CONTROL_SUBSAMPLING_ORDER enum 2935 */ 2936 2937 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { 2938 FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000, 2939 FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001, 2940 } FMT_CONTROL_SUBSAMPLING_ORDER; 2941 2942 /* 2943 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum 2944 */ 2945 2946 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS { 2947 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000, 2948 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001, 2949 } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; 2950 2951 /* 2952 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum 2953 */ 2954 2955 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { 2956 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000, 2957 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001, 2958 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; 2959 2960 /* 2961 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum 2962 */ 2963 2964 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { 2965 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000, 2966 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001, 2967 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002, 2968 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; 2969 2970 /* 2971 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum 2972 */ 2973 2974 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { 2975 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000, 2976 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001, 2977 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002, 2978 } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; 2979 2980 /* 2981 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum 2982 */ 2983 2984 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { 2985 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000, 2986 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001, 2987 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002, 2988 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; 2989 2990 /* 2991 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum 2992 */ 2993 2994 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { 2995 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000, 2996 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001, 2997 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; 2998 2999 /* 3000 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum 3001 */ 3002 3003 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { 3004 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000, 3005 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001, 3006 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002, 3007 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003, 3008 } FMT_BIT_DEPTH_CONTROL_25FRC_SEL; 3009 3010 /* 3011 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum 3012 */ 3013 3014 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { 3015 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000, 3016 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001, 3017 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002, 3018 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003, 3019 } FMT_BIT_DEPTH_CONTROL_50FRC_SEL; 3020 3021 /* 3022 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum 3023 */ 3024 3025 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { 3026 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000, 3027 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001, 3028 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002, 3029 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003, 3030 } FMT_BIT_DEPTH_CONTROL_75FRC_SEL; 3031 3032 /* 3033 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum 3034 */ 3035 3036 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { 3037 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000, 3038 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001, 3039 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; 3040 3041 /* 3042 * FMT_CLAMP_CNTL_COLOR_FORMAT enum 3043 */ 3044 3045 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { 3046 FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000, 3047 FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001, 3048 FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002, 3049 FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003, 3050 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004, 3051 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005, 3052 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006, 3053 FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007, 3054 } FMT_CLAMP_CNTL_COLOR_FORMAT; 3055 3056 /* 3057 * FMT_SPATIAL_DITHER_MODE enum 3058 */ 3059 3060 typedef enum FMT_SPATIAL_DITHER_MODE { 3061 FMT_SPATIAL_DITHER_MODE_0 = 0x00000000, 3062 FMT_SPATIAL_DITHER_MODE_1 = 0x00000001, 3063 FMT_SPATIAL_DITHER_MODE_2 = 0x00000002, 3064 FMT_SPATIAL_DITHER_MODE_3 = 0x00000003, 3065 } FMT_SPATIAL_DITHER_MODE; 3066 3067 /* 3068 * FMT_DYNAMIC_EXP_MODE enum 3069 */ 3070 3071 typedef enum FMT_DYNAMIC_EXP_MODE { 3072 FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000, 3073 FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001, 3074 } FMT_DYNAMIC_EXP_MODE; 3075 3076 /* 3077 * FMTMEM_PWR_FORCE_CTRL enum 3078 */ 3079 3080 typedef enum FMTMEM_PWR_FORCE_CTRL { 3081 FMTMEM_NO_FORCE_REQUEST = 0x00000000, 3082 FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 3083 FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 3084 FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 3085 } FMTMEM_PWR_FORCE_CTRL; 3086 3087 /* 3088 * FMTMEM_PWR_DIS_CTRL enum 3089 */ 3090 3091 typedef enum FMTMEM_PWR_DIS_CTRL { 3092 FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, 3093 FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, 3094 } FMTMEM_PWR_DIS_CTRL; 3095 3096 /* 3097 * FMT_POWER_STATE_ENUM enum 3098 */ 3099 3100 typedef enum FMT_POWER_STATE_ENUM { 3101 FMT_POWER_STATE_ENUM_ON = 0x00000000, 3102 FMT_POWER_STATE_ENUM_LS = 0x00000001, 3103 FMT_POWER_STATE_ENUM_DS = 0x00000002, 3104 FMT_POWER_STATE_ENUM_SD = 0x00000003, 3105 } FMT_POWER_STATE_ENUM; 3106 3107 /* 3108 * FMT_STEREOSYNC_OVERRIDE_CONTROL enum 3109 */ 3110 3111 typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL { 3112 FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000, 3113 FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001, 3114 } FMT_STEREOSYNC_OVERRIDE_CONTROL; 3115 3116 /* 3117 * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum 3118 */ 3119 3120 typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL { 3121 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000, 3122 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001, 3123 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002, 3124 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003, 3125 } FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL; 3126 3127 /* 3128 * FMT_FRAME_RANDOM_ENABLE_CONTROL enum 3129 */ 3130 3131 typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL { 3132 FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000, 3133 FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001, 3134 } FMT_FRAME_RANDOM_ENABLE_CONTROL; 3135 3136 /* 3137 * FMT_RGB_RANDOM_ENABLE_CONTROL enum 3138 */ 3139 3140 typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL { 3141 FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000, 3142 FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001, 3143 } FMT_RGB_RANDOM_ENABLE_CONTROL; 3144 3145 /* 3146 * ENUM_FMT_PTI_FIELD_POLARITY enum 3147 */ 3148 3149 typedef enum ENUM_FMT_PTI_FIELD_POLARITY { 3150 ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000, 3151 ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001, 3152 } ENUM_FMT_PTI_FIELD_POLARITY; 3153 3154 /******************************************************* 3155 * OPP_PIPE Enums 3156 *******************************************************/ 3157 3158 /* 3159 * OPP_PIPE_CLOCK_ENABLE_CONTROL enum 3160 */ 3161 3162 typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL { 3163 OPP_PIPE_CLOCK_DISABLE = 0x00000000, 3164 OPP_PIPE_CLOCK_ENABLE = 0x00000001, 3165 } OPP_PIPE_CLOCK_ENABLE_CONTROL; 3166 3167 /* 3168 * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum 3169 */ 3170 3171 typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL { 3172 OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000, 3173 OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001, 3174 } OPP_PIPE_DIGTIAL_BYPASS_CONTROL; 3175 3176 /******************************************************* 3177 * OPP_PIPE_CRC Enums 3178 *******************************************************/ 3179 3180 /* 3181 * OPP_PIPE_CRC_EN enum 3182 */ 3183 3184 typedef enum OPP_PIPE_CRC_EN { 3185 OPP_PIPE_CRC_DISABLE = 0x00000000, 3186 OPP_PIPE_CRC_ENABLE = 0x00000001, 3187 } OPP_PIPE_CRC_EN; 3188 3189 /* 3190 * OPP_PIPE_CRC_CONT_EN enum 3191 */ 3192 3193 typedef enum OPP_PIPE_CRC_CONT_EN { 3194 OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000, 3195 OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001, 3196 } OPP_PIPE_CRC_CONT_EN; 3197 3198 /* 3199 * OPP_PIPE_CRC_STEREO_MODE enum 3200 */ 3201 3202 typedef enum OPP_PIPE_CRC_STEREO_MODE { 3203 OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000, 3204 OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001, 3205 OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002, 3206 OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003, 3207 } OPP_PIPE_CRC_STEREO_MODE; 3208 3209 /* 3210 * OPP_PIPE_CRC_STEREO_EN enum 3211 */ 3212 3213 typedef enum OPP_PIPE_CRC_STEREO_EN { 3214 OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000, 3215 OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001, 3216 } OPP_PIPE_CRC_STEREO_EN; 3217 3218 /* 3219 * OPP_PIPE_CRC_INTERLACE_MODE enum 3220 */ 3221 3222 typedef enum OPP_PIPE_CRC_INTERLACE_MODE { 3223 OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000, 3224 OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, 3225 OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002, 3226 OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003, 3227 } OPP_PIPE_CRC_INTERLACE_MODE; 3228 3229 /* 3230 * OPP_PIPE_CRC_INTERLACE_EN enum 3231 */ 3232 3233 typedef enum OPP_PIPE_CRC_INTERLACE_EN { 3234 OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000, 3235 OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001, 3236 } OPP_PIPE_CRC_INTERLACE_EN; 3237 3238 /* 3239 * OPP_PIPE_CRC_PIXEL_SELECT enum 3240 */ 3241 3242 typedef enum OPP_PIPE_CRC_PIXEL_SELECT { 3243 OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000, 3244 OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001, 3245 OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002, 3246 OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003, 3247 } OPP_PIPE_CRC_PIXEL_SELECT; 3248 3249 /* 3250 * OPP_PIPE_CRC_SOURCE_SELECT enum 3251 */ 3252 3253 typedef enum OPP_PIPE_CRC_SOURCE_SELECT { 3254 OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000, 3255 OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001, 3256 } OPP_PIPE_CRC_SOURCE_SELECT; 3257 3258 /* 3259 * OPP_PIPE_CRC_ONE_SHOT_PENDING enum 3260 */ 3261 3262 typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING { 3263 OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000, 3264 OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001, 3265 } OPP_PIPE_CRC_ONE_SHOT_PENDING; 3266 3267 /******************************************************* 3268 * OPP_TOP Enums 3269 *******************************************************/ 3270 3271 /* 3272 * OPP_TOP_CLOCK_GATING_CONTROL enum 3273 */ 3274 3275 typedef enum OPP_TOP_CLOCK_GATING_CONTROL { 3276 OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000, 3277 OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001, 3278 } OPP_TOP_CLOCK_GATING_CONTROL; 3279 3280 /* 3281 * OPP_TOP_CLOCK_ENABLE_STATUS enum 3282 */ 3283 3284 typedef enum OPP_TOP_CLOCK_ENABLE_STATUS { 3285 OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000, 3286 OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001, 3287 } OPP_TOP_CLOCK_ENABLE_STATUS; 3288 3289 /* 3290 * OPP_TEST_CLK_SEL_CONTROL enum 3291 */ 3292 3293 typedef enum OPP_TEST_CLK_SEL_CONTROL { 3294 OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000, 3295 OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001, 3296 OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002, 3297 OPP_TEST_CLK_SEL_RESERVED0 = 0x00000003, 3298 OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000004, 3299 OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000005, 3300 OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x00000006, 3301 OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x00000007, 3302 OPP_TEST_CLK_SEL_DISPCLK_OPP4 = 0x00000008, 3303 OPP_TEST_CLK_SEL_DISPCLK_OPP5 = 0x00000009, 3304 } OPP_TEST_CLK_SEL_CONTROL; 3305 3306 /******************************************************* 3307 * OTG Enums 3308 *******************************************************/ 3309 3310 /* 3311 * OTG_CONTROL_OTG_START_POINT_CNTL enum 3312 */ 3313 3314 typedef enum OTG_CONTROL_OTG_START_POINT_CNTL { 3315 OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000, 3316 OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001, 3317 } OTG_CONTROL_OTG_START_POINT_CNTL; 3318 3319 /* 3320 * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum 3321 */ 3322 3323 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL { 3324 OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000, 3325 OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001, 3326 } OTG_CONTROL_OTG_FIELD_NUMBER_CNTL; 3327 3328 /* 3329 * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum 3330 */ 3331 3332 typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL { 3333 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000, 3334 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001, 3335 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED = 0x00000002, 3336 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003, 3337 } OTG_CONTROL_OTG_DISABLE_POINT_CNTL; 3338 3339 /* 3340 * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum 3341 */ 3342 3343 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY { 3344 OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000, 3345 OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001, 3346 } OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY; 3347 3348 /* 3349 * OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE enum 3350 */ 3351 3352 typedef enum OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE { 3353 OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000, 3354 OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001, 3355 } OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE; 3356 3357 /* 3358 * OTG_CONTROL_OTG_SOF_PULL_EN enum 3359 */ 3360 3361 typedef enum OTG_CONTROL_OTG_SOF_PULL_EN { 3362 OTG_CONTROL_OTG_SOF_PULL_EN_FALSE = 0x00000000, 3363 OTG_CONTROL_OTG_SOF_PULL_EN_TRUE = 0x00000001, 3364 } OTG_CONTROL_OTG_SOF_PULL_EN; 3365 3366 /* 3367 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum 3368 */ 3369 3370 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL { 3371 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000, 3372 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001, 3373 } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL; 3374 3375 /* 3376 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum 3377 */ 3378 3379 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL { 3380 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000, 3381 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001, 3382 } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL; 3383 3384 /* 3385 * OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN enum 3386 */ 3387 3388 typedef enum OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN { 3389 OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000, 3390 OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001, 3391 } OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN; 3392 3393 /* 3394 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum 3395 */ 3396 3397 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC { 3398 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000, 3399 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001, 3400 } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC; 3401 3402 /* 3403 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum 3404 */ 3405 3406 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT { 3407 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000, 3408 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001, 3409 } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT; 3410 3411 /* 3412 * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum 3413 */ 3414 3415 typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD { 3416 OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000, 3417 OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001, 3418 } OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD; 3419 3420 /* 3421 * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum 3422 */ 3423 3424 typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK { 3425 OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000, 3426 OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001, 3427 } OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK; 3428 3429 /* 3430 * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum 3431 */ 3432 3433 typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR { 3434 OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000, 3435 OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001, 3436 } OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR; 3437 3438 /* 3439 * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum 3440 */ 3441 3442 typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN { 3443 OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000, 3444 OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001, 3445 } OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN; 3446 3447 /* 3448 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum 3449 */ 3450 3451 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT { 3452 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000, 3453 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001, 3454 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002, 3455 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003, 3456 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004, 3457 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005, 3458 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006, 3459 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, 3460 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, 3461 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, 3462 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, 3463 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b, 3464 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c, 3465 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, 3466 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL = 0x0000000e, 3467 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, 3468 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, 3469 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, 3470 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012, 3471 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013, 3472 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014, 3473 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, 3474 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, 3475 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017, 3476 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018, 3477 } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT; 3478 3479 /* 3480 * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum 3481 */ 3482 3483 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT { 3484 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000, 3485 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001, 3486 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002, 3487 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003, 3488 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004, 3489 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005, 3490 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006, 3491 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007, 3492 } OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT; 3493 3494 /* 3495 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum 3496 */ 3497 3498 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT { 3499 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000, 3500 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001, 3501 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002, 3502 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003, 3503 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004, 3504 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005, 3505 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006, 3506 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, 3507 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, 3508 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, 3509 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, 3510 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b, 3511 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c, 3512 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, 3513 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL = 0x0000000e, 3514 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, 3515 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, 3516 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, 3517 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012, 3518 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013, 3519 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014, 3520 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, 3521 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, 3522 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017, 3523 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018, 3524 } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT; 3525 3526 /* 3527 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum 3528 */ 3529 3530 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT { 3531 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, 3532 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, 3533 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, 3534 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, 3535 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4 = 0x00000004, 3536 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5 = 0x00000005, 3537 } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT; 3538 3539 /* 3540 * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum 3541 */ 3542 3543 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT { 3544 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000, 3545 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001, 3546 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002, 3547 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003, 3548 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004, 3549 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005, 3550 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006, 3551 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007, 3552 } OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT; 3553 3554 /* 3555 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum 3556 */ 3557 3558 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT { 3559 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, 3560 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, 3561 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, 3562 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, 3563 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4 = 0x00000004, 3564 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5 = 0x00000005, 3565 } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT; 3566 3567 /* 3568 * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum 3569 */ 3570 3571 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN { 3572 OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000, 3573 OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001, 3574 } OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN; 3575 3576 /* 3577 * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum 3578 */ 3579 3580 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR { 3581 OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000, 3582 OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001, 3583 } OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR; 3584 3585 /* 3586 * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum 3587 */ 3588 3589 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN { 3590 OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000, 3591 OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001, 3592 } OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN; 3593 3594 /* 3595 * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum 3596 */ 3597 3598 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR { 3599 OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000, 3600 OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001, 3601 } OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR; 3602 3603 /* 3604 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum 3605 */ 3606 3607 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE { 3608 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000, 3609 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001, 3610 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002, 3611 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003, 3612 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE; 3613 3614 /* 3615 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum 3616 */ 3617 3618 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK { 3619 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000, 3620 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001, 3621 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK; 3622 3623 /* 3624 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum 3625 */ 3626 3627 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL { 3628 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000, 3629 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001, 3630 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL; 3631 3632 /* 3633 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum 3634 */ 3635 3636 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR { 3637 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000, 3638 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001, 3639 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR; 3640 3641 /* 3642 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum 3643 */ 3644 3645 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT { 3646 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000, 3647 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001, 3648 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002, 3649 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003, 3650 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004, 3651 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005, 3652 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006, 3653 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007, 3654 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008, 3655 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009, 3656 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a, 3657 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b, 3658 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c, 3659 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d, 3660 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e, 3661 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE = 0x0000000f, 3662 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010, 3663 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011, 3664 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012, 3665 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013, 3666 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT; 3667 3668 /* 3669 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum 3670 */ 3671 3672 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY { 3673 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000, 3674 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001, 3675 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY; 3676 3677 /* 3678 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum 3679 */ 3680 3681 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY { 3682 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000, 3683 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001, 3684 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY; 3685 3686 /* 3687 * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum 3688 */ 3689 3690 typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE { 3691 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000, 3692 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001, 3693 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002, 3694 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003, 3695 } OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE; 3696 3697 /* 3698 * OTG_CONTROL_OTG_MASTER_EN enum 3699 */ 3700 3701 typedef enum OTG_CONTROL_OTG_MASTER_EN { 3702 OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000, 3703 OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001, 3704 } OTG_CONTROL_OTG_MASTER_EN; 3705 3706 /* 3707 * OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN enum 3708 */ 3709 3710 typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN { 3711 OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE = 0x00000000, 3712 OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE = 0x00000001, 3713 } OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN; 3714 3715 /* 3716 * OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE enum 3717 */ 3718 3719 typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE { 3720 OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE = 0x00000000, 3721 OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE = 0x00000001, 3722 } OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE; 3723 3724 /* 3725 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum 3726 */ 3727 3728 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE { 3729 OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000, 3730 OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001, 3731 } OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE; 3732 3733 /* 3734 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum 3735 */ 3736 3737 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD { 3738 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000, 3739 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001, 3740 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002, 3741 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003, 3742 } OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD; 3743 3744 /* 3745 * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY enum 3746 */ 3747 3748 typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY { 3749 OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000, 3750 OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001, 3751 } OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY; 3752 3753 /* 3754 * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT enum 3755 */ 3756 3757 typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT { 3758 OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE = 0x00000000, 3759 OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE = 0x00000001, 3760 } OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT; 3761 3762 /* 3763 * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum 3764 */ 3765 3766 typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN { 3767 OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000, 3768 OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001, 3769 } OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN; 3770 3771 /* 3772 * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum 3773 */ 3774 3775 typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE { 3776 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000, 3777 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001, 3778 } OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; 3779 3780 /* 3781 * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum 3782 */ 3783 3784 typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR { 3785 OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000, 3786 OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001, 3787 } OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR; 3788 3789 /* 3790 * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum 3791 */ 3792 3793 typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE { 3794 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000, 3795 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001, 3796 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002, 3797 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003, 3798 } OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE; 3799 3800 /* 3801 * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum 3802 */ 3803 3804 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY { 3805 OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000, 3806 OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001, 3807 } OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY; 3808 3809 /* 3810 * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum 3811 */ 3812 3813 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY { 3814 OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000, 3815 OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001, 3816 } OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY; 3817 3818 /* 3819 * OTG_STEREO_CONTROL_OTG_STEREO_EN enum 3820 */ 3821 3822 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN { 3823 OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000, 3824 OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001, 3825 } OTG_STEREO_CONTROL_OTG_STEREO_EN; 3826 3827 /* 3828 * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum 3829 */ 3830 3831 typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR { 3832 OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000, 3833 OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001, 3834 } OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR; 3835 3836 /* 3837 * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum 3838 */ 3839 3840 typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL { 3841 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000, 3842 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001, 3843 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002, 3844 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003, 3845 } OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL; 3846 3847 /* 3848 * OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY enum 3849 */ 3850 3851 typedef enum OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY { 3852 OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000, 3853 OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001, 3854 } OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY; 3855 3856 /* 3857 * OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY enum 3858 */ 3859 3860 typedef enum OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY { 3861 OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000, 3862 OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001, 3863 } OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY; 3864 3865 /* 3866 * OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN enum 3867 */ 3868 3869 typedef enum OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN { 3870 OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE = 0x00000000, 3871 OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE = 0x00000001, 3872 } OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN; 3873 3874 /* 3875 * OTG_START_LINE_CONTROL_OTG_PREFETCH_EN enum 3876 */ 3877 3878 typedef enum OTG_START_LINE_CONTROL_OTG_PREFETCH_EN { 3879 OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE = 0x00000000, 3880 OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE = 0x00000001, 3881 } OTG_START_LINE_CONTROL_OTG_PREFETCH_EN; 3882 3883 /* 3884 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum 3885 */ 3886 3887 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK { 3888 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000, 3889 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001, 3890 } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK; 3891 3892 /* 3893 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum 3894 */ 3895 3896 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE { 3897 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000, 3898 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001, 3899 } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE; 3900 3901 /* 3902 * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK enum 3903 */ 3904 3905 typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK { 3906 OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE = 0x00000000, 3907 OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE = 0x00000001, 3908 } OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK; 3909 3910 /* 3911 * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE enum 3912 */ 3913 3914 typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE { 3915 OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE = 0x00000000, 3916 OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE = 0x00000001, 3917 } OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE; 3918 3919 /* 3920 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum 3921 */ 3922 3923 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK { 3924 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000, 3925 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001, 3926 } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK; 3927 3928 /* 3929 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum 3930 */ 3931 3932 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE { 3933 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000, 3934 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001, 3935 } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE; 3936 3937 /* 3938 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum 3939 */ 3940 3941 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK { 3942 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000, 3943 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001, 3944 } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK; 3945 3946 /* 3947 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum 3948 */ 3949 3950 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE { 3951 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000, 3952 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001, 3953 } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE; 3954 3955 /* 3956 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum 3957 */ 3958 3959 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK { 3960 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000, 3961 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001, 3962 } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK; 3963 3964 /* 3965 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum 3966 */ 3967 3968 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE { 3969 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000, 3970 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001, 3971 } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE; 3972 3973 /* 3974 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum 3975 */ 3976 3977 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK { 3978 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000, 3979 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001, 3980 } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK; 3981 3982 /* 3983 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum 3984 */ 3985 3986 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE { 3987 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000, 3988 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001, 3989 } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE; 3990 3991 /* 3992 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum 3993 */ 3994 3995 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK { 3996 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000, 3997 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001, 3998 } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK; 3999 4000 /* 4001 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum 4002 */ 4003 4004 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE { 4005 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000, 4006 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001, 4007 } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE; 4008 4009 /* 4010 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum 4011 */ 4012 4013 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK { 4014 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000, 4015 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001, 4016 } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK; 4017 4018 /* 4019 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum 4020 */ 4021 4022 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE { 4023 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000, 4024 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001, 4025 } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE; 4026 4027 /* 4028 * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum 4029 */ 4030 4031 typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK { 4032 OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000, 4033 OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001, 4034 } OTG_UPDATE_LOCK_OTG_UPDATE_LOCK; 4035 4036 /* 4037 * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum 4038 */ 4039 4040 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY { 4041 OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000, 4042 OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001, 4043 } OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY; 4044 4045 /* 4046 * OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN enum 4047 */ 4048 4049 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN { 4050 OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000, 4051 OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001, 4052 } OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN; 4053 4054 /* 4055 * OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE enum 4056 */ 4057 4058 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE { 4059 OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000, 4060 OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001, 4061 OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002, 4062 OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003, 4063 } OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE; 4064 4065 /* 4066 * OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE enum 4067 */ 4068 4069 typedef enum OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE { 4070 OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000, 4071 OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001, 4072 } OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE; 4073 4074 /* 4075 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum 4076 */ 4077 4078 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { 4079 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000, 4080 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001, 4081 } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; 4082 4083 /* 4084 * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum 4085 */ 4086 4087 typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME { 4088 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000, 4089 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001, 4090 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002, 4091 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003, 4092 } OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME; 4093 4094 /* 4095 * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum 4096 */ 4097 4098 typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK { 4099 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000, 4100 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001, 4101 } MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK; 4102 4103 /* 4104 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum 4105 */ 4106 4107 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { 4108 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000, 4109 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001, 4110 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002, 4111 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003, 4112 } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; 4113 4114 /* 4115 * OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE enum 4116 */ 4117 4118 typedef enum OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE { 4119 OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000, 4120 OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001, 4121 OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002, 4122 } OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE; 4123 4124 /* 4125 * OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR enum 4126 */ 4127 4128 typedef enum OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR { 4129 OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE = 0x00000000, 4130 OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE = 0x00000001, 4131 } OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR; 4132 4133 /* 4134 * OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR enum 4135 */ 4136 4137 typedef enum OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR { 4138 OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000, 4139 OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001, 4140 } OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR; 4141 4142 /* 4143 * OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR enum 4144 */ 4145 4146 typedef enum OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR { 4147 OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE = 0x00000000, 4148 OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE = 0x00000001, 4149 } OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR; 4150 4151 /* 4152 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum 4153 */ 4154 4155 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { 4156 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000, 4157 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001, 4158 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; 4159 4160 /* 4161 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum 4162 */ 4163 4164 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE { 4165 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000, 4166 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001, 4167 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE; 4168 4169 /* 4170 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum 4171 */ 4172 4173 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR { 4174 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000, 4175 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001, 4176 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR; 4177 4178 /* 4179 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum 4180 */ 4181 4182 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE { 4183 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000, 4184 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001, 4185 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE; 4186 4187 /* 4188 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum 4189 */ 4190 4191 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR { 4192 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000, 4193 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001, 4194 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR; 4195 4196 /* 4197 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum 4198 */ 4199 4200 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE { 4201 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000, 4202 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001, 4203 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE; 4204 4205 /* 4206 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum 4207 */ 4208 4209 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE { 4210 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000, 4211 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001, 4212 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE; 4213 4214 /* 4215 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum 4216 */ 4217 4218 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR { 4219 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000, 4220 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001, 4221 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR; 4222 4223 /* 4224 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum 4225 */ 4226 4227 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE { 4228 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000, 4229 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001, 4230 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE; 4231 4232 /* 4233 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum 4234 */ 4235 4236 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE { 4237 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000, 4238 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001, 4239 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE; 4240 4241 /* 4242 * OTG_CRC_CNTL_OTG_CRC_EN enum 4243 */ 4244 4245 typedef enum OTG_CRC_CNTL_OTG_CRC_EN { 4246 OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000, 4247 OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001, 4248 } OTG_CRC_CNTL_OTG_CRC_EN; 4249 4250 /* 4251 * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum 4252 */ 4253 4254 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN { 4255 OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000, 4256 OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001, 4257 } OTG_CRC_CNTL_OTG_CRC_CONT_EN; 4258 4259 /* 4260 * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum 4261 */ 4262 4263 typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE { 4264 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000, 4265 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001, 4266 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002, 4267 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003, 4268 } OTG_CRC_CNTL_OTG_CRC_STEREO_MODE; 4269 4270 /* 4271 * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum 4272 */ 4273 4274 typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE { 4275 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000, 4276 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, 4277 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002, 4278 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003, 4279 } OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE; 4280 4281 /* 4282 * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum 4283 */ 4284 4285 typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS { 4286 OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000, 4287 OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001, 4288 } OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS; 4289 4290 /* 4291 * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum 4292 */ 4293 4294 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT { 4295 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000, 4296 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001, 4297 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002, 4298 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003, 4299 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004, 4300 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005, 4301 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006, 4302 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007, 4303 } OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT; 4304 4305 /* 4306 * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum 4307 */ 4308 4309 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT { 4310 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000, 4311 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001, 4312 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002, 4313 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003, 4314 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004, 4315 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005, 4316 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006, 4317 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007, 4318 } OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT; 4319 4320 /* 4321 * OTG_CRC_CNTL2_OTG_CRC_DSC_MODE enum 4322 */ 4323 4324 typedef enum OTG_CRC_CNTL2_OTG_CRC_DSC_MODE { 4325 OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE = 0x00000000, 4326 OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE = 0x00000001, 4327 } OTG_CRC_CNTL2_OTG_CRC_DSC_MODE; 4328 4329 /* 4330 * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE enum 4331 */ 4332 4333 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE { 4334 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE = 0x00000000, 4335 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE = 0x00000001, 4336 } OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE; 4337 4338 /* 4339 * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE enum 4340 */ 4341 4342 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE { 4343 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE = 0x00000000, 4344 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1 = 0x00000001, 4345 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2 = 0x00000002, 4346 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3 = 0x00000003, 4347 } OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE; 4348 4349 /* 4350 * OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT enum 4351 */ 4352 4353 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT { 4354 OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0 = 0x00000000, 4355 OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1 = 0x00000001, 4356 OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2 = 0x00000002, 4357 OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3 = 0x00000003, 4358 } OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT; 4359 4360 /* 4361 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE enum 4362 */ 4363 4364 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE { 4365 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000, 4366 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001, 4367 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002, 4368 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003, 4369 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE; 4370 4371 /* 4372 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum 4373 */ 4374 4375 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE { 4376 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000, 4377 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001, 4378 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE; 4379 4380 /* 4381 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum 4382 */ 4383 4384 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE { 4385 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000, 4386 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001, 4387 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE; 4388 4389 /* 4390 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum 4391 */ 4392 4393 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW { 4394 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000, 4395 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001, 4396 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002, 4397 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003, 4398 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW; 4399 4400 /* 4401 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE enum 4402 */ 4403 4404 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE { 4405 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000, 4406 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001, 4407 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE; 4408 4409 /* 4410 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE enum 4411 */ 4412 4413 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE { 4414 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000, 4415 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001, 4416 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE; 4417 4418 /* 4419 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY enum 4420 */ 4421 4422 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY { 4423 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000, 4424 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001, 4425 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY; 4426 4427 /* 4428 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY enum 4429 */ 4430 4431 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY { 4432 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000, 4433 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001, 4434 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY; 4435 4436 /* 4437 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE enum 4438 */ 4439 4440 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE { 4441 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000, 4442 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001, 4443 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE; 4444 4445 /* 4446 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum 4447 */ 4448 4449 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE { 4450 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000, 4451 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001, 4452 } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE; 4453 4454 /* 4455 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR enum 4456 */ 4457 4458 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR { 4459 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000, 4460 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001, 4461 } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR; 4462 4463 /* 4464 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE enum 4465 */ 4466 4467 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE { 4468 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000, 4469 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001, 4470 } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE; 4471 4472 /* 4473 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum 4474 */ 4475 4476 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT { 4477 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000, 4478 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001, 4479 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002, 4480 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003, 4481 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004, 4482 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005, 4483 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006, 4484 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007, 4485 } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT; 4486 4487 /* 4488 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE enum 4489 */ 4490 4491 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE { 4492 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000, 4493 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001, 4494 } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE; 4495 4496 /* 4497 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR enum 4498 */ 4499 4500 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR { 4501 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000, 4502 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001, 4503 } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR; 4504 4505 /* 4506 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE enum 4507 */ 4508 4509 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE { 4510 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000, 4511 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001, 4512 } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE; 4513 4514 /* 4515 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum 4516 */ 4517 4518 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE { 4519 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000, 4520 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001, 4521 } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE; 4522 4523 /* 4524 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR enum 4525 */ 4526 4527 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR { 4528 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000, 4529 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001, 4530 } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR; 4531 4532 /* 4533 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum 4534 */ 4535 4536 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE { 4537 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000, 4538 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001, 4539 } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE; 4540 4541 /* 4542 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum 4543 */ 4544 4545 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE { 4546 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000, 4547 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001, 4548 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE; 4549 4550 /* 4551 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum 4552 */ 4553 4554 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR { 4555 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000, 4556 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001, 4557 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR; 4558 4559 /* 4560 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum 4561 */ 4562 4563 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE { 4564 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000, 4565 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001, 4566 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE; 4567 4568 /* 4569 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum 4570 */ 4571 4572 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE { 4573 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000, 4574 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001, 4575 } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE; 4576 4577 /* 4578 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum 4579 */ 4580 4581 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE { 4582 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000, 4583 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001, 4584 } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE; 4585 4586 /* 4587 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum 4588 */ 4589 4590 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN { 4591 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000, 4592 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001, 4593 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN; 4594 4595 /* 4596 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum 4597 */ 4598 4599 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB { 4600 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000, 4601 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001, 4602 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB; 4603 4604 /* 4605 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum 4606 */ 4607 4608 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE { 4609 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000, 4610 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001, 4611 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002, 4612 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003, 4613 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE; 4614 4615 /* 4616 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum 4617 */ 4618 4619 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR { 4620 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000, 4621 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001, 4622 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR; 4623 4624 /* 4625 * OTG_V_SYNC_A_POL enum 4626 */ 4627 4628 typedef enum OTG_V_SYNC_A_POL { 4629 OTG_V_SYNC_A_POL_HIGH = 0x00000000, 4630 OTG_V_SYNC_A_POL_LOW = 0x00000001, 4631 } OTG_V_SYNC_A_POL; 4632 4633 /* 4634 * OTG_H_SYNC_A_POL enum 4635 */ 4636 4637 typedef enum OTG_H_SYNC_A_POL { 4638 OTG_H_SYNC_A_POL_HIGH = 0x00000000, 4639 OTG_H_SYNC_A_POL_LOW = 0x00000001, 4640 } OTG_H_SYNC_A_POL; 4641 4642 /* 4643 * OTG_HORZ_REPETITION_COUNT enum 4644 */ 4645 4646 typedef enum OTG_HORZ_REPETITION_COUNT { 4647 OTG_HORZ_REPETITION_COUNT_0 = 0x00000000, 4648 OTG_HORZ_REPETITION_COUNT_1 = 0x00000001, 4649 OTG_HORZ_REPETITION_COUNT_2 = 0x00000002, 4650 OTG_HORZ_REPETITION_COUNT_3 = 0x00000003, 4651 OTG_HORZ_REPETITION_COUNT_4 = 0x00000004, 4652 OTG_HORZ_REPETITION_COUNT_5 = 0x00000005, 4653 OTG_HORZ_REPETITION_COUNT_6 = 0x00000006, 4654 OTG_HORZ_REPETITION_COUNT_7 = 0x00000007, 4655 OTG_HORZ_REPETITION_COUNT_8 = 0x00000008, 4656 OTG_HORZ_REPETITION_COUNT_9 = 0x00000009, 4657 OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a, 4658 OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b, 4659 OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c, 4660 OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d, 4661 OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e, 4662 OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f, 4663 } OTG_HORZ_REPETITION_COUNT; 4664 4665 /* 4666 * MASTER_UPDATE_LOCK_SEL enum 4667 */ 4668 4669 typedef enum MASTER_UPDATE_LOCK_SEL { 4670 MASTER_UPDATE_LOCK_SEL_0 = 0x00000000, 4671 MASTER_UPDATE_LOCK_SEL_1 = 0x00000001, 4672 MASTER_UPDATE_LOCK_SEL_2 = 0x00000002, 4673 MASTER_UPDATE_LOCK_SEL_3 = 0x00000003, 4674 MASTER_UPDATE_LOCK_SEL_4 = 0x00000004, 4675 MASTER_UPDATE_LOCK_SEL_5 = 0x00000005, 4676 } MASTER_UPDATE_LOCK_SEL; 4677 4678 /* 4679 * DRR_UPDATE_LOCK_SEL enum 4680 */ 4681 4682 typedef enum DRR_UPDATE_LOCK_SEL { 4683 DRR_UPDATE_LOCK_SEL_0 = 0x00000000, 4684 DRR_UPDATE_LOCK_SEL_1 = 0x00000001, 4685 DRR_UPDATE_LOCK_SEL_2 = 0x00000002, 4686 DRR_UPDATE_LOCK_SEL_3 = 0x00000003, 4687 DRR_UPDATE_LOCK_SEL_4 = 0x00000004, 4688 DRR_UPDATE_LOCK_SEL_5 = 0x00000005, 4689 } DRR_UPDATE_LOCK_SEL; 4690 4691 /* 4692 * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum 4693 */ 4694 4695 typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL { 4696 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000, 4697 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001, 4698 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002, 4699 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003, 4700 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4 = 0x00000004, 4701 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5 = 0x00000005, 4702 } OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL; 4703 4704 /* 4705 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum 4706 */ 4707 4708 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD { 4709 MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000, 4710 MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001, 4711 MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000002, 4712 } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD; 4713 4714 /* 4715 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum 4716 */ 4717 4718 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL { 4719 MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000, 4720 MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001, 4721 MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002, 4722 MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003, 4723 } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL; 4724 4725 /* 4726 * OTG_H_TIMING_DIV_BY2 enum 4727 */ 4728 4729 typedef enum OTG_H_TIMING_DIV_BY2 { 4730 OTG_H_TIMING_DIV_BY2_FALSE = 0x00000000, 4731 OTG_H_TIMING_DIV_BY2_TRUE = 0x00000001, 4732 } OTG_H_TIMING_DIV_BY2; 4733 4734 /* 4735 * OTG_H_TIMING_DIV_BY2_UPDATE_MODE enum 4736 */ 4737 4738 typedef enum OTG_H_TIMING_DIV_BY2_UPDATE_MODE { 4739 OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0 = 0x00000000, 4740 OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1 = 0x00000001, 4741 } OTG_H_TIMING_DIV_BY2_UPDATE_MODE; 4742 4743 /* 4744 * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum 4745 */ 4746 4747 typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL { 4748 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, 4749 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, 4750 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, 4751 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, 4752 } OTG_TRIGA_RISING_EDGE_DETECT_CNTL; 4753 4754 /* 4755 * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum 4756 */ 4757 4758 typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL { 4759 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, 4760 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, 4761 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, 4762 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, 4763 } OTG_TRIGA_FALLING_EDGE_DETECT_CNTL; 4764 4765 /* 4766 * OTG_TRIGA_FREQUENCY_SELECT enum 4767 */ 4768 4769 typedef enum OTG_TRIGA_FREQUENCY_SELECT { 4770 OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000, 4771 OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001, 4772 OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002, 4773 OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003, 4774 } OTG_TRIGA_FREQUENCY_SELECT; 4775 4776 /* 4777 * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum 4778 */ 4779 4780 typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL { 4781 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, 4782 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, 4783 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, 4784 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, 4785 } OTG_TRIGB_RISING_EDGE_DETECT_CNTL; 4786 4787 /* 4788 * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum 4789 */ 4790 4791 typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL { 4792 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, 4793 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, 4794 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, 4795 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, 4796 } OTG_TRIGB_FALLING_EDGE_DETECT_CNTL; 4797 4798 /* 4799 * OTG_TRIGB_FREQUENCY_SELECT enum 4800 */ 4801 4802 typedef enum OTG_TRIGB_FREQUENCY_SELECT { 4803 OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000, 4804 OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001, 4805 OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002, 4806 OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003, 4807 } OTG_TRIGB_FREQUENCY_SELECT; 4808 4809 /* 4810 * OTG_PIPE_ABORT enum 4811 */ 4812 4813 typedef enum OTG_PIPE_ABORT { 4814 OTG_PIPE_ABORT_0 = 0x00000000, 4815 OTG_PIPE_ABORT_1 = 0x00000001, 4816 } OTG_PIPE_ABORT; 4817 4818 /* 4819 * OTG_MASTER_UPDATE_LOCK_GSL_EN enum 4820 */ 4821 4822 typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN { 4823 OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000, 4824 OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001, 4825 } OTG_MASTER_UPDATE_LOCK_GSL_EN; 4826 4827 /* 4828 * OTG_PTI_CONTROL_OTG_PIT_EN enum 4829 */ 4830 4831 typedef enum OTG_PTI_CONTROL_OTG_PIT_EN { 4832 OTG_PTI_CONTROL_OTG_PIT_EN_FALSE = 0x00000000, 4833 OTG_PTI_CONTROL_OTG_PIT_EN_TRUE = 0x00000001, 4834 } OTG_PTI_CONTROL_OTG_PIT_EN; 4835 4836 /* 4837 * OTG_GSL_MASTER_MODE enum 4838 */ 4839 4840 typedef enum OTG_GSL_MASTER_MODE { 4841 OTG_GSL_MASTER_MODE_0 = 0x00000000, 4842 OTG_GSL_MASTER_MODE_1 = 0x00000001, 4843 OTG_GSL_MASTER_MODE_2 = 0x00000002, 4844 OTG_GSL_MASTER_MODE_3 = 0x00000003, 4845 } OTG_GSL_MASTER_MODE; 4846 4847 /******************************************************* 4848 * DMCUB Enums 4849 *******************************************************/ 4850 4851 /* 4852 * DC_DMCUB_TIMER_WINDOW enum 4853 */ 4854 4855 typedef enum DC_DMCUB_TIMER_WINDOW { 4856 BITS_31_0 = 0x00000000, 4857 BITS_32_1 = 0x00000001, 4858 BITS_33_2 = 0x00000002, 4859 BITS_34_3 = 0x00000003, 4860 BITS_35_4 = 0x00000004, 4861 BITS_36_5 = 0x00000005, 4862 BITS_37_6 = 0x00000006, 4863 BITS_38_7 = 0x00000007, 4864 } DC_DMCUB_TIMER_WINDOW; 4865 4866 /* 4867 * DC_DMCUB_INT_TYPE enum 4868 */ 4869 4870 typedef enum DC_DMCUB_INT_TYPE { 4871 INT_LEVEL = 0x00000000, 4872 INT_PULSE = 0x00000001, 4873 } DC_DMCUB_INT_TYPE; 4874 4875 /******************************************************* 4876 * RBBMIF Enums 4877 *******************************************************/ 4878 4879 /* 4880 * INVALID_REG_ACCESS_TYPE enum 4881 */ 4882 4883 typedef enum INVALID_REG_ACCESS_TYPE { 4884 REG_UNALLOCATED_ADDR_WRITE = 0x00000000, 4885 REG_UNALLOCATED_ADDR_READ = 0x00000001, 4886 REG_VIRTUAL_WRITE = 0x00000002, 4887 REG_VIRTUAL_READ = 0x00000003, 4888 } INVALID_REG_ACCESS_TYPE; 4889 4890 /******************************************************* 4891 * IHC Enums 4892 *******************************************************/ 4893 4894 /* 4895 * DMU_DC_GPU_TIMER_START_POSITION enum 4896 */ 4897 4898 typedef enum DMU_DC_GPU_TIMER_START_POSITION { 4899 DMU_GPU_TIMER_START_0_END_27 = 0x00000000, 4900 DMU_GPU_TIMER_START_1_END_28 = 0x00000001, 4901 DMU_GPU_TIMER_START_2_END_29 = 0x00000002, 4902 DMU_GPU_TIMER_START_3_END_30 = 0x00000003, 4903 DMU_GPU_TIMER_START_4_END_31 = 0x00000004, 4904 DMU_GPU_TIMER_START_6_END_33 = 0x00000005, 4905 DMU_GPU_TIMER_START_8_END_35 = 0x00000006, 4906 DMU_GPU_TIMER_START_10_END_37 = 0x00000007, 4907 } DMU_DC_GPU_TIMER_START_POSITION; 4908 4909 /* 4910 * DMU_DC_GPU_TIMER_READ_SELECT enum 4911 */ 4912 4913 typedef enum DMU_DC_GPU_TIMER_READ_SELECT { 4914 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000, 4915 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001, 4916 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002, 4917 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003, 4918 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004, 4919 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005, 4920 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006, 4921 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007, 4922 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8 = 0x00000008, 4923 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9 = 0x00000009, 4924 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10 = 0x0000000a, 4925 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11 = 0x0000000b, 4926 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c, 4927 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d, 4928 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e, 4929 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f, 4930 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010, 4931 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011, 4932 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012, 4933 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013, 4934 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20 = 0x00000014, 4935 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21 = 0x00000015, 4936 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22 = 0x00000016, 4937 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23 = 0x00000017, 4938 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018, 4939 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019, 4940 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a, 4941 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b, 4942 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c, 4943 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d, 4944 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e, 4945 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f, 4946 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32 = 0x00000020, 4947 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33 = 0x00000021, 4948 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34 = 0x00000022, 4949 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35 = 0x00000023, 4950 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024, 4951 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025, 4952 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026, 4953 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027, 4954 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028, 4955 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029, 4956 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a, 4957 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b, 4958 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44 = 0x0000002c, 4959 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45 = 0x0000002d, 4960 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46 = 0x0000002e, 4961 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47 = 0x0000002f, 4962 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030, 4963 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031, 4964 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032, 4965 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033, 4966 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034, 4967 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035, 4968 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036, 4969 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037, 4970 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56 = 0x00000038, 4971 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57 = 0x00000039, 4972 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58 = 0x0000003a, 4973 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59 = 0x0000003b, 4974 RESERVED_60 = 0x0000003c, 4975 RESERVED_61 = 0x0000003d, 4976 RESERVED_62 = 0x0000003e, 4977 RESERVED_63 = 0x0000003f, 4978 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040, 4979 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041, 4980 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042, 4981 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043, 4982 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044, 4983 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045, 4984 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046, 4985 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047, 4986 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72 = 0x00000048, 4987 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73 = 0x00000049, 4988 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74 = 0x0000004a, 4989 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75 = 0x0000004b, 4990 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c, 4991 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d, 4992 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e, 4993 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f, 4994 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050, 4995 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051, 4996 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052, 4997 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053, 4998 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84 = 0x00000054, 4999 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85 = 0x00000055, 5000 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86 = 0x00000056, 5001 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87 = 0x00000057, 5002 RESERVED_88 = 0x00000058, 5003 RESERVED_89 = 0x00000059, 5004 RESERVED_90 = 0x0000005a, 5005 RESERVED_91 = 0x0000005b, 5006 } DMU_DC_GPU_TIMER_READ_SELECT; 5007 5008 /* 5009 * IHC_INTERRUPT_LINE_STATUS enum 5010 */ 5011 5012 typedef enum IHC_INTERRUPT_LINE_STATUS { 5013 INTERRUPT_LINE_NOT_ASSERTED = 0x00000000, 5014 INTERRUPT_LINE_ASSERTED = 0x00000001, 5015 } IHC_INTERRUPT_LINE_STATUS; 5016 5017 /******************************************************* 5018 * DMU_MISC Enums 5019 *******************************************************/ 5020 5021 /* 5022 * DMU_CLOCK_GATING_DISABLE enum 5023 */ 5024 5025 typedef enum DMU_CLOCK_GATING_DISABLE { 5026 DMU_ENABLE_CLOCK_GATING = 0x00000000, 5027 DMU_DISABLE_CLOCK_GATING = 0x00000001, 5028 } DMU_CLOCK_GATING_DISABLE; 5029 5030 /* 5031 * DMU_CLOCK_ON enum 5032 */ 5033 5034 typedef enum DMU_CLOCK_ON { 5035 DMU_CLOCK_STATUS_ON = 0x00000000, 5036 DMU_CLOCK_STATUS_OFF = 0x00000001, 5037 } DMU_CLOCK_ON; 5038 5039 /* 5040 * DC_SMU_INTERRUPT_ENABLE enum 5041 */ 5042 5043 typedef enum DC_SMU_INTERRUPT_ENABLE { 5044 DISABLE_THE_INTERRUPT = 0x00000000, 5045 ENABLE_THE_INTERRUPT = 0x00000001, 5046 } DC_SMU_INTERRUPT_ENABLE; 5047 5048 /* 5049 * STATIC_SCREEN_SMU_INTR enum 5050 */ 5051 5052 typedef enum STATIC_SCREEN_SMU_INTR { 5053 STATIC_SCREEN_SMU_INTR_NOOP = 0x00000000, 5054 SET_STATIC_SCREEN_SMU_INTR = 0x00000001, 5055 } STATIC_SCREEN_SMU_INTR; 5056 5057 /******************************************************* 5058 * DCCG Enums 5059 *******************************************************/ 5060 5061 /* 5062 * ENABLE enum 5063 */ 5064 5065 typedef enum ENABLE { 5066 DISABLE_THE_FEATURE = 0x00000000, 5067 ENABLE_THE_FEATURE = 0x00000001, 5068 } ENABLE; 5069 5070 /* 5071 * DS_HW_CAL_ENABLE enum 5072 */ 5073 5074 typedef enum DS_HW_CAL_ENABLE { 5075 DS_HW_CAL_DIS = 0x00000000, 5076 DS_HW_CAL_EN = 0x00000001, 5077 } DS_HW_CAL_ENABLE; 5078 5079 /* 5080 * ENABLE_CLOCK enum 5081 */ 5082 5083 typedef enum ENABLE_CLOCK { 5084 DISABLE_THE_CLOCK = 0x00000000, 5085 ENABLE_THE_CLOCK = 0x00000001, 5086 } ENABLE_CLOCK; 5087 5088 /* 5089 * CLEAR_SMU_INTR enum 5090 */ 5091 5092 typedef enum CLEAR_SMU_INTR { 5093 SMU_INTR_STATUS_NOOP = 0x00000000, 5094 SMU_INTR_STATUS_CLEAR = 0x00000001, 5095 } CLEAR_SMU_INTR; 5096 5097 /* 5098 * JITTER_REMOVE_DISABLE enum 5099 */ 5100 5101 typedef enum JITTER_REMOVE_DISABLE { 5102 ENABLE_JITTER_REMOVAL = 0x00000000, 5103 DISABLE_JITTER_REMOVAL = 0x00000001, 5104 } JITTER_REMOVE_DISABLE; 5105 5106 /* 5107 * DS_REF_SRC enum 5108 */ 5109 5110 typedef enum DS_REF_SRC { 5111 DS_REF_IS_XTALIN = 0x00000000, 5112 DS_REF_IS_EXT_GENLOCK = 0x00000001, 5113 DS_REF_IS_PCIE = 0x00000002, 5114 } DS_REF_SRC; 5115 5116 /* 5117 * DISABLE_CLOCK_GATING enum 5118 */ 5119 5120 typedef enum DISABLE_CLOCK_GATING { 5121 CLOCK_GATING_ENABLED = 0x00000000, 5122 CLOCK_GATING_DISABLED = 0x00000001, 5123 } DISABLE_CLOCK_GATING; 5124 5125 /* 5126 * DISABLE_CLOCK_GATING_IN_DCO enum 5127 */ 5128 5129 typedef enum DISABLE_CLOCK_GATING_IN_DCO { 5130 CLOCK_GATING_ENABLED_IN_DCO = 0x00000000, 5131 CLOCK_GATING_DISABLED_IN_DCO = 0x00000001, 5132 } DISABLE_CLOCK_GATING_IN_DCO; 5133 5134 /* 5135 * DCCG_DEEP_COLOR_CNTL enum 5136 */ 5137 5138 typedef enum DCCG_DEEP_COLOR_CNTL { 5139 DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000, 5140 DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001, 5141 DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002, 5142 DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003, 5143 } DCCG_DEEP_COLOR_CNTL; 5144 5145 /* 5146 * REFCLK_CLOCK_EN enum 5147 */ 5148 5149 typedef enum REFCLK_CLOCK_EN { 5150 REFCLK_CLOCK_EN_XTALIN_CLK = 0x00000000, 5151 REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 0x00000001, 5152 } REFCLK_CLOCK_EN; 5153 5154 /* 5155 * REFCLK_SRC_SEL enum 5156 */ 5157 5158 typedef enum REFCLK_SRC_SEL { 5159 REFCLK_SRC_SEL_PCIE_REFCLK = 0x00000000, 5160 REFCLK_SRC_SEL_CPL_REFCLK = 0x00000001, 5161 } REFCLK_SRC_SEL; 5162 5163 /* 5164 * DPREFCLK_SRC_SEL enum 5165 */ 5166 5167 typedef enum DPREFCLK_SRC_SEL { 5168 DPREFCLK_SRC_SEL_CK = 0x00000000, 5169 DPREFCLK_SRC_SEL_P0PLL = 0x00000001, 5170 DPREFCLK_SRC_SEL_P1PLL = 0x00000002, 5171 DPREFCLK_SRC_SEL_P2PLL = 0x00000003, 5172 } DPREFCLK_SRC_SEL; 5173 5174 /* 5175 * XTAL_REF_SEL enum 5176 */ 5177 5178 typedef enum XTAL_REF_SEL { 5179 XTAL_REF_SEL_1X = 0x00000000, 5180 XTAL_REF_SEL_2X = 0x00000001, 5181 } XTAL_REF_SEL; 5182 5183 /* 5184 * XTAL_REF_CLOCK_SOURCE_SEL enum 5185 */ 5186 5187 typedef enum XTAL_REF_CLOCK_SOURCE_SEL { 5188 XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000, 5189 XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001, 5190 } XTAL_REF_CLOCK_SOURCE_SEL; 5191 5192 /* 5193 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum 5194 */ 5195 5196 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL { 5197 MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, 5198 MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, 5199 } MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; 5200 5201 /* 5202 * ALLOW_SR_ON_TRANS_REQ enum 5203 */ 5204 5205 typedef enum ALLOW_SR_ON_TRANS_REQ { 5206 ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000, 5207 ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001, 5208 } ALLOW_SR_ON_TRANS_REQ; 5209 5210 /* 5211 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum 5212 */ 5213 5214 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL { 5215 MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, 5216 MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, 5217 } MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; 5218 5219 /* 5220 * PIPE_PIXEL_RATE_SOURCE enum 5221 */ 5222 5223 typedef enum PIPE_PIXEL_RATE_SOURCE { 5224 PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000, 5225 PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001, 5226 PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002, 5227 } PIPE_PIXEL_RATE_SOURCE; 5228 5229 /* 5230 * TEST_CLK_DIV_SEL enum 5231 */ 5232 5233 typedef enum TEST_CLK_DIV_SEL { 5234 NO_DIV = 0x00000000, 5235 DIV_2 = 0x00000001, 5236 DIV_4 = 0x00000002, 5237 DIV_8 = 0x00000003, 5238 } TEST_CLK_DIV_SEL; 5239 5240 /* 5241 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum 5242 */ 5243 5244 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE { 5245 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000, 5246 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001, 5247 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002, 5248 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003, 5249 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x00000004, 5250 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x00000005, 5251 PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000006, 5252 } PIPE_PHYPLL_PIXEL_RATE_SOURCE; 5253 5254 /* 5255 * PIPE_PIXEL_RATE_PLL_SOURCE enum 5256 */ 5257 5258 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE { 5259 PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000, 5260 PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001, 5261 } PIPE_PIXEL_RATE_PLL_SOURCE; 5262 5263 /* 5264 * DP_DTO_DS_DISABLE enum 5265 */ 5266 5267 typedef enum DP_DTO_DS_DISABLE { 5268 DP_DTO_DESPREAD_DISABLE = 0x00000000, 5269 DP_DTO_DESPREAD_ENABLE = 0x00000001, 5270 } DP_DTO_DS_DISABLE; 5271 5272 /* 5273 * OTG_ADD_PIXEL enum 5274 */ 5275 5276 typedef enum OTG_ADD_PIXEL { 5277 OTG_ADD_PIXEL_NOOP = 0x00000000, 5278 OTG_ADD_PIXEL_FORCE = 0x00000001, 5279 } OTG_ADD_PIXEL; 5280 5281 /* 5282 * OTG_DROP_PIXEL enum 5283 */ 5284 5285 typedef enum OTG_DROP_PIXEL { 5286 OTG_DROP_PIXEL_NOOP = 0x00000000, 5287 OTG_DROP_PIXEL_FORCE = 0x00000001, 5288 } OTG_DROP_PIXEL; 5289 5290 /* 5291 * SYMCLK_FE_FORCE_EN enum 5292 */ 5293 5294 typedef enum SYMCLK_FE_FORCE_EN { 5295 SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000, 5296 SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001, 5297 } SYMCLK_FE_FORCE_EN; 5298 5299 /* 5300 * SYMCLK_FE_FORCE_SRC enum 5301 */ 5302 5303 typedef enum SYMCLK_FE_FORCE_SRC { 5304 SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000, 5305 SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001, 5306 SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002, 5307 SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003, 5308 SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x00000004, 5309 SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x00000005, 5310 SYMCLK_FE_FORCE_SRC_RESERVED = 0x00000006, 5311 } SYMCLK_FE_FORCE_SRC; 5312 5313 /* 5314 * DVOACLK_COARSE_SKEW_CNTL enum 5315 */ 5316 5317 typedef enum DVOACLK_COARSE_SKEW_CNTL { 5318 DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, 5319 DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, 5320 DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, 5321 DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, 5322 DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004, 5323 DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005, 5324 DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006, 5325 DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007, 5326 DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008, 5327 DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009, 5328 DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a, 5329 DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b, 5330 DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c, 5331 DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d, 5332 DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e, 5333 DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f, 5334 DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010, 5335 DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011, 5336 DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012, 5337 DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013, 5338 DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014, 5339 DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015, 5340 DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016, 5341 DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017, 5342 DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018, 5343 DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019, 5344 DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a, 5345 DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b, 5346 DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c, 5347 DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d, 5348 DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e, 5349 } DVOACLK_COARSE_SKEW_CNTL; 5350 5351 /* 5352 * DVOACLK_FINE_SKEW_CNTL enum 5353 */ 5354 5355 typedef enum DVOACLK_FINE_SKEW_CNTL { 5356 DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, 5357 DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, 5358 DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, 5359 DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, 5360 DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004, 5361 DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005, 5362 DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006, 5363 DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007, 5364 } DVOACLK_FINE_SKEW_CNTL; 5365 5366 /* 5367 * DVOACLKD_IN_PHASE enum 5368 */ 5369 5370 typedef enum DVOACLKD_IN_PHASE { 5371 DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, 5372 DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001, 5373 } DVOACLKD_IN_PHASE; 5374 5375 /* 5376 * DVOACLKC_IN_PHASE enum 5377 */ 5378 5379 typedef enum DVOACLKC_IN_PHASE { 5380 DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, 5381 DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001, 5382 } DVOACLKC_IN_PHASE; 5383 5384 /* 5385 * DVOACLKC_MVP_IN_PHASE enum 5386 */ 5387 5388 typedef enum DVOACLKC_MVP_IN_PHASE { 5389 DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, 5390 DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001, 5391 } DVOACLKC_MVP_IN_PHASE; 5392 5393 /* 5394 * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum 5395 */ 5396 5397 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE { 5398 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000, 5399 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001, 5400 } DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; 5401 5402 /* 5403 * DCCG_AUDIO_DTO0_SOURCE_SEL enum 5404 */ 5405 5406 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL { 5407 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000, 5408 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001, 5409 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002, 5410 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003, 5411 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4 = 0x00000004, 5412 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5 = 0x00000005, 5413 DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000006, 5414 } DCCG_AUDIO_DTO0_SOURCE_SEL; 5415 5416 /* 5417 * DCCG_AUDIO_DTO_SEL enum 5418 */ 5419 5420 typedef enum DCCG_AUDIO_DTO_SEL { 5421 DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000, 5422 DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001, 5423 DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002, 5424 } DCCG_AUDIO_DTO_SEL; 5425 5426 /* 5427 * DCCG_AUDIO_DTO2_SOURCE_SEL enum 5428 */ 5429 5430 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL { 5431 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000, 5432 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x00000001, 5433 } DCCG_AUDIO_DTO2_SOURCE_SEL; 5434 5435 /* 5436 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum 5437 */ 5438 5439 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO { 5440 DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000, 5441 DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001, 5442 } DCCG_AUDIO_DTO_USE_512FBR_DTO; 5443 5444 /* 5445 * DISPCLK_FREQ_RAMP_DONE enum 5446 */ 5447 5448 typedef enum DISPCLK_FREQ_RAMP_DONE { 5449 DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000, 5450 DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001, 5451 } DISPCLK_FREQ_RAMP_DONE; 5452 5453 /* 5454 * DCCG_FIFO_ERRDET_RESET enum 5455 */ 5456 5457 typedef enum DCCG_FIFO_ERRDET_RESET { 5458 DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000, 5459 DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001, 5460 } DCCG_FIFO_ERRDET_RESET; 5461 5462 /* 5463 * DCCG_FIFO_ERRDET_STATE enum 5464 */ 5465 5466 typedef enum DCCG_FIFO_ERRDET_STATE { 5467 DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000, 5468 DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001, 5469 } DCCG_FIFO_ERRDET_STATE; 5470 5471 /* 5472 * DCCG_FIFO_ERRDET_OVR_EN enum 5473 */ 5474 5475 typedef enum DCCG_FIFO_ERRDET_OVR_EN { 5476 DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000, 5477 DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001, 5478 } DCCG_FIFO_ERRDET_OVR_EN; 5479 5480 /* 5481 * DISPCLK_CHG_FWD_CORR_DISABLE enum 5482 */ 5483 5484 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE { 5485 DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000, 5486 DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001, 5487 } DISPCLK_CHG_FWD_CORR_DISABLE; 5488 5489 /* 5490 * DC_MEM_GLOBAL_PWR_REQ_DIS enum 5491 */ 5492 5493 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS { 5494 DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000, 5495 DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001, 5496 } DC_MEM_GLOBAL_PWR_REQ_DIS; 5497 5498 /* 5499 * DCCG_PERF_RUN enum 5500 */ 5501 5502 typedef enum DCCG_PERF_RUN { 5503 DCCG_PERF_RUN_NOOP = 0x00000000, 5504 DCCG_PERF_RUN_START = 0x00000001, 5505 } DCCG_PERF_RUN; 5506 5507 /* 5508 * DCCG_PERF_MODE_VSYNC enum 5509 */ 5510 5511 typedef enum DCCG_PERF_MODE_VSYNC { 5512 DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000, 5513 DCCG_PERF_MODE_VSYNC_START = 0x00000001, 5514 } DCCG_PERF_MODE_VSYNC; 5515 5516 /* 5517 * DCCG_PERF_MODE_HSYNC enum 5518 */ 5519 5520 typedef enum DCCG_PERF_MODE_HSYNC { 5521 DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000, 5522 DCCG_PERF_MODE_HSYNC_START = 0x00000001, 5523 } DCCG_PERF_MODE_HSYNC; 5524 5525 /* 5526 * DCCG_PERF_OTG_SELECT enum 5527 */ 5528 5529 typedef enum DCCG_PERF_OTG_SELECT { 5530 DCCG_PERF_SEL_OTG0 = 0x00000000, 5531 DCCG_PERF_SEL_OTG1 = 0x00000001, 5532 DCCG_PERF_SEL_OTG2 = 0x00000002, 5533 DCCG_PERF_SEL_OTG3 = 0x00000003, 5534 DCCG_PERF_SEL_OTG4 = 0x00000004, 5535 DCCG_PERF_SEL_OTG5 = 0x00000005, 5536 DCCG_PERF_SEL_RESERVED = 0x00000006, 5537 } DCCG_PERF_OTG_SELECT; 5538 5539 /* 5540 * CLOCK_BRANCH_SOFT_RESET enum 5541 */ 5542 5543 typedef enum CLOCK_BRANCH_SOFT_RESET { 5544 CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000, 5545 CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001, 5546 } CLOCK_BRANCH_SOFT_RESET; 5547 5548 /* 5549 * PLL_CFG_IF_SOFT_RESET enum 5550 */ 5551 5552 typedef enum PLL_CFG_IF_SOFT_RESET { 5553 PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000, 5554 PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001, 5555 } PLL_CFG_IF_SOFT_RESET; 5556 5557 /* 5558 * DVO_ENABLE_RST enum 5559 */ 5560 5561 typedef enum DVO_ENABLE_RST { 5562 DVO_ENABLE_RST_DISABLE = 0x00000000, 5563 DVO_ENABLE_RST_ENABLE = 0x00000001, 5564 } DVO_ENABLE_RST; 5565 5566 /* 5567 * DS_JITTER_COUNT_SRC_SEL enum 5568 */ 5569 5570 typedef enum DS_JITTER_COUNT_SRC_SEL { 5571 DS_JITTER_COUNT_SRC_SEL0 = 0x00000000, 5572 DS_JITTER_COUNT_SRC_SEL1 = 0x00000001, 5573 } DS_JITTER_COUNT_SRC_SEL; 5574 5575 /* 5576 * DIO_FIFO_ERROR enum 5577 */ 5578 5579 typedef enum DIO_FIFO_ERROR { 5580 DIO_FIFO_ERROR_00 = 0x00000000, 5581 DIO_FIFO_ERROR_01 = 0x00000001, 5582 DIO_FIFO_ERROR_10 = 0x00000002, 5583 DIO_FIFO_ERROR_11 = 0x00000003, 5584 } DIO_FIFO_ERROR; 5585 5586 /* 5587 * VSYNC_CNT_REFCLK_SEL enum 5588 */ 5589 5590 typedef enum VSYNC_CNT_REFCLK_SEL { 5591 VSYNC_CNT_REFCLK_SEL_0 = 0x00000000, 5592 VSYNC_CNT_REFCLK_SEL_1 = 0x00000001, 5593 } VSYNC_CNT_REFCLK_SEL; 5594 5595 /* 5596 * VSYNC_CNT_RESET_SEL enum 5597 */ 5598 5599 typedef enum VSYNC_CNT_RESET_SEL { 5600 VSYNC_CNT_RESET_SEL_0 = 0x00000000, 5601 VSYNC_CNT_RESET_SEL_1 = 0x00000001, 5602 } VSYNC_CNT_RESET_SEL; 5603 5604 /* 5605 * VSYNC_CNT_LATCH_MASK enum 5606 */ 5607 5608 typedef enum VSYNC_CNT_LATCH_MASK { 5609 VSYNC_CNT_LATCH_MASK_0 = 0x00000000, 5610 VSYNC_CNT_LATCH_MASK_1 = 0x00000001, 5611 } VSYNC_CNT_LATCH_MASK; 5612 5613 /******************************************************* 5614 * HPD Enums 5615 *******************************************************/ 5616 5617 /* 5618 * HPD_INT_CONTROL_ACK enum 5619 */ 5620 5621 typedef enum HPD_INT_CONTROL_ACK { 5622 HPD_INT_CONTROL_ACK_0 = 0x00000000, 5623 HPD_INT_CONTROL_ACK_1 = 0x00000001, 5624 } HPD_INT_CONTROL_ACK; 5625 5626 /* 5627 * HPD_INT_CONTROL_POLARITY enum 5628 */ 5629 5630 typedef enum HPD_INT_CONTROL_POLARITY { 5631 HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000, 5632 HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001, 5633 } HPD_INT_CONTROL_POLARITY; 5634 5635 /* 5636 * HPD_INT_CONTROL_RX_INT_ACK enum 5637 */ 5638 5639 typedef enum HPD_INT_CONTROL_RX_INT_ACK { 5640 HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000, 5641 HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001, 5642 } HPD_INT_CONTROL_RX_INT_ACK; 5643 5644 /******************************************************* 5645 * DP Enums 5646 *******************************************************/ 5647 5648 /* 5649 * DP_MSO_NUM_OF_SST_LINKS enum 5650 */ 5651 5652 typedef enum DP_MSO_NUM_OF_SST_LINKS { 5653 DP_MSO_ONE_SSTLINK = 0x00000000, 5654 DP_MSO_TWO_SSTLINK = 0x00000001, 5655 DP_MSO_FOUR_SSTLINK = 0x00000002, 5656 } DP_MSO_NUM_OF_SST_LINKS; 5657 5658 /* 5659 * DP_SYNC_POLARITY enum 5660 */ 5661 5662 typedef enum DP_SYNC_POLARITY { 5663 DP_SYNC_POLARITY_ACTIVE_HIGH = 0x00000000, 5664 DP_SYNC_POLARITY_ACTIVE_LOW = 0x00000001, 5665 } DP_SYNC_POLARITY; 5666 5667 /* 5668 * DP_COMBINE_PIXEL_NUM enum 5669 */ 5670 5671 typedef enum DP_COMBINE_PIXEL_NUM { 5672 DP_COMBINE_ONE_PIXEL = 0x00000000, 5673 DP_COMBINE_TWO_PIXEL = 0x00000001, 5674 DP_COMBINE_FOUR_PIXEL = 0x00000002, 5675 } DP_COMBINE_PIXEL_NUM; 5676 5677 /* 5678 * DP_LINK_TRAINING_COMPLETE enum 5679 */ 5680 5681 typedef enum DP_LINK_TRAINING_COMPLETE { 5682 DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000, 5683 DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001, 5684 } DP_LINK_TRAINING_COMPLETE; 5685 5686 /* 5687 * DP_EMBEDDED_PANEL_MODE enum 5688 */ 5689 5690 typedef enum DP_EMBEDDED_PANEL_MODE { 5691 DP_EXTERNAL_PANEL = 0x00000000, 5692 DP_EMBEDDED_PANEL = 0x00000001, 5693 } DP_EMBEDDED_PANEL_MODE; 5694 5695 /* 5696 * DP_PIXEL_ENCODING enum 5697 */ 5698 5699 typedef enum DP_PIXEL_ENCODING { 5700 DP_PIXEL_ENCODING_RGB444 = 0x00000000, 5701 DP_PIXEL_ENCODING_YCBCR422 = 0x00000001, 5702 DP_PIXEL_ENCODING_YCBCR444 = 0x00000002, 5703 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003, 5704 DP_PIXEL_ENCODING_Y_ONLY = 0x00000004, 5705 DP_PIXEL_ENCODING_YCBCR420 = 0x00000005, 5706 DP_PIXEL_ENCODING_RESERVED = 0x00000006, 5707 } DP_PIXEL_ENCODING; 5708 5709 /* 5710 * DP_COMPONENT_DEPTH enum 5711 */ 5712 5713 typedef enum DP_COMPONENT_DEPTH { 5714 DP_COMPONENT_DEPTH_6BPC = 0x00000000, 5715 DP_COMPONENT_DEPTH_8BPC = 0x00000001, 5716 DP_COMPONENT_DEPTH_10BPC = 0x00000002, 5717 DP_COMPONENT_DEPTH_12BPC = 0x00000003, 5718 DP_COMPONENT_DEPTH_16BPC_RESERVED = 0x00000004, 5719 DP_COMPONENT_DEPTH_RESERVED = 0x00000005, 5720 } DP_COMPONENT_DEPTH; 5721 5722 /* 5723 * DP_UDI_LANES enum 5724 */ 5725 5726 typedef enum DP_UDI_LANES { 5727 DP_UDI_1_LANE = 0x00000000, 5728 DP_UDI_2_LANES = 0x00000001, 5729 DP_UDI_LANES_RESERVED = 0x00000002, 5730 DP_UDI_4_LANES = 0x00000003, 5731 } DP_UDI_LANES; 5732 5733 /* 5734 * DP_VID_STREAM_DIS_DEFER enum 5735 */ 5736 5737 typedef enum DP_VID_STREAM_DIS_DEFER { 5738 DP_VID_STREAM_DIS_NO_DEFER = 0x00000000, 5739 DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001, 5740 DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002, 5741 } DP_VID_STREAM_DIS_DEFER; 5742 5743 /* 5744 * DP_STEER_OVERFLOW_ACK enum 5745 */ 5746 5747 typedef enum DP_STEER_OVERFLOW_ACK { 5748 DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000, 5749 DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, 5750 } DP_STEER_OVERFLOW_ACK; 5751 5752 /* 5753 * DP_STEER_OVERFLOW_MASK enum 5754 */ 5755 5756 typedef enum DP_STEER_OVERFLOW_MASK { 5757 DP_STEER_OVERFLOW_MASKED = 0x00000000, 5758 DP_STEER_OVERFLOW_UNMASK = 0x00000001, 5759 } DP_STEER_OVERFLOW_MASK; 5760 5761 /* 5762 * DP_TU_OVERFLOW_ACK enum 5763 */ 5764 5765 typedef enum DP_TU_OVERFLOW_ACK { 5766 DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000, 5767 DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, 5768 } DP_TU_OVERFLOW_ACK; 5769 5770 /* 5771 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum 5772 */ 5773 5774 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { 5775 DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000, 5776 DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001, 5777 } DP_VID_M_N_DOUBLE_BUFFER_MODE; 5778 5779 /* 5780 * DP_VID_M_N_GEN_EN enum 5781 */ 5782 5783 typedef enum DP_VID_M_N_GEN_EN { 5784 DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000, 5785 DP_VID_M_N_CALC_AUTO = 0x00000001, 5786 } DP_VID_M_N_GEN_EN; 5787 5788 /* 5789 * DP_VID_N_MUL enum 5790 */ 5791 5792 typedef enum DP_VID_N_MUL { 5793 DP_VID_M_1X_INPUT_PIXEL_RATE = 0x00000000, 5794 DP_VID_M_2X_INPUT_PIXEL_RATE = 0x00000001, 5795 DP_VID_M_4X_INPUT_PIXEL_RATE = 0x00000002, 5796 DP_VID_M_8X_INPUT_PIXEL_RATE = 0x00000003, 5797 } DP_VID_N_MUL; 5798 5799 /* 5800 * DP_VID_ENHANCED_FRAME_MODE enum 5801 */ 5802 5803 typedef enum DP_VID_ENHANCED_FRAME_MODE { 5804 VID_NORMAL_FRAME_MODE = 0x00000000, 5805 VID_ENHANCED_MODE = 0x00000001, 5806 } DP_VID_ENHANCED_FRAME_MODE; 5807 5808 /* 5809 * DP_VID_VBID_FIELD_POL enum 5810 */ 5811 5812 typedef enum DP_VID_VBID_FIELD_POL { 5813 DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000, 5814 DP_VID_VBID_FIELD_POL_INV = 0x00000001, 5815 } DP_VID_VBID_FIELD_POL; 5816 5817 /* 5818 * DP_VID_STREAM_DISABLE_ACK enum 5819 */ 5820 5821 typedef enum DP_VID_STREAM_DISABLE_ACK { 5822 ID_STREAM_DISABLE_NO_ACK = 0x00000000, 5823 ID_STREAM_DISABLE_ACKED = 0x00000001, 5824 } DP_VID_STREAM_DISABLE_ACK; 5825 5826 /* 5827 * DP_VID_STREAM_DISABLE_MASK enum 5828 */ 5829 5830 typedef enum DP_VID_STREAM_DISABLE_MASK { 5831 VID_STREAM_DISABLE_MASKED = 0x00000000, 5832 VID_STREAM_DISABLE_UNMASK = 0x00000001, 5833 } DP_VID_STREAM_DISABLE_MASK; 5834 5835 /* 5836 * DPHY_ATEST_SEL_LANE0 enum 5837 */ 5838 5839 typedef enum DPHY_ATEST_SEL_LANE0 { 5840 DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000, 5841 DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001, 5842 } DPHY_ATEST_SEL_LANE0; 5843 5844 /* 5845 * DPHY_ATEST_SEL_LANE1 enum 5846 */ 5847 5848 typedef enum DPHY_ATEST_SEL_LANE1 { 5849 DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000, 5850 DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001, 5851 } DPHY_ATEST_SEL_LANE1; 5852 5853 /* 5854 * DPHY_ATEST_SEL_LANE2 enum 5855 */ 5856 5857 typedef enum DPHY_ATEST_SEL_LANE2 { 5858 DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000, 5859 DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001, 5860 } DPHY_ATEST_SEL_LANE2; 5861 5862 /* 5863 * DPHY_ATEST_SEL_LANE3 enum 5864 */ 5865 5866 typedef enum DPHY_ATEST_SEL_LANE3 { 5867 DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000, 5868 DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001, 5869 } DPHY_ATEST_SEL_LANE3; 5870 5871 /* 5872 * DPHY_BYPASS enum 5873 */ 5874 5875 typedef enum DPHY_BYPASS { 5876 DPHY_8B10B_OUTPUT = 0x00000000, 5877 DPHY_DBG_OUTPUT = 0x00000001, 5878 } DPHY_BYPASS; 5879 5880 /* 5881 * DPHY_SKEW_BYPASS enum 5882 */ 5883 5884 typedef enum DPHY_SKEW_BYPASS { 5885 DPHY_WITH_SKEW = 0x00000000, 5886 DPHY_NO_SKEW = 0x00000001, 5887 } DPHY_SKEW_BYPASS; 5888 5889 /* 5890 * DPHY_TRAINING_PATTERN_SEL enum 5891 */ 5892 5893 typedef enum DPHY_TRAINING_PATTERN_SEL { 5894 DPHY_TRAINING_PATTERN_1 = 0x00000000, 5895 DPHY_TRAINING_PATTERN_2 = 0x00000001, 5896 DPHY_TRAINING_PATTERN_3 = 0x00000002, 5897 DPHY_TRAINING_PATTERN_4 = 0x00000003, 5898 } DPHY_TRAINING_PATTERN_SEL; 5899 5900 /* 5901 * DPHY_8B10B_RESET enum 5902 */ 5903 5904 typedef enum DPHY_8B10B_RESET { 5905 DPHY_8B10B_NOT_RESET = 0x00000000, 5906 DPHY_8B10B_RESETET = 0x00000001, 5907 } DPHY_8B10B_RESET; 5908 5909 /* 5910 * DP_DPHY_8B10B_EXT_DISP enum 5911 */ 5912 5913 typedef enum DP_DPHY_8B10B_EXT_DISP { 5914 DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000, 5915 DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001, 5916 } DP_DPHY_8B10B_EXT_DISP; 5917 5918 /* 5919 * DPHY_8B10B_CUR_DISP enum 5920 */ 5921 5922 typedef enum DPHY_8B10B_CUR_DISP { 5923 DPHY_8B10B_CUR_DISP_ZERO = 0x00000000, 5924 DPHY_8B10B_CUR_DISP_ONE = 0x00000001, 5925 } DPHY_8B10B_CUR_DISP; 5926 5927 /* 5928 * DPHY_PRBS_EN enum 5929 */ 5930 5931 typedef enum DPHY_PRBS_EN { 5932 DPHY_PRBS_DISABLE = 0x00000000, 5933 DPHY_PRBS_ENABLE = 0x00000001, 5934 } DPHY_PRBS_EN; 5935 5936 /* 5937 * DPHY_PRBS_SEL enum 5938 */ 5939 5940 typedef enum DPHY_PRBS_SEL { 5941 DPHY_PRBS7_SELECTED = 0x00000000, 5942 DPHY_PRBS23_SELECTED = 0x00000001, 5943 DPHY_PRBS11_SELECTED = 0x00000002, 5944 } DPHY_PRBS_SEL; 5945 5946 /* 5947 * DPHY_FEC_ENABLE enum 5948 */ 5949 5950 typedef enum DPHY_FEC_ENABLE { 5951 DPHY_FEC_DISABLED = 0x00000000, 5952 DPHY_FEC_ENABLED = 0x00000001, 5953 } DPHY_FEC_ENABLE; 5954 5955 /* 5956 * FEC_ACTIVE_STATUS enum 5957 */ 5958 5959 typedef enum FEC_ACTIVE_STATUS { 5960 DPHY_FEC_NOT_ACTIVE = 0x00000000, 5961 DPHY_FEC_ACTIVE = 0x00000001, 5962 } FEC_ACTIVE_STATUS; 5963 5964 /* 5965 * DPHY_FEC_READY enum 5966 */ 5967 5968 typedef enum DPHY_FEC_READY { 5969 DPHY_FEC_READY_EN = 0x00000000, 5970 DPHY_FEC_READY_DIS = 0x00000001, 5971 } DPHY_FEC_READY; 5972 5973 /* 5974 * DPHY_LOAD_BS_COUNT_START enum 5975 */ 5976 5977 typedef enum DPHY_LOAD_BS_COUNT_START { 5978 DPHY_LOAD_BS_COUNT_STARTED = 0x00000000, 5979 DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001, 5980 } DPHY_LOAD_BS_COUNT_START; 5981 5982 /* 5983 * DPHY_CRC_EN enum 5984 */ 5985 5986 typedef enum DPHY_CRC_EN { 5987 DPHY_CRC_DISABLED = 0x00000000, 5988 DPHY_CRC_ENABLED = 0x00000001, 5989 } DPHY_CRC_EN; 5990 5991 /* 5992 * DPHY_CRC_CONT_EN enum 5993 */ 5994 5995 typedef enum DPHY_CRC_CONT_EN { 5996 DPHY_CRC_ONE_SHOT = 0x00000000, 5997 DPHY_CRC_CONTINUOUS = 0x00000001, 5998 } DPHY_CRC_CONT_EN; 5999 6000 /* 6001 * DPHY_CRC_FIELD enum 6002 */ 6003 6004 typedef enum DPHY_CRC_FIELD { 6005 DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000, 6006 DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001, 6007 } DPHY_CRC_FIELD; 6008 6009 /* 6010 * DPHY_CRC_SEL enum 6011 */ 6012 6013 typedef enum DPHY_CRC_SEL { 6014 DPHY_CRC_LANE0_SELECTED = 0x00000000, 6015 DPHY_CRC_LANE1_SELECTED = 0x00000001, 6016 DPHY_CRC_LANE2_SELECTED = 0x00000002, 6017 DPHY_CRC_LANE3_SELECTED = 0x00000003, 6018 } DPHY_CRC_SEL; 6019 6020 /* 6021 * DPHY_RX_FAST_TRAINING_CAPABLE enum 6022 */ 6023 6024 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { 6025 DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000, 6026 DPHY_FAST_TRAINING_CAPABLE = 0x00000001, 6027 } DPHY_RX_FAST_TRAINING_CAPABLE; 6028 6029 /* 6030 * DP_SEC_COLLISION_ACK enum 6031 */ 6032 6033 typedef enum DP_SEC_COLLISION_ACK { 6034 DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000, 6035 DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001, 6036 } DP_SEC_COLLISION_ACK; 6037 6038 /* 6039 * DP_SEC_AUDIO_MUTE enum 6040 */ 6041 6042 typedef enum DP_SEC_AUDIO_MUTE { 6043 DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000, 6044 DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001, 6045 } DP_SEC_AUDIO_MUTE; 6046 6047 /* 6048 * DP_SEC_TIMESTAMP_MODE enum 6049 */ 6050 6051 typedef enum DP_SEC_TIMESTAMP_MODE { 6052 DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000, 6053 DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001, 6054 } DP_SEC_TIMESTAMP_MODE; 6055 6056 /* 6057 * DP_SEC_ASP_PRIORITY enum 6058 */ 6059 6060 typedef enum DP_SEC_ASP_PRIORITY { 6061 DP_SEC_ASP_LOW_PRIORITY = 0x00000000, 6062 DP_SEC_ASP_HIGH_PRIORITY = 0x00000001, 6063 } DP_SEC_ASP_PRIORITY; 6064 6065 /* 6066 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum 6067 */ 6068 6069 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { 6070 DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000, 6071 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001, 6072 } DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; 6073 6074 /* 6075 * DP_MSE_SAT_UPDATE_ACT enum 6076 */ 6077 6078 typedef enum DP_MSE_SAT_UPDATE_ACT { 6079 DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000, 6080 DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001, 6081 DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002, 6082 } DP_MSE_SAT_UPDATE_ACT; 6083 6084 /* 6085 * DP_MSE_LINK_LINE enum 6086 */ 6087 6088 typedef enum DP_MSE_LINK_LINE { 6089 DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000, 6090 DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001, 6091 DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002, 6092 DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003, 6093 } DP_MSE_LINK_LINE; 6094 6095 /* 6096 * DP_MSE_BLANK_CODE enum 6097 */ 6098 6099 typedef enum DP_MSE_BLANK_CODE { 6100 DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000, 6101 DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001, 6102 } DP_MSE_BLANK_CODE; 6103 6104 /* 6105 * DP_MSE_TIMESTAMP_MODE enum 6106 */ 6107 6108 typedef enum DP_MSE_TIMESTAMP_MODE { 6109 DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000, 6110 DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001, 6111 } DP_MSE_TIMESTAMP_MODE; 6112 6113 /* 6114 * DP_MSE_ZERO_ENCODER enum 6115 */ 6116 6117 typedef enum DP_MSE_ZERO_ENCODER { 6118 DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000, 6119 DP_MSE_ZERO_FE_ENCODER = 0x00000001, 6120 } DP_MSE_ZERO_ENCODER; 6121 6122 /* 6123 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum 6124 */ 6125 6126 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { 6127 DP_DPHY_HBR2_PASS_THROUGH = 0x00000000, 6128 DP_DPHY_HBR2_PATTERN_1 = 0x00000001, 6129 DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002, 6130 DP_DPHY_HBR2_PATTERN_3 = 0x00000003, 6131 DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006, 6132 } DP_DPHY_HBR2_PATTERN_CONTROL_MODE; 6133 6134 /* 6135 * DPHY_CRC_MST_PHASE_ERROR_ACK enum 6136 */ 6137 6138 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { 6139 DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000, 6140 DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001, 6141 } DPHY_CRC_MST_PHASE_ERROR_ACK; 6142 6143 /* 6144 * DPHY_SW_FAST_TRAINING_START enum 6145 */ 6146 6147 typedef enum DPHY_SW_FAST_TRAINING_START { 6148 DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000, 6149 DPHY_SW_FAST_TRAINING_STARTED = 0x00000001, 6150 } DPHY_SW_FAST_TRAINING_START; 6151 6152 /* 6153 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum 6154 */ 6155 6156 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { 6157 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000, 6158 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001, 6159 } DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; 6160 6161 /* 6162 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum 6163 */ 6164 6165 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { 6166 DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000, 6167 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001, 6168 } DP_DPHY_FAST_TRAINING_COMPLETE_MASK; 6169 6170 /* 6171 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum 6172 */ 6173 6174 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { 6175 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000, 6176 DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001, 6177 } DP_DPHY_FAST_TRAINING_COMPLETE_ACK; 6178 6179 /* 6180 * DP_MSA_V_TIMING_OVERRIDE_EN enum 6181 */ 6182 6183 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { 6184 MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000, 6185 MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001, 6186 } DP_MSA_V_TIMING_OVERRIDE_EN; 6187 6188 /* 6189 * DP_SEC_GSP0_PRIORITY enum 6190 */ 6191 6192 typedef enum DP_SEC_GSP0_PRIORITY { 6193 SEC_GSP0_PRIORITY_LOW = 0x00000000, 6194 SEC_GSP0_PRIORITY_HIGH = 0x00000001, 6195 } DP_SEC_GSP0_PRIORITY; 6196 6197 /* 6198 * DP_SEC_GSP_SEND enum 6199 */ 6200 6201 typedef enum DP_SEC_GSP_SEND { 6202 NOT_SENT = 0x00000000, 6203 FORCE_SENT = 0x00000001, 6204 } DP_SEC_GSP_SEND; 6205 6206 /* 6207 * DP_SEC_GSP_SEND_ANY_LINE enum 6208 */ 6209 6210 typedef enum DP_SEC_GSP_SEND_ANY_LINE { 6211 SEND_AT_LINK_NUMBER = 0x00000000, 6212 SEND_AT_EARLIEST_TIME = 0x00000001, 6213 } DP_SEC_GSP_SEND_ANY_LINE; 6214 6215 /* 6216 * DP_SEC_LINE_REFERENCE enum 6217 */ 6218 6219 typedef enum DP_SEC_LINE_REFERENCE { 6220 REFER_TO_DP_SOF = 0x00000000, 6221 REFER_TO_OTG_SOF = 0x00000001, 6222 } DP_SEC_LINE_REFERENCE; 6223 6224 /* 6225 * DP_SEC_GSP_SEND_PPS enum 6226 */ 6227 6228 typedef enum DP_SEC_GSP_SEND_PPS { 6229 SEND_NORMAL_PACKET = 0x00000000, 6230 SEND_PPS_PACKET = 0x00000001, 6231 } DP_SEC_GSP_SEND_PPS; 6232 6233 /* 6234 * DP_ML_PHY_SEQ_MODE enum 6235 */ 6236 6237 typedef enum DP_ML_PHY_SEQ_MODE { 6238 DP_ML_PHY_SEQ_LINE_NUM = 0x00000000, 6239 DP_ML_PHY_SEQ_IMMEDIATE = 0x00000001, 6240 } DP_ML_PHY_SEQ_MODE; 6241 6242 /* 6243 * DP_LINK_TRAINING_SWITCH_MODE enum 6244 */ 6245 6246 typedef enum DP_LINK_TRAINING_SWITCH_MODE { 6247 DP_LINK_TRAINING_SWITCH_TO_IDLE = 0x00000000, 6248 DP_LINK_TRAINING_SWITCH_TO_VIDEO = 0x00000001, 6249 } DP_LINK_TRAINING_SWITCH_MODE; 6250 6251 /* 6252 * DP_DSC_MODE enum 6253 */ 6254 6255 typedef enum DP_DSC_MODE { 6256 DP_DSC_DISABLE = 0x00000000, 6257 DP_DSC_444_SIMPLE_422 = 0x00000001, 6258 DP_DSC_NATIVE_422_420 = 0x00000002, 6259 } DP_DSC_MODE; 6260 6261 /******************************************************* 6262 * DIG Enums 6263 *******************************************************/ 6264 6265 /* 6266 * HDMI_KEEPOUT_MODE enum 6267 */ 6268 6269 typedef enum HDMI_KEEPOUT_MODE { 6270 HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000, 6271 HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001, 6272 } HDMI_KEEPOUT_MODE; 6273 6274 /* 6275 * HDMI_CLOCK_CHANNEL_RATE enum 6276 */ 6277 6278 typedef enum HDMI_CLOCK_CHANNEL_RATE { 6279 HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000, 6280 HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001, 6281 } HDMI_CLOCK_CHANNEL_RATE; 6282 6283 /* 6284 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum 6285 */ 6286 6287 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { 6288 HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000, 6289 HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001, 6290 } HDMI_NO_EXTRA_NULL_PACKET_FILLED; 6291 6292 /* 6293 * HDMI_PACKET_GEN_VERSION enum 6294 */ 6295 6296 typedef enum HDMI_PACKET_GEN_VERSION { 6297 HDMI_PACKET_GEN_VERSION_OLD = 0x00000000, 6298 HDMI_PACKET_GEN_VERSION_NEW = 0x00000001, 6299 } HDMI_PACKET_GEN_VERSION; 6300 6301 /* 6302 * HDMI_ERROR_ACK enum 6303 */ 6304 6305 typedef enum HDMI_ERROR_ACK { 6306 HDMI_ERROR_ACK_INT = 0x00000000, 6307 HDMI_ERROR_NOT_ACK = 0x00000001, 6308 } HDMI_ERROR_ACK; 6309 6310 /* 6311 * HDMI_ERROR_MASK enum 6312 */ 6313 6314 typedef enum HDMI_ERROR_MASK { 6315 HDMI_ERROR_MASK_INT = 0x00000000, 6316 HDMI_ERROR_NOT_MASK = 0x00000001, 6317 } HDMI_ERROR_MASK; 6318 6319 /* 6320 * HDMI_DEEP_COLOR_DEPTH enum 6321 */ 6322 6323 typedef enum HDMI_DEEP_COLOR_DEPTH { 6324 HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000, 6325 HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001, 6326 HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002, 6327 HDMI_DEEP_COLOR_DEPTH_48BPP = 0x00000003, 6328 } HDMI_DEEP_COLOR_DEPTH; 6329 6330 /* 6331 * HDMI_AUDIO_DELAY_EN enum 6332 */ 6333 6334 typedef enum HDMI_AUDIO_DELAY_EN { 6335 HDMI_AUDIO_DELAY_DISABLE = 0x00000000, 6336 HDMI_AUDIO_DELAY_58CLK = 0x00000001, 6337 HDMI_AUDIO_DELAY_56CLK = 0x00000002, 6338 HDMI_AUDIO_DELAY_RESERVED = 0x00000003, 6339 } HDMI_AUDIO_DELAY_EN; 6340 6341 /* 6342 * HDMI_AUDIO_SEND_MAX_PACKETS enum 6343 */ 6344 6345 typedef enum HDMI_AUDIO_SEND_MAX_PACKETS { 6346 HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000, 6347 HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001, 6348 } HDMI_AUDIO_SEND_MAX_PACKETS; 6349 6350 /* 6351 * HDMI_ACR_SEND enum 6352 */ 6353 6354 typedef enum HDMI_ACR_SEND { 6355 HDMI_ACR_NOT_SEND = 0x00000000, 6356 HDMI_ACR_PKT_SEND = 0x00000001, 6357 } HDMI_ACR_SEND; 6358 6359 /* 6360 * HDMI_ACR_CONT enum 6361 */ 6362 6363 typedef enum HDMI_ACR_CONT { 6364 HDMI_ACR_CONT_DISABLE = 0x00000000, 6365 HDMI_ACR_CONT_ENABLE = 0x00000001, 6366 } HDMI_ACR_CONT; 6367 6368 /* 6369 * HDMI_ACR_SELECT enum 6370 */ 6371 6372 typedef enum HDMI_ACR_SELECT { 6373 HDMI_ACR_SELECT_HW = 0x00000000, 6374 HDMI_ACR_SELECT_32K = 0x00000001, 6375 HDMI_ACR_SELECT_44K = 0x00000002, 6376 HDMI_ACR_SELECT_48K = 0x00000003, 6377 } HDMI_ACR_SELECT; 6378 6379 /* 6380 * HDMI_ACR_SOURCE enum 6381 */ 6382 6383 typedef enum HDMI_ACR_SOURCE { 6384 HDMI_ACR_SOURCE_HW = 0x00000000, 6385 HDMI_ACR_SOURCE_SW = 0x00000001, 6386 } HDMI_ACR_SOURCE; 6387 6388 /* 6389 * HDMI_ACR_N_MULTIPLE enum 6390 */ 6391 6392 typedef enum HDMI_ACR_N_MULTIPLE { 6393 HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000, 6394 HDMI_ACR_1_MULTIPLE = 0x00000001, 6395 HDMI_ACR_2_MULTIPLE = 0x00000002, 6396 HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003, 6397 HDMI_ACR_4_MULTIPLE = 0x00000004, 6398 HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005, 6399 HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006, 6400 HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007, 6401 } HDMI_ACR_N_MULTIPLE; 6402 6403 /* 6404 * HDMI_ACR_AUDIO_PRIORITY enum 6405 */ 6406 6407 typedef enum HDMI_ACR_AUDIO_PRIORITY { 6408 HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000, 6409 HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001, 6410 } HDMI_ACR_AUDIO_PRIORITY; 6411 6412 /* 6413 * HDMI_NULL_SEND enum 6414 */ 6415 6416 typedef enum HDMI_NULL_SEND { 6417 HDMI_NULL_NOT_SEND = 0x00000000, 6418 HDMI_NULL_PKT_SEND = 0x00000001, 6419 } HDMI_NULL_SEND; 6420 6421 /* 6422 * HDMI_GC_SEND enum 6423 */ 6424 6425 typedef enum HDMI_GC_SEND { 6426 HDMI_GC_NOT_SEND = 0x00000000, 6427 HDMI_GC_PKT_SEND = 0x00000001, 6428 } HDMI_GC_SEND; 6429 6430 /* 6431 * HDMI_GC_CONT enum 6432 */ 6433 6434 typedef enum HDMI_GC_CONT { 6435 HDMI_GC_CONT_DISABLE = 0x00000000, 6436 HDMI_GC_CONT_ENABLE = 0x00000001, 6437 } HDMI_GC_CONT; 6438 6439 /* 6440 * HDMI_ISRC_SEND enum 6441 */ 6442 6443 typedef enum HDMI_ISRC_SEND { 6444 HDMI_ISRC_NOT_SEND = 0x00000000, 6445 HDMI_ISRC_PKT_SEND = 0x00000001, 6446 } HDMI_ISRC_SEND; 6447 6448 /* 6449 * HDMI_ISRC_CONT enum 6450 */ 6451 6452 typedef enum HDMI_ISRC_CONT { 6453 HDMI_ISRC_CONT_DISABLE = 0x00000000, 6454 HDMI_ISRC_CONT_ENABLE = 0x00000001, 6455 } HDMI_ISRC_CONT; 6456 6457 /* 6458 * HDMI_AUDIO_INFO_SEND enum 6459 */ 6460 6461 typedef enum HDMI_AUDIO_INFO_SEND { 6462 HDMI_AUDIO_INFO_NOT_SEND = 0x00000000, 6463 HDMI_AUDIO_INFO_PKT_SEND = 0x00000001, 6464 } HDMI_AUDIO_INFO_SEND; 6465 6466 /* 6467 * HDMI_AUDIO_INFO_CONT enum 6468 */ 6469 6470 typedef enum HDMI_AUDIO_INFO_CONT { 6471 HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000, 6472 HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001, 6473 } HDMI_AUDIO_INFO_CONT; 6474 6475 /* 6476 * HDMI_MPEG_INFO_SEND enum 6477 */ 6478 6479 typedef enum HDMI_MPEG_INFO_SEND { 6480 HDMI_MPEG_INFO_NOT_SEND = 0x00000000, 6481 HDMI_MPEG_INFO_PKT_SEND = 0x00000001, 6482 } HDMI_MPEG_INFO_SEND; 6483 6484 /* 6485 * HDMI_MPEG_INFO_CONT enum 6486 */ 6487 6488 typedef enum HDMI_MPEG_INFO_CONT { 6489 HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000, 6490 HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001, 6491 } HDMI_MPEG_INFO_CONT; 6492 6493 /* 6494 * HDMI_GENERIC_SEND enum 6495 */ 6496 6497 typedef enum HDMI_GENERIC_SEND { 6498 HDMI_GENERIC_NOT_SEND = 0x00000000, 6499 HDMI_GENERIC_PKT_SEND = 0x00000001, 6500 } HDMI_GENERIC_SEND; 6501 6502 /* 6503 * HDMI_GENERIC_CONT enum 6504 */ 6505 6506 typedef enum HDMI_GENERIC_CONT { 6507 HDMI_GENERIC_CONT_DISABLE = 0x00000000, 6508 HDMI_GENERIC_CONT_ENABLE = 0x00000001, 6509 } HDMI_GENERIC_CONT; 6510 6511 /* 6512 * HDMI_GC_AVMUTE_CONT enum 6513 */ 6514 6515 typedef enum HDMI_GC_AVMUTE_CONT { 6516 HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000, 6517 HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001, 6518 } HDMI_GC_AVMUTE_CONT; 6519 6520 /* 6521 * HDMI_PACKING_PHASE_OVERRIDE enum 6522 */ 6523 6524 typedef enum HDMI_PACKING_PHASE_OVERRIDE { 6525 HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000, 6526 HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001, 6527 } HDMI_PACKING_PHASE_OVERRIDE; 6528 6529 /* 6530 * TMDS_PIXEL_ENCODING enum 6531 */ 6532 6533 typedef enum TMDS_PIXEL_ENCODING { 6534 TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000, 6535 TMDS_PIXEL_ENCODING_422 = 0x00000001, 6536 } TMDS_PIXEL_ENCODING; 6537 6538 /* 6539 * TMDS_COLOR_FORMAT enum 6540 */ 6541 6542 typedef enum TMDS_COLOR_FORMAT { 6543 TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000, 6544 TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001, 6545 TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002, 6546 TMDS_COLOR_FORMAT_RESERVED = 0x00000003, 6547 } TMDS_COLOR_FORMAT; 6548 6549 /* 6550 * TMDS_STEREOSYNC_CTL_SEL_REG enum 6551 */ 6552 6553 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { 6554 TMDS_STEREOSYNC_CTL0 = 0x00000000, 6555 TMDS_STEREOSYNC_CTL1 = 0x00000001, 6556 TMDS_STEREOSYNC_CTL2 = 0x00000002, 6557 TMDS_STEREOSYNC_CTL3 = 0x00000003, 6558 } TMDS_STEREOSYNC_CTL_SEL_REG; 6559 6560 /* 6561 * TMDS_CTL0_DATA_SEL enum 6562 */ 6563 6564 typedef enum TMDS_CTL0_DATA_SEL { 6565 TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000, 6566 TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, 6567 TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002, 6568 TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003, 6569 TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004, 6570 TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005, 6571 TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006, 6572 TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007, 6573 } TMDS_CTL0_DATA_SEL; 6574 6575 /* 6576 * TMDS_CTL0_DATA_INVERT enum 6577 */ 6578 6579 typedef enum TMDS_CTL0_DATA_INVERT { 6580 TMDS_CTL0_DATA_NORMAL = 0x00000000, 6581 TMDS_CTL0_DATA_INVERT_EN = 0x00000001, 6582 } TMDS_CTL0_DATA_INVERT; 6583 6584 /* 6585 * TMDS_CTL0_DATA_MODULATION enum 6586 */ 6587 6588 typedef enum TMDS_CTL0_DATA_MODULATION { 6589 TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000, 6590 TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001, 6591 TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002, 6592 TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003, 6593 } TMDS_CTL0_DATA_MODULATION; 6594 6595 /* 6596 * TMDS_CTL0_PATTERN_OUT_EN enum 6597 */ 6598 6599 typedef enum TMDS_CTL0_PATTERN_OUT_EN { 6600 TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000, 6601 TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001, 6602 } TMDS_CTL0_PATTERN_OUT_EN; 6603 6604 /* 6605 * TMDS_CTL1_DATA_SEL enum 6606 */ 6607 6608 typedef enum TMDS_CTL1_DATA_SEL { 6609 TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000, 6610 TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, 6611 TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002, 6612 TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003, 6613 TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004, 6614 TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005, 6615 TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006, 6616 TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007, 6617 } TMDS_CTL1_DATA_SEL; 6618 6619 /* 6620 * TMDS_CTL1_DATA_INVERT enum 6621 */ 6622 6623 typedef enum TMDS_CTL1_DATA_INVERT { 6624 TMDS_CTL1_DATA_NORMAL = 0x00000000, 6625 TMDS_CTL1_DATA_INVERT_EN = 0x00000001, 6626 } TMDS_CTL1_DATA_INVERT; 6627 6628 /* 6629 * TMDS_CTL1_DATA_MODULATION enum 6630 */ 6631 6632 typedef enum TMDS_CTL1_DATA_MODULATION { 6633 TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000, 6634 TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001, 6635 TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002, 6636 TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003, 6637 } TMDS_CTL1_DATA_MODULATION; 6638 6639 /* 6640 * TMDS_CTL1_PATTERN_OUT_EN enum 6641 */ 6642 6643 typedef enum TMDS_CTL1_PATTERN_OUT_EN { 6644 TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000, 6645 TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001, 6646 } TMDS_CTL1_PATTERN_OUT_EN; 6647 6648 /* 6649 * TMDS_CTL2_DATA_SEL enum 6650 */ 6651 6652 typedef enum TMDS_CTL2_DATA_SEL { 6653 TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000, 6654 TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, 6655 TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002, 6656 TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003, 6657 TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004, 6658 TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005, 6659 TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006, 6660 TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007, 6661 } TMDS_CTL2_DATA_SEL; 6662 6663 /* 6664 * TMDS_CTL2_DATA_INVERT enum 6665 */ 6666 6667 typedef enum TMDS_CTL2_DATA_INVERT { 6668 TMDS_CTL2_DATA_NORMAL = 0x00000000, 6669 TMDS_CTL2_DATA_INVERT_EN = 0x00000001, 6670 } TMDS_CTL2_DATA_INVERT; 6671 6672 /* 6673 * TMDS_CTL2_DATA_MODULATION enum 6674 */ 6675 6676 typedef enum TMDS_CTL2_DATA_MODULATION { 6677 TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000, 6678 TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001, 6679 TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002, 6680 TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003, 6681 } TMDS_CTL2_DATA_MODULATION; 6682 6683 /* 6684 * TMDS_CTL2_PATTERN_OUT_EN enum 6685 */ 6686 6687 typedef enum TMDS_CTL2_PATTERN_OUT_EN { 6688 TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000, 6689 TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001, 6690 } TMDS_CTL2_PATTERN_OUT_EN; 6691 6692 /* 6693 * TMDS_CTL3_DATA_INVERT enum 6694 */ 6695 6696 typedef enum TMDS_CTL3_DATA_INVERT { 6697 TMDS_CTL3_DATA_NORMAL = 0x00000000, 6698 TMDS_CTL3_DATA_INVERT_EN = 0x00000001, 6699 } TMDS_CTL3_DATA_INVERT; 6700 6701 /* 6702 * TMDS_CTL3_DATA_MODULATION enum 6703 */ 6704 6705 typedef enum TMDS_CTL3_DATA_MODULATION { 6706 TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000, 6707 TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001, 6708 TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002, 6709 TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003, 6710 } TMDS_CTL3_DATA_MODULATION; 6711 6712 /* 6713 * TMDS_CTL3_PATTERN_OUT_EN enum 6714 */ 6715 6716 typedef enum TMDS_CTL3_PATTERN_OUT_EN { 6717 TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000, 6718 TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001, 6719 } TMDS_CTL3_PATTERN_OUT_EN; 6720 6721 /* 6722 * TMDS_CTL3_DATA_SEL enum 6723 */ 6724 6725 typedef enum TMDS_CTL3_DATA_SEL { 6726 TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000, 6727 TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, 6728 TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002, 6729 TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003, 6730 TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004, 6731 TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005, 6732 TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006, 6733 TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007, 6734 } TMDS_CTL3_DATA_SEL; 6735 6736 /* 6737 * DIG_FE_CNTL_SOURCE_SELECT enum 6738 */ 6739 6740 typedef enum DIG_FE_CNTL_SOURCE_SELECT { 6741 DIG_FE_SOURCE_FROM_OTG0 = 0x00000000, 6742 DIG_FE_SOURCE_FROM_OTG1 = 0x00000001, 6743 DIG_FE_SOURCE_FROM_OTG2 = 0x00000002, 6744 DIG_FE_SOURCE_FROM_OTG3 = 0x00000003, 6745 DIG_FE_SOURCE_FROM_OTG4 = 0x00000004, 6746 DIG_FE_SOURCE_FROM_OTG5 = 0x00000005, 6747 DIG_FE_SOURCE_RESERVED = 0x00000006, 6748 } DIG_FE_CNTL_SOURCE_SELECT; 6749 6750 /* 6751 * DIG_FE_CNTL_STEREOSYNC_SELECT enum 6752 */ 6753 6754 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { 6755 DIG_FE_STEREOSYNC_FROM_OTG0 = 0x00000000, 6756 DIG_FE_STEREOSYNC_FROM_OTG1 = 0x00000001, 6757 DIG_FE_STEREOSYNC_FROM_OTG2 = 0x00000002, 6758 DIG_FE_STEREOSYNC_FROM_OTG3 = 0x00000003, 6759 DIG_FE_STEREOSYNC_FROM_OTG4 = 0x00000004, 6760 DIG_FE_STEREOSYNC_FROM_OTG5 = 0x00000005, 6761 DIG_FE_STEREOSYNC_RESERVED = 0x00000006, 6762 } DIG_FE_CNTL_STEREOSYNC_SELECT; 6763 6764 /* 6765 * DIG_FIFO_READ_CLOCK_SRC enum 6766 */ 6767 6768 typedef enum DIG_FIFO_READ_CLOCK_SRC { 6769 DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000, 6770 DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001, 6771 } DIG_FIFO_READ_CLOCK_SRC; 6772 6773 /* 6774 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum 6775 */ 6776 6777 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { 6778 DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000, 6779 DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001, 6780 } DIG_OUTPUT_CRC_CNTL_LINK_SEL; 6781 6782 /* 6783 * DIG_OUTPUT_CRC_DATA_SEL enum 6784 */ 6785 6786 typedef enum DIG_OUTPUT_CRC_DATA_SEL { 6787 DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000, 6788 DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001, 6789 DIG_OUTPUT_CRC_FOR_VBI = 0x00000002, 6790 DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003, 6791 } DIG_OUTPUT_CRC_DATA_SEL; 6792 6793 /* 6794 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum 6795 */ 6796 6797 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { 6798 DIG_IN_NORMAL_OPERATION = 0x00000000, 6799 DIG_IN_DEBUG_MODE = 0x00000001, 6800 } DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; 6801 6802 /* 6803 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum 6804 */ 6805 6806 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { 6807 DIG_10BIT_TEST_PATTERN = 0x00000000, 6808 DIG_ALTERNATING_TEST_PATTERN = 0x00000001, 6809 } DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; 6810 6811 /* 6812 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum 6813 */ 6814 6815 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { 6816 DIG_TEST_PATTERN_NORMAL = 0x00000000, 6817 DIG_TEST_PATTERN_RANDOM = 0x00000001, 6818 } DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; 6819 6820 /* 6821 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum 6822 */ 6823 6824 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { 6825 DIG_RANDOM_PATTERN_ENABLED = 0x00000000, 6826 DIG_RANDOM_PATTERN_RESETED = 0x00000001, 6827 } DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; 6828 6829 /* 6830 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum 6831 */ 6832 6833 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { 6834 DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000, 6835 DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001, 6836 } DIG_TEST_PATTERN_EXTERNAL_RESET_EN; 6837 6838 /* 6839 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum 6840 */ 6841 6842 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { 6843 DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000, 6844 DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001, 6845 } DIG_RANDOM_PATTERN_SEED_RAN_PAT; 6846 6847 /* 6848 * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum 6849 */ 6850 6851 typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL { 6852 DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000, 6853 DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001, 6854 } DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL; 6855 6856 /* 6857 * DIG_FIFO_ERROR_ACK enum 6858 */ 6859 6860 typedef enum DIG_FIFO_ERROR_ACK { 6861 DIG_FIFO_ERROR_ACK_INT = 0x00000000, 6862 DIG_FIFO_ERROR_NOT_ACK = 0x00000001, 6863 } DIG_FIFO_ERROR_ACK; 6864 6865 /* 6866 * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum 6867 */ 6868 6869 typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE { 6870 DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000, 6871 DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001, 6872 } DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE; 6873 6874 /* 6875 * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum 6876 */ 6877 6878 typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX { 6879 DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000, 6880 DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001, 6881 } DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX; 6882 6883 /* 6884 * AFMT_INTERRUPT_STATUS_CHG_MASK enum 6885 */ 6886 6887 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { 6888 AFMT_INTERRUPT_DISABLE = 0x00000000, 6889 AFMT_INTERRUPT_ENABLE = 0x00000001, 6890 } AFMT_INTERRUPT_STATUS_CHG_MASK; 6891 6892 /* 6893 * HDMI_GC_AVMUTE enum 6894 */ 6895 6896 typedef enum HDMI_GC_AVMUTE { 6897 HDMI_GC_AVMUTE_SET = 0x00000000, 6898 HDMI_GC_AVMUTE_UNSET = 0x00000001, 6899 } HDMI_GC_AVMUTE; 6900 6901 /* 6902 * HDMI_DEFAULT_PAHSE enum 6903 */ 6904 6905 typedef enum HDMI_DEFAULT_PAHSE { 6906 HDMI_DEFAULT_PHASE_IS_0 = 0x00000000, 6907 HDMI_DEFAULT_PHASE_IS_1 = 0x00000001, 6908 } HDMI_DEFAULT_PAHSE; 6909 6910 /* 6911 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum 6912 */ 6913 6914 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { 6915 AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000, 6916 AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001, 6917 } AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; 6918 6919 /* 6920 * AUDIO_LAYOUT_SELECT enum 6921 */ 6922 6923 typedef enum AUDIO_LAYOUT_SELECT { 6924 AUDIO_LAYOUT_0 = 0x00000000, 6925 AUDIO_LAYOUT_1 = 0x00000001, 6926 } AUDIO_LAYOUT_SELECT; 6927 6928 /* 6929 * AFMT_AUDIO_CRC_CONTROL_CONT enum 6930 */ 6931 6932 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { 6933 AFMT_AUDIO_CRC_ONESHOT = 0x00000000, 6934 AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001, 6935 } AFMT_AUDIO_CRC_CONTROL_CONT; 6936 6937 /* 6938 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum 6939 */ 6940 6941 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { 6942 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000, 6943 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001, 6944 } AFMT_AUDIO_CRC_CONTROL_SOURCE; 6945 6946 /* 6947 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum 6948 */ 6949 6950 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { 6951 AFMT_AUDIO_CRC_CH0_SIG = 0x00000000, 6952 AFMT_AUDIO_CRC_CH1_SIG = 0x00000001, 6953 AFMT_AUDIO_CRC_CH2_SIG = 0x00000002, 6954 AFMT_AUDIO_CRC_CH3_SIG = 0x00000003, 6955 AFMT_AUDIO_CRC_CH4_SIG = 0x00000004, 6956 AFMT_AUDIO_CRC_CH5_SIG = 0x00000005, 6957 AFMT_AUDIO_CRC_CH6_SIG = 0x00000006, 6958 AFMT_AUDIO_CRC_CH7_SIG = 0x00000007, 6959 AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008, 6960 AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009, 6961 AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a, 6962 AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b, 6963 AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c, 6964 AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d, 6965 AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e, 6966 AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f, 6967 } AFMT_AUDIO_CRC_CONTROL_CH_SEL; 6968 6969 /* 6970 * AFMT_RAMP_CONTROL0_SIGN enum 6971 */ 6972 6973 typedef enum AFMT_RAMP_CONTROL0_SIGN { 6974 AFMT_RAMP_SIGNED = 0x00000000, 6975 AFMT_RAMP_UNSIGNED = 0x00000001, 6976 } AFMT_RAMP_CONTROL0_SIGN; 6977 6978 /* 6979 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum 6980 */ 6981 6982 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { 6983 AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000, 6984 AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001, 6985 } AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; 6986 6987 /* 6988 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum 6989 */ 6990 6991 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { 6992 AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000, 6993 AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001, 6994 } AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; 6995 6996 /* 6997 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum 6998 */ 6999 7000 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { 7001 AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000, 7002 AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001, 7003 } AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; 7004 7005 /* 7006 * AFMT_AUDIO_SRC_CONTROL_SELECT enum 7007 */ 7008 7009 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { 7010 AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000, 7011 AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001, 7012 AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002, 7013 AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003, 7014 AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004, 7015 AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005, 7016 AFMT_AUDIO_SRC_RESERVED = 0x00000006, 7017 } AFMT_AUDIO_SRC_CONTROL_SELECT; 7018 7019 /* 7020 * DIG_BE_CNTL_MODE enum 7021 */ 7022 7023 typedef enum DIG_BE_CNTL_MODE { 7024 DIG_BE_DP_SST_MODE = 0x00000000, 7025 DIG_BE_RESERVED1 = 0x00000001, 7026 DIG_BE_TMDS_DVI_MODE = 0x00000002, 7027 DIG_BE_TMDS_HDMI_MODE = 0x00000003, 7028 DIG_BE_RESERVED4 = 0x00000004, 7029 DIG_BE_DP_MST_MODE = 0x00000005, 7030 DIG_BE_RESERVED2 = 0x00000006, 7031 DIG_BE_RESERVED3 = 0x00000007, 7032 } DIG_BE_CNTL_MODE; 7033 7034 /* 7035 * DIG_BE_CNTL_HPD_SELECT enum 7036 */ 7037 7038 typedef enum DIG_BE_CNTL_HPD_SELECT { 7039 DIG_BE_CNTL_HPD1 = 0x00000000, 7040 DIG_BE_CNTL_HPD2 = 0x00000001, 7041 DIG_BE_CNTL_HPD3 = 0x00000002, 7042 DIG_BE_CNTL_HPD4 = 0x00000003, 7043 DIG_BE_CNTL_HPD5 = 0x00000004, 7044 DIG_BE_CNTL_HPD6 = 0x00000005, 7045 DIG_BE_CNTL_NO_HPD = 0x00000006, 7046 } DIG_BE_CNTL_HPD_SELECT; 7047 7048 /* 7049 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum 7050 */ 7051 7052 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { 7053 LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000, 7054 LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001, 7055 } LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; 7056 7057 /* 7058 * TMDS_SYNC_PHASE enum 7059 */ 7060 7061 typedef enum TMDS_SYNC_PHASE { 7062 TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000, 7063 TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001, 7064 } TMDS_SYNC_PHASE; 7065 7066 /* 7067 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum 7068 */ 7069 7070 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { 7071 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000, 7072 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001, 7073 } TMDS_DATA_SYNCHRONIZATION_DSINTSEL; 7074 7075 /* 7076 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum 7077 */ 7078 7079 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { 7080 TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000, 7081 TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001, 7082 } TMDS_TRANSMITTER_ENABLE_HPD_MASK; 7083 7084 /* 7085 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum 7086 */ 7087 7088 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { 7089 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, 7090 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001, 7091 } TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; 7092 7093 /* 7094 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum 7095 */ 7096 7097 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { 7098 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, 7099 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001, 7100 } TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; 7101 7102 /* 7103 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum 7104 */ 7105 7106 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { 7107 TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000, 7108 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001, 7109 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002, 7110 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003, 7111 } TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; 7112 7113 /* 7114 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum 7115 */ 7116 7117 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { 7118 TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000, 7119 TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001, 7120 } TMDS_TRANSMITTER_CONTROL_IDSCKSELA; 7121 7122 /* 7123 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum 7124 */ 7125 7126 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { 7127 TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000, 7128 TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001, 7129 } TMDS_TRANSMITTER_CONTROL_IDSCKSELB; 7130 7131 /* 7132 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum 7133 */ 7134 7135 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { 7136 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000, 7137 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001, 7138 } TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; 7139 7140 /* 7141 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum 7142 */ 7143 7144 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { 7145 TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000, 7146 TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001, 7147 } TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; 7148 7149 /* 7150 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum 7151 */ 7152 7153 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { 7154 TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000, 7155 TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001, 7156 } TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; 7157 7158 /* 7159 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum 7160 */ 7161 7162 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { 7163 TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000, 7164 TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001, 7165 } TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; 7166 7167 /* 7168 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum 7169 */ 7170 7171 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { 7172 TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000, 7173 TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001, 7174 } TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; 7175 7176 /* 7177 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum 7178 */ 7179 7180 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { 7181 TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000, 7182 TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001, 7183 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; 7184 7185 /* 7186 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum 7187 */ 7188 7189 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { 7190 TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000, 7191 TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001, 7192 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; 7193 7194 /* 7195 * TMDS_REG_TEST_OUTPUTA_CNTLA enum 7196 */ 7197 7198 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { 7199 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000, 7200 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001, 7201 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002, 7202 TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003, 7203 } TMDS_REG_TEST_OUTPUTA_CNTLA; 7204 7205 /* 7206 * TMDS_REG_TEST_OUTPUTB_CNTLB enum 7207 */ 7208 7209 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { 7210 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000, 7211 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001, 7212 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002, 7213 TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003, 7214 } TMDS_REG_TEST_OUTPUTB_CNTLB; 7215 7216 /* 7217 * AFMT_VBI_GSP_INDEX enum 7218 */ 7219 7220 typedef enum AFMT_VBI_GSP_INDEX { 7221 AFMT_VBI_GSP0_INDEX = 0x00000000, 7222 AFMT_VBI_GSP1_INDEX = 0x00000001, 7223 AFMT_VBI_GSP2_INDEX = 0x00000002, 7224 AFMT_VBI_GSP3_INDEX = 0x00000003, 7225 AFMT_VBI_GSP4_INDEX = 0x00000004, 7226 AFMT_VBI_GSP5_INDEX = 0x00000005, 7227 AFMT_VBI_GSP6_INDEX = 0x00000006, 7228 AFMT_VBI_GSP7_INDEX = 0x00000007, 7229 AFMT_VBI_GSP8_INDEX = 0x00000008, 7230 AFMT_VBI_GSP9_INDEX = 0x00000009, 7231 AFMT_VBI_GSP10_INDEX = 0x0000000a, 7232 } AFMT_VBI_GSP_INDEX; 7233 7234 /* 7235 * DIG_DIGITAL_BYPASS_SEL enum 7236 */ 7237 7238 typedef enum DIG_DIGITAL_BYPASS_SEL { 7239 DIG_DIGITAL_BYPASS_SEL_BYPASS = 0x00000000, 7240 DIG_DIGITAL_BYPASS_SEL_36BPP = 0x00000001, 7241 DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 0x00000002, 7242 DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 0x00000003, 7243 DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 0x00000004, 7244 DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 0x00000005, 7245 DIG_DIGITAL_BYPASS_SEL_ALPHA = 0x00000006, 7246 } DIG_DIGITAL_BYPASS_SEL; 7247 7248 /* 7249 * DIG_INPUT_PIXEL_SEL enum 7250 */ 7251 7252 typedef enum DIG_INPUT_PIXEL_SEL { 7253 DIG_ALL_PIXEL = 0x00000000, 7254 DIG_EVEN_PIXEL_ONLY = 0x00000001, 7255 DIG_ODD_PIXEL_ONLY = 0x00000002, 7256 } DIG_INPUT_PIXEL_SEL; 7257 7258 /* 7259 * DOLBY_VISION_ENABLE enum 7260 */ 7261 7262 typedef enum DOLBY_VISION_ENABLE { 7263 DOLBY_VISION_ENABLED = 0x00000000, 7264 DOLBY_VISION_DISABLED = 0x00000001, 7265 } DOLBY_VISION_ENABLE; 7266 7267 /* 7268 * METADATA_HUBP_SEL enum 7269 */ 7270 7271 typedef enum METADATA_HUBP_SEL { 7272 METADATA_HUBP_SEL_0 = 0x00000000, 7273 METADATA_HUBP_SEL_1 = 0x00000001, 7274 METADATA_HUBP_SEL_2 = 0x00000002, 7275 METADATA_HUBP_SEL_3 = 0x00000003, 7276 METADATA_HUBP_SEL_4 = 0x00000004, 7277 METADATA_HUBP_SEL_5 = 0x00000005, 7278 METADATA_HUBP_SEL_RESERVED = 0x00000006, 7279 } METADATA_HUBP_SEL; 7280 7281 /* 7282 * METADATA_STREAM_TYPE_SEL enum 7283 */ 7284 7285 typedef enum METADATA_STREAM_TYPE_SEL { 7286 METADATA_STREAM_DP = 0x00000000, 7287 METADATA_STREAM_DVE = 0x00000001, 7288 } METADATA_STREAM_TYPE_SEL; 7289 7290 /* 7291 * HDMI_METADATA_ENABLE enum 7292 */ 7293 7294 typedef enum HDMI_METADATA_ENABLE { 7295 HDMI_METADATA_NOT_SEND = 0x00000000, 7296 HDMI_METADATA_PKT_SEND = 0x00000001, 7297 } HDMI_METADATA_ENABLE; 7298 7299 /* 7300 * HDMI_PACKET_LINE_REFERENCE enum 7301 */ 7302 7303 typedef enum HDMI_PACKET_LINE_REFERENCE { 7304 HDMI_PKT_LINE_REF_VSYNC = 0x00000000, 7305 HDMI_PKT_LINE_REF_OTGSOF = 0x00000001, 7306 } HDMI_PACKET_LINE_REFERENCE; 7307 7308 /******************************************************* 7309 * DP_AUX Enums 7310 *******************************************************/ 7311 7312 /* 7313 * DP_AUX_CONTROL_HPD_SEL enum 7314 */ 7315 7316 typedef enum DP_AUX_CONTROL_HPD_SEL { 7317 DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000, 7318 DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001, 7319 DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002, 7320 DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003, 7321 DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004, 7322 DP_AUX_CONTROL_HPD6_SELECTED = 0x00000005, 7323 DP_AUX_CONTROL_NO_HPD_SELECTED = 0x00000006, 7324 } DP_AUX_CONTROL_HPD_SEL; 7325 7326 /* 7327 * DP_AUX_CONTROL_TEST_MODE enum 7328 */ 7329 7330 typedef enum DP_AUX_CONTROL_TEST_MODE { 7331 DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000, 7332 DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001, 7333 } DP_AUX_CONTROL_TEST_MODE; 7334 7335 /* 7336 * DP_AUX_SW_CONTROL_SW_GO enum 7337 */ 7338 7339 typedef enum DP_AUX_SW_CONTROL_SW_GO { 7340 DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000, 7341 DP_AUX_SW_CONTROL_SW__GO = 0x00000001, 7342 } DP_AUX_SW_CONTROL_SW_GO; 7343 7344 /* 7345 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum 7346 */ 7347 7348 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { 7349 DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000, 7350 DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001, 7351 } DP_AUX_SW_CONTROL_LS_READ_TRIG; 7352 7353 /* 7354 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum 7355 */ 7356 7357 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { 7358 DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000, 7359 DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001, 7360 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002, 7361 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003, 7362 } DP_AUX_ARB_CONTROL_ARB_PRIORITY; 7363 7364 /* 7365 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum 7366 */ 7367 7368 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { 7369 DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000, 7370 DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001, 7371 } DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; 7372 7373 /* 7374 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum 7375 */ 7376 7377 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { 7378 DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000, 7379 DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001, 7380 } DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; 7381 7382 /* 7383 * DP_AUX_INT_ACK enum 7384 */ 7385 7386 typedef enum DP_AUX_INT_ACK { 7387 DP_AUX_INT__NOT_ACK = 0x00000000, 7388 DP_AUX_INT__ACK = 0x00000001, 7389 } DP_AUX_INT_ACK; 7390 7391 /* 7392 * DP_AUX_LS_UPDATE_ACK enum 7393 */ 7394 7395 typedef enum DP_AUX_LS_UPDATE_ACK { 7396 DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000, 7397 DP_AUX_INT_LS_UPDATE_ACK = 0x00000001, 7398 } DP_AUX_LS_UPDATE_ACK; 7399 7400 /* 7401 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum 7402 */ 7403 7404 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { 7405 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000, 7406 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001, 7407 } DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; 7408 7409 /* 7410 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum 7411 */ 7412 7413 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { 7414 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000, 7415 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001, 7416 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002, 7417 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003, 7418 } DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; 7419 7420 /* 7421 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum 7422 */ 7423 7424 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { 7425 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000, 7426 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001, 7427 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002, 7428 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003, 7429 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004, 7430 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005, 7431 } DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; 7432 7433 /* 7434 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum 7435 */ 7436 7437 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { 7438 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000, 7439 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001, 7440 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002, 7441 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003, 7442 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004, 7443 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005, 7444 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006, 7445 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007, 7446 } DP_AUX_DPHY_RX_CONTROL_START_WINDOW; 7447 7448 /* 7449 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum 7450 */ 7451 7452 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { 7453 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000, 7454 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001, 7455 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002, 7456 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003, 7457 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004, 7458 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005, 7459 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006, 7460 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007, 7461 } DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; 7462 7463 /* 7464 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum 7465 */ 7466 7467 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { 7468 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000, 7469 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001, 7470 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002, 7471 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003, 7472 } DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; 7473 7474 /* 7475 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum 7476 */ 7477 7478 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { 7479 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000, 7480 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001, 7481 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; 7482 7483 /* 7484 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum 7485 */ 7486 7487 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { 7488 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000, 7489 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001, 7490 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; 7491 7492 /* 7493 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum 7494 */ 7495 7496 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { 7497 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000, 7498 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001, 7499 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; 7500 7501 /* 7502 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum 7503 */ 7504 7505 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { 7506 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000, 7507 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001, 7508 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002, 7509 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003, 7510 } DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; 7511 7512 /* 7513 * DP_AUX_RX_TIMEOUT_LEN_MUL enum 7514 */ 7515 7516 typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL { 7517 DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0x00000000, 7518 DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 0x00000001, 7519 DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 0x00000002, 7520 DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 0x00000003, 7521 } DP_AUX_RX_TIMEOUT_LEN_MUL; 7522 7523 /* 7524 * DP_AUX_TX_PRECHARGE_LEN_MUL enum 7525 */ 7526 7527 typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL { 7528 DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0x00000000, 7529 DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 0x00000001, 7530 DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 0x00000002, 7531 DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 0x00000003, 7532 } DP_AUX_TX_PRECHARGE_LEN_MUL; 7533 7534 /* 7535 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum 7536 */ 7537 7538 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { 7539 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000, 7540 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001, 7541 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002, 7542 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003, 7543 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004, 7544 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005, 7545 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006, 7546 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007, 7547 } DP_AUX_DPHY_RX_DETECTION_THRESHOLD; 7548 7549 /* 7550 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum 7551 */ 7552 7553 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { 7554 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000, 7555 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001, 7556 } DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; 7557 7558 /* 7559 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum 7560 */ 7561 7562 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { 7563 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000, 7564 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001, 7565 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002, 7566 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003, 7567 } DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; 7568 7569 /* 7570 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum 7571 */ 7572 7573 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { 7574 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000, 7575 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001, 7576 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002, 7577 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003, 7578 } DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; 7579 7580 /* 7581 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum 7582 */ 7583 7584 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { 7585 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000, 7586 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001, 7587 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002, 7588 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003, 7589 } DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; 7590 7591 /* 7592 * DP_AUX_ERR_OCCURRED_ACK enum 7593 */ 7594 7595 typedef enum DP_AUX_ERR_OCCURRED_ACK { 7596 DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000, 7597 DP_AUX_ERR_OCCURRED__ACK = 0x00000001, 7598 } DP_AUX_ERR_OCCURRED_ACK; 7599 7600 /* 7601 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum 7602 */ 7603 7604 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { 7605 DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000, 7606 DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001, 7607 } DP_AUX_POTENTIAL_ERR_REACHED_ACK; 7608 7609 /* 7610 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum 7611 */ 7612 7613 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { 7614 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000, 7615 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001, 7616 } DP_AUX_DEFINITE_ERR_REACHED_ACK; 7617 7618 /* 7619 * DP_AUX_RESET enum 7620 */ 7621 7622 typedef enum DP_AUX_RESET { 7623 DP_AUX_RESET_DEASSERTED = 0x00000000, 7624 DP_AUX_RESET_ASSERTED = 0x00000001, 7625 } DP_AUX_RESET; 7626 7627 /* 7628 * DP_AUX_RESET_DONE enum 7629 */ 7630 7631 typedef enum DP_AUX_RESET_DONE { 7632 DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000, 7633 DP_AUX_RESET_SEQUENCE_DONE = 0x00000001, 7634 } DP_AUX_RESET_DONE; 7635 7636 /* 7637 * DP_AUX_PHY_WAKE_PRIORITY enum 7638 */ 7639 7640 typedef enum DP_AUX_PHY_WAKE_PRIORITY { 7641 DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0x00000000, 7642 DP_AUX_PHY_WAKE_LOW_PRIORITY = 0x00000001, 7643 } DP_AUX_PHY_WAKE_PRIORITY; 7644 7645 /******************************************************* 7646 * DOUT_I2C Enums 7647 *******************************************************/ 7648 7649 /* 7650 * DOUT_I2C_CONTROL_GO enum 7651 */ 7652 7653 typedef enum DOUT_I2C_CONTROL_GO { 7654 DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000, 7655 DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001, 7656 } DOUT_I2C_CONTROL_GO; 7657 7658 /* 7659 * DOUT_I2C_CONTROL_SOFT_RESET enum 7660 */ 7661 7662 typedef enum DOUT_I2C_CONTROL_SOFT_RESET { 7663 DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000, 7664 DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001, 7665 } DOUT_I2C_CONTROL_SOFT_RESET; 7666 7667 /* 7668 * DOUT_I2C_CONTROL_SEND_RESET enum 7669 */ 7670 7671 typedef enum DOUT_I2C_CONTROL_SEND_RESET { 7672 DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000, 7673 DOUT_I2C_CONTROL__SEND_RESET = 0x00000001, 7674 } DOUT_I2C_CONTROL_SEND_RESET; 7675 7676 /* 7677 * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum 7678 */ 7679 7680 typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH { 7681 DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0x00000000, 7682 DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 0x00000001, 7683 } DOUT_I2C_CONTROL_SEND_RESET_LENGTH; 7684 7685 /* 7686 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum 7687 */ 7688 7689 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { 7690 DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000, 7691 DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001, 7692 } DOUT_I2C_CONTROL_SW_STATUS_RESET; 7693 7694 /* 7695 * DOUT_I2C_CONTROL_DDC_SELECT enum 7696 */ 7697 7698 typedef enum DOUT_I2C_CONTROL_DDC_SELECT { 7699 DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000, 7700 DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001, 7701 DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002, 7702 DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003, 7703 DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004, 7704 DOUT_I2C_CONTROL_SELECT_DDC6 = 0x00000005, 7705 DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000006, 7706 } DOUT_I2C_CONTROL_DDC_SELECT; 7707 7708 /* 7709 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum 7710 */ 7711 7712 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { 7713 DOUT_I2C_CONTROL_TRANS0 = 0x00000000, 7714 DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001, 7715 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002, 7716 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003, 7717 } DOUT_I2C_CONTROL_TRANSACTION_COUNT; 7718 7719 /* 7720 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum 7721 */ 7722 7723 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { 7724 DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000, 7725 DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001, 7726 DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002, 7727 DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003, 7728 } DOUT_I2C_ARBITRATION_SW_PRIORITY; 7729 7730 /* 7731 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum 7732 */ 7733 7734 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { 7735 DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000, 7736 DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001, 7737 } DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; 7738 7739 /* 7740 * DOUT_I2C_ARBITRATION_ABORT_XFER enum 7741 */ 7742 7743 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { 7744 DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000, 7745 DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001, 7746 } DOUT_I2C_ARBITRATION_ABORT_XFER; 7747 7748 /* 7749 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum 7750 */ 7751 7752 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { 7753 DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000, 7754 DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001, 7755 } DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; 7756 7757 /* 7758 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum 7759 */ 7760 7761 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { 7762 DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000, 7763 DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001, 7764 } DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; 7765 7766 /* 7767 * DOUT_I2C_ACK enum 7768 */ 7769 7770 typedef enum DOUT_I2C_ACK { 7771 DOUT_I2C_NO_ACK = 0x00000000, 7772 DOUT_I2C_ACK_TO_CLEAN = 0x00000001, 7773 } DOUT_I2C_ACK; 7774 7775 /* 7776 * DOUT_I2C_DDC_SPEED_THRESHOLD enum 7777 */ 7778 7779 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { 7780 DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000, 7781 DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001, 7782 DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002, 7783 DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003, 7784 } DOUT_I2C_DDC_SPEED_THRESHOLD; 7785 7786 /* 7787 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum 7788 */ 7789 7790 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { 7791 DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, 7792 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001, 7793 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; 7794 7795 /* 7796 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum 7797 */ 7798 7799 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { 7800 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000, 7801 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001, 7802 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; 7803 7804 /* 7805 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum 7806 */ 7807 7808 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { 7809 DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000, 7810 DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001, 7811 } DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; 7812 7813 /* 7814 * DOUT_I2C_DDC_EDID_DETECT_STATUS enum 7815 */ 7816 7817 typedef enum DOUT_I2C_DDC_EDID_DETECT_STATUS { 7818 DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED = 0x00000000, 7819 DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED = 0x00000001, 7820 } DOUT_I2C_DDC_EDID_DETECT_STATUS; 7821 7822 /* 7823 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum 7824 */ 7825 7826 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { 7827 DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, 7828 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001, 7829 } DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; 7830 7831 /* 7832 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum 7833 */ 7834 7835 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { 7836 DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000, 7837 DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001, 7838 } DOUT_I2C_TRANSACTION_STOP_ON_NACK; 7839 7840 /* 7841 * DOUT_I2C_DATA_INDEX_WRITE enum 7842 */ 7843 7844 typedef enum DOUT_I2C_DATA_INDEX_WRITE { 7845 DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000, 7846 DOUT_I2C_DATA__INDEX_WRITE = 0x00000001, 7847 } DOUT_I2C_DATA_INDEX_WRITE; 7848 7849 /* 7850 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum 7851 */ 7852 7853 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { 7854 DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000, 7855 DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001, 7856 } DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; 7857 7858 /* 7859 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum 7860 */ 7861 7862 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { 7863 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000, 7864 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001, 7865 } DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; 7866 7867 /******************************************************* 7868 * DIO_MISC Enums 7869 *******************************************************/ 7870 7871 /* 7872 * DIOMEM_PWR_FORCE_CTRL enum 7873 */ 7874 7875 typedef enum DIOMEM_PWR_FORCE_CTRL { 7876 DIOMEM_NO_FORCE_REQUEST = 0x00000000, 7877 DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 7878 DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 7879 DIOMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 7880 } DIOMEM_PWR_FORCE_CTRL; 7881 7882 /* 7883 * DIOMEM_PWR_FORCE_CTRL2 enum 7884 */ 7885 7886 typedef enum DIOMEM_PWR_FORCE_CTRL2 { 7887 DIOMEM_NO_FORCE_REQ = 0x00000000, 7888 DIOMEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001, 7889 } DIOMEM_PWR_FORCE_CTRL2; 7890 7891 /* 7892 * DIOMEM_PWR_DIS_CTRL enum 7893 */ 7894 7895 typedef enum DIOMEM_PWR_DIS_CTRL { 7896 DIOMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, 7897 DIOMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, 7898 } DIOMEM_PWR_DIS_CTRL; 7899 7900 /* 7901 * CLOCK_GATING_EN enum 7902 */ 7903 7904 typedef enum CLOCK_GATING_EN { 7905 CLOCK_GATING_ENABLE = 0x00000000, 7906 CLOCK_GATING_DISABLE = 0x00000001, 7907 } CLOCK_GATING_EN; 7908 7909 /* 7910 * DIOMEM_PWR_SEL_CTRL enum 7911 */ 7912 7913 typedef enum DIOMEM_PWR_SEL_CTRL { 7914 DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, 7915 DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, 7916 DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, 7917 } DIOMEM_PWR_SEL_CTRL; 7918 7919 /* 7920 * DIOMEM_PWR_SEL_CTRL2 enum 7921 */ 7922 7923 typedef enum DIOMEM_PWR_SEL_CTRL2 { 7924 DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0x00000000, 7925 DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, 7926 } DIOMEM_PWR_SEL_CTRL2; 7927 7928 /* 7929 * PM_ASSERT_RESET enum 7930 */ 7931 7932 typedef enum PM_ASSERT_RESET { 7933 PM_ASSERT_RESET_0 = 0x00000000, 7934 PM_ASSERT_RESET_1 = 0x00000001, 7935 } PM_ASSERT_RESET; 7936 7937 /* 7938 * DAC_MUX_SELECT enum 7939 */ 7940 7941 typedef enum DAC_MUX_SELECT { 7942 DAC_MUX_SELECT_DACA = 0x00000000, 7943 DAC_MUX_SELECT_DACB = 0x00000001, 7944 } DAC_MUX_SELECT; 7945 7946 /* 7947 * TMDS_MUX_SELECT enum 7948 */ 7949 7950 typedef enum TMDS_MUX_SELECT { 7951 TMDS_MUX_SELECT_B = 0x00000000, 7952 TMDS_MUX_SELECT_G = 0x00000001, 7953 TMDS_MUX_SELECT_R = 0x00000002, 7954 TMDS_MUX_SELECT_RESERVED = 0x00000003, 7955 } TMDS_MUX_SELECT; 7956 7957 /* 7958 * SOFT_RESET enum 7959 */ 7960 7961 typedef enum SOFT_RESET { 7962 SOFT_RESET_0 = 0x00000000, 7963 SOFT_RESET_1 = 0x00000001, 7964 } SOFT_RESET; 7965 7966 /* 7967 * GENERIC_STEREOSYNC_SEL enum 7968 */ 7969 7970 typedef enum GENERIC_STEREOSYNC_SEL { 7971 GENERIC_STEREOSYNC_SEL_D1 = 0x00000000, 7972 GENERIC_STEREOSYNC_SEL_D2 = 0x00000001, 7973 GENERIC_STEREOSYNC_SEL_D3 = 0x00000002, 7974 GENERIC_STEREOSYNC_SEL_D4 = 0x00000003, 7975 GENERIC_STEREOSYNC_SEL_D5 = 0x00000004, 7976 GENERIC_STEREOSYNC_SEL_D6 = 0x00000005, 7977 GENERIC_STEREOSYNC_SEL_RESERVED = 0x00000006, 7978 } GENERIC_STEREOSYNC_SEL; 7979 7980 /* 7981 * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum 7982 */ 7983 7984 typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE { 7985 DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000, 7986 DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001, 7987 } DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE; 7988 7989 /* 7990 * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum 7991 */ 7992 7993 typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE { 7994 DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0x00000000, 7995 DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 0x00000001, 7996 } DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE; 7997 7998 /******************************************************* 7999 * DCIO Enums 8000 *******************************************************/ 8001 8002 /* 8003 * DCIO_DC_GENERICA_SEL enum 8004 */ 8005 8006 typedef enum DCIO_DC_GENERICA_SEL { 8007 DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x00000000, 8008 DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001, 8009 DCIO_GENERICA_SEL_DACA_PIXCLK = 0x00000002, 8010 DCIO_GENERICA_SEL_DACB_PIXCLK = 0x00000003, 8011 DCIO_GENERICA_SEL_DVOA_CTL3 = 0x00000004, 8012 DCIO_GENERICA_SEL_P1_PLLCLK = 0x00000005, 8013 DCIO_GENERICA_SEL_P2_PLLCLK = 0x00000006, 8014 DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x00000007, 8015 DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x00000008, 8016 DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x00000009, 8017 DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a, 8018 DCIO_GENERICA_SEL_SYNCEN = 0x0000000b, 8019 DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 0x0000000c, 8020 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 0x0000000d, 8021 DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e, 8022 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f, 8023 DCIO_GENERICA_SEL_GENERICA_DPRX = 0x00000010, 8024 DCIO_GENERICA_SEL_GENERICB_DPRX = 0x00000011, 8025 } DCIO_DC_GENERICA_SEL; 8026 8027 /* 8028 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum 8029 */ 8030 8031 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { 8032 DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000, 8033 DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001, 8034 DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002, 8035 DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003, 8036 DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004, 8037 DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005, 8038 DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006, 8039 } DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; 8040 8041 /* 8042 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum 8043 */ 8044 8045 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { 8046 DCIO_UNIPHYA_FBDIV_CLK = 0x00000000, 8047 DCIO_UNIPHYB_FBDIV_CLK = 0x00000001, 8048 DCIO_UNIPHYC_FBDIV_CLK = 0x00000002, 8049 DCIO_UNIPHYD_FBDIV_CLK = 0x00000003, 8050 DCIO_UNIPHYE_FBDIV_CLK = 0x00000004, 8051 DCIO_UNIPHYF_FBDIV_CLK = 0x00000005, 8052 DCIO_UNIPHYG_FBDIV_CLK = 0x00000006, 8053 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; 8054 8055 /* 8056 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum 8057 */ 8058 8059 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { 8060 DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000, 8061 DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001, 8062 DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002, 8063 DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003, 8064 DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004, 8065 DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005, 8066 DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006, 8067 } DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; 8068 8069 /* 8070 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum 8071 */ 8072 8073 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { 8074 DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000, 8075 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001, 8076 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002, 8077 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003, 8078 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004, 8079 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005, 8080 DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006, 8081 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; 8082 8083 /* 8084 * DCIO_DC_GENERICB_SEL enum 8085 */ 8086 8087 typedef enum DCIO_DC_GENERICB_SEL { 8088 DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x00000000, 8089 DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001, 8090 DCIO_GENERICB_SEL_DACA_PIXCLK = 0x00000002, 8091 DCIO_GENERICB_SEL_DACB_PIXCLK = 0x00000003, 8092 DCIO_GENERICB_SEL_DVOA_CTL3 = 0x00000004, 8093 DCIO_GENERICB_SEL_P1_PLLCLK = 0x00000005, 8094 DCIO_GENERICB_SEL_P2_PLLCLK = 0x00000006, 8095 DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x00000007, 8096 DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x00000008, 8097 DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x00000009, 8098 DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a, 8099 DCIO_GENERICB_SEL_SYNCEN = 0x0000000b, 8100 DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 0x0000000c, 8101 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 0x0000000d, 8102 DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e, 8103 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f, 8104 } DCIO_DC_GENERICB_SEL; 8105 8106 /* 8107 * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum 8108 */ 8109 8110 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { 8111 DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000, 8112 DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001, 8113 DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002, 8114 DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003, 8115 } DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; 8116 8117 /* 8118 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum 8119 */ 8120 8121 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { 8122 DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000, 8123 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001, 8124 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002, 8125 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003, 8126 } DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; 8127 8128 /* 8129 * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum 8130 */ 8131 8132 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { 8133 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000, 8134 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001, 8135 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002, 8136 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003, 8137 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004, 8138 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005, 8139 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006, 8140 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007, 8141 } DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; 8142 8143 /* 8144 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum 8145 */ 8146 8147 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { 8148 DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000, 8149 DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001, 8150 } DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; 8151 8152 /* 8153 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum 8154 */ 8155 8156 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { 8157 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000, 8158 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001, 8159 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002, 8160 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003, 8161 } DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; 8162 8163 /* 8164 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum 8165 */ 8166 8167 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { 8168 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000, 8169 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001, 8170 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002, 8171 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003, 8172 } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; 8173 8174 /* 8175 * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum 8176 */ 8177 8178 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { 8179 DCIO_VIP_MUX_EN_DVO = 0x00000000, 8180 DCIO_VIP_MUX_EN_VIP = 0x00000001, 8181 } DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; 8182 8183 /* 8184 * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum 8185 */ 8186 8187 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { 8188 DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x00000000, 8189 DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001, 8190 } DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; 8191 8192 /* 8193 * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum 8194 */ 8195 8196 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { 8197 DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x00000000, 8198 DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001, 8199 } DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; 8200 8201 /* 8202 * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum 8203 */ 8204 8205 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { 8206 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0x00000000, 8207 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 0x00000001, 8208 } DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; 8209 8210 /* 8211 * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum 8212 */ 8213 8214 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { 8215 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000, 8216 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001, 8217 } DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; 8218 8219 /* 8220 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum 8221 */ 8222 8223 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { 8224 DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x00000000, 8225 DCIO_LVTMA_SYNCEN_POL_INVERT = 0x00000001, 8226 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; 8227 8228 /* 8229 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum 8230 */ 8231 8232 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { 8233 DCIO_LVTMA_DIGON_OFF = 0x00000000, 8234 DCIO_LVTMA_DIGON_ON = 0x00000001, 8235 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; 8236 8237 /* 8238 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum 8239 */ 8240 8241 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { 8242 DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x00000000, 8243 DCIO_LVTMA_DIGON_POL_INVERT = 0x00000001, 8244 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; 8245 8246 /* 8247 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum 8248 */ 8249 8250 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { 8251 DCIO_LVTMA_BLON_OFF = 0x00000000, 8252 DCIO_LVTMA_BLON_ON = 0x00000001, 8253 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; 8254 8255 /* 8256 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum 8257 */ 8258 8259 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { 8260 DCIO_LVTMA_BLON_POL_NON_INVERT = 0x00000000, 8261 DCIO_LVTMA_BLON_POL_INVERT = 0x00000001, 8262 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; 8263 8264 /* 8265 * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum 8266 */ 8267 8268 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { 8269 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x00000000, 8270 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001, 8271 } DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; 8272 8273 /* 8274 * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum 8275 */ 8276 8277 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { 8278 DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x00000000, 8279 DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x00000001, 8280 } DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; 8281 8282 /* 8283 * DCIO_BL_PWM_CNTL_BL_PWM_EN enum 8284 */ 8285 8286 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { 8287 DCIO_BL_PWM_DISABLE = 0x00000000, 8288 DCIO_BL_PWM_ENABLE = 0x00000001, 8289 } DCIO_BL_PWM_CNTL_BL_PWM_EN; 8290 8291 /* 8292 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum 8293 */ 8294 8295 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { 8296 DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000, 8297 DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001, 8298 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; 8299 8300 /* 8301 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum 8302 */ 8303 8304 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { 8305 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x00000000, 8306 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x00000001, 8307 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; 8308 8309 /* 8310 * DCIO_BL_PWM_GRP1_REG_LOCK enum 8311 */ 8312 8313 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { 8314 DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000, 8315 DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001, 8316 } DCIO_BL_PWM_GRP1_REG_LOCK; 8317 8318 /* 8319 * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum 8320 */ 8321 8322 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { 8323 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000, 8324 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001, 8325 } DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; 8326 8327 /* 8328 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum 8329 */ 8330 8331 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { 8332 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000, 8333 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001, 8334 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002, 8335 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003, 8336 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004, 8337 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005, 8338 } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; 8339 8340 /* 8341 * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum 8342 */ 8343 8344 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { 8345 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000, 8346 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001, 8347 } DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; 8348 8349 /* 8350 * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum 8351 */ 8352 8353 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { 8354 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000, 8355 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001, 8356 } DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; 8357 8358 /* 8359 * DCIO_GSL_SEL enum 8360 */ 8361 8362 typedef enum DCIO_GSL_SEL { 8363 DCIO_GSL_SEL_GROUP_0 = 0x00000000, 8364 DCIO_GSL_SEL_GROUP_1 = 0x00000001, 8365 DCIO_GSL_SEL_GROUP_2 = 0x00000002, 8366 } DCIO_GSL_SEL; 8367 8368 /* 8369 * DCIO_GENLK_CLK_GSL_MASK enum 8370 */ 8371 8372 typedef enum DCIO_GENLK_CLK_GSL_MASK { 8373 DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000, 8374 DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001, 8375 DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002, 8376 } DCIO_GENLK_CLK_GSL_MASK; 8377 8378 /* 8379 * DCIO_GENLK_VSYNC_GSL_MASK enum 8380 */ 8381 8382 typedef enum DCIO_GENLK_VSYNC_GSL_MASK { 8383 DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000, 8384 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001, 8385 DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002, 8386 } DCIO_GENLK_VSYNC_GSL_MASK; 8387 8388 /* 8389 * DCIO_SWAPLOCK_A_GSL_MASK enum 8390 */ 8391 8392 typedef enum DCIO_SWAPLOCK_A_GSL_MASK { 8393 DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000, 8394 DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001, 8395 DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002, 8396 } DCIO_SWAPLOCK_A_GSL_MASK; 8397 8398 /* 8399 * DCIO_SWAPLOCK_B_GSL_MASK enum 8400 */ 8401 8402 typedef enum DCIO_SWAPLOCK_B_GSL_MASK { 8403 DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000, 8404 DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001, 8405 DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002, 8406 } DCIO_SWAPLOCK_B_GSL_MASK; 8407 8408 /* 8409 * DCIO_DC_GPU_TIMER_START_POSITION enum 8410 */ 8411 8412 typedef enum DCIO_DC_GPU_TIMER_START_POSITION { 8413 DCIO_GPU_TIMER_START_0_END_27 = 0x00000000, 8414 DCIO_GPU_TIMER_START_1_END_28 = 0x00000001, 8415 DCIO_GPU_TIMER_START_2_END_29 = 0x00000002, 8416 DCIO_GPU_TIMER_START_3_END_30 = 0x00000003, 8417 DCIO_GPU_TIMER_START_4_END_31 = 0x00000004, 8418 DCIO_GPU_TIMER_START_6_END_33 = 0x00000005, 8419 DCIO_GPU_TIMER_START_8_END_35 = 0x00000006, 8420 DCIO_GPU_TIMER_START_10_END_37 = 0x00000007, 8421 } DCIO_DC_GPU_TIMER_START_POSITION; 8422 8423 /* 8424 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum 8425 */ 8426 8427 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { 8428 DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000, 8429 DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001, 8430 DCIO_TEST_CLK_SEL_SOCCLK = 0x00000002, 8431 } DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; 8432 8433 /* 8434 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum 8435 */ 8436 8437 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { 8438 DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000, 8439 DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001, 8440 } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; 8441 8442 /* 8443 * DCIO_DIO_OTG_EXT_VSYNC_MUX enum 8444 */ 8445 8446 typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX { 8447 DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000, 8448 DCIO_EXT_VSYNC_MUX_OTG0 = 0x00000001, 8449 DCIO_EXT_VSYNC_MUX_OTG1 = 0x00000002, 8450 DCIO_EXT_VSYNC_MUX_OTG2 = 0x00000003, 8451 DCIO_EXT_VSYNC_MUX_OTG3 = 0x00000004, 8452 DCIO_EXT_VSYNC_MUX_OTG4 = 0x00000005, 8453 DCIO_EXT_VSYNC_MUX_OTG5 = 0x00000006, 8454 DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007, 8455 } DCIO_DIO_OTG_EXT_VSYNC_MUX; 8456 8457 /* 8458 * DCIO_DIO_EXT_VSYNC_MASK enum 8459 */ 8460 8461 typedef enum DCIO_DIO_EXT_VSYNC_MASK { 8462 DCIO_EXT_VSYNC_MASK_NONE = 0x00000000, 8463 DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001, 8464 DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002, 8465 DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003, 8466 DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004, 8467 DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005, 8468 DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006, 8469 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007, 8470 } DCIO_DIO_EXT_VSYNC_MASK; 8471 8472 /* 8473 * DCIO_DSYNC_SOFT_RESET enum 8474 */ 8475 8476 typedef enum DCIO_DSYNC_SOFT_RESET { 8477 DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000, 8478 DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001, 8479 } DCIO_DSYNC_SOFT_RESET; 8480 8481 /* 8482 * DCIO_DACA_SOFT_RESET enum 8483 */ 8484 8485 typedef enum DCIO_DACA_SOFT_RESET { 8486 DCIO_DACA_SOFT_RESET_DEASSERT = 0x00000000, 8487 DCIO_DACA_SOFT_RESET_ASSERT = 0x00000001, 8488 } DCIO_DACA_SOFT_RESET; 8489 8490 /* 8491 * DCIO_DCRXPHY_SOFT_RESET enum 8492 */ 8493 8494 typedef enum DCIO_DCRXPHY_SOFT_RESET { 8495 DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000, 8496 DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001, 8497 } DCIO_DCRXPHY_SOFT_RESET; 8498 8499 /* 8500 * DCIO_DPHY_LANE_SEL enum 8501 */ 8502 8503 typedef enum DCIO_DPHY_LANE_SEL { 8504 DCIO_DPHY_LANE_SEL_LANE0 = 0x00000000, 8505 DCIO_DPHY_LANE_SEL_LANE1 = 0x00000001, 8506 DCIO_DPHY_LANE_SEL_LANE2 = 0x00000002, 8507 DCIO_DPHY_LANE_SEL_LANE3 = 0x00000003, 8508 } DCIO_DPHY_LANE_SEL; 8509 8510 /* 8511 * DCIO_DPCS_INTERRUPT_TYPE enum 8512 */ 8513 8514 typedef enum DCIO_DPCS_INTERRUPT_TYPE { 8515 DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000, 8516 DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001, 8517 } DCIO_DPCS_INTERRUPT_TYPE; 8518 8519 /* 8520 * DCIO_DPCS_INTERRUPT_MASK enum 8521 */ 8522 8523 typedef enum DCIO_DPCS_INTERRUPT_MASK { 8524 DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000, 8525 DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001, 8526 } DCIO_DPCS_INTERRUPT_MASK; 8527 8528 /* 8529 * DCIO_DC_GPU_TIMER_READ_SELECT enum 8530 */ 8531 8532 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { 8533 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000, 8534 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001, 8535 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x00000002, 8536 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x00000003, 8537 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000004, 8538 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000005, 8539 } DCIO_DC_GPU_TIMER_READ_SELECT; 8540 8541 /* 8542 * DCIO_IMPCAL_STEP_DELAY enum 8543 */ 8544 8545 typedef enum DCIO_IMPCAL_STEP_DELAY { 8546 DCIO_IMPCAL_STEP_DELAY_1us = 0x00000000, 8547 DCIO_IMPCAL_STEP_DELAY_2us = 0x00000001, 8548 DCIO_IMPCAL_STEP_DELAY_3us = 0x00000002, 8549 DCIO_IMPCAL_STEP_DELAY_4us = 0x00000003, 8550 DCIO_IMPCAL_STEP_DELAY_5us = 0x00000004, 8551 DCIO_IMPCAL_STEP_DELAY_6us = 0x00000005, 8552 DCIO_IMPCAL_STEP_DELAY_7us = 0x00000006, 8553 DCIO_IMPCAL_STEP_DELAY_8us = 0x00000007, 8554 DCIO_IMPCAL_STEP_DELAY_9us = 0x00000008, 8555 DCIO_IMPCAL_STEP_DELAY_10us = 0x00000009, 8556 DCIO_IMPCAL_STEP_DELAY_11us = 0x0000000a, 8557 DCIO_IMPCAL_STEP_DELAY_12us = 0x0000000b, 8558 DCIO_IMPCAL_STEP_DELAY_13us = 0x0000000c, 8559 DCIO_IMPCAL_STEP_DELAY_14us = 0x0000000d, 8560 DCIO_IMPCAL_STEP_DELAY_15us = 0x0000000e, 8561 DCIO_IMPCAL_STEP_DELAY_16us = 0x0000000f, 8562 } DCIO_IMPCAL_STEP_DELAY; 8563 8564 /* 8565 * DCIO_UNIPHY_IMPCAL_SEL enum 8566 */ 8567 8568 typedef enum DCIO_UNIPHY_IMPCAL_SEL { 8569 DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000, 8570 DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001, 8571 } DCIO_UNIPHY_IMPCAL_SEL; 8572 8573 /******************************************************* 8574 * DCIO_CHIP Enums 8575 *******************************************************/ 8576 8577 /* 8578 * DCIOCHIP_HPD_SEL enum 8579 */ 8580 8581 typedef enum DCIOCHIP_HPD_SEL { 8582 DCIOCHIP_HPD_SEL_ASYNC = 0x00000000, 8583 DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001, 8584 } DCIOCHIP_HPD_SEL; 8585 8586 /* 8587 * DCIOCHIP_PAD_MODE enum 8588 */ 8589 8590 typedef enum DCIOCHIP_PAD_MODE { 8591 DCIOCHIP_PAD_MODE_DDC = 0x00000000, 8592 DCIOCHIP_PAD_MODE_DP = 0x00000001, 8593 } DCIOCHIP_PAD_MODE; 8594 8595 /* 8596 * DCIOCHIP_AUXSLAVE_PAD_MODE enum 8597 */ 8598 8599 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { 8600 DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x00000000, 8601 DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x00000001, 8602 } DCIOCHIP_AUXSLAVE_PAD_MODE; 8603 8604 /* 8605 * DCIOCHIP_INVERT enum 8606 */ 8607 8608 typedef enum DCIOCHIP_INVERT { 8609 DCIOCHIP_POL_NON_INVERT = 0x00000000, 8610 DCIOCHIP_POL_INVERT = 0x00000001, 8611 } DCIOCHIP_INVERT; 8612 8613 /* 8614 * DCIOCHIP_PD_EN enum 8615 */ 8616 8617 typedef enum DCIOCHIP_PD_EN { 8618 DCIOCHIP_PD_EN_NOTALLOW = 0x00000000, 8619 DCIOCHIP_PD_EN_ALLOW = 0x00000001, 8620 } DCIOCHIP_PD_EN; 8621 8622 /* 8623 * DCIOCHIP_GPIO_MASK_EN enum 8624 */ 8625 8626 typedef enum DCIOCHIP_GPIO_MASK_EN { 8627 DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000, 8628 DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001, 8629 } DCIOCHIP_GPIO_MASK_EN; 8630 8631 /* 8632 * DCIOCHIP_MASK enum 8633 */ 8634 8635 typedef enum DCIOCHIP_MASK { 8636 DCIOCHIP_MASK_DISABLE = 0x00000000, 8637 DCIOCHIP_MASK_ENABLE = 0x00000001, 8638 } DCIOCHIP_MASK; 8639 8640 /* 8641 * DCIOCHIP_GPIO_I2C_MASK enum 8642 */ 8643 8644 typedef enum DCIOCHIP_GPIO_I2C_MASK { 8645 DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x00000000, 8646 DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x00000001, 8647 } DCIOCHIP_GPIO_I2C_MASK; 8648 8649 /* 8650 * DCIOCHIP_GPIO_I2C_DRIVE enum 8651 */ 8652 8653 typedef enum DCIOCHIP_GPIO_I2C_DRIVE { 8654 DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x00000000, 8655 DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x00000001, 8656 } DCIOCHIP_GPIO_I2C_DRIVE; 8657 8658 /* 8659 * DCIOCHIP_GPIO_I2C_EN enum 8660 */ 8661 8662 typedef enum DCIOCHIP_GPIO_I2C_EN { 8663 DCIOCHIP_GPIO_I2C_DISABLE = 0x00000000, 8664 DCIOCHIP_GPIO_I2C_ENABLE = 0x00000001, 8665 } DCIOCHIP_GPIO_I2C_EN; 8666 8667 /* 8668 * DCIOCHIP_MASK_4BIT enum 8669 */ 8670 8671 typedef enum DCIOCHIP_MASK_4BIT { 8672 DCIOCHIP_MASK_4BIT_DISABLE = 0x00000000, 8673 DCIOCHIP_MASK_4BIT_ENABLE = 0x0000000f, 8674 } DCIOCHIP_MASK_4BIT; 8675 8676 /* 8677 * DCIOCHIP_ENABLE_4BIT enum 8678 */ 8679 8680 typedef enum DCIOCHIP_ENABLE_4BIT { 8681 DCIOCHIP_4BIT_DISABLE = 0x00000000, 8682 DCIOCHIP_4BIT_ENABLE = 0x0000000f, 8683 } DCIOCHIP_ENABLE_4BIT; 8684 8685 /* 8686 * DCIOCHIP_MASK_5BIT enum 8687 */ 8688 8689 typedef enum DCIOCHIP_MASK_5BIT { 8690 DCIOCHIP_MASIK_5BIT_DISABLE = 0x00000000, 8691 DCIOCHIP_MASIK_5BIT_ENABLE = 0x0000001f, 8692 } DCIOCHIP_MASK_5BIT; 8693 8694 /* 8695 * DCIOCHIP_ENABLE_5BIT enum 8696 */ 8697 8698 typedef enum DCIOCHIP_ENABLE_5BIT { 8699 DCIOCHIP_5BIT_DISABLE = 0x00000000, 8700 DCIOCHIP_5BIT_ENABLE = 0x0000001f, 8701 } DCIOCHIP_ENABLE_5BIT; 8702 8703 /* 8704 * DCIOCHIP_MASK_2BIT enum 8705 */ 8706 8707 typedef enum DCIOCHIP_MASK_2BIT { 8708 DCIOCHIP_MASK_2BIT_DISABLE = 0x00000000, 8709 DCIOCHIP_MASK_2BIT_ENABLE = 0x00000003, 8710 } DCIOCHIP_MASK_2BIT; 8711 8712 /* 8713 * DCIOCHIP_ENABLE_2BIT enum 8714 */ 8715 8716 typedef enum DCIOCHIP_ENABLE_2BIT { 8717 DCIOCHIP_2BIT_DISABLE = 0x00000000, 8718 DCIOCHIP_2BIT_ENABLE = 0x00000003, 8719 } DCIOCHIP_ENABLE_2BIT; 8720 8721 /* 8722 * DCIOCHIP_REF_27_SRC_SEL enum 8723 */ 8724 8725 typedef enum DCIOCHIP_REF_27_SRC_SEL { 8726 DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000, 8727 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001, 8728 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002, 8729 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003, 8730 } DCIOCHIP_REF_27_SRC_SEL; 8731 8732 /* 8733 * DCIOCHIP_DVO_VREFPON enum 8734 */ 8735 8736 typedef enum DCIOCHIP_DVO_VREFPON { 8737 DCIOCHIP_DVO_VREFPON_DISABLE = 0x00000000, 8738 DCIOCHIP_DVO_VREFPON_ENABLE = 0x00000001, 8739 } DCIOCHIP_DVO_VREFPON; 8740 8741 /* 8742 * DCIOCHIP_DVO_VREFSEL enum 8743 */ 8744 8745 typedef enum DCIOCHIP_DVO_VREFSEL { 8746 DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x00000000, 8747 DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x00000001, 8748 } DCIOCHIP_DVO_VREFSEL; 8749 8750 /* 8751 * DCIOCHIP_SPDIF1_IMODE enum 8752 */ 8753 8754 typedef enum DCIOCHIP_SPDIF1_IMODE { 8755 DCIOCHIP_SPDIF1_IMODE_OE_A = 0x00000000, 8756 DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x00000001, 8757 } DCIOCHIP_SPDIF1_IMODE; 8758 8759 /* 8760 * DCIOCHIP_AUX_FALLSLEWSEL enum 8761 */ 8762 8763 typedef enum DCIOCHIP_AUX_FALLSLEWSEL { 8764 DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000, 8765 DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001, 8766 DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002, 8767 DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003, 8768 } DCIOCHIP_AUX_FALLSLEWSEL; 8769 8770 /* 8771 * DCIOCHIP_I2C_FALLSLEWSEL enum 8772 */ 8773 8774 typedef enum DCIOCHIP_I2C_FALLSLEWSEL { 8775 DCIOCHIP_I2C_FALLSLEWSEL_00 = 0x00000000, 8776 DCIOCHIP_I2C_FALLSLEWSEL_01 = 0x00000001, 8777 DCIOCHIP_I2C_FALLSLEWSEL_10 = 0x00000002, 8778 DCIOCHIP_I2C_FALLSLEWSEL_11 = 0x00000003, 8779 } DCIOCHIP_I2C_FALLSLEWSEL; 8780 8781 /* 8782 * DCIOCHIP_AUX_SPIKESEL enum 8783 */ 8784 8785 typedef enum DCIOCHIP_AUX_SPIKESEL { 8786 DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000, 8787 DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001, 8788 } DCIOCHIP_AUX_SPIKESEL; 8789 8790 /* 8791 * DCIOCHIP_AUX_CSEL0P9 enum 8792 */ 8793 8794 typedef enum DCIOCHIP_AUX_CSEL0P9 { 8795 DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000, 8796 DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001, 8797 } DCIOCHIP_AUX_CSEL0P9; 8798 8799 /* 8800 * DCIOCHIP_AUX_CSEL1P1 enum 8801 */ 8802 8803 typedef enum DCIOCHIP_AUX_CSEL1P1 { 8804 DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000, 8805 DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001, 8806 } DCIOCHIP_AUX_CSEL1P1; 8807 8808 /* 8809 * DCIOCHIP_AUX_RSEL0P9 enum 8810 */ 8811 8812 typedef enum DCIOCHIP_AUX_RSEL0P9 { 8813 DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000, 8814 DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001, 8815 } DCIOCHIP_AUX_RSEL0P9; 8816 8817 /* 8818 * DCIOCHIP_AUX_RSEL1P1 enum 8819 */ 8820 8821 typedef enum DCIOCHIP_AUX_RSEL1P1 { 8822 DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000, 8823 DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001, 8824 } DCIOCHIP_AUX_RSEL1P1; 8825 8826 /* 8827 * DCIOCHIP_AUX_HYS_TUNE enum 8828 */ 8829 8830 typedef enum DCIOCHIP_AUX_HYS_TUNE { 8831 DCIOCHIP_AUX_HYS_TUNE_0 = 0x00000000, 8832 DCIOCHIP_AUX_HYS_TUNE_1 = 0x00000001, 8833 DCIOCHIP_AUX_HYS_TUNE_2 = 0x00000002, 8834 DCIOCHIP_AUX_HYS_TUNE_3 = 0x00000003, 8835 } DCIOCHIP_AUX_HYS_TUNE; 8836 8837 /* 8838 * DCIOCHIP_AUX_VOD_TUNE enum 8839 */ 8840 8841 typedef enum DCIOCHIP_AUX_VOD_TUNE { 8842 DCIOCHIP_AUX_VOD_TUNE_0 = 0x00000000, 8843 DCIOCHIP_AUX_VOD_TUNE_1 = 0x00000001, 8844 DCIOCHIP_AUX_VOD_TUNE_2 = 0x00000002, 8845 DCIOCHIP_AUX_VOD_TUNE_3 = 0x00000003, 8846 } DCIOCHIP_AUX_VOD_TUNE; 8847 8848 /* 8849 * DCIOCHIP_I2C_VPH_1V2_EN enum 8850 */ 8851 8852 typedef enum DCIOCHIP_I2C_VPH_1V2_EN { 8853 DCIOCHIP_I2C_VPH_1V2_EN_0 = 0x00000000, 8854 DCIOCHIP_I2C_VPH_1V2_EN_1 = 0x00000001, 8855 } DCIOCHIP_I2C_VPH_1V2_EN; 8856 8857 /* 8858 * DCIOCHIP_I2C_COMPSEL enum 8859 */ 8860 8861 typedef enum DCIOCHIP_I2C_COMPSEL { 8862 DCIOCHIP_I2C_REC_SCHMIT = 0x00000000, 8863 DCIOCHIP_I2C_REC_COMPARATOR = 0x00000001, 8864 } DCIOCHIP_I2C_COMPSEL; 8865 8866 /* 8867 * DCIOCHIP_AUX_ALL_PWR_OK enum 8868 */ 8869 8870 typedef enum DCIOCHIP_AUX_ALL_PWR_OK { 8871 DCIOCHIP_AUX_ALL_PWR_OK_0 = 0x00000000, 8872 DCIOCHIP_AUX_ALL_PWR_OK_1 = 0x00000001, 8873 } DCIOCHIP_AUX_ALL_PWR_OK; 8874 8875 /* 8876 * DCIOCHIP_I2C_RECEIVER_SEL enum 8877 */ 8878 8879 typedef enum DCIOCHIP_I2C_RECEIVER_SEL { 8880 DCIOCHIP_I2C_RECEIVER_SEL_0 = 0x00000000, 8881 DCIOCHIP_I2C_RECEIVER_SEL_1 = 0x00000001, 8882 DCIOCHIP_I2C_RECEIVER_SEL_2 = 0x00000002, 8883 DCIOCHIP_I2C_RECEIVER_SEL_3 = 0x00000003, 8884 } DCIOCHIP_I2C_RECEIVER_SEL; 8885 8886 /* 8887 * DCIOCHIP_AUX_RECEIVER_SEL enum 8888 */ 8889 8890 typedef enum DCIOCHIP_AUX_RECEIVER_SEL { 8891 DCIOCHIP_AUX_RECEIVER_SEL_0 = 0x00000000, 8892 DCIOCHIP_AUX_RECEIVER_SEL_1 = 0x00000001, 8893 DCIOCHIP_AUX_RECEIVER_SEL_2 = 0x00000002, 8894 DCIOCHIP_AUX_RECEIVER_SEL_3 = 0x00000003, 8895 } DCIOCHIP_AUX_RECEIVER_SEL; 8896 8897 /******************************************************* 8898 * AZCONTROLLER Enums 8899 *******************************************************/ 8900 8901 /* 8902 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum 8903 */ 8904 8905 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { 8906 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000, 8907 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001, 8908 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; 8909 8910 /* 8911 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum 8912 */ 8913 8914 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { 8915 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000, 8916 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001, 8917 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; 8918 8919 /* 8920 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum 8921 */ 8922 8923 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { 8924 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000, 8925 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001, 8926 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS; 8927 8928 /* 8929 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum 8930 */ 8931 8932 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { 8933 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000, 8934 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001, 8935 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; 8936 8937 /* 8938 * AZ_GLOBAL_CAPABILITIES enum 8939 */ 8940 8941 typedef enum AZ_GLOBAL_CAPABILITIES { 8942 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000, 8943 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001, 8944 } AZ_GLOBAL_CAPABILITIES; 8945 8946 /* 8947 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum 8948 */ 8949 8950 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { 8951 ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000, 8952 ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001, 8953 } GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; 8954 8955 /* 8956 * GLOBAL_CONTROL_FLUSH_CONTROL enum 8957 */ 8958 8959 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { 8960 FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000, 8961 FLUSH_CONTROL_FLUSH_STARTED = 0x00000001, 8962 } GLOBAL_CONTROL_FLUSH_CONTROL; 8963 8964 /* 8965 * GLOBAL_CONTROL_CONTROLLER_RESET enum 8966 */ 8967 8968 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { 8969 CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000, 8970 CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001, 8971 } GLOBAL_CONTROL_CONTROLLER_RESET; 8972 8973 /* 8974 * AZ_STATE_CHANGE_STATUS enum 8975 */ 8976 8977 typedef enum AZ_STATE_CHANGE_STATUS { 8978 AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000, 8979 AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001, 8980 } AZ_STATE_CHANGE_STATUS; 8981 8982 /* 8983 * GLOBAL_STATUS_FLUSH_STATUS enum 8984 */ 8985 8986 typedef enum GLOBAL_STATUS_FLUSH_STATUS { 8987 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000, 8988 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001, 8989 } GLOBAL_STATUS_FLUSH_STATUS; 8990 8991 /* 8992 * STREAM_0_SYNCHRONIZATION enum 8993 */ 8994 8995 typedef enum STREAM_0_SYNCHRONIZATION { 8996 STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 8997 STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 8998 } STREAM_0_SYNCHRONIZATION; 8999 9000 /* 9001 * STREAM_1_SYNCHRONIZATION enum 9002 */ 9003 9004 typedef enum STREAM_1_SYNCHRONIZATION { 9005 STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 9006 STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 9007 } STREAM_1_SYNCHRONIZATION; 9008 9009 /* 9010 * STREAM_2_SYNCHRONIZATION enum 9011 */ 9012 9013 typedef enum STREAM_2_SYNCHRONIZATION { 9014 STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 9015 STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 9016 } STREAM_2_SYNCHRONIZATION; 9017 9018 /* 9019 * STREAM_3_SYNCHRONIZATION enum 9020 */ 9021 9022 typedef enum STREAM_3_SYNCHRONIZATION { 9023 STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 9024 STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 9025 } STREAM_3_SYNCHRONIZATION; 9026 9027 /* 9028 * STREAM_4_SYNCHRONIZATION enum 9029 */ 9030 9031 typedef enum STREAM_4_SYNCHRONIZATION { 9032 STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 9033 STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 9034 } STREAM_4_SYNCHRONIZATION; 9035 9036 /* 9037 * STREAM_5_SYNCHRONIZATION enum 9038 */ 9039 9040 typedef enum STREAM_5_SYNCHRONIZATION { 9041 STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 9042 STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 9043 } STREAM_5_SYNCHRONIZATION; 9044 9045 /* 9046 * STREAM_6_SYNCHRONIZATION enum 9047 */ 9048 9049 typedef enum STREAM_6_SYNCHRONIZATION { 9050 STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9051 STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9052 } STREAM_6_SYNCHRONIZATION; 9053 9054 /* 9055 * STREAM_7_SYNCHRONIZATION enum 9056 */ 9057 9058 typedef enum STREAM_7_SYNCHRONIZATION { 9059 STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9060 STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9061 } STREAM_7_SYNCHRONIZATION; 9062 9063 /* 9064 * STREAM_8_SYNCHRONIZATION enum 9065 */ 9066 9067 typedef enum STREAM_8_SYNCHRONIZATION { 9068 STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9069 STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9070 } STREAM_8_SYNCHRONIZATION; 9071 9072 /* 9073 * STREAM_9_SYNCHRONIZATION enum 9074 */ 9075 9076 typedef enum STREAM_9_SYNCHRONIZATION { 9077 STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9078 STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9079 } STREAM_9_SYNCHRONIZATION; 9080 9081 /* 9082 * STREAM_10_SYNCHRONIZATION enum 9083 */ 9084 9085 typedef enum STREAM_10_SYNCHRONIZATION { 9086 STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9087 STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9088 } STREAM_10_SYNCHRONIZATION; 9089 9090 /* 9091 * STREAM_11_SYNCHRONIZATION enum 9092 */ 9093 9094 typedef enum STREAM_11_SYNCHRONIZATION { 9095 STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9096 STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9097 } STREAM_11_SYNCHRONIZATION; 9098 9099 /* 9100 * STREAM_12_SYNCHRONIZATION enum 9101 */ 9102 9103 typedef enum STREAM_12_SYNCHRONIZATION { 9104 STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9105 STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9106 } STREAM_12_SYNCHRONIZATION; 9107 9108 /* 9109 * STREAM_13_SYNCHRONIZATION enum 9110 */ 9111 9112 typedef enum STREAM_13_SYNCHRONIZATION { 9113 STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9114 STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9115 } STREAM_13_SYNCHRONIZATION; 9116 9117 /* 9118 * STREAM_14_SYNCHRONIZATION enum 9119 */ 9120 9121 typedef enum STREAM_14_SYNCHRONIZATION { 9122 STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9123 STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9124 } STREAM_14_SYNCHRONIZATION; 9125 9126 /* 9127 * STREAM_15_SYNCHRONIZATION enum 9128 */ 9129 9130 typedef enum STREAM_15_SYNCHRONIZATION { 9131 STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9132 STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9133 } STREAM_15_SYNCHRONIZATION; 9134 9135 /* 9136 * CORB_READ_POINTER_RESET enum 9137 */ 9138 9139 typedef enum CORB_READ_POINTER_RESET { 9140 CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000, 9141 CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001, 9142 } CORB_READ_POINTER_RESET; 9143 9144 /* 9145 * AZ_CORB_SIZE enum 9146 */ 9147 9148 typedef enum AZ_CORB_SIZE { 9149 AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000, 9150 AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001, 9151 AZ_CORB_SIZE_256ENTRIES = 0x00000002, 9152 AZ_CORB_SIZE_RESERVED = 0x00000003, 9153 } AZ_CORB_SIZE; 9154 9155 /* 9156 * AZ_RIRB_WRITE_POINTER_RESET enum 9157 */ 9158 9159 typedef enum AZ_RIRB_WRITE_POINTER_RESET { 9160 AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000, 9161 AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001, 9162 } AZ_RIRB_WRITE_POINTER_RESET; 9163 9164 /* 9165 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum 9166 */ 9167 9168 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { 9169 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, 9170 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, 9171 } RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; 9172 9173 /* 9174 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum 9175 */ 9176 9177 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { 9178 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, 9179 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, 9180 } RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; 9181 9182 /* 9183 * AZ_RIRB_SIZE enum 9184 */ 9185 9186 typedef enum AZ_RIRB_SIZE { 9187 AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000, 9188 AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001, 9189 AZ_RIRB_SIZE_256ENTRIES = 0x00000002, 9190 AZ_RIRB_SIZE_UNDEFINED = 0x00000003, 9191 } AZ_RIRB_SIZE; 9192 9193 /* 9194 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum 9195 */ 9196 9197 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { 9198 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000, 9199 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001, 9200 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; 9201 9202 /* 9203 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum 9204 */ 9205 9206 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { 9207 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000, 9208 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001, 9209 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; 9210 9211 /* 9212 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum 9213 */ 9214 9215 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { 9216 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000, 9217 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001, 9218 } DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; 9219 9220 /******************************************************* 9221 * AZENDPOINT Enums 9222 *******************************************************/ 9223 9224 /* 9225 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum 9226 */ 9227 9228 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { 9229 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, 9230 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, 9231 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; 9232 9233 /* 9234 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum 9235 */ 9236 9237 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { 9238 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, 9239 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, 9240 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; 9241 9242 /* 9243 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum 9244 */ 9245 9246 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { 9247 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, 9248 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, 9249 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, 9250 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, 9251 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, 9252 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; 9253 9254 /* 9255 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum 9256 */ 9257 9258 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { 9259 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, 9260 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, 9261 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, 9262 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, 9263 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, 9264 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, 9265 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, 9266 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, 9267 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; 9268 9269 /* 9270 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum 9271 */ 9272 9273 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { 9274 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, 9275 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, 9276 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, 9277 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, 9278 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, 9279 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, 9280 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; 9281 9282 /* 9283 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum 9284 */ 9285 9286 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { 9287 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, 9288 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, 9289 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, 9290 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, 9291 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, 9292 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, 9293 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, 9294 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, 9295 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, 9296 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; 9297 9298 /* 9299 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum 9300 */ 9301 9302 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { 9303 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000, 9304 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001, 9305 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; 9306 9307 /* 9308 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum 9309 */ 9310 9311 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { 9312 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000, 9313 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001, 9314 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; 9315 9316 /* 9317 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum 9318 */ 9319 9320 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { 9321 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000, 9322 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001, 9323 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; 9324 9325 /* 9326 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum 9327 */ 9328 9329 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { 9330 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000, 9331 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001, 9332 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; 9333 9334 /* 9335 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum 9336 */ 9337 9338 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { 9339 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000, 9340 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001, 9341 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; 9342 9343 /* 9344 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum 9345 */ 9346 9347 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { 9348 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000, 9349 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001, 9350 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; 9351 9352 /* 9353 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum 9354 */ 9355 9356 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { 9357 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000, 9358 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001, 9359 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; 9360 9361 /* 9362 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum 9363 */ 9364 9365 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { 9366 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, 9367 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, 9368 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; 9369 9370 /* 9371 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum 9372 */ 9373 9374 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { 9375 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000, 9376 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001, 9377 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; 9378 9379 /* 9380 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum 9381 */ 9382 9383 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { 9384 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000, 9385 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001, 9386 } AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; 9387 9388 /* 9389 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum 9390 */ 9391 9392 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { 9393 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, 9394 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, 9395 } AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; 9396 9397 /* 9398 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum 9399 */ 9400 9401 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { 9402 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000, 9403 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001, 9404 } AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; 9405 9406 /* 9407 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum 9408 */ 9409 9410 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { 9411 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000, 9412 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001, 9413 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; 9414 9415 /* 9416 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum 9417 */ 9418 9419 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { 9420 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000, 9421 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001, 9422 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; 9423 9424 /* 9425 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum 9426 */ 9427 9428 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { 9429 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000, 9430 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001, 9431 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; 9432 9433 /* 9434 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum 9435 */ 9436 9437 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { 9438 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000, 9439 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001, 9440 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; 9441 9442 /* 9443 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum 9444 */ 9445 9446 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { 9447 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, 9448 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, 9449 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; 9450 9451 /* 9452 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum 9453 */ 9454 9455 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { 9456 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, 9457 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, 9458 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; 9459 9460 /* 9461 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum 9462 */ 9463 9464 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { 9465 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, 9466 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, 9467 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; 9468 9469 /* 9470 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum 9471 */ 9472 9473 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { 9474 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, 9475 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, 9476 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; 9477 9478 /* 9479 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum 9480 */ 9481 9482 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { 9483 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, 9484 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, 9485 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; 9486 9487 /* 9488 * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum 9489 */ 9490 9491 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE { 9492 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0x00000000, 9493 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 0x00000001, 9494 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 0x00000002, 9495 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 0x00000003, 9496 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 0x00000004, 9497 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 0x00000005, 9498 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 0x00000006, 9499 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 0x00000007, 9500 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 0x00000008, 9501 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 0x00000009, 9502 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 0x0000000a, 9503 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 0x0000000b, 9504 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 0x0000000c, 9505 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 0x0000000d, 9506 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 0x0000000e, 9507 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 0x0000000f, 9508 } AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE; 9509 9510 /******************************************************* 9511 * AZF0CONTROLLER Enums 9512 *******************************************************/ 9513 9514 /* 9515 * MEM_PWR_FORCE_CTRL enum 9516 */ 9517 9518 typedef enum MEM_PWR_FORCE_CTRL { 9519 NO_FORCE_REQUEST = 0x00000000, 9520 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 9521 FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 9522 FORCE_SHUT_DOWN_REQUEST = 0x00000003, 9523 } MEM_PWR_FORCE_CTRL; 9524 9525 /* 9526 * MEM_PWR_FORCE_CTRL2 enum 9527 */ 9528 9529 typedef enum MEM_PWR_FORCE_CTRL2 { 9530 NO_FORCE_REQ = 0x00000000, 9531 FORCE_LIGHT_SLEEP_REQ = 0x00000001, 9532 } MEM_PWR_FORCE_CTRL2; 9533 9534 /* 9535 * MEM_PWR_DIS_CTRL enum 9536 */ 9537 9538 typedef enum MEM_PWR_DIS_CTRL { 9539 ENABLE_MEM_PWR_CTRL = 0x00000000, 9540 DISABLE_MEM_PWR_CTRL = 0x00000001, 9541 } MEM_PWR_DIS_CTRL; 9542 9543 /* 9544 * MEM_PWR_SEL_CTRL enum 9545 */ 9546 9547 typedef enum MEM_PWR_SEL_CTRL { 9548 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, 9549 DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, 9550 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, 9551 } MEM_PWR_SEL_CTRL; 9552 9553 /* 9554 * MEM_PWR_SEL_CTRL2 enum 9555 */ 9556 9557 typedef enum MEM_PWR_SEL_CTRL2 { 9558 DYNAMIC_DEEP_SLEEP_EN = 0x00000000, 9559 DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, 9560 } MEM_PWR_SEL_CTRL2; 9561 9562 /* 9563 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum 9564 */ 9565 9566 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET { 9567 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000, 9568 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001, 9569 } AZALIA_SOFT_RESET_REFCLK_SOFT_RESET; 9570 9571 /******************************************************* 9572 * AZF0ROOT Enums 9573 *******************************************************/ 9574 9575 /* 9576 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum 9577 */ 9578 9579 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { 9580 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000, 9581 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001, 9582 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002, 9583 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003, 9584 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004, 9585 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005, 9586 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006, 9587 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007, 9588 } CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; 9589 9590 /* 9591 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum 9592 */ 9593 9594 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { 9595 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000, 9596 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001, 9597 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002, 9598 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003, 9599 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004, 9600 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005, 9601 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006, 9602 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007, 9603 } CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; 9604 9605 /******************************************************* 9606 * AZINPUTENDPOINT Enums 9607 *******************************************************/ 9608 9609 /* 9610 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum 9611 */ 9612 9613 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { 9614 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, 9615 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, 9616 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; 9617 9618 /* 9619 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum 9620 */ 9621 9622 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { 9623 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, 9624 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, 9625 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; 9626 9627 /* 9628 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum 9629 */ 9630 9631 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { 9632 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, 9633 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, 9634 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, 9635 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, 9636 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, 9637 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; 9638 9639 /* 9640 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum 9641 */ 9642 9643 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { 9644 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, 9645 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, 9646 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, 9647 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, 9648 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, 9649 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, 9650 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, 9651 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, 9652 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; 9653 9654 /* 9655 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum 9656 */ 9657 9658 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { 9659 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, 9660 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, 9661 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, 9662 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, 9663 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, 9664 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, 9665 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; 9666 9667 /* 9668 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum 9669 */ 9670 9671 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { 9672 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, 9673 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, 9674 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, 9675 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, 9676 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, 9677 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, 9678 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, 9679 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, 9680 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, 9681 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; 9682 9683 /* 9684 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum 9685 */ 9686 9687 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { 9688 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, 9689 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, 9690 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; 9691 9692 /* 9693 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum 9694 */ 9695 9696 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { 9697 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000, 9698 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001, 9699 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; 9700 9701 /* 9702 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum 9703 */ 9704 9705 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { 9706 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, 9707 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, 9708 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; 9709 9710 /* 9711 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum 9712 */ 9713 9714 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { 9715 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000, 9716 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001, 9717 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; 9718 9719 /* 9720 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum 9721 */ 9722 9723 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { 9724 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, 9725 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, 9726 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; 9727 9728 /* 9729 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum 9730 */ 9731 9732 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { 9733 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000, 9734 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001, 9735 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; 9736 9737 /* 9738 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum 9739 */ 9740 9741 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { 9742 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, 9743 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, 9744 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; 9745 9746 /* 9747 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum 9748 */ 9749 9750 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { 9751 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000, 9752 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001, 9753 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; 9754 9755 /* 9756 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum 9757 */ 9758 9759 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { 9760 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, 9761 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, 9762 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; 9763 9764 /* 9765 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum 9766 */ 9767 9768 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { 9769 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000, 9770 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001, 9771 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; 9772 9773 /* 9774 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum 9775 */ 9776 9777 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { 9778 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, 9779 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, 9780 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; 9781 9782 /******************************************************* 9783 * AZROOT Enums 9784 *******************************************************/ 9785 9786 /* 9787 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum 9788 */ 9789 9790 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { 9791 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000, 9792 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001, 9793 } AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; 9794 9795 /******************************************************* 9796 * AZF0STREAM Enums 9797 *******************************************************/ 9798 9799 /* 9800 * AZ_LATENCY_COUNTER_CONTROL enum 9801 */ 9802 9803 typedef enum AZ_LATENCY_COUNTER_CONTROL { 9804 AZ_LATENCY_COUNTER_NO_RESET = 0x00000000, 9805 AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001, 9806 } AZ_LATENCY_COUNTER_CONTROL; 9807 9808 /******************************************************* 9809 * AZSTREAM Enums 9810 *******************************************************/ 9811 9812 /* 9813 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum 9814 */ 9815 9816 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { 9817 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000, 9818 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001, 9819 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; 9820 9821 /* 9822 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum 9823 */ 9824 9825 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { 9826 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000, 9827 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001, 9828 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; 9829 9830 /* 9831 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum 9832 */ 9833 9834 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { 9835 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000, 9836 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001, 9837 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; 9838 9839 /* 9840 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum 9841 */ 9842 9843 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { 9844 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000, 9845 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001, 9846 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; 9847 9848 /* 9849 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum 9850 */ 9851 9852 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { 9853 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000, 9854 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001, 9855 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; 9856 9857 /* 9858 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum 9859 */ 9860 9861 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { 9862 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000, 9863 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001, 9864 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; 9865 9866 /* 9867 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum 9868 */ 9869 9870 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { 9871 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000, 9872 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001, 9873 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; 9874 9875 /* 9876 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum 9877 */ 9878 9879 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { 9880 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000, 9881 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001, 9882 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; 9883 9884 /* 9885 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum 9886 */ 9887 9888 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { 9889 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000, 9890 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001, 9891 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; 9892 9893 /* 9894 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum 9895 */ 9896 9897 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { 9898 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, 9899 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, 9900 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; 9901 9902 /* 9903 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum 9904 */ 9905 9906 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { 9907 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, 9908 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, 9909 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, 9910 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, 9911 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, 9912 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; 9913 9914 /* 9915 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum 9916 */ 9917 9918 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { 9919 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, 9920 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, 9921 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, 9922 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, 9923 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, 9924 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, 9925 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, 9926 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, 9927 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; 9928 9929 /* 9930 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum 9931 */ 9932 9933 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { 9934 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, 9935 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, 9936 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, 9937 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, 9938 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, 9939 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, 9940 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; 9941 9942 /* 9943 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum 9944 */ 9945 9946 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { 9947 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, 9948 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, 9949 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, 9950 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, 9951 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, 9952 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, 9953 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, 9954 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, 9955 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008, 9956 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009, 9957 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a, 9958 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b, 9959 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c, 9960 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d, 9961 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e, 9962 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f, 9963 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; 9964 9965 /******************************************************* 9966 * AZF0ENDPOINT Enums 9967 *******************************************************/ 9968 9969 /* 9970 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum 9971 */ 9972 9973 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 9974 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, 9975 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, 9976 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, 9977 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, 9978 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, 9979 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, 9980 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, 9981 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, 9982 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, 9983 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, 9984 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 9985 9986 /* 9987 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum 9988 */ 9989 9990 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 9991 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, 9992 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, 9993 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 9994 9995 /* 9996 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum 9997 */ 9998 9999 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 10000 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, 10001 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, 10002 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 10003 10004 /* 10005 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum 10006 */ 10007 10008 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 10009 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, 10010 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, 10011 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 10012 10013 /* 10014 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum 10015 */ 10016 10017 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 10018 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, 10019 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, 10020 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 10021 10022 /* 10023 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum 10024 */ 10025 10026 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 10027 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, 10028 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, 10029 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 10030 10031 /* 10032 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum 10033 */ 10034 10035 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 10036 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, 10037 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, 10038 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 10039 10040 /* 10041 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum 10042 */ 10043 10044 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 10045 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, 10046 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, 10047 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 10048 10049 /* 10050 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum 10051 */ 10052 10053 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { 10054 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, 10055 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001, 10056 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; 10057 10058 /* 10059 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum 10060 */ 10061 10062 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 10063 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, 10064 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, 10065 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 10066 10067 /* 10068 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum 10069 */ 10070 10071 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 10072 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, 10073 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, 10074 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 10075 10076 /* 10077 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum 10078 */ 10079 10080 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 10081 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, 10082 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, 10083 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 10084 10085 /* 10086 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum 10087 */ 10088 10089 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { 10090 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, 10091 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, 10092 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; 10093 10094 /* 10095 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum 10096 */ 10097 10098 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 10099 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, 10100 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, 10101 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, 10102 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, 10103 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, 10104 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, 10105 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, 10106 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, 10107 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, 10108 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, 10109 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 10110 10111 /* 10112 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum 10113 */ 10114 10115 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 10116 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, 10117 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, 10118 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 10119 10120 /* 10121 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum 10122 */ 10123 10124 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 10125 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, 10126 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, 10127 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 10128 10129 /* 10130 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum 10131 */ 10132 10133 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 10134 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, 10135 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, 10136 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 10137 10138 /* 10139 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum 10140 */ 10141 10142 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 10143 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, 10144 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, 10145 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 10146 10147 /* 10148 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum 10149 */ 10150 10151 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 10152 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, 10153 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, 10154 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 10155 10156 /* 10157 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum 10158 */ 10159 10160 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 10161 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, 10162 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, 10163 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 10164 10165 /* 10166 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum 10167 */ 10168 10169 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 10170 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, 10171 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, 10172 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 10173 10174 /* 10175 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum 10176 */ 10177 10178 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 10179 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, 10180 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, 10181 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 10182 10183 /* 10184 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum 10185 */ 10186 10187 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 10188 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, 10189 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, 10190 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 10191 10192 /* 10193 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum 10194 */ 10195 10196 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 10197 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000, 10198 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, 10199 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 10200 10201 /* 10202 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum 10203 */ 10204 10205 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { 10206 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000, 10207 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001, 10208 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; 10209 10210 /* 10211 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum 10212 */ 10213 10214 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { 10215 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000, 10216 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, 10217 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; 10218 10219 /* 10220 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum 10221 */ 10222 10223 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { 10224 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, 10225 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, 10226 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; 10227 10228 /* 10229 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum 10230 */ 10231 10232 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { 10233 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, 10234 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, 10235 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; 10236 10237 /* 10238 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum 10239 */ 10240 10241 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { 10242 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, 10243 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, 10244 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; 10245 10246 /* 10247 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum 10248 */ 10249 10250 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { 10251 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000, 10252 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001, 10253 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; 10254 10255 /* 10256 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum 10257 */ 10258 10259 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { 10260 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, 10261 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, 10262 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; 10263 10264 /* 10265 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum 10266 */ 10267 10268 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { 10269 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, 10270 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, 10271 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; 10272 10273 /* 10274 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum 10275 */ 10276 10277 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { 10278 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, 10279 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, 10280 } AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; 10281 10282 /* 10283 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum 10284 */ 10285 10286 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { 10287 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000, 10288 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001, 10289 } AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; 10290 10291 /******************************************************* 10292 * AZF0INPUTENDPOINT Enums 10293 *******************************************************/ 10294 10295 /* 10296 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum 10297 */ 10298 10299 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 10300 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, 10301 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, 10302 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, 10303 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, 10304 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, 10305 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, 10306 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, 10307 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, 10308 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, 10309 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, 10310 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 10311 10312 /* 10313 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum 10314 */ 10315 10316 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 10317 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, 10318 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, 10319 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 10320 10321 /* 10322 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum 10323 */ 10324 10325 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 10326 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, 10327 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, 10328 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 10329 10330 /* 10331 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum 10332 */ 10333 10334 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 10335 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000, 10336 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001, 10337 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 10338 10339 /* 10340 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum 10341 */ 10342 10343 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 10344 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, 10345 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, 10346 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 10347 10348 /* 10349 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum 10350 */ 10351 10352 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 10353 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, 10354 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, 10355 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 10356 10357 /* 10358 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum 10359 */ 10360 10361 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 10362 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000, 10363 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001, 10364 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 10365 10366 /* 10367 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum 10368 */ 10369 10370 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 10371 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000, 10372 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, 10373 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 10374 10375 /* 10376 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum 10377 */ 10378 10379 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { 10380 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, 10381 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001, 10382 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; 10383 10384 /* 10385 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum 10386 */ 10387 10388 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 10389 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, 10390 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001, 10391 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 10392 10393 /* 10394 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum 10395 */ 10396 10397 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 10398 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, 10399 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, 10400 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 10401 10402 /* 10403 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum 10404 */ 10405 10406 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 10407 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, 10408 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, 10409 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 10410 10411 /* 10412 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum 10413 */ 10414 10415 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { 10416 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, 10417 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, 10418 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; 10419 10420 /* 10421 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum 10422 */ 10423 10424 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 10425 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, 10426 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, 10427 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, 10428 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, 10429 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, 10430 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, 10431 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, 10432 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, 10433 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, 10434 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, 10435 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 10436 10437 /* 10438 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum 10439 */ 10440 10441 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 10442 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000, 10443 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001, 10444 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 10445 10446 /* 10447 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum 10448 */ 10449 10450 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 10451 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, 10452 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, 10453 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 10454 10455 /* 10456 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum 10457 */ 10458 10459 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 10460 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, 10461 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, 10462 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 10463 10464 /* 10465 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum 10466 */ 10467 10468 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 10469 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, 10470 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, 10471 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 10472 10473 /* 10474 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum 10475 */ 10476 10477 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 10478 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, 10479 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, 10480 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 10481 10482 /* 10483 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum 10484 */ 10485 10486 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 10487 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000, 10488 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001, 10489 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 10490 10491 /* 10492 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum 10493 */ 10494 10495 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 10496 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, 10497 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, 10498 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 10499 10500 /* 10501 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum 10502 */ 10503 10504 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 10505 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, 10506 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, 10507 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 10508 10509 /* 10510 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum 10511 */ 10512 10513 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 10514 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, 10515 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, 10516 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 10517 10518 /* 10519 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum 10520 */ 10521 10522 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 10523 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, 10524 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, 10525 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 10526 10527 /* 10528 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum 10529 */ 10530 10531 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { 10532 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000, 10533 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001, 10534 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; 10535 10536 /* 10537 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum 10538 */ 10539 10540 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { 10541 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000, 10542 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001, 10543 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; 10544 10545 /* 10546 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum 10547 */ 10548 10549 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { 10550 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000, 10551 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001, 10552 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; 10553 10554 /* 10555 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum 10556 */ 10557 10558 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { 10559 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000, 10560 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, 10561 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; 10562 10563 /* 10564 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum 10565 */ 10566 10567 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { 10568 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, 10569 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, 10570 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; 10571 10572 /* 10573 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum 10574 */ 10575 10576 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { 10577 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, 10578 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, 10579 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; 10580 10581 /* 10582 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum 10583 */ 10584 10585 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { 10586 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, 10587 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, 10588 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; 10589 10590 /* 10591 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum 10592 */ 10593 10594 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { 10595 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000, 10596 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001, 10597 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; 10598 10599 /* 10600 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum 10601 */ 10602 10603 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { 10604 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, 10605 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, 10606 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; 10607 10608 /* 10609 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum 10610 */ 10611 10612 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { 10613 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, 10614 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, 10615 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; 10616 10617 /* 10618 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum 10619 */ 10620 10621 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { 10622 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000, 10623 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001, 10624 } AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; 10625 10626 /******************************************************* 10627 * DSCC Enums 10628 *******************************************************/ 10629 10630 /* 10631 * DSCC_ICH_RESET_ENUM enum 10632 */ 10633 10634 typedef enum DSCC_ICH_RESET_ENUM { 10635 DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 0x00000001, 10636 DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 0x00000002, 10637 DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 0x00000004, 10638 DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 0x00000008, 10639 } DSCC_ICH_RESET_ENUM; 10640 10641 /* 10642 * DSCC_DSC_VERSION_MINOR_ENUM enum 10643 */ 10644 10645 typedef enum DSCC_DSC_VERSION_MINOR_ENUM { 10646 DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 0x00000001, 10647 DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 0x00000002, 10648 } DSCC_DSC_VERSION_MINOR_ENUM; 10649 10650 /* 10651 * DSCC_DSC_VERSION_MAJOR_ENUM enum 10652 */ 10653 10654 typedef enum DSCC_DSC_VERSION_MAJOR_ENUM { 10655 DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 0x00000001, 10656 } DSCC_DSC_VERSION_MAJOR_ENUM; 10657 10658 /* 10659 * DSCC_LINEBUF_DEPTH_ENUM enum 10660 */ 10661 10662 typedef enum DSCC_LINEBUF_DEPTH_ENUM { 10663 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 0x00000008, 10664 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 0x00000009, 10665 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 0x0000000a, 10666 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 0x0000000b, 10667 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 0x0000000c, 10668 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 0x0000000d, 10669 } DSCC_LINEBUF_DEPTH_ENUM; 10670 10671 /* 10672 * DSCC_BITS_PER_COMPONENT_ENUM enum 10673 */ 10674 10675 typedef enum DSCC_BITS_PER_COMPONENT_ENUM { 10676 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008, 10677 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a, 10678 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c, 10679 } DSCC_BITS_PER_COMPONENT_ENUM; 10680 10681 /* 10682 * DSCC_ENABLE_ENUM enum 10683 */ 10684 10685 typedef enum DSCC_ENABLE_ENUM { 10686 DSCC_ENABLE_ENUM_DISABLED = 0x00000000, 10687 DSCC_ENABLE_ENUM_ENABLED = 0x00000001, 10688 } DSCC_ENABLE_ENUM; 10689 10690 /* 10691 * DSCC_MEM_PWR_FORCE_ENUM enum 10692 */ 10693 10694 typedef enum DSCC_MEM_PWR_FORCE_ENUM { 10695 DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0x00000000, 10696 DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 10697 DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 10698 DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 10699 } DSCC_MEM_PWR_FORCE_ENUM; 10700 10701 /* 10702 * POWER_STATE_ENUM enum 10703 */ 10704 10705 typedef enum POWER_STATE_ENUM { 10706 POWER_STATE_ENUM_ON = 0x00000000, 10707 POWER_STATE_ENUM_LS = 0x00000001, 10708 POWER_STATE_ENUM_DS = 0x00000002, 10709 POWER_STATE_ENUM_SD = 0x00000003, 10710 } POWER_STATE_ENUM; 10711 10712 /* 10713 * DSCC_MEM_PWR_DIS_ENUM enum 10714 */ 10715 10716 typedef enum DSCC_MEM_PWR_DIS_ENUM { 10717 DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0x00000000, 10718 DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 0x00000001, 10719 } DSCC_MEM_PWR_DIS_ENUM; 10720 10721 /******************************************************* 10722 * DSCCIF Enums 10723 *******************************************************/ 10724 10725 /* 10726 * DSCCIF_ENABLE_ENUM enum 10727 */ 10728 10729 typedef enum DSCCIF_ENABLE_ENUM { 10730 DSCCIF_ENABLE_ENUM_DISABLED = 0x00000000, 10731 DSCCIF_ENABLE_ENUM_ENABLED = 0x00000001, 10732 } DSCCIF_ENABLE_ENUM; 10733 10734 /* 10735 * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum 10736 */ 10737 10738 typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM { 10739 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0x00000000, 10740 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 0x00000001, 10741 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 0x00000002, 10742 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 0x00000003, 10743 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 0x00000004, 10744 } DSCCIF_INPUT_PIXEL_FORMAT_ENUM; 10745 10746 /* 10747 * DSCCIF_BITS_PER_COMPONENT_ENUM enum 10748 */ 10749 10750 typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM { 10751 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008, 10752 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a, 10753 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c, 10754 } DSCCIF_BITS_PER_COMPONENT_ENUM; 10755 10756 /******************************************************* 10757 * DSC_TOP Enums 10758 *******************************************************/ 10759 10760 /* 10761 * ENABLE_ENUM enum 10762 */ 10763 10764 typedef enum ENABLE_ENUM { 10765 ENABLE_ENUM_DISABLED = 0x00000000, 10766 ENABLE_ENUM_ENABLED = 0x00000001, 10767 } ENABLE_ENUM; 10768 10769 /* 10770 * CLOCK_GATING_DISABLE_ENUM enum 10771 */ 10772 10773 typedef enum CLOCK_GATING_DISABLE_ENUM { 10774 CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000, 10775 CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001, 10776 } CLOCK_GATING_DISABLE_ENUM; 10777 10778 /* 10779 * TEST_CLOCK_MUX_SELECT_ENUM enum 10780 */ 10781 10782 typedef enum TEST_CLOCK_MUX_SELECT_ENUM { 10783 TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000, 10784 TEST_CLOCK_MUX_SELECT_DISPCLK_G = 0x00000001, 10785 TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000002, 10786 TEST_CLOCK_MUX_SELECT_DSCCLK_P = 0x00000003, 10787 TEST_CLOCK_MUX_SELECT_DSCCLK_G = 0x00000004, 10788 TEST_CLOCK_MUX_SELECT_DSCCLK_R = 0x00000005, 10789 } TEST_CLOCK_MUX_SELECT_ENUM; 10790 10791 /******************************************************* 10792 * CNV Enums 10793 *******************************************************/ 10794 10795 /* 10796 * WB_ENABLE_ENUM enum 10797 */ 10798 10799 typedef enum WB_ENABLE_ENUM { 10800 WB_EN_DISABLE = 0x00000000, 10801 WB_EN_ENABLE = 0x00000001, 10802 } WB_ENABLE_ENUM; 10803 10804 /* 10805 * WB_CLK_GATE_DIS_ENUM enum 10806 */ 10807 10808 typedef enum WB_CLK_GATE_DIS_ENUM { 10809 WB_CLK_GATE_ENABLE = 0x00000000, 10810 WB_CLK_GATE_DISABLE = 0x00000001, 10811 } WB_CLK_GATE_DIS_ENUM; 10812 10813 /* 10814 * WB_MEM_PWR_DIS_ENUM enum 10815 */ 10816 10817 typedef enum WB_MEM_PWR_DIS_ENUM { 10818 WB_MEM_PWR_ENABLE = 0x00000000, 10819 WB_MEM_PWR_DISABLE = 0x00000001, 10820 } WB_MEM_PWR_DIS_ENUM; 10821 10822 /* 10823 * WB_TEST_CLK_SEL_ENUM enum 10824 */ 10825 10826 typedef enum WB_TEST_CLK_SEL_ENUM { 10827 WB_TEST_CLK_SEL_REG = 0x00000000, 10828 WB_TEST_CLK_SEL_WB = 0x00000001, 10829 WB_TEST_CLK_SEL_WBSCL = 0x00000002, 10830 WB_TEST_CLK_SEL_PERM = 0x00000003, 10831 } WB_TEST_CLK_SEL_ENUM; 10832 10833 /* 10834 * WBSCL_LB_MEM_PWR_MODE_SEL_ENUM enum 10835 */ 10836 10837 typedef enum WBSCL_LB_MEM_PWR_MODE_SEL_ENUM { 10838 WBSCL_LB_MEM_PWR_MODE_SEL_SD = 0x00000000, 10839 WBSCL_LB_MEM_PWR_MODE_SEL_DS = 0x00000001, 10840 WBSCL_LB_MEM_PWR_MODE_SEL_LS = 0x00000002, 10841 WBSCL_LB_MEM_PWR_MODE_SEL_ON = 0x00000003, 10842 } WBSCL_LB_MEM_PWR_MODE_SEL_ENUM; 10843 10844 /* 10845 * WBSCL_LB_MEM_PWR_FORCE_ENUM enum 10846 */ 10847 10848 typedef enum WBSCL_LB_MEM_PWR_FORCE_ENUM { 10849 WBSCL_LB_MEM_PWR_FORCE_NO = 0x00000000, 10850 WBSCL_LB_MEM_PWR_FORCE_LS = 0x00000001, 10851 WBSCL_LB_MEM_PWR_FORCE_DS = 0x00000002, 10852 WBSCL_LB_MEM_PWR_FORCE_SD = 0x00000003, 10853 } WBSCL_LB_MEM_PWR_FORCE_ENUM; 10854 10855 /* 10856 * WBSCL_MEM_PWR_STATE_ENUM enum 10857 */ 10858 10859 typedef enum WBSCL_MEM_PWR_STATE_ENUM { 10860 WBSCL_MEM_PWR_STATE_ON = 0x00000000, 10861 WBSCL_MEM_PWR_STATE_LS = 0x00000001, 10862 WBSCL_MEM_PWR_STATE_DS = 0x00000002, 10863 WBSCL_MEM_PWR_STATE_SD = 0x00000003, 10864 } WBSCL_MEM_PWR_STATE_ENUM; 10865 10866 /* 10867 * WBSCL_LUT_MEM_PWR_STATE_ENUM enum 10868 */ 10869 10870 typedef enum WBSCL_LUT_MEM_PWR_STATE_ENUM { 10871 WBSCL_LUT_MEM_PWR_STATE_ON = 0x00000000, 10872 WBSCL_LUT_MEM_PWR_STATE_LS = 0x00000001, 10873 WBSCL_LUT_MEM_PWR_STATE_RESERVED2 = 0x00000002, 10874 WBSCL_LUT_MEM_PWR_STATE_RESERVED3 = 0x00000003, 10875 } WBSCL_LUT_MEM_PWR_STATE_ENUM; 10876 10877 /* 10878 * WB_RAM_PW_SAVE_MODE_ENUM enum 10879 */ 10880 10881 typedef enum WB_RAM_PW_SAVE_MODE_ENUM { 10882 WB_RAM_PW_SAVE_MODE_LS = 0x00000000, 10883 WB_RAM_PW_SAVE_MODE_SD = 0x00000001, 10884 } WB_RAM_PW_SAVE_MODE_ENUM; 10885 10886 /* 10887 * CNV_OUT_BPC_ENUM enum 10888 */ 10889 10890 typedef enum CNV_OUT_BPC_ENUM { 10891 CNV_OUT_BPC_8BPC = 0x00000000, 10892 CNV_OUT_BPC_10BPC = 0x00000001, 10893 } CNV_OUT_BPC_ENUM; 10894 10895 /* 10896 * CNV_FRAME_CAPTURE_RATE_ENUM enum 10897 */ 10898 10899 typedef enum CNV_FRAME_CAPTURE_RATE_ENUM { 10900 CNV_FRAME_CAPTURE_RATE_0 = 0x00000000, 10901 CNV_FRAME_CAPTURE_RATE_1 = 0x00000001, 10902 CNV_FRAME_CAPTURE_RATE_2 = 0x00000002, 10903 CNV_FRAME_CAPTURE_RATE_3 = 0x00000003, 10904 } CNV_FRAME_CAPTURE_RATE_ENUM; 10905 10906 /* 10907 * CNV_WINDOW_CROP_EN_ENUM enum 10908 */ 10909 10910 typedef enum CNV_WINDOW_CROP_EN_ENUM { 10911 CNV_WINDOW_CROP_DISABLE = 0x00000000, 10912 CNV_WINDOW_CROP_ENABLE = 0x00000001, 10913 } CNV_WINDOW_CROP_EN_ENUM; 10914 10915 /* 10916 * CNV_INTERLACED_MODE_ENUM enum 10917 */ 10918 10919 typedef enum CNV_INTERLACED_MODE_ENUM { 10920 CNV_INTERLACED_MODE_PROGRESSIVE = 0x00000000, 10921 CNV_INTERLACED_MODE_INTERLACED = 0x00000001, 10922 } CNV_INTERLACED_MODE_ENUM; 10923 10924 /* 10925 * CNV_EYE_SELECT enum 10926 */ 10927 10928 typedef enum CNV_EYE_SELECT { 10929 STEREO_DISABLED = 0x00000000, 10930 LEFT_EYE = 0x00000001, 10931 RIGHT_EYE = 0x00000002, 10932 BOTH_EYE = 0x00000003, 10933 } CNV_EYE_SELECT; 10934 10935 /* 10936 * CNV_STEREO_TYPE_ENUM enum 10937 */ 10938 10939 typedef enum CNV_STEREO_TYPE_ENUM { 10940 CNV_STEREO_TYPE_RESERVED0 = 0x00000000, 10941 CNV_STEREO_TYPE_RESERVED1 = 0x00000001, 10942 CNV_STEREO_TYPE_RESERVED2 = 0x00000002, 10943 CNV_STEREO_TYPE_FRAME_SEQUENTIAL = 0x00000003, 10944 } CNV_STEREO_TYPE_ENUM; 10945 10946 /* 10947 * CNV_STEREO_POLARITY_ENUM enum 10948 */ 10949 10950 typedef enum CNV_STEREO_POLARITY_ENUM { 10951 CNV_STEREO_POLARITY_LEFT = 0x00000000, 10952 CNV_STEREO_POLARITY_RIGHT = 0x00000001, 10953 } CNV_STEREO_POLARITY_ENUM; 10954 10955 /* 10956 * CNV_INTERLACED_FIELD_ORDER_ENUM enum 10957 */ 10958 10959 typedef enum CNV_INTERLACED_FIELD_ORDER_ENUM { 10960 CNV_INTERLACED_FIELD_ORDER_TOP = 0x00000000, 10961 CNV_INTERLACED_FIELD_ORDER_BOT = 0x00000001, 10962 } CNV_INTERLACED_FIELD_ORDER_ENUM; 10963 10964 /* 10965 * CNV_STEREO_SPLIT_ENUM enum 10966 */ 10967 10968 typedef enum CNV_STEREO_SPLIT_ENUM { 10969 CNV_STEREO_SPLIT_DISABLE = 0x00000000, 10970 CNV_STEREO_SPLIT_ENABLE = 0x00000001, 10971 } CNV_STEREO_SPLIT_ENUM; 10972 10973 /* 10974 * CNV_NEW_CONTENT_ENUM enum 10975 */ 10976 10977 typedef enum CNV_NEW_CONTENT_ENUM { 10978 CNV_NEW_CONTENT_NEG = 0x00000000, 10979 CNV_NEW_CONTENT_POS = 0x00000001, 10980 } CNV_NEW_CONTENT_ENUM; 10981 10982 /* 10983 * CNV_FRAME_CAPTURE_EN_ENUM enum 10984 */ 10985 10986 typedef enum CNV_FRAME_CAPTURE_EN_ENUM { 10987 CNV_FRAME_CAPTURE_DISABLE = 0x00000000, 10988 CNV_FRAME_CAPTURE_ENABLE = 0x00000001, 10989 } CNV_FRAME_CAPTURE_EN_ENUM; 10990 10991 /* 10992 * CNV_UPDATE_PENDING_ENUM enum 10993 */ 10994 10995 typedef enum CNV_UPDATE_PENDING_ENUM { 10996 CNV_UPDATE_PENDING_NEG = 0x00000000, 10997 CNV_UPDATE_PENDING_POS = 0x00000001, 10998 } CNV_UPDATE_PENDING_ENUM; 10999 11000 /* 11001 * CNV_UPDATE_LOCK_ENUM enum 11002 */ 11003 11004 typedef enum CNV_UPDATE_LOCK_ENUM { 11005 CNV_UPDATE_UNLOCK = 0x00000000, 11006 CNV_UPDATE_LOCK = 0x00000001, 11007 } CNV_UPDATE_LOCK_ENUM; 11008 11009 /* 11010 * CNV_CSC_BYPASS_ENUM enum 11011 */ 11012 11013 typedef enum CNV_CSC_BYPASS_ENUM { 11014 CNV_CSC_BYPASS_NEG = 0x00000000, 11015 CNV_CSC_BYPASS_POS = 0x00000001, 11016 } CNV_CSC_BYPASS_ENUM; 11017 11018 /* 11019 * CNV_TEST_CRC_EN_ENUM enum 11020 */ 11021 11022 typedef enum CNV_TEST_CRC_EN_ENUM { 11023 CNV_TEST_CRC_DISABLE = 0x00000000, 11024 CNV_TEST_CRC_ENABLE = 0x00000001, 11025 } CNV_TEST_CRC_EN_ENUM; 11026 11027 /* 11028 * CNV_TEST_CRC_CONT_EN_ENUM enum 11029 */ 11030 11031 typedef enum CNV_TEST_CRC_CONT_EN_ENUM { 11032 CNV_TEST_CRC_CONT_DISABLE = 0x00000000, 11033 CNV_TEST_CRC_CONT_ENABLE = 0x00000001, 11034 } CNV_TEST_CRC_CONT_EN_ENUM; 11035 11036 /* 11037 * WB_SOFT_RESET_ENUM enum 11038 */ 11039 11040 typedef enum WB_SOFT_RESET_ENUM { 11041 WB_SOFT_RESET_NEG = 0x00000000, 11042 WB_SOFT_RESET_POS = 0x00000001, 11043 } WB_SOFT_RESET_ENUM; 11044 11045 /* 11046 * DWB_GMC_WARM_UP_ENABLE_ENUM enum 11047 */ 11048 11049 typedef enum DWB_GMC_WARM_UP_ENABLE_ENUM { 11050 DWB_GMC_WARM_UP_DISABLE = 0x00000000, 11051 DWB_GMC_WARM_UP_ENABLE = 0x00000001, 11052 } DWB_GMC_WARM_UP_ENABLE_ENUM; 11053 11054 /* 11055 * DWB_MODE_WARMUP_ENUM enum 11056 */ 11057 11058 typedef enum DWB_MODE_WARMUP_ENUM { 11059 DWB_MODE_WARMUP_420 = 0x00000000, 11060 DWB_MODE_WARMUP_444 = 0x00000001, 11061 } DWB_MODE_WARMUP_ENUM; 11062 11063 /* 11064 * DWB_DATA_DEPTH_WARMUP_ENUM enum 11065 */ 11066 11067 typedef enum DWB_DATA_DEPTH_WARMUP_ENUM { 11068 DWB_DATA_DEPTH_WARMUP_8BPC = 0x00000000, 11069 DWB_DATA_DEPTH_WARMUP_10BPC = 0x00000001, 11070 } DWB_DATA_DEPTH_WARMUP_ENUM; 11071 11072 /******************************************************* 11073 * WBSCL Enums 11074 *******************************************************/ 11075 11076 /* 11077 * WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM enum 11078 */ 11079 11080 typedef enum WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM { 11081 WBSCL_COEF_RAM_TAP_PAIR_IDX0 = 0x00000000, 11082 WBSCL_COEF_RAM_TAP_PAIR_IDX1 = 0x00000001, 11083 WBSCL_COEF_RAM_TAP_PAIR_IDX2 = 0x00000002, 11084 WBSCL_COEF_RAM_TAP_PAIR_IDX3 = 0x00000003, 11085 WBSCL_COEF_RAM_TAP_PAIR_IDX4 = 0x00000004, 11086 WBSCL_COEF_RAM_TAP_PAIR_IDX5 = 0x00000005, 11087 } WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM; 11088 11089 /* 11090 * WBSCL_COEF_RAM_PHASE_ENUM enum 11091 */ 11092 11093 typedef enum WBSCL_COEF_RAM_PHASE_ENUM { 11094 WBSCL_COEF_RAM_PHASE0 = 0x00000000, 11095 WBSCL_COEF_RAM_PHASE1 = 0x00000001, 11096 WBSCL_COEF_RAM_PHASE2 = 0x00000002, 11097 WBSCL_COEF_RAM_PHASE3 = 0x00000003, 11098 WBSCL_COEF_RAM_PHASE4 = 0x00000004, 11099 WBSCL_COEF_RAM_PHASE5 = 0x00000005, 11100 WBSCL_COEF_RAM_PHASE6 = 0x00000006, 11101 WBSCL_COEF_RAM_PHASE7 = 0x00000007, 11102 WBSCL_COEF_RAM_PHASE8 = 0x00000008, 11103 } WBSCL_COEF_RAM_PHASE_ENUM; 11104 11105 /* 11106 * WBSCL_COEF_RAM_FILTER_TYPE_ENUM enum 11107 */ 11108 11109 typedef enum WBSCL_COEF_RAM_FILTER_TYPE_ENUM { 11110 WBSCL_COEF_RAM_FILTER_TYPE_VL = 0x00000000, 11111 WBSCL_COEF_RAM_FILTER_TYPE_VC = 0x00000001, 11112 WBSCL_COEF_RAM_FILTER_TYPE_HL = 0x00000002, 11113 WBSCL_COEF_RAM_FILTER_TYPE_HC = 0x00000003, 11114 } WBSCL_COEF_RAM_FILTER_TYPE_ENUM; 11115 11116 /* 11117 * WBSCL_COEF_FILTER_TYPE_SEL enum 11118 */ 11119 11120 typedef enum WBSCL_COEF_FILTER_TYPE_SEL { 11121 WBSCL_COEF_LUMA_VERT_FILTER = 0x00000000, 11122 WBSCL_COEF_CHROMA_VERT_FILTER = 0x00000001, 11123 WBSCL_COEF_LUMA_HORZ_FILTER = 0x00000002, 11124 WBSCL_COEF_CHROMA_HORZ_FILTER = 0x00000003, 11125 } WBSCL_COEF_FILTER_TYPE_SEL; 11126 11127 /* 11128 * WBSCL_MODE_SEL enum 11129 */ 11130 11131 typedef enum WBSCL_MODE_SEL { 11132 WBSCL_MODE_SCALING_444_BYPASS = 0x00000000, 11133 WBSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001, 11134 WBSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002, 11135 WBSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003, 11136 } WBSCL_MODE_SEL; 11137 11138 /* 11139 * WBSCL_PIXEL_DEPTH enum 11140 */ 11141 11142 typedef enum WBSCL_PIXEL_DEPTH { 11143 PIXEL_DEPTH_8BPC = 0x00000000, 11144 PIXEL_DEPTH_10BPC = 0x00000001, 11145 } WBSCL_PIXEL_DEPTH; 11146 11147 /* 11148 * WBSCL_COEF_RAM_SEL_ENUM enum 11149 */ 11150 11151 typedef enum WBSCL_COEF_RAM_SEL_ENUM { 11152 WBSCL_COEF_RAM_SEL_0 = 0x00000000, 11153 WBSCL_COEF_RAM_SEL_1 = 0x00000001, 11154 } WBSCL_COEF_RAM_SEL_ENUM; 11155 11156 /* 11157 * WBSCL_COEF_RAM_RD_SEL_ENUM enum 11158 */ 11159 11160 typedef enum WBSCL_COEF_RAM_RD_SEL_ENUM { 11161 WBSCL_COEF_RAM_RD_SEL_0 = 0x00000000, 11162 WBSCL_COEF_RAM_RD_SEL_1 = 0x00000001, 11163 } WBSCL_COEF_RAM_RD_SEL_ENUM; 11164 11165 /* 11166 * WBSCL_COEF_RAM_TAP_COEF_EN_ENUM enum 11167 */ 11168 11169 typedef enum WBSCL_COEF_RAM_TAP_COEF_EN_ENUM { 11170 WBSCL_COEF_RAM_TAP_COEF_DISABLE = 0x00000000, 11171 WBSCL_COEF_RAM_TAP_COEF_ENABLE = 0x00000001, 11172 } WBSCL_COEF_RAM_TAP_COEF_EN_ENUM; 11173 11174 /* 11175 * WBSCL_NUM_OF_TAPS_ENUM enum 11176 */ 11177 11178 typedef enum WBSCL_NUM_OF_TAPS_ENUM { 11179 WBSCL_NUM_OF_TAPS0 = 0x00000000, 11180 WBSCL_NUM_OF_TAPS1 = 0x00000001, 11181 WBSCL_NUM_OF_TAPS2 = 0x00000002, 11182 WBSCL_NUM_OF_TAPS3 = 0x00000003, 11183 WBSCL_NUM_OF_TAPS4 = 0x00000004, 11184 WBSCL_NUM_OF_TAPS5 = 0x00000005, 11185 WBSCL_NUM_OF_TAPS6 = 0x00000006, 11186 WBSCL_NUM_OF_TAPS7 = 0x00000007, 11187 WBSCL_NUM_OF_TAPS8 = 0x00000008, 11188 WBSCL_NUM_OF_TAPS9 = 0x00000009, 11189 WBSCL_NUM_OF_TAPS10 = 0x0000000a, 11190 WBSCL_NUM_OF_TAPS11 = 0x0000000b, 11191 } WBSCL_NUM_OF_TAPS_ENUM; 11192 11193 /* 11194 * WBSCL_STATUS_ACK_ENUM enum 11195 */ 11196 11197 typedef enum WBSCL_STATUS_ACK_ENUM { 11198 WBSCL_STATUS_ACK_NCLR = 0x00000000, 11199 WBSCL_STATUS_ACK_CLR = 0x00000001, 11200 } WBSCL_STATUS_ACK_ENUM; 11201 11202 /* 11203 * WBSCL_STATUS_MASK_ENUM enum 11204 */ 11205 11206 typedef enum WBSCL_STATUS_MASK_ENUM { 11207 WBSCL_STATUS_MASK_DISABLE = 0x00000000, 11208 WBSCL_STATUS_MASK_ENABLE = 0x00000001, 11209 } WBSCL_STATUS_MASK_ENUM; 11210 11211 /* 11212 * WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM enum 11213 */ 11214 11215 typedef enum WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM { 11216 WBSCL_DATA_OVERFLOW_INT_TYPE_REG = 0x00000000, 11217 WBSCL_DATA_OVERFLOW_INT_TYPE_HW = 0x00000001, 11218 } WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM; 11219 11220 /* 11221 * WBSCL_HOST_CONFLICT_INT_TYPE_ENUM enum 11222 */ 11223 11224 typedef enum WBSCL_HOST_CONFLICT_INT_TYPE_ENUM { 11225 WBSCL_HOST_CONFLICT_INT_TYPE_REG = 0x00000000, 11226 WBSCL_HOST_CONFLICT_INT_TYPE_HW = 0x00000001, 11227 } WBSCL_HOST_CONFLICT_INT_TYPE_ENUM; 11228 11229 /* 11230 * WBSCL_TEST_CRC_EN_ENUM enum 11231 */ 11232 11233 typedef enum WBSCL_TEST_CRC_EN_ENUM { 11234 WBSCL_TEST_CRC_DISABLE = 0x00000000, 11235 WBSCL_TEST_CRC_ENABLE = 0x00000001, 11236 } WBSCL_TEST_CRC_EN_ENUM; 11237 11238 /* 11239 * WBSCL_TEST_CRC_CONT_EN_ENUM enum 11240 */ 11241 11242 typedef enum WBSCL_TEST_CRC_CONT_EN_ENUM { 11243 WBSCL_TEST_CRC_CONT_DISABLE = 0x00000000, 11244 WBSCL_TEST_CRC_CONT_ENABLE = 0x00000001, 11245 } WBSCL_TEST_CRC_CONT_EN_ENUM; 11246 11247 /* 11248 * WBSCL_TEST_CRC_MASK_ENUM enum 11249 */ 11250 11251 typedef enum WBSCL_TEST_CRC_MASK_ENUM { 11252 WBSCL_TEST_CRC_MASKED = 0x00000000, 11253 WBSCL_TEST_CRC_UNMASKED = 0x00000001, 11254 } WBSCL_TEST_CRC_MASK_ENUM; 11255 11256 /* 11257 * WBSCL_BACKPRESSURE_CNT_EN_ENUM enum 11258 */ 11259 11260 typedef enum WBSCL_BACKPRESSURE_CNT_EN_ENUM { 11261 WBSCL_BACKPRESSURE_CNT_DISABLE = 0x00000000, 11262 WBSCL_BACKPRESSURE_CNT_ENABLE = 0x00000001, 11263 } WBSCL_BACKPRESSURE_CNT_EN_ENUM; 11264 11265 /* 11266 * WBSCL_OUTSIDE_PIX_STRATEGY_ENUM enum 11267 */ 11268 11269 typedef enum WBSCL_OUTSIDE_PIX_STRATEGY_ENUM { 11270 WBSCL_OUTSIDE_PIX_STRATEGY_BLACK = 0x00000000, 11271 WBSCL_OUTSIDE_PIX_STRATEGY_EDGE = 0x00000001, 11272 } WBSCL_OUTSIDE_PIX_STRATEGY_ENUM; 11273 11274 /******************************************************* 11275 * DPCSRX Enums 11276 *******************************************************/ 11277 11278 /* 11279 * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum 11280 */ 11281 11282 typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL { 11283 DPCSRX_BPHY_PCS_RX0_CLK = 0x00000000, 11284 DPCSRX_BPHY_PCS_RX1_CLK = 0x00000001, 11285 DPCSRX_BPHY_PCS_RX2_CLK = 0x00000002, 11286 DPCSRX_BPHY_PCS_RX3_CLK = 0x00000003, 11287 } DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL; 11288 11289 /******************************************************* 11290 * DPCSTX Enums 11291 *******************************************************/ 11292 11293 /* 11294 * DPCSTX_DVI_LINK_MODE enum 11295 */ 11296 11297 typedef enum DPCSTX_DVI_LINK_MODE { 11298 DPCSTX_DVI_LINK_MODE_NORMAL = 0x00000000, 11299 DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER = 0x00000001, 11300 DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER = 0x00000002, 11301 } DPCSTX_DVI_LINK_MODE; 11302 11303 /******************************************************* 11304 * RDPCSTX Enums 11305 *******************************************************/ 11306 11307 /* 11308 * RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET enum 11309 */ 11310 11311 typedef enum RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET { 11312 RDPCS_CBUS_SOFT_RESET_DISABLE = 0x00000000, 11313 RDPCS_CBUS_SOFT_RESET_ENABLE = 0x00000001, 11314 } RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET; 11315 11316 /* 11317 * RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET enum 11318 */ 11319 11320 typedef enum RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET { 11321 RDPCS_SRAM_SRAM_RESET_DISABLE = 0x00000000, 11322 } RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET; 11323 11324 /* 11325 * RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN enum 11326 */ 11327 11328 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN { 11329 RDPCS_TX_FIFO_LANE_DISABLE = 0x00000000, 11330 RDPCS_TX_FIFO_LANE_ENABLE = 0x00000001, 11331 } RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN; 11332 11333 /* 11334 * RDPCSTX_CNTL_RDPCS_TX_FIFO_EN enum 11335 */ 11336 11337 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_EN { 11338 RDPCS_TX_FIFO_DISABLE = 0x00000000, 11339 RDPCS_TX_FIFO_ENABLE = 0x00000001, 11340 } RDPCSTX_CNTL_RDPCS_TX_FIFO_EN; 11341 11342 /* 11343 * RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET enum 11344 */ 11345 11346 typedef enum RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET { 11347 RDPCS_TX_SOFT_RESET_DISABLE = 0x00000000, 11348 RDPCS_TX_SOFT_RESET_ENABLE = 0x00000001, 11349 } RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET; 11350 11351 /* 11352 * RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN enum 11353 */ 11354 11355 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN { 11356 RDPCS_EXT_REFCLK_DISABLE = 0x00000000, 11357 RDPCS_EXT_REFCLK_ENABLE = 0x00000001, 11358 } RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN; 11359 11360 /* 11361 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN enum 11362 */ 11363 11364 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN { 11365 RDPCS_EXT_REFCLK_EN_DISABLE = 0x00000000, 11366 RDPCS_EXT_REFCLK_EN_ENABLE = 0x00000001, 11367 } RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN; 11368 11369 /* 11370 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS enum 11371 */ 11372 11373 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS { 11374 RDPCS_SYMCLK_DIV2_GATE_ENABLE = 0x00000000, 11375 RDPCS_SYMCLK_DIV2_GATE_DISABLE = 0x00000001, 11376 } RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS; 11377 11378 /* 11379 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN enum 11380 */ 11381 11382 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN { 11383 RDPCS_SYMCLK_DIV2_DISABLE = 0x00000000, 11384 RDPCS_SYMCLK_DIV2_ENABLE = 0x00000001, 11385 } RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN; 11386 11387 /* 11388 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON enum 11389 */ 11390 11391 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON { 11392 RDPCS_SYMCLK_DIV2_CLOCK_OFF = 0x00000000, 11393 RDPCS_SYMCLK_DIV2_CLOCK_ON = 0x00000001, 11394 } RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON; 11395 11396 /* 11397 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum 11398 */ 11399 11400 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS { 11401 RDPCS_SRAMCLK_GATE_ENABLE = 0x00000000, 11402 RDPCS_SRAMCLK_GATE_DISABLE = 0x00000001, 11403 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS; 11404 11405 /* 11406 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum 11407 */ 11408 11409 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN { 11410 RDPCS_SRAMCLK_DISABLE = 0x00000000, 11411 RDPCS_SRAMCLK_ENABLE = 0x00000001, 11412 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN; 11413 11414 /* 11415 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS enum 11416 */ 11417 11418 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS { 11419 RDPCS_SRAMCLK_NOT_BYPASS = 0x00000000, 11420 RDPCS_SRAMCLK_BYPASS = 0x00000001, 11421 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS; 11422 11423 /* 11424 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum 11425 */ 11426 11427 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON { 11428 RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0x00000000, 11429 RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 0x00000001, 11430 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON; 11431 11432 /* 11433 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum 11434 */ 11435 11436 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE { 11437 RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0x00000000, 11438 RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 0x00000001, 11439 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE; 11440 11441 /* 11442 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum 11443 */ 11444 11445 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE { 11446 RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0x00000000, 11447 RDPCS_DPALT_4LANE_TOGGLE_4LANE = 0x00000001, 11448 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE; 11449 11450 /* 11451 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum 11452 */ 11453 11454 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK { 11455 RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0x00000000, 11456 RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 0x00000001, 11457 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK; 11458 11459 /* 11460 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum 11461 */ 11462 11463 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK { 11464 RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0x00000000, 11465 RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 0x00000001, 11466 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK; 11467 11468 /* 11469 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum 11470 */ 11471 11472 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK { 11473 RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0x00000000, 11474 RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 0x00000001, 11475 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK; 11476 11477 /* 11478 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK enum 11479 */ 11480 11481 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK { 11482 RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0x00000000, 11483 RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 0x00000001, 11484 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK; 11485 11486 /* 11487 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum 11488 */ 11489 11490 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE { 11491 RDPCS_MEM_PWR_NO_FORCE = 0x00000000, 11492 RDPCS_MEM_PWR_LIGHT_SLEEP = 0x00000001, 11493 RDPCS_MEM_PWR_DEEP_SLEEP = 0x00000002, 11494 RDPCS_MEM_PWR_SHUT_DOWN = 0x00000003, 11495 } RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE; 11496 11497 /* 11498 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum 11499 */ 11500 11501 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE { 11502 RDPCS_MEM_PWR_PWR_STATE_ON = 0x00000000, 11503 RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 0x00000001, 11504 RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 0x00000002, 11505 RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 0x00000003, 11506 } RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE; 11507 11508 /* 11509 * RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF enum 11510 */ 11511 11512 typedef enum RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF { 11513 RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY = 0x00000000, 11514 RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD = 0x00000001, 11515 RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3 = 0x00000002, 11516 RDPCS_MEM_POWER_CTRL_POFF_FOR_SD = 0x00000003, 11517 } RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF; 11518 11519 /* 11520 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum 11521 */ 11522 11523 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE { 11524 RDPCS_PHY_REF_RANGE_0 = 0x00000000, 11525 RDPCS_PHY_REF_RANGE_1 = 0x00000001, 11526 RDPCS_PHY_REF_RANGE_2 = 0x00000002, 11527 RDPCS_PHY_REF_RANGE_3 = 0x00000003, 11528 RDPCS_PHY_REF_RANGE_4 = 0x00000004, 11529 RDPCS_PHY_REF_RANGE_5 = 0x00000005, 11530 RDPCS_PHY_REF_RANGE_6 = 0x00000006, 11531 RDPCS_PHY_REF_RANGE_7 = 0x00000007, 11532 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE; 11533 11534 /* 11535 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum 11536 */ 11537 11538 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL { 11539 RDPCS_PHY_CR_PARA_SEL_JTAG = 0x00000000, 11540 RDPCS_PHY_CR_PARA_SEL_CR = 0x00000001, 11541 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL; 11542 11543 /* 11544 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum 11545 */ 11546 11547 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL { 11548 RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0x00000000, 11549 RDPCS_PHY_CR_MUX_SEL_FOR_DC = 0x00000001, 11550 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL; 11551 11552 /* 11553 * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum 11554 */ 11555 11556 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE { 11557 RDPCS_SRAM_INIT_NOT_DONE = 0x00000000, 11558 RDPCS_SRAM_INIT_DONE = 0x00000001, 11559 } RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE; 11560 11561 /* 11562 * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum 11563 */ 11564 11565 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE { 11566 RDPCS_SRAM_EXT_LD_NOT_DONE = 0x00000000, 11567 RDPCS_SRAM_EXT_LD_DONE = 0x00000001, 11568 } RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE; 11569 11570 /* 11571 * RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum 11572 */ 11573 11574 typedef enum RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL { 11575 RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0x00000000, 11576 RDPCS_PHY_DP_TX_TERM_CTRL_52 = 0x00000001, 11577 RDPCS_PHY_DP_TX_TERM_CTRL_50 = 0x00000002, 11578 RDPCS_PHY_DP_TX_TERM_CTRL_48 = 0x00000003, 11579 RDPCS_PHY_DP_TX_TERM_CTRL_46 = 0x00000004, 11580 RDPCS_PHY_DP_TX_TERM_CTRL_44 = 0x00000005, 11581 RDPCS_PHY_DP_TX_TERM_CTRL_42 = 0x00000006, 11582 RDPCS_PHY_DP_TX_TERM_CTRL_40 = 0x00000007, 11583 } RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL; 11584 11585 /* 11586 * RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum 11587 */ 11588 11589 typedef enum RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE { 11590 RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0x00000000, 11591 RRDPCS_PHY_DP_TX_PSTATE_HOLD = 0x00000001, 11592 RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 0x00000002, 11593 RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 0x00000003, 11594 } RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE; 11595 11596 /* 11597 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum 11598 */ 11599 11600 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE { 11601 RDPCS_PHY_DP_TX_RATE = 0x00000000, 11602 RDPCS_PHY_DP_TX_RATE_DIV2 = 0x00000001, 11603 RDPCS_PHY_DP_TX_RATE_DIV4 = 0x00000002, 11604 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE; 11605 11606 /* 11607 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum 11608 */ 11609 11610 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH { 11611 RDPCS_PHY_DP_TX_WIDTH_8 = 0x00000000, 11612 RDPCS_PHY_DP_TX_WIDTH_10 = 0x00000001, 11613 RDPCS_PHY_DP_TX_WIDTH_16 = 0x00000002, 11614 RDPCS_PHY_DP_TX_WIDTH_20 = 0x00000003, 11615 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH; 11616 11617 /* 11618 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum 11619 */ 11620 11621 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT { 11622 RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0x00000000, 11623 RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 0x00000001, 11624 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT; 11625 11626 /* 11627 * RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum 11628 */ 11629 11630 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV { 11631 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0x00000000, 11632 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 0x00000001, 11633 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 0x00000002, 11634 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 0x00000003, 11635 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 0x00000004, 11636 } RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV; 11637 11638 /* 11639 * RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum 11640 */ 11641 11642 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV { 11643 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0x00000000, 11644 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 0x00000001, 11645 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 0x00000002, 11646 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 0x00000003, 11647 } RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV; 11648 11649 /* 11650 * RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum 11651 */ 11652 11653 typedef enum RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV { 11654 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000000, 11655 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 0x00000001, 11656 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 0x00000002, 11657 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 0x00000003, 11658 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 0x00000004, 11659 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 0x00000005, 11660 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 0x00000006, 11661 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 0x00000007, 11662 } RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV; 11663 11664 /* 11665 * RDPCS_TEST_CLK_SEL enum 11666 */ 11667 11668 typedef enum RDPCS_TEST_CLK_SEL { 11669 RDPCS_TEST_CLK_SEL_NONE = 0x00000000, 11670 RDPCS_TEST_CLK_SEL_CFGCLK = 0x00000001, 11671 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 0x00000002, 11672 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 0x00000003, 11673 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 0x00000004, 11674 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 0x00000005, 11675 RDPCS_TEST_CLK_SEL_SRAMCLK = 0x00000006, 11676 RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 0x00000007, 11677 RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 0x00000008, 11678 RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 0x00000009, 11679 RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 0x0000000a, 11680 RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 0x0000000b, 11681 RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 0x0000000c, 11682 RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 0x0000000d, 11683 RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 0x0000000e, 11684 RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 0x0000000f, 11685 RDPCS_TEST_CLK_SEL_dtb_out0 = 0x00000010, 11686 RDPCS_TEST_CLK_SEL_dtb_out1 = 0x00000011, 11687 } RDPCS_TEST_CLK_SEL; 11688 11689 /******************************************************* 11690 * CB Enums 11691 *******************************************************/ 11692 11693 /* 11694 * CBMode enum 11695 */ 11696 11697 typedef enum CBMode { 11698 CB_DISABLE = 0x00000000, 11699 CB_NORMAL = 0x00000001, 11700 CB_ELIMINATE_FAST_CLEAR = 0x00000002, 11701 CB_RESOLVE = 0x00000003, 11702 CB_DECOMPRESS = 0x00000004, 11703 CB_FMASK_DECOMPRESS = 0x00000005, 11704 CB_DCC_DECOMPRESS = 0x00000006, 11705 CB_RESERVED = 0x00000007, 11706 } CBMode; 11707 11708 /* 11709 * BlendOp enum 11710 */ 11711 11712 typedef enum BlendOp { 11713 BLEND_ZERO = 0x00000000, 11714 BLEND_ONE = 0x00000001, 11715 BLEND_SRC_COLOR = 0x00000002, 11716 BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, 11717 BLEND_SRC_ALPHA = 0x00000004, 11718 BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, 11719 BLEND_DST_ALPHA = 0x00000006, 11720 BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, 11721 BLEND_DST_COLOR = 0x00000008, 11722 BLEND_ONE_MINUS_DST_COLOR = 0x00000009, 11723 BLEND_SRC_ALPHA_SATURATE = 0x0000000a, 11724 BLEND_BOTH_SRC_ALPHA = 0x0000000b, 11725 BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c, 11726 BLEND_CONSTANT_COLOR = 0x0000000d, 11727 BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e, 11728 BLEND_SRC1_COLOR = 0x0000000f, 11729 BLEND_INV_SRC1_COLOR = 0x00000010, 11730 BLEND_SRC1_ALPHA = 0x00000011, 11731 BLEND_INV_SRC1_ALPHA = 0x00000012, 11732 BLEND_CONSTANT_ALPHA = 0x00000013, 11733 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014, 11734 } BlendOp; 11735 11736 /* 11737 * CombFunc enum 11738 */ 11739 11740 typedef enum CombFunc { 11741 COMB_DST_PLUS_SRC = 0x00000000, 11742 COMB_SRC_MINUS_DST = 0x00000001, 11743 COMB_MIN_DST_SRC = 0x00000002, 11744 COMB_MAX_DST_SRC = 0x00000003, 11745 COMB_DST_MINUS_SRC = 0x00000004, 11746 } CombFunc; 11747 11748 /* 11749 * BlendOpt enum 11750 */ 11751 11752 typedef enum BlendOpt { 11753 FORCE_OPT_AUTO = 0x00000000, 11754 FORCE_OPT_DISABLE = 0x00000001, 11755 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, 11756 FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, 11757 FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, 11758 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, 11759 FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, 11760 FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, 11761 } BlendOpt; 11762 11763 /* 11764 * CmaskCode enum 11765 */ 11766 11767 typedef enum CmaskCode { 11768 CMASK_CLR00_F0 = 0x00000000, 11769 CMASK_CLR00_F1 = 0x00000001, 11770 CMASK_CLR00_F2 = 0x00000002, 11771 CMASK_CLR00_FX = 0x00000003, 11772 CMASK_CLR01_F0 = 0x00000004, 11773 CMASK_CLR01_F1 = 0x00000005, 11774 CMASK_CLR01_F2 = 0x00000006, 11775 CMASK_CLR01_FX = 0x00000007, 11776 CMASK_CLR10_F0 = 0x00000008, 11777 CMASK_CLR10_F1 = 0x00000009, 11778 CMASK_CLR10_F2 = 0x0000000a, 11779 CMASK_CLR10_FX = 0x0000000b, 11780 CMASK_CLR11_F0 = 0x0000000c, 11781 CMASK_CLR11_F1 = 0x0000000d, 11782 CMASK_CLR11_F2 = 0x0000000e, 11783 CMASK_CLR11_FX = 0x0000000f, 11784 } CmaskCode; 11785 11786 /* 11787 * MemArbMode enum 11788 */ 11789 11790 typedef enum MemArbMode { 11791 MEM_ARB_MODE_FIXED = 0x00000000, 11792 MEM_ARB_MODE_AGE = 0x00000001, 11793 MEM_ARB_MODE_WEIGHT = 0x00000002, 11794 MEM_ARB_MODE_BOTH = 0x00000003, 11795 } MemArbMode; 11796 11797 /* 11798 * CBPerfOpFilterSel enum 11799 */ 11800 11801 typedef enum CBPerfOpFilterSel { 11802 CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, 11803 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, 11804 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, 11805 CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, 11806 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, 11807 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, 11808 } CBPerfOpFilterSel; 11809 11810 /* 11811 * CBPerfClearFilterSel enum 11812 */ 11813 11814 typedef enum CBPerfClearFilterSel { 11815 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, 11816 CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, 11817 } CBPerfClearFilterSel; 11818 11819 /* 11820 * CBPerfSel enum 11821 */ 11822 11823 typedef enum CBPerfSel { 11824 CB_PERF_SEL_NONE = 0x00000000, 11825 CB_PERF_SEL_BUSY = 0x00000001, 11826 CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002, 11827 CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003, 11828 CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004, 11829 CB_PERF_SEL_DRAWN_QUAD = 0x00000005, 11830 CB_PERF_SEL_DRAWN_PIXEL = 0x00000006, 11831 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007, 11832 CB_PERF_SEL_DRAWN_TILE = 0x00000008, 11833 CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009, 11834 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a, 11835 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b, 11836 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c, 11837 CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d, 11838 CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e, 11839 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f, 11840 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010, 11841 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011, 11842 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012, 11843 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013, 11844 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014, 11845 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015, 11846 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016, 11847 CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017, 11848 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018, 11849 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019, 11850 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a, 11851 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b, 11852 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c, 11853 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d, 11854 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e, 11855 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f, 11856 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020, 11857 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021, 11858 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022, 11859 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023, 11860 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024, 11861 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025, 11862 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026, 11863 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027, 11864 CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028, 11865 CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029, 11866 CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a, 11867 CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b, 11868 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c, 11869 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d, 11870 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e, 11871 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f, 11872 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030, 11873 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031, 11874 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032, 11875 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033, 11876 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034, 11877 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035, 11878 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036, 11879 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037, 11880 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038, 11881 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039, 11882 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a, 11883 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b, 11884 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c, 11885 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d, 11886 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e, 11887 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f, 11888 CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040, 11889 CB_PERF_SEL_CM_CACHE_HIT = 0x00000041, 11890 CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042, 11891 CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043, 11892 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044, 11893 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045, 11894 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046, 11895 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047, 11896 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048, 11897 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049, 11898 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a, 11899 CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b, 11900 CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c, 11901 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d, 11902 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e, 11903 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f, 11904 CB_PERF_SEL_FC_CACHE_HIT = 0x00000050, 11905 CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051, 11906 CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052, 11907 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053, 11908 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054, 11909 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055, 11910 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056, 11911 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057, 11912 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058, 11913 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059, 11914 CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a, 11915 CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b, 11916 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c, 11917 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d, 11918 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e, 11919 CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f, 11920 CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060, 11921 CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061, 11922 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062, 11923 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063, 11924 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064, 11925 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065, 11926 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066, 11927 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067, 11928 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068, 11929 CB_PERF_SEL_CC_CACHE_STALL = 0x00000069, 11930 CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a, 11931 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b, 11932 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c, 11933 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d, 11934 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e, 11935 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x0000006f, 11936 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x00000070, 11937 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x00000071, 11938 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x00000072, 11939 CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x00000073, 11940 CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x00000074, 11941 CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x00000075, 11942 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000076, 11943 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000077, 11944 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000078, 11945 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x00000079, 11946 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x0000007a, 11947 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x0000007b, 11948 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x0000007c, 11949 CB_PERF_SEL_CM_MC_READ_REQUEST = 0x0000007d, 11950 CB_PERF_SEL_FC_MC_READ_REQUEST = 0x0000007e, 11951 CB_PERF_SEL_CC_MC_READ_REQUEST = 0x0000007f, 11952 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x00000080, 11953 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000081, 11954 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000082, 11955 CB_PERF_SEL_CM_TQ_FULL = 0x00000083, 11956 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x00000084, 11957 CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL = 0x00000085, 11958 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x00000086, 11959 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x00000087, 11960 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088, 11961 CB_PERF_SEL_FC_TILE_STUTTER_STALL = 0x00000089, 11962 CB_PERF_SEL_FC_QUAD_STUTTER_STALL = 0x0000008a, 11963 CB_PERF_SEL_FC_KEYID_STUTTER_STALL = 0x0000008b, 11964 CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x0000008c, 11965 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x0000008d, 11966 CB_PERF_SEL_CC_SF_FULL = 0x0000008e, 11967 CB_PERF_SEL_CC_RB_FULL = 0x0000008f, 11968 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x00000090, 11969 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x00000091, 11970 CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL = 0x00000092, 11971 CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL = 0x00000093, 11972 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x00000094, 11973 CB_PERF_SEL_EVENT = 0x00000095, 11974 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000096, 11975 CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000097, 11976 CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000098, 11977 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000099, 11978 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x0000009a, 11979 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x0000009b, 11980 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x0000009c, 11981 CB_PERF_SEL_CC_SURFACE_SYNC = 0x0000009d, 11982 CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x0000009e, 11983 CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x0000009f, 11984 CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x000000a0, 11985 CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x000000a1, 11986 CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x000000a2, 11987 CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x000000a3, 11988 CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x000000a4, 11989 CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x000000a5, 11990 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0x000000a6, 11991 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x000000a7, 11992 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x000000a8, 11993 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x000000a9, 11994 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x000000aa, 11995 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x000000ab, 11996 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x000000ac, 11997 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x000000ad, 11998 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x000000ae, 11999 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x000000af, 12000 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x000000b0, 12001 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0x000000b1, 12002 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x000000b2, 12003 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x000000b3, 12004 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x000000b4, 12005 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x000000b5, 12006 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x000000b6, 12007 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x000000b7, 12008 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x000000b8, 12009 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0x000000b9, 12010 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0x000000ba, 12011 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0x000000bb, 12012 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0x000000bc, 12013 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0x000000bd, 12014 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0x000000be, 12015 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0x000000bf, 12016 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0x000000c0, 12017 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0x000000c1, 12018 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0x000000c2, 12019 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0x000000c3, 12020 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0x000000c4, 12021 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0x000000c5, 12022 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0x000000c6, 12023 CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0x000000c7, 12024 CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0x000000c8, 12025 CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0x000000c9, 12026 CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0x000000ca, 12027 CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0x000000cb, 12028 CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0x000000cc, 12029 CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0x000000cd, 12030 CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0x000000ce, 12031 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0x000000cf, 12032 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0x000000d0, 12033 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0x000000d1, 12034 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0x000000d2, 12035 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0x000000d3, 12036 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0x000000d4, 12037 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0x000000d5, 12038 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0x000000d6, 12039 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0x000000d7, 12040 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0x000000d8, 12041 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0x000000d9, 12042 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000da, 12043 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000db, 12044 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000dc, 12045 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000dd, 12046 CB_PERF_SEL_DRAWN_BUSY = 0x000000de, 12047 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0x000000df, 12048 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0x000000e0, 12049 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0x000000e1, 12050 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0x000000e2, 12051 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 0x000000e3, 12052 CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0x000000e4, 12053 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0x000000e5, 12054 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0x000000e6, 12055 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 0x000000e7, 12056 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x000000e8, 12057 CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0x000000e9, 12058 CB_PERF_SEL_FC_DOC_IS_STALLED = 0x000000ea, 12059 CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0x000000eb, 12060 CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0x000000ec, 12061 CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0x000000ed, 12062 CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0x000000ee, 12063 CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0x000000ef, 12064 CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0x000000f0, 12065 CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0x000000f1, 12066 CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0x000000f2, 12067 CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0x000000f3, 12068 CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0x000000f4, 12069 CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0x000000f5, 12070 CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0x000000f6, 12071 CB_PERF_SEL_FC_DCC_CACHE_HIT = 0x000000f7, 12072 CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0x000000f8, 12073 CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0x000000f9, 12074 CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0x000000fa, 12075 CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x000000fb, 12076 CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x000000fc, 12077 CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x000000fd, 12078 CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0x000000fe, 12079 CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0x000000ff, 12080 CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0x00000100, 12081 CB_PERF_SEL_FC_DCC_CACHE_STALL = 0x00000101, 12082 CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0x00000102, 12083 CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0x00000103, 12084 CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0x00000104, 12085 CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x00000105, 12086 CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x00000106, 12087 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x00000107, 12088 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x00000108, 12089 CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x00000109, 12090 CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x0000010a, 12091 CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x0000010b, 12092 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x0000010c, 12093 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x0000010d, 12094 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x0000010e, 12095 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x0000010f, 12096 CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x00000110, 12097 CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x00000111, 12098 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 0x00000112, 12099 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000113, 12100 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 0x00000114, 12101 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 0x00000115, 12102 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 0x00000116, 12103 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000117, 12104 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000118, 12105 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000119, 12106 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 0x0000011a, 12107 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 0x0000011b, 12108 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 0x0000011c, 12109 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 0x0000011d, 12110 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000011e, 12111 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 0x0000011f, 12112 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x00000120, 12113 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 0x00000121, 12114 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 0x00000122, 12115 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 0x00000123, 12116 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 0x00000124, 12117 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x00000125, 12118 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 0x00000126, 12119 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 0x00000127, 12120 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 0x00000128, 12121 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 0x00000129, 12122 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x0000012a, 12123 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 0x0000012b, 12124 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 0x0000012c, 12125 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 0x0000012d, 12126 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 0x0000012e, 12127 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 0x0000012f, 12128 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 0x00000130, 12129 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 0x00000131, 12130 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 0x00000132, 12131 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 0x00000133, 12132 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 0x00000134, 12133 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 0x00000135, 12134 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 0x00000136, 12135 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 0x00000137, 12136 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 0x00000138, 12137 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 0x00000139, 12138 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 0x0000013a, 12139 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 0x0000013b, 12140 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 0x0000013c, 12141 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 0x0000013d, 12142 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 0x0000013e, 12143 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 0x0000013f, 12144 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 0x00000140, 12145 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 0x00000141, 12146 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 0x00000142, 12147 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 0x00000143, 12148 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 0x00000144, 12149 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 0x00000145, 12150 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000146, 12151 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000147, 12152 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000148, 12153 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 0x00000149, 12154 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 0x0000014a, 12155 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 0x0000014b, 12156 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 0x0000014c, 12157 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 0x0000014d, 12158 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 0x0000014e, 12159 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 0x0000014f, 12160 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 0x00000150, 12161 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 0x00000151, 12162 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 0x00000152, 12163 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 0x00000153, 12164 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000154, 12165 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000155, 12166 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000156, 12167 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000157, 12168 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000158, 12169 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000159, 12170 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000015a, 12171 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000015b, 12172 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 0x0000015c, 12173 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 0x0000015d, 12174 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 0x0000015e, 12175 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 0x0000015f, 12176 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 0x00000160, 12177 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 0x00000161, 12178 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x00000162, 12179 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x00000163, 12180 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 0x00000164, 12181 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 0x00000165, 12182 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 0x00000166, 12183 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 0x00000167, 12184 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 0x00000168, 12185 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x00000169, 12186 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x0000016a, 12187 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 0x0000016b, 12188 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 0x0000016c, 12189 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 0x0000016d, 12190 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 0x0000016e, 12191 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 0x0000016f, 12192 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 0x00000170, 12193 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x00000171, 12194 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x00000172, 12195 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 0x00000173, 12196 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 0x00000174, 12197 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 0x00000175, 12198 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 0x00000176, 12199 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 0x00000177, 12200 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x00000178, 12201 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x00000179, 12202 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x0000017a, 12203 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x0000017b, 12204 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x0000017c, 12205 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x0000017d, 12206 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x0000017e, 12207 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x0000017f, 12208 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x00000180, 12209 CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x00000181, 12210 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x00000182, 12211 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x00000183, 12212 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x00000184, 12213 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x00000185, 12214 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x00000186, 12215 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x00000187, 12216 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x00000188, 12217 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x00000189, 12218 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x0000018a, 12219 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x0000018b, 12220 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x0000018c, 12221 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x0000018d, 12222 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x0000018e, 12223 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x0000018f, 12224 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x00000190, 12225 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x00000191, 12226 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x00000192, 12227 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x00000193, 12228 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x00000194, 12229 CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x00000195, 12230 CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x00000196, 12231 CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x00000197, 12232 CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x00000198, 12233 CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x00000199, 12234 CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x0000019a, 12235 CB_PERF_SEL_NACK_CM_READ = 0x0000019b, 12236 CB_PERF_SEL_NACK_CM_WRITE = 0x0000019c, 12237 CB_PERF_SEL_NACK_FC_READ = 0x0000019d, 12238 CB_PERF_SEL_NACK_FC_WRITE = 0x0000019e, 12239 CB_PERF_SEL_NACK_DC_READ = 0x0000019f, 12240 CB_PERF_SEL_NACK_DC_WRITE = 0x000001a0, 12241 CB_PERF_SEL_NACK_CC_READ = 0x000001a1, 12242 CB_PERF_SEL_NACK_CC_WRITE = 0x000001a2, 12243 CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN = 0x000001a3, 12244 CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN = 0x000001a4, 12245 CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN = 0x000001a5, 12246 CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN = 0x000001a6, 12247 CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a7, 12248 CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a8, 12249 CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a9, 12250 CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001aa, 12251 CB_PERF_SEL_CM_MC_WRITE_ACK64B = 0x000001ab, 12252 CB_PERF_SEL_FC_MC_WRITE_ACK64B = 0x000001ac, 12253 CB_PERF_SEL_DC_MC_WRITE_ACK64B = 0x000001ad, 12254 CB_PERF_SEL_CC_MC_WRITE_ACK64B = 0x000001ae, 12255 CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 0x000001af, 12256 CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS = 0x000001b0, 12257 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA = 0x000001b1, 12258 CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT = 0x000001b2, 12259 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX = 0x000001b3, 12260 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX = 0x000001b4, 12261 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX = 0x000001b5, 12262 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX = 0x000001b6, 12263 CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED = 0x000001b7, 12264 CB_PERF_SEL_DB_CB_CONTEXT_DONE = 0x000001b8, 12265 CB_PERF_SEL_DB_CB_EOP_DONE = 0x000001b9, 12266 CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL = 0x000001ba, 12267 CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD = 0x000001bb, 12268 } CBPerfSel; 12269 12270 /* 12271 * CmaskAddr enum 12272 */ 12273 12274 typedef enum CmaskAddr { 12275 CMASK_ADDR_TILED = 0x00000000, 12276 CMASK_ADDR_LINEAR = 0x00000001, 12277 CMASK_ADDR_COMPATIBLE = 0x00000002, 12278 } CmaskAddr; 12279 12280 /* 12281 * SourceFormat enum 12282 */ 12283 12284 typedef enum SourceFormat { 12285 EXPORT_4C_32BPC = 0x00000000, 12286 EXPORT_4C_16BPC = 0x00000001, 12287 EXPORT_2C_32BPC_GR = 0x00000002, 12288 EXPORT_2C_32BPC_AR = 0x00000003, 12289 } SourceFormat; 12290 12291 /******************************************************* 12292 * TC Enums 12293 *******************************************************/ 12294 12295 /* 12296 * TC_OP_MASKS enum 12297 */ 12298 12299 typedef enum TC_OP_MASKS { 12300 TC_OP_MASK_FLUSH_DENROM = 0x00000008, 12301 TC_OP_MASK_64 = 0x00000020, 12302 TC_OP_MASK_NO_RTN = 0x00000040, 12303 } TC_OP_MASKS; 12304 12305 /* 12306 * TC_OP enum 12307 */ 12308 12309 typedef enum TC_OP { 12310 TC_OP_READ = 0x00000000, 12311 TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, 12312 TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, 12313 TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, 12314 TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, 12315 TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005, 12316 TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, 12317 TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, 12318 TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, 12319 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, 12320 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, 12321 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, 12322 TC_OP_PROBE_FILTER = 0x0000000c, 12323 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d, 12324 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, 12325 TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, 12326 TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, 12327 TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, 12328 TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, 12329 TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, 12330 TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, 12331 TC_OP_ATOMIC_AND_RTN_32 = 0x00000015, 12332 TC_OP_ATOMIC_OR_RTN_32 = 0x00000016, 12333 TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017, 12334 TC_OP_ATOMIC_INC_RTN_32 = 0x00000018, 12335 TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019, 12336 TC_OP_WBINVL1_VOL = 0x0000001a, 12337 TC_OP_WBINVL1_SD = 0x0000001b, 12338 TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c, 12339 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d, 12340 TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e, 12341 TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f, 12342 TC_OP_WRITE = 0x00000020, 12343 TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, 12344 TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, 12345 TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, 12346 TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, 12347 TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, 12348 TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, 12349 TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, 12350 TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, 12351 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, 12352 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, 12353 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, 12354 TC_OP_WBINVL2_SD = 0x0000002c, 12355 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d, 12356 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e, 12357 TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, 12358 TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, 12359 TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, 12360 TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, 12361 TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, 12362 TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, 12363 TC_OP_ATOMIC_AND_RTN_64 = 0x00000035, 12364 TC_OP_ATOMIC_OR_RTN_64 = 0x00000036, 12365 TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037, 12366 TC_OP_ATOMIC_INC_RTN_64 = 0x00000038, 12367 TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039, 12368 TC_OP_WBL2_NC = 0x0000003a, 12369 TC_OP_WBL2_WC = 0x0000003b, 12370 TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, 12371 TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, 12372 TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, 12373 TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, 12374 TC_OP_WBINVL1 = 0x00000040, 12375 TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, 12376 TC_OP_ATOMIC_FMIN_32 = 0x00000042, 12377 TC_OP_ATOMIC_FMAX_32 = 0x00000043, 12378 TC_OP_RESERVED_FOP_32_0 = 0x00000044, 12379 TC_OP_RESERVED_FOP_32_1 = 0x00000045, 12380 TC_OP_RESERVED_FOP_32_2 = 0x00000046, 12381 TC_OP_ATOMIC_SWAP_32 = 0x00000047, 12382 TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, 12383 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, 12384 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, 12385 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, 12386 TC_OP_INV_METADATA = 0x0000004c, 12387 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d, 12388 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, 12389 TC_OP_ATOMIC_ADD_32 = 0x0000004f, 12390 TC_OP_ATOMIC_SUB_32 = 0x00000050, 12391 TC_OP_ATOMIC_SMIN_32 = 0x00000051, 12392 TC_OP_ATOMIC_UMIN_32 = 0x00000052, 12393 TC_OP_ATOMIC_SMAX_32 = 0x00000053, 12394 TC_OP_ATOMIC_UMAX_32 = 0x00000054, 12395 TC_OP_ATOMIC_AND_32 = 0x00000055, 12396 TC_OP_ATOMIC_OR_32 = 0x00000056, 12397 TC_OP_ATOMIC_XOR_32 = 0x00000057, 12398 TC_OP_ATOMIC_INC_32 = 0x00000058, 12399 TC_OP_ATOMIC_DEC_32 = 0x00000059, 12400 TC_OP_INVL2_NC = 0x0000005a, 12401 TC_OP_NOP_RTN0 = 0x0000005b, 12402 TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, 12403 TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, 12404 TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, 12405 TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, 12406 TC_OP_WBINVL2 = 0x00000060, 12407 TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, 12408 TC_OP_ATOMIC_FMIN_64 = 0x00000062, 12409 TC_OP_ATOMIC_FMAX_64 = 0x00000063, 12410 TC_OP_RESERVED_FOP_64_0 = 0x00000064, 12411 TC_OP_RESERVED_FOP_64_1 = 0x00000065, 12412 TC_OP_RESERVED_FOP_64_2 = 0x00000066, 12413 TC_OP_ATOMIC_SWAP_64 = 0x00000067, 12414 TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, 12415 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, 12416 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, 12417 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, 12418 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, 12419 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, 12420 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, 12421 TC_OP_ATOMIC_ADD_64 = 0x0000006f, 12422 TC_OP_ATOMIC_SUB_64 = 0x00000070, 12423 TC_OP_ATOMIC_SMIN_64 = 0x00000071, 12424 TC_OP_ATOMIC_UMIN_64 = 0x00000072, 12425 TC_OP_ATOMIC_SMAX_64 = 0x00000073, 12426 TC_OP_ATOMIC_UMAX_64 = 0x00000074, 12427 TC_OP_ATOMIC_AND_64 = 0x00000075, 12428 TC_OP_ATOMIC_OR_64 = 0x00000076, 12429 TC_OP_ATOMIC_XOR_64 = 0x00000077, 12430 TC_OP_ATOMIC_INC_64 = 0x00000078, 12431 TC_OP_ATOMIC_DEC_64 = 0x00000079, 12432 TC_OP_WBINVL2_NC = 0x0000007a, 12433 TC_OP_NOP_ACK = 0x0000007b, 12434 TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, 12435 TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, 12436 TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, 12437 TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, 12438 } TC_OP; 12439 12440 /* 12441 * TC_NACKS enum 12442 */ 12443 12444 typedef enum TC_NACKS { 12445 TC_NACK_NO_FAULT = 0x00000000, 12446 TC_NACK_PAGE_FAULT = 0x00000001, 12447 TC_NACK_PROTECTION_FAULT = 0x00000002, 12448 TC_NACK_DATA_ERROR = 0x00000003, 12449 } TC_NACKS; 12450 12451 /* 12452 * TC_EA_CID enum 12453 */ 12454 12455 typedef enum TC_EA_CID { 12456 TC_EA_CID_RT = 0x00000000, 12457 TC_EA_CID_FMASK = 0x00000001, 12458 TC_EA_CID_DCC = 0x00000002, 12459 TC_EA_CID_TCPMETA = 0x00000003, 12460 TC_EA_CID_Z = 0x00000004, 12461 TC_EA_CID_STENCIL = 0x00000005, 12462 TC_EA_CID_HTILE = 0x00000006, 12463 TC_EA_CID_MISC = 0x00000007, 12464 TC_EA_CID_TCP = 0x00000008, 12465 TC_EA_CID_SQC = 0x00000009, 12466 TC_EA_CID_CPF = 0x0000000a, 12467 TC_EA_CID_CPG = 0x0000000b, 12468 TC_EA_CID_IA = 0x0000000c, 12469 TC_EA_CID_WD = 0x0000000d, 12470 TC_EA_CID_PA = 0x0000000e, 12471 TC_EA_CID_UTCL2_TPI = 0x0000000f, 12472 } TC_EA_CID; 12473 12474 /******************************************************* 12475 * GL2 Enums 12476 *******************************************************/ 12477 12478 /* 12479 * GL2_OP_MASKS enum 12480 */ 12481 12482 typedef enum GL2_OP_MASKS { 12483 GL2_OP_MASK_FLUSH_DENROM = 0x00000008, 12484 GL2_OP_MASK_64 = 0x00000020, 12485 GL2_OP_MASK_NO_RTN = 0x00000040, 12486 } GL2_OP_MASKS; 12487 12488 /* 12489 * GL2_OP enum 12490 */ 12491 12492 typedef enum GL2_OP { 12493 GL2_OP_READ = 0x00000000, 12494 GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, 12495 GL2_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, 12496 GL2_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, 12497 GL2_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, 12498 GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, 12499 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, 12500 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, 12501 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, 12502 GL2_OP_PROBE_FILTER = 0x0000000c, 12503 GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d, 12504 GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, 12505 GL2_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, 12506 GL2_OP_ATOMIC_SUB_RTN_32 = 0x00000010, 12507 GL2_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, 12508 GL2_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, 12509 GL2_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, 12510 GL2_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, 12511 GL2_OP_ATOMIC_AND_RTN_32 = 0x00000015, 12512 GL2_OP_ATOMIC_OR_RTN_32 = 0x00000016, 12513 GL2_OP_ATOMIC_XOR_RTN_32 = 0x00000017, 12514 GL2_OP_ATOMIC_INC_RTN_32 = 0x00000018, 12515 GL2_OP_ATOMIC_DEC_RTN_32 = 0x00000019, 12516 GL2_OP_WRITE = 0x00000020, 12517 GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, 12518 GL2_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, 12519 GL2_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, 12520 GL2_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, 12521 GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, 12522 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, 12523 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, 12524 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, 12525 GL2_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, 12526 GL2_OP_ATOMIC_SUB_RTN_64 = 0x00000030, 12527 GL2_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, 12528 GL2_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, 12529 GL2_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, 12530 GL2_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, 12531 GL2_OP_ATOMIC_AND_RTN_64 = 0x00000035, 12532 GL2_OP_ATOMIC_OR_RTN_64 = 0x00000036, 12533 GL2_OP_ATOMIC_XOR_RTN_64 = 0x00000037, 12534 GL2_OP_ATOMIC_INC_RTN_64 = 0x00000038, 12535 GL2_OP_ATOMIC_DEC_RTN_64 = 0x00000039, 12536 GL2_OP_GL1_INV = 0x00000040, 12537 GL2_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, 12538 GL2_OP_ATOMIC_FMIN_32 = 0x00000042, 12539 GL2_OP_ATOMIC_FMAX_32 = 0x00000043, 12540 GL2_OP_ATOMIC_SWAP_32 = 0x00000047, 12541 GL2_OP_ATOMIC_CMPSWAP_32 = 0x00000048, 12542 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, 12543 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, 12544 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, 12545 GL2_OP_ATOMIC_ADD_32 = 0x0000004f, 12546 GL2_OP_ATOMIC_SUB_32 = 0x00000050, 12547 GL2_OP_ATOMIC_SMIN_32 = 0x00000051, 12548 GL2_OP_ATOMIC_UMIN_32 = 0x00000052, 12549 GL2_OP_ATOMIC_SMAX_32 = 0x00000053, 12550 GL2_OP_ATOMIC_UMAX_32 = 0x00000054, 12551 GL2_OP_ATOMIC_AND_32 = 0x00000055, 12552 GL2_OP_ATOMIC_OR_32 = 0x00000056, 12553 GL2_OP_ATOMIC_XOR_32 = 0x00000057, 12554 GL2_OP_ATOMIC_INC_32 = 0x00000058, 12555 GL2_OP_ATOMIC_DEC_32 = 0x00000059, 12556 GL2_OP_NOP_RTN0 = 0x0000005b, 12557 GL2_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, 12558 GL2_OP_ATOMIC_FMIN_64 = 0x00000062, 12559 GL2_OP_ATOMIC_FMAX_64 = 0x00000063, 12560 GL2_OP_ATOMIC_SWAP_64 = 0x00000067, 12561 GL2_OP_ATOMIC_CMPSWAP_64 = 0x00000068, 12562 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, 12563 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, 12564 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, 12565 GL2_OP_ATOMIC_ADD_64 = 0x0000006f, 12566 GL2_OP_ATOMIC_SUB_64 = 0x00000070, 12567 GL2_OP_ATOMIC_SMIN_64 = 0x00000071, 12568 GL2_OP_ATOMIC_UMIN_64 = 0x00000072, 12569 GL2_OP_ATOMIC_SMAX_64 = 0x00000073, 12570 GL2_OP_ATOMIC_UMAX_64 = 0x00000074, 12571 GL2_OP_ATOMIC_AND_64 = 0x00000075, 12572 GL2_OP_ATOMIC_OR_64 = 0x00000076, 12573 GL2_OP_ATOMIC_XOR_64 = 0x00000077, 12574 GL2_OP_ATOMIC_INC_64 = 0x00000078, 12575 GL2_OP_ATOMIC_DEC_64 = 0x00000079, 12576 GL2_OP_NOP_ACK = 0x0000007b, 12577 } GL2_OP; 12578 12579 /* 12580 * GL2_NACKS enum 12581 */ 12582 12583 typedef enum GL2_NACKS { 12584 GL2_NACK_NO_FAULT = 0x00000000, 12585 GL2_NACK_PAGE_FAULT = 0x00000001, 12586 GL2_NACK_PROTECTION_FAULT = 0x00000002, 12587 GL2_NACK_DATA_ERROR = 0x00000003, 12588 } GL2_NACKS; 12589 12590 /* 12591 * GL2_EA_CID enum 12592 */ 12593 12594 typedef enum GL2_EA_CID { 12595 GL2_EA_CID_CLIENT = 0x00000000, 12596 GL2_EA_CID_SDMA = 0x00000001, 12597 GL2_EA_CID_RLC = 0x00000002, 12598 GL2_EA_CID_CP = 0x00000004, 12599 GL2_EA_CID_CPDMA = 0x00000005, 12600 GL2_EA_CID_UTCL2 = 0x00000006, 12601 GL2_EA_CID_RT = 0x00000007, 12602 GL2_EA_CID_FMASK = 0x00000008, 12603 GL2_EA_CID_DCC = 0x00000009, 12604 GL2_EA_CID_Z_STENCIL = 0x0000000a, 12605 GL2_EA_CID_ZPCPSD = 0x0000000b, 12606 GL2_EA_CID_HTILE = 0x0000000c, 12607 GL2_EA_CID_TCPMETA = 0x0000000f, 12608 } GL2_EA_CID; 12609 12610 /******************************************************* 12611 * SPI Enums 12612 *******************************************************/ 12613 12614 /* 12615 * SPI_SAMPLE_CNTL enum 12616 */ 12617 12618 typedef enum SPI_SAMPLE_CNTL { 12619 CENTROIDS_ONLY = 0x00000000, 12620 CENTERS_ONLY = 0x00000001, 12621 CENTROIDS_AND_CENTERS = 0x00000002, 12622 UNDEF = 0x00000003, 12623 } SPI_SAMPLE_CNTL; 12624 12625 /* 12626 * SPI_FOG_MODE enum 12627 */ 12628 12629 typedef enum SPI_FOG_MODE { 12630 SPI_FOG_NONE = 0x00000000, 12631 SPI_FOG_EXP = 0x00000001, 12632 SPI_FOG_EXP2 = 0x00000002, 12633 SPI_FOG_LINEAR = 0x00000003, 12634 } SPI_FOG_MODE; 12635 12636 /* 12637 * SPI_PNT_SPRITE_OVERRIDE enum 12638 */ 12639 12640 typedef enum SPI_PNT_SPRITE_OVERRIDE { 12641 SPI_PNT_SPRITE_SEL_0 = 0x00000000, 12642 SPI_PNT_SPRITE_SEL_1 = 0x00000001, 12643 SPI_PNT_SPRITE_SEL_S = 0x00000002, 12644 SPI_PNT_SPRITE_SEL_T = 0x00000003, 12645 SPI_PNT_SPRITE_SEL_NONE = 0x00000004, 12646 } SPI_PNT_SPRITE_OVERRIDE; 12647 12648 /* 12649 * SPI_PERFCNT_SEL enum 12650 */ 12651 12652 typedef enum SPI_PERFCNT_SEL { 12653 SPI_PERF_VS_WINDOW_VALID = 0x00000000, 12654 SPI_PERF_VS_BUSY = 0x00000001, 12655 SPI_PERF_VS_FIRST_WAVE = 0x00000002, 12656 SPI_PERF_VS_LAST_WAVE = 0x00000003, 12657 SPI_PERF_VS_LSHS_DEALLOC = 0x00000004, 12658 SPI_PERF_VS_PC_STALL = 0x00000005, 12659 SPI_PERF_VS_POS0_STALL = 0x00000006, 12660 SPI_PERF_VS_POS1_STALL = 0x00000007, 12661 SPI_PERF_VS_CRAWLER_STALL = 0x00000008, 12662 SPI_PERF_VS_EVENT_WAVE = 0x00000009, 12663 SPI_PERF_VS_WAVE = 0x0000000a, 12664 SPI_PERF_VS_PERS_UPD_FULL0 = 0x0000000b, 12665 SPI_PERF_VS_PERS_UPD_FULL1 = 0x0000000c, 12666 SPI_PERF_VS_LATE_ALLOC_FULL = 0x0000000d, 12667 SPI_PERF_VS_FIRST_SUBGRP = 0x0000000e, 12668 SPI_PERF_VS_LAST_SUBGRP = 0x0000000f, 12669 SPI_PERF_VS_ALLOC_CNT = 0x00000010, 12670 SPI_PERF_VS_PC_ALLOC_CNT = 0x00000011, 12671 SPI_PERF_VS_LATE_ALLOC_ACCUM = 0x00000012, 12672 SPI_PERF_GS_WINDOW_VALID = 0x00000013, 12673 SPI_PERF_GS_BUSY = 0x00000014, 12674 SPI_PERF_GS_CRAWLER_STALL = 0x00000015, 12675 SPI_PERF_GS_EVENT_WAVE = 0x00000016, 12676 SPI_PERF_GS_WAVE = 0x00000017, 12677 SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000018, 12678 SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000019, 12679 SPI_PERF_GS_FIRST_SUBGRP = 0x0000001a, 12680 SPI_PERF_GS_LAST_SUBGRP = 0x0000001b, 12681 SPI_PERF_GS_HS_DEALLOC = 0x0000001c, 12682 SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 0x0000001d, 12683 SPI_PERF_GS_GRP_FIFO_FULL = 0x0000001e, 12684 SPI_PERF_HS_WINDOW_VALID = 0x0000001f, 12685 SPI_PERF_HS_BUSY = 0x00000020, 12686 SPI_PERF_HS_CRAWLER_STALL = 0x00000021, 12687 SPI_PERF_HS_FIRST_WAVE = 0x00000022, 12688 SPI_PERF_HS_LAST_WAVE = 0x00000023, 12689 SPI_PERF_HS_OFFCHIP_LDS_STALL = 0x00000024, 12690 SPI_PERF_HS_EVENT_WAVE = 0x00000025, 12691 SPI_PERF_HS_WAVE = 0x00000026, 12692 SPI_PERF_HS_PERS_UPD_FULL0 = 0x00000027, 12693 SPI_PERF_HS_PERS_UPD_FULL1 = 0x00000028, 12694 SPI_PERF_CSG_WINDOW_VALID = 0x00000029, 12695 SPI_PERF_CSG_BUSY = 0x0000002a, 12696 SPI_PERF_CSG_NUM_THREADGROUPS = 0x0000002b, 12697 SPI_PERF_CSG_CRAWLER_STALL = 0x0000002c, 12698 SPI_PERF_CSG_EVENT_WAVE = 0x0000002d, 12699 SPI_PERF_CSG_WAVE = 0x0000002e, 12700 SPI_PERF_CSN_WINDOW_VALID = 0x0000002f, 12701 SPI_PERF_CSN_BUSY = 0x00000030, 12702 SPI_PERF_CSN_NUM_THREADGROUPS = 0x00000031, 12703 SPI_PERF_CSN_CRAWLER_STALL = 0x00000032, 12704 SPI_PERF_CSN_EVENT_WAVE = 0x00000033, 12705 SPI_PERF_CSN_WAVE = 0x00000034, 12706 SPI_PERF_PS0_WINDOW_VALID = 0x00000035, 12707 SPI_PERF_PS1_WINDOW_VALID = 0x00000036, 12708 SPI_PERF_PS2_WINDOW_VALID = 0x00000037, 12709 SPI_PERF_PS3_WINDOW_VALID = 0x00000038, 12710 SPI_PERF_PS0_BUSY = 0x00000039, 12711 SPI_PERF_PS1_BUSY = 0x0000003a, 12712 SPI_PERF_PS2_BUSY = 0x0000003b, 12713 SPI_PERF_PS3_BUSY = 0x0000003c, 12714 SPI_PERF_PS0_ACTIVE = 0x0000003d, 12715 SPI_PERF_PS1_ACTIVE = 0x0000003e, 12716 SPI_PERF_PS2_ACTIVE = 0x0000003f, 12717 SPI_PERF_PS3_ACTIVE = 0x00000040, 12718 SPI_PERF_PS0_DEALLOC_BIN0 = 0x00000041, 12719 SPI_PERF_PS1_DEALLOC_BIN0 = 0x00000042, 12720 SPI_PERF_PS2_DEALLOC_BIN0 = 0x00000043, 12721 SPI_PERF_PS3_DEALLOC_BIN0 = 0x00000044, 12722 SPI_PERF_PS0_FPOS_BIN1_STALL = 0x00000045, 12723 SPI_PERF_PS1_FPOS_BIN1_STALL = 0x00000046, 12724 SPI_PERF_PS2_FPOS_BIN1_STALL = 0x00000047, 12725 SPI_PERF_PS3_FPOS_BIN1_STALL = 0x00000048, 12726 SPI_PERF_PS0_EVENT_WAVE = 0x00000049, 12727 SPI_PERF_PS1_EVENT_WAVE = 0x0000004a, 12728 SPI_PERF_PS2_EVENT_WAVE = 0x0000004b, 12729 SPI_PERF_PS3_EVENT_WAVE = 0x0000004c, 12730 SPI_PERF_PS0_WAVE = 0x0000004d, 12731 SPI_PERF_PS1_WAVE = 0x0000004e, 12732 SPI_PERF_PS2_WAVE = 0x0000004f, 12733 SPI_PERF_PS3_WAVE = 0x00000050, 12734 SPI_PERF_PS0_OPT_WAVE = 0x00000051, 12735 SPI_PERF_PS1_OPT_WAVE = 0x00000052, 12736 SPI_PERF_PS2_OPT_WAVE = 0x00000053, 12737 SPI_PERF_PS3_OPT_WAVE = 0x00000054, 12738 SPI_PERF_PS0_PASS_BIN0 = 0x00000055, 12739 SPI_PERF_PS1_PASS_BIN0 = 0x00000056, 12740 SPI_PERF_PS2_PASS_BIN0 = 0x00000057, 12741 SPI_PERF_PS3_PASS_BIN0 = 0x00000058, 12742 SPI_PERF_PS0_PASS_BIN1 = 0x00000059, 12743 SPI_PERF_PS1_PASS_BIN1 = 0x0000005a, 12744 SPI_PERF_PS2_PASS_BIN1 = 0x0000005b, 12745 SPI_PERF_PS3_PASS_BIN1 = 0x0000005c, 12746 SPI_PERF_PS0_FPOS_BIN2 = 0x0000005d, 12747 SPI_PERF_PS1_FPOS_BIN2 = 0x0000005e, 12748 SPI_PERF_PS2_FPOS_BIN2 = 0x0000005f, 12749 SPI_PERF_PS3_FPOS_BIN2 = 0x00000060, 12750 SPI_PERF_PS0_PRIM_BIN0 = 0x00000061, 12751 SPI_PERF_PS1_PRIM_BIN0 = 0x00000062, 12752 SPI_PERF_PS2_PRIM_BIN0 = 0x00000063, 12753 SPI_PERF_PS3_PRIM_BIN0 = 0x00000064, 12754 SPI_PERF_PS0_PRIM_BIN1 = 0x00000065, 12755 SPI_PERF_PS1_PRIM_BIN1 = 0x00000066, 12756 SPI_PERF_PS2_PRIM_BIN1 = 0x00000067, 12757 SPI_PERF_PS3_PRIM_BIN1 = 0x00000068, 12758 SPI_PERF_PS0_CNF_BIN2 = 0x00000069, 12759 SPI_PERF_PS1_CNF_BIN2 = 0x0000006a, 12760 SPI_PERF_PS2_CNF_BIN2 = 0x0000006b, 12761 SPI_PERF_PS3_CNF_BIN2 = 0x0000006c, 12762 SPI_PERF_PS0_CNF_BIN3 = 0x0000006d, 12763 SPI_PERF_PS1_CNF_BIN3 = 0x0000006e, 12764 SPI_PERF_PS2_CNF_BIN3 = 0x0000006f, 12765 SPI_PERF_PS3_CNF_BIN3 = 0x00000070, 12766 SPI_PERF_PS0_CRAWLER_STALL = 0x00000071, 12767 SPI_PERF_PS1_CRAWLER_STALL = 0x00000072, 12768 SPI_PERF_PS2_CRAWLER_STALL = 0x00000073, 12769 SPI_PERF_PS3_CRAWLER_STALL = 0x00000074, 12770 SPI_PERF_PS0_LDS_RES_FULL = 0x00000075, 12771 SPI_PERF_PS1_LDS_RES_FULL = 0x00000076, 12772 SPI_PERF_PS2_LDS_RES_FULL = 0x00000077, 12773 SPI_PERF_PS3_LDS_RES_FULL = 0x00000078, 12774 SPI_PERF_PS_PERS_UPD_FULL0 = 0x00000079, 12775 SPI_PERF_PS_PERS_UPD_FULL1 = 0x0000007a, 12776 SPI_PERF_PS0_POPS_WAVE_SENT = 0x0000007b, 12777 SPI_PERF_PS1_POPS_WAVE_SENT = 0x0000007c, 12778 SPI_PERF_PS2_POPS_WAVE_SENT = 0x0000007d, 12779 SPI_PERF_PS3_POPS_WAVE_SENT = 0x0000007e, 12780 SPI_PERF_PS0_POPS_WAVE_EXIT = 0x0000007f, 12781 SPI_PERF_PS1_POPS_WAVE_EXIT = 0x00000080, 12782 SPI_PERF_PS2_POPS_WAVE_EXIT = 0x00000081, 12783 SPI_PERF_PS3_POPS_WAVE_EXIT = 0x00000082, 12784 SPI_PERF_LDS0_PC_VALID = 0x00000083, 12785 SPI_PERF_LDS1_PC_VALID = 0x00000084, 12786 SPI_PERF_RA_PIPE_REQ_BIN2 = 0x00000085, 12787 SPI_PERF_RA_TASK_REQ_BIN3 = 0x00000086, 12788 SPI_PERF_RA_WR_CTL_FULL = 0x00000087, 12789 SPI_PERF_RA_REQ_NO_ALLOC = 0x00000088, 12790 SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000089, 12791 SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x0000008a, 12792 SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x0000008b, 12793 SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x0000008c, 12794 SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x0000008d, 12795 SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x0000008e, 12796 SPI_PERF_RA_RES_STALL_PS = 0x0000008f, 12797 SPI_PERF_RA_RES_STALL_VS = 0x00000090, 12798 SPI_PERF_RA_RES_STALL_GS = 0x00000091, 12799 SPI_PERF_RA_RES_STALL_HS = 0x00000092, 12800 SPI_PERF_RA_RES_STALL_CSG = 0x00000093, 12801 SPI_PERF_RA_RES_STALL_CSN = 0x00000094, 12802 SPI_PERF_RA_TMP_STALL_PS = 0x00000095, 12803 SPI_PERF_RA_TMP_STALL_VS = 0x00000096, 12804 SPI_PERF_RA_TMP_STALL_GS = 0x00000097, 12805 SPI_PERF_RA_TMP_STALL_HS = 0x00000098, 12806 SPI_PERF_RA_TMP_STALL_CSG = 0x00000099, 12807 SPI_PERF_RA_TMP_STALL_CSN = 0x0000009a, 12808 SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000009b, 12809 SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000009c, 12810 SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000009d, 12811 SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x0000009e, 12812 SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x0000009f, 12813 SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x000000a0, 12814 SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x000000a1, 12815 SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x000000a2, 12816 SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x000000a3, 12817 SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x000000a4, 12818 SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x000000a5, 12819 SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x000000a6, 12820 SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x000000a7, 12821 SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x000000a8, 12822 SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x000000a9, 12823 SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x000000aa, 12824 SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x000000ab, 12825 SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x000000ac, 12826 SPI_PERF_RA_LDS_CU_FULL_PS = 0x000000ad, 12827 SPI_PERF_RA_LDS_CU_FULL_LS = 0x000000ae, 12828 SPI_PERF_RA_LDS_CU_FULL_ES = 0x000000af, 12829 SPI_PERF_RA_LDS_CU_FULL_CSG = 0x000000b0, 12830 SPI_PERF_RA_LDS_CU_FULL_CSN = 0x000000b1, 12831 SPI_PERF_RA_BAR_CU_FULL_HS = 0x000000b2, 12832 SPI_PERF_RA_BAR_CU_FULL_CSG = 0x000000b3, 12833 SPI_PERF_RA_BAR_CU_FULL_CSN = 0x000000b4, 12834 SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x000000b5, 12835 SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x000000b6, 12836 SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x000000b7, 12837 SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x000000b8, 12838 SPI_PERF_RA_WVLIM_STALL_PS = 0x000000b9, 12839 SPI_PERF_RA_WVLIM_STALL_VS = 0x000000ba, 12840 SPI_PERF_RA_WVLIM_STALL_GS = 0x000000bb, 12841 SPI_PERF_RA_WVLIM_STALL_HS = 0x000000bc, 12842 SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000bd, 12843 SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000be, 12844 SPI_PERF_RA_VS_LOCK = 0x000000bf, 12845 SPI_PERF_RA_GS_LOCK = 0x000000c0, 12846 SPI_PERF_RA_HS_LOCK = 0x000000c1, 12847 SPI_PERF_RA_CSG_LOCK = 0x000000c2, 12848 SPI_PERF_RA_CSN_LOCK = 0x000000c3, 12849 SPI_PERF_RA_RSV_UPD = 0x000000c4, 12850 SPI_PERF_EXP_ARB_COL_CNT = 0x000000c5, 12851 SPI_PERF_EXP_ARB_PAR_CNT = 0x000000c6, 12852 SPI_PERF_EXP_ARB_POS_CNT = 0x000000c7, 12853 SPI_PERF_EXP_ARB_GDS_CNT = 0x000000c8, 12854 SPI_PERF_NUM_PS_COL_R0_EXPORTS = 0x000000c9, 12855 SPI_PERF_NUM_PS_COL_R1_EXPORTS = 0x000000ca, 12856 SPI_PERF_NUM_VS_POS_R0_EXPORTS = 0x000000cb, 12857 SPI_PERF_NUM_VS_POS_R1_EXPORTS = 0x000000cc, 12858 SPI_PERF_NUM_VS_PARAM_R0_EXPORTS = 0x000000cd, 12859 SPI_PERF_NUM_VS_PARAM_R1_EXPORTS = 0x000000ce, 12860 SPI_PERF_NUM_VS_GDS_R0_EXPORTS = 0x000000cf, 12861 SPI_PERF_NUM_VS_GDS_R1_EXPORTS = 0x000000d0, 12862 SPI_PERF_NUM_EXPGRANT_EXPORTS = 0x000000d1, 12863 SPI_PERF_CLKGATE_BUSY_STALL = 0x000000d2, 12864 SPI_PERF_CLKGATE_ACTIVE_STALL = 0x000000d3, 12865 SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0x000000d4, 12866 SPI_PERF_CLKGATE_CGTT_DYN_ON = 0x000000d5, 12867 SPI_PERF_CLKGATE_CGTT_REG_ON = 0x000000d6, 12868 SPI_PERF_PIX_ALLOC_PEND_CNT = 0x000000d7, 12869 SPI_PERF_PIX_ALLOC_SCB0_STALL = 0x000000d8, 12870 SPI_PERF_PIX_ALLOC_SCB1_STALL = 0x000000d9, 12871 SPI_PERF_PIX_ALLOC_SCB2_STALL = 0x000000da, 12872 SPI_PERF_PIX_ALLOC_SCB3_STALL = 0x000000db, 12873 SPI_PERF_PIX_ALLOC_DB0_STALL = 0x000000dc, 12874 SPI_PERF_PIX_ALLOC_DB1_STALL = 0x000000dd, 12875 SPI_PERF_PIX_ALLOC_DB2_STALL = 0x000000de, 12876 SPI_PERF_PIX_ALLOC_DB3_STALL = 0x000000df, 12877 SPI_PERF_PIX_ALLOC_DB4_STALL = 0x000000e0, 12878 SPI_PERF_PIX_ALLOC_DB5_STALL = 0x000000e1, 12879 SPI_PERF_PIX_ALLOC_DB6_STALL = 0x000000e2, 12880 SPI_PERF_PIX_ALLOC_DB7_STALL = 0x000000e3, 12881 SPI_PERF_PC_ALLOC_ACCUM = 0x000000e4, 12882 SPI_PERF_GS_NGG_SE_HAS_BATON = 0x000000e5, 12883 SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON = 0x000000e6, 12884 SPI_PERF_GS_NGG_SE_FORWARDED_BATON = 0x000000e7, 12885 SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT = 0x000000e8, 12886 SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT = 0x000000e9, 12887 SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT = 0x000000ea, 12888 SPI_PERF_GS_NGG_PC_FULL = 0x000000eb, 12889 SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 0x000000ec, 12890 SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY = 0x000000ed, 12891 SPI_PERF_GSC_VTX_BUSY = 0x000000ee, 12892 SPI_PERF_GSC_VTX_INPUT_STARVED = 0x000000ef, 12893 SPI_PERF_GSC_VTX_VSR_STALL = 0x000000f0, 12894 SPI_PERF_GSC_VTX_VSR_FULL = 0x000000f1, 12895 SPI_PERF_GSC_VTX_CAC_BUSY = 0x000000f2, 12896 SPI_PERF_ESC_VTX_BUSY = 0x000000f3, 12897 SPI_PERF_ESC_VTX_INPUT_STARVED = 0x000000f4, 12898 SPI_PERF_ESC_VTX_VSR_STALL = 0x000000f5, 12899 SPI_PERF_ESC_VTX_VSR_FULL = 0x000000f6, 12900 SPI_PERF_ESC_VTX_CAC_BUSY = 0x000000f7, 12901 SPI_PERF_SWC_PS_WR = 0x000000f8, 12902 SPI_PERF_SWC_VS_WR = 0x000000f9, 12903 SPI_PERF_SWC_GS_WR = 0x000000fa, 12904 SPI_PERF_SWC_HS_WR = 0x000000fb, 12905 SPI_PERF_SWC_CSG_WR = 0x000000fc, 12906 SPI_PERF_SWC_CSC_WR = 0x000000fd, 12907 SPI_PERF_VWC_PS_WR = 0x000000fe, 12908 SPI_PERF_VWC_VS_WR = 0x000000ff, 12909 SPI_PERF_VWC_GS_WR = 0x00000100, 12910 SPI_PERF_VWC_HS_WR = 0x00000101, 12911 SPI_PERF_VWC_CSG_WR = 0x00000102, 12912 SPI_PERF_VWC_CSC_WR = 0x00000103, 12913 SPI_PERF_ES_WINDOW_VALID = 0x00000104, 12914 SPI_PERF_ES_BUSY = 0x00000105, 12915 SPI_PERF_ES_CRAWLER_STALL = 0x00000106, 12916 SPI_PERF_ES_FIRST_WAVE = 0x00000107, 12917 SPI_PERF_ES_LAST_WAVE = 0x00000108, 12918 SPI_PERF_ES_LSHS_DEALLOC = 0x00000109, 12919 SPI_PERF_ES_EVENT_WAVE = 0x0000010a, 12920 SPI_PERF_ES_WAVE = 0x0000010b, 12921 SPI_PERF_ES_PERS_UPD_FULL0 = 0x0000010c, 12922 SPI_PERF_ES_PERS_UPD_FULL1 = 0x0000010d, 12923 SPI_PERF_ES_FIRST_SUBGRP = 0x0000010e, 12924 SPI_PERF_ES_LAST_SUBGRP = 0x0000010f, 12925 SPI_PERF_LS_WINDOW_VALID = 0x00000110, 12926 SPI_PERF_LS_BUSY = 0x00000111, 12927 SPI_PERF_LS_CRAWLER_STALL = 0x00000112, 12928 SPI_PERF_LS_FIRST_WAVE = 0x00000113, 12929 SPI_PERF_LS_LAST_WAVE = 0x00000114, 12930 SPI_PERF_LS_OFFCHIP_LDS_STALL = 0x00000115, 12931 SPI_PERF_LS_EVENT_WAVE = 0x00000116, 12932 SPI_PERF_LS_WAVE = 0x00000117, 12933 SPI_PERF_LS_PERS_UPD_FULL0 = 0x00000118, 12934 SPI_PERF_LS_PERS_UPD_FULL1 = 0x00000119, 12935 } SPI_PERFCNT_SEL; 12936 12937 /* 12938 * SPI_SHADER_FORMAT enum 12939 */ 12940 12941 typedef enum SPI_SHADER_FORMAT { 12942 SPI_SHADER_NONE = 0x00000000, 12943 SPI_SHADER_1COMP = 0x00000001, 12944 SPI_SHADER_2COMP = 0x00000002, 12945 SPI_SHADER_4COMPRESS = 0x00000003, 12946 SPI_SHADER_4COMP = 0x00000004, 12947 } SPI_SHADER_FORMAT; 12948 12949 /* 12950 * SPI_SHADER_EX_FORMAT enum 12951 */ 12952 12953 typedef enum SPI_SHADER_EX_FORMAT { 12954 SPI_SHADER_ZERO = 0x00000000, 12955 SPI_SHADER_32_R = 0x00000001, 12956 SPI_SHADER_32_GR = 0x00000002, 12957 SPI_SHADER_32_AR = 0x00000003, 12958 SPI_SHADER_FP16_ABGR = 0x00000004, 12959 SPI_SHADER_UNORM16_ABGR = 0x00000005, 12960 SPI_SHADER_SNORM16_ABGR = 0x00000006, 12961 SPI_SHADER_UINT16_ABGR = 0x00000007, 12962 SPI_SHADER_SINT16_ABGR = 0x00000008, 12963 SPI_SHADER_32_ABGR = 0x00000009, 12964 } SPI_SHADER_EX_FORMAT; 12965 12966 /* 12967 * CLKGATE_SM_MODE enum 12968 */ 12969 12970 typedef enum CLKGATE_SM_MODE { 12971 ON_SEQ = 0x00000000, 12972 OFF_SEQ = 0x00000001, 12973 PROG_SEQ = 0x00000002, 12974 READ_SEQ = 0x00000003, 12975 SM_MODE_RESERVED = 0x00000004, 12976 } CLKGATE_SM_MODE; 12977 12978 /* 12979 * CLKGATE_BASE_MODE enum 12980 */ 12981 12982 typedef enum CLKGATE_BASE_MODE { 12983 MULT_8 = 0x00000000, 12984 MULT_16 = 0x00000001, 12985 } CLKGATE_BASE_MODE; 12986 12987 /* 12988 * SPI_LB_WAVES_SELECT enum 12989 */ 12990 12991 typedef enum SPI_LB_WAVES_SELECT { 12992 HS_GS = 0x00000000, 12993 VS_PS = 0x00000001, 12994 CS_NA = 0x00000002, 12995 SPI_LB_WAVES_RSVD = 0x00000003, 12996 } SPI_LB_WAVES_SELECT; 12997 12998 /******************************************************* 12999 * SQ Enums 13000 *******************************************************/ 13001 13002 /* 13003 * SQ_TEX_CLAMP enum 13004 */ 13005 13006 typedef enum SQ_TEX_CLAMP { 13007 SQ_TEX_WRAP = 0x00000000, 13008 SQ_TEX_MIRROR = 0x00000001, 13009 SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, 13010 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, 13011 SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, 13012 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, 13013 SQ_TEX_CLAMP_BORDER = 0x00000006, 13014 SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, 13015 } SQ_TEX_CLAMP; 13016 13017 /* 13018 * SQ_TEX_XY_FILTER enum 13019 */ 13020 13021 typedef enum SQ_TEX_XY_FILTER { 13022 SQ_TEX_XY_FILTER_POINT = 0x00000000, 13023 SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, 13024 SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, 13025 SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, 13026 } SQ_TEX_XY_FILTER; 13027 13028 /* 13029 * SQ_TEX_Z_FILTER enum 13030 */ 13031 13032 typedef enum SQ_TEX_Z_FILTER { 13033 SQ_TEX_Z_FILTER_NONE = 0x00000000, 13034 SQ_TEX_Z_FILTER_POINT = 0x00000001, 13035 SQ_TEX_Z_FILTER_LINEAR = 0x00000002, 13036 } SQ_TEX_Z_FILTER; 13037 13038 /* 13039 * SQ_TEX_MIP_FILTER enum 13040 */ 13041 13042 typedef enum SQ_TEX_MIP_FILTER { 13043 SQ_TEX_MIP_FILTER_NONE = 0x00000000, 13044 SQ_TEX_MIP_FILTER_POINT = 0x00000001, 13045 SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, 13046 SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003, 13047 } SQ_TEX_MIP_FILTER; 13048 13049 /* 13050 * SQ_TEX_ANISO_RATIO enum 13051 */ 13052 13053 typedef enum SQ_TEX_ANISO_RATIO { 13054 SQ_TEX_ANISO_RATIO_1 = 0x00000000, 13055 SQ_TEX_ANISO_RATIO_2 = 0x00000001, 13056 SQ_TEX_ANISO_RATIO_4 = 0x00000002, 13057 SQ_TEX_ANISO_RATIO_8 = 0x00000003, 13058 SQ_TEX_ANISO_RATIO_16 = 0x00000004, 13059 } SQ_TEX_ANISO_RATIO; 13060 13061 /* 13062 * SQ_TEX_DEPTH_COMPARE enum 13063 */ 13064 13065 typedef enum SQ_TEX_DEPTH_COMPARE { 13066 SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, 13067 SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, 13068 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, 13069 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, 13070 SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, 13071 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, 13072 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, 13073 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, 13074 } SQ_TEX_DEPTH_COMPARE; 13075 13076 /* 13077 * SQ_TEX_BORDER_COLOR enum 13078 */ 13079 13080 typedef enum SQ_TEX_BORDER_COLOR { 13081 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, 13082 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, 13083 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, 13084 SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, 13085 } SQ_TEX_BORDER_COLOR; 13086 13087 /* 13088 * SQ_RSRC_BUF_TYPE enum 13089 */ 13090 13091 typedef enum SQ_RSRC_BUF_TYPE { 13092 SQ_RSRC_BUF = 0x00000000, 13093 SQ_RSRC_BUF_RSVD_1 = 0x00000001, 13094 SQ_RSRC_BUF_RSVD_2 = 0x00000002, 13095 SQ_RSRC_BUF_RSVD_3 = 0x00000003, 13096 } SQ_RSRC_BUF_TYPE; 13097 13098 /* 13099 * SQ_RSRC_IMG_TYPE enum 13100 */ 13101 13102 typedef enum SQ_RSRC_IMG_TYPE { 13103 SQ_RSRC_IMG_RSVD_0 = 0x00000000, 13104 SQ_RSRC_IMG_RSVD_1 = 0x00000001, 13105 SQ_RSRC_IMG_RSVD_2 = 0x00000002, 13106 SQ_RSRC_IMG_RSVD_3 = 0x00000003, 13107 SQ_RSRC_IMG_RSVD_4 = 0x00000004, 13108 SQ_RSRC_IMG_RSVD_5 = 0x00000005, 13109 SQ_RSRC_IMG_RSVD_6 = 0x00000006, 13110 SQ_RSRC_IMG_RSVD_7 = 0x00000007, 13111 SQ_RSRC_IMG_1D = 0x00000008, 13112 SQ_RSRC_IMG_2D = 0x00000009, 13113 SQ_RSRC_IMG_3D = 0x0000000a, 13114 SQ_RSRC_IMG_CUBE = 0x0000000b, 13115 SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, 13116 SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, 13117 SQ_RSRC_IMG_2D_MSAA = 0x0000000e, 13118 SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, 13119 } SQ_RSRC_IMG_TYPE; 13120 13121 /* 13122 * SQ_RSRC_FLAT_TYPE enum 13123 */ 13124 13125 typedef enum SQ_RSRC_FLAT_TYPE { 13126 SQ_RSRC_FLAT_RSVD_0 = 0x00000000, 13127 SQ_RSRC_FLAT = 0x00000001, 13128 SQ_RSRC_FLAT_RSVD_2 = 0x00000002, 13129 SQ_RSRC_FLAT_RSVD_3 = 0x00000003, 13130 } SQ_RSRC_FLAT_TYPE; 13131 13132 /* 13133 * SQ_IMG_FILTER_TYPE enum 13134 */ 13135 13136 typedef enum SQ_IMG_FILTER_TYPE { 13137 SQ_IMG_FILTER_MODE_BLEND = 0x00000000, 13138 SQ_IMG_FILTER_MODE_MIN = 0x00000001, 13139 SQ_IMG_FILTER_MODE_MAX = 0x00000002, 13140 } SQ_IMG_FILTER_TYPE; 13141 13142 /* 13143 * SQ_SEL_XYZW01 enum 13144 */ 13145 13146 typedef enum SQ_SEL_XYZW01 { 13147 SQ_SEL_0 = 0x00000000, 13148 SQ_SEL_1 = 0x00000001, 13149 SQ_SEL_N_BC_1 = 0x00000002, 13150 SQ_SEL_RESERVED_1 = 0x00000003, 13151 SQ_SEL_X = 0x00000004, 13152 SQ_SEL_Y = 0x00000005, 13153 SQ_SEL_Z = 0x00000006, 13154 SQ_SEL_W = 0x00000007, 13155 } SQ_SEL_XYZW01; 13156 13157 /* 13158 * SQ_OOB_SELECT enum 13159 */ 13160 13161 typedef enum SQ_OOB_SELECT { 13162 SQ_OOB_INDEX_AND_OFFSET = 0x00000000, 13163 SQ_OOB_INDEX_ONLY = 0x00000001, 13164 SQ_OOB_NUM_RECORDS_0 = 0x00000002, 13165 SQ_OOB_COMPLETE = 0x00000003, 13166 } SQ_OOB_SELECT; 13167 13168 /* 13169 * SQ_WAVE_TYPE enum 13170 */ 13171 13172 typedef enum SQ_WAVE_TYPE { 13173 SQ_WAVE_TYPE_PS = 0x00000000, 13174 SQ_WAVE_TYPE_VS = 0x00000001, 13175 SQ_WAVE_TYPE_GS = 0x00000002, 13176 SQ_WAVE_TYPE_ES = 0x00000003, 13177 SQ_WAVE_TYPE_HS = 0x00000004, 13178 SQ_WAVE_TYPE_LS = 0x00000005, 13179 SQ_WAVE_TYPE_CS = 0x00000006, 13180 SQ_WAVE_TYPE_PS1 = 0x00000007, 13181 SQ_WAVE_TYPE_PS2 = 0x00000008, 13182 SQ_WAVE_TYPE_PS3 = 0x00000009, 13183 } SQ_WAVE_TYPE; 13184 13185 /* 13186 * SQ_PERF_SEL enum 13187 */ 13188 13189 typedef enum SQ_PERF_SEL { 13190 SQ_PERF_SEL_NONE = 0x00000000, 13191 SQ_PERF_SEL_ACCUM_PREV = 0x00000001, 13192 SQ_PERF_SEL_CYCLES = 0x00000002, 13193 SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, 13194 SQ_PERF_SEL_WAVES = 0x00000004, 13195 SQ_PERF_SEL_WAVES_32 = 0x00000005, 13196 SQ_PERF_SEL_WAVES_64 = 0x00000006, 13197 SQ_PERF_SEL_LEVEL_WAVES = 0x00000007, 13198 SQ_PERF_SEL_ITEMS = 0x00000008, 13199 SQ_PERF_SEL_WAVE32_ITEMS = 0x00000009, 13200 SQ_PERF_SEL_WAVE64_ITEMS = 0x0000000a, 13201 SQ_PERF_SEL_QUADS = 0x0000000b, 13202 SQ_PERF_SEL_EVENTS = 0x0000000c, 13203 SQ_PERF_SEL_WAVES_EQ_64 = 0x0000000d, 13204 SQ_PERF_SEL_WAVES_LT_64 = 0x0000000e, 13205 SQ_PERF_SEL_WAVES_LT_48 = 0x0000000f, 13206 SQ_PERF_SEL_WAVES_LT_32 = 0x00000010, 13207 SQ_PERF_SEL_WAVES_LT_16 = 0x00000011, 13208 SQ_PERF_SEL_WAVES_RESTORED = 0x00000012, 13209 SQ_PERF_SEL_WAVES_SAVED = 0x00000013, 13210 SQ_PERF_SEL_MSG = 0x00000014, 13211 SQ_PERF_SEL_MSG_GSCNT = 0x00000015, 13212 SQ_PERF_SEL_MSG_INTERRUPT = 0x00000016, 13213 SQ_PERF_SEL_Reserved_1 = 0x00000017, 13214 SQ_PERF_SEL_Reserved_2 = 0x00000018, 13215 SQ_PERF_SEL_Reserved_3 = 0x00000019, 13216 SQ_PERF_SEL_WAVE_CYCLES = 0x0000001a, 13217 SQ_PERF_SEL_WAVE_READY = 0x0000001b, 13218 SQ_PERF_SEL_WAIT_INST_ANY = 0x0000001c, 13219 SQ_PERF_SEL_WAIT_INST_VALU = 0x0000001d, 13220 SQ_PERF_SEL_WAIT_INST_SCA = 0x0000001e, 13221 SQ_PERF_SEL_WAIT_INST_LDS = 0x0000001f, 13222 SQ_PERF_SEL_WAIT_INST_TEX = 0x00000020, 13223 SQ_PERF_SEL_WAIT_INST_FLAT = 0x00000021, 13224 SQ_PERF_SEL_WAIT_INST_VMEM = 0x00000022, 13225 SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000023, 13226 SQ_PERF_SEL_WAIT_INST_BR_MSG = 0x00000024, 13227 SQ_PERF_SEL_WAIT_ANY = 0x00000025, 13228 SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000026, 13229 SQ_PERF_SEL_WAIT_CNT_VMVS = 0x00000027, 13230 SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000028, 13231 SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000029, 13232 SQ_PERF_SEL_WAIT_TTRACE = 0x0000002a, 13233 SQ_PERF_SEL_WAIT_IFETCH = 0x0000002b, 13234 SQ_PERF_SEL_WAIT_BARRIER = 0x0000002c, 13235 SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x0000002d, 13236 SQ_PERF_SEL_WAIT_SLEEP = 0x0000002e, 13237 SQ_PERF_SEL_WAIT_SLEEP_XNACK = 0x0000002f, 13238 SQ_PERF_SEL_WAIT_OTHER = 0x00000030, 13239 SQ_PERF_SEL_INSTS_ALL = 0x00000031, 13240 SQ_PERF_SEL_INSTS_BRANCH = 0x00000032, 13241 SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 0x00000033, 13242 SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 0x00000034, 13243 SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 0x00000035, 13244 SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000036, 13245 SQ_PERF_SEL_INSTS_GDS = 0x00000037, 13246 SQ_PERF_SEL_INSTS_EXP = 0x00000038, 13247 SQ_PERF_SEL_INSTS_FLAT = 0x00000039, 13248 SQ_PERF_SEL_Reserved_4 = 0x0000003a, 13249 SQ_PERF_SEL_INSTS_LDS = 0x0000003b, 13250 SQ_PERF_SEL_INSTS_SALU = 0x0000003c, 13251 SQ_PERF_SEL_INSTS_SMEM = 0x0000003d, 13252 SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000003e, 13253 SQ_PERF_SEL_INSTS_SENDMSG = 0x0000003f, 13254 SQ_PERF_SEL_INSTS_VALU = 0x00000040, 13255 SQ_PERF_SEL_Reserved_17 = 0x00000041, 13256 SQ_PERF_SEL_INSTS_VALU_TRANS32 = 0x00000042, 13257 SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 0x00000043, 13258 SQ_PERF_SEL_INSTS_TEX = 0x00000044, 13259 SQ_PERF_SEL_INSTS_TEX_LOAD = 0x00000045, 13260 SQ_PERF_SEL_INSTS_TEX_STORE = 0x00000046, 13261 SQ_PERF_SEL_INSTS_WAVE32 = 0x00000047, 13262 SQ_PERF_SEL_INSTS_WAVE32_FLAT = 0x00000048, 13263 SQ_PERF_SEL_Reserved_5 = 0x00000049, 13264 SQ_PERF_SEL_INSTS_WAVE32_LDS = 0x0000004a, 13265 SQ_PERF_SEL_INSTS_WAVE32_VALU = 0x0000004b, 13266 SQ_PERF_SEL_Reserved_16 = 0x0000004c, 13267 SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 0x0000004d, 13268 SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 0x0000004e, 13269 SQ_PERF_SEL_INSTS_WAVE32_TEX = 0x0000004f, 13270 SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 0x00000050, 13271 SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 0x00000051, 13272 SQ_PERF_SEL_ITEM_CYCLES_VALU = 0x00000052, 13273 SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 0x00000053, 13274 SQ_PERF_SEL_WAVE32_INSTS = 0x00000054, 13275 SQ_PERF_SEL_WAVE64_INSTS = 0x00000055, 13276 SQ_PERF_SEL_Reserved_18 = 0x00000056, 13277 SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 0x00000057, 13278 SQ_PERF_SEL_WAVE64_HALF_SKIP = 0x00000058, 13279 SQ_PERF_SEL_INSTS_TEX_REPLAY = 0x00000059, 13280 SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x0000005a, 13281 SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x0000005b, 13282 SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x0000005c, 13283 SQ_PERF_SEL_XNACK_ALL = 0x0000005d, 13284 SQ_PERF_SEL_XNACK_FIRST = 0x0000005e, 13285 SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD = 0x0000005f, 13286 SQ_PERF_SEL_INSTS_VALU_VINTRP_OP = 0x00000060, 13287 SQ_PERF_SEL_INST_LEVEL_EXP = 0x00000061, 13288 SQ_PERF_SEL_INST_LEVEL_GDS = 0x00000062, 13289 SQ_PERF_SEL_INST_LEVEL_LDS = 0x00000063, 13290 SQ_PERF_SEL_INST_LEVEL_SMEM = 0x00000064, 13291 SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 0x00000065, 13292 SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 0x00000066, 13293 SQ_PERF_SEL_IFETCH_REQS = 0x00000067, 13294 SQ_PERF_SEL_IFETCH_LEVEL = 0x00000068, 13295 SQ_PERF_SEL_IFETCH_XNACK = 0x00000069, 13296 SQ_PERF_SEL_Reserved_6 = 0x0000006a, 13297 SQ_PERF_SEL_Reserved_7 = 0x0000006b, 13298 SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 0x0000006c, 13299 SQ_PERF_SEL_VALU_SGATHER_STALL = 0x0000006d, 13300 SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 0x0000006e, 13301 SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 0x0000006f, 13302 SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 0x00000070, 13303 SQ_PERF_SEL_SALU_SGATHER_STALL = 0x00000071, 13304 SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 0x00000072, 13305 SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 0x00000073, 13306 SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 0x00000074, 13307 SQ_PERF_SEL_INST_CYCLES_VALU = 0x00000075, 13308 SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 0x00000076, 13309 SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 0x00000077, 13310 SQ_PERF_SEL_INST_CYCLES_VMEM = 0x00000078, 13311 SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 0x00000079, 13312 SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 0x0000007a, 13313 SQ_PERF_SEL_INST_CYCLES_LDS = 0x0000007b, 13314 SQ_PERF_SEL_INST_CYCLES_TEX = 0x0000007c, 13315 SQ_PERF_SEL_INST_CYCLES_FLAT = 0x0000007d, 13316 SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x0000007e, 13317 SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 0x0000007f, 13318 SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 0x00000080, 13319 SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000081, 13320 SQ_PERF_SEL_Reserved_8 = 0x00000082, 13321 SQ_PERF_SEL_Reserved_9 = 0x00000083, 13322 SQ_PERF_SEL_Reserved_10 = 0x00000084, 13323 SQ_PERF_SEL_Reserved_11 = 0x00000085, 13324 SQ_PERF_SEL_Reserved_12 = 0x00000086, 13325 SQ_PERF_SEL_Reserved_13 = 0x00000087, 13326 SQ_PERF_SEL_Reserved_14 = 0x00000088, 13327 SQ_PERF_SEL_VMEM_BUS_ACTIVE = 0x00000089, 13328 SQ_PERF_SEL_VMEM_BUS_STALL = 0x0000008a, 13329 SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 0x0000008b, 13330 SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 0x0000008c, 13331 SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 0x0000008d, 13332 SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 0x0000008e, 13333 SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 0x0000008f, 13334 SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 0x00000090, 13335 SQ_PERF_SEL_Reserved_15 = 0x00000091, 13336 SQ_PERF_SEL_SALU_PIPE_STALL = 0x00000092, 13337 SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 0x00000093, 13338 SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL = 0x00000094, 13339 SQ_PERF_SEL_MSG_BUS_BUSY = 0x00000095, 13340 SQ_PERF_SEL_EXP_REQ_BUS_STALL = 0x00000096, 13341 SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000097, 13342 SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000098, 13343 SQ_PERF_SEL_EXP_BUS0_BUSY = 0x00000099, 13344 SQ_PERF_SEL_EXP_BUS1_BUSY = 0x0000009a, 13345 SQ_PERF_SEL_INST_CACHE_REQS = 0x0000009b, 13346 SQ_PERF_SEL_INST_CACHE_REQ_STALL = 0x0000009c, 13347 SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU = 0x0000009d, 13348 SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU = 0x0000009e, 13349 SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM = 0x0000009f, 13350 SQ_PERF_SEL_USER0 = 0x000000a0, 13351 SQ_PERF_SEL_USER1 = 0x000000a1, 13352 SQ_PERF_SEL_USER2 = 0x000000a2, 13353 SQ_PERF_SEL_USER3 = 0x000000a3, 13354 SQ_PERF_SEL_USER4 = 0x000000a4, 13355 SQ_PERF_SEL_USER5 = 0x000000a5, 13356 SQ_PERF_SEL_USER6 = 0x000000a6, 13357 SQ_PERF_SEL_USER7 = 0x000000a7, 13358 SQ_PERF_SEL_USER8 = 0x000000a8, 13359 SQ_PERF_SEL_USER9 = 0x000000a9, 13360 SQ_PERF_SEL_USER10 = 0x000000aa, 13361 SQ_PERF_SEL_USER11 = 0x000000ab, 13362 SQ_PERF_SEL_USER12 = 0x000000ac, 13363 SQ_PERF_SEL_USER13 = 0x000000ad, 13364 SQ_PERF_SEL_USER14 = 0x000000ae, 13365 SQ_PERF_SEL_USER15 = 0x000000af, 13366 SQ_PERF_SEL_USER_LEVEL0 = 0x000000b0, 13367 SQ_PERF_SEL_USER_LEVEL1 = 0x000000b1, 13368 SQ_PERF_SEL_USER_LEVEL2 = 0x000000b2, 13369 SQ_PERF_SEL_USER_LEVEL3 = 0x000000b3, 13370 SQ_PERF_SEL_USER_LEVEL4 = 0x000000b4, 13371 SQ_PERF_SEL_USER_LEVEL5 = 0x000000b5, 13372 SQ_PERF_SEL_USER_LEVEL6 = 0x000000b6, 13373 SQ_PERF_SEL_USER_LEVEL7 = 0x000000b7, 13374 SQ_PERF_SEL_USER_LEVEL8 = 0x000000b8, 13375 SQ_PERF_SEL_USER_LEVEL9 = 0x000000b9, 13376 SQ_PERF_SEL_USER_LEVEL10 = 0x000000ba, 13377 SQ_PERF_SEL_USER_LEVEL11 = 0x000000bb, 13378 SQ_PERF_SEL_USER_LEVEL12 = 0x000000bc, 13379 SQ_PERF_SEL_USER_LEVEL13 = 0x000000bd, 13380 SQ_PERF_SEL_USER_LEVEL14 = 0x000000be, 13381 SQ_PERF_SEL_USER_LEVEL15 = 0x000000bf, 13382 SQ_PERF_SEL_VALU_RETURN_SDST = 0x000000c0, 13383 SQ_PERF_SEL_VMEM_SECOND_TRY_USED = 0x000000c1, 13384 SQ_PERF_SEL_VMEM_SECOND_TRY_STALL = 0x000000c2, 13385 SQ_PERF_SEL_DUMMY_END = 0x000000c3, 13386 SQ_PERF_SEL_DUMMY_LAST = 0x000000ff, 13387 SQG_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000100, 13388 SQG_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000101, 13389 SQG_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000102, 13390 SQG_PERF_SEL_UTCL0_REQUEST = 0x00000103, 13391 SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x00000104, 13392 SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000105, 13393 SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000106, 13394 SQG_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000107, 13395 SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000108, 13396 SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x00000109, 13397 SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL = 0x0000010a, 13398 SQG_PERF_SEL_UTCL0_UTCL1_REQ = 0x0000010b, 13399 SQG_PERF_SEL_TLB_SHOOTDOWN = 0x0000010c, 13400 SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x0000010d, 13401 SQG_PERF_SEL_TTRACE_REQS = 0x0000010e, 13402 SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x0000010f, 13403 SQG_PERF_SEL_TTRACE_STALL = 0x00000110, 13404 SQG_PERF_SEL_TTRACE_LOST_PACKETS = 0x00000111, 13405 SQG_PERF_SEL_DUMMY_LAST = 0x00000112, 13406 SQC_PERF_SEL_POWER_VALU = 0x00000113, 13407 SQC_PERF_SEL_POWER_VALU0 = 0x00000114, 13408 SQC_PERF_SEL_POWER_VALU1 = 0x00000115, 13409 SQC_PERF_SEL_POWER_VALU2 = 0x00000116, 13410 SQC_PERF_SEL_POWER_GPR_RD = 0x00000117, 13411 SQC_PERF_SEL_POWER_GPR_WR = 0x00000118, 13412 SQC_PERF_SEL_POWER_LDS_BUSY = 0x00000119, 13413 SQC_PERF_SEL_POWER_ALU_BUSY = 0x0000011a, 13414 SQC_PERF_SEL_POWER_TEX_BUSY = 0x0000011b, 13415 SQC_PERF_SEL_PT_POWER_STALL = 0x0000011c, 13416 SQC_PERF_SEL_LDS_BANK_CONFLICT = 0x0000011d, 13417 SQC_PERF_SEL_LDS_ADDR_CONFLICT = 0x0000011e, 13418 SQC_PERF_SEL_LDS_UNALIGNED_STALL = 0x0000011f, 13419 SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000120, 13420 SQC_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000121, 13421 SQC_PERF_SEL_LDS_IDX_ACTIVE = 0x00000122, 13422 SQC_PERF_SEL_LDS_DATA_FIFO_FULL = 0x00000123, 13423 SQC_PERF_SEL_LDS_CMD_FIFO_FULL = 0x00000124, 13424 SQC_PERF_SEL_LDS_ADDR_STALL = 0x00000125, 13425 SQC_PERF_SEL_LDS_ADDR_ACTIVE = 0x00000126, 13426 SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL = 0x00000127, 13427 SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 0x00000128, 13428 SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 0x00000129, 13429 SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 0x0000012a, 13430 SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 0x0000012b, 13431 SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000012c, 13432 SQC_PERF_SEL_ICACHE_REQ = 0x0000012d, 13433 SQC_PERF_SEL_ICACHE_HITS = 0x0000012e, 13434 SQC_PERF_SEL_ICACHE_MISSES = 0x0000012f, 13435 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000130, 13436 SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000131, 13437 SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000132, 13438 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000133, 13439 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000134, 13440 SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000135, 13441 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000136, 13442 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000137, 13443 SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0x00000138, 13444 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000139, 13445 SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0x0000013a, 13446 SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0x0000013b, 13447 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x0000013c, 13448 SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0x0000013d, 13449 SQC_PERF_SEL_TC_REQ = 0x0000013e, 13450 SQC_PERF_SEL_TC_INST_REQ = 0x0000013f, 13451 SQC_PERF_SEL_TC_DATA_READ_REQ = 0x00000140, 13452 SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0x00000141, 13453 SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0x00000142, 13454 SQC_PERF_SEL_TC_STALL = 0x00000143, 13455 SQC_PERF_SEL_TC_STARVE = 0x00000144, 13456 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000145, 13457 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000146, 13458 SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000147, 13459 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x00000148, 13460 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000149, 13461 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0x0000014a, 13462 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000014b, 13463 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x0000014c, 13464 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000014d, 13465 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000014e, 13466 SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x0000014f, 13467 SQC_PERF_SEL_DCACHE_REQ = 0x00000150, 13468 SQC_PERF_SEL_DCACHE_HITS = 0x00000151, 13469 SQC_PERF_SEL_DCACHE_MISSES = 0x00000152, 13470 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000153, 13471 SQC_PERF_SEL_DCACHE_INVAL_INST = 0x00000154, 13472 SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x00000155, 13473 SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x00000156, 13474 SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0x00000157, 13475 SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0x00000158, 13476 SQC_PERF_SEL_DCACHE_ATOMIC = 0x00000159, 13477 SQC_PERF_SEL_DCACHE_WB_INST = 0x0000015a, 13478 SQC_PERF_SEL_DCACHE_WB_ASYNC = 0x0000015b, 13479 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000015c, 13480 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x0000015d, 13481 SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x0000015e, 13482 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x0000015f, 13483 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000160, 13484 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000161, 13485 SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0x00000162, 13486 SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0x00000163, 13487 SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 0x00000164, 13488 SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0x00000165, 13489 SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0x00000166, 13490 SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0x00000167, 13491 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x00000168, 13492 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x00000169, 13493 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000016a, 13494 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000016b, 13495 SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x0000016c, 13496 SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x0000016d, 13497 SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x0000016e, 13498 SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x0000016f, 13499 SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000170, 13500 SQC_PERF_SEL_DCACHE_REQ_TIME = 0x00000171, 13501 SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0x00000172, 13502 SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0x00000173, 13503 SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0x00000174, 13504 SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x00000175, 13505 SQC_PERF_SEL_SQ_DCACHE_REQS = 0x00000176, 13506 SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x00000177, 13507 SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0x00000178, 13508 SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS = 0x00000179, 13509 SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS = 0x0000017a, 13510 SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT = 0x0000017b, 13511 SQC_PERF_SEL_ICACHE_UTCL0_REQUEST = 0x0000017c, 13512 SQC_PERF_SEL_ICACHE_UTCL0_XNACK = 0x0000017d, 13513 SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX = 0x0000017e, 13514 SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT = 0x0000017f, 13515 SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL = 0x00000180, 13516 SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES = 0x00000181, 13517 SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x00000182, 13518 SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT = 0x00000183, 13519 SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL = 0x00000184, 13520 SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS = 0x00000185, 13521 SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS = 0x00000186, 13522 SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT = 0x00000187, 13523 SQC_PERF_SEL_DCACHE_UTCL0_REQUEST = 0x00000188, 13524 SQC_PERF_SEL_DCACHE_UTCL0_XNACK = 0x00000189, 13525 SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX = 0x0000018a, 13526 SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT = 0x0000018b, 13527 SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL = 0x0000018c, 13528 SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES = 0x0000018d, 13529 SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000018e, 13530 SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT = 0x0000018f, 13531 SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL = 0x00000190, 13532 SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS = 0x00000191, 13533 SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL = 0x00000192, 13534 SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL = 0x00000193, 13535 SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ = 0x00000194, 13536 SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL = 0x00000195, 13537 SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ = 0x00000196, 13538 SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL = 0x00000197, 13539 SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ = 0x00000198, 13540 SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL = 0x00000199, 13541 SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ = 0x0000019a, 13542 SQC_PERF_SEL_ICACHE_GCR = 0x0000019b, 13543 SQC_PERF_SEL_ICACHE_GCR_HITS = 0x0000019c, 13544 SQC_PERF_SEL_DCACHE_GCR = 0x0000019d, 13545 SQC_PERF_SEL_DCACHE_GCR_HITS = 0x0000019e, 13546 SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 0x0000019f, 13547 SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 0x000001a0, 13548 SQC_PERF_SEL_DCACHE_GCR_WRITEBACK = 0x000001a1, 13549 SQC_PERF_SEL_DUMMY_LAST = 0x000001a2, 13550 SP_PERF_SEL_DUMMY_BEGIN = 0x000001c0, 13551 SP_PERF_SEL_DUMMY_LAST = 0x000001ff, 13552 } SQ_PERF_SEL; 13553 13554 /* 13555 * SQ_CAC_POWER_SEL enum 13556 */ 13557 13558 typedef enum SQ_CAC_POWER_SEL { 13559 SQ_CAC_POWER_VALU = 0x00000000, 13560 SQ_CAC_POWER_VALU0 = 0x00000001, 13561 SQ_CAC_POWER_VALU1 = 0x00000002, 13562 SQ_CAC_POWER_VALU2 = 0x00000003, 13563 SQ_CAC_POWER_GPR_RD = 0x00000004, 13564 SQ_CAC_POWER_GPR_WR = 0x00000005, 13565 SQ_CAC_POWER_LDS_BUSY = 0x00000006, 13566 SQ_CAC_POWER_ALU_BUSY = 0x00000007, 13567 SQ_CAC_POWER_TEX_BUSY = 0x00000008, 13568 } SQ_CAC_POWER_SEL; 13569 13570 /* 13571 * SQ_IND_CMD_CMD enum 13572 */ 13573 13574 typedef enum SQ_IND_CMD_CMD { 13575 SQ_IND_CMD_CMD_NULL = 0x00000000, 13576 SQ_IND_CMD_CMD_SETHALT = 0x00000001, 13577 SQ_IND_CMD_CMD_SAVECTX = 0x00000002, 13578 SQ_IND_CMD_CMD_KILL = 0x00000003, 13579 SQ_IND_CMD_CMD_DEBUG = 0x00000004, 13580 SQ_IND_CMD_CMD_TRAP = 0x00000005, 13581 SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006, 13582 SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007, 13583 SQ_IND_CMD_CMD_SINGLE_STEP = 0x00000008, 13584 } SQ_IND_CMD_CMD; 13585 13586 /* 13587 * SQ_IND_CMD_MODE enum 13588 */ 13589 13590 typedef enum SQ_IND_CMD_MODE { 13591 SQ_IND_CMD_MODE_SINGLE = 0x00000000, 13592 SQ_IND_CMD_MODE_BROADCAST = 0x00000001, 13593 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, 13594 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, 13595 SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, 13596 } SQ_IND_CMD_MODE; 13597 13598 /* 13599 * SQ_EDC_INFO_SOURCE enum 13600 */ 13601 13602 typedef enum SQ_EDC_INFO_SOURCE { 13603 SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, 13604 SQ_EDC_INFO_SOURCE_INST = 0x00000001, 13605 SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, 13606 SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, 13607 SQ_EDC_INFO_SOURCE_LDS = 0x00000004, 13608 SQ_EDC_INFO_SOURCE_GDS = 0x00000005, 13609 SQ_EDC_INFO_SOURCE_TA = 0x00000006, 13610 } SQ_EDC_INFO_SOURCE; 13611 13612 /* 13613 * SQ_ROUND_MODE enum 13614 */ 13615 13616 typedef enum SQ_ROUND_MODE { 13617 SQ_ROUND_NEAREST_EVEN = 0x00000000, 13618 SQ_ROUND_PLUS_INFINITY = 0x00000001, 13619 SQ_ROUND_MINUS_INFINITY = 0x00000002, 13620 SQ_ROUND_TO_ZERO = 0x00000003, 13621 } SQ_ROUND_MODE; 13622 13623 /* 13624 * SQ_INTERRUPT_WORD_ENCODING enum 13625 */ 13626 13627 typedef enum SQ_INTERRUPT_WORD_ENCODING { 13628 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000, 13629 SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001, 13630 SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002, 13631 } SQ_INTERRUPT_WORD_ENCODING; 13632 13633 /* 13634 * SQ_IBUF_ST enum 13635 */ 13636 13637 typedef enum SQ_IBUF_ST { 13638 SQ_IBUF_IB_IDLE = 0x00000000, 13639 SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, 13640 SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, 13641 SQ_IBUF_IB_LE_4DW = 0x00000003, 13642 SQ_IBUF_IB_WAIT_DRET = 0x00000004, 13643 SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, 13644 SQ_IBUF_IB_DRET = 0x00000006, 13645 SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, 13646 } SQ_IBUF_ST; 13647 13648 /* 13649 * SQ_INST_STR_ST enum 13650 */ 13651 13652 typedef enum SQ_INST_STR_ST { 13653 SQ_INST_STR_IB_WAVE_NORML = 0x00000000, 13654 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, 13655 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, 13656 SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, 13657 SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004, 13658 SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005, 13659 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006, 13660 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007, 13661 } SQ_INST_STR_ST; 13662 13663 /* 13664 * SQ_WAVE_IB_ECC_ST enum 13665 */ 13666 13667 typedef enum SQ_WAVE_IB_ECC_ST { 13668 SQ_WAVE_IB_ECC_CLEAN = 0x00000000, 13669 SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001, 13670 SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002, 13671 SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003, 13672 } SQ_WAVE_IB_ECC_ST; 13673 13674 /* 13675 * SH_MEM_ADDRESS_MODE enum 13676 */ 13677 13678 typedef enum SH_MEM_ADDRESS_MODE { 13679 SH_MEM_ADDRESS_MODE_64 = 0x00000000, 13680 SH_MEM_ADDRESS_MODE_32 = 0x00000001, 13681 } SH_MEM_ADDRESS_MODE; 13682 13683 /* 13684 * SH_MEM_RETRY_MODE enum 13685 */ 13686 13687 typedef enum SH_MEM_RETRY_MODE { 13688 SH_MEM_RETRY_MODE_ALL = 0x00000000, 13689 SH_MEM_RETRY_MODE_WRITEATOMIC = 0x00000001, 13690 SH_MEM_RETRY_MODE_NONE = 0x00000002, 13691 } SH_MEM_RETRY_MODE; 13692 13693 /* 13694 * SH_MEM_ALIGNMENT_MODE enum 13695 */ 13696 13697 typedef enum SH_MEM_ALIGNMENT_MODE { 13698 SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, 13699 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, 13700 SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, 13701 SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, 13702 } SH_MEM_ALIGNMENT_MODE; 13703 13704 /* 13705 * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum 13706 */ 13707 13708 typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT { 13709 SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0x00000000, 13710 SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 0x00000001, 13711 SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 0x00000002, 13712 SQ_TT_TOKEN_MASK_COMP_SHIFT = 0x00000003, 13713 SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 0x00000004, 13714 SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 0x00000005, 13715 SQ_TT_TOKEN_MASK_OTHER_SHIFT = 0x00000006, 13716 SQ_TT_TOKEN_MASK_READS_SHIFT = 0x00000007, 13717 } SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT; 13718 13719 /* 13720 * SQ_TT_TOKEN_MASK_REG_INCLUDE enum 13721 */ 13722 13723 typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE { 13724 SQ_TT_TOKEN_MASK_SQDEC_BIT = 0x00000001, 13725 SQ_TT_TOKEN_MASK_SHDEC_BIT = 0x00000002, 13726 SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 0x00000004, 13727 SQ_TT_TOKEN_MASK_COMP_BIT = 0x00000008, 13728 SQ_TT_TOKEN_MASK_CONTEXT_BIT = 0x00000010, 13729 SQ_TT_TOKEN_MASK_CONFIG_BIT = 0x00000020, 13730 SQ_TT_TOKEN_MASK_OTHER_BIT = 0x00000040, 13731 SQ_TT_TOKEN_MASK_READS_BIT = 0x00000080, 13732 } SQ_TT_TOKEN_MASK_REG_INCLUDE; 13733 13734 /* 13735 * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum 13736 */ 13737 13738 typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT { 13739 SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0x00000000, 13740 SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 0x00000001, 13741 SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 0x00000002, 13742 SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 0x00000003, 13743 SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT = 0x00000004, 13744 SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 0x00000005, 13745 SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 0x00000006, 13746 SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 0x00000007, 13747 SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 0x00000008, 13748 SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 0x00000009, 13749 SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 0x0000000a, 13750 SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 0x0000000b, 13751 } SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT; 13752 13753 /* 13754 * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum 13755 */ 13756 13757 typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE { 13758 SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD = 0x00000000, 13759 SQ_TT_INST_EXCLUDE_EXPGNT234 = 0x00000001, 13760 } SQ_TT_TOKEN_MASK_INST_EXCLUDE; 13761 13762 /* 13763 * SQ_TT_MODE enum 13764 */ 13765 13766 typedef enum SQ_TT_MODE { 13767 SQ_TT_MODE_OFF = 0x00000000, 13768 SQ_TT_MODE_ON = 0x00000001, 13769 SQ_TT_MODE_GLOBAL = 0x00000002, 13770 SQ_TT_MODE_DETAIL = 0x00000003, 13771 } SQ_TT_MODE; 13772 13773 /* 13774 * SQ_TT_WTYPE_INCLUDE_SHIFT enum 13775 */ 13776 13777 typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT { 13778 SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0x00000000, 13779 SQ_TT_WTYPE_INCLUDE_VS_SHIFT = 0x00000001, 13780 SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 0x00000002, 13781 SQ_TT_WTYPE_INCLUDE_ES_SHIFT = 0x00000003, 13782 SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 0x00000004, 13783 SQ_TT_WTYPE_INCLUDE_LS_SHIFT = 0x00000005, 13784 SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 0x00000006, 13785 } SQ_TT_WTYPE_INCLUDE_SHIFT; 13786 13787 /* 13788 * SQ_TT_WTYPE_INCLUDE enum 13789 */ 13790 13791 typedef enum SQ_TT_WTYPE_INCLUDE { 13792 SQ_TT_WTYPE_INCLUDE_PS_BIT = 0x00000001, 13793 SQ_TT_WTYPE_INCLUDE_VS_BIT = 0x00000002, 13794 SQ_TT_WTYPE_INCLUDE_GS_BIT = 0x00000004, 13795 SQ_TT_WTYPE_INCLUDE_ES_BIT = 0x00000008, 13796 SQ_TT_WTYPE_INCLUDE_HS_BIT = 0x00000010, 13797 SQ_TT_WTYPE_INCLUDE_LS_BIT = 0x00000020, 13798 SQ_TT_WTYPE_INCLUDE_CS_BIT = 0x00000040, 13799 } SQ_TT_WTYPE_INCLUDE; 13800 13801 /* 13802 * SQ_TT_UTIL_TIMER enum 13803 */ 13804 13805 typedef enum SQ_TT_UTIL_TIMER { 13806 SQ_TT_UTIL_TIMER_100_CLK = 0x00000000, 13807 SQ_TT_UTIL_TIMER_250_CLK = 0x00000001, 13808 } SQ_TT_UTIL_TIMER; 13809 13810 /* 13811 * SQ_TT_WAVESTART_MODE enum 13812 */ 13813 13814 typedef enum SQ_TT_WAVESTART_MODE { 13815 SQ_TT_WAVESTART_MODE_SHORT = 0x00000000, 13816 SQ_TT_WAVESTART_MODE_ALLOC = 0x00000001, 13817 SQ_TT_WAVESTART_MODE_PBB_ID = 0x00000002, 13818 } SQ_TT_WAVESTART_MODE; 13819 13820 /* 13821 * SQ_TT_RT_FREQ enum 13822 */ 13823 13824 typedef enum SQ_TT_RT_FREQ { 13825 SQ_TT_RT_FREQ_NEVER = 0x00000000, 13826 SQ_TT_RT_FREQ_1024_CLK = 0x00000001, 13827 SQ_TT_RT_FREQ_4096_CLK = 0x00000002, 13828 } SQ_TT_RT_FREQ; 13829 13830 /* 13831 * SQ_WATCH_MODES enum 13832 */ 13833 13834 typedef enum SQ_WATCH_MODES { 13835 SQ_WATCH_MODE_READ = 0x00000000, 13836 SQ_WATCH_MODE_NONREAD = 0x00000001, 13837 SQ_WATCH_MODE_ATOMIC = 0x00000002, 13838 SQ_WATCH_MODE_ALL = 0x00000003, 13839 } SQ_WATCH_MODES; 13840 13841 /* 13842 * SQ_WAVE_SCHED_MODES enum 13843 */ 13844 13845 typedef enum SQ_WAVE_SCHED_MODES { 13846 SQ_WAVE_SCHED_MODE_NORMAL = 0x00000000, 13847 SQ_WAVE_SCHED_MODE_EXPERT = 0x00000001, 13848 SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 0x00000002, 13849 } SQ_WAVE_SCHED_MODES; 13850 13851 /* 13852 * SQ_WAVE_TYPE value 13853 */ 13854 13855 #define SQ_WAVE_TYPE_PS0 0x00000000 13856 13857 /* 13858 * SQIND_PARTITIONS value 13859 */ 13860 13861 #define SQIND_GLOBAL_REGS_OFFSET 0x00000000 13862 #define SQIND_GLOBAL_REGS_SIZE 0x00000008 13863 #define SQIND_LOCAL_REGS_OFFSET 0x00000008 13864 #define SQIND_LOCAL_REGS_SIZE 0x00000008 13865 #define SQIND_WAVE_HWREGS_OFFSET 0x00000100 13866 #define SQIND_WAVE_HWREGS_SIZE 0x00000100 13867 #define SQIND_WAVE_SGPRS_OFFSET 0x00000200 13868 #define SQIND_WAVE_SGPRS_SIZE 0x00000200 13869 #define SQIND_WAVE_VGPRS_OFFSET 0x00000400 13870 #define SQIND_WAVE_VGPRS_SIZE 0x00000400 13871 13872 /* 13873 * SQ_GFXDEC value 13874 */ 13875 13876 #define SQ_GFXDEC_BEGIN 0x0000a000 13877 #define SQ_GFXDEC_END 0x0000c000 13878 #define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a 13879 13880 /* 13881 * SQDEC value 13882 */ 13883 13884 #define SQDEC_BEGIN 0x00002300 13885 #define SQDEC_END 0x000023ff 13886 13887 /* 13888 * SQPERFSDEC value 13889 */ 13890 13891 #define SQPERFSDEC_BEGIN 0x0000d9c0 13892 #define SQPERFSDEC_END 0x0000da40 13893 13894 /* 13895 * SQPERFDDEC value 13896 */ 13897 13898 #define SQPERFDDEC_BEGIN 0x0000d1c0 13899 #define SQPERFDDEC_END 0x0000d240 13900 13901 /* 13902 * SQGFXUDEC value 13903 */ 13904 13905 #define SQGFXUDEC_BEGIN 0x0000c330 13906 #define SQGFXUDEC_END 0x0000c380 13907 13908 /* 13909 * SQPWRDEC value 13910 */ 13911 13912 #define SQPWRDEC_BEGIN 0x0000f08c 13913 #define SQPWRDEC_END 0x0000f094 13914 13915 /* 13916 * SQ_DISPATCHER value 13917 */ 13918 13919 #define SQ_DISPATCHER_GFX_MIN 0x00000010 13920 #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 13921 13922 /* 13923 * SQ_MAX value 13924 */ 13925 13926 #define SQ_MAX_PGM_SGPRS 0x00000068 13927 #define SQ_MAX_PGM_VGPRS 0x00000100 13928 13929 /* 13930 * SQ_EXCP_BITS value 13931 */ 13932 13933 #define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000 13934 #define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007 13935 #define SQ_EX_MODE_EXCP_INVALID 0x00000000 13936 #define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001 13937 #define SQ_EX_MODE_EXCP_DIV0 0x00000002 13938 #define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003 13939 #define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004 13940 #define SQ_EX_MODE_EXCP_INEXACT 0x00000005 13941 #define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006 13942 #define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007 13943 #define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008 13944 13945 /* 13946 * SQ_EXCP_HI_BITS value 13947 */ 13948 13949 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000 13950 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001 13951 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002 13952 13953 /* 13954 * HW_INSERTED_INST_ID value 13955 */ 13956 13957 #define INST_ID_PRIV_START 0x80000000 13958 #define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 13959 #define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 13960 #define INST_ID_HW_TRAP 0xfffffff2 13961 #define INST_ID_KILL_SEQ 0xfffffff3 13962 #define INST_ID_SPI_WREXEC 0xfffffff4 13963 #define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe 13964 13965 /* 13966 * SIMM16_WAITCNT_PARTITIONS value 13967 */ 13968 13969 #define SIMM16_WAITCNT_VM_CNT_START 0x00000000 13970 #define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000004 13971 #define SIMM16_WAITCNT_EXP_CNT_START 0x00000004 13972 #define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003 13973 #define SIMM16_WAITCNT_LGKM_CNT_START 0x00000008 13974 #define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000004 13975 #define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e 13976 #define SIMM16_WAITCNT_VM_CNT_HI_SIZE 0x00000002 13977 #define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000 13978 #define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001 13979 #define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001 13980 #define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001 13981 #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002 13982 #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003 13983 #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000008 13984 #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001 13985 #define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000009 13986 #define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003 13987 #define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000c 13988 #define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000004 13989 13990 /* 13991 * SQ_EDC_FUE_CNTL_BITS value 13992 */ 13993 13994 #define SQ_EDC_FUE_CNTL_SIMD0 0x00000000 13995 #define SQ_EDC_FUE_CNTL_SIMD1 0x00000001 13996 #define SQ_EDC_FUE_CNTL_SIMD2 0x00000002 13997 #define SQ_EDC_FUE_CNTL_SIMD3 0x00000003 13998 #define SQ_EDC_FUE_CNTL_SQ 0x00000004 13999 #define SQ_EDC_FUE_CNTL_LDS 0x00000005 14000 #define SQ_EDC_FUE_CNTL_TD 0x00000006 14001 #define SQ_EDC_FUE_CNTL_TA 0x00000007 14002 #define SQ_EDC_FUE_CNTL_TCP 0x00000008 14003 14004 /******************************************************* 14005 * COMP Enums 14006 *******************************************************/ 14007 14008 /* 14009 * CSDATA_TYPE enum 14010 */ 14011 14012 typedef enum CSDATA_TYPE { 14013 CSDATA_TYPE_TG = 0x00000000, 14014 CSDATA_TYPE_STATE = 0x00000001, 14015 CSDATA_TYPE_EVENT = 0x00000002, 14016 CSDATA_TYPE_PRIVATE = 0x00000003, 14017 } CSDATA_TYPE; 14018 14019 /* 14020 * CSCNTL_TYPE enum 14021 */ 14022 14023 typedef enum CSCNTL_TYPE { 14024 CSCNTL_TYPE_TG = 0x00000000, 14025 CSCNTL_TYPE_STATE = 0x00000001, 14026 CSCNTL_TYPE_EVENT = 0x00000002, 14027 CSCNTL_TYPE_PRIVATE = 0x00000003, 14028 } CSCNTL_TYPE; 14029 14030 /* 14031 * CSDATA_TYPE_WIDTH value 14032 */ 14033 14034 #define CSDATA_TYPE_WIDTH 0x00000002 14035 14036 /* 14037 * CSDATA_ADDR_WIDTH value 14038 */ 14039 14040 #define CSDATA_ADDR_WIDTH 0x00000007 14041 14042 /* 14043 * CSDATA_DATA_WIDTH value 14044 */ 14045 14046 #define CSDATA_DATA_WIDTH 0x00000020 14047 14048 /* 14049 * CSCNTL_TYPE_WIDTH value 14050 */ 14051 14052 #define CSCNTL_TYPE_WIDTH 0x00000002 14053 14054 /* 14055 * CSCNTL_ADDR_WIDTH value 14056 */ 14057 14058 #define CSCNTL_ADDR_WIDTH 0x00000007 14059 14060 /* 14061 * CSCNTL_DATA_WIDTH value 14062 */ 14063 14064 #define CSCNTL_DATA_WIDTH 0x00000020 14065 14066 /******************************************************* 14067 * GE Enums 14068 *******************************************************/ 14069 14070 /* 14071 * VGT_OUT_PRIM_TYPE enum 14072 */ 14073 14074 typedef enum VGT_OUT_PRIM_TYPE { 14075 VGT_OUT_POINT = 0x00000000, 14076 VGT_OUT_LINE = 0x00000001, 14077 VGT_OUT_TRI = 0x00000002, 14078 VGT_OUT_RECT_V0 = 0x00000003, 14079 VGT_OUT_RECT_V1 = 0x00000004, 14080 VGT_OUT_RECT_V2 = 0x00000005, 14081 VGT_OUT_RECT_V3 = 0x00000006, 14082 VGT_OUT_2D_RECT = 0x00000007, 14083 VGT_TE_QUAD = 0x00000008, 14084 VGT_TE_PRIM_INDEX_LINE = 0x00000009, 14085 VGT_TE_PRIM_INDEX_TRI = 0x0000000a, 14086 VGT_TE_PRIM_INDEX_QUAD = 0x0000000b, 14087 VGT_OUT_LINE_ADJ = 0x0000000c, 14088 VGT_OUT_TRI_ADJ = 0x0000000d, 14089 VGT_OUT_PATCH = 0x0000000e, 14090 } VGT_OUT_PRIM_TYPE; 14091 14092 /* 14093 * VGT_DI_PRIM_TYPE enum 14094 */ 14095 14096 typedef enum VGT_DI_PRIM_TYPE { 14097 DI_PT_NONE = 0x00000000, 14098 DI_PT_POINTLIST = 0x00000001, 14099 DI_PT_LINELIST = 0x00000002, 14100 DI_PT_LINESTRIP = 0x00000003, 14101 DI_PT_TRILIST = 0x00000004, 14102 DI_PT_TRIFAN = 0x00000005, 14103 DI_PT_TRISTRIP = 0x00000006, 14104 DI_PT_2D_RECTANGLE = 0x00000007, 14105 DI_PT_UNUSED_1 = 0x00000008, 14106 DI_PT_PATCH = 0x00000009, 14107 DI_PT_LINELIST_ADJ = 0x0000000a, 14108 DI_PT_LINESTRIP_ADJ = 0x0000000b, 14109 DI_PT_TRILIST_ADJ = 0x0000000c, 14110 DI_PT_TRISTRIP_ADJ = 0x0000000d, 14111 DI_PT_UNUSED_3 = 0x0000000e, 14112 DI_PT_UNUSED_4 = 0x0000000f, 14113 DI_PT_TRI_WITH_WFLAGS = 0x00000010, 14114 DI_PT_RECTLIST = 0x00000011, 14115 DI_PT_LINELOOP = 0x00000012, 14116 DI_PT_QUADLIST = 0x00000013, 14117 DI_PT_QUADSTRIP = 0x00000014, 14118 DI_PT_POLYGON = 0x00000015, 14119 } VGT_DI_PRIM_TYPE; 14120 14121 /* 14122 * VGT_DI_SOURCE_SELECT enum 14123 */ 14124 14125 typedef enum VGT_DI_SOURCE_SELECT { 14126 DI_SRC_SEL_DMA = 0x00000000, 14127 DI_SRC_SEL_IMMEDIATE = 0x00000001, 14128 DI_SRC_SEL_AUTO_INDEX = 0x00000002, 14129 DI_SRC_SEL_RESERVED = 0x00000003, 14130 } VGT_DI_SOURCE_SELECT; 14131 14132 /* 14133 * VGT_DI_MAJOR_MODE_SELECT enum 14134 */ 14135 14136 typedef enum VGT_DI_MAJOR_MODE_SELECT { 14137 DI_MAJOR_MODE_0 = 0x00000000, 14138 DI_MAJOR_MODE_1 = 0x00000001, 14139 } VGT_DI_MAJOR_MODE_SELECT; 14140 14141 /* 14142 * VGT_DI_INDEX_SIZE enum 14143 */ 14144 14145 typedef enum VGT_DI_INDEX_SIZE { 14146 DI_INDEX_SIZE_16_BIT = 0x00000000, 14147 DI_INDEX_SIZE_32_BIT = 0x00000001, 14148 DI_INDEX_SIZE_8_BIT = 0x00000002, 14149 } VGT_DI_INDEX_SIZE; 14150 14151 /* 14152 * VGT_EVENT_TYPE enum 14153 */ 14154 14155 typedef enum VGT_EVENT_TYPE { 14156 Reserved_0x00 = 0x00000000, 14157 SAMPLE_STREAMOUTSTATS1 = 0x00000001, 14158 SAMPLE_STREAMOUTSTATS2 = 0x00000002, 14159 SAMPLE_STREAMOUTSTATS3 = 0x00000003, 14160 CACHE_FLUSH_TS = 0x00000004, 14161 CONTEXT_DONE = 0x00000005, 14162 CACHE_FLUSH = 0x00000006, 14163 CS_PARTIAL_FLUSH = 0x00000007, 14164 VGT_STREAMOUT_SYNC = 0x00000008, 14165 SET_FE_ID = 0x00000009, 14166 VGT_STREAMOUT_RESET = 0x0000000a, 14167 END_OF_PIPE_INCR_DE = 0x0000000b, 14168 END_OF_PIPE_IB_END = 0x0000000c, 14169 RST_PIX_CNT = 0x0000000d, 14170 BREAK_BATCH = 0x0000000e, 14171 VS_PARTIAL_FLUSH = 0x0000000f, 14172 PS_PARTIAL_FLUSH = 0x00000010, 14173 FLUSH_HS_OUTPUT = 0x00000011, 14174 FLUSH_DFSM = 0x00000012, 14175 RESET_TO_LOWEST_VGT = 0x00000013, 14176 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, 14177 ZPASS_DONE = 0x00000015, 14178 CACHE_FLUSH_AND_INV_EVENT = 0x00000016, 14179 PERFCOUNTER_START = 0x00000017, 14180 PERFCOUNTER_STOP = 0x00000018, 14181 PIPELINESTAT_START = 0x00000019, 14182 PIPELINESTAT_STOP = 0x0000001a, 14183 PERFCOUNTER_SAMPLE = 0x0000001b, 14184 FLUSH_ES_OUTPUT = 0x0000001c, 14185 BIN_CONF_OVERRIDE_CHECK = 0x0000001d, 14186 SAMPLE_PIPELINESTAT = 0x0000001e, 14187 SO_VGTSTREAMOUT_FLUSH = 0x0000001f, 14188 SAMPLE_STREAMOUTSTATS = 0x00000020, 14189 RESET_VTX_CNT = 0x00000021, 14190 BLOCK_CONTEXT_DONE = 0x00000022, 14191 CS_CONTEXT_DONE = 0x00000023, 14192 VGT_FLUSH = 0x00000024, 14193 TGID_ROLLOVER = 0x00000025, 14194 SQ_NON_EVENT = 0x00000026, 14195 SC_SEND_DB_VPZ = 0x00000027, 14196 BOTTOM_OF_PIPE_TS = 0x00000028, 14197 FLUSH_SX_TS = 0x00000029, 14198 DB_CACHE_FLUSH_AND_INV = 0x0000002a, 14199 FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, 14200 FLUSH_AND_INV_DB_META = 0x0000002c, 14201 FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, 14202 FLUSH_AND_INV_CB_META = 0x0000002e, 14203 CS_DONE = 0x0000002f, 14204 PS_DONE = 0x00000030, 14205 FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, 14206 SX_CB_RAT_ACK_REQUEST = 0x00000032, 14207 THREAD_TRACE_START = 0x00000033, 14208 THREAD_TRACE_STOP = 0x00000034, 14209 THREAD_TRACE_MARKER = 0x00000035, 14210 THREAD_TRACE_DRAW = 0x00000036, 14211 THREAD_TRACE_FINISH = 0x00000037, 14212 PIXEL_PIPE_STAT_CONTROL = 0x00000038, 14213 PIXEL_PIPE_STAT_DUMP = 0x00000039, 14214 PIXEL_PIPE_STAT_RESET = 0x0000003a, 14215 CONTEXT_SUSPEND = 0x0000003b, 14216 OFFCHIP_HS_DEALLOC = 0x0000003c, 14217 ENABLE_NGG_PIPELINE = 0x0000003d, 14218 ENABLE_LEGACY_PIPELINE = 0x0000003e, 14219 DRAW_DONE = 0x0000003f, 14220 } VGT_EVENT_TYPE; 14221 14222 /* 14223 * VGT_DMA_SWAP_MODE enum 14224 */ 14225 14226 typedef enum VGT_DMA_SWAP_MODE { 14227 VGT_DMA_SWAP_NONE = 0x00000000, 14228 VGT_DMA_SWAP_16_BIT = 0x00000001, 14229 VGT_DMA_SWAP_32_BIT = 0x00000002, 14230 VGT_DMA_SWAP_WORD = 0x00000003, 14231 } VGT_DMA_SWAP_MODE; 14232 14233 /* 14234 * VGT_INDEX_TYPE_MODE enum 14235 */ 14236 14237 typedef enum VGT_INDEX_TYPE_MODE { 14238 VGT_INDEX_16 = 0x00000000, 14239 VGT_INDEX_32 = 0x00000001, 14240 VGT_INDEX_8 = 0x00000002, 14241 } VGT_INDEX_TYPE_MODE; 14242 14243 /* 14244 * VGT_DMA_BUF_TYPE enum 14245 */ 14246 14247 typedef enum VGT_DMA_BUF_TYPE { 14248 VGT_DMA_BUF_MEM = 0x00000000, 14249 VGT_DMA_BUF_RING = 0x00000001, 14250 VGT_DMA_BUF_SETUP = 0x00000002, 14251 VGT_DMA_PTR_UPDATE = 0x00000003, 14252 } VGT_DMA_BUF_TYPE; 14253 14254 /* 14255 * VGT_OUTPATH_SELECT enum 14256 */ 14257 14258 typedef enum VGT_OUTPATH_SELECT { 14259 VGT_OUTPATH_VTX_REUSE = 0x00000000, 14260 VGT_OUTPATH_GS_BLOCK = 0x00000001, 14261 VGT_OUTPATH_HS_BLOCK = 0x00000002, 14262 VGT_OUTPATH_PRIM_GEN = 0x00000003, 14263 VGT_OUTPATH_TE_PRIM_GEN = 0x00000004, 14264 VGT_OUTPATH_TE_GS_BLOCK = 0x00000005, 14265 VGT_OUTPATH_TE_OUTPUT = 0x00000006, 14266 } VGT_OUTPATH_SELECT; 14267 14268 /* 14269 * VGT_GRP_PRIM_TYPE enum 14270 */ 14271 14272 typedef enum VGT_GRP_PRIM_TYPE { 14273 VGT_GRP_3D_POINT = 0x00000000, 14274 VGT_GRP_3D_LINE = 0x00000001, 14275 VGT_GRP_3D_TRI = 0x00000002, 14276 VGT_GRP_3D_RECT = 0x00000003, 14277 VGT_GRP_3D_QUAD = 0x00000004, 14278 VGT_GRP_2D_COPY_RECT_V0 = 0x00000005, 14279 VGT_GRP_2D_COPY_RECT_V1 = 0x00000006, 14280 VGT_GRP_2D_COPY_RECT_V2 = 0x00000007, 14281 VGT_GRP_2D_COPY_RECT_V3 = 0x00000008, 14282 VGT_GRP_2D_FILL_RECT = 0x00000009, 14283 VGT_GRP_2D_LINE = 0x0000000a, 14284 VGT_GRP_2D_TRI = 0x0000000b, 14285 VGT_GRP_PRIM_INDEX_LINE = 0x0000000c, 14286 VGT_GRP_PRIM_INDEX_TRI = 0x0000000d, 14287 VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e, 14288 VGT_GRP_3D_LINE_ADJ = 0x0000000f, 14289 VGT_GRP_3D_TRI_ADJ = 0x00000010, 14290 VGT_GRP_3D_PATCH = 0x00000011, 14291 VGT_GRP_2D_RECT = 0x00000012, 14292 } VGT_GRP_PRIM_TYPE; 14293 14294 /* 14295 * VGT_GRP_PRIM_ORDER enum 14296 */ 14297 14298 typedef enum VGT_GRP_PRIM_ORDER { 14299 VGT_GRP_LIST = 0x00000000, 14300 VGT_GRP_STRIP = 0x00000001, 14301 VGT_GRP_FAN = 0x00000002, 14302 VGT_GRP_LOOP = 0x00000003, 14303 VGT_GRP_POLYGON = 0x00000004, 14304 } VGT_GRP_PRIM_ORDER; 14305 14306 /* 14307 * VGT_GROUP_CONV_SEL enum 14308 */ 14309 14310 typedef enum VGT_GROUP_CONV_SEL { 14311 VGT_GRP_INDEX_16 = 0x00000000, 14312 VGT_GRP_INDEX_32 = 0x00000001, 14313 VGT_GRP_UINT_16 = 0x00000002, 14314 VGT_GRP_UINT_32 = 0x00000003, 14315 VGT_GRP_SINT_16 = 0x00000004, 14316 VGT_GRP_SINT_32 = 0x00000005, 14317 VGT_GRP_FLOAT_32 = 0x00000006, 14318 VGT_GRP_AUTO_PRIM = 0x00000007, 14319 VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, 14320 } VGT_GROUP_CONV_SEL; 14321 14322 /* 14323 * VGT_GS_MODE_TYPE enum 14324 */ 14325 14326 typedef enum VGT_GS_MODE_TYPE { 14327 GS_OFF = 0x00000000, 14328 GS_SCENARIO_A = 0x00000001, 14329 GS_SCENARIO_B = 0x00000002, 14330 GS_SCENARIO_G = 0x00000003, 14331 GS_SCENARIO_C = 0x00000004, 14332 SPRITE_EN = 0x00000005, 14333 } VGT_GS_MODE_TYPE; 14334 14335 /* 14336 * VGT_GS_CUT_MODE enum 14337 */ 14338 14339 typedef enum VGT_GS_CUT_MODE { 14340 GS_CUT_1024 = 0x00000000, 14341 GS_CUT_512 = 0x00000001, 14342 GS_CUT_256 = 0x00000002, 14343 GS_CUT_128 = 0x00000003, 14344 } VGT_GS_CUT_MODE; 14345 14346 /* 14347 * VGT_GS_OUTPRIM_TYPE enum 14348 */ 14349 14350 typedef enum VGT_GS_OUTPRIM_TYPE { 14351 POINTLIST = 0x00000000, 14352 LINESTRIP = 0x00000001, 14353 TRISTRIP = 0x00000002, 14354 RECTLIST = 0x00000003, 14355 } VGT_GS_OUTPRIM_TYPE; 14356 14357 /* 14358 * VGT_CACHE_INVALID_MODE enum 14359 */ 14360 14361 typedef enum VGT_CACHE_INVALID_MODE { 14362 VC_ONLY = 0x00000000, 14363 TC_ONLY = 0x00000001, 14364 VC_AND_TC = 0x00000002, 14365 } VGT_CACHE_INVALID_MODE; 14366 14367 /* 14368 * VGT_TESS_TYPE enum 14369 */ 14370 14371 typedef enum VGT_TESS_TYPE { 14372 TESS_ISOLINE = 0x00000000, 14373 TESS_TRIANGLE = 0x00000001, 14374 TESS_QUAD = 0x00000002, 14375 } VGT_TESS_TYPE; 14376 14377 /* 14378 * VGT_TESS_PARTITION enum 14379 */ 14380 14381 typedef enum VGT_TESS_PARTITION { 14382 PART_INTEGER = 0x00000000, 14383 PART_POW2 = 0x00000001, 14384 PART_FRAC_ODD = 0x00000002, 14385 PART_FRAC_EVEN = 0x00000003, 14386 } VGT_TESS_PARTITION; 14387 14388 /* 14389 * VGT_TESS_TOPOLOGY enum 14390 */ 14391 14392 typedef enum VGT_TESS_TOPOLOGY { 14393 OUTPUT_POINT = 0x00000000, 14394 OUTPUT_LINE = 0x00000001, 14395 OUTPUT_TRIANGLE_CW = 0x00000002, 14396 OUTPUT_TRIANGLE_CCW = 0x00000003, 14397 } VGT_TESS_TOPOLOGY; 14398 14399 /* 14400 * VGT_RDREQ_POLICY enum 14401 */ 14402 14403 typedef enum VGT_RDREQ_POLICY { 14404 VGT_POLICY_LRU = 0x00000000, 14405 VGT_POLICY_STREAM = 0x00000001, 14406 VGT_POLICY_BYPASS = 0x00000002, 14407 } VGT_RDREQ_POLICY; 14408 14409 /* 14410 * VGT_DIST_MODE enum 14411 */ 14412 14413 typedef enum VGT_DIST_MODE { 14414 NO_DIST = 0x00000000, 14415 PATCHES = 0x00000001, 14416 DONUTS = 0x00000002, 14417 TRAPEZOIDS = 0x00000003, 14418 } VGT_DIST_MODE; 14419 14420 /* 14421 * VGT_DETECT_ONE enum 14422 */ 14423 14424 typedef enum VGT_DETECT_ONE { 14425 PRE_CLAMP_TF1 = 0x00000000, 14426 POST_CLAMP_TF1 = 0x00000001, 14427 DISABLE_TF1 = 0x00000002, 14428 } VGT_DETECT_ONE; 14429 14430 /* 14431 * VGT_DETECT_ZERO enum 14432 */ 14433 14434 typedef enum VGT_DETECT_ZERO { 14435 PRE_CLAMP_TF0 = 0x00000000, 14436 POST_CLAMP_TF0 = 0x00000001, 14437 DISABLE_TF0 = 0x00000002, 14438 } VGT_DETECT_ZERO; 14439 14440 /* 14441 * VGT_STAGES_LS_EN enum 14442 */ 14443 14444 typedef enum VGT_STAGES_LS_EN { 14445 LS_STAGE_OFF = 0x00000000, 14446 LS_STAGE_ON = 0x00000001, 14447 CS_STAGE_ON = 0x00000002, 14448 RESERVED_LS = 0x00000003, 14449 } VGT_STAGES_LS_EN; 14450 14451 /* 14452 * VGT_STAGES_HS_EN enum 14453 */ 14454 14455 typedef enum VGT_STAGES_HS_EN { 14456 HS_STAGE_OFF = 0x00000000, 14457 HS_STAGE_ON = 0x00000001, 14458 } VGT_STAGES_HS_EN; 14459 14460 /* 14461 * VGT_STAGES_ES_EN enum 14462 */ 14463 14464 typedef enum VGT_STAGES_ES_EN { 14465 ES_STAGE_OFF = 0x00000000, 14466 ES_STAGE_DS = 0x00000001, 14467 ES_STAGE_REAL = 0x00000002, 14468 RESERVED_ES = 0x00000003, 14469 } VGT_STAGES_ES_EN; 14470 14471 /* 14472 * VGT_STAGES_GS_EN enum 14473 */ 14474 14475 typedef enum VGT_STAGES_GS_EN { 14476 GS_STAGE_OFF = 0x00000000, 14477 GS_STAGE_ON = 0x00000001, 14478 } VGT_STAGES_GS_EN; 14479 14480 /* 14481 * VGT_STAGES_VS_EN enum 14482 */ 14483 14484 typedef enum VGT_STAGES_VS_EN { 14485 VS_STAGE_REAL = 0x00000000, 14486 VS_STAGE_DS = 0x00000001, 14487 VS_STAGE_COPY_SHADER = 0x00000002, 14488 RESERVED_VS = 0x00000003, 14489 } VGT_STAGES_VS_EN; 14490 14491 /* 14492 * GE_PERFCOUNT_SELECT enum 14493 */ 14494 14495 typedef enum GE_PERFCOUNT_SELECT { 14496 ge_assembler_busy = 0x00000000, 14497 ge_assembler_stalled = 0x00000001, 14498 ge_cm_reading_stalled = 0x00000002, 14499 ge_cm_stalled_by_gog = 0x00000003, 14500 ge_cm_stalled_by_gsfetch_done = 0x00000004, 14501 ge_dma_busy = 0x00000005, 14502 ge_dma_lat_bin_0 = 0x00000006, 14503 ge_dma_lat_bin_1 = 0x00000007, 14504 ge_dma_lat_bin_2 = 0x00000008, 14505 ge_dma_lat_bin_3 = 0x00000009, 14506 ge_dma_lat_bin_4 = 0x0000000a, 14507 ge_dma_lat_bin_5 = 0x0000000b, 14508 ge_dma_lat_bin_6 = 0x0000000c, 14509 ge_dma_lat_bin_7 = 0x0000000d, 14510 ge_dma_return = 0x0000000e, 14511 ge_dma_utcl1_consecutive_retry_event = 0x0000000f, 14512 ge_dma_utcl1_request_event = 0x00000010, 14513 ge_dma_utcl1_retry_event = 0x00000011, 14514 ge_dma_utcl1_stall_event = 0x00000012, 14515 ge_dma_utcl1_stall_utcl2_event = 0x00000013, 14516 ge_dma_utcl1_translation_hit_event = 0x00000014, 14517 ge_dma_utcl1_translation_miss_event = 0x00000015, 14518 ge_dma_utcl2_stall_on_trans = 0x00000016, 14519 ge_dma_utcl2_trans_ack = 0x00000017, 14520 ge_dma_utcl2_trans_xnack = 0x00000018, 14521 ge_ds_cache_hits = 0x00000019, 14522 ge_ds_prims = 0x0000001a, 14523 ge_es_done = 0x0000001b, 14524 ge_es_done_latency = 0x0000001c, 14525 ge_es_flush = 0x0000001d, 14526 ge_es_ring_high_water_mark = 0x0000001e, 14527 ge_es_thread_groups = 0x0000001f, 14528 ge_esthread_stalled_es_rb_full = 0x00000020, 14529 ge_esthread_stalled_spi_bp = 0x00000021, 14530 ge_esvert_stalled_es_tbl = 0x00000022, 14531 ge_esvert_stalled_gs_event = 0x00000023, 14532 ge_esvert_stalled_gs_tbl = 0x00000024, 14533 ge_esvert_stalled_gsprim = 0x00000025, 14534 ge_gea_dma_starved = 0x00000026, 14535 ge_gog_busy = 0x00000027, 14536 ge_gog_out_indx_stalled = 0x00000028, 14537 ge_gog_out_prim_stalled = 0x00000029, 14538 ge_gog_vs_tbl_stalled = 0x0000002a, 14539 ge_gs_cache_hits = 0x0000002b, 14540 ge_gs_counters_avail_stalled = 0x0000002c, 14541 ge_gs_done = 0x0000002d, 14542 ge_gs_done_latency = 0x0000002e, 14543 ge_gs_event_stall = 0x0000002f, 14544 ge_gs_issue_rtr_stalled = 0x00000030, 14545 ge_gs_rb_space_avail_stalled = 0x00000031, 14546 ge_gs_ring_high_water_mark = 0x00000032, 14547 ge_gsprim_stalled_es_tbl = 0x00000033, 14548 ge_gsprim_stalled_esvert = 0x00000034, 14549 ge_gsprim_stalled_gs_event = 0x00000035, 14550 ge_gsprim_stalled_gs_tbl = 0x00000036, 14551 ge_gsthread_stalled = 0x00000037, 14552 ge_hs_done = 0x00000038, 14553 ge_hs_done_latency = 0x00000039, 14554 ge_hs_done_se0 = 0x0000003a, 14555 ge_hs_done_se1 = 0x0000003b, 14556 ge_hs_done_se2_reserved = 0x0000003c, 14557 ge_hs_done_se3_reserved = 0x0000003d, 14558 ge_hs_tfm_stall = 0x0000003e, 14559 ge_hs_tgs_active_high_water_mark = 0x0000003f, 14560 ge_hs_thread_groups = 0x00000040, 14561 ge_inside_tf_bin_0 = 0x00000041, 14562 ge_inside_tf_bin_1 = 0x00000042, 14563 ge_inside_tf_bin_2 = 0x00000043, 14564 ge_inside_tf_bin_3 = 0x00000044, 14565 ge_inside_tf_bin_4 = 0x00000045, 14566 ge_inside_tf_bin_5 = 0x00000046, 14567 ge_inside_tf_bin_6 = 0x00000047, 14568 ge_inside_tf_bin_7 = 0x00000048, 14569 ge_inside_tf_bin_8 = 0x00000049, 14570 ge_ls_done = 0x0000004a, 14571 ge_ls_done_latency = 0x0000004b, 14572 ge_null_patch = 0x0000004c, 14573 ge_pa_clipp_eop = 0x0000004d, 14574 ge_pa_clipp_is_event = 0x0000004e, 14575 ge_pa_clipp_new_vtx_vect = 0x0000004f, 14576 ge_pa_clipp_null_prim = 0x00000050, 14577 ge_pa_clipp_send = 0x00000051, 14578 ge_pa_clipp_send_not_event = 0x00000052, 14579 ge_pa_clipp_stalled = 0x00000053, 14580 ge_pa_clipp_starved_busy = 0x00000054, 14581 ge_pa_clipp_starved_idle = 0x00000055, 14582 ge_pa_clipp_valid_prim = 0x00000056, 14583 ge_pa_clips_send = 0x00000057, 14584 ge_pa_clips_stalled = 0x00000058, 14585 ge_pa_clipv_send = 0x00000059, 14586 ge_pa_clipv_stalled = 0x0000005a, 14587 ge_rbiu_di_fifo_stalled = 0x0000005b, 14588 ge_rbiu_di_fifo_starved = 0x0000005c, 14589 ge_rbiu_dr_fifo_stalled = 0x0000005d, 14590 ge_rbiu_dr_fifo_starved = 0x0000005e, 14591 ge_reused_es_indices = 0x0000005f, 14592 ge_reused_vs_indices = 0x00000060, 14593 ge_sclk_core_vld = 0x00000061, 14594 ge_sclk_gs_vld = 0x00000062, 14595 ge_sclk_input_vld = 0x00000063, 14596 ge_sclk_leg_gs_arb_vld = 0x00000064, 14597 ge_sclk_ngg_vld = 0x00000065, 14598 ge_sclk_reg_vld = 0x00000066, 14599 ge_sclk_te11_vld = 0x00000067, 14600 ge_sclk_vr_vld = 0x00000068, 14601 ge_sclk_wd_te11_vld = 0x00000069, 14602 ge_spi_esvert_eov = 0x0000006a, 14603 ge_spi_esvert_stalled = 0x0000006b, 14604 ge_spi_esvert_starved_busy = 0x0000006c, 14605 ge_spi_esvert_valid = 0x0000006d, 14606 ge_spi_eswave_is_event = 0x0000006e, 14607 ge_spi_eswave_send = 0x0000006f, 14608 ge_spi_gsprim_cont = 0x00000070, 14609 ge_spi_gsprim_eov = 0x00000071, 14610 ge_spi_gsprim_stalled = 0x00000072, 14611 ge_spi_gsprim_starved_busy = 0x00000073, 14612 ge_spi_gsprim_starved_idle = 0x00000074, 14613 ge_spi_gsprim_valid = 0x00000075, 14614 ge_spi_gssubgrp_is_event = 0x00000076, 14615 ge_spi_gssubgrp_send = 0x00000077, 14616 ge_spi_gswave_is_event = 0x00000078, 14617 ge_spi_gswave_send = 0x00000079, 14618 ge_spi_hsvert_eov = 0x0000007a, 14619 ge_spi_hsvert_stalled = 0x0000007b, 14620 ge_spi_hsvert_starved_busy = 0x0000007c, 14621 ge_spi_hsvert_valid = 0x0000007d, 14622 ge_spi_hswave_is_event = 0x0000007e, 14623 ge_spi_hswave_send = 0x0000007f, 14624 ge_spi_lsvert_eov = 0x00000080, 14625 ge_spi_lsvert_stalled = 0x00000081, 14626 ge_spi_lsvert_starved_busy = 0x00000082, 14627 ge_spi_lsvert_starved_idle = 0x00000083, 14628 ge_spi_lsvert_valid = 0x00000084, 14629 ge_spi_lswave_is_event = 0x00000085, 14630 ge_spi_lswave_send = 0x00000086, 14631 ge_spi_vsvert_eov = 0x00000087, 14632 ge_spi_vsvert_send = 0x00000088, 14633 ge_spi_vsvert_stalled = 0x00000089, 14634 ge_spi_vsvert_starved_busy = 0x0000008a, 14635 ge_spi_vsvert_starved_idle = 0x0000008b, 14636 ge_spi_vswave_is_event = 0x0000008c, 14637 ge_spi_vswave_send = 0x0000008d, 14638 ge_starved_on_hs_done = 0x0000008e, 14639 ge_stat_busy = 0x0000008f, 14640 ge_stat_combined_busy = 0x00000090, 14641 ge_stat_no_dma_busy = 0x00000091, 14642 ge_strmout_stalled = 0x00000092, 14643 ge_te11_busy = 0x00000093, 14644 ge_te11_starved = 0x00000094, 14645 ge_tfreq_lat_bin_0 = 0x00000095, 14646 ge_tfreq_lat_bin_1 = 0x00000096, 14647 ge_tfreq_lat_bin_2 = 0x00000097, 14648 ge_tfreq_lat_bin_3 = 0x00000098, 14649 ge_tfreq_lat_bin_4 = 0x00000099, 14650 ge_tfreq_lat_bin_5 = 0x0000009a, 14651 ge_tfreq_lat_bin_6 = 0x0000009b, 14652 ge_tfreq_lat_bin_7 = 0x0000009c, 14653 ge_tfreq_utcl1_consecutive_retry_event = 0x0000009d, 14654 ge_tfreq_utcl1_request_event = 0x0000009e, 14655 ge_tfreq_utcl1_retry_event = 0x0000009f, 14656 ge_tfreq_utcl1_stall_event = 0x000000a0, 14657 ge_tfreq_utcl1_stall_utcl2_event = 0x000000a1, 14658 ge_tfreq_utcl1_translation_hit_event = 0x000000a2, 14659 ge_tfreq_utcl1_translation_miss_event = 0x000000a3, 14660 ge_tfreq_utcl2_stall_on_trans = 0x000000a4, 14661 ge_tfreq_utcl2_trans_ack = 0x000000a5, 14662 ge_tfreq_utcl2_trans_xnack = 0x000000a6, 14663 ge_vs_cache_hits = 0x000000a7, 14664 ge_vs_done = 0x000000a8, 14665 ge_vs_pc_stall = 0x000000a9, 14666 ge_vs_table_high_water_mark = 0x000000aa, 14667 ge_vs_thread_groups = 0x000000ab, 14668 ge_vsvert_api_send = 0x000000ac, 14669 ge_vsvert_ds_send = 0x000000ad, 14670 ge_wait_for_es_done_stalled = 0x000000ae, 14671 ge_waveid_stalled = 0x000000af, 14672 } GE_PERFCOUNT_SELECT; 14673 14674 /* 14675 * WD_IA_DRAW_TYPE enum 14676 */ 14677 14678 typedef enum WD_IA_DRAW_TYPE { 14679 WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, 14680 WD_IA_DRAW_TYPE_REG_XFER = 0x00000001, 14681 WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, 14682 WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, 14683 WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004, 14684 WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005, 14685 WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006, 14686 WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, 14687 } WD_IA_DRAW_TYPE; 14688 14689 /* 14690 * WD_IA_DRAW_REG_XFER enum 14691 */ 14692 14693 typedef enum WD_IA_DRAW_REG_XFER { 14694 WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000, 14695 WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001, 14696 WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000002, 14697 WD_IA_DRAW_REG_XFER_GE_CNTL = 0x00000003, 14698 } WD_IA_DRAW_REG_XFER; 14699 14700 /* 14701 * WD_IA_DRAW_SOURCE enum 14702 */ 14703 14704 typedef enum WD_IA_DRAW_SOURCE { 14705 WD_IA_DRAW_SOURCE_DMA = 0x00000000, 14706 WD_IA_DRAW_SOURCE_IMMD = 0x00000001, 14707 WD_IA_DRAW_SOURCE_AUTO = 0x00000002, 14708 WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, 14709 } WD_IA_DRAW_SOURCE; 14710 14711 /* 14712 * GS_THREADID_SIZE value 14713 */ 14714 14715 #define GSTHREADID_SIZE 0x00000002 14716 14717 /******************************************************* 14718 * GB Enums 14719 *******************************************************/ 14720 14721 /* 14722 * GB_EDC_DED_MODE enum 14723 */ 14724 14725 typedef enum GB_EDC_DED_MODE { 14726 GB_EDC_DED_MODE_LOG = 0x00000000, 14727 GB_EDC_DED_MODE_HALT = 0x00000001, 14728 GB_EDC_DED_MODE_INT_HALT = 0x00000002, 14729 } GB_EDC_DED_MODE; 14730 14731 /******************************************************* 14732 * GLX Enums 14733 *******************************************************/ 14734 14735 /* 14736 * CHA_PERF_SEL enum 14737 */ 14738 14739 typedef enum CHA_PERF_SEL { 14740 CHA_PERF_SEL_BUSY = 0x00000000, 14741 CHA_PERF_SEL_STALL_CHC0 = 0x00000001, 14742 CHA_PERF_SEL_STALL_CHC1 = 0x00000002, 14743 CHA_PERF_SEL_STALL_CHC2 = 0x00000003, 14744 CHA_PERF_SEL_STALL_CHC3 = 0x00000004, 14745 CHA_PERF_SEL_STALL_CHC4 = 0x00000005, 14746 CHA_PERF_SEL_REQUEST_CHC0 = 0x00000006, 14747 CHA_PERF_SEL_REQUEST_CHC1 = 0x00000007, 14748 CHA_PERF_SEL_REQUEST_CHC2 = 0x00000008, 14749 CHA_PERF_SEL_REQUEST_CHC3 = 0x00000009, 14750 CHA_PERF_SEL_REQUEST_CHC4 = 0x0000000a, 14751 CHA_PERF_SEL_REQUEST_CHC5 = 0x0000000b, 14752 CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 0x0000000c, 14753 CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 0x0000000d, 14754 CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 0x0000000e, 14755 CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 0x0000000f, 14756 CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 0x00000010, 14757 CHA_PERF_SEL_IO_32B_WDS_CHC0 = 0x00000011, 14758 CHA_PERF_SEL_IO_32B_WDS_CHC1 = 0x00000012, 14759 CHA_PERF_SEL_IO_32B_WDS_CHC2 = 0x00000013, 14760 CHA_PERF_SEL_IO_32B_WDS_CHC3 = 0x00000014, 14761 CHA_PERF_SEL_IO_32B_WDS_CHC4 = 0x00000015, 14762 CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 0x00000016, 14763 CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 0x00000017, 14764 CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 0x00000018, 14765 CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 0x00000019, 14766 CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 0x0000001a, 14767 CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 0x0000001b, 14768 CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 0x0000001c, 14769 CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 0x0000001d, 14770 CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 0x0000001e, 14771 CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 0x0000001f, 14772 CHA_PERF_SEL_ARB_REQUESTS = 0x00000020, 14773 CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000021, 14774 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 0x00000022, 14775 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 0x00000023, 14776 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 0x00000024, 14777 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 0x00000025, 14778 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 0x00000026, 14779 CHA_PERF_SEL_CYCLE = 0x00000027, 14780 } CHA_PERF_SEL; 14781 14782 /* 14783 * CHC_PERF_SEL enum 14784 */ 14785 14786 typedef enum CHC_PERF_SEL { 14787 CHC_PERF_SEL_GATE_EN1 = 0x00000000, 14788 CHC_PERF_SEL_GATE_EN2 = 0x00000001, 14789 CHC_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002, 14790 CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 0x00000003, 14791 CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 0x00000004, 14792 CHC_PERF_SEL_CYCLE = 0x00000005, 14793 CHC_PERF_SEL_REQ = 0x00000006, 14794 } CHC_PERF_SEL; 14795 14796 /* 14797 * CHCG_PERF_SEL enum 14798 */ 14799 14800 typedef enum CHCG_PERF_SEL { 14801 CHCG_PERF_SEL_GATE_EN1 = 0x00000000, 14802 CHCG_PERF_SEL_GATE_EN2 = 0x00000001, 14803 CHCG_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002, 14804 CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 0x00000003, 14805 CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 0x00000004, 14806 CHCG_PERF_SEL_CYCLE = 0x00000005, 14807 CHCG_PERF_SEL_REQ = 0x00000006, 14808 } CHCG_PERF_SEL; 14809 14810 /* 14811 * GL1A_PERF_SEL enum 14812 */ 14813 14814 typedef enum GL1A_PERF_SEL { 14815 GL1A_PERF_SEL_BUSY = 0x00000000, 14816 GL1A_PERF_SEL_STALL_GL1C0 = 0x00000001, 14817 GL1A_PERF_SEL_STALL_GL1C1 = 0x00000002, 14818 GL1A_PERF_SEL_STALL_GL1C2 = 0x00000003, 14819 GL1A_PERF_SEL_STALL_GL1C3 = 0x00000004, 14820 GL1A_PERF_SEL_STALL_GL1C4 = 0x00000005, 14821 GL1A_PERF_SEL_REQUEST_GL1C0 = 0x00000006, 14822 GL1A_PERF_SEL_REQUEST_GL1C1 = 0x00000007, 14823 GL1A_PERF_SEL_REQUEST_GL1C2 = 0x00000008, 14824 GL1A_PERF_SEL_REQUEST_GL1C3 = 0x00000009, 14825 GL1A_PERF_SEL_REQUEST_GL1C4 = 0x0000000a, 14826 GL1A_PERF_SEL_MEM_32B_WDS_GL1C0 = 0x0000000b, 14827 GL1A_PERF_SEL_MEM_32B_WDS_GL1C1 = 0x0000000c, 14828 GL1A_PERF_SEL_MEM_32B_WDS_GL1C2 = 0x0000000d, 14829 GL1A_PERF_SEL_MEM_32B_WDS_GL1C3 = 0x0000000e, 14830 GL1A_PERF_SEL_MEM_32B_WDS_GL1C4 = 0x0000000f, 14831 GL1A_PERF_SEL_IO_32B_WDS_GL1C0 = 0x00000010, 14832 GL1A_PERF_SEL_IO_32B_WDS_GL1C1 = 0x00000011, 14833 GL1A_PERF_SEL_IO_32B_WDS_GL1C2 = 0x00000012, 14834 GL1A_PERF_SEL_IO_32B_WDS_GL1C3 = 0x00000013, 14835 GL1A_PERF_SEL_IO_32B_WDS_GL1C4 = 0x00000014, 14836 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0 = 0x00000015, 14837 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1 = 0x00000016, 14838 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2 = 0x00000017, 14839 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3 = 0x00000018, 14840 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4 = 0x00000019, 14841 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0 = 0x0000001a, 14842 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1 = 0x0000001b, 14843 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2 = 0x0000001c, 14844 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3 = 0x0000001d, 14845 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4 = 0x0000001e, 14846 GL1A_PERF_SEL_ARB_REQUESTS = 0x0000001f, 14847 GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000020, 14848 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 0x00000021, 14849 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 0x00000022, 14850 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 0x00000023, 14851 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 0x00000024, 14852 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4 = 0x00000025, 14853 GL1A_PERF_SEL_CYCLE = 0x00000026, 14854 } GL1A_PERF_SEL; 14855 14856 /* 14857 * GL1C_PERF_SEL enum 14858 */ 14859 14860 typedef enum GL1C_PERF_SEL { 14861 GL1C_PERF_SEL_GATE_EN1 = 0x00000000, 14862 GL1C_PERF_SEL_GATE_EN2 = 0x00000001, 14863 GL1C_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002, 14864 GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 0x00000003, 14865 GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 0x00000004, 14866 GL1C_PERF_SEL_CYCLE = 0x00000005, 14867 GL1C_PERF_SEL_REQ = 0x00000006, 14868 } GL1C_PERF_SEL; 14869 14870 /* 14871 * GL1CG_PERF_SEL enum 14872 */ 14873 14874 typedef enum GL1CG_PERF_SEL { 14875 GL1CG_PERF_SEL_GATE_EN1 = 0x00000000, 14876 GL1CG_PERF_SEL_GATE_EN2 = 0x00000001, 14877 GL1CG_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002, 14878 GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 0x00000003, 14879 GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 0x00000004, 14880 GL1CG_PERF_SEL_CYCLE = 0x00000005, 14881 GL1CG_PERF_SEL_REQ = 0x00000006, 14882 } GL1CG_PERF_SEL; 14883 14884 /******************************************************* 14885 * TP Enums 14886 *******************************************************/ 14887 14888 /* 14889 * TA_TC_REQ_MODES enum 14890 */ 14891 14892 typedef enum TA_TC_REQ_MODES { 14893 TA_TC_REQ_MODE_BORDER = 0x00000000, 14894 TA_TC_REQ_MODE_TEX2 = 0x00000001, 14895 TA_TC_REQ_MODE_TEX1 = 0x00000002, 14896 TA_TC_REQ_MODE_TEX0 = 0x00000003, 14897 TA_TC_REQ_MODE_NORMAL = 0x00000004, 14898 TA_TC_REQ_MODE_DWORD = 0x00000005, 14899 TA_TC_REQ_MODE_BYTE = 0x00000006, 14900 TA_TC_REQ_MODE_BYTE_NV = 0x00000007, 14901 } TA_TC_REQ_MODES; 14902 14903 /* 14904 * TA_TC_ADDR_MODES enum 14905 */ 14906 14907 typedef enum TA_TC_ADDR_MODES { 14908 TA_TC_ADDR_MODE_DEFAULT = 0x00000000, 14909 TA_TC_ADDR_MODE_COMP0 = 0x00000001, 14910 TA_TC_ADDR_MODE_COMP1 = 0x00000002, 14911 TA_TC_ADDR_MODE_COMP2 = 0x00000003, 14912 TA_TC_ADDR_MODE_COMP3 = 0x00000004, 14913 TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, 14914 TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, 14915 } TA_TC_ADDR_MODES; 14916 14917 /* 14918 * TA_PERFCOUNT_SEL enum 14919 */ 14920 14921 typedef enum TA_PERFCOUNT_SEL { 14922 TA_PERF_SEL_NULL = 0x00000000, 14923 TA_PERF_SEL_sh_fifo_busy = 0x00000001, 14924 TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002, 14925 TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003, 14926 TA_PERF_SEL_sh_fifo_data_busy = 0x00000004, 14927 TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005, 14928 TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006, 14929 TA_PERF_SEL_gradient_busy = 0x00000007, 14930 TA_PERF_SEL_gradient_fifo_busy = 0x00000008, 14931 TA_PERF_SEL_lod_busy = 0x00000009, 14932 TA_PERF_SEL_lod_fifo_busy = 0x0000000a, 14933 TA_PERF_SEL_addresser_busy = 0x0000000b, 14934 TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, 14935 TA_PERF_SEL_aligner_busy = 0x0000000d, 14936 TA_PERF_SEL_write_path_busy = 0x0000000e, 14937 TA_PERF_SEL_ta_busy = 0x0000000f, 14938 TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010, 14939 TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011, 14940 TA_PERF_SEL_sp_ta_data_cycles = 0x00000012, 14941 TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013, 14942 TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014, 14943 TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015, 14944 TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016, 14945 TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017, 14946 TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018, 14947 TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019, 14948 TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a, 14949 TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b, 14950 TA_PERF_SEL_ta_sh_fifo_starved = 0x0000001c, 14951 TA_PERF_SEL_RESERVED_29 = 0x0000001d, 14952 TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e, 14953 TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f, 14954 TA_PERF_SEL_total_wavefronts = 0x00000020, 14955 TA_PERF_SEL_gradient_cycles = 0x00000021, 14956 TA_PERF_SEL_walker_cycles = 0x00000022, 14957 TA_PERF_SEL_aligner_cycles = 0x00000023, 14958 TA_PERF_SEL_image_wavefronts = 0x00000024, 14959 TA_PERF_SEL_image_read_wavefronts = 0x00000025, 14960 TA_PERF_SEL_image_write_wavefronts = 0x00000026, 14961 TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, 14962 TA_PERF_SEL_image_total_cycles = 0x00000028, 14963 TA_PERF_SEL_RESERVED_41 = 0x00000029, 14964 TA_PERF_SEL_RESERVED_42 = 0x0000002a, 14965 TA_PERF_SEL_RESERVED_43 = 0x0000002b, 14966 TA_PERF_SEL_buffer_wavefronts = 0x0000002c, 14967 TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d, 14968 TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e, 14969 TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, 14970 TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030, 14971 TA_PERF_SEL_buffer_total_cycles = 0x00000031, 14972 TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032, 14973 TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033, 14974 TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034, 14975 TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035, 14976 TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, 14977 TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, 14978 TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038, 14979 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039, 14980 TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, 14981 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b, 14982 TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, 14983 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, 14984 TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, 14985 TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f, 14986 TA_PERF_SEL_color_1_cycle_pixels = 0x00000040, 14987 TA_PERF_SEL_color_2_cycle_pixels = 0x00000041, 14988 TA_PERF_SEL_color_3_cycle_pixels = 0x00000042, 14989 TA_PERF_SEL_color_4_cycle_pixels = 0x00000043, 14990 TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044, 14991 TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045, 14992 TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046, 14993 TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047, 14994 TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048, 14995 TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, 14996 TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, 14997 TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, 14998 TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, 14999 TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, 15000 TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, 15001 TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, 15002 TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, 15003 TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, 15004 TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, 15005 TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, 15006 TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, 15007 TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, 15008 TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, 15009 TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, 15010 TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, 15011 TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, 15012 TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, 15013 TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, 15014 TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, 15015 TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, 15016 TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, 15017 TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, 15018 TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, 15019 TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, 15020 TA_PERF_SEL_write_path_input_cycles = 0x00000062, 15021 TA_PERF_SEL_write_path_output_cycles = 0x00000063, 15022 TA_PERF_SEL_flat_wavefronts = 0x00000064, 15023 TA_PERF_SEL_flat_read_wavefronts = 0x00000065, 15024 TA_PERF_SEL_flat_write_wavefronts = 0x00000066, 15025 TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067, 15026 TA_PERF_SEL_flat_coalesceable_wavefronts = 0x00000068, 15027 TA_PERF_SEL_reg_sclk_vld = 0x00000069, 15028 TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x0000006a, 15029 TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x0000006b, 15030 TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c, 15031 TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x0000006d, 15032 TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x0000006e, 15033 TA_PERF_SEL_xnack_on_phase0 = 0x0000006f, 15034 TA_PERF_SEL_xnack_on_phase1 = 0x00000070, 15035 TA_PERF_SEL_xnack_on_phase2 = 0x00000071, 15036 TA_PERF_SEL_xnack_on_phase3 = 0x00000072, 15037 TA_PERF_SEL_first_xnack_on_phase0 = 0x00000073, 15038 TA_PERF_SEL_first_xnack_on_phase1 = 0x00000074, 15039 TA_PERF_SEL_first_xnack_on_phase2 = 0x00000075, 15040 TA_PERF_SEL_first_xnack_on_phase3 = 0x00000076, 15041 } TA_PERFCOUNT_SEL; 15042 15043 /* 15044 * TD_PERFCOUNT_SEL enum 15045 */ 15046 15047 typedef enum TD_PERFCOUNT_SEL { 15048 TD_PERF_SEL_none = 0x00000000, 15049 TD_PERF_SEL_td_busy = 0x00000001, 15050 TD_PERF_SEL_input_busy = 0x00000002, 15051 TD_PERF_SEL_sampler_lerp_busy = 0x00000003, 15052 TD_PERF_SEL_sampler_out_busy = 0x00000004, 15053 TD_PERF_SEL_nofilter_busy = 0x00000005, 15054 TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 0x00000006, 15055 TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 0x00000007, 15056 TD_PERF_SEL_RESERVED_8 = 0x00000008, 15057 TD_PERF_SEL_core_state_rams_read = 0x00000009, 15058 TD_PERF_SEL_weight_data_rams_read = 0x0000000a, 15059 TD_PERF_SEL_reference_data_rams_read = 0x0000000b, 15060 TD_PERF_SEL_tc_td_data_fifo_full = 0x0000000c, 15061 TD_PERF_SEL_tc_td_ram_fifo_full = 0x0000000d, 15062 TD_PERF_SEL_input_state_fifo_full = 0x0000000e, 15063 TD_PERF_SEL_ta_data_stall = 0x0000000f, 15064 TD_PERF_SEL_tc_data_stall = 0x00000010, 15065 TD_PERF_SEL_tc_ram_stall = 0x00000011, 15066 TD_PERF_SEL_lds_stall = 0x00000012, 15067 TD_PERF_SEL_sampler_pkr_full = 0x00000013, 15068 TD_PERF_SEL_nofilter_pkr_full = 0x00000014, 15069 TD_PERF_SEL_RESERVED_21 = 0x00000015, 15070 TD_PERF_SEL_gather4_wavefront = 0x00000016, 15071 TD_PERF_SEL_gather4h_wavefront = 0x00000017, 15072 TD_PERF_SEL_gather4h_packed_wavefront = 0x00000018, 15073 TD_PERF_SEL_gather8h_packed_wavefront = 0x00000019, 15074 TD_PERF_SEL_sample_c_wavefront = 0x0000001a, 15075 TD_PERF_SEL_load_wavefront = 0x0000001b, 15076 TD_PERF_SEL_store_wavefront = 0x0000001c, 15077 TD_PERF_SEL_ldfptr_wavefront = 0x0000001d, 15078 TD_PERF_SEL_write_ack_wavefront = 0x0000001e, 15079 TD_PERF_SEL_d16_en_wavefront = 0x0000001f, 15080 TD_PERF_SEL_bypassLerp_wavefront = 0x00000020, 15081 TD_PERF_SEL_min_max_filter_wavefront = 0x00000021, 15082 TD_PERF_SEL_one_comp_wavefront = 0x00000022, 15083 TD_PERF_SEL_two_comp_wavefront = 0x00000023, 15084 TD_PERF_SEL_three_comp_wavefront = 0x00000024, 15085 TD_PERF_SEL_four_comp_wavefront = 0x00000025, 15086 TD_PERF_SEL_user_defined_border = 0x00000026, 15087 TD_PERF_SEL_white_border = 0x00000027, 15088 TD_PERF_SEL_opaque_black_border = 0x00000028, 15089 TD_PERF_SEL_lod_warn_from_ta = 0x00000029, 15090 TD_PERF_SEL_wavefront_dest_is_lds = 0x0000002a, 15091 TD_PERF_SEL_td_cycling_of_nofilter_instr = 0x0000002b, 15092 TD_PERF_SEL_tc_cycling_of_nofilter_instr = 0x0000002c, 15093 TD_PERF_SEL_out_of_order_instr = 0x0000002d, 15094 TD_PERF_SEL_total_num_instr = 0x0000002e, 15095 TD_PERF_SEL_mixmode_instruction = 0x0000002f, 15096 TD_PERF_SEL_mixmode_resource = 0x00000030, 15097 TD_PERF_SEL_status_packet = 0x00000031, 15098 TD_PERF_SEL_address_cmd_poison = 0x00000032, 15099 TD_PERF_SEL_data_poison = 0x00000033, 15100 TD_PERF_SEL_done_scoreboard_not_empty = 0x00000034, 15101 TD_PERF_SEL_done_scoreboard_is_full = 0x00000035, 15102 TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 0x00000036, 15103 TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 0x00000037, 15104 TD_PERF_SEL_nofilter_formatters_turned_off = 0x00000038, 15105 TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 0x00000039, 15106 TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 0x0000003a, 15107 } TD_PERFCOUNT_SEL; 15108 15109 /* 15110 * TCP_PERFCOUNT_SELECT enum 15111 */ 15112 15113 typedef enum TCP_PERFCOUNT_SELECT { 15114 TCP_PERF_SEL_GATE_EN1 = 0x00000000, 15115 TCP_PERF_SEL_GATE_EN2 = 0x00000001, 15116 TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002, 15117 TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x00000003, 15118 TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x00000004, 15119 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x00000005, 15120 TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x00000006, 15121 TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x00000007, 15122 TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x00000008, 15123 TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES = 0x00000009, 15124 TCP_PERF_SEL_LOD_STALL_CYCLES = 0x0000000a, 15125 TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x0000000b, 15126 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x0000000c, 15127 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x0000000d, 15128 TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0x0000000e, 15129 TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x0000000f, 15130 TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0x00000010, 15131 TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0x00000011, 15132 TCP_PERF_SEL_TCR_RDRET_STALL = 0x00000012, 15133 TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0x00000013, 15134 TCP_PERF_SEL_HOLE_READ_STALL = 0x00000014, 15135 TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x00000015, 15136 TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x00000016, 15137 TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x00000017, 15138 TCP_PERF_SEL_POWER_STALL = 0x00000018, 15139 TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL = 0x00000019, 15140 TCP_PERF_SEL_TC_TA_XNACK_STALL = 0x0000001a, 15141 TCP_PERF_SEL_TA_TCP_STATE_READ = 0x0000001b, 15142 TCP_PERF_SEL_TOTAL_ACCESSES = 0x0000001c, 15143 TCP_PERF_SEL_TOTAL_READ = 0x0000001d, 15144 TCP_PERF_SEL_TOTAL_NON_READ = 0x0000001e, 15145 TCP_PERF_SEL_TOTAL_WRITE = 0x0000001f, 15146 TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x00000020, 15147 TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x00000021, 15148 TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x00000022, 15149 TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x00000023, 15150 TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x00000024, 15151 TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x00000025, 15152 TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x00000026, 15153 TCP_PERF_SEL_TOTAL_WBINVL1 = 0x00000027, 15154 TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x00000028, 15155 TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x00000029, 15156 TCP_PERF_SEL_SHOOTDOWN = 0x0000002a, 15157 TCP_PERF_SEL_UTCL0_REQUEST = 0x0000002b, 15158 TCP_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x0000002c, 15159 TCP_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x0000002d, 15160 TCP_PERF_SEL_UTCL0_PERMISSION_MISS = 0x0000002e, 15161 TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x0000002f, 15162 TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000030, 15163 TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x00000031, 15164 TCP_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000032, 15165 TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000033, 15166 TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000034, 15167 TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x00000035, 15168 TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT = 0x00000036, 15169 TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x00000037, 15170 TCP_PERF_SEL_TOTAL_CACHE_ACCESSES = 0x00000038, 15171 TCP_PERF_SEL_TAGRAM0_REQ = 0x00000039, 15172 TCP_PERF_SEL_TAGRAM1_REQ = 0x0000003a, 15173 TCP_PERF_SEL_TAGRAM2_REQ = 0x0000003b, 15174 TCP_PERF_SEL_TAGRAM3_REQ = 0x0000003c, 15175 TCP_PERF_SEL_TCP_LATENCY = 0x0000003d, 15176 TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x0000003e, 15177 TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x0000003f, 15178 TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x00000040, 15179 TCP_PERF_SEL_TCC_READ_REQ = 0x00000041, 15180 TCP_PERF_SEL_TCC_WRITE_REQ = 0x00000042, 15181 TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x00000043, 15182 TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x00000044, 15183 TCP_PERF_SEL_TCC_LRU_REQ = 0x00000045, 15184 TCP_PERF_SEL_TCC_STREAM_REQ = 0x00000046, 15185 TCP_PERF_SEL_TCC_NC_READ_REQ = 0x00000047, 15186 TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x00000048, 15187 TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x00000049, 15188 TCP_PERF_SEL_TCC_UC_READ_REQ = 0x0000004a, 15189 TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0x0000004b, 15190 TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0x0000004c, 15191 TCP_PERF_SEL_TCC_CC_READ_REQ = 0x0000004d, 15192 TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0x0000004e, 15193 TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0x0000004f, 15194 TCP_PERF_SEL_TCC_DCC_REQ = 0x00000050, 15195 TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 0x00000051, 15196 TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 0x00000052, 15197 TCP_PERF_SEL_GL1_REQ_READ = 0x00000053, 15198 TCP_PERF_SEL_GL1_REQ_READ_LATENCY = 0x00000054, 15199 TCP_PERF_SEL_GL1_REQ_WRITE = 0x00000055, 15200 TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY = 0x00000056, 15201 TCP_PERF_SEL_REQ_MISS_TAGRAM0 = 0x00000057, 15202 TCP_PERF_SEL_REQ_MISS_TAGRAM1 = 0x00000058, 15203 TCP_PERF_SEL_REQ_MISS_TAGRAM2 = 0x00000059, 15204 TCP_PERF_SEL_REQ_MISS_TAGRAM3 = 0x0000005a, 15205 TCP_PERF_SEL_TA_REQ = 0x0000005b, 15206 TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 0x0000005c, 15207 TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 0x0000005d, 15208 TCP_PERF_SEL_TA_REQ_READ = 0x0000005e, 15209 TCP_PERF_SEL_TA_REQ_WRITE = 0x0000005f, 15210 TCP_PERF_SEL_TA_REQ_STATE_READ = 0x00000060, 15211 } TCP_PERFCOUNT_SELECT; 15212 15213 /* 15214 * TCP_CACHE_POLICIES enum 15215 */ 15216 15217 typedef enum TCP_CACHE_POLICIES { 15218 TCP_CACHE_POLICY_MISS_LRU = 0x00000000, 15219 TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, 15220 TCP_CACHE_POLICY_HIT_LRU = 0x00000002, 15221 TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, 15222 } TCP_CACHE_POLICIES; 15223 15224 /* 15225 * TCP_CACHE_STORE_POLICIES enum 15226 */ 15227 15228 typedef enum TCP_CACHE_STORE_POLICIES { 15229 TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000, 15230 TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001, 15231 } TCP_CACHE_STORE_POLICIES; 15232 15233 /* 15234 * TCP_WATCH_MODES enum 15235 */ 15236 15237 typedef enum TCP_WATCH_MODES { 15238 TCP_WATCH_MODE_READ = 0x00000000, 15239 TCP_WATCH_MODE_NONREAD = 0x00000001, 15240 TCP_WATCH_MODE_ATOMIC = 0x00000002, 15241 TCP_WATCH_MODE_ALL = 0x00000003, 15242 } TCP_WATCH_MODES; 15243 15244 /* 15245 * TCP_DSM_DATA_SEL enum 15246 */ 15247 15248 typedef enum TCP_DSM_DATA_SEL { 15249 TCP_DSM_DISABLE = 0x00000000, 15250 TCP_DSM_SEL0 = 0x00000001, 15251 TCP_DSM_SEL1 = 0x00000002, 15252 TCP_DSM_SEL_BOTH = 0x00000003, 15253 } TCP_DSM_DATA_SEL; 15254 15255 /* 15256 * TCP_DSM_SINGLE_WRITE enum 15257 */ 15258 15259 typedef enum TCP_DSM_SINGLE_WRITE { 15260 TCP_DSM_SINGLE_WRITE_DIS = 0x00000000, 15261 TCP_DSM_SINGLE_WRITE_EN = 0x00000001, 15262 } TCP_DSM_SINGLE_WRITE; 15263 15264 /* 15265 * TCP_DSM_INJECT_SEL enum 15266 */ 15267 15268 typedef enum TCP_DSM_INJECT_SEL { 15269 TCP_DSM_INJECT_SEL0 = 0x00000000, 15270 TCP_DSM_INJECT_SEL1 = 0x00000001, 15271 TCP_DSM_INJECT_SEL2 = 0x00000002, 15272 TCP_DSM_INJECT_SEL3 = 0x00000003, 15273 } TCP_DSM_INJECT_SEL; 15274 15275 /* 15276 * TCP_OPCODE_TYPE enum 15277 */ 15278 15279 typedef enum TCP_OPCODE_TYPE { 15280 TCP_OPCODE_READ = 0x00000000, 15281 TCP_OPCODE_WRITE = 0x00000001, 15282 TCP_OPCODE_ATOMIC = 0x00000002, 15283 TCP_OPCODE_WBINVL1 = 0x00000003, 15284 TCP_OPCODE_ATOMIC_CMPSWAP = 0x00000004, 15285 TCP_OPCODE_GATHERH = 0x00000005, 15286 } TCP_OPCODE_TYPE; 15287 15288 /******************************************************* 15289 * GL2C Enums 15290 *******************************************************/ 15291 15292 /* 15293 * GL2C_PERF_SEL enum 15294 */ 15295 15296 typedef enum GL2C_PERF_SEL { 15297 GL2C_PERF_SEL_NONE = 0x00000000, 15298 GL2C_PERF_SEL_CYCLE = 0x00000001, 15299 GL2C_PERF_SEL_BUSY = 0x00000002, 15300 GL2C_PERF_SEL_REQ = 0x00000003, 15301 GL2C_PERF_SEL_VOL_REQ = 0x00000004, 15302 GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 0x00000005, 15303 GL2C_PERF_SEL_READ = 0x00000006, 15304 GL2C_PERF_SEL_WRITE = 0x00000007, 15305 GL2C_PERF_SEL_ATOMIC = 0x00000008, 15306 GL2C_PERF_SEL_NOP_ACK = 0x00000009, 15307 GL2C_PERF_SEL_NOP_RTN0 = 0x0000000a, 15308 GL2C_PERF_SEL_PROBE = 0x0000000b, 15309 GL2C_PERF_SEL_PROBE_ALL = 0x0000000c, 15310 GL2C_PERF_SEL_INTERNAL_PROBE = 0x0000000d, 15311 GL2C_PERF_SEL_COMPRESSED_READ_REQ = 0x0000000e, 15312 GL2C_PERF_SEL_METADATA_READ_REQ = 0x0000000f, 15313 GL2C_PERF_SEL_CLIENT0_REQ = 0x00000010, 15314 GL2C_PERF_SEL_CLIENT1_REQ = 0x00000011, 15315 GL2C_PERF_SEL_CLIENT2_REQ = 0x00000012, 15316 GL2C_PERF_SEL_CLIENT3_REQ = 0x00000013, 15317 GL2C_PERF_SEL_CLIENT4_REQ = 0x00000014, 15318 GL2C_PERF_SEL_CLIENT5_REQ = 0x00000015, 15319 GL2C_PERF_SEL_CLIENT6_REQ = 0x00000016, 15320 GL2C_PERF_SEL_CLIENT7_REQ = 0x00000017, 15321 GL2C_PERF_SEL_C_RW_S_REQ = 0x00000018, 15322 GL2C_PERF_SEL_C_RW_US_REQ = 0x00000019, 15323 GL2C_PERF_SEL_C_RO_S_REQ = 0x0000001a, 15324 GL2C_PERF_SEL_C_RO_US_REQ = 0x0000001b, 15325 GL2C_PERF_SEL_UC_REQ = 0x0000001c, 15326 GL2C_PERF_SEL_LRU_REQ = 0x0000001d, 15327 GL2C_PERF_SEL_STREAM_REQ = 0x0000001e, 15328 GL2C_PERF_SEL_BYPASS_REQ = 0x0000001f, 15329 GL2C_PERF_SEL_NOA_REQ = 0x00000020, 15330 GL2C_PERF_SEL_SHARED_REQ = 0x00000021, 15331 GL2C_PERF_SEL_HIT = 0x00000022, 15332 GL2C_PERF_SEL_MISS = 0x00000023, 15333 GL2C_PERF_SEL_FULL_HIT = 0x00000024, 15334 GL2C_PERF_SEL_PARTIAL_32B_HIT = 0x00000025, 15335 GL2C_PERF_SEL_PARTIAL_64B_HIT = 0x00000026, 15336 GL2C_PERF_SEL_PARTIAL_96B_HIT = 0x00000027, 15337 GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000028, 15338 GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000029, 15339 GL2C_PERF_SEL_UNCACHED_WRITE = 0x0000002a, 15340 GL2C_PERF_SEL_WRITEBACK = 0x0000002b, 15341 GL2C_PERF_SEL_NORMAL_WRITEBACK = 0x0000002c, 15342 GL2C_PERF_SEL_EVICT = 0x0000002d, 15343 GL2C_PERF_SEL_NORMAL_EVICT = 0x0000002e, 15344 GL2C_PERF_SEL_PROBE_EVICT = 0x0000002f, 15345 GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 0x00000030, 15346 GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO = 0x00000031, 15347 GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP = 0x00000032, 15348 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 0x00000033, 15349 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 0x00000034, 15350 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 0x00000035, 15351 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 0x00000036, 15352 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 0x00000037, 15353 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 0x00000038, 15354 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 0x00000039, 15355 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 0x0000003a, 15356 GL2C_PERF_SEL_READ_32_REQ = 0x0000003b, 15357 GL2C_PERF_SEL_READ_64_REQ = 0x0000003c, 15358 GL2C_PERF_SEL_READ_128_REQ = 0x0000003d, 15359 GL2C_PERF_SEL_WRITE_32_REQ = 0x0000003e, 15360 GL2C_PERF_SEL_WRITE_64_REQ = 0x0000003f, 15361 GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 0x00000040, 15362 GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 0x00000041, 15363 GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 0x00000042, 15364 GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 0x00000043, 15365 GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 0x00000044, 15366 GL2C_PERF_SEL_MC_WRREQ = 0x00000045, 15367 GL2C_PERF_SEL_EA_WRREQ_64B = 0x00000046, 15368 GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x00000047, 15369 GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 0x00000048, 15370 GL2C_PERF_SEL_MC_WRREQ_STALL = 0x00000049, 15371 GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 0x0000004a, 15372 GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 0x0000004b, 15373 GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x0000004c, 15374 GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x0000004d, 15375 GL2C_PERF_SEL_MC_WRREQ_LEVEL = 0x0000004e, 15376 GL2C_PERF_SEL_EA_ATOMIC = 0x0000004f, 15377 GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 0x00000050, 15378 GL2C_PERF_SEL_MC_RDREQ = 0x00000051, 15379 GL2C_PERF_SEL_EA_RDREQ_SPLIT = 0x00000052, 15380 GL2C_PERF_SEL_EA_RDREQ_32B = 0x00000053, 15381 GL2C_PERF_SEL_EA_RDREQ_64B = 0x00000054, 15382 GL2C_PERF_SEL_EA_RDREQ_96B = 0x00000055, 15383 GL2C_PERF_SEL_EA_RDREQ_128B = 0x00000056, 15384 GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000057, 15385 GL2C_PERF_SEL_EA_RD_MDC_32B = 0x00000058, 15386 GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000059, 15387 GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 0x0000005a, 15388 GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 0x0000005b, 15389 GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x0000005c, 15390 GL2C_PERF_SEL_MC_RDREQ_LEVEL = 0x0000005d, 15391 GL2C_PERF_SEL_EA_RDREQ_DRAM = 0x0000005e, 15392 GL2C_PERF_SEL_EA_WRREQ_DRAM = 0x0000005f, 15393 GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 0x00000060, 15394 GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 0x00000061, 15395 GL2C_PERF_SEL_ONION_READ = 0x00000062, 15396 GL2C_PERF_SEL_ONION_WRITE = 0x00000063, 15397 GL2C_PERF_SEL_IO_READ = 0x00000064, 15398 GL2C_PERF_SEL_IO_WRITE = 0x00000065, 15399 GL2C_PERF_SEL_GARLIC_READ = 0x00000066, 15400 GL2C_PERF_SEL_GARLIC_WRITE = 0x00000067, 15401 GL2C_PERF_SEL_LATENCY_FIFO_FULL = 0x00000068, 15402 GL2C_PERF_SEL_SRC_FIFO_FULL = 0x00000069, 15403 GL2C_PERF_SEL_TAG_STALL = 0x0000006a, 15404 GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000006b, 15405 GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000006c, 15406 GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000006d, 15407 GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000006e, 15408 GL2C_PERF_SEL_TAG_PROBE_STALL = 0x0000006f, 15409 GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000070, 15410 GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 0x00000071, 15411 GL2C_PERF_SEL_TAG_READ_DST_STALL = 0x00000072, 15412 GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000073, 15413 GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000074, 15414 GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000075, 15415 GL2C_PERF_SEL_BUBBLE = 0x00000076, 15416 GL2C_PERF_SEL_IB_REQ = 0x00000077, 15417 GL2C_PERF_SEL_IB_STALL = 0x00000078, 15418 GL2C_PERF_SEL_IB_TAG_STALL = 0x00000079, 15419 GL2C_PERF_SEL_IB_CM_STALL = 0x0000007a, 15420 GL2C_PERF_SEL_RETURN_ACK = 0x0000007b, 15421 GL2C_PERF_SEL_RETURN_DATA = 0x0000007c, 15422 GL2C_PERF_SEL_EA_RDRET_NACK = 0x0000007d, 15423 GL2C_PERF_SEL_EA_WRRET_NACK = 0x0000007e, 15424 GL2C_PERF_SEL_GL2A_LEVEL = 0x0000007f, 15425 GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000080, 15426 GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 0x00000081, 15427 GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x00000082, 15428 GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000083, 15429 GL2C_PERF_SEL_GCR_INV = 0x00000084, 15430 GL2C_PERF_SEL_GCR_WB = 0x00000085, 15431 GL2C_PERF_SEL_GCR_DISCARD = 0x00000086, 15432 GL2C_PERF_SEL_GCR_RANGE = 0x00000087, 15433 GL2C_PERF_SEL_GCR_ALL = 0x00000088, 15434 GL2C_PERF_SEL_GCR_VOL = 0x00000089, 15435 GL2C_PERF_SEL_GCR_UNSHARED = 0x0000008a, 15436 GL2C_PERF_SEL_GCR_MDC_INV = 0x0000008b, 15437 GL2C_PERF_SEL_GCR_GL2_INV_ALL = 0x0000008c, 15438 GL2C_PERF_SEL_GCR_GL2_WB_ALL = 0x0000008d, 15439 GL2C_PERF_SEL_GCR_MDC_INV_ALL = 0x0000008e, 15440 GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 0x0000008f, 15441 GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 0x00000090, 15442 GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 0x00000091, 15443 GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 0x00000092, 15444 GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 0x00000093, 15445 GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 0x00000094, 15446 GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 0x00000095, 15447 GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x00000096, 15448 GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 0x00000097, 15449 GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 0x00000098, 15450 GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 0x00000099, 15451 GL2C_PERF_SEL_GCR_INVL2_VOL_START = 0x0000009a, 15452 GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 0x0000009b, 15453 GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT = 0x0000009c, 15454 GL2C_PERF_SEL_GCR_WBL2_VOL_START = 0x0000009d, 15455 GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 0x0000009e, 15456 GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 0x0000009f, 15457 GL2C_PERF_SEL_GCR_WBINVL2_START = 0x000000a0, 15458 GL2C_PERF_SEL_MDC_INV_METADATA = 0x000000a1, 15459 GL2C_PERF_SEL_MDC_REQ = 0x000000a2, 15460 GL2C_PERF_SEL_MDC_LEVEL = 0x000000a3, 15461 GL2C_PERF_SEL_MDC_TAG_HIT = 0x000000a4, 15462 GL2C_PERF_SEL_MDC_SECTOR_HIT = 0x000000a5, 15463 GL2C_PERF_SEL_MDC_SECTOR_MISS = 0x000000a6, 15464 GL2C_PERF_SEL_MDC_TAG_STALL = 0x000000a7, 15465 GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x000000a8, 15466 GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x000000a9, 15467 GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x000000aa, 15468 GL2C_PERF_SEL_CM_CHANNEL0_REQ = 0x000000ab, 15469 GL2C_PERF_SEL_CM_CHANNEL1_REQ = 0x000000ac, 15470 GL2C_PERF_SEL_CM_CHANNEL2_REQ = 0x000000ad, 15471 GL2C_PERF_SEL_CM_CHANNEL3_REQ = 0x000000ae, 15472 GL2C_PERF_SEL_CM_CHANNEL4_REQ = 0x000000af, 15473 GL2C_PERF_SEL_CM_CHANNEL5_REQ = 0x000000b0, 15474 GL2C_PERF_SEL_CM_CHANNEL6_REQ = 0x000000b1, 15475 GL2C_PERF_SEL_CM_CHANNEL7_REQ = 0x000000b2, 15476 GL2C_PERF_SEL_CM_CHANNEL8_REQ = 0x000000b3, 15477 GL2C_PERF_SEL_CM_CHANNEL9_REQ = 0x000000b4, 15478 GL2C_PERF_SEL_CM_CHANNEL10_REQ = 0x000000b5, 15479 GL2C_PERF_SEL_CM_CHANNEL11_REQ = 0x000000b6, 15480 GL2C_PERF_SEL_CM_CHANNEL12_REQ = 0x000000b7, 15481 GL2C_PERF_SEL_CM_CHANNEL13_REQ = 0x000000b8, 15482 GL2C_PERF_SEL_CM_CHANNEL14_REQ = 0x000000b9, 15483 GL2C_PERF_SEL_CM_CHANNEL15_REQ = 0x000000ba, 15484 GL2C_PERF_SEL_CM_CHANNEL16_REQ = 0x000000bb, 15485 GL2C_PERF_SEL_CM_CHANNEL17_REQ = 0x000000bc, 15486 GL2C_PERF_SEL_CM_CHANNEL18_REQ = 0x000000bd, 15487 GL2C_PERF_SEL_CM_CHANNEL19_REQ = 0x000000be, 15488 GL2C_PERF_SEL_CM_CHANNEL20_REQ = 0x000000bf, 15489 GL2C_PERF_SEL_CM_CHANNEL21_REQ = 0x000000c0, 15490 GL2C_PERF_SEL_CM_CHANNEL22_REQ = 0x000000c1, 15491 GL2C_PERF_SEL_CM_CHANNEL23_REQ = 0x000000c2, 15492 GL2C_PERF_SEL_CM_CHANNEL24_REQ = 0x000000c3, 15493 GL2C_PERF_SEL_CM_CHANNEL25_REQ = 0x000000c4, 15494 GL2C_PERF_SEL_CM_CHANNEL26_REQ = 0x000000c5, 15495 GL2C_PERF_SEL_CM_CHANNEL27_REQ = 0x000000c6, 15496 GL2C_PERF_SEL_CM_CHANNEL28_REQ = 0x000000c7, 15497 GL2C_PERF_SEL_CM_CHANNEL29_REQ = 0x000000c8, 15498 GL2C_PERF_SEL_CM_CHANNEL30_REQ = 0x000000c9, 15499 GL2C_PERF_SEL_CM_CHANNEL31_REQ = 0x000000ca, 15500 GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 0x000000cb, 15501 GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 0x000000cc, 15502 GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 0x000000cd, 15503 GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 0x000000ce, 15504 GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 0x000000cf, 15505 GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 0x000000d0, 15506 GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 0x000000d1, 15507 GL2C_PERF_SEL_CM_COMP_READ_REQ = 0x000000d2, 15508 GL2C_PERF_SEL_CM_READ_BACK_REQ = 0x000000d3, 15509 GL2C_PERF_SEL_CM_METADATA_WR_REQ = 0x000000d4, 15510 GL2C_PERF_SEL_CM_WR_ACK_REQ = 0x000000d5, 15511 GL2C_PERF_SEL_CM_NO_ACK_REQ = 0x000000d6, 15512 GL2C_PERF_SEL_CM_NOOP_REQ = 0x000000d7, 15513 GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 0x000000d8, 15514 GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 0x000000d9, 15515 GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 0x000000da, 15516 GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 0x000000db, 15517 GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 0x000000dc, 15518 GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 0x000000dd, 15519 GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 0x000000de, 15520 GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 0x000000df, 15521 GL2C_PERF_SEL_CM_RVF_FULL = 0x000000e0, 15522 GL2C_PERF_SEL_CM_SDR_FULL = 0x000000e1, 15523 GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 0x000000e2, 15524 GL2C_PERF_SEL_CM_DCC_STALL = 0x000000e3, 15525 } GL2C_PERF_SEL; 15526 15527 /* 15528 * GL2A_PERF_SEL enum 15529 */ 15530 15531 typedef enum GL2A_PERF_SEL { 15532 GL2A_PERF_SEL_NONE = 0x00000000, 15533 GL2A_PERF_SEL_CYCLE = 0x00000001, 15534 GL2A_PERF_SEL_BUSY = 0x00000002, 15535 GL2A_PERF_SEL_REQ_GL2C0 = 0x00000003, 15536 GL2A_PERF_SEL_REQ_GL2C1 = 0x00000004, 15537 GL2A_PERF_SEL_REQ_GL2C2 = 0x00000005, 15538 GL2A_PERF_SEL_REQ_GL2C3 = 0x00000006, 15539 GL2A_PERF_SEL_REQ_GL2C4 = 0x00000007, 15540 GL2A_PERF_SEL_REQ_GL2C5 = 0x00000008, 15541 GL2A_PERF_SEL_REQ_GL2C6 = 0x00000009, 15542 GL2A_PERF_SEL_REQ_GL2C7 = 0x0000000a, 15543 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 0x0000000b, 15544 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 0x0000000c, 15545 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 0x0000000d, 15546 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 0x0000000e, 15547 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 0x0000000f, 15548 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 0x00000010, 15549 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 0x00000011, 15550 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 0x00000012, 15551 GL2A_PERF_SEL_REQ_BURST_GL2C0 = 0x00000013, 15552 GL2A_PERF_SEL_REQ_BURST_GL2C1 = 0x00000014, 15553 GL2A_PERF_SEL_REQ_BURST_GL2C2 = 0x00000015, 15554 GL2A_PERF_SEL_REQ_BURST_GL2C3 = 0x00000016, 15555 GL2A_PERF_SEL_REQ_BURST_GL2C4 = 0x00000017, 15556 GL2A_PERF_SEL_REQ_BURST_GL2C5 = 0x00000018, 15557 GL2A_PERF_SEL_REQ_BURST_GL2C6 = 0x00000019, 15558 GL2A_PERF_SEL_REQ_BURST_GL2C7 = 0x0000001a, 15559 GL2A_PERF_SEL_REQ_STALL_GL2C0 = 0x0000001b, 15560 GL2A_PERF_SEL_REQ_STALL_GL2C1 = 0x0000001c, 15561 GL2A_PERF_SEL_REQ_STALL_GL2C2 = 0x0000001d, 15562 GL2A_PERF_SEL_REQ_STALL_GL2C3 = 0x0000001e, 15563 GL2A_PERF_SEL_REQ_STALL_GL2C4 = 0x0000001f, 15564 GL2A_PERF_SEL_REQ_STALL_GL2C5 = 0x00000020, 15565 GL2A_PERF_SEL_REQ_STALL_GL2C6 = 0x00000021, 15566 GL2A_PERF_SEL_REQ_STALL_GL2C7 = 0x00000022, 15567 GL2A_PERF_SEL_RTN_STALL_GL2C0 = 0x00000023, 15568 GL2A_PERF_SEL_RTN_STALL_GL2C1 = 0x00000024, 15569 GL2A_PERF_SEL_RTN_STALL_GL2C2 = 0x00000025, 15570 GL2A_PERF_SEL_RTN_STALL_GL2C3 = 0x00000026, 15571 GL2A_PERF_SEL_RTN_STALL_GL2C4 = 0x00000027, 15572 GL2A_PERF_SEL_RTN_STALL_GL2C5 = 0x00000028, 15573 GL2A_PERF_SEL_RTN_STALL_GL2C6 = 0x00000029, 15574 GL2A_PERF_SEL_RTN_STALL_GL2C7 = 0x0000002a, 15575 GL2A_PERF_SEL_RTN_CLIENT0 = 0x0000002b, 15576 GL2A_PERF_SEL_RTN_CLIENT1 = 0x0000002c, 15577 GL2A_PERF_SEL_RTN_CLIENT2 = 0x0000002d, 15578 GL2A_PERF_SEL_RTN_CLIENT3 = 0x0000002e, 15579 GL2A_PERF_SEL_RTN_CLIENT4 = 0x0000002f, 15580 GL2A_PERF_SEL_RTN_CLIENT5 = 0x00000030, 15581 GL2A_PERF_SEL_RTN_CLIENT6 = 0x00000031, 15582 GL2A_PERF_SEL_RTN_CLIENT7 = 0x00000032, 15583 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 0x00000033, 15584 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 0x00000034, 15585 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 0x00000035, 15586 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 0x00000036, 15587 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 0x00000037, 15588 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 0x00000038, 15589 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 0x00000039, 15590 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 0x0000003a, 15591 } GL2A_PERF_SEL; 15592 15593 /******************************************************* 15594 * GRBM Enums 15595 *******************************************************/ 15596 15597 /* 15598 * GRBM_PERF_SEL enum 15599 */ 15600 15601 typedef enum GRBM_PERF_SEL { 15602 GRBM_PERF_SEL_COUNT = 0x00000000, 15603 GRBM_PERF_SEL_USER_DEFINED = 0x00000001, 15604 GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, 15605 GRBM_PERF_SEL_CP_BUSY = 0x00000003, 15606 GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, 15607 GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, 15608 GRBM_PERF_SEL_CB_BUSY = 0x00000006, 15609 GRBM_PERF_SEL_DB_BUSY = 0x00000007, 15610 GRBM_PERF_SEL_PA_BUSY = 0x00000008, 15611 GRBM_PERF_SEL_SC_BUSY = 0x00000009, 15612 GRBM_PERF_SEL_RESERVED_6 = 0x0000000a, 15613 GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, 15614 GRBM_PERF_SEL_SX_BUSY = 0x0000000c, 15615 GRBM_PERF_SEL_TA_BUSY = 0x0000000d, 15616 GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, 15617 GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, 15618 GRBM_PERF_SEL_RESERVED_5 = 0x00000010, 15619 GRBM_PERF_SEL_RESERVED_9 = 0x00000011, 15620 GRBM_PERF_SEL_RESERVED_4 = 0x00000012, 15621 GRBM_PERF_SEL_RESERVED_3 = 0x00000013, 15622 GRBM_PERF_SEL_RESERVED_2 = 0x00000014, 15623 GRBM_PERF_SEL_RESERVED_1 = 0x00000015, 15624 GRBM_PERF_SEL_RESERVED_0 = 0x00000016, 15625 GRBM_PERF_SEL_RESERVED_8 = 0x00000017, 15626 GRBM_PERF_SEL_RESERVED_7 = 0x00000018, 15627 GRBM_PERF_SEL_GDS_BUSY = 0x00000019, 15628 GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, 15629 GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, 15630 GRBM_PERF_SEL_TCP_BUSY = 0x0000001c, 15631 GRBM_PERF_SEL_CPG_BUSY = 0x0000001d, 15632 GRBM_PERF_SEL_CPC_BUSY = 0x0000001e, 15633 GRBM_PERF_SEL_CPF_BUSY = 0x0000001f, 15634 GRBM_PERF_SEL_GE_BUSY = 0x00000020, 15635 GRBM_PERF_SEL_GE_NO_DMA_BUSY = 0x00000021, 15636 GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022, 15637 GRBM_PERF_SEL_EA_BUSY = 0x00000023, 15638 GRBM_PERF_SEL_RMI_BUSY = 0x00000024, 15639 GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025, 15640 GRBM_PERF_SEL_UTCL1_BUSY = 0x00000027, 15641 GRBM_PERF_SEL_GL2CC_BUSY = 0x00000028, 15642 GRBM_PERF_SEL_SDMA_BUSY = 0x00000029, 15643 GRBM_PERF_SEL_CH_BUSY = 0x0000002a, 15644 GRBM_PERF_SEL_PH_BUSY = 0x0000002b, 15645 GRBM_PERF_SEL_PMM_BUSY = 0x0000002c, 15646 GRBM_PERF_SEL_GUS_BUSY = 0x0000002d, 15647 GRBM_PERF_SEL_GL1CC_BUSY = 0x0000002e, 15648 } GRBM_PERF_SEL; 15649 15650 /* 15651 * GRBM_SE0_PERF_SEL enum 15652 */ 15653 15654 typedef enum GRBM_SE0_PERF_SEL { 15655 GRBM_SE0_PERF_SEL_COUNT = 0x00000000, 15656 GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001, 15657 GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002, 15658 GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003, 15659 GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004, 15660 GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005, 15661 GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006, 15662 GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007, 15663 GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008, 15664 GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009, 15665 GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a, 15666 GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b, 15667 GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c, 15668 GRBM_SE0_PERF_SEL_RESERVED_2 = 0x0000000d, 15669 GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e, 15670 GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f, 15671 GRBM_SE0_PERF_SEL_UTCL1_BUSY = 0x00000010, 15672 GRBM_SE0_PERF_SEL_TCP_BUSY = 0x00000011, 15673 GRBM_SE0_PERF_SEL_GL1CC_BUSY = 0x00000012, 15674 } GRBM_SE0_PERF_SEL; 15675 15676 /* 15677 * GRBM_SE1_PERF_SEL enum 15678 */ 15679 15680 typedef enum GRBM_SE1_PERF_SEL { 15681 GRBM_SE1_PERF_SEL_COUNT = 0x00000000, 15682 GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001, 15683 GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002, 15684 GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003, 15685 GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004, 15686 GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005, 15687 GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006, 15688 GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007, 15689 GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008, 15690 GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009, 15691 GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a, 15692 GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b, 15693 GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c, 15694 GRBM_SE1_PERF_SEL_RESERVED_2 = 0x0000000d, 15695 GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e, 15696 GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f, 15697 GRBM_SE1_PERF_SEL_UTCL1_BUSY = 0x00000010, 15698 GRBM_SE1_PERF_SEL_TCP_BUSY = 0x00000011, 15699 GRBM_SE1_PERF_SEL_GL1CC_BUSY = 0x00000012, 15700 } GRBM_SE1_PERF_SEL; 15701 15702 /* 15703 * GRBM_SE2_PERF_SEL enum 15704 */ 15705 15706 typedef enum GRBM_SE2_PERF_SEL { 15707 GRBM_SE2_PERF_SEL_COUNT = 0x00000000, 15708 GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001, 15709 GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002, 15710 GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003, 15711 GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004, 15712 GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005, 15713 GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006, 15714 GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007, 15715 GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008, 15716 GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009, 15717 GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a, 15718 GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b, 15719 GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c, 15720 GRBM_SE2_PERF_SEL_RESERVED_2 = 0x0000000d, 15721 GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e, 15722 GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f, 15723 GRBM_SE2_PERF_SEL_UTCL1_BUSY = 0x00000010, 15724 GRBM_SE2_PERF_SEL_TCP_BUSY = 0x00000011, 15725 GRBM_SE2_PERF_SEL_GL1CC_BUSY = 0x00000012, 15726 } GRBM_SE2_PERF_SEL; 15727 15728 /* 15729 * GRBM_SE3_PERF_SEL enum 15730 */ 15731 15732 typedef enum GRBM_SE3_PERF_SEL { 15733 GRBM_SE3_PERF_SEL_COUNT = 0x00000000, 15734 GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001, 15735 GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002, 15736 GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003, 15737 GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004, 15738 GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005, 15739 GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006, 15740 GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007, 15741 GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008, 15742 GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009, 15743 GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a, 15744 GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b, 15745 GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c, 15746 GRBM_SE3_PERF_SEL_RESERVED_2 = 0x0000000d, 15747 GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e, 15748 GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f, 15749 GRBM_SE3_PERF_SEL_UTCL1_BUSY = 0x00000010, 15750 GRBM_SE3_PERF_SEL_TCP_BUSY = 0x00000011, 15751 GRBM_SE3_PERF_SEL_GL1CC_BUSY = 0x00000012, 15752 } GRBM_SE3_PERF_SEL; 15753 15754 /******************************************************* 15755 * CP Enums 15756 *******************************************************/ 15757 15758 /* 15759 * CP_RING_ID enum 15760 */ 15761 15762 typedef enum CP_RING_ID { 15763 RINGID0 = 0x00000000, 15764 RINGID1 = 0x00000001, 15765 RINGID2 = 0x00000002, 15766 RINGID3 = 0x00000003, 15767 } CP_RING_ID; 15768 15769 /* 15770 * CP_PIPE_ID enum 15771 */ 15772 15773 typedef enum CP_PIPE_ID { 15774 PIPE_ID0 = 0x00000000, 15775 PIPE_ID1 = 0x00000001, 15776 PIPE_ID2 = 0x00000002, 15777 PIPE_ID3 = 0x00000003, 15778 } CP_PIPE_ID; 15779 15780 /* 15781 * CP_ME_ID enum 15782 */ 15783 15784 typedef enum CP_ME_ID { 15785 ME_ID0 = 0x00000000, 15786 ME_ID1 = 0x00000001, 15787 ME_ID2 = 0x00000002, 15788 ME_ID3 = 0x00000003, 15789 } CP_ME_ID; 15790 15791 /* 15792 * SPM_PERFMON_STATE enum 15793 */ 15794 15795 typedef enum SPM_PERFMON_STATE { 15796 STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, 15797 STRM_PERFMON_STATE_START_COUNTING = 0x00000001, 15798 STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, 15799 STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, 15800 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, 15801 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, 15802 } SPM_PERFMON_STATE; 15803 15804 /* 15805 * CP_PERFMON_STATE enum 15806 */ 15807 15808 typedef enum CP_PERFMON_STATE { 15809 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, 15810 CP_PERFMON_STATE_START_COUNTING = 0x00000001, 15811 CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, 15812 CP_PERFMON_STATE_RESERVED_3 = 0x00000003, 15813 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, 15814 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, 15815 } CP_PERFMON_STATE; 15816 15817 /* 15818 * CP_PERFMON_ENABLE_MODE enum 15819 */ 15820 15821 typedef enum CP_PERFMON_ENABLE_MODE { 15822 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, 15823 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, 15824 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, 15825 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, 15826 } CP_PERFMON_ENABLE_MODE; 15827 15828 /* 15829 * CPG_PERFCOUNT_SEL enum 15830 */ 15831 15832 typedef enum CPG_PERFCOUNT_SEL { 15833 CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, 15834 CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, 15835 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, 15836 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003, 15837 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, 15838 CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, 15839 CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, 15840 CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, 15841 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008, 15842 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, 15843 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, 15844 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, 15845 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, 15846 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, 15847 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, 15848 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, 15849 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, 15850 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, 15851 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, 15852 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, 15853 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, 15854 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, 15855 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, 15856 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, 15857 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, 15858 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, 15859 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, 15860 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, 15861 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, 15862 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, 15863 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e, 15864 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, 15865 CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, 15866 CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, 15867 CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000022, 15868 CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000023, 15869 CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, 15870 CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, 15871 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, 15872 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, 15873 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028, 15874 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, 15875 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, 15876 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, 15877 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, 15878 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, 15879 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e, 15880 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f, 15881 CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030, 15882 CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000031, 15883 CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000032, 15884 CPG_PERF_SEL_CPG_STAT_BUSY = 0x00000033, 15885 CPG_PERF_SEL_CPG_STAT_IDLE = 0x00000034, 15886 CPG_PERF_SEL_CPG_STAT_STALL = 0x00000035, 15887 CPG_PERF_SEL_CPG_TCIU_BUSY = 0x00000036, 15888 CPG_PERF_SEL_CPG_TCIU_IDLE = 0x00000037, 15889 CPF_PERF_SEL_CPG_TCIU_STALL = 0x00000038, 15890 CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 0x00000039, 15891 CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 0x0000003a, 15892 CPG_PERF_SEL_CPG_UTCL2IU_STALL = 0x0000003b, 15893 CPG_PERF_SEL_CPG_GCRIU_BUSY = 0x0000003c, 15894 CPG_PERF_SEL_CPG_GCRIU_IDLE = 0x0000003d, 15895 CPG_PERF_SEL_CPG_GCRIU_STALL = 0x0000003e, 15896 CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x0000003f, 15897 CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 0x00000040, 15898 CPG_PERF_SEL_CPG_UTCL2IU_XACK = 0x00000041, 15899 CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 0x00000042, 15900 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 0x00000043, 15901 CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 0x00000044, 15902 CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 0x00000045, 15903 CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 0x00000046, 15904 CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 0x00000047, 15905 CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 0x00000048, 15906 CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 0x00000049, 15907 CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 0x0000004a, 15908 CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 0x0000004b, 15909 CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 0x0000004c, 15910 CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 0x0000004d, 15911 } CPG_PERFCOUNT_SEL; 15912 15913 /* 15914 * CPF_PERFCOUNT_SEL enum 15915 */ 15916 15917 typedef enum CPF_PERFCOUNT_SEL { 15918 CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, 15919 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001, 15920 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, 15921 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, 15922 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, 15923 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, 15924 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, 15925 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007, 15926 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008, 15927 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009, 15928 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, 15929 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, 15930 CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, 15931 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, 15932 CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, 15933 CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND = 0x0000000f, 15934 CPF_PERF_SEL_GUS_READ_REQUEST_SEND = 0x00000010, 15935 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011, 15936 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012, 15937 CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013, 15938 CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014, 15939 CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000015, 15940 CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000016, 15941 CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000017, 15942 CPF_PERF_SEL_CPF_STAT_BUSY = 0x00000018, 15943 CPF_PERF_SEL_CPF_STAT_IDLE = 0x00000019, 15944 CPF_PERF_SEL_CPF_STAT_STALL = 0x0000001a, 15945 CPF_PERF_SEL_CPF_TCIU_BUSY = 0x0000001b, 15946 CPF_PERF_SEL_CPF_TCIU_IDLE = 0x0000001c, 15947 CPF_PERF_SEL_CPF_TCIU_STALL = 0x0000001d, 15948 CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 0x0000001e, 15949 CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 0x0000001f, 15950 CPF_PERF_SEL_CPF_UTCL2IU_STALL = 0x00000020, 15951 CPF_PERF_SEL_CPF_GCRIU_BUSY = 0x00000021, 15952 CPF_PERF_SEL_CPF_GCRIU_IDLE = 0x00000022, 15953 CPF_PERF_SEL_CPF_GCRIU_STALL = 0x00000023, 15954 CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000024, 15955 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 0x00000025, 15956 CPF_PERF_SEL_CPF_UTCL2IU_XACK = 0x00000026, 15957 CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 0x00000027, 15958 } CPF_PERFCOUNT_SEL; 15959 15960 /* 15961 * CPC_PERFCOUNT_SEL enum 15962 */ 15963 15964 typedef enum CPC_PERFCOUNT_SEL { 15965 CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, 15966 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, 15967 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, 15968 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003, 15969 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004, 15970 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, 15971 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, 15972 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, 15973 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, 15974 CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 0x00000009, 15975 CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 0x0000000a, 15976 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, 15977 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, 15978 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, 15979 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, 15980 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, 15981 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, 15982 CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 0x00000011, 15983 CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 0x00000012, 15984 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, 15985 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, 15986 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, 15987 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016, 15988 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017, 15989 CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018, 15990 CPC_PERF_SEL_CPC_STAT_BUSY = 0x00000019, 15991 CPC_PERF_SEL_CPC_STAT_IDLE = 0x0000001a, 15992 CPC_PERF_SEL_CPC_STAT_STALL = 0x0000001b, 15993 CPC_PERF_SEL_CPC_TCIU_BUSY = 0x0000001c, 15994 CPC_PERF_SEL_CPC_TCIU_IDLE = 0x0000001d, 15995 CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 0x0000001e, 15996 CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 0x0000001f, 15997 CPC_PERF_SEL_CPC_UTCL2IU_STALL = 0x00000020, 15998 CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 0x00000021, 15999 CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 0x00000022, 16000 CPC_PERF_SEL_CPC_GCRIU_BUSY = 0x00000023, 16001 CPC_PERF_SEL_CPC_GCRIU_IDLE = 0x00000024, 16002 CPC_PERF_SEL_CPC_GCRIU_STALL = 0x00000025, 16003 CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000026, 16004 CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 0x00000027, 16005 CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 0x00000028, 16006 CPC_PERF_SEL_CPC_UTCL2IU_XACK = 0x00000029, 16007 CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 0x0000002a, 16008 CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 0x0000002b, 16009 CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 0x0000002c, 16010 } CPC_PERFCOUNT_SEL; 16011 16012 /* 16013 * CP_ALPHA_TAG_RAM_SEL enum 16014 */ 16015 16016 typedef enum CP_ALPHA_TAG_RAM_SEL { 16017 CPG_TAG_RAM = 0x00000000, 16018 CPC_TAG_RAM = 0x00000001, 16019 CPF_TAG_RAM = 0x00000002, 16020 RSV_TAG_RAM = 0x00000003, 16021 } CP_ALPHA_TAG_RAM_SEL; 16022 16023 /* 16024 * CPF_PERFCOUNTWINDOW_SEL enum 16025 */ 16026 16027 typedef enum CPF_PERFCOUNTWINDOW_SEL { 16028 CPF_PERFWINDOW_SEL_CSF = 0x00000000, 16029 CPF_PERFWINDOW_SEL_HQD1 = 0x00000001, 16030 CPF_PERFWINDOW_SEL_HQD2 = 0x00000002, 16031 CPF_PERFWINDOW_SEL_RDMA = 0x00000003, 16032 CPF_PERFWINDOW_SEL_RWPP = 0x00000004, 16033 } CPF_PERFCOUNTWINDOW_SEL; 16034 16035 /* 16036 * CPG_PERFCOUNTWINDOW_SEL enum 16037 */ 16038 16039 typedef enum CPG_PERFCOUNTWINDOW_SEL { 16040 CPG_PERFWINDOW_SEL_PFP = 0x00000000, 16041 CPG_PERFWINDOW_SEL_ME = 0x00000001, 16042 CPG_PERFWINDOW_SEL_CE = 0x00000002, 16043 CPG_PERFWINDOW_SEL_MES = 0x00000003, 16044 CPG_PERFWINDOW_SEL_MEC1 = 0x00000004, 16045 CPG_PERFWINDOW_SEL_MEC2 = 0x00000005, 16046 CPG_PERFWINDOW_SEL_DFY = 0x00000006, 16047 CPG_PERFWINDOW_SEL_DMA = 0x00000007, 16048 CPG_PERFWINDOW_SEL_SHADOW = 0x00000008, 16049 CPG_PERFWINDOW_SEL_RB = 0x00000009, 16050 CPG_PERFWINDOW_SEL_CEDMA = 0x0000000a, 16051 CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 0x0000000b, 16052 CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 0x0000000c, 16053 CPG_PERFWINDOW_SEL_PQ1 = 0x0000000d, 16054 CPG_PERFWINDOW_SEL_PQ2 = 0x0000000e, 16055 CPG_PERFWINDOW_SEL_PQ3 = 0x0000000f, 16056 CPG_PERFWINDOW_SEL_MEMWR = 0x00000010, 16057 CPG_PERFWINDOW_SEL_MEMRD = 0x00000011, 16058 CPG_PERFWINDOW_SEL_VGT0 = 0x00000012, 16059 CPG_PERFWINDOW_SEL_VGT1 = 0x00000013, 16060 CPG_PERFWINDOW_SEL_APPEND = 0x00000014, 16061 CPG_PERFWINDOW_SEL_QURD = 0x00000015, 16062 CPG_PERFWINDOW_SEL_DDID = 0x00000016, 16063 CPG_PERFWINDOW_SEL_SR = 0x00000017, 16064 CPG_PERFWINDOW_SEL_QU_EOP = 0x00000018, 16065 CPG_PERFWINDOW_SEL_QU_STRM = 0x00000019, 16066 CPG_PERFWINDOW_SEL_QU_PIPE = 0x0000001a, 16067 CPG_PERFWINDOW_SEL_RESERVED1 = 0x0000001b, 16068 CPG_PERFWINDOW_SEL_CPC_IC = 0x0000001c, 16069 CPG_PERFWINDOW_SEL_RESERVED2 = 0x0000001d, 16070 CPG_PERFWINDOW_SEL_CPG_IC = 0x0000001e, 16071 } CPG_PERFCOUNTWINDOW_SEL; 16072 16073 /* 16074 * CPF_LATENCY_STATS_SEL enum 16075 */ 16076 16077 typedef enum CPF_LATENCY_STATS_SEL { 16078 CPF_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, 16079 CPF_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, 16080 CPF_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, 16081 CPF_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, 16082 CPF_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, 16083 CPF_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, 16084 CPF_LATENCY_STATS_SEL_READ_MAX = 0x00000006, 16085 CPF_LATENCY_STATS_SEL_READ_MIN = 0x00000007, 16086 CPF_LATENCY_STATS_SEL_READ_LAST = 0x00000008, 16087 CPF_LATENCY_STATS_SEL_INVAL_MAX = 0x00000009, 16088 CPF_LATENCY_STATS_SEL_INVAL_MIN = 0x0000000a, 16089 CPF_LATENCY_STATS_SEL_INVAL_LAST = 0x0000000b, 16090 } CPF_LATENCY_STATS_SEL; 16091 16092 /* 16093 * CPG_LATENCY_STATS_SEL enum 16094 */ 16095 16096 typedef enum CPG_LATENCY_STATS_SEL { 16097 CPG_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, 16098 CPG_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, 16099 CPG_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, 16100 CPG_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, 16101 CPG_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, 16102 CPG_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, 16103 CPG_LATENCY_STATS_SEL_WRITE_MAX = 0x00000006, 16104 CPG_LATENCY_STATS_SEL_WRITE_MIN = 0x00000007, 16105 CPG_LATENCY_STATS_SEL_WRITE_LAST = 0x00000008, 16106 CPG_LATENCY_STATS_SEL_READ_MAX = 0x00000009, 16107 CPG_LATENCY_STATS_SEL_READ_MIN = 0x0000000a, 16108 CPG_LATENCY_STATS_SEL_READ_LAST = 0x0000000b, 16109 CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 0x0000000c, 16110 CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 0x0000000d, 16111 CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 0x0000000e, 16112 CPG_LATENCY_STATS_SEL_INVAL_MAX = 0x0000000f, 16113 CPG_LATENCY_STATS_SEL_INVAL_MIN = 0x00000010, 16114 CPG_LATENCY_STATS_SEL_INVAL_LAST = 0x00000011, 16115 } CPG_LATENCY_STATS_SEL; 16116 16117 /* 16118 * CPC_LATENCY_STATS_SEL enum 16119 */ 16120 16121 typedef enum CPC_LATENCY_STATS_SEL { 16122 CPC_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, 16123 CPC_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, 16124 CPC_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, 16125 CPC_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, 16126 CPC_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, 16127 CPC_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, 16128 CPC_LATENCY_STATS_SEL_INVAL_MAX = 0x00000006, 16129 CPC_LATENCY_STATS_SEL_INVAL_MIN = 0x00000007, 16130 CPC_LATENCY_STATS_SEL_INVAL_LAST = 0x00000008, 16131 } CPC_LATENCY_STATS_SEL; 16132 16133 /* 16134 * CP_DDID_CNTL_MODE enum 16135 */ 16136 16137 typedef enum CP_DDID_CNTL_MODE { 16138 STALL = 0x00000000, 16139 OVERRUN = 0x00000001, 16140 } CP_DDID_CNTL_MODE; 16141 16142 /* 16143 * CP_DDID_CNTL_SIZE enum 16144 */ 16145 16146 typedef enum CP_DDID_CNTL_SIZE { 16147 SIZE_8K = 0x00000000, 16148 SIZE_16K = 0x00000001, 16149 } CP_DDID_CNTL_SIZE; 16150 16151 /* 16152 * CP_DDID_CNTL_VMID_SEL enum 16153 */ 16154 16155 typedef enum CP_DDID_CNTL_VMID_SEL { 16156 DDID_VMID_PIPE = 0x00000000, 16157 DDID_VMID_CNTL = 0x00000001, 16158 } CP_DDID_CNTL_VMID_SEL; 16159 16160 /* 16161 * SEM_RESPONSE value 16162 */ 16163 16164 #define SEM_ECC_ERROR 0x00000000 16165 #define SEM_TRANS_ERROR 0x00000001 16166 #define SEM_RESP_FAILED 0x00000002 16167 #define SEM_RESP_PASSED 0x00000003 16168 16169 /* 16170 * IQ_RETRY_TYPE value 16171 */ 16172 16173 #define IQ_QUEUE_SLEEP 0x00000000 16174 #define IQ_OFFLOAD_RETRY 0x00000001 16175 #define IQ_SCH_WAVE_MSG 0x00000002 16176 #define IQ_SEM_REARM 0x00000003 16177 #define IQ_DEQUEUE_RETRY 0x00000004 16178 16179 /* 16180 * IQ_INTR_TYPE value 16181 */ 16182 16183 #define IQ_INTR_TYPE_PQ 0x00000000 16184 #define IQ_INTR_TYPE_IB 0x00000001 16185 #define IQ_INTR_TYPE_MQD 0x00000002 16186 16187 /* 16188 * VMID_SIZE value 16189 */ 16190 16191 #define VMID_SZ 0x00000004 16192 16193 /* 16194 * CONFIG_SPACE value 16195 */ 16196 16197 #define CONFIG_SPACE_START 0x00002000 16198 #define CONFIG_SPACE_END 0x00009fff 16199 16200 /* 16201 * CONFIG_SPACE1 value 16202 */ 16203 16204 #define CONFIG_SPACE1_START 0x00002000 16205 #define CONFIG_SPACE1_END 0x00002bff 16206 16207 /* 16208 * CONFIG_SPACE2 value 16209 */ 16210 16211 #define CONFIG_SPACE2_START 0x00003000 16212 #define CONFIG_SPACE2_END 0x00009fff 16213 16214 /* 16215 * UCONFIG_SPACE value 16216 */ 16217 16218 #define UCONFIG_SPACE_START 0x0000c000 16219 #define UCONFIG_SPACE_END 0x0000ffff 16220 16221 /* 16222 * PERSISTENT_SPACE value 16223 */ 16224 16225 #define PERSISTENT_SPACE_START 0x00002c00 16226 #define PERSISTENT_SPACE_END 0x00002fff 16227 16228 /* 16229 * CONTEXT_SPACE value 16230 */ 16231 16232 #define CONTEXT_SPACE_START 0x0000a000 16233 #define CONTEXT_SPACE_END 0x0000bfff 16234 16235 /******************************************************* 16236 * SX Enums 16237 *******************************************************/ 16238 16239 /* 16240 * SX_BLEND_OPT enum 16241 */ 16242 16243 typedef enum SX_BLEND_OPT { 16244 BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, 16245 BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, 16246 BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, 16247 BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, 16248 BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, 16249 BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, 16250 BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, 16251 BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, 16252 } SX_BLEND_OPT; 16253 16254 /* 16255 * SX_OPT_COMB_FCN enum 16256 */ 16257 16258 typedef enum SX_OPT_COMB_FCN { 16259 OPT_COMB_NONE = 0x00000000, 16260 OPT_COMB_ADD = 0x00000001, 16261 OPT_COMB_SUBTRACT = 0x00000002, 16262 OPT_COMB_MIN = 0x00000003, 16263 OPT_COMB_MAX = 0x00000004, 16264 OPT_COMB_REVSUBTRACT = 0x00000005, 16265 OPT_COMB_BLEND_DISABLED = 0x00000006, 16266 OPT_COMB_SAFE_ADD = 0x00000007, 16267 } SX_OPT_COMB_FCN; 16268 16269 /* 16270 * SX_DOWNCONVERT_FORMAT enum 16271 */ 16272 16273 typedef enum SX_DOWNCONVERT_FORMAT { 16274 SX_RT_EXPORT_NO_CONVERSION = 0x00000000, 16275 SX_RT_EXPORT_32_R = 0x00000001, 16276 SX_RT_EXPORT_32_A = 0x00000002, 16277 SX_RT_EXPORT_10_11_11 = 0x00000003, 16278 SX_RT_EXPORT_2_10_10_10 = 0x00000004, 16279 SX_RT_EXPORT_8_8_8_8 = 0x00000005, 16280 SX_RT_EXPORT_5_6_5 = 0x00000006, 16281 SX_RT_EXPORT_1_5_5_5 = 0x00000007, 16282 SX_RT_EXPORT_4_4_4_4 = 0x00000008, 16283 SX_RT_EXPORT_16_16_GR = 0x00000009, 16284 SX_RT_EXPORT_16_16_AR = 0x0000000a, 16285 } SX_DOWNCONVERT_FORMAT; 16286 16287 /* 16288 * SX_PERFCOUNTER_VALS enum 16289 */ 16290 16291 typedef enum SX_PERFCOUNTER_VALS { 16292 SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000, 16293 SX_PERF_SEL_PA_REQ = 0x00000001, 16294 SX_PERF_SEL_PA_POS = 0x00000002, 16295 SX_PERF_SEL_CLOCK = 0x00000003, 16296 SX_PERF_SEL_GATE_EN1 = 0x00000004, 16297 SX_PERF_SEL_GATE_EN2 = 0x00000005, 16298 SX_PERF_SEL_GATE_EN3 = 0x00000006, 16299 SX_PERF_SEL_GATE_EN4 = 0x00000007, 16300 SX_PERF_SEL_SH_POS_STARVE = 0x00000008, 16301 SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009, 16302 SX_PERF_SEL_SH_POS_STALL = 0x0000000a, 16303 SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b, 16304 SX_PERF_SEL_DB0_PIXELS = 0x0000000c, 16305 SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d, 16306 SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e, 16307 SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f, 16308 SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010, 16309 SX_PERF_SEL_DB1_PIXELS = 0x00000011, 16310 SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012, 16311 SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013, 16312 SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014, 16313 SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015, 16314 SX_PERF_SEL_DB2_PIXELS = 0x00000016, 16315 SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017, 16316 SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018, 16317 SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019, 16318 SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a, 16319 SX_PERF_SEL_DB3_PIXELS = 0x0000001b, 16320 SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c, 16321 SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d, 16322 SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e, 16323 SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f, 16324 SX_PERF_SEL_COL_BUSY = 0x00000020, 16325 SX_PERF_SEL_POS_BUSY = 0x00000021, 16326 SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 0x00000022, 16327 SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 0x00000023, 16328 SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 0x00000024, 16329 SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 0x00000025, 16330 SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 0x00000026, 16331 SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 0x00000027, 16332 SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 0x00000028, 16333 SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 0x00000029, 16334 SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 0x0000002a, 16335 SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 0x0000002b, 16336 SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 0x0000002c, 16337 SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 0x0000002d, 16338 SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 0x0000002e, 16339 SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 0x0000002f, 16340 SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 0x00000030, 16341 SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 0x00000031, 16342 SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 0x00000032, 16343 SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 0x00000033, 16344 SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 0x00000034, 16345 SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 0x00000035, 16346 SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 0x00000036, 16347 SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 0x00000037, 16348 SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 0x00000038, 16349 SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 0x00000039, 16350 SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 0x0000003a, 16351 SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 0x0000003b, 16352 SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 0x0000003c, 16353 SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 0x0000003d, 16354 SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 0x0000003e, 16355 SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 0x0000003f, 16356 SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 0x00000040, 16357 SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 0x00000041, 16358 SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 0x00000042, 16359 SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 0x00000043, 16360 SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 0x00000044, 16361 SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 0x00000045, 16362 SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 0x00000046, 16363 SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 0x00000047, 16364 SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 0x00000048, 16365 SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 0x00000049, 16366 SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 0x0000004a, 16367 SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 0x0000004b, 16368 SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 0x0000004c, 16369 SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 0x0000004d, 16370 SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 0x0000004e, 16371 SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 0x0000004f, 16372 SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 0x00000050, 16373 SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 0x00000051, 16374 SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 0x00000052, 16375 SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 0x00000053, 16376 SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 0x00000054, 16377 SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 0x00000055, 16378 SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 0x00000056, 16379 SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 0x00000057, 16380 SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 0x00000058, 16381 SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 0x00000059, 16382 SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 0x0000005a, 16383 SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 0x0000005b, 16384 SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 0x0000005c, 16385 SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 0x0000005d, 16386 SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 0x0000005e, 16387 SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 0x0000005f, 16388 SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 0x00000060, 16389 SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 0x00000061, 16390 SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 0x00000062, 16391 SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 0x00000063, 16392 SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 0x00000064, 16393 SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 0x00000065, 16394 SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 0x00000066, 16395 SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 0x00000067, 16396 SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 0x00000068, 16397 SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 0x00000069, 16398 SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 0x0000006a, 16399 SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 0x0000006b, 16400 SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 0x0000006c, 16401 SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 0x0000006d, 16402 SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 0x0000006e, 16403 SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 0x0000006f, 16404 SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 0x00000070, 16405 SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 0x00000071, 16406 SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 0x00000072, 16407 SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 0x00000073, 16408 SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 0x00000074, 16409 SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 0x00000075, 16410 SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 0x00000076, 16411 SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 0x00000077, 16412 SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 0x00000078, 16413 SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 0x00000079, 16414 SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 0x0000007a, 16415 SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 0x0000007b, 16416 SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 0x0000007c, 16417 SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 0x0000007d, 16418 SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 0x0000007e, 16419 SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 0x0000007f, 16420 SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 0x00000080, 16421 SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 0x00000081, 16422 SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 0x00000082, 16423 SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 0x00000083, 16424 SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 0x00000084, 16425 SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 0x00000085, 16426 SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 0x00000086, 16427 SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 0x00000087, 16428 SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 0x00000088, 16429 SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 0x00000089, 16430 SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 0x0000008a, 16431 SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 0x0000008b, 16432 SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 0x0000008c, 16433 SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 0x0000008d, 16434 SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 0x0000008e, 16435 SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 0x0000008f, 16436 SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 0x00000090, 16437 SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 0x00000091, 16438 SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 0x00000092, 16439 SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 0x00000093, 16440 SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 0x00000094, 16441 SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 0x00000095, 16442 SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 0x00000096, 16443 SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 0x00000097, 16444 SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 0x00000098, 16445 SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 0x00000099, 16446 SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 0x0000009a, 16447 SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 0x0000009b, 16448 SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 0x0000009c, 16449 SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 0x0000009d, 16450 SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 0x0000009e, 16451 SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 0x0000009f, 16452 SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 0x000000a0, 16453 SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 0x000000a1, 16454 SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 0x000000a2, 16455 SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 0x000000a3, 16456 SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 0x000000a4, 16457 SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 0x000000a5, 16458 SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 0x000000a6, 16459 SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 0x000000a7, 16460 SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 0x000000a8, 16461 SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 0x000000a9, 16462 SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 0x000000aa, 16463 SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 0x000000ab, 16464 SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 0x000000ac, 16465 SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 0x000000ad, 16466 SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 0x000000ae, 16467 SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 0x000000af, 16468 SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 0x000000b0, 16469 SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 0x000000b1, 16470 SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 0x000000b2, 16471 SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 0x000000b3, 16472 SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 0x000000b4, 16473 SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 0x000000b5, 16474 SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 0x000000b6, 16475 SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 0x000000b7, 16476 SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 0x000000b8, 16477 SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 0x000000b9, 16478 SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 0x000000ba, 16479 SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 0x000000bb, 16480 SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 0x000000bc, 16481 SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 0x000000bd, 16482 SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 0x000000be, 16483 SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 0x000000bf, 16484 SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 0x000000c0, 16485 SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 0x000000c1, 16486 SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 0x000000c2, 16487 SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 0x000000c3, 16488 SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 0x000000c4, 16489 SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 0x000000c5, 16490 SX_PERF_SEL_PA_REQ_LATENCY = 0x000000c6, 16491 SX_PERF_SEL_POS_SCBD_STALL = 0x000000c7, 16492 SX_PERF_SEL_COL_SCBD_STALL = 0x000000c8, 16493 SX_PERF_SEL_CLOCK_DROP_STALL = 0x000000c9, 16494 SX_PERF_SEL_GATE_EN5 = 0x000000ca, 16495 SX_PERF_SEL_GATE_EN6 = 0x000000cb, 16496 SX_PERF_SEL_DB0_SIZE = 0x000000cc, 16497 SX_PERF_SEL_DB1_SIZE = 0x000000cd, 16498 SX_PERF_SEL_DB2_SIZE = 0x000000ce, 16499 SX_PERF_SEL_DB3_SIZE = 0x000000cf, 16500 SX_PERF_SEL_SPLITMODE = 0x000000d0, 16501 SX_PERF_SEL_COL_SCBD0_STALL = 0x000000d1, 16502 SX_PERF_SEL_COL_SCBD1_STALL = 0x000000d2, 16503 SX_PERF_SEL_IDX_STALL_CYCLES = 0x000000d3, 16504 SX_PERF_SEL_IDX_IDLE_CYCLES = 0x000000d4, 16505 SX_PERF_SEL_IDX_REQ = 0x000000d5, 16506 SX_PERF_SEL_IDX_RET = 0x000000d6, 16507 SX_PERF_SEL_IDX_REQ_LATENCY = 0x000000d7, 16508 SX_PERF_SEL_IDX_SCBD_STALL = 0x000000d8, 16509 SX_PERF_SEL_GATE_EN7 = 0x000000d9, 16510 SX_PERF_SEL_GATE_EN8 = 0x000000da, 16511 SX_PERF_SEL_SH_IDX_STARVE = 0x000000db, 16512 SX_PERF_SEL_IDX_BUSY = 0x000000dc, 16513 } SX_PERFCOUNTER_VALS; 16514 16515 /******************************************************* 16516 * DB Enums 16517 *******************************************************/ 16518 16519 /* 16520 * ForceControl enum 16521 */ 16522 16523 typedef enum ForceControl { 16524 FORCE_OFF = 0x00000000, 16525 FORCE_ENABLE = 0x00000001, 16526 FORCE_DISABLE = 0x00000002, 16527 FORCE_RESERVED = 0x00000003, 16528 } ForceControl; 16529 16530 /* 16531 * ZSamplePosition enum 16532 */ 16533 16534 typedef enum ZSamplePosition { 16535 Z_SAMPLE_CENTER = 0x00000000, 16536 Z_SAMPLE_CENTROID = 0x00000001, 16537 } ZSamplePosition; 16538 16539 /* 16540 * ZOrder enum 16541 */ 16542 16543 typedef enum ZOrder { 16544 LATE_Z = 0x00000000, 16545 EARLY_Z_THEN_LATE_Z = 0x00000001, 16546 RE_Z = 0x00000002, 16547 EARLY_Z_THEN_RE_Z = 0x00000003, 16548 } ZOrder; 16549 16550 /* 16551 * ZpassControl enum 16552 */ 16553 16554 typedef enum ZpassControl { 16555 ZPASS_DISABLE = 0x00000000, 16556 ZPASS_SAMPLES = 0x00000001, 16557 ZPASS_PIXELS = 0x00000002, 16558 } ZpassControl; 16559 16560 /* 16561 * ZModeForce enum 16562 */ 16563 16564 typedef enum ZModeForce { 16565 NO_FORCE = 0x00000000, 16566 FORCE_EARLY_Z = 0x00000001, 16567 FORCE_LATE_Z = 0x00000002, 16568 FORCE_RE_Z = 0x00000003, 16569 } ZModeForce; 16570 16571 /* 16572 * ZLimitSumm enum 16573 */ 16574 16575 typedef enum ZLimitSumm { 16576 FORCE_SUMM_OFF = 0x00000000, 16577 FORCE_SUMM_MINZ = 0x00000001, 16578 FORCE_SUMM_MAXZ = 0x00000002, 16579 FORCE_SUMM_BOTH = 0x00000003, 16580 } ZLimitSumm; 16581 16582 /* 16583 * CompareFrag enum 16584 */ 16585 16586 typedef enum CompareFrag { 16587 FRAG_NEVER = 0x00000000, 16588 FRAG_LESS = 0x00000001, 16589 FRAG_EQUAL = 0x00000002, 16590 FRAG_LEQUAL = 0x00000003, 16591 FRAG_GREATER = 0x00000004, 16592 FRAG_NOTEQUAL = 0x00000005, 16593 FRAG_GEQUAL = 0x00000006, 16594 FRAG_ALWAYS = 0x00000007, 16595 } CompareFrag; 16596 16597 /* 16598 * StencilOp enum 16599 */ 16600 16601 typedef enum StencilOp { 16602 STENCIL_KEEP = 0x00000000, 16603 STENCIL_ZERO = 0x00000001, 16604 STENCIL_ONES = 0x00000002, 16605 STENCIL_REPLACE_TEST = 0x00000003, 16606 STENCIL_REPLACE_OP = 0x00000004, 16607 STENCIL_ADD_CLAMP = 0x00000005, 16608 STENCIL_SUB_CLAMP = 0x00000006, 16609 STENCIL_INVERT = 0x00000007, 16610 STENCIL_ADD_WRAP = 0x00000008, 16611 STENCIL_SUB_WRAP = 0x00000009, 16612 STENCIL_AND = 0x0000000a, 16613 STENCIL_OR = 0x0000000b, 16614 STENCIL_XOR = 0x0000000c, 16615 STENCIL_NAND = 0x0000000d, 16616 STENCIL_NOR = 0x0000000e, 16617 STENCIL_XNOR = 0x0000000f, 16618 } StencilOp; 16619 16620 /* 16621 * ConservativeZExport enum 16622 */ 16623 16624 typedef enum ConservativeZExport { 16625 EXPORT_ANY_Z = 0x00000000, 16626 EXPORT_LESS_THAN_Z = 0x00000001, 16627 EXPORT_GREATER_THAN_Z = 0x00000002, 16628 EXPORT_RESERVED = 0x00000003, 16629 } ConservativeZExport; 16630 16631 /* 16632 * DbPSLControl enum 16633 */ 16634 16635 typedef enum DbPSLControl { 16636 PSLC_AUTO = 0x00000000, 16637 PSLC_ON_HANG_ONLY = 0x00000001, 16638 PSLC_ASAP = 0x00000002, 16639 PSLC_COUNTDOWN = 0x00000003, 16640 } DbPSLControl; 16641 16642 /* 16643 * DbPRTFaultBehavior enum 16644 */ 16645 16646 typedef enum DbPRTFaultBehavior { 16647 FAULT_ZERO = 0x00000000, 16648 FAULT_ONE = 0x00000001, 16649 FAULT_FAIL = 0x00000002, 16650 FAULT_PASS = 0x00000003, 16651 } DbPRTFaultBehavior; 16652 16653 /* 16654 * PerfCounter_Vals enum 16655 */ 16656 16657 typedef enum PerfCounter_Vals { 16658 DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, 16659 DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, 16660 DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, 16661 DB_PERF_SEL_SC_DB_tile_events = 0x00000003, 16662 DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, 16663 DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, 16664 DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, 16665 DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, 16666 DB_PERF_SEL_hiz_tile_culled = 0x00000008, 16667 DB_PERF_SEL_his_tile_culled = 0x00000009, 16668 DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, 16669 DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, 16670 DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, 16671 DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, 16672 DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, 16673 DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, 16674 DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, 16675 DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, 16676 DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, 16677 DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, 16678 DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, 16679 DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, 16680 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, 16681 DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, 16682 DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, 16683 DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, 16684 DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, 16685 DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, 16686 DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, 16687 DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, 16688 DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, 16689 DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, 16690 DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020, 16691 DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021, 16692 DB_PERF_SEL_DB_CB_tile_sends = 0x00000022, 16693 DB_PERF_SEL_DB_CB_tile_busy = 0x00000023, 16694 DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024, 16695 DB_PERF_SEL_SX_DB_quad_sends = 0x00000025, 16696 DB_PERF_SEL_SX_DB_quad_busy = 0x00000026, 16697 DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027, 16698 DB_PERF_SEL_SX_DB_quad_quads = 0x00000028, 16699 DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029, 16700 DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a, 16701 DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b, 16702 DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c, 16703 DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d, 16704 DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e, 16705 DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f, 16706 DB_PERF_SEL_tile_rd_sends = 0x00000030, 16707 DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031, 16708 DB_PERF_SEL_quad_rd_sends = 0x00000032, 16709 DB_PERF_SEL_quad_rd_busy = 0x00000033, 16710 DB_PERF_SEL_quad_rd_mi_stall = 0x00000034, 16711 DB_PERF_SEL_quad_rd_rw_collision = 0x00000035, 16712 DB_PERF_SEL_quad_rd_tag_stall = 0x00000036, 16713 DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037, 16714 DB_PERF_SEL_quad_rd_panic = 0x00000038, 16715 DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039, 16716 DB_PERF_SEL_quad_rdret_sends = 0x0000003a, 16717 DB_PERF_SEL_quad_rdret_busy = 0x0000003b, 16718 DB_PERF_SEL_tile_wr_sends = 0x0000003c, 16719 DB_PERF_SEL_tile_wr_acks = 0x0000003d, 16720 DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e, 16721 DB_PERF_SEL_quad_wr_sends = 0x0000003f, 16722 DB_PERF_SEL_quad_wr_busy = 0x00000040, 16723 DB_PERF_SEL_quad_wr_mi_stall = 0x00000041, 16724 DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042, 16725 DB_PERF_SEL_quad_wr_acks = 0x00000043, 16726 DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044, 16727 DB_PERF_SEL_Tile_Cache_misses = 0x00000045, 16728 DB_PERF_SEL_Tile_Cache_hits = 0x00000046, 16729 DB_PERF_SEL_Tile_Cache_flushes = 0x00000047, 16730 DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048, 16731 DB_PERF_SEL_Tile_Cache_starves = 0x00000049, 16732 DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a, 16733 DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b, 16734 DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c, 16735 DB_PERF_SEL_tcp_preloader_reads = 0x0000004d, 16736 DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e, 16737 DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f, 16738 DB_PERF_SEL_tcp_preloader_flushes = 0x00000050, 16739 DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051, 16740 DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052, 16741 DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053, 16742 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054, 16743 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055, 16744 DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056, 16745 DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057, 16746 DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058, 16747 DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059, 16748 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a, 16749 DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b, 16750 DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c, 16751 DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d, 16752 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e, 16753 DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f, 16754 DB_PERF_SEL_Stencil_Cache_hits = 0x00000060, 16755 DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061, 16756 DB_PERF_SEL_Stencil_Cache_starves = 0x00000062, 16757 DB_PERF_SEL_Stencil_Cache_frees = 0x00000063, 16758 DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064, 16759 DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065, 16760 DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066, 16761 DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067, 16762 DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068, 16763 DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069, 16764 DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a, 16765 DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b, 16766 DB_PERF_SEL_Z_Cache_frees = 0x0000006c, 16767 DB_PERF_SEL_Plane_Cache_misses = 0x0000006d, 16768 DB_PERF_SEL_Plane_Cache_hits = 0x0000006e, 16769 DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f, 16770 DB_PERF_SEL_Plane_Cache_starves = 0x00000070, 16771 DB_PERF_SEL_Plane_Cache_frees = 0x00000071, 16772 DB_PERF_SEL_flush_expanded_stencil = 0x00000072, 16773 DB_PERF_SEL_flush_compressed_stencil = 0x00000073, 16774 DB_PERF_SEL_flush_single_stencil = 0x00000074, 16775 DB_PERF_SEL_planes_flushed = 0x00000075, 16776 DB_PERF_SEL_flush_1plane = 0x00000076, 16777 DB_PERF_SEL_flush_2plane = 0x00000077, 16778 DB_PERF_SEL_flush_3plane = 0x00000078, 16779 DB_PERF_SEL_flush_4plane = 0x00000079, 16780 DB_PERF_SEL_flush_5plane = 0x0000007a, 16781 DB_PERF_SEL_flush_6plane = 0x0000007b, 16782 DB_PERF_SEL_flush_7plane = 0x0000007c, 16783 DB_PERF_SEL_flush_8plane = 0x0000007d, 16784 DB_PERF_SEL_flush_9plane = 0x0000007e, 16785 DB_PERF_SEL_flush_10plane = 0x0000007f, 16786 DB_PERF_SEL_flush_11plane = 0x00000080, 16787 DB_PERF_SEL_flush_12plane = 0x00000081, 16788 DB_PERF_SEL_flush_13plane = 0x00000082, 16789 DB_PERF_SEL_flush_14plane = 0x00000083, 16790 DB_PERF_SEL_flush_15plane = 0x00000084, 16791 DB_PERF_SEL_flush_16plane = 0x00000085, 16792 DB_PERF_SEL_flush_expanded_z = 0x00000086, 16793 DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087, 16794 DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088, 16795 DB_PERF_SEL_dk_tile_sends = 0x00000089, 16796 DB_PERF_SEL_dk_tile_busy = 0x0000008a, 16797 DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b, 16798 DB_PERF_SEL_dk_tile_stalls = 0x0000008c, 16799 DB_PERF_SEL_dk_squad_sends = 0x0000008d, 16800 DB_PERF_SEL_dk_squad_busy = 0x0000008e, 16801 DB_PERF_SEL_dk_squad_stalls = 0x0000008f, 16802 DB_PERF_SEL_Op_Pipe_Busy = 0x00000090, 16803 DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091, 16804 DB_PERF_SEL_qc_busy = 0x00000092, 16805 DB_PERF_SEL_qc_xfc = 0x00000093, 16806 DB_PERF_SEL_qc_conflicts = 0x00000094, 16807 DB_PERF_SEL_qc_full_stall = 0x00000095, 16808 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096, 16809 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097, 16810 DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098, 16811 DB_PERF_SEL_tl_busy = 0x00000099, 16812 DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a, 16813 DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b, 16814 DB_PERF_SEL_tl_stencil_stall = 0x0000009c, 16815 DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d, 16816 DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e, 16817 DB_PERF_SEL_tl_events = 0x0000009f, 16818 DB_PERF_SEL_tl_summarize_squads = 0x000000a0, 16819 DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1, 16820 DB_PERF_SEL_tl_expand_squads = 0x000000a2, 16821 DB_PERF_SEL_tl_preZ_squads = 0x000000a3, 16822 DB_PERF_SEL_tl_postZ_squads = 0x000000a4, 16823 DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5, 16824 DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6, 16825 DB_PERF_SEL_tl_tile_ops = 0x000000a7, 16826 DB_PERF_SEL_tl_in_xfc = 0x000000a8, 16827 DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9, 16828 DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa, 16829 DB_PERF_SEL_tl_out_xfc = 0x000000ab, 16830 DB_PERF_SEL_tl_out_squads = 0x000000ac, 16831 DB_PERF_SEL_zf_plane_multicycle = 0x000000ad, 16832 DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae, 16833 DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af, 16834 DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0, 16835 DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1, 16836 DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2, 16837 DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3, 16838 DB_PERF_SEL_ts_tc_update_stall = 0x000000b4, 16839 DB_PERF_SEL_sc_kick_start = 0x000000b5, 16840 DB_PERF_SEL_sc_kick_end = 0x000000b6, 16841 DB_PERF_SEL_clock_reg_active = 0x000000b7, 16842 DB_PERF_SEL_clock_main_active = 0x000000b8, 16843 DB_PERF_SEL_clock_mem_export_active = 0x000000b9, 16844 DB_PERF_SEL_esr_ps_out_busy = 0x000000ba, 16845 DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb, 16846 DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc, 16847 DB_PERF_SEL_etr_out_send = 0x000000bd, 16848 DB_PERF_SEL_etr_out_busy = 0x000000be, 16849 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf, 16850 DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0, 16851 DB_PERF_SEL_etr_out_esr_stall = 0x000000c1, 16852 DB_PERF_SEL_esr_ps_sqq_busy = 0x000000c2, 16853 DB_PERF_SEL_esr_ps_sqq_stall = 0x000000c3, 16854 DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4, 16855 DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5, 16856 DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6, 16857 DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7, 16858 DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8, 16859 DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9, 16860 DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca, 16861 DB_PERF_SEL_postzl_se_busy = 0x000000cb, 16862 DB_PERF_SEL_postzl_se_stall = 0x000000cc, 16863 DB_PERF_SEL_postzl_partial_launch = 0x000000cd, 16864 DB_PERF_SEL_postzl_full_launch = 0x000000ce, 16865 DB_PERF_SEL_postzl_partial_waiting = 0x000000cf, 16866 DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0, 16867 DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1, 16868 DB_PERF_SEL_prezl_tile_mem_stall = 0x000000d2, 16869 DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3, 16870 DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4, 16871 DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5, 16872 DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6, 16873 DB_PERF_SEL_mi_rdreq_busy = 0x000000d7, 16874 DB_PERF_SEL_mi_rdreq_stall = 0x000000d8, 16875 DB_PERF_SEL_mi_wrreq_busy = 0x000000d9, 16876 DB_PERF_SEL_mi_wrreq_stall = 0x000000da, 16877 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db, 16878 DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc, 16879 DB_PERF_SEL_prezl_src_in_sends = 0x000000dd, 16880 DB_PERF_SEL_prezl_src_in_stall = 0x000000de, 16881 DB_PERF_SEL_prezl_src_in_squads = 0x000000df, 16882 DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0, 16883 DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1, 16884 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2, 16885 DB_PERF_SEL_prezl_src_out_stall = 0x000000e3, 16886 DB_PERF_SEL_postzl_src_in_sends = 0x000000e4, 16887 DB_PERF_SEL_postzl_src_in_stall = 0x000000e5, 16888 DB_PERF_SEL_postzl_src_in_squads = 0x000000e6, 16889 DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7, 16890 DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8, 16891 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9, 16892 DB_PERF_SEL_postzl_src_out_stall = 0x000000ea, 16893 DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb, 16894 DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec, 16895 DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed, 16896 DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee, 16897 DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef, 16898 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0, 16899 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1, 16900 DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2, 16901 DB_PERF_SEL_depth_bounds_tile_culled = 0x000000f3, 16902 DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4, 16903 DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5, 16904 DB_PERF_SEL_flush_compressed = 0x000000f6, 16905 DB_PERF_SEL_flush_plane_le4 = 0x000000f7, 16906 DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8, 16907 DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9, 16908 DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa, 16909 DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb, 16910 DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc, 16911 DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd, 16912 DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe, 16913 DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff, 16914 DB_PERF_SEL_di_dt_stall = 0x00000100, 16915 DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke = 0x00000101, 16916 DB_PERF_SEL_DB_SC_s_tile_rate = 0x00000102, 16917 DB_PERF_SEL_DB_SC_c_tile_rate = 0x00000103, 16918 DB_PERF_SEL_DB_SC_z_tile_rate = 0x00000104, 16919 Spare_261 = 0x00000105, 16920 DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000106, 16921 DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000107, 16922 DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000108, 16923 DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000109, 16924 DB_PERF_SEL_CB_DB_rdreq_sends = 0x0000010a, 16925 DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010b, 16926 DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010c, 16927 DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010d, 16928 DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010e, 16929 DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010f, 16930 DB_PERF_SEL_DB_CB_wrret_ack = 0x00000110, 16931 DB_PERF_SEL_DB_CB_wrret_nack = 0x00000111, 16932 DB_PERF_SEL_DFSM_Stall_opmode_change = 0x00000112, 16933 DB_PERF_SEL_DFSM_Stall_cam_fifo = 0x00000113, 16934 DB_PERF_SEL_DFSM_Stall_bypass_fifo = 0x00000114, 16935 DB_PERF_SEL_DFSM_Stall_retained_tile_fifo = 0x00000115, 16936 DB_PERF_SEL_DFSM_Stall_control_fifo = 0x00000116, 16937 DB_PERF_SEL_DFSM_Stall_overflow_counter = 0x00000117, 16938 DB_PERF_SEL_DFSM_Stall_pops_stall_overflow = 0x00000118, 16939 DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush = 0x00000119, 16940 DB_PERF_SEL_DFSM_Stall_middle_output = 0x0000011a, 16941 DB_PERF_SEL_DFSM_Stall_stalling_general = 0x0000011b, 16942 Spare_285 = 0x0000011c, 16943 Spare_286 = 0x0000011d, 16944 DB_PERF_SEL_DFSM_prez_killed_squad = 0x0000011e, 16945 DB_PERF_SEL_DFSM_squads_in = 0x0000011f, 16946 DB_PERF_SEL_DFSM_full_cleared_squads_out = 0x00000120, 16947 DB_PERF_SEL_DFSM_quads_in = 0x00000121, 16948 DB_PERF_SEL_DFSM_fully_cleared_quads_out = 0x00000122, 16949 DB_PERF_SEL_DFSM_lit_pixels_in = 0x00000123, 16950 DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 0x00000124, 16951 DB_PERF_SEL_DFSM_lit_samples_in = 0x00000125, 16952 DB_PERF_SEL_DFSM_lit_samples_out = 0x00000126, 16953 DB_PERF_SEL_DFSM_evicted_tiles_above_watermark = 0x00000127, 16954 DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 0x00000128, 16955 DB_PERF_SEL_DFSM_stalled_by_downstream = 0x00000129, 16956 DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 0x0000012a, 16957 DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 0x0000012b, 16958 DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 0x0000012c, 16959 DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 0x0000012d, 16960 DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x0000012e, 16961 DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x0000012f, 16962 DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000130, 16963 DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000131, 16964 DB_PERF_SEL_unmapped_z_tile_culled = 0x00000132, 16965 DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000133, 16966 DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000134, 16967 DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 0x00000135, 16968 DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 0x00000136, 16969 DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 0x00000137, 16970 DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 0x00000138, 16971 DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 0x00000139, 16972 DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 0x0000013a, 16973 DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 0x0000013b, 16974 DB_PERF_SEL_DB_CB_context_dones = 0x0000013c, 16975 DB_PERF_SEL_DB_CB_eop_dones = 0x0000013d, 16976 DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x0000013e, 16977 DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x0000013f, 16978 DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000140, 16979 DB_PERF_SEL_SC_DB_tile_backface = 0x00000141, 16980 DB_PERF_SEL_SC_DB_quad_quads = 0x00000142, 16981 DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000143, 16982 DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000144, 16983 DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000145, 16984 DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000146, 16985 DB_PERF_SEL_DFSM_Flush_flushabit = 0x00000147, 16986 DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo = 0x00000148, 16987 DB_PERF_SEL_DFSM_Flush_flushabit_passthrough = 0x00000149, 16988 DB_PERF_SEL_DFSM_Flush_flushabit_forceflush = 0x0000014a, 16989 DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull = 0x0000014b, 16990 DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark = 0x0000014c, 16991 DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling = 0x0000014d, 16992 DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark = 0x0000014e, 16993 DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark = 0x0000014f, 16994 DB_PERF_SEL_DFSM_Flush_flushall = 0x00000150, 16995 DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush = 0x00000151, 16996 DB_PERF_SEL_DFSM_Flush_flushall_opmodechange = 0x00000152, 16997 DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange = 0x00000153, 16998 DB_PERF_SEL_DFSM_Flush_flushall_watchdog = 0x00000154, 16999 DB_PERF_SEL_DB_SC_quad_double_quad = 0x00000155, 17000 DB_PERF_SEL_SX_DB_quad_export_quads = 0x00000156, 17001 DB_PERF_SEL_SX_DB_quad_double_format = 0x00000157, 17002 DB_PERF_SEL_SX_DB_quad_fast_format = 0x00000158, 17003 DB_PERF_SEL_SX_DB_quad_slow_format = 0x00000159, 17004 } PerfCounter_Vals; 17005 17006 /* 17007 * RingCounterControl enum 17008 */ 17009 17010 typedef enum RingCounterControl { 17011 COUNTER_RING_SPLIT = 0x00000000, 17012 COUNTER_RING_0 = 0x00000001, 17013 COUNTER_RING_1 = 0x00000002, 17014 } RingCounterControl; 17015 17016 /* 17017 * DbMemArbWatermarks enum 17018 */ 17019 17020 typedef enum DbMemArbWatermarks { 17021 TRANSFERRED_64_BYTES = 0x00000000, 17022 TRANSFERRED_128_BYTES = 0x00000001, 17023 TRANSFERRED_256_BYTES = 0x00000002, 17024 TRANSFERRED_512_BYTES = 0x00000003, 17025 TRANSFERRED_1024_BYTES = 0x00000004, 17026 TRANSFERRED_2048_BYTES = 0x00000005, 17027 TRANSFERRED_4096_BYTES = 0x00000006, 17028 TRANSFERRED_8192_BYTES = 0x00000007, 17029 } DbMemArbWatermarks; 17030 17031 /* 17032 * DFSMFlushEvents enum 17033 */ 17034 17035 typedef enum DFSMFlushEvents { 17036 DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000, 17037 DB_FLUSH_AND_INV_DB_META = 0x00000001, 17038 DB_CACHE_FLUSH = 0x00000002, 17039 DB_CACHE_FLUSH_TS = 0x00000003, 17040 DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004, 17041 DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005, 17042 DB_VPORT_CHANGED_EVENT = 0x00000006, 17043 DB_CONTEXT_DONE_EVENT = 0x00000007, 17044 DB_BREAK_BATCH_EVENT = 0x00000008, 17045 DB_PSINVOKE_CHANGE_EVENT = 0x00000009, 17046 DB_CONTEXT_SUSPEND_EVENT = 0x0000000a, 17047 } DFSMFlushEvents; 17048 17049 /* 17050 * PixelPipeCounterId enum 17051 */ 17052 17053 typedef enum PixelPipeCounterId { 17054 PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, 17055 PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, 17056 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, 17057 PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, 17058 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004, 17059 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005, 17060 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006, 17061 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007, 17062 } PixelPipeCounterId; 17063 17064 /* 17065 * PixelPipeStride enum 17066 */ 17067 17068 typedef enum PixelPipeStride { 17069 PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, 17070 PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, 17071 PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, 17072 PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, 17073 } PixelPipeStride; 17074 17075 /* 17076 * FullTileWaveBreak enum 17077 */ 17078 17079 typedef enum FullTileWaveBreak { 17080 FULL_TILE_WAVE_BREAK_NBC_ONLY = 0x00000000, 17081 FULL_TILE_WAVE_BREAK_BOTH = 0x00000001, 17082 FULL_TILE_WAVE_BREAK_NONE = 0x00000002, 17083 FULL_TILE_WAVE_BREAK_BC_ONLY = 0x00000003, 17084 } FullTileWaveBreak; 17085 17086 /******************************************************* 17087 * TA Enums 17088 *******************************************************/ 17089 17090 /* 17091 * TEX_BORDER_COLOR_TYPE enum 17092 */ 17093 17094 typedef enum TEX_BORDER_COLOR_TYPE { 17095 TEX_BorderColor_TransparentBlack = 0x00000000, 17096 TEX_BorderColor_OpaqueBlack = 0x00000001, 17097 TEX_BorderColor_OpaqueWhite = 0x00000002, 17098 TEX_BorderColor_Register = 0x00000003, 17099 } TEX_BORDER_COLOR_TYPE; 17100 17101 /* 17102 * TEX_BC_SWIZZLE enum 17103 */ 17104 17105 typedef enum TEX_BC_SWIZZLE { 17106 TEX_BC_Swizzle_XYZW = 0x00000000, 17107 TEX_BC_Swizzle_XWYZ = 0x00000001, 17108 TEX_BC_Swizzle_WZYX = 0x00000002, 17109 TEX_BC_Swizzle_WXYZ = 0x00000003, 17110 TEX_BC_Swizzle_ZYXW = 0x00000004, 17111 TEX_BC_Swizzle_YXWZ = 0x00000005, 17112 } TEX_BC_SWIZZLE; 17113 17114 /* 17115 * TEX_CHROMA_KEY enum 17116 */ 17117 17118 typedef enum TEX_CHROMA_KEY { 17119 TEX_ChromaKey_Disabled = 0x00000000, 17120 TEX_ChromaKey_Kill = 0x00000001, 17121 TEX_ChromaKey_Blend = 0x00000002, 17122 TEX_ChromaKey_RESERVED_3 = 0x00000003, 17123 } TEX_CHROMA_KEY; 17124 17125 /* 17126 * TEX_CLAMP enum 17127 */ 17128 17129 typedef enum TEX_CLAMP { 17130 TEX_Clamp_Repeat = 0x00000000, 17131 TEX_Clamp_Mirror = 0x00000001, 17132 TEX_Clamp_ClampToLast = 0x00000002, 17133 TEX_Clamp_MirrorOnceToLast = 0x00000003, 17134 TEX_Clamp_ClampHalfToBorder = 0x00000004, 17135 TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, 17136 TEX_Clamp_ClampToBorder = 0x00000006, 17137 TEX_Clamp_MirrorOnceToBorder = 0x00000007, 17138 } TEX_CLAMP; 17139 17140 /* 17141 * TEX_COORD_TYPE enum 17142 */ 17143 17144 typedef enum TEX_COORD_TYPE { 17145 TEX_CoordType_Unnormalized = 0x00000000, 17146 TEX_CoordType_Normalized = 0x00000001, 17147 } TEX_COORD_TYPE; 17148 17149 /* 17150 * TEX_DEPTH_COMPARE_FUNCTION enum 17151 */ 17152 17153 typedef enum TEX_DEPTH_COMPARE_FUNCTION { 17154 TEX_DepthCompareFunction_Never = 0x00000000, 17155 TEX_DepthCompareFunction_Less = 0x00000001, 17156 TEX_DepthCompareFunction_Equal = 0x00000002, 17157 TEX_DepthCompareFunction_LessEqual = 0x00000003, 17158 TEX_DepthCompareFunction_Greater = 0x00000004, 17159 TEX_DepthCompareFunction_NotEqual = 0x00000005, 17160 TEX_DepthCompareFunction_GreaterEqual = 0x00000006, 17161 TEX_DepthCompareFunction_Always = 0x00000007, 17162 } TEX_DEPTH_COMPARE_FUNCTION; 17163 17164 /* 17165 * TEX_DIM enum 17166 */ 17167 17168 typedef enum TEX_DIM { 17169 TEX_Dim_1D = 0x00000000, 17170 TEX_Dim_2D = 0x00000001, 17171 TEX_Dim_3D = 0x00000002, 17172 TEX_Dim_CubeMap = 0x00000003, 17173 TEX_Dim_1DArray = 0x00000004, 17174 TEX_Dim_2DArray = 0x00000005, 17175 TEX_Dim_2D_MSAA = 0x00000006, 17176 TEX_Dim_2DArray_MSAA = 0x00000007, 17177 } TEX_DIM; 17178 17179 /* 17180 * TEX_FORMAT_COMP enum 17181 */ 17182 17183 typedef enum TEX_FORMAT_COMP { 17184 TEX_FormatComp_Unsigned = 0x00000000, 17185 TEX_FormatComp_Signed = 0x00000001, 17186 TEX_FormatComp_UnsignedBiased = 0x00000002, 17187 TEX_FormatComp_RESERVED_3 = 0x00000003, 17188 } TEX_FORMAT_COMP; 17189 17190 /* 17191 * TEX_MAX_ANISO_RATIO enum 17192 */ 17193 17194 typedef enum TEX_MAX_ANISO_RATIO { 17195 TEX_MaxAnisoRatio_1to1 = 0x00000000, 17196 TEX_MaxAnisoRatio_2to1 = 0x00000001, 17197 TEX_MaxAnisoRatio_4to1 = 0x00000002, 17198 TEX_MaxAnisoRatio_8to1 = 0x00000003, 17199 TEX_MaxAnisoRatio_16to1 = 0x00000004, 17200 TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, 17201 TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, 17202 TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, 17203 } TEX_MAX_ANISO_RATIO; 17204 17205 /* 17206 * TEX_MIP_FILTER enum 17207 */ 17208 17209 typedef enum TEX_MIP_FILTER { 17210 TEX_MipFilter_None = 0x00000000, 17211 TEX_MipFilter_Point = 0x00000001, 17212 TEX_MipFilter_Linear = 0x00000002, 17213 TEX_MipFilter_Point_Aniso_Adj = 0x00000003, 17214 } TEX_MIP_FILTER; 17215 17216 /* 17217 * TEX_REQUEST_SIZE enum 17218 */ 17219 17220 typedef enum TEX_REQUEST_SIZE { 17221 TEX_RequestSize_32B = 0x00000000, 17222 TEX_RequestSize_64B = 0x00000001, 17223 TEX_RequestSize_128B = 0x00000002, 17224 TEX_RequestSize_2X64B = 0x00000003, 17225 } TEX_REQUEST_SIZE; 17226 17227 /* 17228 * TEX_SAMPLER_TYPE enum 17229 */ 17230 17231 typedef enum TEX_SAMPLER_TYPE { 17232 TEX_SamplerType_Invalid = 0x00000000, 17233 TEX_SamplerType_Valid = 0x00000001, 17234 } TEX_SAMPLER_TYPE; 17235 17236 /* 17237 * TEX_XY_FILTER enum 17238 */ 17239 17240 typedef enum TEX_XY_FILTER { 17241 TEX_XYFilter_Point = 0x00000000, 17242 TEX_XYFilter_Linear = 0x00000001, 17243 TEX_XYFilter_AnisoPoint = 0x00000002, 17244 TEX_XYFilter_AnisoLinear = 0x00000003, 17245 } TEX_XY_FILTER; 17246 17247 /* 17248 * TEX_Z_FILTER enum 17249 */ 17250 17251 typedef enum TEX_Z_FILTER { 17252 TEX_ZFilter_None = 0x00000000, 17253 TEX_ZFilter_Point = 0x00000001, 17254 TEX_ZFilter_Linear = 0x00000002, 17255 TEX_ZFilter_RESERVED_3 = 0x00000003, 17256 } TEX_Z_FILTER; 17257 17258 /* 17259 * VTX_CLAMP enum 17260 */ 17261 17262 typedef enum VTX_CLAMP { 17263 VTX_Clamp_ClampToZero = 0x00000000, 17264 VTX_Clamp_ClampToNAN = 0x00000001, 17265 } VTX_CLAMP; 17266 17267 /* 17268 * VTX_FETCH_TYPE enum 17269 */ 17270 17271 typedef enum VTX_FETCH_TYPE { 17272 VTX_FetchType_VertexData = 0x00000000, 17273 VTX_FetchType_InstanceData = 0x00000001, 17274 VTX_FetchType_NoIndexOffset = 0x00000002, 17275 VTX_FetchType_RESERVED_3 = 0x00000003, 17276 } VTX_FETCH_TYPE; 17277 17278 /* 17279 * VTX_FORMAT_COMP_ALL enum 17280 */ 17281 17282 typedef enum VTX_FORMAT_COMP_ALL { 17283 VTX_FormatCompAll_Unsigned = 0x00000000, 17284 VTX_FormatCompAll_Signed = 0x00000001, 17285 } VTX_FORMAT_COMP_ALL; 17286 17287 /* 17288 * VTX_MEM_REQUEST_SIZE enum 17289 */ 17290 17291 typedef enum VTX_MEM_REQUEST_SIZE { 17292 VTX_MemRequestSize_32B = 0x00000000, 17293 VTX_MemRequestSize_64B = 0x00000001, 17294 } VTX_MEM_REQUEST_SIZE; 17295 17296 /* 17297 * TVX_DATA_FORMAT enum 17298 */ 17299 17300 typedef enum TVX_DATA_FORMAT { 17301 TVX_FMT_INVALID = 0x00000000, 17302 TVX_FMT_8 = 0x00000001, 17303 TVX_FMT_4_4 = 0x00000002, 17304 TVX_FMT_3_3_2 = 0x00000003, 17305 TVX_FMT_RESERVED_4 = 0x00000004, 17306 TVX_FMT_16 = 0x00000005, 17307 TVX_FMT_16_FLOAT = 0x00000006, 17308 TVX_FMT_8_8 = 0x00000007, 17309 TVX_FMT_5_6_5 = 0x00000008, 17310 TVX_FMT_6_5_5 = 0x00000009, 17311 TVX_FMT_1_5_5_5 = 0x0000000a, 17312 TVX_FMT_4_4_4_4 = 0x0000000b, 17313 TVX_FMT_5_5_5_1 = 0x0000000c, 17314 TVX_FMT_32 = 0x0000000d, 17315 TVX_FMT_32_FLOAT = 0x0000000e, 17316 TVX_FMT_16_16 = 0x0000000f, 17317 TVX_FMT_16_16_FLOAT = 0x00000010, 17318 TVX_FMT_8_24 = 0x00000011, 17319 TVX_FMT_8_24_FLOAT = 0x00000012, 17320 TVX_FMT_24_8 = 0x00000013, 17321 TVX_FMT_24_8_FLOAT = 0x00000014, 17322 TVX_FMT_10_11_11 = 0x00000015, 17323 TVX_FMT_10_11_11_FLOAT = 0x00000016, 17324 TVX_FMT_11_11_10 = 0x00000017, 17325 TVX_FMT_11_11_10_FLOAT = 0x00000018, 17326 TVX_FMT_2_10_10_10 = 0x00000019, 17327 TVX_FMT_8_8_8_8 = 0x0000001a, 17328 TVX_FMT_10_10_10_2 = 0x0000001b, 17329 TVX_FMT_X24_8_32_FLOAT = 0x0000001c, 17330 TVX_FMT_32_32 = 0x0000001d, 17331 TVX_FMT_32_32_FLOAT = 0x0000001e, 17332 TVX_FMT_16_16_16_16 = 0x0000001f, 17333 TVX_FMT_16_16_16_16_FLOAT = 0x00000020, 17334 TVX_FMT_RESERVED_33 = 0x00000021, 17335 TVX_FMT_32_32_32_32 = 0x00000022, 17336 TVX_FMT_32_32_32_32_FLOAT = 0x00000023, 17337 TVX_FMT_RESERVED_36 = 0x00000024, 17338 TVX_FMT_1 = 0x00000025, 17339 TVX_FMT_1_REVERSED = 0x00000026, 17340 TVX_FMT_GB_GR = 0x00000027, 17341 TVX_FMT_BG_RG = 0x00000028, 17342 TVX_FMT_32_AS_8 = 0x00000029, 17343 TVX_FMT_32_AS_8_8 = 0x0000002a, 17344 TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b, 17345 TVX_FMT_8_8_8 = 0x0000002c, 17346 TVX_FMT_16_16_16 = 0x0000002d, 17347 TVX_FMT_16_16_16_FLOAT = 0x0000002e, 17348 TVX_FMT_32_32_32 = 0x0000002f, 17349 TVX_FMT_32_32_32_FLOAT = 0x00000030, 17350 TVX_FMT_BC1 = 0x00000031, 17351 TVX_FMT_BC2 = 0x00000032, 17352 TVX_FMT_BC3 = 0x00000033, 17353 TVX_FMT_BC4 = 0x00000034, 17354 TVX_FMT_BC5 = 0x00000035, 17355 TVX_FMT_APC0 = 0x00000036, 17356 TVX_FMT_APC1 = 0x00000037, 17357 TVX_FMT_APC2 = 0x00000038, 17358 TVX_FMT_APC3 = 0x00000039, 17359 TVX_FMT_APC4 = 0x0000003a, 17360 TVX_FMT_APC5 = 0x0000003b, 17361 TVX_FMT_APC6 = 0x0000003c, 17362 TVX_FMT_APC7 = 0x0000003d, 17363 TVX_FMT_CTX1 = 0x0000003e, 17364 TVX_FMT_RESERVED_63 = 0x0000003f, 17365 } TVX_DATA_FORMAT; 17366 17367 /* 17368 * TVX_DST_SEL enum 17369 */ 17370 17371 typedef enum TVX_DST_SEL { 17372 TVX_DstSel_X = 0x00000000, 17373 TVX_DstSel_Y = 0x00000001, 17374 TVX_DstSel_Z = 0x00000002, 17375 TVX_DstSel_W = 0x00000003, 17376 TVX_DstSel_0f = 0x00000004, 17377 TVX_DstSel_1f = 0x00000005, 17378 TVX_DstSel_RESERVED_6 = 0x00000006, 17379 TVX_DstSel_Mask = 0x00000007, 17380 } TVX_DST_SEL; 17381 17382 /* 17383 * TVX_ENDIAN_SWAP enum 17384 */ 17385 17386 typedef enum TVX_ENDIAN_SWAP { 17387 TVX_EndianSwap_None = 0x00000000, 17388 TVX_EndianSwap_8in16 = 0x00000001, 17389 TVX_EndianSwap_8in32 = 0x00000002, 17390 TVX_EndianSwap_8in64 = 0x00000003, 17391 } TVX_ENDIAN_SWAP; 17392 17393 /* 17394 * TVX_INST enum 17395 */ 17396 17397 typedef enum TVX_INST { 17398 TVX_Inst_NormalVertexFetch = 0x00000000, 17399 TVX_Inst_SemanticVertexFetch = 0x00000001, 17400 TVX_Inst_RESERVED_2 = 0x00000002, 17401 TVX_Inst_LD = 0x00000003, 17402 TVX_Inst_GetTextureResInfo = 0x00000004, 17403 TVX_Inst_GetNumberOfSamples = 0x00000005, 17404 TVX_Inst_GetLOD = 0x00000006, 17405 TVX_Inst_GetGradientsH = 0x00000007, 17406 TVX_Inst_GetGradientsV = 0x00000008, 17407 TVX_Inst_SetTextureOffsets = 0x00000009, 17408 TVX_Inst_KeepGradients = 0x0000000a, 17409 TVX_Inst_SetGradientsH = 0x0000000b, 17410 TVX_Inst_SetGradientsV = 0x0000000c, 17411 TVX_Inst_Pass = 0x0000000d, 17412 TVX_Inst_GetBufferResInfo = 0x0000000e, 17413 TVX_Inst_RESERVED_15 = 0x0000000f, 17414 TVX_Inst_Sample = 0x00000010, 17415 TVX_Inst_Sample_L = 0x00000011, 17416 TVX_Inst_Sample_LB = 0x00000012, 17417 TVX_Inst_Sample_LZ = 0x00000013, 17418 TVX_Inst_Sample_G = 0x00000014, 17419 TVX_Inst_Gather4 = 0x00000015, 17420 TVX_Inst_Sample_G_LB = 0x00000016, 17421 TVX_Inst_Gather4_O = 0x00000017, 17422 TVX_Inst_Sample_C = 0x00000018, 17423 TVX_Inst_Sample_C_L = 0x00000019, 17424 TVX_Inst_Sample_C_LB = 0x0000001a, 17425 TVX_Inst_Sample_C_LZ = 0x0000001b, 17426 TVX_Inst_Sample_C_G = 0x0000001c, 17427 TVX_Inst_Gather4_C = 0x0000001d, 17428 TVX_Inst_Sample_C_G_LB = 0x0000001e, 17429 TVX_Inst_Gather4_C_O = 0x0000001f, 17430 } TVX_INST; 17431 17432 /* 17433 * TVX_NUM_FORMAT_ALL enum 17434 */ 17435 17436 typedef enum TVX_NUM_FORMAT_ALL { 17437 TVX_NumFormatAll_Norm = 0x00000000, 17438 TVX_NumFormatAll_Int = 0x00000001, 17439 TVX_NumFormatAll_Scaled = 0x00000002, 17440 TVX_NumFormatAll_RESERVED_3 = 0x00000003, 17441 } TVX_NUM_FORMAT_ALL; 17442 17443 /* 17444 * TVX_SRC_SEL enum 17445 */ 17446 17447 typedef enum TVX_SRC_SEL { 17448 TVX_SrcSel_X = 0x00000000, 17449 TVX_SrcSel_Y = 0x00000001, 17450 TVX_SrcSel_Z = 0x00000002, 17451 TVX_SrcSel_W = 0x00000003, 17452 TVX_SrcSel_0f = 0x00000004, 17453 TVX_SrcSel_1f = 0x00000005, 17454 } TVX_SRC_SEL; 17455 17456 /* 17457 * TVX_SRF_MODE_ALL enum 17458 */ 17459 17460 typedef enum TVX_SRF_MODE_ALL { 17461 TVX_SRFModeAll_ZCMO = 0x00000000, 17462 TVX_SRFModeAll_NZ = 0x00000001, 17463 } TVX_SRF_MODE_ALL; 17464 17465 /* 17466 * TVX_TYPE enum 17467 */ 17468 17469 typedef enum TVX_TYPE { 17470 TVX_Type_InvalidTextureResource = 0x00000000, 17471 TVX_Type_InvalidVertexBuffer = 0x00000001, 17472 TVX_Type_ValidTextureResource = 0x00000002, 17473 TVX_Type_ValidVertexBuffer = 0x00000003, 17474 } TVX_TYPE; 17475 17476 /******************************************************* 17477 * PA Enums 17478 *******************************************************/ 17479 17480 /* 17481 * PH_PERFCNT_SEL enum 17482 */ 17483 17484 typedef enum PH_PERFCNT_SEL { 17485 PH_SC0_SRPS_WINDOW_VALID = 0x00000000, 17486 PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000001, 17487 PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 0x00000002, 17488 PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x00000003, 17489 PH_SC0_ARB_STALLED_FROM_BELOW = 0x00000004, 17490 PH_SC0_ARB_STARVED_FROM_ABOVE = 0x00000005, 17491 PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006, 17492 PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007, 17493 PH_SC0_ARB_BUSY = 0x00000008, 17494 PH_SC0_ARB_PA_BUSY_SOP = 0x00000009, 17495 PH_SC0_ARB_EOP_POP_SYNC_POP = 0x0000000a, 17496 PH_SC0_ARB_EVENT_SYNC_POP = 0x0000000b, 17497 PH_SC0_PS_ENG_MULTICYCLE_BUBBLE = 0x0000000c, 17498 PH_SC0_EOP_SYNC_WINDOW = 0x0000000d, 17499 PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x0000000e, 17500 PH_SC0_BUSY_CNT_NOT_ZERO = 0x0000000f, 17501 PH_SC0_SEND = 0x00000010, 17502 PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000011, 17503 PH_SC0_CREDIT_AT_MAX = 0x00000012, 17504 PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000013, 17505 PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000014, 17506 PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000015, 17507 PH_SC0_GFX_PIPE0_TO_1_TRANSITION = 0x00000016, 17508 PH_SC0_GFX_PIPE1_TO_0_TRANSITION = 0x00000017, 17509 PH_SC0_PA0_DATA_FIFO_RD = 0x00000018, 17510 PH_SC0_PA0_DATA_FIFO_WE = 0x00000019, 17511 PH_SC0_PA0_FIFO_EMPTY = 0x0000001a, 17512 PH_SC0_PA0_FIFO_FULL = 0x0000001b, 17513 PH_SC0_PA0_NULL_WE = 0x0000001c, 17514 PH_SC0_PA0_EVENT_WE = 0x0000001d, 17515 PH_SC0_PA0_FPOV_WE = 0x0000001e, 17516 PH_SC0_PA0_LPOV_WE = 0x0000001f, 17517 PH_SC0_PA0_EOP_WE = 0x00000020, 17518 PH_SC0_PA0_DATA_FIFO_EOP_RD = 0x00000021, 17519 PH_SC0_PA0_EOPG_WE = 0x00000022, 17520 PH_SC0_PA0_DEALLOC_4_0_RD = 0x00000023, 17521 PH_SC0_PA1_DATA_FIFO_RD = 0x00000024, 17522 PH_SC0_PA1_DATA_FIFO_WE = 0x00000025, 17523 PH_SC0_PA1_FIFO_EMPTY = 0x00000026, 17524 PH_SC0_PA1_FIFO_FULL = 0x00000027, 17525 PH_SC0_PA1_NULL_WE = 0x00000028, 17526 PH_SC0_PA1_EVENT_WE = 0x00000029, 17527 PH_SC0_PA1_FPOV_WE = 0x0000002a, 17528 PH_SC0_PA1_LPOV_WE = 0x0000002b, 17529 PH_SC0_PA1_EOP_WE = 0x0000002c, 17530 PH_SC0_PA1_DATA_FIFO_EOP_RD = 0x0000002d, 17531 PH_SC0_PA1_EOPG_WE = 0x0000002e, 17532 PH_SC0_PA1_DEALLOC_4_0_RD = 0x0000002f, 17533 PH_SC0_PA2_DATA_FIFO_RD = 0x00000030, 17534 PH_SC0_PA2_DATA_FIFO_WE = 0x00000031, 17535 PH_SC0_PA2_FIFO_EMPTY = 0x00000032, 17536 PH_SC0_PA2_FIFO_FULL = 0x00000033, 17537 PH_SC0_PA2_NULL_WE = 0x00000034, 17538 PH_SC0_PA2_EVENT_WE = 0x00000035, 17539 PH_SC0_PA2_FPOV_WE = 0x00000036, 17540 PH_SC0_PA2_LPOV_WE = 0x00000037, 17541 PH_SC0_PA2_EOP_WE = 0x00000038, 17542 PH_SC0_PA2_DATA_FIFO_EOP_RD = 0x00000039, 17543 PH_SC0_PA2_EOPG_WE = 0x0000003a, 17544 PH_SC0_PA2_DEALLOC_4_0_RD = 0x0000003b, 17545 PH_SC0_PA3_DATA_FIFO_RD = 0x0000003c, 17546 PH_SC0_PA3_DATA_FIFO_WE = 0x0000003d, 17547 PH_SC0_PA3_FIFO_EMPTY = 0x0000003e, 17548 PH_SC0_PA3_FIFO_FULL = 0x0000003f, 17549 PH_SC0_PA3_NULL_WE = 0x00000040, 17550 PH_SC0_PA3_EVENT_WE = 0x00000041, 17551 PH_SC0_PA3_FPOV_WE = 0x00000042, 17552 PH_SC0_PA3_LPOV_WE = 0x00000043, 17553 PH_SC0_PA3_EOP_WE = 0x00000044, 17554 PH_SC0_PA3_DATA_FIFO_EOP_RD = 0x00000045, 17555 PH_SC0_PA3_EOPG_WE = 0x00000046, 17556 PH_SC0_PA3_DEALLOC_4_0_RD = 0x00000047, 17557 PH_SC0_PA4_DATA_FIFO_RD = 0x00000048, 17558 PH_SC0_PA4_DATA_FIFO_WE = 0x00000049, 17559 PH_SC0_PA4_FIFO_EMPTY = 0x0000004a, 17560 PH_SC0_PA4_FIFO_FULL = 0x0000004b, 17561 PH_SC0_PA4_NULL_WE = 0x0000004c, 17562 PH_SC0_PA4_EVENT_WE = 0x0000004d, 17563 PH_SC0_PA4_FPOV_WE = 0x0000004e, 17564 PH_SC0_PA4_LPOV_WE = 0x0000004f, 17565 PH_SC0_PA4_EOP_WE = 0x00000050, 17566 PH_SC0_PA4_DATA_FIFO_EOP_RD = 0x00000051, 17567 PH_SC0_PA4_EOPG_WE = 0x00000052, 17568 PH_SC0_PA4_DEALLOC_4_0_RD = 0x00000053, 17569 PH_SC0_PA5_DATA_FIFO_RD = 0x00000054, 17570 PH_SC0_PA5_DATA_FIFO_WE = 0x00000055, 17571 PH_SC0_PA5_FIFO_EMPTY = 0x00000056, 17572 PH_SC0_PA5_FIFO_FULL = 0x00000057, 17573 PH_SC0_PA5_NULL_WE = 0x00000058, 17574 PH_SC0_PA5_EVENT_WE = 0x00000059, 17575 PH_SC0_PA5_FPOV_WE = 0x0000005a, 17576 PH_SC0_PA5_LPOV_WE = 0x0000005b, 17577 PH_SC0_PA5_EOP_WE = 0x0000005c, 17578 PH_SC0_PA5_DATA_FIFO_EOP_RD = 0x0000005d, 17579 PH_SC0_PA5_EOPG_WE = 0x0000005e, 17580 PH_SC0_PA5_DEALLOC_4_0_RD = 0x0000005f, 17581 PH_SC0_PA6_DATA_FIFO_RD = 0x00000060, 17582 PH_SC0_PA6_DATA_FIFO_WE = 0x00000061, 17583 PH_SC0_PA6_FIFO_EMPTY = 0x00000062, 17584 PH_SC0_PA6_FIFO_FULL = 0x00000063, 17585 PH_SC0_PA6_NULL_WE = 0x00000064, 17586 PH_SC0_PA6_EVENT_WE = 0x00000065, 17587 PH_SC0_PA6_FPOV_WE = 0x00000066, 17588 PH_SC0_PA6_LPOV_WE = 0x00000067, 17589 PH_SC0_PA6_EOP_WE = 0x00000068, 17590 PH_SC0_PA6_DATA_FIFO_EOP_RD = 0x00000069, 17591 PH_SC0_PA6_EOPG_WE = 0x0000006a, 17592 PH_SC0_PA6_DEALLOC_4_0_RD = 0x0000006b, 17593 PH_SC0_PA7_DATA_FIFO_RD = 0x0000006c, 17594 PH_SC0_PA7_DATA_FIFO_WE = 0x0000006d, 17595 PH_SC0_PA7_FIFO_EMPTY = 0x0000006e, 17596 PH_SC0_PA7_FIFO_FULL = 0x0000006f, 17597 PH_SC0_PA7_NULL_WE = 0x00000070, 17598 PH_SC0_PA7_EVENT_WE = 0x00000071, 17599 PH_SC0_PA7_FPOV_WE = 0x00000072, 17600 PH_SC0_PA7_LPOV_WE = 0x00000073, 17601 PH_SC0_PA7_EOP_WE = 0x00000074, 17602 PH_SC0_PA7_DATA_FIFO_EOP_RD = 0x00000075, 17603 PH_SC0_PA7_EOPG_WE = 0x00000076, 17604 PH_SC0_PA7_DEALLOC_4_0_RD = 0x00000077, 17605 PH_SC1_SRPS_WINDOW_VALID = 0x00000078, 17606 PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000079, 17607 PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000007a, 17608 PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000007b, 17609 PH_SC1_ARB_STALLED_FROM_BELOW = 0x0000007c, 17610 PH_SC1_ARB_STARVED_FROM_ABOVE = 0x0000007d, 17611 PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e, 17612 PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f, 17613 PH_SC1_ARB_BUSY = 0x00000080, 17614 PH_SC1_ARB_PA_BUSY_SOP = 0x00000081, 17615 PH_SC1_ARB_EOP_POP_SYNC_POP = 0x00000082, 17616 PH_SC1_ARB_EVENT_SYNC_POP = 0x00000083, 17617 PH_SC1_PS_ENG_MULTICYCLE_BUBBLE = 0x00000084, 17618 PH_SC1_EOP_SYNC_WINDOW = 0x00000085, 17619 PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000086, 17620 PH_SC1_BUSY_CNT_NOT_ZERO = 0x00000087, 17621 PH_SC1_SEND = 0x00000088, 17622 PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000089, 17623 PH_SC1_CREDIT_AT_MAX = 0x0000008a, 17624 PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000008b, 17625 PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008c, 17626 PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008d, 17627 PH_SC1_GFX_PIPE0_TO_1_TRANSITION = 0x0000008e, 17628 PH_SC1_GFX_PIPE1_TO_0_TRANSITION = 0x0000008f, 17629 PH_SC1_PA0_DATA_FIFO_RD = 0x00000090, 17630 PH_SC1_PA0_DATA_FIFO_WE = 0x00000091, 17631 PH_SC1_PA0_FIFO_EMPTY = 0x00000092, 17632 PH_SC1_PA0_FIFO_FULL = 0x00000093, 17633 PH_SC1_PA0_NULL_WE = 0x00000094, 17634 PH_SC1_PA0_EVENT_WE = 0x00000095, 17635 PH_SC1_PA0_FPOV_WE = 0x00000096, 17636 PH_SC1_PA0_LPOV_WE = 0x00000097, 17637 PH_SC1_PA0_EOP_WE = 0x00000098, 17638 PH_SC1_PA0_DATA_FIFO_EOP_RD = 0x00000099, 17639 PH_SC1_PA0_EOPG_WE = 0x0000009a, 17640 PH_SC1_PA0_DEALLOC_4_0_RD = 0x0000009b, 17641 PH_SC1_PA1_DATA_FIFO_RD = 0x0000009c, 17642 PH_SC1_PA1_DATA_FIFO_WE = 0x0000009d, 17643 PH_SC1_PA1_FIFO_EMPTY = 0x0000009e, 17644 PH_SC1_PA1_FIFO_FULL = 0x0000009f, 17645 PH_SC1_PA1_NULL_WE = 0x000000a0, 17646 PH_SC1_PA1_EVENT_WE = 0x000000a1, 17647 PH_SC1_PA1_FPOV_WE = 0x000000a2, 17648 PH_SC1_PA1_LPOV_WE = 0x000000a3, 17649 PH_SC1_PA1_EOP_WE = 0x000000a4, 17650 PH_SC1_PA1_DATA_FIFO_EOP_RD = 0x000000a5, 17651 PH_SC1_PA1_EOPG_WE = 0x000000a6, 17652 PH_SC1_PA1_DEALLOC_4_0_RD = 0x000000a7, 17653 PH_SC1_PA2_DATA_FIFO_RD = 0x000000a8, 17654 PH_SC1_PA2_DATA_FIFO_WE = 0x000000a9, 17655 PH_SC1_PA2_FIFO_EMPTY = 0x000000aa, 17656 PH_SC1_PA2_FIFO_FULL = 0x000000ab, 17657 PH_SC1_PA2_NULL_WE = 0x000000ac, 17658 PH_SC1_PA2_EVENT_WE = 0x000000ad, 17659 PH_SC1_PA2_FPOV_WE = 0x000000ae, 17660 PH_SC1_PA2_LPOV_WE = 0x000000af, 17661 PH_SC1_PA2_EOP_WE = 0x000000b0, 17662 PH_SC1_PA2_DATA_FIFO_EOP_RD = 0x000000b1, 17663 PH_SC1_PA2_EOPG_WE = 0x000000b2, 17664 PH_SC1_PA2_DEALLOC_4_0_RD = 0x000000b3, 17665 PH_SC1_PA3_DATA_FIFO_RD = 0x000000b4, 17666 PH_SC1_PA3_DATA_FIFO_WE = 0x000000b5, 17667 PH_SC1_PA3_FIFO_EMPTY = 0x000000b6, 17668 PH_SC1_PA3_FIFO_FULL = 0x000000b7, 17669 PH_SC1_PA3_NULL_WE = 0x000000b8, 17670 PH_SC1_PA3_EVENT_WE = 0x000000b9, 17671 PH_SC1_PA3_FPOV_WE = 0x000000ba, 17672 PH_SC1_PA3_LPOV_WE = 0x000000bb, 17673 PH_SC1_PA3_EOP_WE = 0x000000bc, 17674 PH_SC1_PA3_DATA_FIFO_EOP_RD = 0x000000bd, 17675 PH_SC1_PA3_EOPG_WE = 0x000000be, 17676 PH_SC1_PA3_DEALLOC_4_0_RD = 0x000000bf, 17677 PH_SC1_PA4_DATA_FIFO_RD = 0x000000c0, 17678 PH_SC1_PA4_DATA_FIFO_WE = 0x000000c1, 17679 PH_SC1_PA4_FIFO_EMPTY = 0x000000c2, 17680 PH_SC1_PA4_FIFO_FULL = 0x000000c3, 17681 PH_SC1_PA4_NULL_WE = 0x000000c4, 17682 PH_SC1_PA4_EVENT_WE = 0x000000c5, 17683 PH_SC1_PA4_FPOV_WE = 0x000000c6, 17684 PH_SC1_PA4_LPOV_WE = 0x000000c7, 17685 PH_SC1_PA4_EOP_WE = 0x000000c8, 17686 PH_SC1_PA4_DATA_FIFO_EOP_RD = 0x000000c9, 17687 PH_SC1_PA4_EOPG_WE = 0x000000ca, 17688 PH_SC1_PA4_DEALLOC_4_0_RD = 0x000000cb, 17689 PH_SC1_PA5_DATA_FIFO_RD = 0x000000cc, 17690 PH_SC1_PA5_DATA_FIFO_WE = 0x000000cd, 17691 PH_SC1_PA5_FIFO_EMPTY = 0x000000ce, 17692 PH_SC1_PA5_FIFO_FULL = 0x000000cf, 17693 PH_SC1_PA5_NULL_WE = 0x000000d0, 17694 PH_SC1_PA5_EVENT_WE = 0x000000d1, 17695 PH_SC1_PA5_FPOV_WE = 0x000000d2, 17696 PH_SC1_PA5_LPOV_WE = 0x000000d3, 17697 PH_SC1_PA5_EOP_WE = 0x000000d4, 17698 PH_SC1_PA5_DATA_FIFO_EOP_RD = 0x000000d5, 17699 PH_SC1_PA5_EOPG_WE = 0x000000d6, 17700 PH_SC1_PA5_DEALLOC_4_0_RD = 0x000000d7, 17701 PH_SC1_PA6_DATA_FIFO_RD = 0x000000d8, 17702 PH_SC1_PA6_DATA_FIFO_WE = 0x000000d9, 17703 PH_SC1_PA6_FIFO_EMPTY = 0x000000da, 17704 PH_SC1_PA6_FIFO_FULL = 0x000000db, 17705 PH_SC1_PA6_NULL_WE = 0x000000dc, 17706 PH_SC1_PA6_EVENT_WE = 0x000000dd, 17707 PH_SC1_PA6_FPOV_WE = 0x000000de, 17708 PH_SC1_PA6_LPOV_WE = 0x000000df, 17709 PH_SC1_PA6_EOP_WE = 0x000000e0, 17710 PH_SC1_PA6_DATA_FIFO_EOP_RD = 0x000000e1, 17711 PH_SC1_PA6_EOPG_WE = 0x000000e2, 17712 PH_SC1_PA6_DEALLOC_4_0_RD = 0x000000e3, 17713 PH_SC1_PA7_DATA_FIFO_RD = 0x000000e4, 17714 PH_SC1_PA7_DATA_FIFO_WE = 0x000000e5, 17715 PH_SC1_PA7_FIFO_EMPTY = 0x000000e6, 17716 PH_SC1_PA7_FIFO_FULL = 0x000000e7, 17717 PH_SC1_PA7_NULL_WE = 0x000000e8, 17718 PH_SC1_PA7_EVENT_WE = 0x000000e9, 17719 PH_SC1_PA7_FPOV_WE = 0x000000ea, 17720 PH_SC1_PA7_LPOV_WE = 0x000000eb, 17721 PH_SC1_PA7_EOP_WE = 0x000000ec, 17722 PH_SC1_PA7_DATA_FIFO_EOP_RD = 0x000000ed, 17723 PH_SC1_PA7_EOPG_WE = 0x000000ee, 17724 PH_SC1_PA7_DEALLOC_4_0_RD = 0x000000ef, 17725 PH_SC2_SRPS_WINDOW_VALID = 0x000000f0, 17726 PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000000f1, 17727 PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 0x000000f2, 17728 PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000000f3, 17729 PH_SC2_ARB_STALLED_FROM_BELOW = 0x000000f4, 17730 PH_SC2_ARB_STARVED_FROM_ABOVE = 0x000000f5, 17731 PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6, 17732 PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7, 17733 PH_SC2_ARB_BUSY = 0x000000f8, 17734 PH_SC2_ARB_PA_BUSY_SOP = 0x000000f9, 17735 PH_SC2_ARB_EOP_POP_SYNC_POP = 0x000000fa, 17736 PH_SC2_ARB_EVENT_SYNC_POP = 0x000000fb, 17737 PH_SC2_PS_ENG_MULTICYCLE_BUBBLE = 0x000000fc, 17738 PH_SC2_EOP_SYNC_WINDOW = 0x000000fd, 17739 PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000000fe, 17740 PH_SC2_BUSY_CNT_NOT_ZERO = 0x000000ff, 17741 PH_SC2_SEND = 0x00000100, 17742 PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000101, 17743 PH_SC2_CREDIT_AT_MAX = 0x00000102, 17744 PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000103, 17745 PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000104, 17746 PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000105, 17747 PH_SC2_GFX_PIPE0_TO_1_TRANSITION = 0x00000106, 17748 PH_SC2_GFX_PIPE1_TO_0_TRANSITION = 0x00000107, 17749 PH_SC2_PA0_DATA_FIFO_RD = 0x00000108, 17750 PH_SC2_PA0_DATA_FIFO_WE = 0x00000109, 17751 PH_SC2_PA0_FIFO_EMPTY = 0x0000010a, 17752 PH_SC2_PA0_FIFO_FULL = 0x0000010b, 17753 PH_SC2_PA0_NULL_WE = 0x0000010c, 17754 PH_SC2_PA0_EVENT_WE = 0x0000010d, 17755 PH_SC2_PA0_FPOV_WE = 0x0000010e, 17756 PH_SC2_PA0_LPOV_WE = 0x0000010f, 17757 PH_SC2_PA0_EOP_WE = 0x00000110, 17758 PH_SC2_PA0_DATA_FIFO_EOP_RD = 0x00000111, 17759 PH_SC2_PA0_EOPG_WE = 0x00000112, 17760 PH_SC2_PA0_DEALLOC_4_0_RD = 0x00000113, 17761 PH_SC2_PA1_DATA_FIFO_RD = 0x00000114, 17762 PH_SC2_PA1_DATA_FIFO_WE = 0x00000115, 17763 PH_SC2_PA1_FIFO_EMPTY = 0x00000116, 17764 PH_SC2_PA1_FIFO_FULL = 0x00000117, 17765 PH_SC2_PA1_NULL_WE = 0x00000118, 17766 PH_SC2_PA1_EVENT_WE = 0x00000119, 17767 PH_SC2_PA1_FPOV_WE = 0x0000011a, 17768 PH_SC2_PA1_LPOV_WE = 0x0000011b, 17769 PH_SC2_PA1_EOP_WE = 0x0000011c, 17770 PH_SC2_PA1_DATA_FIFO_EOP_RD = 0x0000011d, 17771 PH_SC2_PA1_EOPG_WE = 0x0000011e, 17772 PH_SC2_PA1_DEALLOC_4_0_RD = 0x0000011f, 17773 PH_SC2_PA2_DATA_FIFO_RD = 0x00000120, 17774 PH_SC2_PA2_DATA_FIFO_WE = 0x00000121, 17775 PH_SC2_PA2_FIFO_EMPTY = 0x00000122, 17776 PH_SC2_PA2_FIFO_FULL = 0x00000123, 17777 PH_SC2_PA2_NULL_WE = 0x00000124, 17778 PH_SC2_PA2_EVENT_WE = 0x00000125, 17779 PH_SC2_PA2_FPOV_WE = 0x00000126, 17780 PH_SC2_PA2_LPOV_WE = 0x00000127, 17781 PH_SC2_PA2_EOP_WE = 0x00000128, 17782 PH_SC2_PA2_DATA_FIFO_EOP_RD = 0x00000129, 17783 PH_SC2_PA2_EOPG_WE = 0x0000012a, 17784 PH_SC2_PA2_DEALLOC_4_0_RD = 0x0000012b, 17785 PH_SC2_PA3_DATA_FIFO_RD = 0x0000012c, 17786 PH_SC2_PA3_DATA_FIFO_WE = 0x0000012d, 17787 PH_SC2_PA3_FIFO_EMPTY = 0x0000012e, 17788 PH_SC2_PA3_FIFO_FULL = 0x0000012f, 17789 PH_SC2_PA3_NULL_WE = 0x00000130, 17790 PH_SC2_PA3_EVENT_WE = 0x00000131, 17791 PH_SC2_PA3_FPOV_WE = 0x00000132, 17792 PH_SC2_PA3_LPOV_WE = 0x00000133, 17793 PH_SC2_PA3_EOP_WE = 0x00000134, 17794 PH_SC2_PA3_DATA_FIFO_EOP_RD = 0x00000135, 17795 PH_SC2_PA3_EOPG_WE = 0x00000136, 17796 PH_SC2_PA3_DEALLOC_4_0_RD = 0x00000137, 17797 PH_SC2_PA4_DATA_FIFO_RD = 0x00000138, 17798 PH_SC2_PA4_DATA_FIFO_WE = 0x00000139, 17799 PH_SC2_PA4_FIFO_EMPTY = 0x0000013a, 17800 PH_SC2_PA4_FIFO_FULL = 0x0000013b, 17801 PH_SC2_PA4_NULL_WE = 0x0000013c, 17802 PH_SC2_PA4_EVENT_WE = 0x0000013d, 17803 PH_SC2_PA4_FPOV_WE = 0x0000013e, 17804 PH_SC2_PA4_LPOV_WE = 0x0000013f, 17805 PH_SC2_PA4_EOP_WE = 0x00000140, 17806 PH_SC2_PA4_DATA_FIFO_EOP_RD = 0x00000141, 17807 PH_SC2_PA4_EOPG_WE = 0x00000142, 17808 PH_SC2_PA4_DEALLOC_4_0_RD = 0x00000143, 17809 PH_SC2_PA5_DATA_FIFO_RD = 0x00000144, 17810 PH_SC2_PA5_DATA_FIFO_WE = 0x00000145, 17811 PH_SC2_PA5_FIFO_EMPTY = 0x00000146, 17812 PH_SC2_PA5_FIFO_FULL = 0x00000147, 17813 PH_SC2_PA5_NULL_WE = 0x00000148, 17814 PH_SC2_PA5_EVENT_WE = 0x00000149, 17815 PH_SC2_PA5_FPOV_WE = 0x0000014a, 17816 PH_SC2_PA5_LPOV_WE = 0x0000014b, 17817 PH_SC2_PA5_EOP_WE = 0x0000014c, 17818 PH_SC2_PA5_DATA_FIFO_EOP_RD = 0x0000014d, 17819 PH_SC2_PA5_EOPG_WE = 0x0000014e, 17820 PH_SC2_PA5_DEALLOC_4_0_RD = 0x0000014f, 17821 PH_SC2_PA6_DATA_FIFO_RD = 0x00000150, 17822 PH_SC2_PA6_DATA_FIFO_WE = 0x00000151, 17823 PH_SC2_PA6_FIFO_EMPTY = 0x00000152, 17824 PH_SC2_PA6_FIFO_FULL = 0x00000153, 17825 PH_SC2_PA6_NULL_WE = 0x00000154, 17826 PH_SC2_PA6_EVENT_WE = 0x00000155, 17827 PH_SC2_PA6_FPOV_WE = 0x00000156, 17828 PH_SC2_PA6_LPOV_WE = 0x00000157, 17829 PH_SC2_PA6_EOP_WE = 0x00000158, 17830 PH_SC2_PA6_DATA_FIFO_EOP_RD = 0x00000159, 17831 PH_SC2_PA6_EOPG_WE = 0x0000015a, 17832 PH_SC2_PA6_DEALLOC_4_0_RD = 0x0000015b, 17833 PH_SC2_PA7_DATA_FIFO_RD = 0x0000015c, 17834 PH_SC2_PA7_DATA_FIFO_WE = 0x0000015d, 17835 PH_SC2_PA7_FIFO_EMPTY = 0x0000015e, 17836 PH_SC2_PA7_FIFO_FULL = 0x0000015f, 17837 PH_SC2_PA7_NULL_WE = 0x00000160, 17838 PH_SC2_PA7_EVENT_WE = 0x00000161, 17839 PH_SC2_PA7_FPOV_WE = 0x00000162, 17840 PH_SC2_PA7_LPOV_WE = 0x00000163, 17841 PH_SC2_PA7_EOP_WE = 0x00000164, 17842 PH_SC2_PA7_DATA_FIFO_EOP_RD = 0x00000165, 17843 PH_SC2_PA7_EOPG_WE = 0x00000166, 17844 PH_SC2_PA7_DEALLOC_4_0_RD = 0x00000167, 17845 PH_SC3_SRPS_WINDOW_VALID = 0x00000168, 17846 PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000169, 17847 PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000016a, 17848 PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000016b, 17849 PH_SC3_ARB_STALLED_FROM_BELOW = 0x0000016c, 17850 PH_SC3_ARB_STARVED_FROM_ABOVE = 0x0000016d, 17851 PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e, 17852 PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f, 17853 PH_SC3_ARB_BUSY = 0x00000170, 17854 PH_SC3_ARB_PA_BUSY_SOP = 0x00000171, 17855 PH_SC3_ARB_EOP_POP_SYNC_POP = 0x00000172, 17856 PH_SC3_ARB_EVENT_SYNC_POP = 0x00000173, 17857 PH_SC3_PS_ENG_MULTICYCLE_BUBBLE = 0x00000174, 17858 PH_SC3_EOP_SYNC_WINDOW = 0x00000175, 17859 PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000176, 17860 PH_SC3_BUSY_CNT_NOT_ZERO = 0x00000177, 17861 PH_SC3_SEND = 0x00000178, 17862 PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000179, 17863 PH_SC3_CREDIT_AT_MAX = 0x0000017a, 17864 PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000017b, 17865 PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017c, 17866 PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017d, 17867 PH_SC3_GFX_PIPE0_TO_1_TRANSITION = 0x0000017e, 17868 PH_SC3_GFX_PIPE1_TO_0_TRANSITION = 0x0000017f, 17869 PH_SC3_PA0_DATA_FIFO_RD = 0x00000180, 17870 PH_SC3_PA0_DATA_FIFO_WE = 0x00000181, 17871 PH_SC3_PA0_FIFO_EMPTY = 0x00000182, 17872 PH_SC3_PA0_FIFO_FULL = 0x00000183, 17873 PH_SC3_PA0_NULL_WE = 0x00000184, 17874 PH_SC3_PA0_EVENT_WE = 0x00000185, 17875 PH_SC3_PA0_FPOV_WE = 0x00000186, 17876 PH_SC3_PA0_LPOV_WE = 0x00000187, 17877 PH_SC3_PA0_EOP_WE = 0x00000188, 17878 PH_SC3_PA0_DATA_FIFO_EOP_RD = 0x00000189, 17879 PH_SC3_PA0_EOPG_WE = 0x0000018a, 17880 PH_SC3_PA0_DEALLOC_4_0_RD = 0x0000018b, 17881 PH_SC3_PA1_DATA_FIFO_RD = 0x0000018c, 17882 PH_SC3_PA1_DATA_FIFO_WE = 0x0000018d, 17883 PH_SC3_PA1_FIFO_EMPTY = 0x0000018e, 17884 PH_SC3_PA1_FIFO_FULL = 0x0000018f, 17885 PH_SC3_PA1_NULL_WE = 0x00000190, 17886 PH_SC3_PA1_EVENT_WE = 0x00000191, 17887 PH_SC3_PA1_FPOV_WE = 0x00000192, 17888 PH_SC3_PA1_LPOV_WE = 0x00000193, 17889 PH_SC3_PA1_EOP_WE = 0x00000194, 17890 PH_SC3_PA1_DATA_FIFO_EOP_RD = 0x00000195, 17891 PH_SC3_PA1_EOPG_WE = 0x00000196, 17892 PH_SC3_PA1_DEALLOC_4_0_RD = 0x00000197, 17893 PH_SC3_PA2_DATA_FIFO_RD = 0x00000198, 17894 PH_SC3_PA2_DATA_FIFO_WE = 0x00000199, 17895 PH_SC3_PA2_FIFO_EMPTY = 0x0000019a, 17896 PH_SC3_PA2_FIFO_FULL = 0x0000019b, 17897 PH_SC3_PA2_NULL_WE = 0x0000019c, 17898 PH_SC3_PA2_EVENT_WE = 0x0000019d, 17899 PH_SC3_PA2_FPOV_WE = 0x0000019e, 17900 PH_SC3_PA2_LPOV_WE = 0x0000019f, 17901 PH_SC3_PA2_EOP_WE = 0x000001a0, 17902 PH_SC3_PA2_DATA_FIFO_EOP_RD = 0x000001a1, 17903 PH_SC3_PA2_EOPG_WE = 0x000001a2, 17904 PH_SC3_PA2_DEALLOC_4_0_RD = 0x000001a3, 17905 PH_SC3_PA3_DATA_FIFO_RD = 0x000001a4, 17906 PH_SC3_PA3_DATA_FIFO_WE = 0x000001a5, 17907 PH_SC3_PA3_FIFO_EMPTY = 0x000001a6, 17908 PH_SC3_PA3_FIFO_FULL = 0x000001a7, 17909 PH_SC3_PA3_NULL_WE = 0x000001a8, 17910 PH_SC3_PA3_EVENT_WE = 0x000001a9, 17911 PH_SC3_PA3_FPOV_WE = 0x000001aa, 17912 PH_SC3_PA3_LPOV_WE = 0x000001ab, 17913 PH_SC3_PA3_EOP_WE = 0x000001ac, 17914 PH_SC3_PA3_DATA_FIFO_EOP_RD = 0x000001ad, 17915 PH_SC3_PA3_EOPG_WE = 0x000001ae, 17916 PH_SC3_PA3_DEALLOC_4_0_RD = 0x000001af, 17917 PH_SC3_PA4_DATA_FIFO_RD = 0x000001b0, 17918 PH_SC3_PA4_DATA_FIFO_WE = 0x000001b1, 17919 PH_SC3_PA4_FIFO_EMPTY = 0x000001b2, 17920 PH_SC3_PA4_FIFO_FULL = 0x000001b3, 17921 PH_SC3_PA4_NULL_WE = 0x000001b4, 17922 PH_SC3_PA4_EVENT_WE = 0x000001b5, 17923 PH_SC3_PA4_FPOV_WE = 0x000001b6, 17924 PH_SC3_PA4_LPOV_WE = 0x000001b7, 17925 PH_SC3_PA4_EOP_WE = 0x000001b8, 17926 PH_SC3_PA4_DATA_FIFO_EOP_RD = 0x000001b9, 17927 PH_SC3_PA4_EOPG_WE = 0x000001ba, 17928 PH_SC3_PA4_DEALLOC_4_0_RD = 0x000001bb, 17929 PH_SC3_PA5_DATA_FIFO_RD = 0x000001bc, 17930 PH_SC3_PA5_DATA_FIFO_WE = 0x000001bd, 17931 PH_SC3_PA5_FIFO_EMPTY = 0x000001be, 17932 PH_SC3_PA5_FIFO_FULL = 0x000001bf, 17933 PH_SC3_PA5_NULL_WE = 0x000001c0, 17934 PH_SC3_PA5_EVENT_WE = 0x000001c1, 17935 PH_SC3_PA5_FPOV_WE = 0x000001c2, 17936 PH_SC3_PA5_LPOV_WE = 0x000001c3, 17937 PH_SC3_PA5_EOP_WE = 0x000001c4, 17938 PH_SC3_PA5_DATA_FIFO_EOP_RD = 0x000001c5, 17939 PH_SC3_PA5_EOPG_WE = 0x000001c6, 17940 PH_SC3_PA5_DEALLOC_4_0_RD = 0x000001c7, 17941 PH_SC3_PA6_DATA_FIFO_RD = 0x000001c8, 17942 PH_SC3_PA6_DATA_FIFO_WE = 0x000001c9, 17943 PH_SC3_PA6_FIFO_EMPTY = 0x000001ca, 17944 PH_SC3_PA6_FIFO_FULL = 0x000001cb, 17945 PH_SC3_PA6_NULL_WE = 0x000001cc, 17946 PH_SC3_PA6_EVENT_WE = 0x000001cd, 17947 PH_SC3_PA6_FPOV_WE = 0x000001ce, 17948 PH_SC3_PA6_LPOV_WE = 0x000001cf, 17949 PH_SC3_PA6_EOP_WE = 0x000001d0, 17950 PH_SC3_PA6_DATA_FIFO_EOP_RD = 0x000001d1, 17951 PH_SC3_PA6_EOPG_WE = 0x000001d2, 17952 PH_SC3_PA6_DEALLOC_4_0_RD = 0x000001d3, 17953 PH_SC3_PA7_DATA_FIFO_RD = 0x000001d4, 17954 PH_SC3_PA7_DATA_FIFO_WE = 0x000001d5, 17955 PH_SC3_PA7_FIFO_EMPTY = 0x000001d6, 17956 PH_SC3_PA7_FIFO_FULL = 0x000001d7, 17957 PH_SC3_PA7_NULL_WE = 0x000001d8, 17958 PH_SC3_PA7_EVENT_WE = 0x000001d9, 17959 PH_SC3_PA7_FPOV_WE = 0x000001da, 17960 PH_SC3_PA7_LPOV_WE = 0x000001db, 17961 PH_SC3_PA7_EOP_WE = 0x000001dc, 17962 PH_SC3_PA7_DATA_FIFO_EOP_RD = 0x000001dd, 17963 PH_SC3_PA7_EOPG_WE = 0x000001de, 17964 PH_SC3_PA7_DEALLOC_4_0_RD = 0x000001df, 17965 PH_SC4_SRPS_WINDOW_VALID = 0x000001e0, 17966 PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000001e1, 17967 PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 0x000001e2, 17968 PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000001e3, 17969 PH_SC4_ARB_STALLED_FROM_BELOW = 0x000001e4, 17970 PH_SC4_ARB_STARVED_FROM_ABOVE = 0x000001e5, 17971 PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6, 17972 PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7, 17973 PH_SC4_ARB_BUSY = 0x000001e8, 17974 PH_SC4_ARB_PA_BUSY_SOP = 0x000001e9, 17975 PH_SC4_ARB_EOP_POP_SYNC_POP = 0x000001ea, 17976 PH_SC4_ARB_EVENT_SYNC_POP = 0x000001eb, 17977 PH_SC4_PS_ENG_MULTICYCLE_BUBBLE = 0x000001ec, 17978 PH_SC4_EOP_SYNC_WINDOW = 0x000001ed, 17979 PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000001ee, 17980 PH_SC4_BUSY_CNT_NOT_ZERO = 0x000001ef, 17981 PH_SC4_SEND = 0x000001f0, 17982 PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001f1, 17983 PH_SC4_CREDIT_AT_MAX = 0x000001f2, 17984 PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001f3, 17985 PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f4, 17986 PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f5, 17987 PH_SC4_GFX_PIPE0_TO_1_TRANSITION = 0x000001f6, 17988 PH_SC4_GFX_PIPE1_TO_0_TRANSITION = 0x000001f7, 17989 PH_SC4_PA0_DATA_FIFO_RD = 0x000001f8, 17990 PH_SC4_PA0_DATA_FIFO_WE = 0x000001f9, 17991 PH_SC4_PA0_FIFO_EMPTY = 0x000001fa, 17992 PH_SC4_PA0_FIFO_FULL = 0x000001fb, 17993 PH_SC4_PA0_NULL_WE = 0x000001fc, 17994 PH_SC4_PA0_EVENT_WE = 0x000001fd, 17995 PH_SC4_PA0_FPOV_WE = 0x000001fe, 17996 PH_SC4_PA0_LPOV_WE = 0x000001ff, 17997 PH_SC4_PA0_EOP_WE = 0x00000200, 17998 PH_SC4_PA0_DATA_FIFO_EOP_RD = 0x00000201, 17999 PH_SC4_PA0_EOPG_WE = 0x00000202, 18000 PH_SC4_PA0_DEALLOC_4_0_RD = 0x00000203, 18001 PH_SC4_PA1_DATA_FIFO_RD = 0x00000204, 18002 PH_SC4_PA1_DATA_FIFO_WE = 0x00000205, 18003 PH_SC4_PA1_FIFO_EMPTY = 0x00000206, 18004 PH_SC4_PA1_FIFO_FULL = 0x00000207, 18005 PH_SC4_PA1_NULL_WE = 0x00000208, 18006 PH_SC4_PA1_EVENT_WE = 0x00000209, 18007 PH_SC4_PA1_FPOV_WE = 0x0000020a, 18008 PH_SC4_PA1_LPOV_WE = 0x0000020b, 18009 PH_SC4_PA1_EOP_WE = 0x0000020c, 18010 PH_SC4_PA1_DATA_FIFO_EOP_RD = 0x0000020d, 18011 PH_SC4_PA1_EOPG_WE = 0x0000020e, 18012 PH_SC4_PA1_DEALLOC_4_0_RD = 0x0000020f, 18013 PH_SC4_PA2_DATA_FIFO_RD = 0x00000210, 18014 PH_SC4_PA2_DATA_FIFO_WE = 0x00000211, 18015 PH_SC4_PA2_FIFO_EMPTY = 0x00000212, 18016 PH_SC4_PA2_FIFO_FULL = 0x00000213, 18017 PH_SC4_PA2_NULL_WE = 0x00000214, 18018 PH_SC4_PA2_EVENT_WE = 0x00000215, 18019 PH_SC4_PA2_FPOV_WE = 0x00000216, 18020 PH_SC4_PA2_LPOV_WE = 0x00000217, 18021 PH_SC4_PA2_EOP_WE = 0x00000218, 18022 PH_SC4_PA2_DATA_FIFO_EOP_RD = 0x00000219, 18023 PH_SC4_PA2_EOPG_WE = 0x0000021a, 18024 PH_SC4_PA2_DEALLOC_4_0_RD = 0x0000021b, 18025 PH_SC4_PA3_DATA_FIFO_RD = 0x0000021c, 18026 PH_SC4_PA3_DATA_FIFO_WE = 0x0000021d, 18027 PH_SC4_PA3_FIFO_EMPTY = 0x0000021e, 18028 PH_SC4_PA3_FIFO_FULL = 0x0000021f, 18029 PH_SC4_PA3_NULL_WE = 0x00000220, 18030 PH_SC4_PA3_EVENT_WE = 0x00000221, 18031 PH_SC4_PA3_FPOV_WE = 0x00000222, 18032 PH_SC4_PA3_LPOV_WE = 0x00000223, 18033 PH_SC4_PA3_EOP_WE = 0x00000224, 18034 PH_SC4_PA3_DATA_FIFO_EOP_RD = 0x00000225, 18035 PH_SC4_PA3_EOPG_WE = 0x00000226, 18036 PH_SC4_PA3_DEALLOC_4_0_RD = 0x00000227, 18037 PH_SC4_PA4_DATA_FIFO_RD = 0x00000228, 18038 PH_SC4_PA4_DATA_FIFO_WE = 0x00000229, 18039 PH_SC4_PA4_FIFO_EMPTY = 0x0000022a, 18040 PH_SC4_PA4_FIFO_FULL = 0x0000022b, 18041 PH_SC4_PA4_NULL_WE = 0x0000022c, 18042 PH_SC4_PA4_EVENT_WE = 0x0000022d, 18043 PH_SC4_PA4_FPOV_WE = 0x0000022e, 18044 PH_SC4_PA4_LPOV_WE = 0x0000022f, 18045 PH_SC4_PA4_EOP_WE = 0x00000230, 18046 PH_SC4_PA4_DATA_FIFO_EOP_RD = 0x00000231, 18047 PH_SC4_PA4_EOPG_WE = 0x00000232, 18048 PH_SC4_PA4_DEALLOC_4_0_RD = 0x00000233, 18049 PH_SC4_PA5_DATA_FIFO_RD = 0x00000234, 18050 PH_SC4_PA5_DATA_FIFO_WE = 0x00000235, 18051 PH_SC4_PA5_FIFO_EMPTY = 0x00000236, 18052 PH_SC4_PA5_FIFO_FULL = 0x00000237, 18053 PH_SC4_PA5_NULL_WE = 0x00000238, 18054 PH_SC4_PA5_EVENT_WE = 0x00000239, 18055 PH_SC4_PA5_FPOV_WE = 0x0000023a, 18056 PH_SC4_PA5_LPOV_WE = 0x0000023b, 18057 PH_SC4_PA5_EOP_WE = 0x0000023c, 18058 PH_SC4_PA5_DATA_FIFO_EOP_RD = 0x0000023d, 18059 PH_SC4_PA5_EOPG_WE = 0x0000023e, 18060 PH_SC4_PA5_DEALLOC_4_0_RD = 0x0000023f, 18061 PH_SC4_PA6_DATA_FIFO_RD = 0x00000240, 18062 PH_SC4_PA6_DATA_FIFO_WE = 0x00000241, 18063 PH_SC4_PA6_FIFO_EMPTY = 0x00000242, 18064 PH_SC4_PA6_FIFO_FULL = 0x00000243, 18065 PH_SC4_PA6_NULL_WE = 0x00000244, 18066 PH_SC4_PA6_EVENT_WE = 0x00000245, 18067 PH_SC4_PA6_FPOV_WE = 0x00000246, 18068 PH_SC4_PA6_LPOV_WE = 0x00000247, 18069 PH_SC4_PA6_EOP_WE = 0x00000248, 18070 PH_SC4_PA6_DATA_FIFO_EOP_RD = 0x00000249, 18071 PH_SC4_PA6_EOPG_WE = 0x0000024a, 18072 PH_SC4_PA6_DEALLOC_4_0_RD = 0x0000024b, 18073 PH_SC4_PA7_DATA_FIFO_RD = 0x0000024c, 18074 PH_SC4_PA7_DATA_FIFO_WE = 0x0000024d, 18075 PH_SC4_PA7_FIFO_EMPTY = 0x0000024e, 18076 PH_SC4_PA7_FIFO_FULL = 0x0000024f, 18077 PH_SC4_PA7_NULL_WE = 0x00000250, 18078 PH_SC4_PA7_EVENT_WE = 0x00000251, 18079 PH_SC4_PA7_FPOV_WE = 0x00000252, 18080 PH_SC4_PA7_LPOV_WE = 0x00000253, 18081 PH_SC4_PA7_EOP_WE = 0x00000254, 18082 PH_SC4_PA7_DATA_FIFO_EOP_RD = 0x00000255, 18083 PH_SC4_PA7_EOPG_WE = 0x00000256, 18084 PH_SC4_PA7_DEALLOC_4_0_RD = 0x00000257, 18085 PH_SC5_SRPS_WINDOW_VALID = 0x00000258, 18086 PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000259, 18087 PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000025a, 18088 PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000025b, 18089 PH_SC5_ARB_STALLED_FROM_BELOW = 0x0000025c, 18090 PH_SC5_ARB_STARVED_FROM_ABOVE = 0x0000025d, 18091 PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e, 18092 PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f, 18093 PH_SC5_ARB_BUSY = 0x00000260, 18094 PH_SC5_ARB_PA_BUSY_SOP = 0x00000261, 18095 PH_SC5_ARB_EOP_POP_SYNC_POP = 0x00000262, 18096 PH_SC5_ARB_EVENT_SYNC_POP = 0x00000263, 18097 PH_SC5_PS_ENG_MULTICYCLE_BUBBLE = 0x00000264, 18098 PH_SC5_EOP_SYNC_WINDOW = 0x00000265, 18099 PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000266, 18100 PH_SC5_BUSY_CNT_NOT_ZERO = 0x00000267, 18101 PH_SC5_SEND = 0x00000268, 18102 PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000269, 18103 PH_SC5_CREDIT_AT_MAX = 0x0000026a, 18104 PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000026b, 18105 PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026c, 18106 PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026d, 18107 PH_SC5_GFX_PIPE0_TO_1_TRANSITION = 0x0000026e, 18108 PH_SC5_GFX_PIPE1_TO_0_TRANSITION = 0x0000026f, 18109 PH_SC5_PA0_DATA_FIFO_RD = 0x00000270, 18110 PH_SC5_PA0_DATA_FIFO_WE = 0x00000271, 18111 PH_SC5_PA0_FIFO_EMPTY = 0x00000272, 18112 PH_SC5_PA0_FIFO_FULL = 0x00000273, 18113 PH_SC5_PA0_NULL_WE = 0x00000274, 18114 PH_SC5_PA0_EVENT_WE = 0x00000275, 18115 PH_SC5_PA0_FPOV_WE = 0x00000276, 18116 PH_SC5_PA0_LPOV_WE = 0x00000277, 18117 PH_SC5_PA0_EOP_WE = 0x00000278, 18118 PH_SC5_PA0_DATA_FIFO_EOP_RD = 0x00000279, 18119 PH_SC5_PA0_EOPG_WE = 0x0000027a, 18120 PH_SC5_PA0_DEALLOC_4_0_RD = 0x0000027b, 18121 PH_SC5_PA1_DATA_FIFO_RD = 0x0000027c, 18122 PH_SC5_PA1_DATA_FIFO_WE = 0x0000027d, 18123 PH_SC5_PA1_FIFO_EMPTY = 0x0000027e, 18124 PH_SC5_PA1_FIFO_FULL = 0x0000027f, 18125 PH_SC5_PA1_NULL_WE = 0x00000280, 18126 PH_SC5_PA1_EVENT_WE = 0x00000281, 18127 PH_SC5_PA1_FPOV_WE = 0x00000282, 18128 PH_SC5_PA1_LPOV_WE = 0x00000283, 18129 PH_SC5_PA1_EOP_WE = 0x00000284, 18130 PH_SC5_PA1_DATA_FIFO_EOP_RD = 0x00000285, 18131 PH_SC5_PA1_EOPG_WE = 0x00000286, 18132 PH_SC5_PA1_DEALLOC_4_0_RD = 0x00000287, 18133 PH_SC5_PA2_DATA_FIFO_RD = 0x00000288, 18134 PH_SC5_PA2_DATA_FIFO_WE = 0x00000289, 18135 PH_SC5_PA2_FIFO_EMPTY = 0x0000028a, 18136 PH_SC5_PA2_FIFO_FULL = 0x0000028b, 18137 PH_SC5_PA2_NULL_WE = 0x0000028c, 18138 PH_SC5_PA2_EVENT_WE = 0x0000028d, 18139 PH_SC5_PA2_FPOV_WE = 0x0000028e, 18140 PH_SC5_PA2_LPOV_WE = 0x0000028f, 18141 PH_SC5_PA2_EOP_WE = 0x00000290, 18142 PH_SC5_PA2_DATA_FIFO_EOP_RD = 0x00000291, 18143 PH_SC5_PA2_EOPG_WE = 0x00000292, 18144 PH_SC5_PA2_DEALLOC_4_0_RD = 0x00000293, 18145 PH_SC5_PA3_DATA_FIFO_RD = 0x00000294, 18146 PH_SC5_PA3_DATA_FIFO_WE = 0x00000295, 18147 PH_SC5_PA3_FIFO_EMPTY = 0x00000296, 18148 PH_SC5_PA3_FIFO_FULL = 0x00000297, 18149 PH_SC5_PA3_NULL_WE = 0x00000298, 18150 PH_SC5_PA3_EVENT_WE = 0x00000299, 18151 PH_SC5_PA3_FPOV_WE = 0x0000029a, 18152 PH_SC5_PA3_LPOV_WE = 0x0000029b, 18153 PH_SC5_PA3_EOP_WE = 0x0000029c, 18154 PH_SC5_PA3_DATA_FIFO_EOP_RD = 0x0000029d, 18155 PH_SC5_PA3_EOPG_WE = 0x0000029e, 18156 PH_SC5_PA3_DEALLOC_4_0_RD = 0x0000029f, 18157 PH_SC5_PA4_DATA_FIFO_RD = 0x000002a0, 18158 PH_SC5_PA4_DATA_FIFO_WE = 0x000002a1, 18159 PH_SC5_PA4_FIFO_EMPTY = 0x000002a2, 18160 PH_SC5_PA4_FIFO_FULL = 0x000002a3, 18161 PH_SC5_PA4_NULL_WE = 0x000002a4, 18162 PH_SC5_PA4_EVENT_WE = 0x000002a5, 18163 PH_SC5_PA4_FPOV_WE = 0x000002a6, 18164 PH_SC5_PA4_LPOV_WE = 0x000002a7, 18165 PH_SC5_PA4_EOP_WE = 0x000002a8, 18166 PH_SC5_PA4_DATA_FIFO_EOP_RD = 0x000002a9, 18167 PH_SC5_PA4_EOPG_WE = 0x000002aa, 18168 PH_SC5_PA4_DEALLOC_4_0_RD = 0x000002ab, 18169 PH_SC5_PA5_DATA_FIFO_RD = 0x000002ac, 18170 PH_SC5_PA5_DATA_FIFO_WE = 0x000002ad, 18171 PH_SC5_PA5_FIFO_EMPTY = 0x000002ae, 18172 PH_SC5_PA5_FIFO_FULL = 0x000002af, 18173 PH_SC5_PA5_NULL_WE = 0x000002b0, 18174 PH_SC5_PA5_EVENT_WE = 0x000002b1, 18175 PH_SC5_PA5_FPOV_WE = 0x000002b2, 18176 PH_SC5_PA5_LPOV_WE = 0x000002b3, 18177 PH_SC5_PA5_EOP_WE = 0x000002b4, 18178 PH_SC5_PA5_DATA_FIFO_EOP_RD = 0x000002b5, 18179 PH_SC5_PA5_EOPG_WE = 0x000002b6, 18180 PH_SC5_PA5_DEALLOC_4_0_RD = 0x000002b7, 18181 PH_SC5_PA6_DATA_FIFO_RD = 0x000002b8, 18182 PH_SC5_PA6_DATA_FIFO_WE = 0x000002b9, 18183 PH_SC5_PA6_FIFO_EMPTY = 0x000002ba, 18184 PH_SC5_PA6_FIFO_FULL = 0x000002bb, 18185 PH_SC5_PA6_NULL_WE = 0x000002bc, 18186 PH_SC5_PA6_EVENT_WE = 0x000002bd, 18187 PH_SC5_PA6_FPOV_WE = 0x000002be, 18188 PH_SC5_PA6_LPOV_WE = 0x000002bf, 18189 PH_SC5_PA6_EOP_WE = 0x000002c0, 18190 PH_SC5_PA6_DATA_FIFO_EOP_RD = 0x000002c1, 18191 PH_SC5_PA6_EOPG_WE = 0x000002c2, 18192 PH_SC5_PA6_DEALLOC_4_0_RD = 0x000002c3, 18193 PH_SC5_PA7_DATA_FIFO_RD = 0x000002c4, 18194 PH_SC5_PA7_DATA_FIFO_WE = 0x000002c5, 18195 PH_SC5_PA7_FIFO_EMPTY = 0x000002c6, 18196 PH_SC5_PA7_FIFO_FULL = 0x000002c7, 18197 PH_SC5_PA7_NULL_WE = 0x000002c8, 18198 PH_SC5_PA7_EVENT_WE = 0x000002c9, 18199 PH_SC5_PA7_FPOV_WE = 0x000002ca, 18200 PH_SC5_PA7_LPOV_WE = 0x000002cb, 18201 PH_SC5_PA7_EOP_WE = 0x000002cc, 18202 PH_SC5_PA7_DATA_FIFO_EOP_RD = 0x000002cd, 18203 PH_SC5_PA7_EOPG_WE = 0x000002ce, 18204 PH_SC5_PA7_DEALLOC_4_0_RD = 0x000002cf, 18205 PH_SC6_SRPS_WINDOW_VALID = 0x000002d0, 18206 PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000002d1, 18207 PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 0x000002d2, 18208 PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000002d3, 18209 PH_SC6_ARB_STALLED_FROM_BELOW = 0x000002d4, 18210 PH_SC6_ARB_STARVED_FROM_ABOVE = 0x000002d5, 18211 PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6, 18212 PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7, 18213 PH_SC6_ARB_BUSY = 0x000002d8, 18214 PH_SC6_ARB_PA_BUSY_SOP = 0x000002d9, 18215 PH_SC6_ARB_EOP_POP_SYNC_POP = 0x000002da, 18216 PH_SC6_ARB_EVENT_SYNC_POP = 0x000002db, 18217 PH_SC6_PS_ENG_MULTICYCLE_BUBBLE = 0x000002dc, 18218 PH_SC6_EOP_SYNC_WINDOW = 0x000002dd, 18219 PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000002de, 18220 PH_SC6_BUSY_CNT_NOT_ZERO = 0x000002df, 18221 PH_SC6_SEND = 0x000002e0, 18222 PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000002e1, 18223 PH_SC6_CREDIT_AT_MAX = 0x000002e2, 18224 PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000002e3, 18225 PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e4, 18226 PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e5, 18227 PH_SC6_GFX_PIPE0_TO_1_TRANSITION = 0x000002e6, 18228 PH_SC6_GFX_PIPE1_TO_0_TRANSITION = 0x000002e7, 18229 PH_SC6_PA0_DATA_FIFO_RD = 0x000002e8, 18230 PH_SC6_PA0_DATA_FIFO_WE = 0x000002e9, 18231 PH_SC6_PA0_FIFO_EMPTY = 0x000002ea, 18232 PH_SC6_PA0_FIFO_FULL = 0x000002eb, 18233 PH_SC6_PA0_NULL_WE = 0x000002ec, 18234 PH_SC6_PA0_EVENT_WE = 0x000002ed, 18235 PH_SC6_PA0_FPOV_WE = 0x000002ee, 18236 PH_SC6_PA0_LPOV_WE = 0x000002ef, 18237 PH_SC6_PA0_EOP_WE = 0x000002f0, 18238 PH_SC6_PA0_DATA_FIFO_EOP_RD = 0x000002f1, 18239 PH_SC6_PA0_EOPG_WE = 0x000002f2, 18240 PH_SC6_PA0_DEALLOC_4_0_RD = 0x000002f3, 18241 PH_SC6_PA1_DATA_FIFO_RD = 0x000002f4, 18242 PH_SC6_PA1_DATA_FIFO_WE = 0x000002f5, 18243 PH_SC6_PA1_FIFO_EMPTY = 0x000002f6, 18244 PH_SC6_PA1_FIFO_FULL = 0x000002f7, 18245 PH_SC6_PA1_NULL_WE = 0x000002f8, 18246 PH_SC6_PA1_EVENT_WE = 0x000002f9, 18247 PH_SC6_PA1_FPOV_WE = 0x000002fa, 18248 PH_SC6_PA1_LPOV_WE = 0x000002fb, 18249 PH_SC6_PA1_EOP_WE = 0x000002fc, 18250 PH_SC6_PA1_DATA_FIFO_EOP_RD = 0x000002fd, 18251 PH_SC6_PA1_EOPG_WE = 0x000002fe, 18252 PH_SC6_PA1_DEALLOC_4_0_RD = 0x000002ff, 18253 PH_SC6_PA2_DATA_FIFO_RD = 0x00000300, 18254 PH_SC6_PA2_DATA_FIFO_WE = 0x00000301, 18255 PH_SC6_PA2_FIFO_EMPTY = 0x00000302, 18256 PH_SC6_PA2_FIFO_FULL = 0x00000303, 18257 PH_SC6_PA2_NULL_WE = 0x00000304, 18258 PH_SC6_PA2_EVENT_WE = 0x00000305, 18259 PH_SC6_PA2_FPOV_WE = 0x00000306, 18260 PH_SC6_PA2_LPOV_WE = 0x00000307, 18261 PH_SC6_PA2_EOP_WE = 0x00000308, 18262 PH_SC6_PA2_DATA_FIFO_EOP_RD = 0x00000309, 18263 PH_SC6_PA2_EOPG_WE = 0x0000030a, 18264 PH_SC6_PA2_DEALLOC_4_0_RD = 0x0000030b, 18265 PH_SC6_PA3_DATA_FIFO_RD = 0x0000030c, 18266 PH_SC6_PA3_DATA_FIFO_WE = 0x0000030d, 18267 PH_SC6_PA3_FIFO_EMPTY = 0x0000030e, 18268 PH_SC6_PA3_FIFO_FULL = 0x0000030f, 18269 PH_SC6_PA3_NULL_WE = 0x00000310, 18270 PH_SC6_PA3_EVENT_WE = 0x00000311, 18271 PH_SC6_PA3_FPOV_WE = 0x00000312, 18272 PH_SC6_PA3_LPOV_WE = 0x00000313, 18273 PH_SC6_PA3_EOP_WE = 0x00000314, 18274 PH_SC6_PA3_DATA_FIFO_EOP_RD = 0x00000315, 18275 PH_SC6_PA3_EOPG_WE = 0x00000316, 18276 PH_SC6_PA3_DEALLOC_4_0_RD = 0x00000317, 18277 PH_SC6_PA4_DATA_FIFO_RD = 0x00000318, 18278 PH_SC6_PA4_DATA_FIFO_WE = 0x00000319, 18279 PH_SC6_PA4_FIFO_EMPTY = 0x0000031a, 18280 PH_SC6_PA4_FIFO_FULL = 0x0000031b, 18281 PH_SC6_PA4_NULL_WE = 0x0000031c, 18282 PH_SC6_PA4_EVENT_WE = 0x0000031d, 18283 PH_SC6_PA4_FPOV_WE = 0x0000031e, 18284 PH_SC6_PA4_LPOV_WE = 0x0000031f, 18285 PH_SC6_PA4_EOP_WE = 0x00000320, 18286 PH_SC6_PA4_DATA_FIFO_EOP_RD = 0x00000321, 18287 PH_SC6_PA4_EOPG_WE = 0x00000322, 18288 PH_SC6_PA4_DEALLOC_4_0_RD = 0x00000323, 18289 PH_SC6_PA5_DATA_FIFO_RD = 0x00000324, 18290 PH_SC6_PA5_DATA_FIFO_WE = 0x00000325, 18291 PH_SC6_PA5_FIFO_EMPTY = 0x00000326, 18292 PH_SC6_PA5_FIFO_FULL = 0x00000327, 18293 PH_SC6_PA5_NULL_WE = 0x00000328, 18294 PH_SC6_PA5_EVENT_WE = 0x00000329, 18295 PH_SC6_PA5_FPOV_WE = 0x0000032a, 18296 PH_SC6_PA5_LPOV_WE = 0x0000032b, 18297 PH_SC6_PA5_EOP_WE = 0x0000032c, 18298 PH_SC6_PA5_DATA_FIFO_EOP_RD = 0x0000032d, 18299 PH_SC6_PA5_EOPG_WE = 0x0000032e, 18300 PH_SC6_PA5_DEALLOC_4_0_RD = 0x0000032f, 18301 PH_SC6_PA6_DATA_FIFO_RD = 0x00000330, 18302 PH_SC6_PA6_DATA_FIFO_WE = 0x00000331, 18303 PH_SC6_PA6_FIFO_EMPTY = 0x00000332, 18304 PH_SC6_PA6_FIFO_FULL = 0x00000333, 18305 PH_SC6_PA6_NULL_WE = 0x00000334, 18306 PH_SC6_PA6_EVENT_WE = 0x00000335, 18307 PH_SC6_PA6_FPOV_WE = 0x00000336, 18308 PH_SC6_PA6_LPOV_WE = 0x00000337, 18309 PH_SC6_PA6_EOP_WE = 0x00000338, 18310 PH_SC6_PA6_DATA_FIFO_EOP_RD = 0x00000339, 18311 PH_SC6_PA6_EOPG_WE = 0x0000033a, 18312 PH_SC6_PA6_DEALLOC_4_0_RD = 0x0000033b, 18313 PH_SC6_PA7_DATA_FIFO_RD = 0x0000033c, 18314 PH_SC6_PA7_DATA_FIFO_WE = 0x0000033d, 18315 PH_SC6_PA7_FIFO_EMPTY = 0x0000033e, 18316 PH_SC6_PA7_FIFO_FULL = 0x0000033f, 18317 PH_SC6_PA7_NULL_WE = 0x00000340, 18318 PH_SC6_PA7_EVENT_WE = 0x00000341, 18319 PH_SC6_PA7_FPOV_WE = 0x00000342, 18320 PH_SC6_PA7_LPOV_WE = 0x00000343, 18321 PH_SC6_PA7_EOP_WE = 0x00000344, 18322 PH_SC6_PA7_DATA_FIFO_EOP_RD = 0x00000345, 18323 PH_SC6_PA7_EOPG_WE = 0x00000346, 18324 PH_SC6_PA7_DEALLOC_4_0_RD = 0x00000347, 18325 PH_SC7_SRPS_WINDOW_VALID = 0x00000348, 18326 PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000349, 18327 PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000034a, 18328 PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000034b, 18329 PH_SC7_ARB_STALLED_FROM_BELOW = 0x0000034c, 18330 PH_SC7_ARB_STARVED_FROM_ABOVE = 0x0000034d, 18331 PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e, 18332 PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f, 18333 PH_SC7_ARB_BUSY = 0x00000350, 18334 PH_SC7_ARB_PA_BUSY_SOP = 0x00000351, 18335 PH_SC7_ARB_EOP_POP_SYNC_POP = 0x00000352, 18336 PH_SC7_ARB_EVENT_SYNC_POP = 0x00000353, 18337 PH_SC7_PS_ENG_MULTICYCLE_BUBBLE = 0x00000354, 18338 PH_SC7_EOP_SYNC_WINDOW = 0x00000355, 18339 PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000356, 18340 PH_SC7_BUSY_CNT_NOT_ZERO = 0x00000357, 18341 PH_SC7_SEND = 0x00000358, 18342 PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000359, 18343 PH_SC7_CREDIT_AT_MAX = 0x0000035a, 18344 PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000035b, 18345 PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035c, 18346 PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035d, 18347 PH_SC7_GFX_PIPE0_TO_1_TRANSITION = 0x0000035e, 18348 PH_SC7_GFX_PIPE1_TO_0_TRANSITION = 0x0000035f, 18349 PH_SC7_PA0_DATA_FIFO_RD = 0x00000360, 18350 PH_SC7_PA0_DATA_FIFO_WE = 0x00000361, 18351 PH_SC7_PA0_FIFO_EMPTY = 0x00000362, 18352 PH_SC7_PA0_FIFO_FULL = 0x00000363, 18353 PH_SC7_PA0_NULL_WE = 0x00000364, 18354 PH_SC7_PA0_EVENT_WE = 0x00000365, 18355 PH_SC7_PA0_FPOV_WE = 0x00000366, 18356 PH_SC7_PA0_LPOV_WE = 0x00000367, 18357 PH_SC7_PA0_EOP_WE = 0x00000368, 18358 PH_SC7_PA0_DATA_FIFO_EOP_RD = 0x00000369, 18359 PH_SC7_PA0_EOPG_WE = 0x0000036a, 18360 PH_SC7_PA0_DEALLOC_4_0_RD = 0x0000036b, 18361 PH_SC7_PA1_DATA_FIFO_RD = 0x0000036c, 18362 PH_SC7_PA1_DATA_FIFO_WE = 0x0000036d, 18363 PH_SC7_PA1_FIFO_EMPTY = 0x0000036e, 18364 PH_SC7_PA1_FIFO_FULL = 0x0000036f, 18365 PH_SC7_PA1_NULL_WE = 0x00000370, 18366 PH_SC7_PA1_EVENT_WE = 0x00000371, 18367 PH_SC7_PA1_FPOV_WE = 0x00000372, 18368 PH_SC7_PA1_LPOV_WE = 0x00000373, 18369 PH_SC7_PA1_EOP_WE = 0x00000374, 18370 PH_SC7_PA1_DATA_FIFO_EOP_RD = 0x00000375, 18371 PH_SC7_PA1_EOPG_WE = 0x00000376, 18372 PH_SC7_PA1_DEALLOC_4_0_RD = 0x00000377, 18373 PH_SC7_PA2_DATA_FIFO_RD = 0x00000378, 18374 PH_SC7_PA2_DATA_FIFO_WE = 0x00000379, 18375 PH_SC7_PA2_FIFO_EMPTY = 0x0000037a, 18376 PH_SC7_PA2_FIFO_FULL = 0x0000037b, 18377 PH_SC7_PA2_NULL_WE = 0x0000037c, 18378 PH_SC7_PA2_EVENT_WE = 0x0000037d, 18379 PH_SC7_PA2_FPOV_WE = 0x0000037e, 18380 PH_SC7_PA2_LPOV_WE = 0x0000037f, 18381 PH_SC7_PA2_EOP_WE = 0x00000380, 18382 PH_SC7_PA2_DATA_FIFO_EOP_RD = 0x00000381, 18383 PH_SC7_PA2_EOPG_WE = 0x00000382, 18384 PH_SC7_PA2_DEALLOC_4_0_RD = 0x00000383, 18385 PH_SC7_PA3_DATA_FIFO_RD = 0x00000384, 18386 PH_SC7_PA3_DATA_FIFO_WE = 0x00000385, 18387 PH_SC7_PA3_FIFO_EMPTY = 0x00000386, 18388 PH_SC7_PA3_FIFO_FULL = 0x00000387, 18389 PH_SC7_PA3_NULL_WE = 0x00000388, 18390 PH_SC7_PA3_EVENT_WE = 0x00000389, 18391 PH_SC7_PA3_FPOV_WE = 0x0000038a, 18392 PH_SC7_PA3_LPOV_WE = 0x0000038b, 18393 PH_SC7_PA3_EOP_WE = 0x0000038c, 18394 PH_SC7_PA3_DATA_FIFO_EOP_RD = 0x0000038d, 18395 PH_SC7_PA3_EOPG_WE = 0x0000038e, 18396 PH_SC7_PA3_DEALLOC_4_0_RD = 0x0000038f, 18397 PH_SC7_PA4_DATA_FIFO_RD = 0x00000390, 18398 PH_SC7_PA4_DATA_FIFO_WE = 0x00000391, 18399 PH_SC7_PA4_FIFO_EMPTY = 0x00000392, 18400 PH_SC7_PA4_FIFO_FULL = 0x00000393, 18401 PH_SC7_PA4_NULL_WE = 0x00000394, 18402 PH_SC7_PA4_EVENT_WE = 0x00000395, 18403 PH_SC7_PA4_FPOV_WE = 0x00000396, 18404 PH_SC7_PA4_LPOV_WE = 0x00000397, 18405 PH_SC7_PA4_EOP_WE = 0x00000398, 18406 PH_SC7_PA4_DATA_FIFO_EOP_RD = 0x00000399, 18407 PH_SC7_PA4_EOPG_WE = 0x0000039a, 18408 PH_SC7_PA4_DEALLOC_4_0_RD = 0x0000039b, 18409 PH_SC7_PA5_DATA_FIFO_RD = 0x0000039c, 18410 PH_SC7_PA5_DATA_FIFO_WE = 0x0000039d, 18411 PH_SC7_PA5_FIFO_EMPTY = 0x0000039e, 18412 PH_SC7_PA5_FIFO_FULL = 0x0000039f, 18413 PH_SC7_PA5_NULL_WE = 0x000003a0, 18414 PH_SC7_PA5_EVENT_WE = 0x000003a1, 18415 PH_SC7_PA5_FPOV_WE = 0x000003a2, 18416 PH_SC7_PA5_LPOV_WE = 0x000003a3, 18417 PH_SC7_PA5_EOP_WE = 0x000003a4, 18418 PH_SC7_PA5_DATA_FIFO_EOP_RD = 0x000003a5, 18419 PH_SC7_PA5_EOPG_WE = 0x000003a6, 18420 PH_SC7_PA5_DEALLOC_4_0_RD = 0x000003a7, 18421 PH_SC7_PA6_DATA_FIFO_RD = 0x000003a8, 18422 PH_SC7_PA6_DATA_FIFO_WE = 0x000003a9, 18423 PH_SC7_PA6_FIFO_EMPTY = 0x000003aa, 18424 PH_SC7_PA6_FIFO_FULL = 0x000003ab, 18425 PH_SC7_PA6_NULL_WE = 0x000003ac, 18426 PH_SC7_PA6_EVENT_WE = 0x000003ad, 18427 PH_SC7_PA6_FPOV_WE = 0x000003ae, 18428 PH_SC7_PA6_LPOV_WE = 0x000003af, 18429 PH_SC7_PA6_EOP_WE = 0x000003b0, 18430 PH_SC7_PA6_DATA_FIFO_EOP_RD = 0x000003b1, 18431 PH_SC7_PA6_EOPG_WE = 0x000003b2, 18432 PH_SC7_PA6_DEALLOC_4_0_RD = 0x000003b3, 18433 PH_SC7_PA7_DATA_FIFO_RD = 0x000003b4, 18434 PH_SC7_PA7_DATA_FIFO_WE = 0x000003b5, 18435 PH_SC7_PA7_FIFO_EMPTY = 0x000003b6, 18436 PH_SC7_PA7_FIFO_FULL = 0x000003b7, 18437 PH_SC7_PA7_NULL_WE = 0x000003b8, 18438 PH_SC7_PA7_EVENT_WE = 0x000003b9, 18439 PH_SC7_PA7_FPOV_WE = 0x000003ba, 18440 PH_SC7_PA7_LPOV_WE = 0x000003bb, 18441 PH_SC7_PA7_EOP_WE = 0x000003bc, 18442 PH_SC7_PA7_DATA_FIFO_EOP_RD = 0x000003bd, 18443 PH_SC7_PA7_EOPG_WE = 0x000003be, 18444 PH_SC7_PA7_DEALLOC_4_0_RD = 0x000003bf, 18445 } PH_PERFCNT_SEL; 18446 18447 /* 18448 * SU_PERFCNT_SEL enum 18449 */ 18450 18451 typedef enum SU_PERFCNT_SEL { 18452 PERF_PAPC_PASX_REQ = 0x00000000, 18453 PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001, 18454 PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002, 18455 PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003, 18456 PERF_PAPC_PASX_FIRST_DEAD = 0x00000004, 18457 PERF_PAPC_PASX_SECOND_DEAD = 0x00000005, 18458 PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, 18459 PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, 18460 PERF_PAPC_PA_INPUT_PRIM = 0x00000008, 18461 PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009, 18462 PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a, 18463 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b, 18464 PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c, 18465 PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d, 18466 PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, 18467 PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, 18468 PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, 18469 PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, 18470 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, 18471 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, 18472 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, 18473 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, 18474 PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, 18475 PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, 18476 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, 18477 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, 18478 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, 18479 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, 18480 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, 18481 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, 18482 PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e, 18483 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, 18484 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, 18485 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, 18486 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, 18487 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, 18488 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, 18489 PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025, 18490 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, 18491 PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, 18492 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, 18493 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, 18494 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, 18495 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, 18496 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, 18497 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, 18498 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, 18499 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f, 18500 PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, 18501 PERF_PAPC_SU_INPUT_PRIM = 0x00000031, 18502 PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, 18503 PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, 18504 PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, 18505 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, 18506 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, 18507 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, 18508 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, 18509 PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, 18510 PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, 18511 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, 18512 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, 18513 PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, 18514 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, 18515 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, 18516 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, 18517 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, 18518 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, 18519 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, 18520 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, 18521 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, 18522 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, 18523 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, 18524 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, 18525 PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, 18526 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, 18527 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, 18528 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, 18529 PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, 18530 PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, 18531 PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, 18532 PERF_PAPC_PASX_REC_IDLE = 0x00000050, 18533 PERF_PAPC_PASX_REC_BUSY = 0x00000051, 18534 PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, 18535 PERF_PAPC_PASX_REC_STALLED = 0x00000053, 18536 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, 18537 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, 18538 PERF_PAPC_CCGSM_IDLE = 0x00000056, 18539 PERF_PAPC_CCGSM_BUSY = 0x00000057, 18540 PERF_PAPC_CCGSM_STALLED = 0x00000058, 18541 PERF_PAPC_CLPRIM_IDLE = 0x00000059, 18542 PERF_PAPC_CLPRIM_BUSY = 0x0000005a, 18543 PERF_PAPC_CLPRIM_STALLED = 0x0000005b, 18544 PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, 18545 PERF_PAPC_CLIPSM_IDLE = 0x0000005d, 18546 PERF_PAPC_CLIPSM_BUSY = 0x0000005e, 18547 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, 18548 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, 18549 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, 18550 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, 18551 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, 18552 PERF_PAPC_CLIPGA_IDLE = 0x00000064, 18553 PERF_PAPC_CLIPGA_BUSY = 0x00000065, 18554 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, 18555 PERF_PAPC_CLIPGA_STALLED = 0x00000067, 18556 PERF_PAPC_CLIP_IDLE = 0x00000068, 18557 PERF_PAPC_CLIP_BUSY = 0x00000069, 18558 PERF_PAPC_SU_IDLE = 0x0000006a, 18559 PERF_PAPC_SU_BUSY = 0x0000006b, 18560 PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, 18561 PERF_PAPC_SU_STALLED_SC = 0x0000006d, 18562 PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, 18563 PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, 18564 PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, 18565 PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071, 18566 PERF_PAPC_PASX_SE0_REQ = 0x00000072, 18567 PERF_PAPC_PASX_SE1_REQ = 0x00000073, 18568 PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074, 18569 PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075, 18570 PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076, 18571 PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077, 18572 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, 18573 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, 18574 PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a, 18575 PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, 18576 PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, 18577 PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d, 18578 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, 18579 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, 18580 PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080, 18581 PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081, 18582 PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082, 18583 PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, 18584 PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, 18585 PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085, 18586 PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, 18587 PERF_PAPC_SU_CULLED_PRIM = 0x00000087, 18588 PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088, 18589 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089, 18590 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a, 18591 PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b, 18592 PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c, 18593 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d, 18594 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e, 18595 PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f, 18596 PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090, 18597 PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091, 18598 PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092, 18599 PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093, 18600 PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094, 18601 PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095, 18602 PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096, 18603 PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097, 18604 PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098, 18605 PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 0x00000099, 18606 PERF_SMALL_PRIM_CULL_PRIM_1X1 = 0x0000009a, 18607 PERF_SMALL_PRIM_CULL_PRIM_2X1 = 0x0000009b, 18608 PERF_SMALL_PRIM_CULL_PRIM_1X2 = 0x0000009c, 18609 PERF_SMALL_PRIM_CULL_PRIM_2X2 = 0x0000009d, 18610 PERF_SMALL_PRIM_CULL_PRIM_3X1 = 0x0000009e, 18611 PERF_SMALL_PRIM_CULL_PRIM_1X3 = 0x0000009f, 18612 PERF_SMALL_PRIM_CULL_PRIM_3X2 = 0x000000a0, 18613 PERF_SMALL_PRIM_CULL_PRIM_2X3 = 0x000000a1, 18614 PERF_SMALL_PRIM_CULL_PRIM_NX1 = 0x000000a2, 18615 PERF_SMALL_PRIM_CULL_PRIM_1XN = 0x000000a3, 18616 PERF_SMALL_PRIM_CULL_PRIM_NX2 = 0x000000a4, 18617 PERF_SMALL_PRIM_CULL_PRIM_2XN = 0x000000a5, 18618 PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 0x000000a6, 18619 PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 0x000000a7, 18620 PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 0x000000a8, 18621 PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 0x000000a9, 18622 PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000aa, 18623 PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 0x000000ab, 18624 PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ac, 18625 PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 0x000000ad, 18626 PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ae, 18627 PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 0x000000af, 18628 PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000b0, 18629 PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1 = 0x000000b1, 18630 PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT = 0x000000b2, 18631 PERF_UTC_SIDEBAND_DRIVER_BUSY = 0x000000b3, 18632 PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1 = 0x000000b4, 18633 PERF_UTC_INDEX_DRIVER_STALLING_CLIENT = 0x000000b5, 18634 PERF_UTC_INDEX_DRIVER_BUSY = 0x000000b6, 18635 PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1 = 0x000000b7, 18636 PERF_UTC_POSITION_DRIVER_STALLING_CLIENT = 0x000000b8, 18637 PERF_UTC_POSITION_DRIVER_BUSY = 0x000000b9, 18638 PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1 = 0x000000ba, 18639 PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER = 0x000000bb, 18640 PERF_UTC_SIDEBAND_RECEIVER_BUSY = 0x000000bc, 18641 PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1 = 0x000000bd, 18642 PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER = 0x000000be, 18643 PERF_UTC_INDEX_RECEIVER_BUSY = 0x000000bf, 18644 PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1 = 0x000000c0, 18645 PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER = 0x000000c1, 18646 PERF_UTC_POSITION_RECEIVER_BUSY = 0x000000c2, 18647 PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE = 0x000000c3, 18648 PERF_TCIF_STALLING_CLIENT_NO_CREDITS = 0x000000c4, 18649 PERF_TCIF_BUSY = 0x000000c5, 18650 PERF_TCIF_SIDEBAND_RDREQ = 0x000000c6, 18651 PERF_TCIF_INDEX_RDREQ = 0x000000c7, 18652 PERF_TCIF_POSITION_RDREQ = 0x000000c8, 18653 PERF_SIDEBAND_WAITING_ON_UTCL1 = 0x000000c9, 18654 PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY = 0x000000ca, 18655 PERF_WRITING_TO_SIDEBAND_MEMORY = 0x000000cb, 18656 PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD = 0x000000cc, 18657 PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD = 0x000000cd, 18658 PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD = 0x000000ce, 18659 PERF_SIDEBAND_WAITING_ON_RETURNED_DATA = 0x000000cf, 18660 PERF_SIDEBAND_POP_BIT_FIFO_FULL = 0x000000d0, 18661 PERF_SIDEBAND_FIFO_VMID_FIFO_FULL = 0x000000d1, 18662 PERF_SIDEBAND_INVALID_REFETCH = 0x000000d2, 18663 PERF_SIDEBAND_QUALIFIED_BUSY = 0x000000d3, 18664 PERF_SIDEBAND_QUALIFIED_STARVED = 0x000000d4, 18665 PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_ = 0x000000d5, 18666 PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_ = 0x000000d6, 18667 PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_ = 0x000000d7, 18668 PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_ = 0x000000d8, 18669 PERF_INDEX_REQUEST_WAITING_ON_TOKENS = 0x000000d9, 18670 PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO = 0x000000da, 18671 PERF_INDEX_REQUEST_QUALIFIED_BUSY = 0x000000db, 18672 PERF_INDEX_REQUEST_QUALIFIED_STARVED = 0x000000dc, 18673 PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE = 0x000000dd, 18674 PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO = 0x000000de, 18675 PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE = 0x000000df, 18676 PERF_INDEX_RECEIVE_QUALIFIED_BUSY = 0x000000e0, 18677 PERF_INDEX_RECEIVE_QUALIFIED_STARVED = 0x000000e1, 18678 PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE = 0x000000e2, 18679 PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE = 0x000000e3, 18680 PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE = 0x000000e4, 18681 PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE = 0x000000e5, 18682 PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE = 0x000000e6, 18683 PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE = 0x000000e7, 18684 PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE = 0x000000e8, 18685 PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE = 0x000000e9, 18686 PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE = 0x000000ea, 18687 PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE = 0x000000eb, 18688 PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE = 0x000000ec, 18689 PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE = 0x000000ed, 18690 PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE = 0x000000ee, 18691 PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE = 0x000000ef, 18692 PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE = 0x000000f0, 18693 PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE = 0x000000f1, 18694 PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE = 0x000000f2, 18695 PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x000000f3, 18696 PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x000000f4, 18697 PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO = 0x000000f5, 18698 PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO = 0x000000f6, 18699 PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO = 0x000000f7, 18700 PERF_POS_REQ_STALLED_BY_NO_TOKENS = 0x000000f8, 18701 PERF_POS_REQ_STARVED_BY_NO_PRIM = 0x000000f9, 18702 PERF_POS_REQ_STALLED_BY_UTCL1 = 0x000000fa, 18703 PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x000000fb, 18704 PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x000000fc, 18705 PERF_POS_REQ_QUALIFIED_BUSY = 0x000000fd, 18706 PERF_POS_REQ_QUALIFIED_STARVED = 0x000000fe, 18707 PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM = 0x000000ff, 18708 PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM = 0x00000100, 18709 PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM = 0x00000101, 18710 PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM = 0x00000102, 18711 PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO = 0x00000103, 18712 PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO = 0x00000104, 18713 PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE = 0x00000105, 18714 PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE = 0x00000106, 18715 PERF_POS_RET_QUALIFIED_BUSY = 0x00000107, 18716 PERF_POS_RET_QUALIFIED_STARVED = 0x00000108, 18717 PERF_POS_RET_1_CACHELINE_POSITION_USED = 0x00000109, 18718 PERF_POS_RET_2_CACHELINE_POSITION_USED = 0x0000010a, 18719 PERF_POS_RET_3_CACHELINE_POSITION_USED = 0x0000010b, 18720 PERF_POS_RET_4_CACHELINE_POSITION_USED = 0x0000010c, 18721 PERF_TC_INDEX_LATENCY_BIN0 = 0x0000010d, 18722 PERF_TC_INDEX_LATENCY_BIN1 = 0x0000010e, 18723 PERF_TC_INDEX_LATENCY_BIN2 = 0x0000010f, 18724 PERF_TC_INDEX_LATENCY_BIN3 = 0x00000110, 18725 PERF_TC_INDEX_LATENCY_BIN4 = 0x00000111, 18726 PERF_TC_INDEX_LATENCY_BIN5 = 0x00000112, 18727 PERF_TC_INDEX_LATENCY_BIN6 = 0x00000113, 18728 PERF_TC_INDEX_LATENCY_BIN7 = 0x00000114, 18729 PERF_TC_INDEX_LATENCY_BIN8 = 0x00000115, 18730 PERF_TC_INDEX_LATENCY_BIN9 = 0x00000116, 18731 PERF_TC_INDEX_LATENCY_BIN10 = 0x00000117, 18732 PERF_TC_INDEX_LATENCY_BIN11 = 0x00000118, 18733 PERF_TC_INDEX_LATENCY_BIN12 = 0x00000119, 18734 PERF_TC_INDEX_LATENCY_BIN13 = 0x0000011a, 18735 PERF_TC_INDEX_LATENCY_BIN14 = 0x0000011b, 18736 PERF_TC_INDEX_LATENCY_BIN15 = 0x0000011c, 18737 PERF_TC_POSITION_LATENCY_BIN0 = 0x0000011d, 18738 PERF_TC_POSITION_LATENCY_BIN1 = 0x0000011e, 18739 PERF_TC_POSITION_LATENCY_BIN2 = 0x0000011f, 18740 PERF_TC_POSITION_LATENCY_BIN3 = 0x00000120, 18741 PERF_TC_POSITION_LATENCY_BIN4 = 0x00000121, 18742 PERF_TC_POSITION_LATENCY_BIN5 = 0x00000122, 18743 PERF_TC_POSITION_LATENCY_BIN6 = 0x00000123, 18744 PERF_TC_POSITION_LATENCY_BIN7 = 0x00000124, 18745 PERF_TC_POSITION_LATENCY_BIN8 = 0x00000125, 18746 PERF_TC_POSITION_LATENCY_BIN9 = 0x00000126, 18747 PERF_TC_POSITION_LATENCY_BIN10 = 0x00000127, 18748 PERF_TC_POSITION_LATENCY_BIN11 = 0x00000128, 18749 PERF_TC_POSITION_LATENCY_BIN12 = 0x00000129, 18750 PERF_TC_POSITION_LATENCY_BIN13 = 0x0000012a, 18751 PERF_TC_POSITION_LATENCY_BIN14 = 0x0000012b, 18752 PERF_TC_POSITION_LATENCY_BIN15 = 0x0000012c, 18753 PERF_TC_STREAM0_DATA_AVAILABLE = 0x0000012d, 18754 PERF_TC_STREAM1_DATA_AVAILABLE = 0x0000012e, 18755 PERF_TC_STREAM2_DATA_AVAILABLE = 0x0000012f, 18756 PERF_PAWD_DEALLOC_FIFO_IS_FULL = 0x00000130, 18757 PERF_PAWD_DEALLOC_WAITING_TO_BE_READ = 0x00000131, 18758 PERF_SHOOTDOWN_WAIT_ON_UTCL1 = 0x00000132, 18759 PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND = 0x00000133, 18760 PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX = 0x00000134, 18761 PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION = 0x00000135, 18762 PERF_SHOOTDOWN_WAIT_ALL_CLEAN = 0x00000136, 18763 PERF_SHOOTDOWN_WAIT_DEASSERT = 0x00000137, 18764 PERF_UTCL1_TRANSLATION_MISS_CLIENT0 = 0x00000138, 18765 PERF_UTCL1_TRANSLATION_MISS_CLIENT1 = 0x00000139, 18766 PERF_UTCL1_TRANSLATION_MISS_CLIENT2 = 0x0000013a, 18767 PERF_UTCL1_PERMISSION_MISS_CLIENT0 = 0x0000013b, 18768 PERF_UTCL1_PERMISSION_MISS_CLIENT1 = 0x0000013c, 18769 PERF_UTCL1_PERMISSION_MISS_CLIENT2 = 0x0000013d, 18770 PERF_UTCL1_TRANSLATION_HIT_CLIENT0 = 0x0000013e, 18771 PERF_UTCL1_TRANSLATION_HIT_CLIENT1 = 0x0000013f, 18772 PERF_UTCL1_TRANSLATION_HIT_CLIENT2 = 0x00000140, 18773 PERF_UTCL1_REQUEST_CLIENT0 = 0x00000141, 18774 PERF_UTCL1_REQUEST_CLIENT1 = 0x00000142, 18775 PERF_UTCL1_REQUEST_CLIENT2 = 0x00000143, 18776 PERF_UTCL1_STALL_MISSFIFO_FULL = 0x00000144, 18777 PERF_UTCL1_STALL_INFLIGHT_MAX = 0x00000145, 18778 PERF_UTCL1_STALL_LRU_INFLIGHT = 0x00000146, 18779 PERF_UTCL1_STALL_MULTI_MISS = 0x00000147, 18780 PERF_UTCL1_LFIFO_FULL = 0x00000148, 18781 PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0 = 0x00000149, 18782 PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1 = 0x0000014a, 18783 PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2 = 0x0000014b, 18784 PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x0000014c, 18785 PERF_UTCL1_UTCL2_REQ = 0x0000014d, 18786 PERF_UTCL1_UTCL2_RET = 0x0000014e, 18787 PERF_UTCL1_UTCL2_INFLIGHT = 0x0000014f, 18788 PERF_CLIENT_UTCL1_INFLIGHT = 0x00000150, 18789 PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 0x00000151, 18790 PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 0x00000152, 18791 PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 0x00000153, 18792 PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 0x00000154, 18793 PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 0x00000155, 18794 PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 0x00000156, 18795 PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 0x00000157, 18796 PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 0x00000158, 18797 PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 0x00000159, 18798 PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 0x0000015a, 18799 PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 0x0000015b, 18800 PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 0x0000015c, 18801 PERF_PA_VERTEX_FIFO_FULL = 0x0000015d, 18802 PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 0x0000015e, 18803 PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 0x0000015f, 18804 PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 0x00000160, 18805 ENGG_CSB_MACHINE_IS_STARVED = 0x00000163, 18806 ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 0x00000164, 18807 ENGG_CSB_MACHINE_STALLED_BY_SPI = 0x00000165, 18808 ENGG_CSB_GE_INPUT_FIFO_FULL = 0x00000166, 18809 ENGG_CSB_SPI_INPUT_FIFO_FULL = 0x00000167, 18810 ENGG_CSB_OBJECTID_INPUT_FIFO_FULL = 0x00000168, 18811 ENGG_CSB_PRIM_COUNT_EQ0 = 0x00000169, 18812 ENGG_CSB_GE_SENDING_SUBGROUP = 0x0000016a, 18813 ENGG_CSB_DELAY_BIN00 = 0x0000016b, 18814 ENGG_CSB_DELAY_BIN01 = 0x0000016c, 18815 ENGG_CSB_DELAY_BIN02 = 0x0000016d, 18816 ENGG_CSB_DELAY_BIN03 = 0x0000016e, 18817 ENGG_CSB_DELAY_BIN04 = 0x0000016f, 18818 ENGG_CSB_DELAY_BIN05 = 0x00000170, 18819 ENGG_CSB_DELAY_BIN06 = 0x00000171, 18820 ENGG_CSB_DELAY_BIN07 = 0x00000172, 18821 ENGG_CSB_DELAY_BIN08 = 0x00000173, 18822 ENGG_CSB_DELAY_BIN09 = 0x00000174, 18823 ENGG_CSB_DELAY_BIN10 = 0x00000175, 18824 ENGG_CSB_DELAY_BIN11 = 0x00000176, 18825 ENGG_CSB_DELAY_BIN12 = 0x00000177, 18826 ENGG_CSB_DELAY_BIN13 = 0x00000178, 18827 ENGG_CSB_DELAY_BIN14 = 0x00000179, 18828 ENGG_CSB_DELAY_BIN15 = 0x0000017a, 18829 ENGG_CSB_SPI_DELAY_BIN00 = 0x0000017b, 18830 ENGG_CSB_SPI_DELAY_BIN01 = 0x0000017c, 18831 ENGG_CSB_SPI_DELAY_BIN02 = 0x0000017d, 18832 ENGG_CSB_SPI_DELAY_BIN03 = 0x0000017e, 18833 ENGG_CSB_SPI_DELAY_BIN04 = 0x0000017f, 18834 ENGG_CSB_SPI_DELAY_BIN05 = 0x00000180, 18835 ENGG_CSB_SPI_DELAY_BIN06 = 0x00000181, 18836 ENGG_CSB_SPI_DELAY_BIN07 = 0x00000182, 18837 ENGG_CSB_SPI_DELAY_BIN08 = 0x00000183, 18838 ENGG_CSB_SPI_DELAY_BIN09 = 0x00000184, 18839 ENGG_CSB_SPI_DELAY_BIN10 = 0x00000185, 18840 ENGG_CSB_SPI_DELAY_BIN11 = 0x00000186, 18841 ENGG_CSB_SPI_DELAY_BIN12 = 0x00000187, 18842 ENGG_CSB_SPI_DELAY_BIN13 = 0x00000188, 18843 ENGG_CSB_SPI_DELAY_BIN14 = 0x00000189, 18844 ENGG_CSB_SPI_DELAY_BIN15 = 0x0000018a, 18845 ENGG_INDEX_REQ_STARVED = 0x0000018b, 18846 ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x0000018c, 18847 ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x0000018d, 18848 ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 0x0000018e, 18849 ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 0x0000018f, 18850 ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 0x00000190, 18851 ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 0x00000191, 18852 ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 0x00000192, 18853 ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 0x00000193, 18854 ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 0x00000194, 18855 ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 0x00000195, 18856 ENGG_INDEX_RET_SXRX_READING_EVENT = 0x00000196, 18857 ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 0x00000197, 18858 ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 0x00000198, 18859 ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 0x00000199, 18860 ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 0x0000019a, 18861 ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 0x0000019b, 18862 ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 0x0000019c, 18863 ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS = 0x0000019d, 18864 ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS = 0x0000019e, 18865 ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS = 0x0000019f, 18866 ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x000001a0, 18867 ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x000001a1, 18868 ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 0x000001a2, 18869 ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x000001a3, 18870 ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x000001a4, 18871 ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY = 0x000001a5, 18872 ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED = 0x000001a6, 18873 ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM = 0x000001a7, 18874 ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM = 0x000001a8, 18875 ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM = 0x000001a9, 18876 ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM = 0x000001aa, 18877 ENGG_POS_REQ_STARVED = 0x000001ab, 18878 ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO = 0x000001ac, 18879 } SU_PERFCNT_SEL; 18880 18881 /* 18882 * SC_PERFCNT_SEL enum 18883 */ 18884 18885 typedef enum SC_PERFCNT_SEL { 18886 SC_SRPS_WINDOW_VALID = 0x00000000, 18887 SC_PSSW_WINDOW_VALID = 0x00000001, 18888 SC_TPQZ_WINDOW_VALID = 0x00000002, 18889 SC_QZQP_WINDOW_VALID = 0x00000003, 18890 SC_TRPK_WINDOW_VALID = 0x00000004, 18891 SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, 18892 SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, 18893 SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, 18894 SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, 18895 SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, 18896 SC_STARVED_BY_PA = 0x0000000a, 18897 SC_STALLED_BY_PRIMFIFO = 0x0000000b, 18898 SC_STALLED_BY_DB_TILE = 0x0000000c, 18899 SC_STARVED_BY_DB_TILE = 0x0000000d, 18900 SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, 18901 SC_STALLED_BY_TILEFIFO = 0x0000000f, 18902 SC_STALLED_BY_DB_QUAD = 0x00000010, 18903 SC_STARVED_BY_DB_QUAD = 0x00000011, 18904 SC_STALLED_BY_QUADFIFO = 0x00000012, 18905 SC_STALLED_BY_BCI = 0x00000013, 18906 SC_STALLED_BY_SPI = 0x00000014, 18907 SC_SCISSOR_DISCARD = 0x00000015, 18908 SC_BB_DISCARD = 0x00000016, 18909 SC_SUPERTILE_COUNT = 0x00000017, 18910 SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, 18911 SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, 18912 SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, 18913 SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, 18914 SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, 18915 SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, 18916 SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, 18917 SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, 18918 SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, 18919 SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, 18920 SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, 18921 SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, 18922 SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, 18923 SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, 18924 SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, 18925 SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, 18926 SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, 18927 SC_TILE_PER_PRIM_H0 = 0x00000029, 18928 SC_TILE_PER_PRIM_H1 = 0x0000002a, 18929 SC_TILE_PER_PRIM_H2 = 0x0000002b, 18930 SC_TILE_PER_PRIM_H3 = 0x0000002c, 18931 SC_TILE_PER_PRIM_H4 = 0x0000002d, 18932 SC_TILE_PER_PRIM_H5 = 0x0000002e, 18933 SC_TILE_PER_PRIM_H6 = 0x0000002f, 18934 SC_TILE_PER_PRIM_H7 = 0x00000030, 18935 SC_TILE_PER_PRIM_H8 = 0x00000031, 18936 SC_TILE_PER_PRIM_H9 = 0x00000032, 18937 SC_TILE_PER_PRIM_H10 = 0x00000033, 18938 SC_TILE_PER_PRIM_H11 = 0x00000034, 18939 SC_TILE_PER_PRIM_H12 = 0x00000035, 18940 SC_TILE_PER_PRIM_H13 = 0x00000036, 18941 SC_TILE_PER_PRIM_H14 = 0x00000037, 18942 SC_TILE_PER_PRIM_H15 = 0x00000038, 18943 SC_TILE_PER_PRIM_H16 = 0x00000039, 18944 SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, 18945 SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, 18946 SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, 18947 SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, 18948 SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, 18949 SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, 18950 SC_TILE_PER_SUPERTILE_H6 = 0x00000040, 18951 SC_TILE_PER_SUPERTILE_H7 = 0x00000041, 18952 SC_TILE_PER_SUPERTILE_H8 = 0x00000042, 18953 SC_TILE_PER_SUPERTILE_H9 = 0x00000043, 18954 SC_TILE_PER_SUPERTILE_H10 = 0x00000044, 18955 SC_TILE_PER_SUPERTILE_H11 = 0x00000045, 18956 SC_TILE_PER_SUPERTILE_H12 = 0x00000046, 18957 SC_TILE_PER_SUPERTILE_H13 = 0x00000047, 18958 SC_TILE_PER_SUPERTILE_H14 = 0x00000048, 18959 SC_TILE_PER_SUPERTILE_H15 = 0x00000049, 18960 SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, 18961 SC_TILE_PICKED_H1 = 0x0000004b, 18962 SC_TILE_PICKED_H2 = 0x0000004c, 18963 SC_TILE_PICKED_H3 = 0x0000004d, 18964 SC_TILE_PICKED_H4 = 0x0000004e, 18965 SC_QZ0_TILE_COUNT = 0x0000004f, 18966 SC_QZ1_TILE_COUNT = 0x00000050, 18967 SC_QZ2_TILE_COUNT = 0x00000051, 18968 SC_QZ3_TILE_COUNT = 0x00000052, 18969 SC_QZ0_TILE_COVERED_COUNT = 0x00000053, 18970 SC_QZ1_TILE_COVERED_COUNT = 0x00000054, 18971 SC_QZ2_TILE_COVERED_COUNT = 0x00000055, 18972 SC_QZ3_TILE_COVERED_COUNT = 0x00000056, 18973 SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057, 18974 SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00000058, 18975 SC_QZ2_TILE_NOT_COVERED_COUNT = 0x00000059, 18976 SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005a, 18977 SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b, 18978 SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c, 18979 SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d, 18980 SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e, 18981 SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f, 18982 SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060, 18983 SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061, 18984 SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062, 18985 SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063, 18986 SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064, 18987 SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065, 18988 SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066, 18989 SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067, 18990 SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068, 18991 SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069, 18992 SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a, 18993 SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b, 18994 SC_QZ1_QUAD_PER_TILE_H0 = 0x0000006c, 18995 SC_QZ1_QUAD_PER_TILE_H1 = 0x0000006d, 18996 SC_QZ1_QUAD_PER_TILE_H2 = 0x0000006e, 18997 SC_QZ1_QUAD_PER_TILE_H3 = 0x0000006f, 18998 SC_QZ1_QUAD_PER_TILE_H4 = 0x00000070, 18999 SC_QZ1_QUAD_PER_TILE_H5 = 0x00000071, 19000 SC_QZ1_QUAD_PER_TILE_H6 = 0x00000072, 19001 SC_QZ1_QUAD_PER_TILE_H7 = 0x00000073, 19002 SC_QZ1_QUAD_PER_TILE_H8 = 0x00000074, 19003 SC_QZ1_QUAD_PER_TILE_H9 = 0x00000075, 19004 SC_QZ1_QUAD_PER_TILE_H10 = 0x00000076, 19005 SC_QZ1_QUAD_PER_TILE_H11 = 0x00000077, 19006 SC_QZ1_QUAD_PER_TILE_H12 = 0x00000078, 19007 SC_QZ1_QUAD_PER_TILE_H13 = 0x00000079, 19008 SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007a, 19009 SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007b, 19010 SC_QZ1_QUAD_PER_TILE_H16 = 0x0000007c, 19011 SC_QZ2_QUAD_PER_TILE_H0 = 0x0000007d, 19012 SC_QZ2_QUAD_PER_TILE_H1 = 0x0000007e, 19013 SC_QZ2_QUAD_PER_TILE_H2 = 0x0000007f, 19014 SC_QZ2_QUAD_PER_TILE_H3 = 0x00000080, 19015 SC_QZ2_QUAD_PER_TILE_H4 = 0x00000081, 19016 SC_QZ2_QUAD_PER_TILE_H5 = 0x00000082, 19017 SC_QZ2_QUAD_PER_TILE_H6 = 0x00000083, 19018 SC_QZ2_QUAD_PER_TILE_H7 = 0x00000084, 19019 SC_QZ2_QUAD_PER_TILE_H8 = 0x00000085, 19020 SC_QZ2_QUAD_PER_TILE_H9 = 0x00000086, 19021 SC_QZ2_QUAD_PER_TILE_H10 = 0x00000087, 19022 SC_QZ2_QUAD_PER_TILE_H11 = 0x00000088, 19023 SC_QZ2_QUAD_PER_TILE_H12 = 0x00000089, 19024 SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008a, 19025 SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008b, 19026 SC_QZ2_QUAD_PER_TILE_H15 = 0x0000008c, 19027 SC_QZ2_QUAD_PER_TILE_H16 = 0x0000008d, 19028 SC_QZ3_QUAD_PER_TILE_H0 = 0x0000008e, 19029 SC_QZ3_QUAD_PER_TILE_H1 = 0x0000008f, 19030 SC_QZ3_QUAD_PER_TILE_H2 = 0x00000090, 19031 SC_QZ3_QUAD_PER_TILE_H3 = 0x00000091, 19032 SC_QZ3_QUAD_PER_TILE_H4 = 0x00000092, 19033 SC_QZ3_QUAD_PER_TILE_H5 = 0x00000093, 19034 SC_QZ3_QUAD_PER_TILE_H6 = 0x00000094, 19035 SC_QZ3_QUAD_PER_TILE_H7 = 0x00000095, 19036 SC_QZ3_QUAD_PER_TILE_H8 = 0x00000096, 19037 SC_QZ3_QUAD_PER_TILE_H9 = 0x00000097, 19038 SC_QZ3_QUAD_PER_TILE_H10 = 0x00000098, 19039 SC_QZ3_QUAD_PER_TILE_H11 = 0x00000099, 19040 SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009a, 19041 SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009b, 19042 SC_QZ3_QUAD_PER_TILE_H14 = 0x0000009c, 19043 SC_QZ3_QUAD_PER_TILE_H15 = 0x0000009d, 19044 SC_QZ3_QUAD_PER_TILE_H16 = 0x0000009e, 19045 SC_QZ0_QUAD_COUNT = 0x0000009f, 19046 SC_QZ1_QUAD_COUNT = 0x000000a0, 19047 SC_QZ2_QUAD_COUNT = 0x000000a1, 19048 SC_QZ3_QUAD_COUNT = 0x000000a2, 19049 SC_P0_HIZ_TILE_COUNT = 0x000000a3, 19050 SC_P1_HIZ_TILE_COUNT = 0x000000a4, 19051 SC_P2_HIZ_TILE_COUNT = 0x000000a5, 19052 SC_P3_HIZ_TILE_COUNT = 0x000000a6, 19053 SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7, 19054 SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8, 19055 SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9, 19056 SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa, 19057 SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab, 19058 SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac, 19059 SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad, 19060 SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae, 19061 SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af, 19062 SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0, 19063 SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1, 19064 SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2, 19065 SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3, 19066 SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4, 19067 SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5, 19068 SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6, 19069 SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7, 19070 SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000b8, 19071 SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000b9, 19072 SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000ba, 19073 SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bb, 19074 SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000bc, 19075 SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000bd, 19076 SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000be, 19077 SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000bf, 19078 SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c0, 19079 SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c1, 19080 SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c2, 19081 SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c3, 19082 SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c4, 19083 SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c5, 19084 SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000c6, 19085 SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000c7, 19086 SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000c8, 19087 SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000c9, 19088 SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ca, 19089 SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cb, 19090 SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000cc, 19091 SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000cd, 19092 SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000ce, 19093 SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000cf, 19094 SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d0, 19095 SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d1, 19096 SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d2, 19097 SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d3, 19098 SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d4, 19099 SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d5, 19100 SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000d6, 19101 SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000d7, 19102 SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000d8, 19103 SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000d9, 19104 SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000da, 19105 SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000db, 19106 SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000dc, 19107 SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000dd, 19108 SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000de, 19109 SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000df, 19110 SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e0, 19111 SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e1, 19112 SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e2, 19113 SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e3, 19114 SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e4, 19115 SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e5, 19116 SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000e6, 19117 SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000e7, 19118 SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000e8, 19119 SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000e9, 19120 SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ea, 19121 SC_P0_HIZ_QUAD_COUNT = 0x000000eb, 19122 SC_P1_HIZ_QUAD_COUNT = 0x000000ec, 19123 SC_P2_HIZ_QUAD_COUNT = 0x000000ed, 19124 SC_P3_HIZ_QUAD_COUNT = 0x000000ee, 19125 SC_P0_DETAIL_QUAD_COUNT = 0x000000ef, 19126 SC_P1_DETAIL_QUAD_COUNT = 0x000000f0, 19127 SC_P2_DETAIL_QUAD_COUNT = 0x000000f1, 19128 SC_P3_DETAIL_QUAD_COUNT = 0x000000f2, 19129 SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3, 19130 SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4, 19131 SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5, 19132 SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6, 19133 SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000f7, 19134 SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000f8, 19135 SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000f9, 19136 SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fa, 19137 SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000fb, 19138 SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000000fc, 19139 SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000000fd, 19140 SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000000fe, 19141 SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000000ff, 19142 SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000100, 19143 SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000101, 19144 SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000102, 19145 SC_EARLYZ_QUAD_COUNT = 0x00000103, 19146 SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104, 19147 SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105, 19148 SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106, 19149 SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107, 19150 SC_PKR_QUAD_PER_ROW_H1 = 0x00000108, 19151 SC_PKR_QUAD_PER_ROW_H2 = 0x00000109, 19152 SC_PKR_4X2_QUAD_SPLIT = 0x0000010a, 19153 SC_PKR_4X2_FILL_QUAD = 0x0000010b, 19154 SC_PKR_END_OF_VECTOR = 0x0000010c, 19155 SC_PKR_CONTROL_XFER = 0x0000010d, 19156 SC_PKR_DBHANG_FORCE_EOV = 0x0000010e, 19157 SC_REG_SCLK_BUSY = 0x0000010f, 19158 SC_GRP0_DYN_SCLK_BUSY = 0x00000110, 19159 SC_GRP1_DYN_SCLK_BUSY = 0x00000111, 19160 SC_GRP2_DYN_SCLK_BUSY = 0x00000112, 19161 SC_GRP3_DYN_SCLK_BUSY = 0x00000113, 19162 SC_GRP4_DYN_SCLK_BUSY = 0x00000114, 19163 SC_PA0_SC_DATA_FIFO_RD = 0x00000115, 19164 SC_PA0_SC_DATA_FIFO_WE = 0x00000116, 19165 SC_PA1_SC_DATA_FIFO_RD = 0x00000117, 19166 SC_PA1_SC_DATA_FIFO_WE = 0x00000118, 19167 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119, 19168 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a, 19169 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b, 19170 SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c, 19171 SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d, 19172 SC_PS_ARB_SC_BUSY = 0x0000011e, 19173 SC_PS_ARB_PA_SC_BUSY = 0x0000011f, 19174 SC_PA2_SC_DATA_FIFO_RD = 0x00000120, 19175 SC_PA2_SC_DATA_FIFO_WE = 0x00000121, 19176 SC_PA3_SC_DATA_FIFO_RD = 0x00000122, 19177 SC_PA3_SC_DATA_FIFO_WE = 0x00000123, 19178 SC_PA_SC_DEALLOC_0_0_WE = 0x00000124, 19179 SC_PA_SC_DEALLOC_0_1_WE = 0x00000125, 19180 SC_PA_SC_DEALLOC_1_0_WE = 0x00000126, 19181 SC_PA_SC_DEALLOC_1_1_WE = 0x00000127, 19182 SC_PA_SC_DEALLOC_2_0_WE = 0x00000128, 19183 SC_PA_SC_DEALLOC_2_1_WE = 0x00000129, 19184 SC_PA_SC_DEALLOC_3_0_WE = 0x0000012a, 19185 SC_PA_SC_DEALLOC_3_1_WE = 0x0000012b, 19186 SC_PA0_SC_EOP_WE = 0x0000012c, 19187 SC_PA0_SC_EOPG_WE = 0x0000012d, 19188 SC_PA0_SC_EVENT_WE = 0x0000012e, 19189 SC_PA1_SC_EOP_WE = 0x0000012f, 19190 SC_PA1_SC_EOPG_WE = 0x00000130, 19191 SC_PA1_SC_EVENT_WE = 0x00000131, 19192 SC_PA2_SC_EOP_WE = 0x00000132, 19193 SC_PA2_SC_EOPG_WE = 0x00000133, 19194 SC_PA2_SC_EVENT_WE = 0x00000134, 19195 SC_PA3_SC_EOP_WE = 0x00000135, 19196 SC_PA3_SC_EOPG_WE = 0x00000136, 19197 SC_PA3_SC_EVENT_WE = 0x00000137, 19198 SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138, 19199 SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x00000139, 19200 SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013a, 19201 SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013b, 19202 SC_PS_ARB_EVENT_SYNC_POP = 0x0000013c, 19203 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x0000013d, 19204 SC_PA0_SC_FPOV_WE = 0x0000013e, 19205 SC_PA1_SC_FPOV_WE = 0x0000013f, 19206 SC_PA2_SC_FPOV_WE = 0x00000140, 19207 SC_PA3_SC_FPOV_WE = 0x00000141, 19208 SC_PA0_SC_LPOV_WE = 0x00000142, 19209 SC_PA1_SC_LPOV_WE = 0x00000143, 19210 SC_PA2_SC_LPOV_WE = 0x00000144, 19211 SC_PA3_SC_LPOV_WE = 0x00000145, 19212 SC_SC_SPI_DEALLOC_0_0 = 0x00000146, 19213 SC_SC_SPI_DEALLOC_0_1 = 0x00000147, 19214 SC_SC_SPI_DEALLOC_0_2 = 0x00000148, 19215 SC_SC_SPI_DEALLOC_1_0 = 0x00000149, 19216 SC_SC_SPI_DEALLOC_1_1 = 0x0000014a, 19217 SC_SC_SPI_DEALLOC_1_2 = 0x0000014b, 19218 SC_SC_SPI_DEALLOC_2_0 = 0x0000014c, 19219 SC_SC_SPI_DEALLOC_2_1 = 0x0000014d, 19220 SC_SC_SPI_DEALLOC_2_2 = 0x0000014e, 19221 SC_SC_SPI_DEALLOC_3_0 = 0x0000014f, 19222 SC_SC_SPI_DEALLOC_3_1 = 0x00000150, 19223 SC_SC_SPI_DEALLOC_3_2 = 0x00000151, 19224 SC_SC_SPI_FPOV_0 = 0x00000152, 19225 SC_SC_SPI_FPOV_1 = 0x00000153, 19226 SC_SC_SPI_FPOV_2 = 0x00000154, 19227 SC_SC_SPI_FPOV_3 = 0x00000155, 19228 SC_SC_SPI_EVENT = 0x00000156, 19229 SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157, 19230 SC_PS_TS_EVENT_FIFO_POP = 0x00000158, 19231 SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159, 19232 SC_PS_CTX_DONE_FIFO_POP = 0x0000015a, 19233 SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015b, 19234 SC_EOP_SYNC_WINDOW = 0x0000015c, 19235 SC_PA0_SC_NULL_WE = 0x0000015d, 19236 SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e, 19237 SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x0000015f, 19238 SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160, 19239 SC_PA0_SC_DEALLOC_0_RD = 0x00000161, 19240 SC_PA0_SC_DEALLOC_1_RD = 0x00000162, 19241 SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000163, 19242 SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000164, 19243 SC_PA1_SC_DEALLOC_0_RD = 0x00000165, 19244 SC_PA1_SC_DEALLOC_1_RD = 0x00000166, 19245 SC_PA1_SC_NULL_WE = 0x00000167, 19246 SC_PA1_SC_NULL_DEALLOC_WE = 0x00000168, 19247 SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x00000169, 19248 SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016a, 19249 SC_PA2_SC_DEALLOC_0_RD = 0x0000016b, 19250 SC_PA2_SC_DEALLOC_1_RD = 0x0000016c, 19251 SC_PA2_SC_NULL_WE = 0x0000016d, 19252 SC_PA2_SC_NULL_DEALLOC_WE = 0x0000016e, 19253 SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x0000016f, 19254 SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000170, 19255 SC_PA3_SC_DEALLOC_0_RD = 0x00000171, 19256 SC_PA3_SC_DEALLOC_1_RD = 0x00000172, 19257 SC_PA3_SC_NULL_WE = 0x00000173, 19258 SC_PA3_SC_NULL_DEALLOC_WE = 0x00000174, 19259 SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175, 19260 SC_PS_PA0_SC_FIFO_FULL = 0x00000176, 19261 SC_RESERVED_0 = 0x00000177, 19262 SC_PS_PA1_SC_FIFO_EMPTY = 0x00000178, 19263 SC_PS_PA1_SC_FIFO_FULL = 0x00000179, 19264 SC_RESERVED_1 = 0x0000017a, 19265 SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017b, 19266 SC_PS_PA2_SC_FIFO_FULL = 0x0000017c, 19267 SC_RESERVED_2 = 0x0000017d, 19268 SC_PS_PA3_SC_FIFO_EMPTY = 0x0000017e, 19269 SC_PS_PA3_SC_FIFO_FULL = 0x0000017f, 19270 SC_RESERVED_3 = 0x00000180, 19271 SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000181, 19272 SC_BUSY_CNT_NOT_ZERO = 0x00000182, 19273 SC_BM_BUSY = 0x00000183, 19274 SC_BACKEND_BUSY = 0x00000184, 19275 SC_SCF_SCB_INTERFACE_BUSY = 0x00000185, 19276 SC_SCB_BUSY = 0x00000186, 19277 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187, 19278 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188, 19279 SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189, 19280 SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a, 19281 SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b, 19282 SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c, 19283 SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d, 19284 SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e, 19285 SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f, 19286 SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190, 19287 SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191, 19288 SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192, 19289 SC_PBB_BUSY = 0x00000193, 19290 SC_PBB_BUSY_AND_NO_SENDS = 0x00000194, 19291 SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195, 19292 SC_PBB_NUM_BINS = 0x00000196, 19293 SC_PBB_END_OF_BIN = 0x00000197, 19294 SC_PBB_END_OF_BATCH = 0x00000198, 19295 SC_PBB_PRIMBIN_PROCESSED = 0x00000199, 19296 SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a, 19297 SC_PBB_NONBINNED_PRIM = 0x0000019b, 19298 SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c, 19299 SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d, 19300 SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e, 19301 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f, 19302 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0, 19303 SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1, 19304 SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2, 19305 SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3, 19306 SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4, 19307 SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5, 19308 SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6, 19309 SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001a7, 19310 SC_POPS_FORCE_EOV = 0x000001a8, 19311 SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 0x000001a9, 19312 SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 0x000001aa, 19313 SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 0x000001ab, 19314 SC_FULL_FULL_QUAD = 0x000001ac, 19315 SC_FULL_HALF_QUAD = 0x000001ad, 19316 SC_FULL_QTR_QUAD = 0x000001ae, 19317 SC_HALF_FULL_QUAD = 0x000001af, 19318 SC_HALF_HALF_QUAD = 0x000001b0, 19319 SC_HALF_QTR_QUAD = 0x000001b1, 19320 SC_QTR_FULL_QUAD = 0x000001b2, 19321 SC_QTR_HALF_QUAD = 0x000001b3, 19322 SC_QTR_QTR_QUAD = 0x000001b4, 19323 SC_GRP5_DYN_SCLK_BUSY = 0x000001b5, 19324 SC_GRP6_DYN_SCLK_BUSY = 0x000001b6, 19325 SC_GRP7_DYN_SCLK_BUSY = 0x000001b7, 19326 SC_GRP8_DYN_SCLK_BUSY = 0x000001b8, 19327 SC_GRP9_DYN_SCLK_BUSY = 0x000001b9, 19328 SC_PS_TO_BE_SCLK_GATE_STALL = 0x000001ba, 19329 SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 0x000001bb, 19330 SC_PK_BUSY = 0x000001bc, 19331 SC_PK_MAX_DEALLOC_FORCE_EOV = 0x000001bd, 19332 SC_PK_DEALLOC_WAVE_BREAK = 0x000001be, 19333 SC_SPI_SEND = 0x000001bf, 19334 SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c0, 19335 SC_SPI_CREDIT_AT_MAX = 0x000001c1, 19336 SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c2, 19337 SC_BCI_SEND = 0x000001c3, 19338 SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c4, 19339 SC_BCI_CREDIT_AT_MAX = 0x000001c5, 19340 SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c6, 19341 SC_SPIBC_FULL_FREEZE = 0x000001c7, 19342 SC_PW_BM_PASS_EMPTY_PRIM = 0x000001c8, 19343 SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9, 19344 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca, 19345 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb, 19346 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc, 19347 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd, 19348 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce, 19349 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf, 19350 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0, 19351 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1, 19352 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2, 19353 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3, 19354 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4, 19355 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5, 19356 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6, 19357 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7, 19358 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8, 19359 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9, 19360 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da, 19361 SC_DB0_TILE_INTERFACE_BUSY = 0x000001db, 19362 SC_DB0_TILE_INTERFACE_SEND = 0x000001dc, 19363 SC_DB0_TILE_INTERFACE_SEND_EVENT = 0x000001dd, 19364 SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001de, 19365 SC_DB0_TILE_INTERFACE_SEND_SOP = 0x000001df, 19366 SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0, 19367 SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e1, 19368 SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2, 19369 SC_DB1_TILE_INTERFACE_BUSY = 0x000001e3, 19370 SC_DB1_TILE_INTERFACE_SEND = 0x000001e4, 19371 SC_DB1_TILE_INTERFACE_SEND_EVENT = 0x000001e5, 19372 SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001e6, 19373 SC_DB1_TILE_INTERFACE_SEND_SOP = 0x000001e7, 19374 SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e8, 19375 SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e9, 19376 SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001ea, 19377 SC_BACKEND_PRIM_FIFO_FULL = 0x000001eb, 19378 SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 0x000001ec, 19379 SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 0x000001ed, 19380 SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 0x000001ee, 19381 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 0x000001ef, 19382 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 0x000001f0, 19383 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 0x000001f1, 19384 SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 0x000001f2, 19385 SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 0x000001f3, 19386 SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 0x000001f4, 19387 } SC_PERFCNT_SEL; 19388 19389 /* 19390 * SePairXsel enum 19391 */ 19392 19393 typedef enum SePairXsel { 19394 RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, 19395 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, 19396 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, 19397 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, 19398 } SePairXsel; 19399 19400 /* 19401 * SePairYsel enum 19402 */ 19403 19404 typedef enum SePairYsel { 19405 RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, 19406 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, 19407 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, 19408 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, 19409 } SePairYsel; 19410 19411 /* 19412 * SePairMap enum 19413 */ 19414 19415 typedef enum SePairMap { 19416 RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, 19417 RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, 19418 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, 19419 RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, 19420 } SePairMap; 19421 19422 /* 19423 * SeXsel enum 19424 */ 19425 19426 typedef enum SeXsel { 19427 RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, 19428 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, 19429 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, 19430 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, 19431 } SeXsel; 19432 19433 /* 19434 * SeYsel enum 19435 */ 19436 19437 typedef enum SeYsel { 19438 RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, 19439 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, 19440 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, 19441 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, 19442 } SeYsel; 19443 19444 /* 19445 * SeMap enum 19446 */ 19447 19448 typedef enum SeMap { 19449 RASTER_CONFIG_SE_MAP_0 = 0x00000000, 19450 RASTER_CONFIG_SE_MAP_1 = 0x00000001, 19451 RASTER_CONFIG_SE_MAP_2 = 0x00000002, 19452 RASTER_CONFIG_SE_MAP_3 = 0x00000003, 19453 } SeMap; 19454 19455 /* 19456 * ScXsel enum 19457 */ 19458 19459 typedef enum ScXsel { 19460 RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, 19461 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, 19462 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, 19463 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, 19464 } ScXsel; 19465 19466 /* 19467 * ScYsel enum 19468 */ 19469 19470 typedef enum ScYsel { 19471 RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, 19472 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, 19473 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, 19474 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, 19475 } ScYsel; 19476 19477 /* 19478 * ScMap enum 19479 */ 19480 19481 typedef enum ScMap { 19482 RASTER_CONFIG_SC_MAP_0 = 0x00000000, 19483 RASTER_CONFIG_SC_MAP_1 = 0x00000001, 19484 RASTER_CONFIG_SC_MAP_2 = 0x00000002, 19485 RASTER_CONFIG_SC_MAP_3 = 0x00000003, 19486 } ScMap; 19487 19488 /* 19489 * PkrXsel2 enum 19490 */ 19491 19492 typedef enum PkrXsel2 { 19493 RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, 19494 RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, 19495 RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, 19496 RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, 19497 } PkrXsel2; 19498 19499 /* 19500 * PkrXsel enum 19501 */ 19502 19503 typedef enum PkrXsel { 19504 RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, 19505 RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, 19506 RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, 19507 RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, 19508 } PkrXsel; 19509 19510 /* 19511 * PkrYsel enum 19512 */ 19513 19514 typedef enum PkrYsel { 19515 RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, 19516 RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, 19517 RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, 19518 RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, 19519 } PkrYsel; 19520 19521 /* 19522 * PkrMap enum 19523 */ 19524 19525 typedef enum PkrMap { 19526 RASTER_CONFIG_PKR_MAP_0 = 0x00000000, 19527 RASTER_CONFIG_PKR_MAP_1 = 0x00000001, 19528 RASTER_CONFIG_PKR_MAP_2 = 0x00000002, 19529 RASTER_CONFIG_PKR_MAP_3 = 0x00000003, 19530 } PkrMap; 19531 19532 /* 19533 * RbXsel enum 19534 */ 19535 19536 typedef enum RbXsel { 19537 RASTER_CONFIG_RB_XSEL_0 = 0x00000000, 19538 RASTER_CONFIG_RB_XSEL_1 = 0x00000001, 19539 } RbXsel; 19540 19541 /* 19542 * RbYsel enum 19543 */ 19544 19545 typedef enum RbYsel { 19546 RASTER_CONFIG_RB_YSEL_0 = 0x00000000, 19547 RASTER_CONFIG_RB_YSEL_1 = 0x00000001, 19548 } RbYsel; 19549 19550 /* 19551 * RbXsel2 enum 19552 */ 19553 19554 typedef enum RbXsel2 { 19555 RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, 19556 RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, 19557 RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, 19558 RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, 19559 } RbXsel2; 19560 19561 /* 19562 * RbMap enum 19563 */ 19564 19565 typedef enum RbMap { 19566 RASTER_CONFIG_RB_MAP_0 = 0x00000000, 19567 RASTER_CONFIG_RB_MAP_1 = 0x00000001, 19568 RASTER_CONFIG_RB_MAP_2 = 0x00000002, 19569 RASTER_CONFIG_RB_MAP_3 = 0x00000003, 19570 } RbMap; 19571 19572 /* 19573 * BinningMode enum 19574 */ 19575 19576 typedef enum BinningMode { 19577 BINNING_ALLOWED = 0x00000000, 19578 FORCE_BINNING_ON = 0x00000001, 19579 DISABLE_BINNING_USE_NEW_SC = 0x00000002, 19580 DISABLE_BINNING_USE_LEGACY_SC = 0x00000003, 19581 } BinningMode; 19582 19583 /* 19584 * BinSizeExtend enum 19585 */ 19586 19587 typedef enum BinSizeExtend { 19588 BIN_SIZE_32_PIXELS = 0x00000000, 19589 BIN_SIZE_64_PIXELS = 0x00000001, 19590 BIN_SIZE_128_PIXELS = 0x00000002, 19591 BIN_SIZE_256_PIXELS = 0x00000003, 19592 BIN_SIZE_512_PIXELS = 0x00000004, 19593 } BinSizeExtend; 19594 19595 /* 19596 * BinMapMode enum 19597 */ 19598 19599 typedef enum BinMapMode { 19600 BIN_MAP_MODE_NONE = 0x00000000, 19601 BIN_MAP_MODE_RTA_INDEX = 0x00000001, 19602 BIN_MAP_MODE_POPS = 0x00000002, 19603 } BinMapMode; 19604 19605 /* 19606 * BinEventCntl enum 19607 */ 19608 19609 typedef enum BinEventCntl { 19610 BINNER_BREAK_BATCH = 0x00000000, 19611 BINNER_PIPELINE = 0x00000001, 19612 BINNER_DROP = 0x00000002, 19613 BINNER_DROP_ASSERT = 0x00000003, 19614 } BinEventCntl; 19615 19616 /* 19617 * CovToShaderSel enum 19618 */ 19619 19620 typedef enum CovToShaderSel { 19621 INPUT_COVERAGE = 0x00000000, 19622 INPUT_INNER_COVERAGE = 0x00000001, 19623 INPUT_DEPTH_COVERAGE = 0x00000002, 19624 RAW = 0x00000003, 19625 } CovToShaderSel; 19626 19627 /* 19628 * ScUncertaintyRegionMode enum 19629 */ 19630 19631 typedef enum ScUncertaintyRegionMode { 19632 SC_HALF_LSB = 0x00000000, 19633 SC_LSB_ONE_SIDED = 0x00000001, 19634 SC_LSB_TWO_SIDED = 0x00000002, 19635 } ScUncertaintyRegionMode; 19636 19637 /******************************************************* 19638 * RMI Enums 19639 *******************************************************/ 19640 19641 /* 19642 * RMIPerfSel enum 19643 */ 19644 19645 typedef enum RMIPerfSel { 19646 RMI_PERF_SEL_NONE = 0x00000000, 19647 RMI_PERF_SEL_BUSY = 0x00000001, 19648 RMI_PERF_SEL_REG_CLK_VLD = 0x00000002, 19649 RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003, 19650 RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004, 19651 RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005, 19652 RMI_PERF_SEL_PERF_WINDOW = 0x00000006, 19653 RMI_PERF_SEL_EVENT_SEND = 0x00000007, 19654 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008, 19655 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009, 19656 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a, 19657 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b, 19658 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c, 19659 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d, 19660 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e, 19661 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f, 19662 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010, 19663 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011, 19664 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012, 19665 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013, 19666 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014, 19667 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015, 19668 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016, 19669 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017, 19670 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018, 19671 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019, 19672 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a, 19673 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b, 19674 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c, 19675 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d, 19676 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e, 19677 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f, 19678 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020, 19679 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021, 19680 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022, 19681 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023, 19682 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024, 19683 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025, 19684 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026, 19685 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027, 19686 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028, 19687 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029, 19688 RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x0000002a, 19689 RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 0x0000002b, 19690 RMI_PERF_SEL_UTCL1_TRANSLATION_HIT = 0x0000002c, 19691 RMI_PERF_SEL_UTCL1_REQUEST = 0x0000002d, 19692 RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x0000002e, 19693 RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x0000002f, 19694 RMI_PERF_SEL_UTCL1_LFIFO_FULL = 0x00000030, 19695 RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000031, 19696 RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000032, 19697 RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x00000033, 19698 RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 0x00000034, 19699 RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000035, 19700 RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000036, 19701 RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 0x00000037, 19702 RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x00000038, 19703 RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x00000039, 19704 RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x0000003a, 19705 RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000003b, 19706 RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000003c, 19707 RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000003d, 19708 RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x0000003e, 19709 RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x0000003f, 19710 RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 0x00000040, 19711 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000041, 19712 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000042, 19713 RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000043, 19714 RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000044, 19715 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000045, 19716 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000046, 19717 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000047, 19718 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x00000048, 19719 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x00000049, 19720 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x0000004a, 19721 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000004b, 19722 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000004c, 19723 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000004d, 19724 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x0000004e, 19725 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x0000004f, 19726 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x00000050, 19727 RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000051, 19728 RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000052, 19729 RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 0x00000053, 19730 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000054, 19731 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000055, 19732 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000056, 19733 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000057, 19734 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x00000058, 19735 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x00000059, 19736 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x0000005a, 19737 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000005b, 19738 RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000005c, 19739 RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000005d, 19740 RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x0000005e, 19741 RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x0000005f, 19742 RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x00000060, 19743 RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000061, 19744 RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000062, 19745 RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000063, 19746 RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000064, 19747 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000065, 19748 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000066, 19749 RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000067, 19750 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000068, 19751 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x00000069, 19752 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x0000006a, 19753 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000006b, 19754 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000006c, 19755 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000006d, 19756 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x0000006e, 19757 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x0000006f, 19758 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x00000070, 19759 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000071, 19760 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000072, 19761 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000073, 19762 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000074, 19763 RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 0x00000075, 19764 RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 0x00000076, 19765 RMI_PERF_SEL_RB_RMI_WR_IDLE = 0x00000077, 19766 RMI_PERF_SEL_RB_RMI_WR_STARVE = 0x00000078, 19767 RMI_PERF_SEL_RB_RMI_WR_STALL = 0x00000079, 19768 RMI_PERF_SEL_RB_RMI_WR_BUSY = 0x0000007a, 19769 RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 0x0000007b, 19770 RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 0x0000007c, 19771 RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 0x0000007d, 19772 RMI_PERF_SEL_RB_RMI_RD_IDLE = 0x0000007e, 19773 RMI_PERF_SEL_RB_RMI_RD_STARVE = 0x0000007f, 19774 RMI_PERF_SEL_RB_RMI_RD_STALL = 0x00000080, 19775 RMI_PERF_SEL_RB_RMI_RD_BUSY = 0x00000081, 19776 RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 0x00000082, 19777 RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 0x00000083, 19778 RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 0x00000084, 19779 RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000085, 19780 RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000086, 19781 RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000087, 19782 RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x00000088, 19783 RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x00000089, 19784 RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x0000008a, 19785 RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000008b, 19786 RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000008c, 19787 RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000008d, 19788 RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x0000008e, 19789 RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000008f, 19790 RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x00000090, 19791 RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000091, 19792 RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000092, 19793 RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000093, 19794 RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000094, 19795 RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000095, 19796 RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000096, 19797 RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000097, 19798 RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x00000098, 19799 RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x00000099, 19800 RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 0x0000009a, 19801 RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 0x0000009b, 19802 RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 0x0000009c, 19803 RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 0x0000009d, 19804 RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 0x0000009e, 19805 RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x0000009f, 19806 RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x000000a0, 19807 RMI_PERF_SEL_UTCL1_BUSY = 0x000000a1, 19808 RMI_PERF_SEL_RMI_UTC_REQ = 0x000000a2, 19809 RMI_PERF_SEL_RMI_UTC_BUSY = 0x000000a3, 19810 RMI_PERF_SEL_UTCL1_UTCL2_REQ = 0x000000a4, 19811 RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2 = 0x000000a5, 19812 RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 0x000000a6, 19813 RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 0x000000a7, 19814 RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 0x000000a8, 19815 RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS = 0x000000a9, 19816 RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x000000aa, 19817 RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 0x000000ab, 19818 RMI_PERF_SEL_LAT_FIFO_NUM_USED = 0x000000ac, 19819 RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 0x000000ad, 19820 RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 0x000000ae, 19821 RMI_PERF_SEL_XNACK_FIFO_FULL = 0x000000af, 19822 RMI_PERF_SEL_XNACK_FIFO_BUSY = 0x000000b0, 19823 RMI_PERF_SEL_LAT_FIFO_FULL = 0x000000b1, 19824 RMI_PERF_SEL_SKID_FIFO_DEPTH = 0x000000b2, 19825 RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x000000b3, 19826 RMI_PERF_SEL_PRT_FIFO_NUM_USED = 0x000000b4, 19827 RMI_PERF_SEL_PRT_FIFO_REQ = 0x000000b5, 19828 RMI_PERF_SEL_PRT_FIFO_BUSY = 0x000000b6, 19829 RMI_PERF_SEL_TCIW_REQ = 0x000000b7, 19830 RMI_PERF_SEL_TCIW_BUSY = 0x000000b8, 19831 RMI_PERF_SEL_SKID_FIFO_REQ = 0x000000b9, 19832 RMI_PERF_SEL_SKID_FIFO_BUSY = 0x000000ba, 19833 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 0x000000bb, 19834 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 0x000000bc, 19835 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 0x000000bd, 19836 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 0x000000be, 19837 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 0x000000bf, 19838 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 0x000000c0, 19839 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 0x000000c1, 19840 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 0x000000c2, 19841 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000c3, 19842 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000c4, 19843 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000c5, 19844 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000c6, 19845 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000c7, 19846 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000c8, 19847 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000c9, 19848 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000ca, 19849 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000cb, 19850 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000cc, 19851 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000cd, 19852 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000ce, 19853 RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 0x000000cf, 19854 RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 0x000000d0, 19855 RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 0x000000d1, 19856 RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 0x000000d2, 19857 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 0x000000d3, 19858 RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC = 0x000000d4, 19859 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 0x000000d5, 19860 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 0x000000d6, 19861 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 0x000000d7, 19862 RMI_PERF_SEL_UTC_POP_RTS_RTR = 0x000000d8, 19863 RMI_PERF_SEL_UTC_POP_RTSB_RTR = 0x000000d9, 19864 RMI_PERF_SEL_UTC_POP_RTS_RTRB = 0x000000da, 19865 RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 0x000000db, 19866 RMI_PERF_SEL_POP_XNACK_RTS_RTR = 0x000000dc, 19867 RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 0x000000dd, 19868 RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 0x000000de, 19869 RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 0x000000df, 19870 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 0x000000e0, 19871 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 0x000000e1, 19872 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 0x000000e2, 19873 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 0x000000e3, 19874 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000e4, 19875 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000e5, 19876 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000e6, 19877 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000e7, 19878 RMI_PERF_SEL_SKID_FIFO_IN_RTS = 0x000000e8, 19879 RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 0x000000e9, 19880 RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 0x000000ea, 19881 RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 0x000000eb, 19882 RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 0x000000ec, 19883 RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000ed, 19884 RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 0x000000ee, 19885 RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 0x000000ef, 19886 RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 0x000000f0, 19887 RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 0x000000f1, 19888 RMI_PERF_SEL_REORDER_FIFO_REQ = 0x000000f2, 19889 RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x000000f3, 19890 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x000000f4, 19891 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x000000f5, 19892 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x000000f6, 19893 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x000000f7, 19894 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x000000f8, 19895 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x000000f9, 19896 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x000000fa, 19897 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x000000fb, 19898 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x000000fc, 19899 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 0x000000fd, 19900 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 0x000000fe, 19901 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 0x000000ff, 19902 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 0x00000100, 19903 } RMIPerfSel; 19904 19905 /******************************************************* 19906 * PMM Enums 19907 *******************************************************/ 19908 19909 /* 19910 * GCRPerfSel enum 19911 */ 19912 19913 typedef enum GCRPerfSel { 19914 GCR_PERF_SEL_NONE = 0x00000000, 19915 GCR_PERF_SEL_SDMA0_ALL_REQ = 0x00000001, 19916 GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 0x00000002, 19917 GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 0x00000003, 19918 GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 0x00000004, 19919 GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 0x00000005, 19920 GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 0x00000006, 19921 GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 0x00000007, 19922 GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 0x00000008, 19923 GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 0x00000009, 19924 GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 0x0000000a, 19925 GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 0x0000000b, 19926 GCR_PERF_SEL_SDMA0_METADATA_REQ = 0x0000000c, 19927 GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 0x0000000d, 19928 GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 0x0000000e, 19929 GCR_PERF_SEL_SDMA0_TCP_REQ = 0x0000000f, 19930 GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 0x00000010, 19931 GCR_PERF_SEL_SDMA1_ALL_REQ = 0x00000011, 19932 GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 0x00000012, 19933 GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 0x00000013, 19934 GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 0x00000014, 19935 GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 0x00000015, 19936 GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 0x00000016, 19937 GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 0x00000017, 19938 GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 0x00000018, 19939 GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 0x00000019, 19940 GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 0x0000001a, 19941 GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 0x0000001b, 19942 GCR_PERF_SEL_SDMA1_METADATA_REQ = 0x0000001c, 19943 GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 0x0000001d, 19944 GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 0x0000001e, 19945 GCR_PERF_SEL_SDMA1_TCP_REQ = 0x0000001f, 19946 GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 0x00000020, 19947 GCR_PERF_SEL_CPG_ALL_REQ = 0x00000021, 19948 GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 0x00000022, 19949 GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 0x00000023, 19950 GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 0x00000024, 19951 GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 0x00000025, 19952 GCR_PERF_SEL_CPG_GL2_ALL_REQ = 0x00000026, 19953 GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 0x00000027, 19954 GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 0x00000028, 19955 GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 0x00000029, 19956 GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 0x0000002a, 19957 GCR_PERF_SEL_CPG_GL1_ALL_REQ = 0x0000002b, 19958 GCR_PERF_SEL_CPG_METADATA_REQ = 0x0000002c, 19959 GCR_PERF_SEL_CPG_SQC_DATA_REQ = 0x0000002d, 19960 GCR_PERF_SEL_CPG_SQC_INST_REQ = 0x0000002e, 19961 GCR_PERF_SEL_CPG_TCP_REQ = 0x0000002f, 19962 GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 0x00000030, 19963 GCR_PERF_SEL_CPC_ALL_REQ = 0x00000031, 19964 GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 0x00000032, 19965 GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 0x00000033, 19966 GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 0x00000034, 19967 GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 0x00000035, 19968 GCR_PERF_SEL_CPC_GL2_ALL_REQ = 0x00000036, 19969 GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 0x00000037, 19970 GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 0x00000038, 19971 GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 0x00000039, 19972 GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 0x0000003a, 19973 GCR_PERF_SEL_CPC_GL1_ALL_REQ = 0x0000003b, 19974 GCR_PERF_SEL_CPC_METADATA_REQ = 0x0000003c, 19975 GCR_PERF_SEL_CPC_SQC_DATA_REQ = 0x0000003d, 19976 GCR_PERF_SEL_CPC_SQC_INST_REQ = 0x0000003e, 19977 GCR_PERF_SEL_CPC_TCP_REQ = 0x0000003f, 19978 GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 0x00000040, 19979 GCR_PERF_SEL_CPF_ALL_REQ = 0x00000041, 19980 GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 0x00000042, 19981 GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 0x00000043, 19982 GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 0x00000044, 19983 GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 0x00000045, 19984 GCR_PERF_SEL_CPF_GL2_ALL_REQ = 0x00000046, 19985 GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 0x00000047, 19986 GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 0x00000048, 19987 GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 0x00000049, 19988 GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 0x0000004a, 19989 GCR_PERF_SEL_CPF_GL1_ALL_REQ = 0x0000004b, 19990 GCR_PERF_SEL_CPF_METADATA_REQ = 0x0000004c, 19991 GCR_PERF_SEL_CPF_SQC_DATA_REQ = 0x0000004d, 19992 GCR_PERF_SEL_CPF_SQC_INST_REQ = 0x0000004e, 19993 GCR_PERF_SEL_CPF_TCP_REQ = 0x0000004f, 19994 GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 0x00000050, 19995 GCR_PERF_SEL_VIRT_REQ = 0x00000051, 19996 GCR_PERF_SEL_PHY_REQ = 0x00000052, 19997 GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 0x00000053, 19998 GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 0x00000054, 19999 GCR_PERF_SEL_ALL_REQ = 0x00000055, 20000 GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056, 20001 GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057, 20002 GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058, 20003 GCR_PERF_SEL_UTCL2_REQ = 0x00000059, 20004 GCR_PERF_SEL_UTCL2_RET = 0x0000005a, 20005 GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 0x0000005b, 20006 GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 0x0000005c, 20007 GCR_PERF_SEL_UTCL2_FILTERED_RET = 0x0000005d, 20008 } GCRPerfSel; 20009 20010 /******************************************************* 20011 * UTCL1 Enums 20012 *******************************************************/ 20013 20014 /* 20015 * UTCL1PerfSel enum 20016 */ 20017 20018 typedef enum UTCL1PerfSel { 20019 UTCL1_PERF_SEL_NONE = 0x00000000, 20020 UTCL1_PERF_SEL_REQS = 0x00000001, 20021 UTCL1_PERF_SEL_HITS = 0x00000002, 20022 UTCL1_PERF_SEL_MISSES = 0x00000003, 20023 UTCL1_PERF_SEL_BYPASS_REQS = 0x00000004, 20024 UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 0x00000005, 20025 UTCL1_PERF_SEL_NUM_SMALLK_PAGES = 0x00000006, 20026 UTCL1_PERF_SEL_NUM_BIGK_PAGES = 0x00000007, 20027 UTCL1_PERF_SEL_TOTAL_UTCL2_REQS = 0x00000008, 20028 UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM = 0x00000009, 20029 UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS = 0x0000000a, 20030 UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL = 0x0000000b, 20031 UTCL1_PERF_SEL_STALL_MH_CAM_FULL = 0x0000000c, 20032 UTCL1_PERF_SEL_NONRANGE_INV_REQS = 0x0000000d, 20033 UTCL1_PERF_SEL_RANGE_INV_REQS = 0x0000000e, 20034 } UTCL1PerfSel; 20035 20036 /******************************************************* 20037 * SDMA Enums 20038 *******************************************************/ 20039 20040 /* 20041 * SDMA_PERF_SEL enum 20042 */ 20043 20044 typedef enum SDMA_PERF_SEL { 20045 SDMA_PERF_SEL_CYCLE = 0x00000000, 20046 SDMA_PERF_SEL_IDLE = 0x00000001, 20047 SDMA_PERF_SEL_REG_IDLE = 0x00000002, 20048 SDMA_PERF_SEL_RB_EMPTY = 0x00000003, 20049 SDMA_PERF_SEL_RB_FULL = 0x00000004, 20050 SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, 20051 SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, 20052 SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, 20053 SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, 20054 SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, 20055 SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, 20056 SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, 20057 SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, 20058 SDMA_PERF_SEL_EX_IDLE = 0x0000000d, 20059 SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, 20060 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, 20061 SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, 20062 SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, 20063 SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, 20064 SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, 20065 SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, 20066 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, 20067 SDMA_PERF_SEL_SEM_IDLE = 0x00000018, 20068 SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, 20069 SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, 20070 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, 20071 SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, 20072 SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, 20073 SDMA_PERF_SEL_INT_IDLE = 0x0000001e, 20074 SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, 20075 SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, 20076 SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, 20077 SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, 20078 SDMA_PERF_SEL_NUM_PACKET = 0x00000023, 20079 SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, 20080 SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, 20081 SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, 20082 SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, 20083 SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, 20084 SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, 20085 SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, 20086 SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, 20087 SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, 20088 SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, 20089 SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, 20090 SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, 20091 SDMA_PERF_SEL_GFX_SELECT = 0x00000035, 20092 SDMA_PERF_SEL_RLC0_SELECT = 0x00000036, 20093 SDMA_PERF_SEL_RLC1_SELECT = 0x00000037, 20094 SDMA_PERF_SEL_PAGE_SELECT = 0x00000038, 20095 SDMA_PERF_SEL_CTX_CHANGE = 0x00000039, 20096 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, 20097 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, 20098 SDMA_PERF_SEL_DOORBELL = 0x0000003c, 20099 SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, 20100 SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, 20101 SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, 20102 SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, 20103 SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041, 20104 SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042, 20105 SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043, 20106 SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044, 20107 SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045, 20108 SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046, 20109 SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047, 20110 SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048, 20111 SDMA_PERF_SEL_UTCL2_FREE = 0x00000049, 20112 SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a, 20113 SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b, 20114 SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c, 20115 SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d, 20116 SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e, 20117 SDMA_PERF_SEL_GPUVM_INVREQ_HIGH = 0x0000004f, 20118 SDMA_PERF_SEL_GPUVM_INVREQ_LOW = 0x00000050, 20119 SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051, 20120 SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052, 20121 SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053, 20122 SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054, 20123 SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055, 20124 SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056, 20125 SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057, 20126 SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058, 20127 SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059, 20128 SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a, 20129 SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b, 20130 SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c, 20131 SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d, 20132 SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e, 20133 SDMA_PERF_SEL_TLBI_SEND = 0x0000005f, 20134 SDMA_PERF_SEL_TLBI_RTN = 0x00000060, 20135 SDMA_PERF_SEL_GCR_SEND = 0x00000061, 20136 SDMA_PERF_SEL_GCR_RTN = 0x00000062, 20137 SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063, 20138 SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064, 20139 } SDMA_PERF_SEL; 20140 20141 /******************************************************* 20142 * ADDRLIB Enums 20143 *******************************************************/ 20144 20145 /* 20146 * NUM_PIPES_BC_ENUM enum 20147 */ 20148 20149 typedef enum NUM_PIPES_BC_ENUM { 20150 ADDR_NUM_PIPES_BC_P8 = 0x00000000, 20151 ADDR_NUM_PIPES_BC_P16 = 0x00000001, 20152 } NUM_PIPES_BC_ENUM; 20153 20154 /* 20155 * NUM_BANKS_BC_ENUM enum 20156 */ 20157 20158 typedef enum NUM_BANKS_BC_ENUM { 20159 ADDR_NUM_BANKS_BC_BANKS_1 = 0x00000000, 20160 ADDR_NUM_BANKS_BC_BANKS_2 = 0x00000001, 20161 ADDR_NUM_BANKS_BC_BANKS_4 = 0x00000002, 20162 ADDR_NUM_BANKS_BC_BANKS_8 = 0x00000003, 20163 ADDR_NUM_BANKS_BC_BANKS_16 = 0x00000004, 20164 } NUM_BANKS_BC_ENUM; 20165 20166 /* 20167 * SWIZZLE_TYPE_ENUM enum 20168 */ 20169 20170 typedef enum SWIZZLE_TYPE_ENUM { 20171 SW_Z = 0x00000000, 20172 SW_S = 0x00000001, 20173 SW_D = 0x00000002, 20174 SW_R = 0x00000003, 20175 SW_L = 0x00000004, 20176 } SWIZZLE_TYPE_ENUM; 20177 20178 /* 20179 * TC_MICRO_TILE_MODE enum 20180 */ 20181 20182 typedef enum TC_MICRO_TILE_MODE { 20183 MICRO_TILE_MODE_LINEAR = 0x00000000, 20184 MICRO_TILE_MODE_RENDER_TARGET = 0x00000001, 20185 MICRO_TILE_MODE_STD_2D = 0x00000002, 20186 MICRO_TILE_MODE_STD_3D = 0x00000003, 20187 MICRO_TILE_MODE_DISPLAY_2D = 0x00000004, 20188 MICRO_TILE_MODE_DISPLAY_3D = 0x00000005, 20189 MICRO_TILE_MODE_Z = 0x00000006, 20190 } TC_MICRO_TILE_MODE; 20191 20192 /* 20193 * SWIZZLE_MODE_ENUM enum 20194 */ 20195 20196 typedef enum SWIZZLE_MODE_ENUM { 20197 SW_LINEAR = 0x00000000, 20198 SW_256B_S = 0x00000001, 20199 SW_256B_D = 0x00000002, 20200 SW_256B_R = 0x00000003, 20201 SW_4KB_Z = 0x00000004, 20202 SW_4KB_S = 0x00000005, 20203 SW_4KB_D = 0x00000006, 20204 SW_4KB_R = 0x00000007, 20205 SW_64KB_Z = 0x00000008, 20206 SW_64KB_S = 0x00000009, 20207 SW_64KB_D = 0x0000000a, 20208 SW_64KB_R = 0x0000000b, 20209 SW_VAR_Z = 0x0000000c, 20210 SW_VAR_S = 0x0000000d, 20211 SW_VAR_D = 0x0000000e, 20212 SW_VAR_R = 0x0000000f, 20213 SW_64KB_Z_T = 0x00000010, 20214 SW_64KB_S_T = 0x00000011, 20215 SW_64KB_D_T = 0x00000012, 20216 SW_64KB_R_T = 0x00000013, 20217 SW_4KB_Z_X = 0x00000014, 20218 SW_4KB_S_X = 0x00000015, 20219 SW_4KB_D_X = 0x00000016, 20220 SW_4KB_R_X = 0x00000017, 20221 SW_64KB_Z_X = 0x00000018, 20222 SW_64KB_S_X = 0x00000019, 20223 SW_64KB_D_X = 0x0000001a, 20224 SW_64KB_R_X = 0x0000001b, 20225 SW_VAR_Z_X = 0x0000001c, 20226 SW_VAR_S_X = 0x0000001d, 20227 SW_VAR_D_X = 0x0000001e, 20228 SW_VAR_R_X = 0x0000001f, 20229 } SWIZZLE_MODE_ENUM; 20230 20231 /* 20232 * SurfaceEndian enum 20233 */ 20234 20235 typedef enum SurfaceEndian { 20236 ENDIAN_NONE = 0x00000000, 20237 ENDIAN_8IN16 = 0x00000001, 20238 ENDIAN_8IN32 = 0x00000002, 20239 ENDIAN_8IN64 = 0x00000003, 20240 } SurfaceEndian; 20241 20242 /* 20243 * ArrayMode enum 20244 */ 20245 20246 typedef enum ArrayMode { 20247 ARRAY_LINEAR_GENERAL = 0x00000000, 20248 ARRAY_LINEAR_ALIGNED = 0x00000001, 20249 ARRAY_1D_TILED_THIN1 = 0x00000002, 20250 ARRAY_1D_TILED_THICK = 0x00000003, 20251 ARRAY_2D_TILED_THIN1 = 0x00000004, 20252 ARRAY_PRT_TILED_THIN1 = 0x00000005, 20253 ARRAY_PRT_2D_TILED_THIN1 = 0x00000006, 20254 ARRAY_2D_TILED_THICK = 0x00000007, 20255 ARRAY_2D_TILED_XTHICK = 0x00000008, 20256 ARRAY_PRT_TILED_THICK = 0x00000009, 20257 ARRAY_PRT_2D_TILED_THICK = 0x0000000a, 20258 ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b, 20259 ARRAY_3D_TILED_THIN1 = 0x0000000c, 20260 ARRAY_3D_TILED_THICK = 0x0000000d, 20261 ARRAY_3D_TILED_XTHICK = 0x0000000e, 20262 ARRAY_PRT_3D_TILED_THICK = 0x0000000f, 20263 } ArrayMode; 20264 20265 /* 20266 * NumPipes enum 20267 */ 20268 20269 typedef enum NumPipes { 20270 ADDR_CONFIG_1_PIPE = 0x00000000, 20271 ADDR_CONFIG_2_PIPE = 0x00000001, 20272 ADDR_CONFIG_4_PIPE = 0x00000002, 20273 ADDR_CONFIG_8_PIPE = 0x00000003, 20274 ADDR_CONFIG_16_PIPE = 0x00000004, 20275 ADDR_CONFIG_32_PIPE = 0x00000005, 20276 ADDR_CONFIG_64_PIPE = 0x00000006, 20277 } NumPipes; 20278 20279 /* 20280 * NumBanksConfig enum 20281 */ 20282 20283 typedef enum NumBanksConfig { 20284 ADDR_CONFIG_1_BANK = 0x00000000, 20285 ADDR_CONFIG_2_BANK = 0x00000001, 20286 ADDR_CONFIG_4_BANK = 0x00000002, 20287 ADDR_CONFIG_8_BANK = 0x00000003, 20288 ADDR_CONFIG_16_BANK = 0x00000004, 20289 } NumBanksConfig; 20290 20291 /* 20292 * PipeInterleaveSize enum 20293 */ 20294 20295 typedef enum PipeInterleaveSize { 20296 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, 20297 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, 20298 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, 20299 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, 20300 } PipeInterleaveSize; 20301 20302 /* 20303 * BankInterleaveSize enum 20304 */ 20305 20306 typedef enum BankInterleaveSize { 20307 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, 20308 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, 20309 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, 20310 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, 20311 } BankInterleaveSize; 20312 20313 /* 20314 * NumShaderEngines enum 20315 */ 20316 20317 typedef enum NumShaderEngines { 20318 ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, 20319 ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, 20320 ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, 20321 ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, 20322 } NumShaderEngines; 20323 20324 /* 20325 * NumRbPerShaderEngine enum 20326 */ 20327 20328 typedef enum NumRbPerShaderEngine { 20329 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, 20330 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, 20331 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, 20332 } NumRbPerShaderEngine; 20333 20334 /* 20335 * NumGPUs enum 20336 */ 20337 20338 typedef enum NumGPUs { 20339 ADDR_CONFIG_1_GPU = 0x00000000, 20340 ADDR_CONFIG_2_GPU = 0x00000001, 20341 ADDR_CONFIG_4_GPU = 0x00000002, 20342 ADDR_CONFIG_8_GPU = 0x00000003, 20343 } NumGPUs; 20344 20345 /* 20346 * NumMaxCompressedFragments enum 20347 */ 20348 20349 typedef enum NumMaxCompressedFragments { 20350 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, 20351 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, 20352 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, 20353 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, 20354 } NumMaxCompressedFragments; 20355 20356 /* 20357 * ShaderEngineTileSize enum 20358 */ 20359 20360 typedef enum ShaderEngineTileSize { 20361 ADDR_CONFIG_SE_TILE_16 = 0x00000000, 20362 ADDR_CONFIG_SE_TILE_32 = 0x00000001, 20363 } ShaderEngineTileSize; 20364 20365 /* 20366 * MultiGPUTileSize enum 20367 */ 20368 20369 typedef enum MultiGPUTileSize { 20370 ADDR_CONFIG_GPU_TILE_16 = 0x00000000, 20371 ADDR_CONFIG_GPU_TILE_32 = 0x00000001, 20372 ADDR_CONFIG_GPU_TILE_64 = 0x00000002, 20373 ADDR_CONFIG_GPU_TILE_128 = 0x00000003, 20374 } MultiGPUTileSize; 20375 20376 /* 20377 * RowSize enum 20378 */ 20379 20380 typedef enum RowSize { 20381 ADDR_CONFIG_1KB_ROW = 0x00000000, 20382 ADDR_CONFIG_2KB_ROW = 0x00000001, 20383 ADDR_CONFIG_4KB_ROW = 0x00000002, 20384 } RowSize; 20385 20386 /* 20387 * NumLowerPipes enum 20388 */ 20389 20390 typedef enum NumLowerPipes { 20391 ADDR_CONFIG_1_LOWER_PIPES = 0x00000000, 20392 ADDR_CONFIG_2_LOWER_PIPES = 0x00000001, 20393 } NumLowerPipes; 20394 20395 /* 20396 * ColorTransform enum 20397 */ 20398 20399 typedef enum ColorTransform { 20400 DCC_CT_AUTO = 0x00000000, 20401 DCC_CT_NONE = 0x00000001, 20402 ABGR_TO_A_BG_G_RB = 0x00000002, 20403 BGRA_TO_BG_G_RB_A = 0x00000003, 20404 } ColorTransform; 20405 20406 /* 20407 * CompareRef enum 20408 */ 20409 20410 typedef enum CompareRef { 20411 REF_NEVER = 0x00000000, 20412 REF_LESS = 0x00000001, 20413 REF_EQUAL = 0x00000002, 20414 REF_LEQUAL = 0x00000003, 20415 REF_GREATER = 0x00000004, 20416 REF_NOTEQUAL = 0x00000005, 20417 REF_GEQUAL = 0x00000006, 20418 REF_ALWAYS = 0x00000007, 20419 } CompareRef; 20420 20421 /* 20422 * ReadSize enum 20423 */ 20424 20425 typedef enum ReadSize { 20426 READ_256_BITS = 0x00000000, 20427 READ_512_BITS = 0x00000001, 20428 } ReadSize; 20429 20430 /* 20431 * DepthFormat enum 20432 */ 20433 20434 typedef enum DepthFormat { 20435 DEPTH_INVALID = 0x00000000, 20436 DEPTH_16 = 0x00000001, 20437 DEPTH_X8_24 = 0x00000002, 20438 DEPTH_8_24 = 0x00000003, 20439 DEPTH_X8_24_FLOAT = 0x00000004, 20440 DEPTH_8_24_FLOAT = 0x00000005, 20441 DEPTH_32_FLOAT = 0x00000006, 20442 DEPTH_X24_8_32_FLOAT = 0x00000007, 20443 } DepthFormat; 20444 20445 /* 20446 * ZFormat enum 20447 */ 20448 20449 typedef enum ZFormat { 20450 Z_INVALID = 0x00000000, 20451 Z_16 = 0x00000001, 20452 Z_24 = 0x00000002, 20453 Z_32_FLOAT = 0x00000003, 20454 } ZFormat; 20455 20456 /* 20457 * StencilFormat enum 20458 */ 20459 20460 typedef enum StencilFormat { 20461 STENCIL_INVALID = 0x00000000, 20462 STENCIL_8 = 0x00000001, 20463 } StencilFormat; 20464 20465 /* 20466 * CmaskMode enum 20467 */ 20468 20469 typedef enum CmaskMode { 20470 CMASK_CLEAR_NONE = 0x00000000, 20471 CMASK_CLEAR_ONE = 0x00000001, 20472 CMASK_CLEAR_ALL = 0x00000002, 20473 CMASK_ANY_EXPANDED = 0x00000003, 20474 CMASK_ALPHA0_FRAG1 = 0x00000004, 20475 CMASK_ALPHA0_FRAG2 = 0x00000005, 20476 CMASK_ALPHA0_FRAG4 = 0x00000006, 20477 CMASK_ALPHA0_FRAGS = 0x00000007, 20478 CMASK_ALPHA1_FRAG1 = 0x00000008, 20479 CMASK_ALPHA1_FRAG2 = 0x00000009, 20480 CMASK_ALPHA1_FRAG4 = 0x0000000a, 20481 CMASK_ALPHA1_FRAGS = 0x0000000b, 20482 CMASK_ALPHAX_FRAG1 = 0x0000000c, 20483 CMASK_ALPHAX_FRAG2 = 0x0000000d, 20484 CMASK_ALPHAX_FRAG4 = 0x0000000e, 20485 CMASK_ALPHAX_FRAGS = 0x0000000f, 20486 } CmaskMode; 20487 20488 /* 20489 * QuadExportFormat enum 20490 */ 20491 20492 typedef enum QuadExportFormat { 20493 EXPORT_UNUSED = 0x00000000, 20494 EXPORT_32_R = 0x00000001, 20495 EXPORT_32_GR = 0x00000002, 20496 EXPORT_32_AR = 0x00000003, 20497 EXPORT_FP16_ABGR = 0x00000004, 20498 EXPORT_UNSIGNED16_ABGR = 0x00000005, 20499 EXPORT_SIGNED16_ABGR = 0x00000006, 20500 EXPORT_32_ABGR = 0x00000007, 20501 EXPORT_32BPP_8PIX = 0x00000008, 20502 EXPORT_16_16_UNSIGNED_8PIX = 0x00000009, 20503 EXPORT_16_16_SIGNED_8PIX = 0x0000000a, 20504 EXPORT_16_16_FLOAT_8PIX = 0x0000000b, 20505 } QuadExportFormat; 20506 20507 /* 20508 * QuadExportFormatOld enum 20509 */ 20510 20511 typedef enum QuadExportFormatOld { 20512 EXPORT_4P_32BPC_ABGR = 0x00000000, 20513 EXPORT_4P_16BPC_ABGR = 0x00000001, 20514 EXPORT_4P_32BPC_GR = 0x00000002, 20515 EXPORT_4P_32BPC_AR = 0x00000003, 20516 EXPORT_2P_32BPC_ABGR = 0x00000004, 20517 EXPORT_8P_32BPC_R = 0x00000005, 20518 } QuadExportFormatOld; 20519 20520 /* 20521 * ColorFormat enum 20522 */ 20523 20524 typedef enum ColorFormat { 20525 COLOR_INVALID = 0x00000000, 20526 COLOR_8 = 0x00000001, 20527 COLOR_16 = 0x00000002, 20528 COLOR_8_8 = 0x00000003, 20529 COLOR_32 = 0x00000004, 20530 COLOR_16_16 = 0x00000005, 20531 COLOR_10_11_11 = 0x00000006, 20532 COLOR_11_11_10 = 0x00000007, 20533 COLOR_10_10_10_2 = 0x00000008, 20534 COLOR_2_10_10_10 = 0x00000009, 20535 COLOR_8_8_8_8 = 0x0000000a, 20536 COLOR_32_32 = 0x0000000b, 20537 COLOR_16_16_16_16 = 0x0000000c, 20538 COLOR_RESERVED_13 = 0x0000000d, 20539 COLOR_32_32_32_32 = 0x0000000e, 20540 COLOR_RESERVED_15 = 0x0000000f, 20541 COLOR_5_6_5 = 0x00000010, 20542 COLOR_1_5_5_5 = 0x00000011, 20543 COLOR_5_5_5_1 = 0x00000012, 20544 COLOR_4_4_4_4 = 0x00000013, 20545 COLOR_8_24 = 0x00000014, 20546 COLOR_24_8 = 0x00000015, 20547 COLOR_X24_8_32_FLOAT = 0x00000016, 20548 COLOR_RESERVED_23 = 0x00000017, 20549 COLOR_RESERVED_24 = 0x00000018, 20550 COLOR_RESERVED_25 = 0x00000019, 20551 COLOR_RESERVED_26 = 0x0000001a, 20552 COLOR_RESERVED_27 = 0x0000001b, 20553 COLOR_RESERVED_28 = 0x0000001c, 20554 COLOR_RESERVED_29 = 0x0000001d, 20555 COLOR_RESERVED_30 = 0x0000001e, 20556 COLOR_2_10_10_10_6E4 = 0x0000001f, 20557 } ColorFormat; 20558 20559 /* 20560 * SurfaceFormat enum 20561 */ 20562 20563 typedef enum SurfaceFormat { 20564 FMT_INVALID = 0x00000000, 20565 FMT_8 = 0x00000001, 20566 FMT_16 = 0x00000002, 20567 FMT_8_8 = 0x00000003, 20568 FMT_32 = 0x00000004, 20569 FMT_16_16 = 0x00000005, 20570 FMT_10_11_11 = 0x00000006, 20571 FMT_11_11_10 = 0x00000007, 20572 FMT_10_10_10_2 = 0x00000008, 20573 FMT_2_10_10_10 = 0x00000009, 20574 FMT_8_8_8_8 = 0x0000000a, 20575 FMT_32_32 = 0x0000000b, 20576 FMT_16_16_16_16 = 0x0000000c, 20577 FMT_32_32_32 = 0x0000000d, 20578 FMT_32_32_32_32 = 0x0000000e, 20579 FMT_RESERVED_4 = 0x0000000f, 20580 FMT_5_6_5 = 0x00000010, 20581 FMT_1_5_5_5 = 0x00000011, 20582 FMT_5_5_5_1 = 0x00000012, 20583 FMT_4_4_4_4 = 0x00000013, 20584 FMT_8_24 = 0x00000014, 20585 FMT_24_8 = 0x00000015, 20586 FMT_X24_8_32_FLOAT = 0x00000016, 20587 FMT_RESERVED_33 = 0x00000017, 20588 FMT_11_11_10_FLOAT = 0x00000018, 20589 FMT_16_FLOAT = 0x00000019, 20590 FMT_32_FLOAT = 0x0000001a, 20591 FMT_16_16_FLOAT = 0x0000001b, 20592 FMT_8_24_FLOAT = 0x0000001c, 20593 FMT_24_8_FLOAT = 0x0000001d, 20594 FMT_32_32_FLOAT = 0x0000001e, 20595 FMT_10_11_11_FLOAT = 0x0000001f, 20596 FMT_16_16_16_16_FLOAT = 0x00000020, 20597 FMT_3_3_2 = 0x00000021, 20598 FMT_6_5_5 = 0x00000022, 20599 FMT_32_32_32_32_FLOAT = 0x00000023, 20600 FMT_RESERVED_36 = 0x00000024, 20601 FMT_1 = 0x00000025, 20602 FMT_1_REVERSED = 0x00000026, 20603 FMT_GB_GR = 0x00000027, 20604 FMT_BG_RG = 0x00000028, 20605 FMT_32_AS_8 = 0x00000029, 20606 FMT_32_AS_8_8 = 0x0000002a, 20607 FMT_5_9_9_9_SHAREDEXP = 0x0000002b, 20608 FMT_8_8_8 = 0x0000002c, 20609 FMT_16_16_16 = 0x0000002d, 20610 FMT_16_16_16_FLOAT = 0x0000002e, 20611 FMT_4_4 = 0x0000002f, 20612 FMT_32_32_32_FLOAT = 0x00000030, 20613 FMT_BC1 = 0x00000031, 20614 FMT_BC2 = 0x00000032, 20615 FMT_BC3 = 0x00000033, 20616 FMT_BC4 = 0x00000034, 20617 FMT_BC5 = 0x00000035, 20618 FMT_BC6 = 0x00000036, 20619 FMT_BC7 = 0x00000037, 20620 FMT_32_AS_32_32_32_32 = 0x00000038, 20621 FMT_APC3 = 0x00000039, 20622 FMT_APC4 = 0x0000003a, 20623 FMT_APC5 = 0x0000003b, 20624 FMT_APC6 = 0x0000003c, 20625 FMT_APC7 = 0x0000003d, 20626 FMT_CTX1 = 0x0000003e, 20627 FMT_RESERVED_63 = 0x0000003f, 20628 } SurfaceFormat; 20629 20630 /* 20631 * IMG_NUM_FORMAT_FMASK enum 20632 */ 20633 20634 typedef enum IMG_NUM_FORMAT_FMASK { 20635 IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000, 20636 IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001, 20637 IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002, 20638 IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003, 20639 IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004, 20640 IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005, 20641 IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006, 20642 IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007, 20643 IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008, 20644 IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009, 20645 IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a, 20646 IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b, 20647 IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c, 20648 IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d, 20649 IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e, 20650 IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f, 20651 } IMG_NUM_FORMAT_FMASK; 20652 20653 /* 20654 * IMG_NUM_FORMAT_N_IN_16 enum 20655 */ 20656 20657 typedef enum IMG_NUM_FORMAT_N_IN_16 { 20658 IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000, 20659 IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001, 20660 IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002, 20661 IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003, 20662 IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004, 20663 IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005, 20664 IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006, 20665 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007, 20666 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008, 20667 IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009, 20668 IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a, 20669 IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b, 20670 IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c, 20671 IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d, 20672 IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e, 20673 IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f, 20674 } IMG_NUM_FORMAT_N_IN_16; 20675 20676 /* 20677 * TileType enum 20678 */ 20679 20680 typedef enum TileType { 20681 ARRAY_COLOR_TILE = 0x00000000, 20682 ARRAY_DEPTH_TILE = 0x00000001, 20683 } TileType; 20684 20685 /* 20686 * NonDispTilingOrder enum 20687 */ 20688 20689 typedef enum NonDispTilingOrder { 20690 ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000, 20691 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001, 20692 } NonDispTilingOrder; 20693 20694 /* 20695 * MicroTileMode enum 20696 */ 20697 20698 typedef enum MicroTileMode { 20699 ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000, 20700 ADDR_SURF_THIN_MICRO_TILING = 0x00000001, 20701 ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002, 20702 ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003, 20703 ADDR_SURF_THICK_MICRO_TILING = 0x00000004, 20704 } MicroTileMode; 20705 20706 /* 20707 * TileSplit enum 20708 */ 20709 20710 typedef enum TileSplit { 20711 ADDR_SURF_TILE_SPLIT_64B = 0x00000000, 20712 ADDR_SURF_TILE_SPLIT_128B = 0x00000001, 20713 ADDR_SURF_TILE_SPLIT_256B = 0x00000002, 20714 ADDR_SURF_TILE_SPLIT_512B = 0x00000003, 20715 ADDR_SURF_TILE_SPLIT_1KB = 0x00000004, 20716 ADDR_SURF_TILE_SPLIT_2KB = 0x00000005, 20717 ADDR_SURF_TILE_SPLIT_4KB = 0x00000006, 20718 } TileSplit; 20719 20720 /* 20721 * SampleSplit enum 20722 */ 20723 20724 typedef enum SampleSplit { 20725 ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000, 20726 ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001, 20727 ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002, 20728 ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003, 20729 } SampleSplit; 20730 20731 /* 20732 * PipeConfig enum 20733 */ 20734 20735 typedef enum PipeConfig { 20736 ADDR_SURF_P2 = 0x00000000, 20737 ADDR_SURF_P2_RESERVED0 = 0x00000001, 20738 ADDR_SURF_P2_RESERVED1 = 0x00000002, 20739 ADDR_SURF_P2_RESERVED2 = 0x00000003, 20740 ADDR_SURF_P4_8x16 = 0x00000004, 20741 ADDR_SURF_P4_16x16 = 0x00000005, 20742 ADDR_SURF_P4_16x32 = 0x00000006, 20743 ADDR_SURF_P4_32x32 = 0x00000007, 20744 ADDR_SURF_P8_16x16_8x16 = 0x00000008, 20745 ADDR_SURF_P8_16x32_8x16 = 0x00000009, 20746 ADDR_SURF_P8_32x32_8x16 = 0x0000000a, 20747 ADDR_SURF_P8_16x32_16x16 = 0x0000000b, 20748 ADDR_SURF_P8_32x32_16x16 = 0x0000000c, 20749 ADDR_SURF_P8_32x32_16x32 = 0x0000000d, 20750 ADDR_SURF_P8_32x64_32x32 = 0x0000000e, 20751 ADDR_SURF_P8_RESERVED0 = 0x0000000f, 20752 ADDR_SURF_P16_32x32_8x16 = 0x00000010, 20753 ADDR_SURF_P16_32x32_16x16 = 0x00000011, 20754 ADDR_SURF_P16 = 0x00000012, 20755 } PipeConfig; 20756 20757 /* 20758 * SeEnable enum 20759 */ 20760 20761 typedef enum SeEnable { 20762 ADDR_CONFIG_DISABLE_SE = 0x00000000, 20763 ADDR_CONFIG_ENABLE_SE = 0x00000001, 20764 } SeEnable; 20765 20766 /* 20767 * NumBanks enum 20768 */ 20769 20770 typedef enum NumBanks { 20771 ADDR_SURF_2_BANK = 0x00000000, 20772 ADDR_SURF_4_BANK = 0x00000001, 20773 ADDR_SURF_8_BANK = 0x00000002, 20774 ADDR_SURF_16_BANK = 0x00000003, 20775 } NumBanks; 20776 20777 /* 20778 * BankWidth enum 20779 */ 20780 20781 typedef enum BankWidth { 20782 ADDR_SURF_BANK_WIDTH_1 = 0x00000000, 20783 ADDR_SURF_BANK_WIDTH_2 = 0x00000001, 20784 ADDR_SURF_BANK_WIDTH_4 = 0x00000002, 20785 ADDR_SURF_BANK_WIDTH_8 = 0x00000003, 20786 } BankWidth; 20787 20788 /* 20789 * BankHeight enum 20790 */ 20791 20792 typedef enum BankHeight { 20793 ADDR_SURF_BANK_HEIGHT_1 = 0x00000000, 20794 ADDR_SURF_BANK_HEIGHT_2 = 0x00000001, 20795 ADDR_SURF_BANK_HEIGHT_4 = 0x00000002, 20796 ADDR_SURF_BANK_HEIGHT_8 = 0x00000003, 20797 } BankHeight; 20798 20799 /* 20800 * BankWidthHeight enum 20801 */ 20802 20803 typedef enum BankWidthHeight { 20804 ADDR_SURF_BANK_WH_1 = 0x00000000, 20805 ADDR_SURF_BANK_WH_2 = 0x00000001, 20806 ADDR_SURF_BANK_WH_4 = 0x00000002, 20807 ADDR_SURF_BANK_WH_8 = 0x00000003, 20808 } BankWidthHeight; 20809 20810 /* 20811 * MacroTileAspect enum 20812 */ 20813 20814 typedef enum MacroTileAspect { 20815 ADDR_SURF_MACRO_ASPECT_1 = 0x00000000, 20816 ADDR_SURF_MACRO_ASPECT_2 = 0x00000001, 20817 ADDR_SURF_MACRO_ASPECT_4 = 0x00000002, 20818 ADDR_SURF_MACRO_ASPECT_8 = 0x00000003, 20819 } MacroTileAspect; 20820 20821 /* 20822 * PipeTiling enum 20823 */ 20824 20825 typedef enum PipeTiling { 20826 CONFIG_1_PIPE = 0x00000000, 20827 CONFIG_2_PIPE = 0x00000001, 20828 CONFIG_4_PIPE = 0x00000002, 20829 CONFIG_8_PIPE = 0x00000003, 20830 } PipeTiling; 20831 20832 /* 20833 * BankTiling enum 20834 */ 20835 20836 typedef enum BankTiling { 20837 CONFIG_4_BANK = 0x00000000, 20838 CONFIG_8_BANK = 0x00000001, 20839 } BankTiling; 20840 20841 /* 20842 * GroupInterleave enum 20843 */ 20844 20845 typedef enum GroupInterleave { 20846 CONFIG_256B_GROUP = 0x00000000, 20847 CONFIG_512B_GROUP = 0x00000001, 20848 } GroupInterleave; 20849 20850 /* 20851 * RowTiling enum 20852 */ 20853 20854 typedef enum RowTiling { 20855 CONFIG_1KB_ROW = 0x00000000, 20856 CONFIG_2KB_ROW = 0x00000001, 20857 CONFIG_4KB_ROW = 0x00000002, 20858 CONFIG_8KB_ROW = 0x00000003, 20859 CONFIG_1KB_ROW_OPT = 0x00000004, 20860 CONFIG_2KB_ROW_OPT = 0x00000005, 20861 CONFIG_4KB_ROW_OPT = 0x00000006, 20862 CONFIG_8KB_ROW_OPT = 0x00000007, 20863 } RowTiling; 20864 20865 /* 20866 * BankSwapBytes enum 20867 */ 20868 20869 typedef enum BankSwapBytes { 20870 CONFIG_128B_SWAPS = 0x00000000, 20871 CONFIG_256B_SWAPS = 0x00000001, 20872 CONFIG_512B_SWAPS = 0x00000002, 20873 CONFIG_1KB_SWAPS = 0x00000003, 20874 } BankSwapBytes; 20875 20876 /* 20877 * SampleSplitBytes enum 20878 */ 20879 20880 typedef enum SampleSplitBytes { 20881 CONFIG_1KB_SPLIT = 0x00000000, 20882 CONFIG_2KB_SPLIT = 0x00000001, 20883 CONFIG_4KB_SPLIT = 0x00000002, 20884 CONFIG_8KB_SPLIT = 0x00000003, 20885 } SampleSplitBytes; 20886 20887 /* 20888 * SurfaceNumber enum 20889 */ 20890 20891 typedef enum SurfaceNumber { 20892 NUMBER_UNORM = 0x00000000, 20893 NUMBER_SNORM = 0x00000001, 20894 NUMBER_USCALED = 0x00000002, 20895 NUMBER_SSCALED = 0x00000003, 20896 NUMBER_UINT = 0x00000004, 20897 NUMBER_SINT = 0x00000005, 20898 NUMBER_SRGB = 0x00000006, 20899 NUMBER_FLOAT = 0x00000007, 20900 } SurfaceNumber; 20901 20902 /* 20903 * SurfaceSwap enum 20904 */ 20905 20906 typedef enum SurfaceSwap { 20907 SWAP_STD = 0x00000000, 20908 SWAP_ALT = 0x00000001, 20909 SWAP_STD_REV = 0x00000002, 20910 SWAP_ALT_REV = 0x00000003, 20911 } SurfaceSwap; 20912 20913 /* 20914 * RoundMode enum 20915 */ 20916 20917 typedef enum RoundMode { 20918 ROUND_BY_HALF = 0x00000000, 20919 ROUND_TRUNCATE = 0x00000001, 20920 } RoundMode; 20921 20922 /* 20923 * BUF_FMT enum 20924 */ 20925 20926 typedef enum BUF_FMT { 20927 BUF_FMT_INVALID = 0x00000000, 20928 BUF_FMT_8_UNORM = 0x00000001, 20929 BUF_FMT_8_SNORM = 0x00000002, 20930 BUF_FMT_8_USCALED = 0x00000003, 20931 BUF_FMT_8_SSCALED = 0x00000004, 20932 BUF_FMT_8_UINT = 0x00000005, 20933 BUF_FMT_8_SINT = 0x00000006, 20934 BUF_FMT_16_UNORM = 0x00000007, 20935 BUF_FMT_16_SNORM = 0x00000008, 20936 BUF_FMT_16_USCALED = 0x00000009, 20937 BUF_FMT_16_SSCALED = 0x0000000a, 20938 BUF_FMT_16_UINT = 0x0000000b, 20939 BUF_FMT_16_SINT = 0x0000000c, 20940 BUF_FMT_16_FLOAT = 0x0000000d, 20941 BUF_FMT_8_8_UNORM = 0x0000000e, 20942 BUF_FMT_8_8_SNORM = 0x0000000f, 20943 BUF_FMT_8_8_USCALED = 0x00000010, 20944 BUF_FMT_8_8_SSCALED = 0x00000011, 20945 BUF_FMT_8_8_UINT = 0x00000012, 20946 BUF_FMT_8_8_SINT = 0x00000013, 20947 BUF_FMT_32_UINT = 0x00000014, 20948 BUF_FMT_32_SINT = 0x00000015, 20949 BUF_FMT_32_FLOAT = 0x00000016, 20950 BUF_FMT_16_16_UNORM = 0x00000017, 20951 BUF_FMT_16_16_SNORM = 0x00000018, 20952 BUF_FMT_16_16_USCALED = 0x00000019, 20953 BUF_FMT_16_16_SSCALED = 0x0000001a, 20954 BUF_FMT_16_16_UINT = 0x0000001b, 20955 BUF_FMT_16_16_SINT = 0x0000001c, 20956 BUF_FMT_16_16_FLOAT = 0x0000001d, 20957 BUF_FMT_10_11_11_UNORM = 0x0000001e, 20958 BUF_FMT_10_11_11_SNORM = 0x0000001f, 20959 BUF_FMT_10_11_11_USCALED = 0x00000020, 20960 BUF_FMT_10_11_11_SSCALED = 0x00000021, 20961 BUF_FMT_10_11_11_UINT = 0x00000022, 20962 BUF_FMT_10_11_11_SINT = 0x00000023, 20963 BUF_FMT_10_11_11_FLOAT = 0x00000024, 20964 BUF_FMT_11_11_10_UNORM = 0x00000025, 20965 BUF_FMT_11_11_10_SNORM = 0x00000026, 20966 BUF_FMT_11_11_10_USCALED = 0x00000027, 20967 BUF_FMT_11_11_10_SSCALED = 0x00000028, 20968 BUF_FMT_11_11_10_UINT = 0x00000029, 20969 BUF_FMT_11_11_10_SINT = 0x0000002a, 20970 BUF_FMT_11_11_10_FLOAT = 0x0000002b, 20971 BUF_FMT_10_10_10_2_UNORM = 0x0000002c, 20972 BUF_FMT_10_10_10_2_SNORM = 0x0000002d, 20973 BUF_FMT_10_10_10_2_USCALED = 0x0000002e, 20974 BUF_FMT_10_10_10_2_SSCALED = 0x0000002f, 20975 BUF_FMT_10_10_10_2_UINT = 0x00000030, 20976 BUF_FMT_10_10_10_2_SINT = 0x00000031, 20977 BUF_FMT_2_10_10_10_UNORM = 0x00000032, 20978 BUF_FMT_2_10_10_10_SNORM = 0x00000033, 20979 BUF_FMT_2_10_10_10_USCALED = 0x00000034, 20980 BUF_FMT_2_10_10_10_SSCALED = 0x00000035, 20981 BUF_FMT_2_10_10_10_UINT = 0x00000036, 20982 BUF_FMT_2_10_10_10_SINT = 0x00000037, 20983 BUF_FMT_8_8_8_8_UNORM = 0x00000038, 20984 BUF_FMT_8_8_8_8_SNORM = 0x00000039, 20985 BUF_FMT_8_8_8_8_USCALED = 0x0000003a, 20986 BUF_FMT_8_8_8_8_SSCALED = 0x0000003b, 20987 BUF_FMT_8_8_8_8_UINT = 0x0000003c, 20988 BUF_FMT_8_8_8_8_SINT = 0x0000003d, 20989 BUF_FMT_32_32_UINT = 0x0000003e, 20990 BUF_FMT_32_32_SINT = 0x0000003f, 20991 BUF_FMT_32_32_FLOAT = 0x00000040, 20992 BUF_FMT_16_16_16_16_UNORM = 0x00000041, 20993 BUF_FMT_16_16_16_16_SNORM = 0x00000042, 20994 BUF_FMT_16_16_16_16_USCALED = 0x00000043, 20995 BUF_FMT_16_16_16_16_SSCALED = 0x00000044, 20996 BUF_FMT_16_16_16_16_UINT = 0x00000045, 20997 BUF_FMT_16_16_16_16_SINT = 0x00000046, 20998 BUF_FMT_16_16_16_16_FLOAT = 0x00000047, 20999 BUF_FMT_32_32_32_UINT = 0x00000048, 21000 BUF_FMT_32_32_32_SINT = 0x00000049, 21001 BUF_FMT_32_32_32_FLOAT = 0x0000004a, 21002 BUF_FMT_32_32_32_32_UINT = 0x0000004b, 21003 BUF_FMT_32_32_32_32_SINT = 0x0000004c, 21004 BUF_FMT_32_32_32_32_FLOAT = 0x0000004d, 21005 BUF_FMT_RESERVED_78 = 0x0000004e, 21006 BUF_FMT_RESERVED_79 = 0x0000004f, 21007 BUF_FMT_RESERVED_80 = 0x00000050, 21008 BUF_FMT_RESERVED_81 = 0x00000051, 21009 BUF_FMT_RESERVED_82 = 0x00000052, 21010 BUF_FMT_RESERVED_83 = 0x00000053, 21011 BUF_FMT_RESERVED_84 = 0x00000054, 21012 BUF_FMT_RESERVED_85 = 0x00000055, 21013 BUF_FMT_RESERVED_86 = 0x00000056, 21014 BUF_FMT_RESERVED_87 = 0x00000057, 21015 BUF_FMT_RESERVED_88 = 0x00000058, 21016 BUF_FMT_RESERVED_89 = 0x00000059, 21017 BUF_FMT_RESERVED_90 = 0x0000005a, 21018 BUF_FMT_RESERVED_91 = 0x0000005b, 21019 BUF_FMT_RESERVED_92 = 0x0000005c, 21020 BUF_FMT_RESERVED_93 = 0x0000005d, 21021 BUF_FMT_RESERVED_94 = 0x0000005e, 21022 BUF_FMT_RESERVED_95 = 0x0000005f, 21023 BUF_FMT_RESERVED_96 = 0x00000060, 21024 BUF_FMT_RESERVED_97 = 0x00000061, 21025 BUF_FMT_RESERVED_98 = 0x00000062, 21026 BUF_FMT_RESERVED_99 = 0x00000063, 21027 BUF_FMT_RESERVED_100 = 0x00000064, 21028 BUF_FMT_RESERVED_101 = 0x00000065, 21029 BUF_FMT_RESERVED_102 = 0x00000066, 21030 BUF_FMT_RESERVED_103 = 0x00000067, 21031 BUF_FMT_RESERVED_104 = 0x00000068, 21032 BUF_FMT_RESERVED_105 = 0x00000069, 21033 BUF_FMT_RESERVED_106 = 0x0000006a, 21034 BUF_FMT_RESERVED_107 = 0x0000006b, 21035 BUF_FMT_RESERVED_108 = 0x0000006c, 21036 BUF_FMT_RESERVED_109 = 0x0000006d, 21037 BUF_FMT_RESERVED_110 = 0x0000006e, 21038 BUF_FMT_RESERVED_111 = 0x0000006f, 21039 BUF_FMT_RESERVED_112 = 0x00000070, 21040 BUF_FMT_RESERVED_113 = 0x00000071, 21041 BUF_FMT_RESERVED_114 = 0x00000072, 21042 BUF_FMT_RESERVED_115 = 0x00000073, 21043 BUF_FMT_RESERVED_116 = 0x00000074, 21044 BUF_FMT_RESERVED_117 = 0x00000075, 21045 BUF_FMT_RESERVED_118 = 0x00000076, 21046 BUF_FMT_RESERVED_119 = 0x00000077, 21047 BUF_FMT_RESERVED_120 = 0x00000078, 21048 BUF_FMT_RESERVED_121 = 0x00000079, 21049 BUF_FMT_RESERVED_122 = 0x0000007a, 21050 BUF_FMT_RESERVED_123 = 0x0000007b, 21051 BUF_FMT_RESERVED_124 = 0x0000007c, 21052 BUF_FMT_RESERVED_125 = 0x0000007d, 21053 BUF_FMT_RESERVED_126 = 0x0000007e, 21054 BUF_FMT_RESERVED_127 = 0x0000007f, 21055 } BUF_FMT; 21056 21057 /* 21058 * IMG_FMT enum 21059 */ 21060 21061 typedef enum IMG_FMT { 21062 IMG_FMT_INVALID = 0x00000000, 21063 IMG_FMT_8_UNORM = 0x00000001, 21064 IMG_FMT_8_SNORM = 0x00000002, 21065 IMG_FMT_8_USCALED = 0x00000003, 21066 IMG_FMT_8_SSCALED = 0x00000004, 21067 IMG_FMT_8_UINT = 0x00000005, 21068 IMG_FMT_8_SINT = 0x00000006, 21069 IMG_FMT_16_UNORM = 0x00000007, 21070 IMG_FMT_16_SNORM = 0x00000008, 21071 IMG_FMT_16_USCALED = 0x00000009, 21072 IMG_FMT_16_SSCALED = 0x0000000a, 21073 IMG_FMT_16_UINT = 0x0000000b, 21074 IMG_FMT_16_SINT = 0x0000000c, 21075 IMG_FMT_16_FLOAT = 0x0000000d, 21076 IMG_FMT_8_8_UNORM = 0x0000000e, 21077 IMG_FMT_8_8_SNORM = 0x0000000f, 21078 IMG_FMT_8_8_USCALED = 0x00000010, 21079 IMG_FMT_8_8_SSCALED = 0x00000011, 21080 IMG_FMT_8_8_UINT = 0x00000012, 21081 IMG_FMT_8_8_SINT = 0x00000013, 21082 IMG_FMT_32_UINT = 0x00000014, 21083 IMG_FMT_32_SINT = 0x00000015, 21084 IMG_FMT_32_FLOAT = 0x00000016, 21085 IMG_FMT_16_16_UNORM = 0x00000017, 21086 IMG_FMT_16_16_SNORM = 0x00000018, 21087 IMG_FMT_16_16_USCALED = 0x00000019, 21088 IMG_FMT_16_16_SSCALED = 0x0000001a, 21089 IMG_FMT_16_16_UINT = 0x0000001b, 21090 IMG_FMT_16_16_SINT = 0x0000001c, 21091 IMG_FMT_16_16_FLOAT = 0x0000001d, 21092 IMG_FMT_10_11_11_UNORM = 0x0000001e, 21093 IMG_FMT_10_11_11_SNORM = 0x0000001f, 21094 IMG_FMT_10_11_11_USCALED = 0x00000020, 21095 IMG_FMT_10_11_11_SSCALED = 0x00000021, 21096 IMG_FMT_10_11_11_UINT = 0x00000022, 21097 IMG_FMT_10_11_11_SINT = 0x00000023, 21098 IMG_FMT_10_11_11_FLOAT = 0x00000024, 21099 IMG_FMT_11_11_10_UNORM = 0x00000025, 21100 IMG_FMT_11_11_10_SNORM = 0x00000026, 21101 IMG_FMT_11_11_10_USCALED = 0x00000027, 21102 IMG_FMT_11_11_10_SSCALED = 0x00000028, 21103 IMG_FMT_11_11_10_UINT = 0x00000029, 21104 IMG_FMT_11_11_10_SINT = 0x0000002a, 21105 IMG_FMT_11_11_10_FLOAT = 0x0000002b, 21106 IMG_FMT_10_10_10_2_UNORM = 0x0000002c, 21107 IMG_FMT_10_10_10_2_SNORM = 0x0000002d, 21108 IMG_FMT_10_10_10_2_USCALED = 0x0000002e, 21109 IMG_FMT_10_10_10_2_SSCALED = 0x0000002f, 21110 IMG_FMT_10_10_10_2_UINT = 0x00000030, 21111 IMG_FMT_10_10_10_2_SINT = 0x00000031, 21112 IMG_FMT_2_10_10_10_UNORM = 0x00000032, 21113 IMG_FMT_2_10_10_10_SNORM = 0x00000033, 21114 IMG_FMT_2_10_10_10_USCALED = 0x00000034, 21115 IMG_FMT_2_10_10_10_SSCALED = 0x00000035, 21116 IMG_FMT_2_10_10_10_UINT = 0x00000036, 21117 IMG_FMT_2_10_10_10_SINT = 0x00000037, 21118 IMG_FMT_8_8_8_8_UNORM = 0x00000038, 21119 IMG_FMT_8_8_8_8_SNORM = 0x00000039, 21120 IMG_FMT_8_8_8_8_USCALED = 0x0000003a, 21121 IMG_FMT_8_8_8_8_SSCALED = 0x0000003b, 21122 IMG_FMT_8_8_8_8_UINT = 0x0000003c, 21123 IMG_FMT_8_8_8_8_SINT = 0x0000003d, 21124 IMG_FMT_32_32_UINT = 0x0000003e, 21125 IMG_FMT_32_32_SINT = 0x0000003f, 21126 IMG_FMT_32_32_FLOAT = 0x00000040, 21127 IMG_FMT_16_16_16_16_UNORM = 0x00000041, 21128 IMG_FMT_16_16_16_16_SNORM = 0x00000042, 21129 IMG_FMT_16_16_16_16_USCALED = 0x00000043, 21130 IMG_FMT_16_16_16_16_SSCALED = 0x00000044, 21131 IMG_FMT_16_16_16_16_UINT = 0x00000045, 21132 IMG_FMT_16_16_16_16_SINT = 0x00000046, 21133 IMG_FMT_16_16_16_16_FLOAT = 0x00000047, 21134 IMG_FMT_32_32_32_UINT = 0x00000048, 21135 IMG_FMT_32_32_32_SINT = 0x00000049, 21136 IMG_FMT_32_32_32_FLOAT = 0x0000004a, 21137 IMG_FMT_32_32_32_32_UINT = 0x0000004b, 21138 IMG_FMT_32_32_32_32_SINT = 0x0000004c, 21139 IMG_FMT_32_32_32_32_FLOAT = 0x0000004d, 21140 IMG_FMT_RESERVED_78 = 0x0000004e, 21141 IMG_FMT_RESERVED_79 = 0x0000004f, 21142 IMG_FMT_RESERVED_80 = 0x00000050, 21143 IMG_FMT_RESERVED_81 = 0x00000051, 21144 IMG_FMT_RESERVED_82 = 0x00000052, 21145 IMG_FMT_RESERVED_83 = 0x00000053, 21146 IMG_FMT_RESERVED_84 = 0x00000054, 21147 IMG_FMT_RESERVED_85 = 0x00000055, 21148 IMG_FMT_RESERVED_86 = 0x00000056, 21149 IMG_FMT_RESERVED_87 = 0x00000057, 21150 IMG_FMT_RESERVED_88 = 0x00000058, 21151 IMG_FMT_RESERVED_89 = 0x00000059, 21152 IMG_FMT_RESERVED_90 = 0x0000005a, 21153 IMG_FMT_RESERVED_91 = 0x0000005b, 21154 IMG_FMT_RESERVED_92 = 0x0000005c, 21155 IMG_FMT_RESERVED_93 = 0x0000005d, 21156 IMG_FMT_RESERVED_94 = 0x0000005e, 21157 IMG_FMT_RESERVED_95 = 0x0000005f, 21158 IMG_FMT_RESERVED_96 = 0x00000060, 21159 IMG_FMT_RESERVED_97 = 0x00000061, 21160 IMG_FMT_RESERVED_98 = 0x00000062, 21161 IMG_FMT_RESERVED_99 = 0x00000063, 21162 IMG_FMT_RESERVED_100 = 0x00000064, 21163 IMG_FMT_RESERVED_101 = 0x00000065, 21164 IMG_FMT_RESERVED_102 = 0x00000066, 21165 IMG_FMT_RESERVED_103 = 0x00000067, 21166 IMG_FMT_RESERVED_104 = 0x00000068, 21167 IMG_FMT_RESERVED_105 = 0x00000069, 21168 IMG_FMT_RESERVED_106 = 0x0000006a, 21169 IMG_FMT_RESERVED_107 = 0x0000006b, 21170 IMG_FMT_RESERVED_108 = 0x0000006c, 21171 IMG_FMT_RESERVED_109 = 0x0000006d, 21172 IMG_FMT_RESERVED_110 = 0x0000006e, 21173 IMG_FMT_RESERVED_111 = 0x0000006f, 21174 IMG_FMT_RESERVED_112 = 0x00000070, 21175 IMG_FMT_RESERVED_113 = 0x00000071, 21176 IMG_FMT_RESERVED_114 = 0x00000072, 21177 IMG_FMT_RESERVED_115 = 0x00000073, 21178 IMG_FMT_RESERVED_116 = 0x00000074, 21179 IMG_FMT_RESERVED_117 = 0x00000075, 21180 IMG_FMT_RESERVED_118 = 0x00000076, 21181 IMG_FMT_RESERVED_119 = 0x00000077, 21182 IMG_FMT_RESERVED_120 = 0x00000078, 21183 IMG_FMT_RESERVED_121 = 0x00000079, 21184 IMG_FMT_RESERVED_122 = 0x0000007a, 21185 IMG_FMT_RESERVED_123 = 0x0000007b, 21186 IMG_FMT_RESERVED_124 = 0x0000007c, 21187 IMG_FMT_RESERVED_125 = 0x0000007d, 21188 IMG_FMT_RESERVED_126 = 0x0000007e, 21189 IMG_FMT_RESERVED_127 = 0x0000007f, 21190 IMG_FMT_8_SRGB = 0x00000080, 21191 IMG_FMT_8_8_SRGB = 0x00000081, 21192 IMG_FMT_8_8_8_8_SRGB = 0x00000082, 21193 IMG_FMT_6E4_FLOAT = 0x00000083, 21194 IMG_FMT_5_9_9_9_FLOAT = 0x00000084, 21195 IMG_FMT_5_6_5_UNORM = 0x00000085, 21196 IMG_FMT_1_5_5_5_UNORM = 0x00000086, 21197 IMG_FMT_5_5_5_1_UNORM = 0x00000087, 21198 IMG_FMT_4_4_4_4_UNORM = 0x00000088, 21199 IMG_FMT_4_4_UNORM = 0x00000089, 21200 IMG_FMT_1_UNORM = 0x0000008a, 21201 IMG_FMT_1_REVERSED_UNORM = 0x0000008b, 21202 IMG_FMT_32_FLOAT_CLAMP = 0x0000008c, 21203 IMG_FMT_8_24_UNORM = 0x0000008d, 21204 IMG_FMT_8_24_UINT = 0x0000008e, 21205 IMG_FMT_24_8_UNORM = 0x0000008f, 21206 IMG_FMT_24_8_UINT = 0x00000090, 21207 IMG_FMT_X24_8_32_UINT = 0x00000091, 21208 IMG_FMT_X24_8_32_FLOAT = 0x00000092, 21209 IMG_FMT_GB_GR_UNORM = 0x00000093, 21210 IMG_FMT_GB_GR_SNORM = 0x00000094, 21211 IMG_FMT_GB_GR_UINT = 0x00000095, 21212 IMG_FMT_GB_GR_SRGB = 0x00000096, 21213 IMG_FMT_BG_RG_UNORM = 0x00000097, 21214 IMG_FMT_BG_RG_SNORM = 0x00000098, 21215 IMG_FMT_BG_RG_UINT = 0x00000099, 21216 IMG_FMT_BG_RG_SRGB = 0x0000009a, 21217 IMG_FMT_RESERVED_155 = 0x0000009b, 21218 IMG_FMT_FMASK8_S2_F1 = 0x0000009c, 21219 IMG_FMT_FMASK8_S4_F1 = 0x0000009d, 21220 IMG_FMT_FMASK8_S8_F1 = 0x0000009e, 21221 IMG_FMT_FMASK8_S2_F2 = 0x0000009f, 21222 IMG_FMT_FMASK8_S4_F2 = 0x000000a0, 21223 IMG_FMT_FMASK8_S4_F4 = 0x000000a1, 21224 IMG_FMT_FMASK16_S16_F1 = 0x000000a2, 21225 IMG_FMT_FMASK16_S8_F2 = 0x000000a3, 21226 IMG_FMT_FMASK32_S16_F2 = 0x000000a4, 21227 IMG_FMT_FMASK32_S8_F4 = 0x000000a5, 21228 IMG_FMT_FMASK32_S8_F8 = 0x000000a6, 21229 IMG_FMT_FMASK64_S16_F4 = 0x000000a7, 21230 IMG_FMT_FMASK64_S16_F8 = 0x000000a8, 21231 IMG_FMT_BC1_UNORM = 0x000000a9, 21232 IMG_FMT_BC1_SRGB = 0x000000aa, 21233 IMG_FMT_BC2_UNORM = 0x000000ab, 21234 IMG_FMT_BC2_SRGB = 0x000000ac, 21235 IMG_FMT_BC3_UNORM = 0x000000ad, 21236 IMG_FMT_BC3_SRGB = 0x000000ae, 21237 IMG_FMT_BC4_UNORM = 0x000000af, 21238 IMG_FMT_BC4_SNORM = 0x000000b0, 21239 IMG_FMT_BC5_UNORM = 0x000000b1, 21240 IMG_FMT_BC5_SNORM = 0x000000b2, 21241 IMG_FMT_BC6_UFLOAT = 0x000000b3, 21242 IMG_FMT_BC6_SFLOAT = 0x000000b4, 21243 IMG_FMT_BC7_UNORM = 0x000000b5, 21244 IMG_FMT_BC7_SRGB = 0x000000b6, 21245 IMG_FMT_MM_8_UNORM = 0x00000109, 21246 IMG_FMT_MM_8_UINT = 0x0000010a, 21247 IMG_FMT_MM_8_8_UNORM = 0x0000010b, 21248 IMG_FMT_MM_8_8_UINT = 0x0000010c, 21249 IMG_FMT_MM_8_8_8_8_UNORM = 0x0000010d, 21250 IMG_FMT_MM_8_8_8_8_UINT = 0x0000010e, 21251 IMG_FMT_MM_VYUY8_UNORM = 0x0000010f, 21252 IMG_FMT_MM_VYUY8_UINT = 0x00000110, 21253 IMG_FMT_MM_10_11_11_UNORM = 0x00000111, 21254 IMG_FMT_MM_10_11_11_UINT = 0x00000112, 21255 IMG_FMT_MM_2_10_10_10_UNORM = 0x00000113, 21256 IMG_FMT_MM_2_10_10_10_UINT = 0x00000114, 21257 IMG_FMT_MM_16_16_16_16_UNORM = 0x00000115, 21258 IMG_FMT_MM_16_16_16_16_UINT = 0x00000116, 21259 IMG_FMT_MM_10_IN_16_UNORM = 0x00000117, 21260 IMG_FMT_MM_10_IN_16_UINT = 0x00000118, 21261 IMG_FMT_MM_10_IN_16_16_UNORM = 0x00000119, 21262 IMG_FMT_MM_10_IN_16_16_UINT = 0x0000011a, 21263 IMG_FMT_MM_10_IN_16_16_16_16_UNORM = 0x0000011b, 21264 IMG_FMT_MM_10_IN_16_16_16_16_UINT = 0x0000011c, 21265 IMG_FMT_RESERVED_285 = 0x0000011d, 21266 IMG_FMT_RESERVED_286 = 0x0000011e, 21267 IMG_FMT_RESERVED_287 = 0x0000011f, 21268 IMG_FMT_RESERVED_288 = 0x00000120, 21269 IMG_FMT_RESERVED_289 = 0x00000121, 21270 IMG_FMT_RESERVED_290 = 0x00000122, 21271 IMG_FMT_RESERVED_291 = 0x00000123, 21272 IMG_FMT_RESERVED_292 = 0x00000124, 21273 IMG_FMT_RESERVED_293 = 0x00000125, 21274 IMG_FMT_RESERVED_294 = 0x00000126, 21275 IMG_FMT_RESERVED_295 = 0x00000127, 21276 IMG_FMT_RESERVED_296 = 0x00000128, 21277 IMG_FMT_RESERVED_297 = 0x00000129, 21278 IMG_FMT_RESERVED_298 = 0x0000012a, 21279 IMG_FMT_RESERVED_299 = 0x0000012b, 21280 IMG_FMT_RESERVED_300 = 0x0000012c, 21281 IMG_FMT_RESERVED_301 = 0x0000012d, 21282 IMG_FMT_RESERVED_302 = 0x0000012e, 21283 IMG_FMT_RESERVED_303 = 0x0000012f, 21284 IMG_FMT_RESERVED_304 = 0x00000130, 21285 IMG_FMT_RESERVED_305 = 0x00000131, 21286 IMG_FMT_RESERVED_306 = 0x00000132, 21287 IMG_FMT_RESERVED_307 = 0x00000133, 21288 IMG_FMT_RESERVED_308 = 0x00000134, 21289 IMG_FMT_RESERVED_309 = 0x00000135, 21290 IMG_FMT_RESERVED_310 = 0x00000136, 21291 IMG_FMT_RESERVED_311 = 0x00000137, 21292 IMG_FMT_RESERVED_312 = 0x00000138, 21293 IMG_FMT_RESERVED_313 = 0x00000139, 21294 IMG_FMT_RESERVED_314 = 0x0000013a, 21295 IMG_FMT_RESERVED_315 = 0x0000013b, 21296 IMG_FMT_RESERVED_316 = 0x0000013c, 21297 IMG_FMT_RESERVED_317 = 0x0000013d, 21298 IMG_FMT_RESERVED_318 = 0x0000013e, 21299 IMG_FMT_RESERVED_319 = 0x0000013f, 21300 IMG_FMT_RESERVED_320 = 0x00000140, 21301 IMG_FMT_RESERVED_321 = 0x00000141, 21302 IMG_FMT_RESERVED_322 = 0x00000142, 21303 IMG_FMT_RESERVED_323 = 0x00000143, 21304 IMG_FMT_RESERVED_324 = 0x00000144, 21305 IMG_FMT_RESERVED_325 = 0x00000145, 21306 IMG_FMT_RESERVED_326 = 0x00000146, 21307 IMG_FMT_RESERVED_327 = 0x00000147, 21308 IMG_FMT_RESERVED_328 = 0x00000148, 21309 IMG_FMT_RESERVED_329 = 0x00000149, 21310 IMG_FMT_RESERVED_330 = 0x0000014a, 21311 IMG_FMT_RESERVED_331 = 0x0000014b, 21312 IMG_FMT_RESERVED_332 = 0x0000014c, 21313 IMG_FMT_RESERVED_333 = 0x0000014d, 21314 IMG_FMT_RESERVED_334 = 0x0000014e, 21315 IMG_FMT_RESERVED_335 = 0x0000014f, 21316 IMG_FMT_RESERVED_336 = 0x00000150, 21317 IMG_FMT_RESERVED_337 = 0x00000151, 21318 IMG_FMT_RESERVED_338 = 0x00000152, 21319 IMG_FMT_RESERVED_339 = 0x00000153, 21320 IMG_FMT_RESERVED_340 = 0x00000154, 21321 IMG_FMT_RESERVED_341 = 0x00000155, 21322 IMG_FMT_RESERVED_342 = 0x00000156, 21323 IMG_FMT_RESERVED_343 = 0x00000157, 21324 IMG_FMT_RESERVED_344 = 0x00000158, 21325 IMG_FMT_RESERVED_345 = 0x00000159, 21326 IMG_FMT_RESERVED_346 = 0x0000015a, 21327 IMG_FMT_RESERVED_347 = 0x0000015b, 21328 IMG_FMT_RESERVED_348 = 0x0000015c, 21329 IMG_FMT_RESERVED_349 = 0x0000015d, 21330 IMG_FMT_RESERVED_350 = 0x0000015e, 21331 IMG_FMT_RESERVED_351 = 0x0000015f, 21332 IMG_FMT_RESERVED_352 = 0x00000160, 21333 IMG_FMT_RESERVED_353 = 0x00000161, 21334 IMG_FMT_RESERVED_354 = 0x00000162, 21335 IMG_FMT_RESERVED_355 = 0x00000163, 21336 IMG_FMT_RESERVED_356 = 0x00000164, 21337 IMG_FMT_RESERVED_357 = 0x00000165, 21338 IMG_FMT_RESERVED_358 = 0x00000166, 21339 IMG_FMT_RESERVED_359 = 0x00000167, 21340 IMG_FMT_RESERVED_360 = 0x00000168, 21341 IMG_FMT_RESERVED_361 = 0x00000169, 21342 IMG_FMT_RESERVED_362 = 0x0000016a, 21343 IMG_FMT_RESERVED_363 = 0x0000016b, 21344 IMG_FMT_RESERVED_364 = 0x0000016c, 21345 IMG_FMT_RESERVED_365 = 0x0000016d, 21346 IMG_FMT_RESERVED_366 = 0x0000016e, 21347 IMG_FMT_RESERVED_367 = 0x0000016f, 21348 IMG_FMT_RESERVED_368 = 0x00000170, 21349 IMG_FMT_RESERVED_369 = 0x00000171, 21350 IMG_FMT_RESERVED_370 = 0x00000172, 21351 IMG_FMT_RESERVED_371 = 0x00000173, 21352 IMG_FMT_RESERVED_372 = 0x00000174, 21353 IMG_FMT_RESERVED_373 = 0x00000175, 21354 IMG_FMT_RESERVED_374 = 0x00000176, 21355 IMG_FMT_RESERVED_375 = 0x00000177, 21356 IMG_FMT_RESERVED_376 = 0x00000178, 21357 IMG_FMT_RESERVED_377 = 0x00000179, 21358 IMG_FMT_RESERVED_378 = 0x0000017a, 21359 IMG_FMT_RESERVED_379 = 0x0000017b, 21360 IMG_FMT_RESERVED_380 = 0x0000017c, 21361 IMG_FMT_RESERVED_381 = 0x0000017d, 21362 IMG_FMT_RESERVED_382 = 0x0000017e, 21363 IMG_FMT_RESERVED_383 = 0x0000017f, 21364 IMG_FMT_RESERVED_384 = 0x00000180, 21365 IMG_FMT_RESERVED_385 = 0x00000181, 21366 IMG_FMT_RESERVED_386 = 0x00000182, 21367 IMG_FMT_RESERVED_387 = 0x00000183, 21368 IMG_FMT_RESERVED_388 = 0x00000184, 21369 IMG_FMT_RESERVED_389 = 0x00000185, 21370 IMG_FMT_RESERVED_390 = 0x00000186, 21371 IMG_FMT_RESERVED_391 = 0x00000187, 21372 IMG_FMT_RESERVED_392 = 0x00000188, 21373 IMG_FMT_RESERVED_393 = 0x00000189, 21374 IMG_FMT_RESERVED_394 = 0x0000018a, 21375 IMG_FMT_RESERVED_395 = 0x0000018b, 21376 IMG_FMT_RESERVED_396 = 0x0000018c, 21377 IMG_FMT_RESERVED_397 = 0x0000018d, 21378 IMG_FMT_RESERVED_398 = 0x0000018e, 21379 IMG_FMT_RESERVED_399 = 0x0000018f, 21380 IMG_FMT_RESERVED_400 = 0x00000190, 21381 IMG_FMT_RESERVED_401 = 0x00000191, 21382 IMG_FMT_RESERVED_402 = 0x00000192, 21383 IMG_FMT_RESERVED_403 = 0x00000193, 21384 IMG_FMT_RESERVED_404 = 0x00000194, 21385 IMG_FMT_RESERVED_405 = 0x00000195, 21386 IMG_FMT_RESERVED_406 = 0x00000196, 21387 IMG_FMT_RESERVED_407 = 0x00000197, 21388 IMG_FMT_RESERVED_408 = 0x00000198, 21389 IMG_FMT_RESERVED_409 = 0x00000199, 21390 IMG_FMT_RESERVED_410 = 0x0000019a, 21391 IMG_FMT_RESERVED_411 = 0x0000019b, 21392 IMG_FMT_RESERVED_412 = 0x0000019c, 21393 IMG_FMT_RESERVED_413 = 0x0000019d, 21394 IMG_FMT_RESERVED_414 = 0x0000019e, 21395 IMG_FMT_RESERVED_415 = 0x0000019f, 21396 IMG_FMT_RESERVED_416 = 0x000001a0, 21397 IMG_FMT_RESERVED_417 = 0x000001a1, 21398 IMG_FMT_RESERVED_418 = 0x000001a2, 21399 IMG_FMT_RESERVED_419 = 0x000001a3, 21400 IMG_FMT_RESERVED_420 = 0x000001a4, 21401 IMG_FMT_RESERVED_421 = 0x000001a5, 21402 IMG_FMT_RESERVED_422 = 0x000001a6, 21403 IMG_FMT_RESERVED_423 = 0x000001a7, 21404 IMG_FMT_RESERVED_424 = 0x000001a8, 21405 IMG_FMT_RESERVED_425 = 0x000001a9, 21406 IMG_FMT_RESERVED_426 = 0x000001aa, 21407 IMG_FMT_RESERVED_427 = 0x000001ab, 21408 IMG_FMT_RESERVED_428 = 0x000001ac, 21409 IMG_FMT_RESERVED_429 = 0x000001ad, 21410 IMG_FMT_RESERVED_430 = 0x000001ae, 21411 IMG_FMT_RESERVED_431 = 0x000001af, 21412 IMG_FMT_RESERVED_432 = 0x000001b0, 21413 IMG_FMT_RESERVED_433 = 0x000001b1, 21414 IMG_FMT_RESERVED_434 = 0x000001b2, 21415 IMG_FMT_RESERVED_435 = 0x000001b3, 21416 IMG_FMT_RESERVED_436 = 0x000001b4, 21417 IMG_FMT_RESERVED_437 = 0x000001b5, 21418 IMG_FMT_RESERVED_438 = 0x000001b6, 21419 IMG_FMT_RESERVED_439 = 0x000001b7, 21420 IMG_FMT_RESERVED_440 = 0x000001b8, 21421 IMG_FMT_RESERVED_441 = 0x000001b9, 21422 IMG_FMT_RESERVED_442 = 0x000001ba, 21423 IMG_FMT_RESERVED_443 = 0x000001bb, 21424 IMG_FMT_RESERVED_444 = 0x000001bc, 21425 IMG_FMT_RESERVED_445 = 0x000001bd, 21426 IMG_FMT_RESERVED_446 = 0x000001be, 21427 IMG_FMT_RESERVED_447 = 0x000001bf, 21428 IMG_FMT_RESERVED_448 = 0x000001c0, 21429 IMG_FMT_RESERVED_449 = 0x000001c1, 21430 IMG_FMT_RESERVED_450 = 0x000001c2, 21431 IMG_FMT_RESERVED_451 = 0x000001c3, 21432 IMG_FMT_RESERVED_452 = 0x000001c4, 21433 IMG_FMT_RESERVED_453 = 0x000001c5, 21434 IMG_FMT_RESERVED_454 = 0x000001c6, 21435 IMG_FMT_RESERVED_455 = 0x000001c7, 21436 IMG_FMT_RESERVED_456 = 0x000001c8, 21437 IMG_FMT_RESERVED_457 = 0x000001c9, 21438 IMG_FMT_RESERVED_458 = 0x000001ca, 21439 IMG_FMT_RESERVED_459 = 0x000001cb, 21440 IMG_FMT_RESERVED_460 = 0x000001cc, 21441 IMG_FMT_RESERVED_461 = 0x000001cd, 21442 IMG_FMT_RESERVED_462 = 0x000001ce, 21443 IMG_FMT_RESERVED_463 = 0x000001cf, 21444 IMG_FMT_RESERVED_464 = 0x000001d0, 21445 IMG_FMT_RESERVED_465 = 0x000001d1, 21446 IMG_FMT_RESERVED_466 = 0x000001d2, 21447 IMG_FMT_RESERVED_467 = 0x000001d3, 21448 IMG_FMT_RESERVED_468 = 0x000001d4, 21449 IMG_FMT_RESERVED_469 = 0x000001d5, 21450 IMG_FMT_RESERVED_470 = 0x000001d6, 21451 IMG_FMT_RESERVED_471 = 0x000001d7, 21452 IMG_FMT_RESERVED_472 = 0x000001d8, 21453 IMG_FMT_RESERVED_473 = 0x000001d9, 21454 IMG_FMT_RESERVED_474 = 0x000001da, 21455 IMG_FMT_RESERVED_475 = 0x000001db, 21456 IMG_FMT_RESERVED_476 = 0x000001dc, 21457 IMG_FMT_RESERVED_477 = 0x000001dd, 21458 IMG_FMT_RESERVED_478 = 0x000001de, 21459 IMG_FMT_RESERVED_479 = 0x000001df, 21460 IMG_FMT_RESERVED_480 = 0x000001e0, 21461 IMG_FMT_RESERVED_481 = 0x000001e1, 21462 IMG_FMT_RESERVED_482 = 0x000001e2, 21463 IMG_FMT_RESERVED_483 = 0x000001e3, 21464 IMG_FMT_RESERVED_484 = 0x000001e4, 21465 IMG_FMT_RESERVED_485 = 0x000001e5, 21466 IMG_FMT_RESERVED_486 = 0x000001e6, 21467 IMG_FMT_RESERVED_487 = 0x000001e7, 21468 IMG_FMT_RESERVED_488 = 0x000001e8, 21469 IMG_FMT_RESERVED_489 = 0x000001e9, 21470 IMG_FMT_RESERVED_490 = 0x000001ea, 21471 IMG_FMT_RESERVED_491 = 0x000001eb, 21472 IMG_FMT_RESERVED_492 = 0x000001ec, 21473 IMG_FMT_RESERVED_493 = 0x000001ed, 21474 IMG_FMT_RESERVED_494 = 0x000001ee, 21475 IMG_FMT_RESERVED_495 = 0x000001ef, 21476 IMG_FMT_RESERVED_496 = 0x000001f0, 21477 IMG_FMT_RESERVED_497 = 0x000001f1, 21478 IMG_FMT_RESERVED_498 = 0x000001f2, 21479 IMG_FMT_RESERVED_499 = 0x000001f3, 21480 IMG_FMT_RESERVED_500 = 0x000001f4, 21481 IMG_FMT_RESERVED_501 = 0x000001f5, 21482 IMG_FMT_RESERVED_502 = 0x000001f6, 21483 IMG_FMT_RESERVED_503 = 0x000001f7, 21484 IMG_FMT_RESERVED_504 = 0x000001f8, 21485 IMG_FMT_RESERVED_505 = 0x000001f9, 21486 IMG_FMT_RESERVED_506 = 0x000001fa, 21487 IMG_FMT_RESERVED_507 = 0x000001fb, 21488 IMG_FMT_RESERVED_508 = 0x000001fc, 21489 IMG_FMT_RESERVED_509 = 0x000001fd, 21490 IMG_FMT_RESERVED_510 = 0x000001fe, 21491 IMG_FMT_RESERVED_511 = 0x000001ff, 21492 } IMG_FMT; 21493 21494 /* 21495 * BUF_DATA_FORMAT enum 21496 */ 21497 21498 typedef enum BUF_DATA_FORMAT { 21499 BUF_DATA_FORMAT_INVALID = 0x00000000, 21500 BUF_DATA_FORMAT_8 = 0x00000001, 21501 BUF_DATA_FORMAT_16 = 0x00000002, 21502 BUF_DATA_FORMAT_8_8 = 0x00000003, 21503 BUF_DATA_FORMAT_32 = 0x00000004, 21504 BUF_DATA_FORMAT_16_16 = 0x00000005, 21505 BUF_DATA_FORMAT_10_11_11 = 0x00000006, 21506 BUF_DATA_FORMAT_11_11_10 = 0x00000007, 21507 BUF_DATA_FORMAT_10_10_10_2 = 0x00000008, 21508 BUF_DATA_FORMAT_2_10_10_10 = 0x00000009, 21509 BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a, 21510 BUF_DATA_FORMAT_32_32 = 0x0000000b, 21511 BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c, 21512 BUF_DATA_FORMAT_32_32_32 = 0x0000000d, 21513 BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e, 21514 BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f, 21515 } BUF_DATA_FORMAT; 21516 21517 /* 21518 * IMG_DATA_FORMAT enum 21519 */ 21520 21521 typedef enum IMG_DATA_FORMAT { 21522 IMG_DATA_FORMAT_INVALID = 0x00000000, 21523 IMG_DATA_FORMAT_8 = 0x00000001, 21524 IMG_DATA_FORMAT_16 = 0x00000002, 21525 IMG_DATA_FORMAT_8_8 = 0x00000003, 21526 IMG_DATA_FORMAT_32 = 0x00000004, 21527 IMG_DATA_FORMAT_16_16 = 0x00000005, 21528 IMG_DATA_FORMAT_10_11_11 = 0x00000006, 21529 IMG_DATA_FORMAT_11_11_10 = 0x00000007, 21530 IMG_DATA_FORMAT_10_10_10_2 = 0x00000008, 21531 IMG_DATA_FORMAT_2_10_10_10 = 0x00000009, 21532 IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a, 21533 IMG_DATA_FORMAT_32_32 = 0x0000000b, 21534 IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c, 21535 IMG_DATA_FORMAT_32_32_32 = 0x0000000d, 21536 IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e, 21537 IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f, 21538 IMG_DATA_FORMAT_5_6_5 = 0x00000010, 21539 IMG_DATA_FORMAT_1_5_5_5 = 0x00000011, 21540 IMG_DATA_FORMAT_5_5_5_1 = 0x00000012, 21541 IMG_DATA_FORMAT_4_4_4_4 = 0x00000013, 21542 IMG_DATA_FORMAT_8_24 = 0x00000014, 21543 IMG_DATA_FORMAT_24_8 = 0x00000015, 21544 IMG_DATA_FORMAT_X24_8_32 = 0x00000016, 21545 IMG_DATA_FORMAT_RESERVED_23 = 0x00000017, 21546 IMG_DATA_FORMAT_RESERVED_24 = 0x00000018, 21547 IMG_DATA_FORMAT_RESERVED_25 = 0x00000019, 21548 IMG_DATA_FORMAT_RESERVED_26 = 0x0000001a, 21549 IMG_DATA_FORMAT_RESERVED_27 = 0x0000001b, 21550 IMG_DATA_FORMAT_RESERVED_28 = 0x0000001c, 21551 IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d, 21552 IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e, 21553 IMG_DATA_FORMAT_6E4 = 0x0000001f, 21554 IMG_DATA_FORMAT_GB_GR = 0x00000020, 21555 IMG_DATA_FORMAT_BG_RG = 0x00000021, 21556 IMG_DATA_FORMAT_5_9_9_9 = 0x00000022, 21557 IMG_DATA_FORMAT_BC1 = 0x00000023, 21558 IMG_DATA_FORMAT_BC2 = 0x00000024, 21559 IMG_DATA_FORMAT_BC3 = 0x00000025, 21560 IMG_DATA_FORMAT_BC4 = 0x00000026, 21561 IMG_DATA_FORMAT_BC5 = 0x00000027, 21562 IMG_DATA_FORMAT_BC6 = 0x00000028, 21563 IMG_DATA_FORMAT_BC7 = 0x00000029, 21564 IMG_DATA_FORMAT_RESERVED_42 = 0x0000002a, 21565 IMG_DATA_FORMAT_RESERVED_43 = 0x0000002b, 21566 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x0000002c, 21567 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x0000002d, 21568 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x0000002e, 21569 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x0000002f, 21570 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x00000030, 21571 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x00000031, 21572 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x00000032, 21573 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x00000033, 21574 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x00000034, 21575 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x00000035, 21576 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x00000036, 21577 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x00000037, 21578 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x00000038, 21579 IMG_DATA_FORMAT_4_4 = 0x00000039, 21580 IMG_DATA_FORMAT_6_5_5 = 0x0000003a, 21581 IMG_DATA_FORMAT_1 = 0x0000003b, 21582 IMG_DATA_FORMAT_1_REVERSED = 0x0000003c, 21583 IMG_DATA_FORMAT_RESERVED_61 = 0x0000003d, 21584 IMG_DATA_FORMAT_RESERVED_62 = 0x0000003e, 21585 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f, 21586 IMG_DATA_FORMAT_RESERVED_75 = 0x0000004b, 21587 IMG_DATA_FORMAT_MM_8 = 0x0000004c, 21588 IMG_DATA_FORMAT_MM_8_8 = 0x0000004d, 21589 IMG_DATA_FORMAT_MM_8_8_8_8 = 0x0000004e, 21590 IMG_DATA_FORMAT_MM_VYUY8 = 0x0000004f, 21591 IMG_DATA_FORMAT_MM_10_11_11 = 0x00000050, 21592 IMG_DATA_FORMAT_MM_2_10_10_10 = 0x00000051, 21593 IMG_DATA_FORMAT_MM_16_16_16_16 = 0x00000052, 21594 IMG_DATA_FORMAT_MM_10_IN_16 = 0x00000053, 21595 IMG_DATA_FORMAT_MM_10_IN_16_16 = 0x00000054, 21596 IMG_DATA_FORMAT_MM_10_IN_16_16_16_16 = 0x00000055, 21597 IMG_DATA_FORMAT_RESERVED_86 = 0x00000056, 21598 IMG_DATA_FORMAT_RESERVED_87 = 0x00000057, 21599 IMG_DATA_FORMAT_RESERVED_88 = 0x00000058, 21600 IMG_DATA_FORMAT_RESERVED_89 = 0x00000059, 21601 IMG_DATA_FORMAT_RESERVED_90 = 0x0000005a, 21602 IMG_DATA_FORMAT_RESERVED_91 = 0x0000005b, 21603 IMG_DATA_FORMAT_RESERVED_92 = 0x0000005c, 21604 IMG_DATA_FORMAT_RESERVED_93 = 0x0000005d, 21605 IMG_DATA_FORMAT_RESERVED_94 = 0x0000005e, 21606 IMG_DATA_FORMAT_RESERVED_95 = 0x0000005f, 21607 IMG_DATA_FORMAT_RESERVED_96 = 0x00000060, 21608 IMG_DATA_FORMAT_RESERVED_97 = 0x00000061, 21609 IMG_DATA_FORMAT_RESERVED_98 = 0x00000062, 21610 IMG_DATA_FORMAT_RESERVED_99 = 0x00000063, 21611 IMG_DATA_FORMAT_RESERVED_100 = 0x00000064, 21612 IMG_DATA_FORMAT_RESERVED_101 = 0x00000065, 21613 IMG_DATA_FORMAT_RESERVED_102 = 0x00000066, 21614 IMG_DATA_FORMAT_RESERVED_103 = 0x00000067, 21615 IMG_DATA_FORMAT_RESERVED_104 = 0x00000068, 21616 IMG_DATA_FORMAT_RESERVED_105 = 0x00000069, 21617 IMG_DATA_FORMAT_RESERVED_106 = 0x0000006a, 21618 IMG_DATA_FORMAT_RESERVED_107 = 0x0000006b, 21619 IMG_DATA_FORMAT_RESERVED_108 = 0x0000006c, 21620 IMG_DATA_FORMAT_RESERVED_109 = 0x0000006d, 21621 IMG_DATA_FORMAT_RESERVED_110 = 0x0000006e, 21622 IMG_DATA_FORMAT_RESERVED_111 = 0x0000006f, 21623 IMG_DATA_FORMAT_RESERVED_112 = 0x00000070, 21624 IMG_DATA_FORMAT_RESERVED_113 = 0x00000071, 21625 IMG_DATA_FORMAT_RESERVED_114 = 0x00000072, 21626 IMG_DATA_FORMAT_RESERVED_115 = 0x00000073, 21627 IMG_DATA_FORMAT_RESERVED_116 = 0x00000074, 21628 IMG_DATA_FORMAT_RESERVED_117 = 0x00000075, 21629 IMG_DATA_FORMAT_RESERVED_118 = 0x00000076, 21630 IMG_DATA_FORMAT_RESERVED_119 = 0x00000077, 21631 IMG_DATA_FORMAT_RESERVED_120 = 0x00000078, 21632 IMG_DATA_FORMAT_RESERVED_121 = 0x00000079, 21633 IMG_DATA_FORMAT_RESERVED_122 = 0x0000007a, 21634 IMG_DATA_FORMAT_RESERVED_123 = 0x0000007b, 21635 IMG_DATA_FORMAT_RESERVED_124 = 0x0000007c, 21636 IMG_DATA_FORMAT_RESERVED_125 = 0x0000007d, 21637 IMG_DATA_FORMAT_RESERVED_126 = 0x0000007e, 21638 IMG_DATA_FORMAT_RESERVED_127 = 0x0000007f, 21639 } IMG_DATA_FORMAT; 21640 21641 /* 21642 * BUF_NUM_FORMAT enum 21643 */ 21644 21645 typedef enum BUF_NUM_FORMAT { 21646 BUF_NUM_FORMAT_UNORM = 0x00000000, 21647 BUF_NUM_FORMAT_SNORM = 0x00000001, 21648 BUF_NUM_FORMAT_USCALED = 0x00000002, 21649 BUF_NUM_FORMAT_SSCALED = 0x00000003, 21650 BUF_NUM_FORMAT_UINT = 0x00000004, 21651 BUF_NUM_FORMAT_SINT = 0x00000005, 21652 BUF_NUM_FORMAT_SNORM_NZ = 0x00000006, 21653 BUF_NUM_FORMAT_FLOAT = 0x00000007, 21654 } BUF_NUM_FORMAT; 21655 21656 /* 21657 * IMG_NUM_FORMAT enum 21658 */ 21659 21660 typedef enum IMG_NUM_FORMAT { 21661 IMG_NUM_FORMAT_UNORM = 0x00000000, 21662 IMG_NUM_FORMAT_SNORM = 0x00000001, 21663 IMG_NUM_FORMAT_USCALED = 0x00000002, 21664 IMG_NUM_FORMAT_SSCALED = 0x00000003, 21665 IMG_NUM_FORMAT_UINT = 0x00000004, 21666 IMG_NUM_FORMAT_SINT = 0x00000005, 21667 IMG_NUM_FORMAT_SNORM_NZ = 0x00000006, 21668 IMG_NUM_FORMAT_FLOAT = 0x00000007, 21669 IMG_NUM_FORMAT_RESERVED_8 = 0x00000008, 21670 IMG_NUM_FORMAT_SRGB = 0x00000009, 21671 IMG_NUM_FORMAT_UBNORM = 0x0000000a, 21672 IMG_NUM_FORMAT_UBNORM_NZ = 0x0000000b, 21673 IMG_NUM_FORMAT_UBINT = 0x0000000c, 21674 IMG_NUM_FORMAT_UBSCALED = 0x0000000d, 21675 IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e, 21676 IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f, 21677 } IMG_NUM_FORMAT; 21678 21679 /******************************************************* 21680 * IH Enums 21681 *******************************************************/ 21682 21683 /* 21684 * IH_PERF_SEL enum 21685 */ 21686 21687 typedef enum IH_PERF_SEL { 21688 IH_PERF_SEL_CYCLE = 0x00000000, 21689 IH_PERF_SEL_IDLE = 0x00000001, 21690 IH_PERF_SEL_INPUT_IDLE = 0x00000002, 21691 IH_PERF_SEL_BUFFER_IDLE = 0x00000003, 21692 IH_PERF_SEL_RB0_FULL = 0x00000004, 21693 IH_PERF_SEL_RB0_OVERFLOW = 0x00000005, 21694 IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006, 21695 IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007, 21696 IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008, 21697 IH_PERF_SEL_MC_WR_IDLE = 0x00000009, 21698 IH_PERF_SEL_MC_WR_COUNT = 0x0000000a, 21699 IH_PERF_SEL_MC_WR_STALL = 0x0000000b, 21700 IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c, 21701 IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d, 21702 IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e, 21703 IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f, 21704 IH_PERF_SEL_RB1_FULL = 0x00000010, 21705 IH_PERF_SEL_RB1_OVERFLOW = 0x00000011, 21706 IH_PERF_SEL_COOKIE_REC_ERROR = 0x00000012, 21707 IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013, 21708 IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014, 21709 IH_PERF_SEL_RB2_FULL = 0x00000015, 21710 IH_PERF_SEL_RB2_OVERFLOW = 0x00000016, 21711 IH_PERF_SEL_CLIENT_CREDIT_ERROR = 0x00000017, 21712 IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018, 21713 IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019, 21714 IH_PERF_SEL_STORM_CLIENT_INT_DROP = 0x0000001a, 21715 IH_PERF_SEL_SELF_IV_VALID = 0x0000001b, 21716 IH_PERF_SEL_BUFFER_FIFO_FULL = 0x0000001c, 21717 IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001d, 21718 IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001e, 21719 IH_PERF_SEL_RB0_FULL_VF2 = 0x0000001f, 21720 IH_PERF_SEL_RB0_FULL_VF3 = 0x00000020, 21721 IH_PERF_SEL_RB0_FULL_VF4 = 0x00000021, 21722 IH_PERF_SEL_RB0_FULL_VF5 = 0x00000022, 21723 IH_PERF_SEL_RB0_FULL_VF6 = 0x00000023, 21724 IH_PERF_SEL_RB0_FULL_VF7 = 0x00000024, 21725 IH_PERF_SEL_RB0_FULL_VF8 = 0x00000025, 21726 IH_PERF_SEL_RB0_FULL_VF9 = 0x00000026, 21727 IH_PERF_SEL_RB0_FULL_VF10 = 0x00000027, 21728 IH_PERF_SEL_RB0_FULL_VF11 = 0x00000028, 21729 IH_PERF_SEL_RB0_FULL_VF12 = 0x00000029, 21730 IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002a, 21731 IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002b, 21732 IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002c, 21733 IH_PERF_SEL_RB0_FULL_VF16 = 0x0000002d, 21734 IH_PERF_SEL_RB0_FULL_VF17 = 0x0000002e, 21735 IH_PERF_SEL_RB0_FULL_VF18 = 0x0000002f, 21736 IH_PERF_SEL_RB0_FULL_VF19 = 0x00000030, 21737 IH_PERF_SEL_RB0_FULL_VF20 = 0x00000031, 21738 IH_PERF_SEL_RB0_FULL_VF21 = 0x00000032, 21739 IH_PERF_SEL_RB0_FULL_VF22 = 0x00000033, 21740 IH_PERF_SEL_RB0_FULL_VF23 = 0x00000034, 21741 IH_PERF_SEL_RB0_FULL_VF24 = 0x00000035, 21742 IH_PERF_SEL_RB0_FULL_VF25 = 0x00000036, 21743 IH_PERF_SEL_RB0_FULL_VF26 = 0x00000037, 21744 IH_PERF_SEL_RB0_FULL_VF27 = 0x00000038, 21745 IH_PERF_SEL_RB0_FULL_VF28 = 0x00000039, 21746 IH_PERF_SEL_RB0_FULL_VF29 = 0x0000003a, 21747 IH_PERF_SEL_RB0_FULL_VF30 = 0x0000003b, 21748 IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000003c, 21749 IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000003d, 21750 IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x0000003e, 21751 IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x0000003f, 21752 IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000040, 21753 IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000041, 21754 IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000042, 21755 IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000043, 21756 IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000044, 21757 IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000045, 21758 IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000046, 21759 IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000047, 21760 IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x00000048, 21761 IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x00000049, 21762 IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000004a, 21763 IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000004b, 21764 IH_PERF_SEL_RB0_OVERFLOW_VF16 = 0x0000004c, 21765 IH_PERF_SEL_RB0_OVERFLOW_VF17 = 0x0000004d, 21766 IH_PERF_SEL_RB0_OVERFLOW_VF18 = 0x0000004e, 21767 IH_PERF_SEL_RB0_OVERFLOW_VF19 = 0x0000004f, 21768 IH_PERF_SEL_RB0_OVERFLOW_VF20 = 0x00000050, 21769 IH_PERF_SEL_RB0_OVERFLOW_VF21 = 0x00000051, 21770 IH_PERF_SEL_RB0_OVERFLOW_VF22 = 0x00000052, 21771 IH_PERF_SEL_RB0_OVERFLOW_VF23 = 0x00000053, 21772 IH_PERF_SEL_RB0_OVERFLOW_VF24 = 0x00000054, 21773 IH_PERF_SEL_RB0_OVERFLOW_VF25 = 0x00000055, 21774 IH_PERF_SEL_RB0_OVERFLOW_VF26 = 0x00000056, 21775 IH_PERF_SEL_RB0_OVERFLOW_VF27 = 0x00000057, 21776 IH_PERF_SEL_RB0_OVERFLOW_VF28 = 0x00000058, 21777 IH_PERF_SEL_RB0_OVERFLOW_VF29 = 0x00000059, 21778 IH_PERF_SEL_RB0_OVERFLOW_VF30 = 0x0000005a, 21779 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000005b, 21780 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000005c, 21781 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x0000005d, 21782 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x0000005e, 21783 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x0000005f, 21784 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000060, 21785 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000061, 21786 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000062, 21787 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000063, 21788 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000064, 21789 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000065, 21790 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000066, 21791 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x00000067, 21792 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x00000068, 21793 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x00000069, 21794 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000006a, 21795 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16 = 0x0000006b, 21796 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17 = 0x0000006c, 21797 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18 = 0x0000006d, 21798 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19 = 0x0000006e, 21799 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20 = 0x0000006f, 21800 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21 = 0x00000070, 21801 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22 = 0x00000071, 21802 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23 = 0x00000072, 21803 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24 = 0x00000073, 21804 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25 = 0x00000074, 21805 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26 = 0x00000075, 21806 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27 = 0x00000076, 21807 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28 = 0x00000077, 21808 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29 = 0x00000078, 21809 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30 = 0x00000079, 21810 IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000007a, 21811 IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000007b, 21812 IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x0000007c, 21813 IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x0000007d, 21814 IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x0000007e, 21815 IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x0000007f, 21816 IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000080, 21817 IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000081, 21818 IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000082, 21819 IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000083, 21820 IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000084, 21821 IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000085, 21822 IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x00000086, 21823 IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x00000087, 21824 IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x00000088, 21825 IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x00000089, 21826 IH_PERF_SEL_RB0_WPTR_WRAP_VF16 = 0x0000008a, 21827 IH_PERF_SEL_RB0_WPTR_WRAP_VF17 = 0x0000008b, 21828 IH_PERF_SEL_RB0_WPTR_WRAP_VF18 = 0x0000008c, 21829 IH_PERF_SEL_RB0_WPTR_WRAP_VF19 = 0x0000008d, 21830 IH_PERF_SEL_RB0_WPTR_WRAP_VF20 = 0x0000008e, 21831 IH_PERF_SEL_RB0_WPTR_WRAP_VF21 = 0x0000008f, 21832 IH_PERF_SEL_RB0_WPTR_WRAP_VF22 = 0x00000090, 21833 IH_PERF_SEL_RB0_WPTR_WRAP_VF23 = 0x00000091, 21834 IH_PERF_SEL_RB0_WPTR_WRAP_VF24 = 0x00000092, 21835 IH_PERF_SEL_RB0_WPTR_WRAP_VF25 = 0x00000093, 21836 IH_PERF_SEL_RB0_WPTR_WRAP_VF26 = 0x00000094, 21837 IH_PERF_SEL_RB0_WPTR_WRAP_VF27 = 0x00000095, 21838 IH_PERF_SEL_RB0_WPTR_WRAP_VF28 = 0x00000096, 21839 IH_PERF_SEL_RB0_WPTR_WRAP_VF29 = 0x00000097, 21840 IH_PERF_SEL_RB0_WPTR_WRAP_VF30 = 0x00000098, 21841 IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x00000099, 21842 IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000009a, 21843 IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x0000009b, 21844 IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x0000009c, 21845 IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x0000009d, 21846 IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x0000009e, 21847 IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x0000009f, 21848 IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x000000a0, 21849 IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x000000a1, 21850 IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x000000a2, 21851 IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x000000a3, 21852 IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x000000a4, 21853 IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x000000a5, 21854 IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x000000a6, 21855 IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x000000a7, 21856 IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x000000a8, 21857 IH_PERF_SEL_RB0_RPTR_WRAP_VF16 = 0x000000a9, 21858 IH_PERF_SEL_RB0_RPTR_WRAP_VF17 = 0x000000aa, 21859 IH_PERF_SEL_RB0_RPTR_WRAP_VF18 = 0x000000ab, 21860 IH_PERF_SEL_RB0_RPTR_WRAP_VF19 = 0x000000ac, 21861 IH_PERF_SEL_RB0_RPTR_WRAP_VF20 = 0x000000ad, 21862 IH_PERF_SEL_RB0_RPTR_WRAP_VF21 = 0x000000ae, 21863 IH_PERF_SEL_RB0_RPTR_WRAP_VF22 = 0x000000af, 21864 IH_PERF_SEL_RB0_RPTR_WRAP_VF23 = 0x000000b0, 21865 IH_PERF_SEL_RB0_RPTR_WRAP_VF24 = 0x000000b1, 21866 IH_PERF_SEL_RB0_RPTR_WRAP_VF25 = 0x000000b2, 21867 IH_PERF_SEL_RB0_RPTR_WRAP_VF26 = 0x000000b3, 21868 IH_PERF_SEL_RB0_RPTR_WRAP_VF27 = 0x000000b4, 21869 IH_PERF_SEL_RB0_RPTR_WRAP_VF28 = 0x000000b5, 21870 IH_PERF_SEL_RB0_RPTR_WRAP_VF29 = 0x000000b6, 21871 IH_PERF_SEL_RB0_RPTR_WRAP_VF30 = 0x000000b7, 21872 IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x000000b8, 21873 IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x000000b9, 21874 IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x000000ba, 21875 IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x000000bb, 21876 IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x000000bc, 21877 IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x000000bd, 21878 IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x000000be, 21879 IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x000000bf, 21880 IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x000000c0, 21881 IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x000000c1, 21882 IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x000000c2, 21883 IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x000000c3, 21884 IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x000000c4, 21885 IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x000000c5, 21886 IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x000000c6, 21887 IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x000000c7, 21888 IH_PERF_SEL_BIF_LINE0_RISING_VF16 = 0x000000c8, 21889 IH_PERF_SEL_BIF_LINE0_RISING_VF17 = 0x000000c9, 21890 IH_PERF_SEL_BIF_LINE0_RISING_VF18 = 0x000000ca, 21891 IH_PERF_SEL_BIF_LINE0_RISING_VF19 = 0x000000cb, 21892 IH_PERF_SEL_BIF_LINE0_RISING_VF20 = 0x000000cc, 21893 IH_PERF_SEL_BIF_LINE0_RISING_VF21 = 0x000000cd, 21894 IH_PERF_SEL_BIF_LINE0_RISING_VF22 = 0x000000ce, 21895 IH_PERF_SEL_BIF_LINE0_RISING_VF23 = 0x000000cf, 21896 IH_PERF_SEL_BIF_LINE0_RISING_VF24 = 0x000000d0, 21897 IH_PERF_SEL_BIF_LINE0_RISING_VF25 = 0x000000d1, 21898 IH_PERF_SEL_BIF_LINE0_RISING_VF26 = 0x000000d2, 21899 IH_PERF_SEL_BIF_LINE0_RISING_VF27 = 0x000000d3, 21900 IH_PERF_SEL_BIF_LINE0_RISING_VF28 = 0x000000d4, 21901 IH_PERF_SEL_BIF_LINE0_RISING_VF29 = 0x000000d5, 21902 IH_PERF_SEL_BIF_LINE0_RISING_VF30 = 0x000000d6, 21903 IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x000000d7, 21904 IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x000000d8, 21905 IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x000000d9, 21906 IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x000000da, 21907 IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x000000db, 21908 IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x000000dc, 21909 IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x000000dd, 21910 IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x000000de, 21911 IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x000000df, 21912 IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x000000e0, 21913 IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x000000e1, 21914 IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x000000e2, 21915 IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x000000e3, 21916 IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x000000e4, 21917 IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x000000e5, 21918 IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x000000e6, 21919 IH_PERF_SEL_BIF_LINE0_FALLING_VF16 = 0x000000e7, 21920 IH_PERF_SEL_BIF_LINE0_FALLING_VF17 = 0x000000e8, 21921 IH_PERF_SEL_BIF_LINE0_FALLING_VF18 = 0x000000e9, 21922 IH_PERF_SEL_BIF_LINE0_FALLING_VF19 = 0x000000ea, 21923 IH_PERF_SEL_BIF_LINE0_FALLING_VF20 = 0x000000eb, 21924 IH_PERF_SEL_BIF_LINE0_FALLING_VF21 = 0x000000ec, 21925 IH_PERF_SEL_BIF_LINE0_FALLING_VF22 = 0x000000ed, 21926 IH_PERF_SEL_BIF_LINE0_FALLING_VF23 = 0x000000ee, 21927 IH_PERF_SEL_BIF_LINE0_FALLING_VF24 = 0x000000ef, 21928 IH_PERF_SEL_BIF_LINE0_FALLING_VF25 = 0x000000f0, 21929 IH_PERF_SEL_BIF_LINE0_FALLING_VF26 = 0x000000f1, 21930 IH_PERF_SEL_BIF_LINE0_FALLING_VF27 = 0x000000f2, 21931 IH_PERF_SEL_BIF_LINE0_FALLING_VF28 = 0x000000f3, 21932 IH_PERF_SEL_BIF_LINE0_FALLING_VF29 = 0x000000f4, 21933 IH_PERF_SEL_BIF_LINE0_FALLING_VF30 = 0x000000f5, 21934 IH_PERF_SEL_CLIENT0_INT = 0x000000f6, 21935 IH_PERF_SEL_CLIENT1_INT = 0x000000f7, 21936 IH_PERF_SEL_CLIENT2_INT = 0x000000f8, 21937 IH_PERF_SEL_CLIENT3_INT = 0x000000f9, 21938 IH_PERF_SEL_CLIENT4_INT = 0x000000fa, 21939 IH_PERF_SEL_CLIENT5_INT = 0x000000fb, 21940 IH_PERF_SEL_CLIENT6_INT = 0x000000fc, 21941 IH_PERF_SEL_CLIENT7_INT = 0x000000fd, 21942 IH_PERF_SEL_CLIENT8_INT = 0x000000fe, 21943 IH_PERF_SEL_CLIENT9_INT = 0x000000ff, 21944 IH_PERF_SEL_CLIENT10_INT = 0x00000100, 21945 IH_PERF_SEL_CLIENT11_INT = 0x00000101, 21946 IH_PERF_SEL_CLIENT12_INT = 0x00000102, 21947 IH_PERF_SEL_CLIENT13_INT = 0x00000103, 21948 IH_PERF_SEL_CLIENT14_INT = 0x00000104, 21949 IH_PERF_SEL_CLIENT15_INT = 0x00000105, 21950 IH_PERF_SEL_CLIENT16_INT = 0x00000106, 21951 IH_PERF_SEL_CLIENT17_INT = 0x00000107, 21952 IH_PERF_SEL_CLIENT18_INT = 0x00000108, 21953 IH_PERF_SEL_CLIENT19_INT = 0x00000109, 21954 IH_PERF_SEL_CLIENT20_INT = 0x0000010a, 21955 IH_PERF_SEL_CLIENT21_INT = 0x0000010b, 21956 IH_PERF_SEL_CLIENT22_INT = 0x0000010c, 21957 IH_PERF_SEL_CLIENT23_INT = 0x0000010d, 21958 IH_PERF_SEL_CLIENT24_INT = 0x0000010e, 21959 IH_PERF_SEL_CLIENT25_INT = 0x0000010f, 21960 IH_PERF_SEL_CLIENT26_INT = 0x00000110, 21961 IH_PERF_SEL_CLIENT27_INT = 0x00000111, 21962 IH_PERF_SEL_CLIENT28_INT = 0x00000112, 21963 IH_PERF_SEL_CLIENT29_INT = 0x00000113, 21964 IH_PERF_SEL_CLIENT30_INT = 0x00000114, 21965 IH_PERF_SEL_CLIENT31_INT = 0x00000115, 21966 IH_PERF_SEL_RB1_FULL_VF0 = 0x00000116, 21967 IH_PERF_SEL_RB1_FULL_VF1 = 0x00000117, 21968 IH_PERF_SEL_RB1_FULL_VF2 = 0x00000118, 21969 IH_PERF_SEL_RB1_FULL_VF3 = 0x00000119, 21970 IH_PERF_SEL_RB1_FULL_VF4 = 0x0000011a, 21971 IH_PERF_SEL_RB1_FULL_VF5 = 0x0000011b, 21972 IH_PERF_SEL_RB1_FULL_VF6 = 0x0000011c, 21973 IH_PERF_SEL_RB1_FULL_VF7 = 0x0000011d, 21974 IH_PERF_SEL_RB1_FULL_VF8 = 0x0000011e, 21975 IH_PERF_SEL_RB1_FULL_VF9 = 0x0000011f, 21976 IH_PERF_SEL_RB1_FULL_VF10 = 0x00000120, 21977 IH_PERF_SEL_RB1_FULL_VF11 = 0x00000121, 21978 IH_PERF_SEL_RB1_FULL_VF12 = 0x00000122, 21979 IH_PERF_SEL_RB1_FULL_VF13 = 0x00000123, 21980 IH_PERF_SEL_RB1_FULL_VF14 = 0x00000124, 21981 IH_PERF_SEL_RB1_FULL_VF15 = 0x00000125, 21982 IH_PERF_SEL_RB1_FULL_VF16 = 0x00000126, 21983 IH_PERF_SEL_RB1_FULL_VF17 = 0x00000127, 21984 IH_PERF_SEL_RB1_FULL_VF18 = 0x00000128, 21985 IH_PERF_SEL_RB1_FULL_VF19 = 0x00000129, 21986 IH_PERF_SEL_RB1_FULL_VF20 = 0x0000012a, 21987 IH_PERF_SEL_RB1_FULL_VF21 = 0x0000012b, 21988 IH_PERF_SEL_RB1_FULL_VF22 = 0x0000012c, 21989 IH_PERF_SEL_RB1_FULL_VF23 = 0x0000012d, 21990 IH_PERF_SEL_RB1_FULL_VF24 = 0x0000012e, 21991 IH_PERF_SEL_RB1_FULL_VF25 = 0x0000012f, 21992 IH_PERF_SEL_RB1_FULL_VF26 = 0x00000130, 21993 IH_PERF_SEL_RB1_FULL_VF27 = 0x00000131, 21994 IH_PERF_SEL_RB1_FULL_VF28 = 0x00000132, 21995 IH_PERF_SEL_RB1_FULL_VF29 = 0x00000133, 21996 IH_PERF_SEL_RB1_FULL_VF30 = 0x00000134, 21997 IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x00000135, 21998 IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x00000136, 21999 IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x00000137, 22000 IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x00000138, 22001 IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x00000139, 22002 IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x0000013a, 22003 IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x0000013b, 22004 IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x0000013c, 22005 IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x0000013d, 22006 IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x0000013e, 22007 IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x0000013f, 22008 IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x00000140, 22009 IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x00000141, 22010 IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x00000142, 22011 IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x00000143, 22012 IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x00000144, 22013 IH_PERF_SEL_RB1_OVERFLOW_VF16 = 0x00000145, 22014 IH_PERF_SEL_RB1_OVERFLOW_VF17 = 0x00000146, 22015 IH_PERF_SEL_RB1_OVERFLOW_VF18 = 0x00000147, 22016 IH_PERF_SEL_RB1_OVERFLOW_VF19 = 0x00000148, 22017 IH_PERF_SEL_RB1_OVERFLOW_VF20 = 0x00000149, 22018 IH_PERF_SEL_RB1_OVERFLOW_VF21 = 0x0000014a, 22019 IH_PERF_SEL_RB1_OVERFLOW_VF22 = 0x0000014b, 22020 IH_PERF_SEL_RB1_OVERFLOW_VF23 = 0x0000014c, 22021 IH_PERF_SEL_RB1_OVERFLOW_VF24 = 0x0000014d, 22022 IH_PERF_SEL_RB1_OVERFLOW_VF25 = 0x0000014e, 22023 IH_PERF_SEL_RB1_OVERFLOW_VF26 = 0x0000014f, 22024 IH_PERF_SEL_RB1_OVERFLOW_VF27 = 0x00000150, 22025 IH_PERF_SEL_RB1_OVERFLOW_VF28 = 0x00000151, 22026 IH_PERF_SEL_RB1_OVERFLOW_VF29 = 0x00000152, 22027 IH_PERF_SEL_RB1_OVERFLOW_VF30 = 0x00000153, 22028 IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x00000154, 22029 IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x00000155, 22030 IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x00000156, 22031 IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x00000157, 22032 IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x00000158, 22033 IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x00000159, 22034 IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x0000015a, 22035 IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x0000015b, 22036 IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x0000015c, 22037 IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x0000015d, 22038 IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x0000015e, 22039 IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x0000015f, 22040 IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x00000160, 22041 IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x00000161, 22042 IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x00000162, 22043 IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x00000163, 22044 IH_PERF_SEL_RB1_WPTR_WRAP_VF16 = 0x00000164, 22045 IH_PERF_SEL_RB1_WPTR_WRAP_VF17 = 0x00000165, 22046 IH_PERF_SEL_RB1_WPTR_WRAP_VF18 = 0x00000166, 22047 IH_PERF_SEL_RB1_WPTR_WRAP_VF19 = 0x00000167, 22048 IH_PERF_SEL_RB1_WPTR_WRAP_VF20 = 0x00000168, 22049 IH_PERF_SEL_RB1_WPTR_WRAP_VF21 = 0x00000169, 22050 IH_PERF_SEL_RB1_WPTR_WRAP_VF22 = 0x0000016a, 22051 IH_PERF_SEL_RB1_WPTR_WRAP_VF23 = 0x0000016b, 22052 IH_PERF_SEL_RB1_WPTR_WRAP_VF24 = 0x0000016c, 22053 IH_PERF_SEL_RB1_WPTR_WRAP_VF25 = 0x0000016d, 22054 IH_PERF_SEL_RB1_WPTR_WRAP_VF26 = 0x0000016e, 22055 IH_PERF_SEL_RB1_WPTR_WRAP_VF27 = 0x0000016f, 22056 IH_PERF_SEL_RB1_WPTR_WRAP_VF28 = 0x00000170, 22057 IH_PERF_SEL_RB1_WPTR_WRAP_VF29 = 0x00000171, 22058 IH_PERF_SEL_RB1_WPTR_WRAP_VF30 = 0x00000172, 22059 IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x00000173, 22060 IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x00000174, 22061 IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x00000175, 22062 IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x00000176, 22063 IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x00000177, 22064 IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x00000178, 22065 IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x00000179, 22066 IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x0000017a, 22067 IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x0000017b, 22068 IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x0000017c, 22069 IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x0000017d, 22070 IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x0000017e, 22071 IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x0000017f, 22072 IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x00000180, 22073 IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x00000181, 22074 IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x00000182, 22075 IH_PERF_SEL_RB1_RPTR_WRAP_VF16 = 0x00000183, 22076 IH_PERF_SEL_RB1_RPTR_WRAP_VF17 = 0x00000184, 22077 IH_PERF_SEL_RB1_RPTR_WRAP_VF18 = 0x00000185, 22078 IH_PERF_SEL_RB1_RPTR_WRAP_VF19 = 0x00000186, 22079 IH_PERF_SEL_RB1_RPTR_WRAP_VF20 = 0x00000187, 22080 IH_PERF_SEL_RB1_RPTR_WRAP_VF21 = 0x00000188, 22081 IH_PERF_SEL_RB1_RPTR_WRAP_VF22 = 0x00000189, 22082 IH_PERF_SEL_RB1_RPTR_WRAP_VF23 = 0x0000018a, 22083 IH_PERF_SEL_RB1_RPTR_WRAP_VF24 = 0x0000018b, 22084 IH_PERF_SEL_RB1_RPTR_WRAP_VF25 = 0x0000018c, 22085 IH_PERF_SEL_RB1_RPTR_WRAP_VF26 = 0x0000018d, 22086 IH_PERF_SEL_RB1_RPTR_WRAP_VF27 = 0x0000018e, 22087 IH_PERF_SEL_RB1_RPTR_WRAP_VF28 = 0x0000018f, 22088 IH_PERF_SEL_RB1_RPTR_WRAP_VF29 = 0x00000190, 22089 IH_PERF_SEL_RB1_RPTR_WRAP_VF30 = 0x00000191, 22090 IH_PERF_SEL_RB2_FULL_VF0 = 0x00000192, 22091 IH_PERF_SEL_RB2_FULL_VF1 = 0x00000193, 22092 IH_PERF_SEL_RB2_FULL_VF2 = 0x00000194, 22093 IH_PERF_SEL_RB2_FULL_VF3 = 0x00000195, 22094 IH_PERF_SEL_RB2_FULL_VF4 = 0x00000196, 22095 IH_PERF_SEL_RB2_FULL_VF5 = 0x00000197, 22096 IH_PERF_SEL_RB2_FULL_VF6 = 0x00000198, 22097 IH_PERF_SEL_RB2_FULL_VF7 = 0x00000199, 22098 IH_PERF_SEL_RB2_FULL_VF8 = 0x0000019a, 22099 IH_PERF_SEL_RB2_FULL_VF9 = 0x0000019b, 22100 IH_PERF_SEL_RB2_FULL_VF10 = 0x0000019c, 22101 IH_PERF_SEL_RB2_FULL_VF11 = 0x0000019d, 22102 IH_PERF_SEL_RB2_FULL_VF12 = 0x0000019e, 22103 IH_PERF_SEL_RB2_FULL_VF13 = 0x0000019f, 22104 IH_PERF_SEL_RB2_FULL_VF14 = 0x000001a0, 22105 IH_PERF_SEL_RB2_FULL_VF15 = 0x000001a1, 22106 IH_PERF_SEL_RB2_FULL_VF16 = 0x000001a2, 22107 IH_PERF_SEL_RB2_FULL_VF17 = 0x000001a3, 22108 IH_PERF_SEL_RB2_FULL_VF18 = 0x000001a4, 22109 IH_PERF_SEL_RB2_FULL_VF19 = 0x000001a5, 22110 IH_PERF_SEL_RB2_FULL_VF20 = 0x000001a6, 22111 IH_PERF_SEL_RB2_FULL_VF21 = 0x000001a7, 22112 IH_PERF_SEL_RB2_FULL_VF22 = 0x000001a8, 22113 IH_PERF_SEL_RB2_FULL_VF23 = 0x000001a9, 22114 IH_PERF_SEL_RB2_FULL_VF24 = 0x000001aa, 22115 IH_PERF_SEL_RB2_FULL_VF25 = 0x000001ab, 22116 IH_PERF_SEL_RB2_FULL_VF26 = 0x000001ac, 22117 IH_PERF_SEL_RB2_FULL_VF27 = 0x000001ad, 22118 IH_PERF_SEL_RB2_FULL_VF28 = 0x000001ae, 22119 IH_PERF_SEL_RB2_FULL_VF29 = 0x000001af, 22120 IH_PERF_SEL_RB2_FULL_VF30 = 0x000001b0, 22121 IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x000001b1, 22122 IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x000001b2, 22123 IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x000001b3, 22124 IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x000001b4, 22125 IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x000001b5, 22126 IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x000001b6, 22127 IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x000001b7, 22128 IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x000001b8, 22129 IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x000001b9, 22130 IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x000001ba, 22131 IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x000001bb, 22132 IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x000001bc, 22133 IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x000001bd, 22134 IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x000001be, 22135 IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x000001bf, 22136 IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x000001c0, 22137 IH_PERF_SEL_RB2_OVERFLOW_VF16 = 0x000001c1, 22138 IH_PERF_SEL_RB2_OVERFLOW_VF17 = 0x000001c2, 22139 IH_PERF_SEL_RB2_OVERFLOW_VF18 = 0x000001c3, 22140 IH_PERF_SEL_RB2_OVERFLOW_VF19 = 0x000001c4, 22141 IH_PERF_SEL_RB2_OVERFLOW_VF20 = 0x000001c5, 22142 IH_PERF_SEL_RB2_OVERFLOW_VF21 = 0x000001c6, 22143 IH_PERF_SEL_RB2_OVERFLOW_VF22 = 0x000001c7, 22144 IH_PERF_SEL_RB2_OVERFLOW_VF23 = 0x000001c8, 22145 IH_PERF_SEL_RB2_OVERFLOW_VF24 = 0x000001c9, 22146 IH_PERF_SEL_RB2_OVERFLOW_VF25 = 0x000001ca, 22147 IH_PERF_SEL_RB2_OVERFLOW_VF26 = 0x000001cb, 22148 IH_PERF_SEL_RB2_OVERFLOW_VF27 = 0x000001cc, 22149 IH_PERF_SEL_RB2_OVERFLOW_VF28 = 0x000001cd, 22150 IH_PERF_SEL_RB2_OVERFLOW_VF29 = 0x000001ce, 22151 IH_PERF_SEL_RB2_OVERFLOW_VF30 = 0x000001cf, 22152 IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x000001d0, 22153 IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x000001d1, 22154 IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x000001d2, 22155 IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x000001d3, 22156 IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x000001d4, 22157 IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x000001d5, 22158 IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x000001d6, 22159 IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x000001d7, 22160 IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x000001d8, 22161 IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x000001d9, 22162 IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x000001da, 22163 IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x000001db, 22164 IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x000001dc, 22165 IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x000001dd, 22166 IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x000001de, 22167 IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x000001df, 22168 IH_PERF_SEL_RB2_WPTR_WRAP_VF16 = 0x000001e0, 22169 IH_PERF_SEL_RB2_WPTR_WRAP_VF17 = 0x000001e1, 22170 IH_PERF_SEL_RB2_WPTR_WRAP_VF18 = 0x000001e2, 22171 IH_PERF_SEL_RB2_WPTR_WRAP_VF19 = 0x000001e3, 22172 IH_PERF_SEL_RB2_WPTR_WRAP_VF20 = 0x000001e4, 22173 IH_PERF_SEL_RB2_WPTR_WRAP_VF21 = 0x000001e5, 22174 IH_PERF_SEL_RB2_WPTR_WRAP_VF22 = 0x000001e6, 22175 IH_PERF_SEL_RB2_WPTR_WRAP_VF23 = 0x000001e7, 22176 IH_PERF_SEL_RB2_WPTR_WRAP_VF24 = 0x000001e8, 22177 IH_PERF_SEL_RB2_WPTR_WRAP_VF25 = 0x000001e9, 22178 IH_PERF_SEL_RB2_WPTR_WRAP_VF26 = 0x000001ea, 22179 IH_PERF_SEL_RB2_WPTR_WRAP_VF27 = 0x000001eb, 22180 IH_PERF_SEL_RB2_WPTR_WRAP_VF28 = 0x000001ec, 22181 IH_PERF_SEL_RB2_WPTR_WRAP_VF29 = 0x000001ed, 22182 IH_PERF_SEL_RB2_WPTR_WRAP_VF30 = 0x000001ee, 22183 IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x000001ef, 22184 IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x000001f0, 22185 IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x000001f1, 22186 IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x000001f2, 22187 IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x000001f3, 22188 IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x000001f4, 22189 IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x000001f5, 22190 IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x000001f6, 22191 IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x000001f7, 22192 IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x000001f8, 22193 IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x000001f9, 22194 IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x000001fa, 22195 IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x000001fb, 22196 IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x000001fc, 22197 IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x000001fd, 22198 IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x000001fe, 22199 IH_PERF_SEL_RB2_RPTR_WRAP_VF16 = 0x000001ff, 22200 IH_PERF_SEL_RB2_RPTR_WRAP_VF17 = 0x00000200, 22201 IH_PERF_SEL_RB2_RPTR_WRAP_VF18 = 0x00000201, 22202 IH_PERF_SEL_RB2_RPTR_WRAP_VF19 = 0x00000202, 22203 IH_PERF_SEL_RB2_RPTR_WRAP_VF20 = 0x00000203, 22204 IH_PERF_SEL_RB2_RPTR_WRAP_VF21 = 0x00000204, 22205 IH_PERF_SEL_RB2_RPTR_WRAP_VF22 = 0x00000205, 22206 IH_PERF_SEL_RB2_RPTR_WRAP_VF23 = 0x00000206, 22207 IH_PERF_SEL_RB2_RPTR_WRAP_VF24 = 0x00000207, 22208 IH_PERF_SEL_RB2_RPTR_WRAP_VF25 = 0x00000208, 22209 IH_PERF_SEL_RB2_RPTR_WRAP_VF26 = 0x00000209, 22210 IH_PERF_SEL_RB2_RPTR_WRAP_VF27 = 0x0000020a, 22211 IH_PERF_SEL_RB2_RPTR_WRAP_VF28 = 0x0000020b, 22212 IH_PERF_SEL_RB2_RPTR_WRAP_VF29 = 0x0000020c, 22213 IH_PERF_SEL_RB2_RPTR_WRAP_VF30 = 0x0000020d, 22214 IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 0x0000020e, 22215 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 0x0000020f, 22216 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 0x00000210, 22217 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 0x00000211, 22218 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 0x00000212, 22219 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 0x00000213, 22220 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 0x00000214, 22221 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 0x00000215, 22222 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 0x00000216, 22223 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 0x00000217, 22224 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 0x00000218, 22225 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 0x00000219, 22226 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 0x0000021a, 22227 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 0x0000021b, 22228 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 0x0000021c, 22229 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 0x0000021d, 22230 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 0x0000021e, 22231 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16 = 0x0000021f, 22232 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17 = 0x00000220, 22233 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18 = 0x00000221, 22234 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19 = 0x00000222, 22235 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20 = 0x00000223, 22236 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21 = 0x00000224, 22237 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22 = 0x00000225, 22238 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23 = 0x00000226, 22239 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24 = 0x00000227, 22240 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25 = 0x00000228, 22241 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26 = 0x00000229, 22242 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27 = 0x0000022a, 22243 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28 = 0x0000022b, 22244 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29 = 0x0000022c, 22245 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30 = 0x0000022d, 22246 IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 0x0000022e, 22247 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 0x0000022f, 22248 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 0x00000230, 22249 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 0x00000231, 22250 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 0x00000232, 22251 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 0x00000233, 22252 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 0x00000234, 22253 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 0x00000235, 22254 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 0x00000236, 22255 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 0x00000237, 22256 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 0x00000238, 22257 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 0x00000239, 22258 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 0x0000023a, 22259 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 0x0000023b, 22260 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 0x0000023c, 22261 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 0x0000023d, 22262 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 0x0000023e, 22263 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16 = 0x0000023f, 22264 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17 = 0x00000240, 22265 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18 = 0x00000241, 22266 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19 = 0x00000242, 22267 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20 = 0x00000243, 22268 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21 = 0x00000244, 22269 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22 = 0x00000245, 22270 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23 = 0x00000246, 22271 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24 = 0x00000247, 22272 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25 = 0x00000248, 22273 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26 = 0x00000249, 22274 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27 = 0x0000024a, 22275 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28 = 0x0000024b, 22276 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29 = 0x0000024c, 22277 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30 = 0x0000024d, 22278 IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 0x0000024e, 22279 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 0x0000024f, 22280 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 0x00000250, 22281 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 0x00000251, 22282 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 0x00000252, 22283 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 0x00000253, 22284 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 0x00000254, 22285 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 0x00000255, 22286 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 0x00000256, 22287 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 0x00000257, 22288 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 0x00000258, 22289 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 0x00000259, 22290 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 0x0000025a, 22291 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 0x0000025b, 22292 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 0x0000025c, 22293 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 0x0000025d, 22294 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 0x0000025e, 22295 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16 = 0x0000025f, 22296 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17 = 0x00000260, 22297 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18 = 0x00000261, 22298 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19 = 0x00000262, 22299 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20 = 0x00000263, 22300 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21 = 0x00000264, 22301 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22 = 0x00000265, 22302 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23 = 0x00000266, 22303 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24 = 0x00000267, 22304 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25 = 0x00000268, 22305 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26 = 0x00000269, 22306 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27 = 0x0000026a, 22307 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28 = 0x0000026b, 22308 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29 = 0x0000026c, 22309 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30 = 0x0000026d, 22310 IH_PERF_SEL_RB0_LOAD_RPTR = 0x0000026e, 22311 IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 0x0000026f, 22312 IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 0x00000270, 22313 IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 0x00000271, 22314 IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 0x00000272, 22315 IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 0x00000273, 22316 IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 0x00000274, 22317 IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 0x00000275, 22318 IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 0x00000276, 22319 IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 0x00000277, 22320 IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 0x00000278, 22321 IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 0x00000279, 22322 IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 0x0000027a, 22323 IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 0x0000027b, 22324 IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 0x0000027c, 22325 IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 0x0000027d, 22326 IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 0x0000027e, 22327 IH_PERF_SEL_RB0_LOAD_RPTR_VF16 = 0x0000027f, 22328 IH_PERF_SEL_RB0_LOAD_RPTR_VF17 = 0x00000280, 22329 IH_PERF_SEL_RB0_LOAD_RPTR_VF18 = 0x00000281, 22330 IH_PERF_SEL_RB0_LOAD_RPTR_VF19 = 0x00000282, 22331 IH_PERF_SEL_RB0_LOAD_RPTR_VF20 = 0x00000283, 22332 IH_PERF_SEL_RB0_LOAD_RPTR_VF21 = 0x00000284, 22333 IH_PERF_SEL_RB0_LOAD_RPTR_VF22 = 0x00000285, 22334 IH_PERF_SEL_RB0_LOAD_RPTR_VF23 = 0x00000286, 22335 IH_PERF_SEL_RB0_LOAD_RPTR_VF24 = 0x00000287, 22336 IH_PERF_SEL_RB0_LOAD_RPTR_VF25 = 0x00000288, 22337 IH_PERF_SEL_RB0_LOAD_RPTR_VF26 = 0x00000289, 22338 IH_PERF_SEL_RB0_LOAD_RPTR_VF27 = 0x0000028a, 22339 IH_PERF_SEL_RB0_LOAD_RPTR_VF28 = 0x0000028b, 22340 IH_PERF_SEL_RB0_LOAD_RPTR_VF29 = 0x0000028c, 22341 IH_PERF_SEL_RB0_LOAD_RPTR_VF30 = 0x0000028d, 22342 IH_PERF_SEL_RB1_LOAD_RPTR = 0x0000028e, 22343 IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 0x0000028f, 22344 IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 0x00000290, 22345 IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 0x00000291, 22346 IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 0x00000292, 22347 IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 0x00000293, 22348 IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 0x00000294, 22349 IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 0x00000295, 22350 IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 0x00000296, 22351 IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 0x00000297, 22352 IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 0x00000298, 22353 IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 0x00000299, 22354 IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 0x0000029a, 22355 IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 0x0000029b, 22356 IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 0x0000029c, 22357 IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 0x0000029d, 22358 IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 0x0000029e, 22359 IH_PERF_SEL_RB1_LOAD_RPTR_VF16 = 0x0000029f, 22360 IH_PERF_SEL_RB1_LOAD_RPTR_VF17 = 0x000002a0, 22361 IH_PERF_SEL_RB1_LOAD_RPTR_VF18 = 0x000002a1, 22362 IH_PERF_SEL_RB1_LOAD_RPTR_VF19 = 0x000002a2, 22363 IH_PERF_SEL_RB1_LOAD_RPTR_VF20 = 0x000002a3, 22364 IH_PERF_SEL_RB1_LOAD_RPTR_VF21 = 0x000002a4, 22365 IH_PERF_SEL_RB1_LOAD_RPTR_VF22 = 0x000002a5, 22366 IH_PERF_SEL_RB1_LOAD_RPTR_VF23 = 0x000002a6, 22367 IH_PERF_SEL_RB1_LOAD_RPTR_VF24 = 0x000002a7, 22368 IH_PERF_SEL_RB1_LOAD_RPTR_VF25 = 0x000002a8, 22369 IH_PERF_SEL_RB1_LOAD_RPTR_VF26 = 0x000002a9, 22370 IH_PERF_SEL_RB1_LOAD_RPTR_VF27 = 0x000002aa, 22371 IH_PERF_SEL_RB1_LOAD_RPTR_VF28 = 0x000002ab, 22372 IH_PERF_SEL_RB1_LOAD_RPTR_VF29 = 0x000002ac, 22373 IH_PERF_SEL_RB1_LOAD_RPTR_VF30 = 0x000002ad, 22374 IH_PERF_SEL_RB2_LOAD_RPTR = 0x000002ae, 22375 IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 0x000002af, 22376 IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 0x000002b0, 22377 IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 0x000002b1, 22378 IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 0x000002b2, 22379 IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 0x000002b3, 22380 IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 0x000002b4, 22381 IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 0x000002b5, 22382 IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 0x000002b6, 22383 IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 0x000002b7, 22384 IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 0x000002b8, 22385 IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 0x000002b9, 22386 IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 0x000002ba, 22387 IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 0x000002bb, 22388 IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 0x000002bc, 22389 IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 0x000002bd, 22390 IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 0x000002be, 22391 IH_PERF_SEL_RB2_LOAD_RPTR_VF16 = 0x000002bf, 22392 IH_PERF_SEL_RB2_LOAD_RPTR_VF17 = 0x000002c0, 22393 IH_PERF_SEL_RB2_LOAD_RPTR_VF18 = 0x000002c1, 22394 IH_PERF_SEL_RB2_LOAD_RPTR_VF19 = 0x000002c2, 22395 IH_PERF_SEL_RB2_LOAD_RPTR_VF20 = 0x000002c3, 22396 IH_PERF_SEL_RB2_LOAD_RPTR_VF21 = 0x000002c4, 22397 IH_PERF_SEL_RB2_LOAD_RPTR_VF22 = 0x000002c5, 22398 IH_PERF_SEL_RB2_LOAD_RPTR_VF23 = 0x000002c6, 22399 IH_PERF_SEL_RB2_LOAD_RPTR_VF24 = 0x000002c7, 22400 IH_PERF_SEL_RB2_LOAD_RPTR_VF25 = 0x000002c8, 22401 IH_PERF_SEL_RB2_LOAD_RPTR_VF26 = 0x000002c9, 22402 IH_PERF_SEL_RB2_LOAD_RPTR_VF27 = 0x000002ca, 22403 IH_PERF_SEL_RB2_LOAD_RPTR_VF28 = 0x000002cb, 22404 IH_PERF_SEL_RB2_LOAD_RPTR_VF29 = 0x000002cc, 22405 IH_PERF_SEL_RB2_LOAD_RPTR_VF30 = 0x000002cd, 22406 } IH_PERF_SEL; 22407 22408 /* 22409 * IH_CLIENT_TYPE enum 22410 */ 22411 22412 typedef enum IH_CLIENT_TYPE { 22413 IH_GFX_VMID_CLIENT = 0x00000000, 22414 IH_MM_VMID_CLIENT = 0x00000001, 22415 IH_MULTI_VMID_CLIENT = 0x00000002, 22416 IH_CLIENT_TYPE_RESERVED = 0x00000003, 22417 } IH_CLIENT_TYPE; 22418 22419 /* 22420 * IH_RING_ID enum 22421 */ 22422 22423 typedef enum IH_RING_ID { 22424 IH_RING_ID_INTERRUPT = 0x00000000, 22425 IH_RING_ID_REQUEST = 0x00000001, 22426 IH_RING_ID_TRANSLATION = 0x00000002, 22427 IH_RING_ID_RESERVED = 0x00000003, 22428 } IH_RING_ID; 22429 22430 /* 22431 * IH_VF_RB_SELECT enum 22432 */ 22433 22434 typedef enum IH_VF_RB_SELECT { 22435 IH_VF_RB_SELECT_CLIENT_FCN_ID = 0x00000000, 22436 IH_VF_RB_SELECT_IH_FCN_ID = 0x00000001, 22437 IH_VF_RB_SELECT_PF = 0x00000002, 22438 IH_VF_RB_SELECT_RESERVED = 0x00000003, 22439 } IH_VF_RB_SELECT; 22440 22441 /* 22442 * IH_INTERFACE_TYPE enum 22443 */ 22444 22445 typedef enum IH_INTERFACE_TYPE { 22446 IH_LEGACY_INTERFACE = 0x00000000, 22447 IH_REGISTER_WRITE_INTERFACE = 0x00000001, 22448 } IH_INTERFACE_TYPE; 22449 22450 /******************************************************* 22451 * SEM Enums 22452 *******************************************************/ 22453 22454 /* 22455 * SEM_PERF_SEL enum 22456 */ 22457 22458 typedef enum SEM_PERF_SEL { 22459 SEM_PERF_SEL_CYCLE = 0x00000000, 22460 SEM_PERF_SEL_IDLE = 0x00000001, 22461 SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002, 22462 SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003, 22463 SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004, 22464 SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005, 22465 SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006, 22466 SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007, 22467 SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008, 22468 SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009, 22469 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a, 22470 SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b, 22471 SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c, 22472 SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d, 22473 SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e, 22474 SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f, 22475 SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010, 22476 SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011, 22477 SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012, 22478 SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013, 22479 SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014, 22480 SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015, 22481 SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016, 22482 SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017, 22483 SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018, 22484 SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019, 22485 SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a, 22486 SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b, 22487 SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c, 22488 SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d, 22489 SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e, 22490 SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f, 22491 SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020, 22492 SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021, 22493 SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022, 22494 SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023, 22495 SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024, 22496 SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025, 22497 SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026, 22498 SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027, 22499 SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028, 22500 SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029, 22501 SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a, 22502 SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b, 22503 SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c, 22504 SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d, 22505 SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e, 22506 SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f, 22507 SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030, 22508 SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031, 22509 SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032, 22510 SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033, 22511 SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034, 22512 SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035, 22513 SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036, 22514 SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037, 22515 SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038, 22516 SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039, 22517 SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a, 22518 SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b, 22519 SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c, 22520 SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d, 22521 SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e, 22522 SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f, 22523 SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040, 22524 SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041, 22525 SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042, 22526 SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043, 22527 SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044, 22528 SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045, 22529 SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046, 22530 SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047, 22531 SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048, 22532 SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049, 22533 SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a, 22534 SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b, 22535 SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c, 22536 SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d, 22537 SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e, 22538 SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f, 22539 SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050, 22540 SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051, 22541 SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052, 22542 SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053, 22543 SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054, 22544 SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055, 22545 SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056, 22546 SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057, 22547 SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058, 22548 SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059, 22549 SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a, 22550 SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b, 22551 SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c, 22552 SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d, 22553 SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e, 22554 SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f, 22555 SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060, 22556 SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061, 22557 SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062, 22558 SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063, 22559 SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064, 22560 SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065, 22561 SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066, 22562 SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067, 22563 SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068, 22564 SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069, 22565 SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a, 22566 SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b, 22567 SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c, 22568 SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d, 22569 SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e, 22570 SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f, 22571 SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070, 22572 SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071, 22573 SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072, 22574 SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073, 22575 SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074, 22576 SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075, 22577 SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076, 22578 SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077, 22579 SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078, 22580 SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079, 22581 SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a, 22582 SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b, 22583 SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c, 22584 SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d, 22585 SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e, 22586 SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f, 22587 SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080, 22588 SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081, 22589 SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082, 22590 SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083, 22591 SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084, 22592 SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085, 22593 SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086, 22594 SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087, 22595 SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088, 22596 SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089, 22597 SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a, 22598 SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b, 22599 SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c, 22600 SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d, 22601 SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e, 22602 SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f, 22603 SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090, 22604 SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091, 22605 SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092, 22606 SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093, 22607 SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094, 22608 SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095, 22609 SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096, 22610 SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097, 22611 SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098, 22612 SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099, 22613 SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a, 22614 SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b, 22615 SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c, 22616 SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d, 22617 SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e, 22618 SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f, 22619 SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0, 22620 SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1, 22621 SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2, 22622 SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3, 22623 SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4, 22624 SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5, 22625 SEM_PERF_SEL_MC_RD_REQ = 0x000000a6, 22626 SEM_PERF_SEL_MC_RD_RET = 0x000000a7, 22627 SEM_PERF_SEL_MC_WR_REQ = 0x000000a8, 22628 SEM_PERF_SEL_MC_WR_RET = 0x000000a9, 22629 SEM_PERF_SEL_ATC_REQ = 0x000000aa, 22630 SEM_PERF_SEL_ATC_RET = 0x000000ab, 22631 SEM_PERF_SEL_ATC_XNACK = 0x000000ac, 22632 SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad, 22633 SEM_PERF_SEL_ATC_VM_INVALIDATION = 0x000000ae, 22634 } SEM_PERF_SEL; 22635 22636 /******************************************************* 22637 * SMUIO Enums 22638 *******************************************************/ 22639 22640 /* 22641 * ROM_SIGNATURE value 22642 */ 22643 22644 #define ROM_SIGNATURE 0x0000aa55 22645 22646 /******************************************************* 22647 * UVD_EFC Enums 22648 *******************************************************/ 22649 22650 /* 22651 * EFC_SURFACE_PIXEL_FORMAT enum 22652 */ 22653 22654 typedef enum EFC_SURFACE_PIXEL_FORMAT { 22655 EFC_ARGB1555 = 0x00000001, 22656 EFC_RGBA5551 = 0x00000002, 22657 EFC_RGB565 = 0x00000003, 22658 EFC_BGR565 = 0x00000004, 22659 EFC_ARGB4444 = 0x00000005, 22660 EFC_RGBA4444 = 0x00000006, 22661 EFC_ARGB8888 = 0x00000008, 22662 EFC_RGBA8888 = 0x00000009, 22663 EFC_ARGB2101010 = 0x0000000a, 22664 EFC_RGBA1010102 = 0x0000000b, 22665 EFC_AYCrCb8888 = 0x0000000c, 22666 EFC_YCrCbA8888 = 0x0000000d, 22667 EFC_ACrYCb8888 = 0x0000000e, 22668 EFC_CrYCbA8888 = 0x0000000f, 22669 EFC_ARGB16161616_10MSB = 0x00000010, 22670 EFC_RGBA16161616_10MSB = 0x00000011, 22671 EFC_ARGB16161616_10LSB = 0x00000012, 22672 EFC_RGBA16161616_10LSB = 0x00000013, 22673 EFC_ARGB16161616_12MSB = 0x00000014, 22674 EFC_RGBA16161616_12MSB = 0x00000015, 22675 EFC_ARGB16161616_12LSB = 0x00000016, 22676 EFC_RGBA16161616_12LSB = 0x00000017, 22677 EFC_ARGB16161616_FLOAT = 0x00000018, 22678 EFC_RGBA16161616_FLOAT = 0x00000019, 22679 EFC_ARGB16161616_UNORM = 0x0000001a, 22680 EFC_RGBA16161616_UNORM = 0x0000001b, 22681 EFC_ARGB16161616_SNORM = 0x0000001c, 22682 EFC_RGBA16161616_SNORM = 0x0000001d, 22683 EFC_AYCrCb16161616_10MSB = 0x00000020, 22684 EFC_AYCrCb16161616_10LSB = 0x00000021, 22685 EFC_YCrCbA16161616_10MSB = 0x00000022, 22686 EFC_YCrCbA16161616_10LSB = 0x00000023, 22687 EFC_ACrYCb16161616_10MSB = 0x00000024, 22688 EFC_ACrYCb16161616_10LSB = 0x00000025, 22689 EFC_CrYCbA16161616_10MSB = 0x00000026, 22690 EFC_CrYCbA16161616_10LSB = 0x00000027, 22691 EFC_AYCrCb16161616_12MSB = 0x00000028, 22692 EFC_AYCrCb16161616_12LSB = 0x00000029, 22693 EFC_YCrCbA16161616_12MSB = 0x0000002a, 22694 EFC_YCrCbA16161616_12LSB = 0x0000002b, 22695 EFC_ACrYCb16161616_12MSB = 0x0000002c, 22696 EFC_ACrYCb16161616_12LSB = 0x0000002d, 22697 EFC_CrYCbA16161616_12MSB = 0x0000002e, 22698 EFC_CrYCbA16161616_12LSB = 0x0000002f, 22699 EFC_Y8_CrCb88_420_PLANAR = 0x00000040, 22700 EFC_Y8_CbCr88_420_PLANAR = 0x00000041, 22701 EFC_Y10_CrCb1010_420_PLANAR = 0x00000042, 22702 EFC_Y10_CbCr1010_420_PLANAR = 0x00000043, 22703 EFC_Y12_CrCb1212_420_PLANAR = 0x00000044, 22704 EFC_Y12_CbCr1212_420_PLANAR = 0x00000045, 22705 EFC_YCrYCb8888_422_PACKED = 0x00000048, 22706 EFC_YCbYCr8888_422_PACKED = 0x00000049, 22707 EFC_CrYCbY8888_422_PACKED = 0x0000004a, 22708 EFC_CbYCrY8888_422_PACKED = 0x0000004b, 22709 EFC_YCrYCb10101010_422_PACKED = 0x0000004c, 22710 EFC_YCbYCr10101010_422_PACKED = 0x0000004d, 22711 EFC_CrYCbY10101010_422_PACKED = 0x0000004e, 22712 EFC_CbYCrY10101010_422_PACKED = 0x0000004f, 22713 EFC_YCrYCb12121212_422_PACKED = 0x00000050, 22714 EFC_YCbYCr12121212_422_PACKED = 0x00000051, 22715 EFC_CrYCbY12121212_422_PACKED = 0x00000052, 22716 EFC_CbYCrY12121212_422_PACKED = 0x00000053, 22717 EFC_RGB111110_FIX = 0x00000070, 22718 EFC_BGR101111_FIX = 0x00000071, 22719 EFC_ACrYCb2101010 = 0x00000072, 22720 EFC_CrYCbA1010102 = 0x00000073, 22721 EFC_RGB111110_FLOAT = 0x00000076, 22722 EFC_BGR101111_FLOAT = 0x00000077, 22723 EFC_MONO_8 = 0x00000078, 22724 EFC_MONO_10MSB = 0x00000079, 22725 EFC_MONO_10LSB = 0x0000007a, 22726 EFC_MONO_12MSB = 0x0000007b, 22727 EFC_MONO_12LSB = 0x0000007c, 22728 EFC_MONO_16 = 0x0000007d, 22729 } EFC_SURFACE_PIXEL_FORMAT; 22730 22731 /******************************************************* 22732 * UVD Enums 22733 *******************************************************/ 22734 22735 /* 22736 * UVDFirmwareCommand enum 22737 */ 22738 22739 typedef enum UVDFirmwareCommand { 22740 UVDFC_FENCE = 0x00000000, 22741 UVDFC_TRAP = 0x00000001, 22742 UVDFC_DECODED_ADDR = 0x00000002, 22743 UVDFC_MBLOCK_ADDR = 0x00000003, 22744 UVDFC_ITBUF_ADDR = 0x00000004, 22745 UVDFC_DISPLAY_ADDR = 0x00000005, 22746 UVDFC_EOD = 0x00000006, 22747 UVDFC_DISPLAY_PITCH = 0x00000007, 22748 UVDFC_DISPLAY_TILING = 0x00000008, 22749 UVDFC_BITSTREAM_ADDR = 0x00000009, 22750 UVDFC_BITSTREAM_SIZE = 0x0000000a, 22751 } UVDFirmwareCommand; 22752 22753 /******************************************************* 22754 * I2C_4_ Enums 22755 *******************************************************/ 22756 22757 /* 22758 * REVISION_ID value 22759 */ 22760 22761 #define IP_USB_PD_REVISION_ID 0x00000000 22762 22763 #endif /*_navi10_ENUM_HEADER*/ 22764 22765