1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 8) 28 29 #define MES_API_VERSION 0x14 30 31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */ 32 #define AMDGPU_MES_LOG_BUFFER_SIZE 0xC000 33 34 /* Driver submits one API(cmd) as a single Frame and this command size is same for all API 35 * to ease the debugging and parsing of ring buffer. 36 */ 37 enum {API_FRAME_SIZE_IN_DWORDS = 64}; 38 39 /* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in, 40 * this creates another queue 41 */ 42 enum {API_NUMBER_OF_COMMAND_MAX = 32}; 43 44 enum MES_API_TYPE { 45 MES_API_TYPE_SCHEDULER = 1, 46 MES_API_TYPE_MAX 47 }; 48 49 enum MES_SCH_API_OPCODE { 50 MES_SCH_API_SET_HW_RSRC = 0, 51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 52 MES_SCH_API_ADD_QUEUE = 2, 53 MES_SCH_API_REMOVE_QUEUE = 3, 54 MES_SCH_API_PERFORM_YIELD = 4, 55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, /* For windows GANG = Context */ 56 MES_SCH_API_SUSPEND = 6, 57 MES_SCH_API_RESUME = 7, 58 MES_SCH_API_RESET = 8, 59 MES_SCH_API_SET_LOG_BUFFER = 9, 60 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 62 MES_SCH_API_SET_DEBUG_VMID = 13, 63 MES_SCH_API_MISC = 14, 64 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 65 MES_SCH_API_AMD_LOG = 16, 66 MES_SCH_API_SET_SE_MODE = 17, 67 MES_SCH_API_SET_GANG_SUBMIT = 18, 68 MES_SCH_API_SET_HW_RSRC_1 = 19, 69 MES_SCH_API_INV_TLBS = 20, 70 71 MES_SCH_API_MAX = 0xFF 72 }; 73 74 union MES_API_HEADER { 75 struct { 76 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 77 uint32_t opcode : 8; 78 uint32_t dwsize : 8; /* including header */ 79 uint32_t reserved : 12; 80 }; 81 82 uint32_t u32All; 83 }; 84 85 enum MES_AMD_PRIORITY_LEVEL { 86 AMD_PRIORITY_LEVEL_LOW = 0, 87 AMD_PRIORITY_LEVEL_NORMAL = 1, 88 AMD_PRIORITY_LEVEL_MEDIUM = 2, 89 AMD_PRIORITY_LEVEL_HIGH = 3, 90 AMD_PRIORITY_LEVEL_REALTIME = 4, 91 92 AMD_PRIORITY_NUM_LEVELS 93 }; 94 95 enum MES_QUEUE_TYPE { 96 MES_QUEUE_TYPE_GFX, 97 MES_QUEUE_TYPE_COMPUTE, 98 MES_QUEUE_TYPE_SDMA, 99 100 MES_QUEUE_TYPE_MAX, 101 MES_QUEUE_TYPE_SCHQ = MES_QUEUE_TYPE_MAX, 102 }; 103 104 struct MES_API_STATUS { 105 uint64_t api_completion_fence_addr; 106 uint64_t api_completion_fence_value; 107 }; 108 109 /* 110 * MES will set api_completion_fence_value in api_completion_fence_addr 111 * when it can successflly process the API. MES will also trigger 112 * following interrupt when it finish process the API no matter success 113 * or failed. 114 * Interrupt source id 181 (EOP) with context ID (DW 6 in the int 115 * cookie) set to 0xb1 and context type set to 8. Driver side need 116 * to enable TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to 117 * catch this interrupt. 118 * Driver side also need to set enable_mes_fence_int = 1 in 119 * set_HW_resource package to enable this fence interrupt. 120 * when the API process failed. 121 * lowre 32 bits set to 0. 122 * higher 32 bits set as follows (bit shift within high 32) 123 * bit 0 - 7 API specific error code. 124 * bit 8 - 15 API OPCODE. 125 * bit 16 - 23 MISC OPCODE if any 126 * bit 24 - 30 ERROR category (API_ERROR_XXX) 127 * bit 31 Set to 1 to indicate error status 128 * 129 */ 130 enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 }; 131 enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 }; 132 enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 }; 133 enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 }; 134 135 enum MES_ERROR_CATEGORY_CODE_12 { 136 MES_ERROR_API = 1, 137 MES_ERROR_SCHEDULING = 2, 138 MES_ERROR_UNKNOWN = 3, 139 }; 140 141 #define MES_ERR_CODE(api_err, opcode, misc_op, category) \ 142 ((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \ 143 misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \ 144 category << MES_ERROR_CATEGORY_SHIFT_12 | \ 145 1 << MES_API_STATUS_ERROR_SHIFT_12) << 32) 146 147 enum { MAX_COMPUTE_PIPES = 8 }; 148 enum { MAX_GFX_PIPES = 2 }; 149 enum { MAX_SDMA_PIPES = 2 }; 150 151 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 152 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 153 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 154 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 155 156 157 enum { MAX_QUEUES_IN_A_GANG = 8 }; 158 159 enum VM_HUB_TYPE { 160 VM_HUB_TYPE_GC = 0, 161 VM_HUB_TYPE_MM = 1, 162 163 VM_HUB_TYPE_MAX, 164 }; 165 166 enum { VMID_INVALID = 0xffff }; 167 168 enum { MAX_VMID_GCHUB = 16 }; 169 enum { MAX_VMID_MMHUB = 16 }; 170 171 enum SET_DEBUG_VMID_OPERATIONS { 172 DEBUG_VMID_OP_PROGRAM = 0, 173 DEBUG_VMID_OP_ALLOCATE = 1, 174 DEBUG_VMID_OP_RELEASE = 2, 175 DEBUG_VMID_OP_VM_SETUP = 3 // used to set up the debug vmid page table in the kernel queue case (mode 1) 176 }; 177 178 enum MES_MS_LOG_CONTEXT_STATE { 179 MES_LOG_CONTEXT_STATE_IDLE = 0, 180 MES_LOG_CONTEXT_STATE_RUNNING = 1, 181 MES_LOG_CONTEXT_STATE_READY = 2, 182 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 183 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 184 }; 185 186 enum MES_MS_LOG_OPERATION { 187 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 188 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 189 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 190 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 191 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 192 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 193 }; 194 195 struct MES_LOG_CONTEXT_STATE_CHANGE { 196 uint64_t h_context; 197 enum MES_MS_LOG_CONTEXT_STATE new_context_state; 198 }; 199 200 struct MES_LOG_QUEUE_NEW_WORK { 201 uint64_t h_queue; 202 uint64_t reserved; 203 }; 204 205 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 206 uint64_t h_queue; 207 uint64_t h_sync_object; 208 }; 209 210 struct MES_LOG_QUEUE_NO_MORE_WORK { 211 uint64_t h_queue; 212 uint64_t reserved; 213 }; 214 215 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 216 uint64_t h_queue; 217 uint64_t h_sync_object; 218 }; 219 220 struct MES_LOG_ENTRY_HEADER { 221 uint32_t first_free_entry_index; 222 uint32_t wraparound_count; 223 uint64_t number_of_entries; 224 uint64_t reserved[2]; 225 }; 226 227 struct MES_LOG_ENTRY_DATA { 228 uint64_t gpu_time_stamp; 229 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 230 uint32_t reserved_operation_type_bits; 231 union { 232 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 233 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 234 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 235 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 236 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 237 uint64_t all[2]; 238 }; 239 }; 240 241 struct MES_LOG_BUFFER { 242 struct MES_LOG_ENTRY_HEADER header; 243 struct MES_LOG_ENTRY_DATA entries[]; 244 }; 245 246 enum MES_SWIP_TO_HWIP_DEF { 247 MES_MAX_HWIP_SEGMENT = 8, 248 }; 249 250 union MESAPI_SET_HW_RESOURCES { 251 struct { 252 union MES_API_HEADER header; 253 uint32_t vmid_mask_mmhub; 254 uint32_t vmid_mask_gfxhub; 255 uint32_t gds_size; 256 uint32_t paging_vmid; 257 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 258 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 259 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 260 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 261 uint64_t g_sch_ctx_gpu_mc_ptr; 262 uint64_t query_status_fence_gpu_mc_ptr; 263 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 264 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 265 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 266 struct MES_API_STATUS api_status; 267 union { 268 struct { 269 uint32_t disable_reset : 1; 270 uint32_t use_different_vmid_compute : 1; 271 uint32_t disable_mes_log : 1; 272 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 273 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 274 uint32_t second_gfx_pipe_enabled : 1; 275 uint32_t enable_level_process_quantum_check : 1; 276 uint32_t legacy_sch_mode : 1; 277 uint32_t disable_add_queue_wptr_mc_addr : 1; 278 uint32_t enable_mes_event_int_logging : 1; 279 uint32_t enable_reg_active_poll : 1; 280 uint32_t use_disable_queue_in_legacy_uq_preemption : 1; 281 uint32_t send_write_data : 1; 282 uint32_t os_tdr_timeout_override : 1; 283 uint32_t use_rs64mem_for_proc_gang_ctx : 1; 284 uint32_t halt_on_misaligned_access : 1; 285 uint32_t use_add_queue_unmap_flag_addr : 1; 286 uint32_t enable_mes_sch_stb_log : 1; 287 uint32_t limit_single_process : 1; 288 uint32_t unmapped_doorbell_handling: 2; 289 uint32_t enable_mes_fence_int: 1; 290 uint32_t enable_lr_compute_wa : 1; 291 uint32_t reserved : 9; 292 }; 293 uint32_t uint32_all; 294 }; 295 uint32_t oversubscription_timer; 296 uint64_t doorbell_info; 297 uint64_t event_intr_history_gpu_mc_ptr; 298 uint64_t timestamp; 299 uint32_t os_tdr_timeout_in_sec; 300 }; 301 302 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 303 }; 304 305 union MESAPI_SET_HW_RESOURCES_1 { 306 struct { 307 union MES_API_HEADER header; 308 struct MES_API_STATUS api_status; 309 uint64_t timestamp; 310 union { 311 struct { 312 uint32_t enable_mes_debug_ctx : 1; 313 uint32_t reserved : 31; 314 }; 315 uint32_t uint32_all; 316 }; 317 uint64_t mes_debug_ctx_mc_addr; 318 uint32_t mes_debug_ctx_size; 319 /* unit is 100ms */ 320 uint32_t mes_kiq_unmap_timeout; 321 uint64_t reserved1; 322 uint64_t cleaner_shader_fence_mc_addr; 323 }; 324 325 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 326 }; 327 328 union MESAPI__ADD_QUEUE { 329 struct { 330 union MES_API_HEADER header; 331 uint32_t process_id; 332 uint64_t page_table_base_addr; 333 uint64_t process_va_start; 334 uint64_t process_va_end; 335 uint64_t process_quantum; 336 uint64_t process_context_addr; 337 uint64_t gang_quantum; 338 uint64_t gang_context_addr; 339 uint32_t inprocess_gang_priority; 340 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 341 uint32_t doorbell_offset; 342 uint64_t mqd_addr; 343 /* From MES_API_VERSION 2, mc addr is expected for wptr_addr */ 344 uint64_t wptr_addr; 345 uint64_t h_context; 346 uint64_t h_queue; 347 enum MES_QUEUE_TYPE queue_type; 348 uint32_t gds_base; 349 union { 350 /* backwards compatibility with Linux, remove union once they use kfd_queue_size */ 351 uint32_t gds_size; 352 uint32_t kfd_queue_size; 353 }; 354 uint32_t gws_base; 355 uint32_t gws_size; 356 uint32_t oa_mask; 357 uint64_t trap_handler_addr; 358 uint32_t vm_context_cntl; 359 360 struct { 361 uint32_t paging : 1; 362 uint32_t debug_vmid : 4; 363 uint32_t program_gds : 1; 364 uint32_t is_gang_suspended : 1; 365 uint32_t is_tmz_queue : 1; 366 uint32_t map_kiq_utility_queue : 1; 367 uint32_t is_kfd_process : 1; 368 uint32_t trap_en : 1; 369 uint32_t is_aql_queue : 1; 370 uint32_t skip_process_ctx_clear : 1; 371 uint32_t map_legacy_kq : 1; 372 uint32_t exclusively_scheduled : 1; 373 uint32_t is_long_running : 1; 374 uint32_t is_dwm_queue : 1; 375 uint32_t reserved : 15; 376 }; 377 struct MES_API_STATUS api_status; 378 uint64_t tma_addr; 379 uint32_t sch_id; 380 uint64_t timestamp; 381 uint32_t process_context_array_index; 382 uint32_t gang_context_array_index; 383 uint32_t pipe_id; //used for mapping legacy kernel queue 384 uint32_t queue_id; 385 uint32_t alignment_mode_setting; 386 }; 387 388 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 389 }; 390 391 union MESAPI__REMOVE_QUEUE { 392 struct { 393 union MES_API_HEADER header; 394 uint32_t doorbell_offset; 395 uint64_t gang_context_addr; 396 397 struct { 398 uint32_t reserved01 : 1; 399 uint32_t unmap_kiq_utility_queue : 1; 400 uint32_t preempt_legacy_gfx_queue : 1; 401 uint32_t unmap_legacy_queue : 1; 402 uint32_t remove_queue_after_reset : 1; 403 uint32_t reserved : 27; 404 }; 405 struct MES_API_STATUS api_status; 406 407 uint32_t pipe_id; 408 uint32_t queue_id; 409 410 uint64_t tf_addr; 411 uint32_t tf_data; 412 413 enum MES_QUEUE_TYPE queue_type; 414 uint64_t timestamp; 415 uint32_t gang_context_array_index; 416 }; 417 418 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 419 }; 420 421 union MESAPI__SET_SCHEDULING_CONFIG { 422 struct { 423 union MES_API_HEADER header; 424 /* Grace period when preempting another priority band for this priority band. 425 * The value for idle priority band is ignored, as it never preempts other bands. 426 */ 427 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 428 429 /* Default quantum for scheduling across processes within a priority band. */ 430 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 431 432 /* Default grace period for processes that preempt each other within a priority band.*/ 433 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 434 435 /* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level. 436 * Valid values are between 0 and 50, with the default being 10. 437 */ 438 uint32_t normal_yield_percent; 439 440 struct MES_API_STATUS api_status; 441 uint64_t timestamp; 442 }; 443 444 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 445 }; 446 447 union MESAPI__PERFORM_YIELD { 448 struct { 449 union MES_API_HEADER header; 450 uint32_t dummy; 451 struct MES_API_STATUS api_status; 452 uint64_t timestamp; 453 }; 454 455 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 456 }; 457 458 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 459 struct { 460 union MES_API_HEADER header; 461 uint32_t inprocess_gang_priority; 462 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 463 uint64_t gang_quantum; 464 uint64_t gang_context_addr; 465 struct MES_API_STATUS api_status; 466 uint32_t doorbell_offset; 467 uint64_t timestamp; 468 uint32_t gang_context_array_index; 469 struct { 470 uint32_t queue_quantum_scale : 2; 471 uint32_t queue_quantum_duration : 8; 472 uint32_t apply_quantum_all_processes : 1; 473 uint32_t reserved : 21; 474 }; 475 }; 476 477 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 478 }; 479 480 union MESAPI__SUSPEND { 481 struct { 482 union MES_API_HEADER header; 483 /* false - suspend all gangs; true - specific gang */ 484 struct { 485 uint32_t suspend_all_gangs : 1; 486 uint32_t reserved : 31; 487 }; 488 /* gang_context_addr is valid only if suspend_all = false */ 489 490 uint64_t gang_context_addr; 491 492 uint64_t suspend_fence_addr; 493 uint32_t suspend_fence_value; 494 495 struct MES_API_STATUS api_status; 496 497 union { 498 uint32_t return_value; // to be removed 499 uint32_t sch_id; //keep the old return_value temporarily for compatibility 500 }; 501 uint32_t doorbell_offset; 502 uint64_t timestamp; 503 enum MES_QUEUE_TYPE legacy_uq_type; 504 enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level; 505 uint32_t gang_context_array_index; 506 }; 507 508 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 509 }; 510 511 union MESAPI__RESUME { 512 struct { 513 union MES_API_HEADER header; 514 /* false - resume all gangs; true - specified gang */ 515 struct { 516 uint32_t resume_all_gangs : 1; 517 uint32_t reserved : 31; 518 }; 519 /* valid only if resume_all_gangs = false */ 520 uint64_t gang_context_addr; 521 522 struct MES_API_STATUS api_status; 523 uint32_t doorbell_offset; 524 uint64_t timestamp; 525 uint32_t gang_context_array_index; 526 }; 527 528 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 529 }; 530 531 union MESAPI__RESET { 532 struct { 533 union MES_API_HEADER header; 534 535 struct { 536 /* Only reset the queue given by doorbell_offset (not entire gang) */ 537 uint32_t reset_queue_only : 1; 538 /* Hang detection first then reset any queues that are hung */ 539 uint32_t hang_detect_then_reset : 1; 540 /* Only do hang detection (no reset) */ 541 uint32_t hang_detect_only : 1; 542 /* Reset HP and LP kernel queues not managed by MES */ 543 uint32_t reset_legacy_gfx : 1; 544 /* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */ 545 uint32_t use_connected_queue_index : 1; 546 /* For gfx pipe 1 */ 547 uint32_t use_connected_queue_index_p1 : 1; 548 uint32_t reserved : 26; 549 }; 550 551 uint64_t gang_context_addr; 552 553 /* valid only if reset_queue_only = true */ 554 uint32_t doorbell_offset; 555 556 /* valid only if hang_detect_then_reset = true */ 557 uint64_t doorbell_offset_addr; 558 enum MES_QUEUE_TYPE queue_type; 559 560 /* valid only if reset_legacy_gfx = true */ 561 uint32_t pipe_id_lp; 562 uint32_t queue_id_lp; 563 uint32_t vmid_id_lp; 564 uint64_t mqd_mc_addr_lp; 565 uint32_t doorbell_offset_lp; 566 uint64_t wptr_addr_lp; 567 568 uint32_t pipe_id_hp; 569 uint32_t queue_id_hp; 570 uint32_t vmid_id_hp; 571 uint64_t mqd_mc_addr_hp; 572 uint32_t doorbell_offset_hp; 573 uint64_t wptr_addr_hp; 574 575 struct MES_API_STATUS api_status; 576 uint32_t active_vmids; 577 uint64_t timestamp; 578 579 uint32_t gang_context_array_index; 580 581 uint32_t connected_queue_index; 582 uint32_t connected_queue_index_p1; 583 }; 584 585 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 586 }; 587 588 union MESAPI__SET_LOGGING_BUFFER { 589 struct { 590 union MES_API_HEADER header; 591 /* There are separate log buffers for each queue type */ 592 enum MES_QUEUE_TYPE log_type; 593 /* Log buffer GPU Address */ 594 uint64_t logging_buffer_addr; 595 /* number of entries in the log buffer */ 596 uint32_t number_of_entries; 597 /* Entry index at which CPU interrupt needs to be signalled */ 598 uint32_t interrupt_entry; 599 600 struct MES_API_STATUS api_status; 601 uint64_t timestamp; 602 uint32_t vmid; 603 }; 604 605 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 606 }; 607 608 enum MES_API_QUERY_MES_OPCODE { 609 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE, 610 MES_API_QUERY_MES__CHECK_HEALTHY, 611 MES_API_QUERY_MES__MAX, 612 }; 613 614 enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 }; 615 616 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE { 617 uint64_t proc_ctx_array_size_addr; 618 uint64_t gang_ctx_array_size_addr; 619 }; 620 621 struct MES_API_QUERY_MES__HEALTHY_CHECK { 622 uint64_t healthy_addr; 623 }; 624 625 union MESAPI__QUERY_MES_STATUS { 626 struct { 627 union MES_API_HEADER header; 628 enum MES_API_QUERY_MES_OPCODE subopcode; 629 struct MES_API_STATUS api_status; 630 uint64_t timestamp; 631 union { 632 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size; 633 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check; 634 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS]; 635 }; 636 }; 637 638 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 639 }; 640 641 union MESAPI__SET_DEBUG_VMID { 642 struct { 643 union MES_API_HEADER header; 644 struct MES_API_STATUS api_status; 645 union { 646 struct { 647 uint32_t use_gds : 1; 648 uint32_t operation : 2; 649 uint32_t reserved : 29; 650 } flags; 651 uint32_t u32All; 652 }; 653 uint32_t reserved; 654 uint32_t debug_vmid; 655 uint64_t process_context_addr; 656 uint64_t page_table_base_addr; 657 uint64_t process_va_start; 658 uint64_t process_va_end; 659 uint32_t gds_base; 660 uint32_t gds_size; 661 uint32_t gws_base; 662 uint32_t gws_size; 663 uint32_t oa_mask; 664 665 uint64_t output_addr; // output addr of the acquired vmid value 666 667 uint64_t timestamp; 668 669 uint32_t process_vm_cntl; 670 enum MES_QUEUE_TYPE queue_type; 671 672 uint32_t process_context_array_index; 673 674 uint32_t alignment_mode_setting; 675 }; 676 677 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 678 }; 679 680 enum MESAPI_MISC_OPCODE { 681 MESAPI_MISC__WRITE_REG, 682 MESAPI_MISC__INV_GART, 683 MESAPI_MISC__QUERY_STATUS, 684 MESAPI_MISC__READ_REG, 685 MESAPI_MISC__WAIT_REG_MEM, 686 MESAPI_MISC__SET_SHADER_DEBUGGER, 687 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE, 688 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES, 689 MESAPI_MISC__QUERY_HUNG_ENGINE_ID, 690 MESAPI_MISC__CHANGE_CONFIG, 691 MESAPI_MISC__LAUNCH_CLEANER_SHADER, 692 MESAPI_MISC__SETUP_MES_DBGEXT, 693 694 MESAPI_MISC__MAX, 695 }; 696 697 enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20}; 698 699 struct WRITE_REG { 700 uint32_t reg_offset; 701 uint32_t reg_value; 702 }; 703 704 struct READ_REG { 705 uint32_t reg_offset; 706 uint64_t buffer_addr; 707 union { 708 struct { 709 uint32_t read64Bits : 1; 710 uint32_t reserved : 31; 711 } bits; 712 uint32_t all; 713 } option; 714 }; 715 716 struct INV_GART { 717 uint64_t inv_range_va_start; 718 uint64_t inv_range_size; 719 }; 720 721 struct QUERY_STATUS { 722 uint32_t context_id; 723 }; 724 725 enum WRM_OPERATION { 726 WRM_OPERATION__WAIT_REG_MEM, 727 WRM_OPERATION__WR_WAIT_WR_REG, 728 729 WRM_OPERATION__MAX, 730 }; 731 732 struct WAIT_REG_MEM { 733 enum WRM_OPERATION op; 734 /* only function = equal_to_the_reference_value and mem_space = register_space supported for now */ 735 uint32_t reference; 736 uint32_t mask; 737 uint32_t reg_offset1; 738 uint32_t reg_offset2; 739 }; 740 741 struct SET_SHADER_DEBUGGER { 742 uint64_t process_context_addr; 743 union { 744 struct { 745 uint32_t single_memop : 1; // SQ_DEBUG.single_memop 746 uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op 747 uint32_t reserved : 30; 748 }; 749 uint32_t u32all; 750 } flags; 751 uint32_t spi_gdbg_per_vmid_cntl; 752 uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL 753 uint32_t trap_en; 754 }; 755 756 struct SET_GANG_SUBMIT { 757 uint64_t gang_context_addr; 758 uint64_t slave_gang_context_addr; 759 uint32_t gang_context_array_index; 760 uint32_t slave_gang_context_array_index; 761 }; 762 763 enum MESAPI_MISC__CHANGE_CONFIG_OPTION { 764 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0, 765 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1, 766 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2, 767 768 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F 769 }; 770 771 struct CHANGE_CONFIG { 772 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode; 773 union { 774 struct { 775 uint32_t limit_single_process : 1; 776 uint32_t enable_hws_logging_buffer : 1; 777 uint32_t reserved : 30; 778 } bits; 779 uint32_t all; 780 } option; 781 782 struct { 783 uint32_t tdr_level; 784 uint32_t tdr_delay; 785 } tdr_config; 786 }; 787 788 union MESAPI__MISC { 789 struct { 790 union MES_API_HEADER header; 791 enum MESAPI_MISC_OPCODE opcode; 792 struct MES_API_STATUS api_status; 793 union { 794 struct WRITE_REG write_reg; 795 struct INV_GART inv_gart; 796 struct QUERY_STATUS query_status; 797 struct READ_REG read_reg; 798 struct WAIT_REG_MEM wait_reg_mem; 799 struct SET_SHADER_DEBUGGER set_shader_debugger; 800 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 801 struct CHANGE_CONFIG change_config; 802 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 803 }; 804 uint64_t timestamp; 805 uint32_t doorbell_offset; 806 uint32_t os_fence; 807 }; 808 809 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 810 }; 811 812 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 813 struct { 814 union MES_API_HEADER header; 815 uint64_t page_table_base_addr; 816 uint64_t process_context_addr; 817 struct MES_API_STATUS api_status; 818 uint64_t timestamp; 819 uint32_t process_context_array_index; 820 }; 821 822 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 823 }; 824 825 union MESAPI_AMD_LOG { 826 struct { 827 union MES_API_HEADER header; 828 uint64_t p_buffer_memory; 829 uint64_t p_buffer_size_used; 830 struct MES_API_STATUS api_status; 831 uint64_t timestamp; 832 }; 833 834 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 835 }; 836 837 enum MES_SE_MODE { 838 MES_SE_MODE_INVALID = 0, 839 MES_SE_MODE_SINGLE_SE = 1, 840 MES_SE_MODE_DUAL_SE = 2, 841 MES_SE_MODE_LOWER_POWER = 3, 842 }; 843 844 union MESAPI__SET_SE_MODE { 845 struct { 846 union MES_API_HEADER header; 847 /* the new SE mode to apply*/ 848 enum MES_SE_MODE new_se_mode; 849 /* the fence to make sure the ItCpgCtxtSync packet is completed */ 850 uint64_t cpg_ctxt_sync_fence_addr; 851 uint32_t cpg_ctxt_sync_fence_value; 852 /* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */ 853 union { 854 struct { 855 uint32_t log_seq_time : 1; 856 uint32_t reserved : 31; 857 }; 858 uint32_t uint32_all; 859 }; 860 struct MES_API_STATUS api_status; 861 }; 862 863 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 864 }; 865 866 union MESAPI__SET_GANG_SUBMIT { 867 struct { 868 union MES_API_HEADER header; 869 struct MES_API_STATUS api_status; 870 struct SET_GANG_SUBMIT set_gang_submit; 871 }; 872 873 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 874 }; 875 876 /* 877 * @inv_sel 0-select pasid as input to do the invalidation , 1-select vmid 878 * @flush_type 0-old style, 1-light weight, 2-heavyweight, 3-heavyweight2 879 * @inv_sel_id specific pasid when inv_sel is 0 and specific vmid if inv_sel is 1 880 * @hub_id 0-gc_hub, 1-mm_hub 881 */ 882 struct INV_TLBS { 883 uint8_t inv_sel; 884 uint8_t flush_type; 885 uint16_t inv_sel_id; 886 uint32_t hub_id; 887 /* If following two inv_range setting are all 0 , whole VM will be invalidated, 888 * otherwise only required range be invalidated 889 */ 890 uint64_t inv_range_va_start; 891 uint64_t inv_range_size; 892 uint64_t reserved; 893 }; 894 895 union MESAPI__INV_TLBS { 896 struct { 897 union MES_API_HEADER header; 898 struct MES_API_STATUS api_status; 899 struct INV_TLBS invalidate_tlbs; 900 }; 901 902 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 903 }; 904 905 #pragma pack(pop) 906 907 #endif 908