1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 8) 28 29 #define MES_API_VERSION 0x14 30 31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */ 32 #define AMDGPU_MES_LOG_BUFFER_SIZE 0xC000 33 34 /* Driver submits one API(cmd) as a single Frame and this command size is same for all API 35 * to ease the debugging and parsing of ring buffer. 36 */ 37 enum {API_FRAME_SIZE_IN_DWORDS = 64}; 38 39 /* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in, 40 * this creates another queue 41 */ 42 enum {API_NUMBER_OF_COMMAND_MAX = 32}; 43 44 enum MES_API_TYPE { 45 MES_API_TYPE_SCHEDULER = 1, 46 MES_API_TYPE_MAX 47 }; 48 49 enum MES_SCH_API_OPCODE { 50 MES_SCH_API_SET_HW_RSRC = 0, 51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 52 MES_SCH_API_ADD_QUEUE = 2, 53 MES_SCH_API_REMOVE_QUEUE = 3, 54 MES_SCH_API_PERFORM_YIELD = 4, 55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, /* For windows GANG = Context */ 56 MES_SCH_API_SUSPEND = 6, 57 MES_SCH_API_RESUME = 7, 58 MES_SCH_API_RESET = 8, 59 MES_SCH_API_SET_LOG_BUFFER = 9, 60 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 62 MES_SCH_API_SET_DEBUG_VMID = 13, 63 MES_SCH_API_MISC = 14, 64 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 65 MES_SCH_API_AMD_LOG = 16, 66 MES_SCH_API_SET_SE_MODE = 17, 67 MES_SCH_API_SET_GANG_SUBMIT = 18, 68 MES_SCH_API_SET_HW_RSRC_1 = 19, 69 70 MES_SCH_API_MAX = 0xFF 71 }; 72 73 union MES_API_HEADER { 74 struct { 75 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 76 uint32_t opcode : 8; 77 uint32_t dwsize : 8; /* including header */ 78 uint32_t reserved : 12; 79 }; 80 81 uint32_t u32All; 82 }; 83 84 enum MES_AMD_PRIORITY_LEVEL { 85 AMD_PRIORITY_LEVEL_LOW = 0, 86 AMD_PRIORITY_LEVEL_NORMAL = 1, 87 AMD_PRIORITY_LEVEL_MEDIUM = 2, 88 AMD_PRIORITY_LEVEL_HIGH = 3, 89 AMD_PRIORITY_LEVEL_REALTIME = 4, 90 91 AMD_PRIORITY_NUM_LEVELS 92 }; 93 94 enum MES_QUEUE_TYPE { 95 MES_QUEUE_TYPE_GFX, 96 MES_QUEUE_TYPE_COMPUTE, 97 MES_QUEUE_TYPE_SDMA, 98 99 MES_QUEUE_TYPE_MAX, 100 MES_QUEUE_TYPE_SCHQ = MES_QUEUE_TYPE_MAX, 101 }; 102 103 struct MES_API_STATUS { 104 uint64_t api_completion_fence_addr; 105 uint64_t api_completion_fence_value; 106 }; 107 108 109 enum { MAX_COMPUTE_PIPES = 8 }; 110 enum { MAX_GFX_PIPES = 2 }; 111 enum { MAX_SDMA_PIPES = 2 }; 112 113 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 114 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 115 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 116 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 117 118 119 enum { MAX_QUEUES_IN_A_GANG = 8 }; 120 121 enum VM_HUB_TYPE { 122 VM_HUB_TYPE_GC = 0, 123 VM_HUB_TYPE_MM = 1, 124 125 VM_HUB_TYPE_MAX, 126 }; 127 128 enum { VMID_INVALID = 0xffff }; 129 130 enum { MAX_VMID_GCHUB = 16 }; 131 enum { MAX_VMID_MMHUB = 16 }; 132 133 enum SET_DEBUG_VMID_OPERATIONS { 134 DEBUG_VMID_OP_PROGRAM = 0, 135 DEBUG_VMID_OP_ALLOCATE = 1, 136 DEBUG_VMID_OP_RELEASE = 2, 137 DEBUG_VMID_OP_VM_SETUP = 3 // used to set up the debug vmid page table in the kernel queue case (mode 1) 138 }; 139 140 enum MES_MS_LOG_CONTEXT_STATE { 141 MES_LOG_CONTEXT_STATE_IDLE = 0, 142 MES_LOG_CONTEXT_STATE_RUNNING = 1, 143 MES_LOG_CONTEXT_STATE_READY = 2, 144 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 145 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 146 }; 147 148 enum MES_MS_LOG_OPERATION { 149 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 150 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 151 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 152 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 153 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 154 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 155 }; 156 157 struct MES_LOG_CONTEXT_STATE_CHANGE { 158 uint64_t h_context; 159 enum MES_MS_LOG_CONTEXT_STATE new_context_state; 160 }; 161 162 struct MES_LOG_QUEUE_NEW_WORK { 163 uint64_t h_queue; 164 uint64_t reserved; 165 }; 166 167 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 168 uint64_t h_queue; 169 uint64_t h_sync_object; 170 }; 171 172 struct MES_LOG_QUEUE_NO_MORE_WORK { 173 uint64_t h_queue; 174 uint64_t reserved; 175 }; 176 177 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 178 uint64_t h_queue; 179 uint64_t h_sync_object; 180 }; 181 182 struct MES_LOG_ENTRY_HEADER { 183 uint32_t first_free_entry_index; 184 uint32_t wraparound_count; 185 uint64_t number_of_entries; 186 uint64_t reserved[2]; 187 }; 188 189 struct MES_LOG_ENTRY_DATA { 190 uint64_t gpu_time_stamp; 191 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 192 uint32_t reserved_operation_type_bits; 193 union { 194 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 195 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 196 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 197 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 198 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 199 uint64_t all[2]; 200 }; 201 }; 202 203 struct MES_LOG_BUFFER { 204 struct MES_LOG_ENTRY_HEADER header; 205 struct MES_LOG_ENTRY_DATA entries[]; 206 }; 207 208 enum MES_SWIP_TO_HWIP_DEF { 209 MES_MAX_HWIP_SEGMENT = 8, 210 }; 211 212 union MESAPI_SET_HW_RESOURCES { 213 struct { 214 union MES_API_HEADER header; 215 uint32_t vmid_mask_mmhub; 216 uint32_t vmid_mask_gfxhub; 217 uint32_t gds_size; 218 uint32_t paging_vmid; 219 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 220 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 221 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 222 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 223 uint64_t g_sch_ctx_gpu_mc_ptr; 224 uint64_t query_status_fence_gpu_mc_ptr; 225 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 226 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 227 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 228 struct MES_API_STATUS api_status; 229 union { 230 struct { 231 uint32_t disable_reset : 1; 232 uint32_t use_different_vmid_compute : 1; 233 uint32_t disable_mes_log : 1; 234 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 235 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 236 uint32_t second_gfx_pipe_enabled : 1; 237 uint32_t enable_level_process_quantum_check : 1; 238 uint32_t legacy_sch_mode : 1; 239 uint32_t disable_add_queue_wptr_mc_addr : 1; 240 uint32_t enable_mes_event_int_logging : 1; 241 uint32_t enable_reg_active_poll : 1; 242 uint32_t use_disable_queue_in_legacy_uq_preemption : 1; 243 uint32_t send_write_data : 1; 244 uint32_t os_tdr_timeout_override : 1; 245 uint32_t use_rs64mem_for_proc_gang_ctx : 1; 246 uint32_t halt_on_misaligned_access : 1; 247 uint32_t use_add_queue_unmap_flag_addr : 1; 248 uint32_t enable_mes_sch_stb_log : 1; 249 uint32_t limit_single_process : 1; 250 uint32_t unmapped_doorbell_handling: 2; 251 uint32_t reserved : 11; 252 }; 253 uint32_t uint32_all; 254 }; 255 uint32_t oversubscription_timer; 256 uint64_t doorbell_info; 257 uint64_t event_intr_history_gpu_mc_ptr; 258 uint64_t timestamp; 259 uint32_t os_tdr_timeout_in_sec; 260 }; 261 262 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 263 }; 264 265 union MESAPI_SET_HW_RESOURCES_1 { 266 struct { 267 union MES_API_HEADER header; 268 struct MES_API_STATUS api_status; 269 uint64_t timestamp; 270 union { 271 struct { 272 uint32_t enable_mes_debug_ctx : 1; 273 uint32_t reserved : 31; 274 }; 275 uint32_t uint32_all; 276 }; 277 uint64_t mes_debug_ctx_mc_addr; 278 uint32_t mes_debug_ctx_size; 279 /* unit is 100ms */ 280 uint32_t mes_kiq_unmap_timeout; 281 uint64_t reserved1; 282 uint64_t cleaner_shader_fence_mc_addr; 283 }; 284 285 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 286 }; 287 288 union MESAPI__ADD_QUEUE { 289 struct { 290 union MES_API_HEADER header; 291 uint32_t process_id; 292 uint64_t page_table_base_addr; 293 uint64_t process_va_start; 294 uint64_t process_va_end; 295 uint64_t process_quantum; 296 uint64_t process_context_addr; 297 uint64_t gang_quantum; 298 uint64_t gang_context_addr; 299 uint32_t inprocess_gang_priority; 300 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 301 uint32_t doorbell_offset; 302 uint64_t mqd_addr; 303 /* From MES_API_VERSION 2, mc addr is expected for wptr_addr */ 304 uint64_t wptr_addr; 305 uint64_t h_context; 306 uint64_t h_queue; 307 enum MES_QUEUE_TYPE queue_type; 308 uint32_t gds_base; 309 union { 310 /* backwards compatibility with Linux, remove union once they use kfd_queue_size */ 311 uint32_t gds_size; 312 uint32_t kfd_queue_size; 313 }; 314 uint32_t gws_base; 315 uint32_t gws_size; 316 uint32_t oa_mask; 317 uint64_t trap_handler_addr; 318 uint32_t vm_context_cntl; 319 320 struct { 321 uint32_t paging : 1; 322 uint32_t debug_vmid : 4; 323 uint32_t program_gds : 1; 324 uint32_t is_gang_suspended : 1; 325 uint32_t is_tmz_queue : 1; 326 uint32_t map_kiq_utility_queue : 1; 327 uint32_t is_kfd_process : 1; 328 uint32_t trap_en : 1; 329 uint32_t is_aql_queue : 1; 330 uint32_t skip_process_ctx_clear : 1; 331 uint32_t map_legacy_kq : 1; 332 uint32_t exclusively_scheduled : 1; 333 uint32_t is_long_running : 1; 334 uint32_t is_dwm_queue : 1; 335 uint32_t reserved : 15; 336 }; 337 struct MES_API_STATUS api_status; 338 uint64_t tma_addr; 339 uint32_t sch_id; 340 uint64_t timestamp; 341 uint32_t process_context_array_index; 342 uint32_t gang_context_array_index; 343 uint32_t pipe_id; //used for mapping legacy kernel queue 344 uint32_t queue_id; 345 uint32_t alignment_mode_setting; 346 }; 347 348 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 349 }; 350 351 union MESAPI__REMOVE_QUEUE { 352 struct { 353 union MES_API_HEADER header; 354 uint32_t doorbell_offset; 355 uint64_t gang_context_addr; 356 357 struct { 358 uint32_t reserved01 : 1; 359 uint32_t unmap_kiq_utility_queue : 1; 360 uint32_t preempt_legacy_gfx_queue : 1; 361 uint32_t unmap_legacy_queue : 1; 362 uint32_t reserved : 28; 363 }; 364 struct MES_API_STATUS api_status; 365 366 uint32_t pipe_id; 367 uint32_t queue_id; 368 369 uint64_t tf_addr; 370 uint32_t tf_data; 371 372 enum MES_QUEUE_TYPE queue_type; 373 uint64_t timestamp; 374 uint32_t gang_context_array_index; 375 }; 376 377 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 378 }; 379 380 union MESAPI__SET_SCHEDULING_CONFIG { 381 struct { 382 union MES_API_HEADER header; 383 /* Grace period when preempting another priority band for this priority band. 384 * The value for idle priority band is ignored, as it never preempts other bands. 385 */ 386 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 387 388 /* Default quantum for scheduling across processes within a priority band. */ 389 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 390 391 /* Default grace period for processes that preempt each other within a priority band.*/ 392 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 393 394 /* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level. 395 * Valid values are between 0 and 50, with the default being 10. 396 */ 397 uint32_t normal_yield_percent; 398 399 struct MES_API_STATUS api_status; 400 uint64_t timestamp; 401 }; 402 403 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 404 }; 405 406 union MESAPI__PERFORM_YIELD { 407 struct { 408 union MES_API_HEADER header; 409 uint32_t dummy; 410 struct MES_API_STATUS api_status; 411 uint64_t timestamp; 412 }; 413 414 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 415 }; 416 417 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 418 struct { 419 union MES_API_HEADER header; 420 uint32_t inprocess_gang_priority; 421 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 422 uint64_t gang_quantum; 423 uint64_t gang_context_addr; 424 struct MES_API_STATUS api_status; 425 uint32_t doorbell_offset; 426 uint64_t timestamp; 427 uint32_t gang_context_array_index; 428 struct { 429 uint32_t queue_quantum_scale : 2; 430 uint32_t queue_quantum_duration : 8; 431 uint32_t apply_quantum_all_processes : 1; 432 uint32_t reserved : 21; 433 }; 434 }; 435 436 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 437 }; 438 439 union MESAPI__SUSPEND { 440 struct { 441 union MES_API_HEADER header; 442 /* false - suspend all gangs; true - specific gang */ 443 struct { 444 uint32_t suspend_all_gangs : 1; 445 uint32_t reserved : 31; 446 }; 447 /* gang_context_addr is valid only if suspend_all = false */ 448 449 uint64_t gang_context_addr; 450 451 uint64_t suspend_fence_addr; 452 uint32_t suspend_fence_value; 453 454 struct MES_API_STATUS api_status; 455 456 union { 457 uint32_t return_value; // to be removed 458 uint32_t sch_id; //keep the old return_value temporarily for compatibility 459 }; 460 uint32_t doorbell_offset; 461 uint64_t timestamp; 462 enum MES_QUEUE_TYPE legacy_uq_type; 463 enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level; 464 uint32_t gang_context_array_index; 465 }; 466 467 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 468 }; 469 470 union MESAPI__RESUME { 471 struct { 472 union MES_API_HEADER header; 473 /* false - resume all gangs; true - specified gang */ 474 struct { 475 uint32_t resume_all_gangs : 1; 476 uint32_t reserved : 31; 477 }; 478 /* valid only if resume_all_gangs = false */ 479 uint64_t gang_context_addr; 480 481 struct MES_API_STATUS api_status; 482 uint32_t doorbell_offset; 483 uint64_t timestamp; 484 uint32_t gang_context_array_index; 485 }; 486 487 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 488 }; 489 490 union MESAPI__RESET { 491 struct { 492 union MES_API_HEADER header; 493 494 struct { 495 /* Only reset the queue given by doorbell_offset (not entire gang) */ 496 uint32_t reset_queue_only : 1; 497 /* Hang detection first then reset any queues that are hung */ 498 uint32_t hang_detect_then_reset : 1; 499 /* Only do hang detection (no reset) */ 500 uint32_t hang_detect_only : 1; 501 /* Reset HP and LP kernel queues not managed by MES */ 502 uint32_t reset_legacy_gfx : 1; 503 /* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */ 504 uint32_t use_connected_queue_index : 1; 505 /* For gfx pipe 1 */ 506 uint32_t use_connected_queue_index_p1 : 1; 507 uint32_t reserved : 26; 508 }; 509 510 uint64_t gang_context_addr; 511 512 /* valid only if reset_queue_only = true */ 513 uint32_t doorbell_offset; 514 515 /* valid only if hang_detect_then_reset = true */ 516 uint64_t doorbell_offset_addr; 517 enum MES_QUEUE_TYPE queue_type; 518 519 /* valid only if reset_legacy_gfx = true */ 520 uint32_t pipe_id_lp; 521 uint32_t queue_id_lp; 522 uint32_t vmid_id_lp; 523 uint64_t mqd_mc_addr_lp; 524 uint32_t doorbell_offset_lp; 525 uint64_t wptr_addr_lp; 526 527 uint32_t pipe_id_hp; 528 uint32_t queue_id_hp; 529 uint32_t vmid_id_hp; 530 uint64_t mqd_mc_addr_hp; 531 uint32_t doorbell_offset_hp; 532 uint64_t wptr_addr_hp; 533 534 struct MES_API_STATUS api_status; 535 uint32_t active_vmids; 536 uint64_t timestamp; 537 538 uint32_t gang_context_array_index; 539 540 uint32_t connected_queue_index; 541 uint32_t connected_queue_index_p1; 542 }; 543 544 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 545 }; 546 547 union MESAPI__SET_LOGGING_BUFFER { 548 struct { 549 union MES_API_HEADER header; 550 /* There are separate log buffers for each queue type */ 551 enum MES_QUEUE_TYPE log_type; 552 /* Log buffer GPU Address */ 553 uint64_t logging_buffer_addr; 554 /* number of entries in the log buffer */ 555 uint32_t number_of_entries; 556 /* Entry index at which CPU interrupt needs to be signalled */ 557 uint32_t interrupt_entry; 558 559 struct MES_API_STATUS api_status; 560 uint64_t timestamp; 561 uint32_t vmid; 562 }; 563 564 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 565 }; 566 567 enum MES_API_QUERY_MES_OPCODE { 568 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE, 569 MES_API_QUERY_MES__CHECK_HEALTHY, 570 MES_API_QUERY_MES__MAX, 571 }; 572 573 enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 }; 574 575 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE { 576 uint64_t proc_ctx_array_size_addr; 577 uint64_t gang_ctx_array_size_addr; 578 }; 579 580 struct MES_API_QUERY_MES__HEALTHY_CHECK { 581 uint64_t healthy_addr; 582 }; 583 584 union MESAPI__QUERY_MES_STATUS { 585 struct { 586 union MES_API_HEADER header; 587 enum MES_API_QUERY_MES_OPCODE subopcode; 588 struct MES_API_STATUS api_status; 589 uint64_t timestamp; 590 union { 591 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size; 592 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check; 593 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS]; 594 }; 595 }; 596 597 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 598 }; 599 600 union MESAPI__SET_DEBUG_VMID { 601 struct { 602 union MES_API_HEADER header; 603 struct MES_API_STATUS api_status; 604 union { 605 struct { 606 uint32_t use_gds : 1; 607 uint32_t operation : 2; 608 uint32_t reserved : 29; 609 } flags; 610 uint32_t u32All; 611 }; 612 uint32_t reserved; 613 uint32_t debug_vmid; 614 uint64_t process_context_addr; 615 uint64_t page_table_base_addr; 616 uint64_t process_va_start; 617 uint64_t process_va_end; 618 uint32_t gds_base; 619 uint32_t gds_size; 620 uint32_t gws_base; 621 uint32_t gws_size; 622 uint32_t oa_mask; 623 624 uint64_t output_addr; // output addr of the acquired vmid value 625 626 uint64_t timestamp; 627 628 uint32_t process_vm_cntl; 629 enum MES_QUEUE_TYPE queue_type; 630 631 uint32_t process_context_array_index; 632 633 uint32_t alignment_mode_setting; 634 }; 635 636 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 637 }; 638 639 enum MESAPI_MISC_OPCODE { 640 MESAPI_MISC__WRITE_REG, 641 MESAPI_MISC__INV_GART, 642 MESAPI_MISC__QUERY_STATUS, 643 MESAPI_MISC__READ_REG, 644 MESAPI_MISC__WAIT_REG_MEM, 645 MESAPI_MISC__SET_SHADER_DEBUGGER, 646 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE, 647 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES, 648 MESAPI_MISC__QUERY_HUNG_ENGINE_ID, 649 MESAPI_MISC__CHANGE_CONFIG, 650 MESAPI_MISC__LAUNCH_CLEANER_SHADER, 651 MESAPI_MISC__SETUP_MES_DBGEXT, 652 653 MESAPI_MISC__MAX, 654 }; 655 656 enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20}; 657 658 struct WRITE_REG { 659 uint32_t reg_offset; 660 uint32_t reg_value; 661 }; 662 663 struct READ_REG { 664 uint32_t reg_offset; 665 uint64_t buffer_addr; 666 union { 667 struct { 668 uint32_t read64Bits : 1; 669 uint32_t reserved : 31; 670 } bits; 671 uint32_t all; 672 } option; 673 }; 674 675 struct INV_GART { 676 uint64_t inv_range_va_start; 677 uint64_t inv_range_size; 678 }; 679 680 struct QUERY_STATUS { 681 uint32_t context_id; 682 }; 683 684 enum WRM_OPERATION { 685 WRM_OPERATION__WAIT_REG_MEM, 686 WRM_OPERATION__WR_WAIT_WR_REG, 687 688 WRM_OPERATION__MAX, 689 }; 690 691 struct WAIT_REG_MEM { 692 enum WRM_OPERATION op; 693 /* only function = equal_to_the_reference_value and mem_space = register_space supported for now */ 694 uint32_t reference; 695 uint32_t mask; 696 uint32_t reg_offset1; 697 uint32_t reg_offset2; 698 }; 699 700 struct SET_SHADER_DEBUGGER { 701 uint64_t process_context_addr; 702 union { 703 struct { 704 uint32_t single_memop : 1; // SQ_DEBUG.single_memop 705 uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op 706 uint32_t reserved : 30; 707 }; 708 uint32_t u32all; 709 } flags; 710 uint32_t spi_gdbg_per_vmid_cntl; 711 uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL 712 uint32_t trap_en; 713 }; 714 715 struct SET_GANG_SUBMIT { 716 uint64_t gang_context_addr; 717 uint64_t slave_gang_context_addr; 718 uint32_t gang_context_array_index; 719 uint32_t slave_gang_context_array_index; 720 }; 721 722 enum MESAPI_MISC__CHANGE_CONFIG_OPTION { 723 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0, 724 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1, 725 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2, 726 727 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F 728 }; 729 730 struct CHANGE_CONFIG { 731 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode; 732 union { 733 struct { 734 uint32_t limit_single_process : 1; 735 uint32_t enable_hws_logging_buffer : 1; 736 uint32_t reserved : 30; 737 } bits; 738 uint32_t all; 739 } option; 740 741 struct { 742 uint32_t tdr_level; 743 uint32_t tdr_delay; 744 } tdr_config; 745 }; 746 747 union MESAPI__MISC { 748 struct { 749 union MES_API_HEADER header; 750 enum MESAPI_MISC_OPCODE opcode; 751 struct MES_API_STATUS api_status; 752 union { 753 struct WRITE_REG write_reg; 754 struct INV_GART inv_gart; 755 struct QUERY_STATUS query_status; 756 struct READ_REG read_reg; 757 struct WAIT_REG_MEM wait_reg_mem; 758 struct SET_SHADER_DEBUGGER set_shader_debugger; 759 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 760 struct CHANGE_CONFIG change_config; 761 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 762 }; 763 uint64_t timestamp; 764 uint32_t doorbell_offset; 765 uint32_t os_fence; 766 }; 767 768 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 769 }; 770 771 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 772 struct { 773 union MES_API_HEADER header; 774 uint64_t page_table_base_addr; 775 uint64_t process_context_addr; 776 struct MES_API_STATUS api_status; 777 uint64_t timestamp; 778 uint32_t process_context_array_index; 779 }; 780 781 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 782 }; 783 784 union MESAPI_AMD_LOG { 785 struct { 786 union MES_API_HEADER header; 787 uint64_t p_buffer_memory; 788 uint64_t p_buffer_size_used; 789 struct MES_API_STATUS api_status; 790 uint64_t timestamp; 791 }; 792 793 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 794 }; 795 796 enum MES_SE_MODE { 797 MES_SE_MODE_INVALID = 0, 798 MES_SE_MODE_SINGLE_SE = 1, 799 MES_SE_MODE_DUAL_SE = 2, 800 MES_SE_MODE_LOWER_POWER = 3, 801 }; 802 803 union MESAPI__SET_SE_MODE { 804 struct { 805 union MES_API_HEADER header; 806 /* the new SE mode to apply*/ 807 enum MES_SE_MODE new_se_mode; 808 /* the fence to make sure the ItCpgCtxtSync packet is completed */ 809 uint64_t cpg_ctxt_sync_fence_addr; 810 uint32_t cpg_ctxt_sync_fence_value; 811 /* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */ 812 union { 813 struct { 814 uint32_t log_seq_time : 1; 815 uint32_t reserved : 31; 816 }; 817 uint32_t uint32_all; 818 }; 819 struct MES_API_STATUS api_status; 820 }; 821 822 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 823 }; 824 825 union MESAPI__SET_GANG_SUBMIT { 826 struct { 827 union MES_API_HEADER header; 828 struct MES_API_STATUS api_status; 829 struct SET_GANG_SUBMIT set_gang_submit; 830 }; 831 832 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 833 }; 834 835 #pragma pack(pop) 836 837 #endif 838