1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 8) 28 29 #define MES_API_VERSION 0x14 30 31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */ 32 #define AMDGPU_MES_LOG_BUFFER_SIZE 0xC000 33 34 /* Driver submits one API(cmd) as a single Frame and this command size is same for all API 35 * to ease the debugging and parsing of ring buffer. 36 */ 37 enum {API_FRAME_SIZE_IN_DWORDS = 64}; 38 39 /* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in, 40 * this creates another queue 41 */ 42 enum {API_NUMBER_OF_COMMAND_MAX = 32}; 43 44 enum MES_API_TYPE { 45 MES_API_TYPE_SCHEDULER = 1, 46 MES_API_TYPE_MAX 47 }; 48 49 enum MES_SCH_API_OPCODE { 50 MES_SCH_API_SET_HW_RSRC = 0, 51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 52 MES_SCH_API_ADD_QUEUE = 2, 53 MES_SCH_API_REMOVE_QUEUE = 3, 54 MES_SCH_API_PERFORM_YIELD = 4, 55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, /* For windows GANG = Context */ 56 MES_SCH_API_SUSPEND = 6, 57 MES_SCH_API_RESUME = 7, 58 MES_SCH_API_RESET = 8, 59 MES_SCH_API_SET_LOG_BUFFER = 9, 60 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 62 MES_SCH_API_SET_DEBUG_VMID = 13, 63 MES_SCH_API_MISC = 14, 64 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 65 MES_SCH_API_AMD_LOG = 16, 66 MES_SCH_API_SET_SE_MODE = 17, 67 MES_SCH_API_SET_GANG_SUBMIT = 18, 68 MES_SCH_API_SET_HW_RSRC_1 = 19, 69 MES_SCH_API_INV_TLBS = 20, 70 71 MES_SCH_API_MAX = 0xFF 72 }; 73 74 enum MES_RRMT_MODE { 75 MES_RRMT_MODE_LOCAL_XCD, 76 MES_RRMT_MODE_LOCAL_REMOTE_AID, 77 MES_RRMT_MODE_REMOTE_XCD, 78 MES_RRMT_MODE_REMOTE_MID 79 }; 80 81 union MES_API_HEADER { 82 struct { 83 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 84 uint32_t opcode : 8; 85 uint32_t dwsize : 8; /* including header */ 86 uint32_t reserved : 12; 87 }; 88 89 uint32_t u32All; 90 }; 91 92 enum MES_AMD_PRIORITY_LEVEL { 93 AMD_PRIORITY_LEVEL_LOW = 0, 94 AMD_PRIORITY_LEVEL_NORMAL = 1, 95 AMD_PRIORITY_LEVEL_MEDIUM = 2, 96 AMD_PRIORITY_LEVEL_HIGH = 3, 97 AMD_PRIORITY_LEVEL_REALTIME = 4, 98 99 AMD_PRIORITY_NUM_LEVELS 100 }; 101 102 enum MES_QUEUE_TYPE { 103 MES_QUEUE_TYPE_GFX, 104 MES_QUEUE_TYPE_COMPUTE, 105 MES_QUEUE_TYPE_SDMA, 106 107 MES_QUEUE_TYPE_MAX, 108 MES_QUEUE_TYPE_SCHQ = MES_QUEUE_TYPE_MAX, 109 }; 110 111 struct MES_API_STATUS { 112 uint64_t api_completion_fence_addr; 113 uint64_t api_completion_fence_value; 114 }; 115 116 /* 117 * MES will set api_completion_fence_value in api_completion_fence_addr 118 * when it can successflly process the API. MES will also trigger 119 * following interrupt when it finish process the API no matter success 120 * or failed. 121 * Interrupt source id 181 (EOP) with context ID (DW 6 in the int 122 * cookie) set to 0xb1 and context type set to 8. Driver side need 123 * to enable TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to 124 * catch this interrupt. 125 * Driver side also need to set enable_mes_fence_int = 1 in 126 * set_HW_resource package to enable this fence interrupt. 127 * when the API process failed. 128 * lowre 32 bits set to 0. 129 * higher 32 bits set as follows (bit shift within high 32) 130 * bit 0 - 7 API specific error code. 131 * bit 8 - 15 API OPCODE. 132 * bit 16 - 23 MISC OPCODE if any 133 * bit 24 - 30 ERROR category (API_ERROR_XXX) 134 * bit 31 Set to 1 to indicate error status 135 * 136 */ 137 enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 }; 138 enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 }; 139 enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 }; 140 enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 }; 141 142 enum MES_ERROR_CATEGORY_CODE_12 { 143 MES_ERROR_API = 1, 144 MES_ERROR_SCHEDULING = 2, 145 MES_ERROR_UNKNOWN = 3, 146 }; 147 148 #define MES_ERR_CODE(api_err, opcode, misc_op, category) \ 149 ((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \ 150 misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \ 151 category << MES_ERROR_CATEGORY_SHIFT_12 | \ 152 1 << MES_API_STATUS_ERROR_SHIFT_12) << 32) 153 154 enum { MAX_COMPUTE_PIPES = 8 }; 155 enum { MAX_GFX_PIPES = 2 }; 156 enum { MAX_SDMA_PIPES = 2 }; 157 158 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 159 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 160 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 161 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 162 163 164 enum { MAX_QUEUES_IN_A_GANG = 8 }; 165 166 enum VM_HUB_TYPE { 167 VM_HUB_TYPE_GC = 0, 168 VM_HUB_TYPE_MM = 1, 169 170 VM_HUB_TYPE_MAX, 171 }; 172 173 enum { VMID_INVALID = 0xffff }; 174 175 enum { MAX_VMID_GCHUB = 16 }; 176 enum { MAX_VMID_MMHUB = 16 }; 177 178 enum SET_DEBUG_VMID_OPERATIONS { 179 DEBUG_VMID_OP_PROGRAM = 0, 180 DEBUG_VMID_OP_ALLOCATE = 1, 181 DEBUG_VMID_OP_RELEASE = 2, 182 DEBUG_VMID_OP_VM_SETUP = 3 // used to set up the debug vmid page table in the kernel queue case (mode 1) 183 }; 184 185 enum MES_MS_LOG_CONTEXT_STATE { 186 MES_LOG_CONTEXT_STATE_IDLE = 0, 187 MES_LOG_CONTEXT_STATE_RUNNING = 1, 188 MES_LOG_CONTEXT_STATE_READY = 2, 189 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 190 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 191 }; 192 193 enum MES_MS_LOG_OPERATION { 194 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 195 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 196 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 197 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 198 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 199 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 200 }; 201 202 struct MES_LOG_CONTEXT_STATE_CHANGE { 203 uint64_t h_context; 204 enum MES_MS_LOG_CONTEXT_STATE new_context_state; 205 }; 206 207 struct MES_LOG_QUEUE_NEW_WORK { 208 uint64_t h_queue; 209 uint64_t reserved; 210 }; 211 212 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 213 uint64_t h_queue; 214 uint64_t h_sync_object; 215 }; 216 217 struct MES_LOG_QUEUE_NO_MORE_WORK { 218 uint64_t h_queue; 219 uint64_t reserved; 220 }; 221 222 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 223 uint64_t h_queue; 224 uint64_t h_sync_object; 225 }; 226 227 struct MES_LOG_ENTRY_HEADER { 228 uint32_t first_free_entry_index; 229 uint32_t wraparound_count; 230 uint64_t number_of_entries; 231 uint64_t reserved[2]; 232 }; 233 234 struct MES_LOG_ENTRY_DATA { 235 uint64_t gpu_time_stamp; 236 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 237 uint32_t reserved_operation_type_bits; 238 union { 239 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 240 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 241 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 242 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 243 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 244 uint64_t all[2]; 245 }; 246 }; 247 248 struct MES_LOG_BUFFER { 249 struct MES_LOG_ENTRY_HEADER header; 250 struct MES_LOG_ENTRY_DATA entries[]; 251 }; 252 253 enum MES_SWIP_TO_HWIP_DEF { 254 MES_MAX_HWIP_SEGMENT = 8, 255 }; 256 257 union MESAPI_SET_HW_RESOURCES { 258 struct { 259 union MES_API_HEADER header; 260 uint32_t vmid_mask_mmhub; 261 uint32_t vmid_mask_gfxhub; 262 uint32_t gds_size; 263 uint32_t paging_vmid; 264 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 265 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 266 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 267 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 268 uint64_t g_sch_ctx_gpu_mc_ptr; 269 uint64_t query_status_fence_gpu_mc_ptr; 270 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 271 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 272 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 273 struct MES_API_STATUS api_status; 274 union { 275 struct { 276 uint32_t disable_reset : 1; 277 uint32_t use_different_vmid_compute : 1; 278 uint32_t disable_mes_log : 1; 279 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 280 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 281 uint32_t second_gfx_pipe_enabled : 1; 282 uint32_t enable_level_process_quantum_check : 1; 283 uint32_t legacy_sch_mode : 1; 284 uint32_t disable_add_queue_wptr_mc_addr : 1; 285 uint32_t enable_mes_event_int_logging : 1; 286 uint32_t enable_reg_active_poll : 1; 287 uint32_t use_disable_queue_in_legacy_uq_preemption : 1; 288 uint32_t send_write_data : 1; 289 uint32_t os_tdr_timeout_override : 1; 290 uint32_t use_rs64mem_for_proc_gang_ctx : 1; 291 uint32_t halt_on_misaligned_access : 1; 292 uint32_t use_add_queue_unmap_flag_addr : 1; 293 uint32_t enable_mes_sch_stb_log : 1; 294 uint32_t limit_single_process : 1; 295 uint32_t unmapped_doorbell_handling: 2; 296 uint32_t enable_mes_fence_int: 1; 297 uint32_t enable_lr_compute_wa : 1; 298 uint32_t reserved : 9; 299 }; 300 uint32_t uint32_all; 301 }; 302 uint32_t oversubscription_timer; 303 uint64_t doorbell_info; 304 uint64_t event_intr_history_gpu_mc_ptr; 305 uint64_t timestamp; 306 uint32_t os_tdr_timeout_in_sec; 307 }; 308 309 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 310 }; 311 312 union MESAPI_SET_HW_RESOURCES_1 { 313 struct { 314 union MES_API_HEADER header; 315 struct MES_API_STATUS api_status; 316 uint64_t timestamp; 317 union { 318 struct { 319 uint32_t enable_mes_debug_ctx : 1; 320 uint32_t mes_coop_mode : 1; /* 0: non-coop; 1: coop */ 321 uint32_t reserved : 30; 322 }; 323 uint32_t uint32_all; 324 }; 325 uint64_t mes_debug_ctx_mc_addr; 326 uint32_t mes_debug_ctx_size; 327 /* unit is 100ms */ 328 uint32_t mes_kiq_unmap_timeout; 329 /* shared buffer of master/slaves, valid if mes_coop_mode=1 */ 330 uint64_t coop_sch_shared_mc_addr; 331 uint64_t cleaner_shader_fence_mc_addr; 332 }; 333 334 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 335 }; 336 337 union MESAPI__ADD_QUEUE { 338 struct { 339 union MES_API_HEADER header; 340 uint32_t process_id; 341 uint64_t page_table_base_addr; 342 uint64_t process_va_start; 343 uint64_t process_va_end; 344 uint64_t process_quantum; 345 uint64_t process_context_addr; 346 uint64_t gang_quantum; 347 uint64_t gang_context_addr; 348 uint32_t inprocess_gang_priority; 349 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 350 uint32_t doorbell_offset; 351 uint64_t mqd_addr; 352 /* From MES_API_VERSION 2, mc addr is expected for wptr_addr */ 353 uint64_t wptr_addr; 354 uint64_t h_context; 355 uint64_t h_queue; 356 enum MES_QUEUE_TYPE queue_type; 357 uint32_t gds_base; 358 union { 359 /* backwards compatibility with Linux, remove union once they use kfd_queue_size */ 360 uint32_t gds_size; 361 uint32_t kfd_queue_size; 362 }; 363 uint32_t gws_base; 364 uint32_t gws_size; 365 uint32_t oa_mask; 366 uint64_t trap_handler_addr; 367 uint32_t vm_context_cntl; 368 369 struct { 370 uint32_t paging : 1; 371 uint32_t debug_vmid : 4; 372 uint32_t program_gds : 1; 373 uint32_t is_gang_suspended : 1; 374 uint32_t is_tmz_queue : 1; 375 uint32_t map_kiq_utility_queue : 1; 376 uint32_t is_kfd_process : 1; 377 uint32_t trap_en : 1; 378 uint32_t is_aql_queue : 1; 379 uint32_t skip_process_ctx_clear : 1; 380 uint32_t map_legacy_kq : 1; 381 uint32_t exclusively_scheduled : 1; 382 uint32_t is_long_running : 1; 383 uint32_t is_dwm_queue : 1; 384 uint32_t reserved : 15; 385 }; 386 struct MES_API_STATUS api_status; 387 uint64_t tma_addr; 388 uint32_t sch_id; 389 uint64_t timestamp; 390 uint32_t process_context_array_index; 391 uint32_t gang_context_array_index; 392 uint32_t pipe_id; //used for mapping legacy kernel queue 393 uint32_t queue_id; 394 uint32_t alignment_mode_setting; 395 uint32_t full_sh_mem_config_data; 396 }; 397 398 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 399 }; 400 401 union MESAPI__REMOVE_QUEUE { 402 struct { 403 union MES_API_HEADER header; 404 uint32_t doorbell_offset; 405 uint64_t gang_context_addr; 406 407 struct { 408 uint32_t reserved01 : 1; 409 uint32_t unmap_kiq_utility_queue : 1; 410 uint32_t preempt_legacy_gfx_queue : 1; 411 uint32_t unmap_legacy_queue : 1; 412 uint32_t remove_queue_after_reset : 1; 413 uint32_t reserved : 27; 414 }; 415 struct MES_API_STATUS api_status; 416 417 uint32_t pipe_id; 418 uint32_t queue_id; 419 420 uint64_t tf_addr; 421 uint32_t tf_data; 422 423 enum MES_QUEUE_TYPE queue_type; 424 uint64_t timestamp; 425 uint32_t gang_context_array_index; 426 }; 427 428 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 429 }; 430 431 union MESAPI__SET_SCHEDULING_CONFIG { 432 struct { 433 union MES_API_HEADER header; 434 /* Grace period when preempting another priority band for this priority band. 435 * The value for idle priority band is ignored, as it never preempts other bands. 436 */ 437 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 438 439 /* Default quantum for scheduling across processes within a priority band. */ 440 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 441 442 /* Default grace period for processes that preempt each other within a priority band.*/ 443 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 444 445 /* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level. 446 * Valid values are between 0 and 50, with the default being 10. 447 */ 448 uint32_t normal_yield_percent; 449 450 struct MES_API_STATUS api_status; 451 uint64_t timestamp; 452 }; 453 454 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 455 }; 456 457 union MESAPI__PERFORM_YIELD { 458 struct { 459 union MES_API_HEADER header; 460 uint32_t dummy; 461 struct MES_API_STATUS api_status; 462 uint64_t timestamp; 463 }; 464 465 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 466 }; 467 468 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 469 struct { 470 union MES_API_HEADER header; 471 uint32_t inprocess_gang_priority; 472 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 473 uint64_t gang_quantum; 474 uint64_t gang_context_addr; 475 struct MES_API_STATUS api_status; 476 uint32_t doorbell_offset; 477 uint64_t timestamp; 478 uint32_t gang_context_array_index; 479 struct { 480 uint32_t queue_quantum_scale : 2; 481 uint32_t queue_quantum_duration : 8; 482 uint32_t apply_quantum_all_processes : 1; 483 uint32_t reserved : 21; 484 }; 485 }; 486 487 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 488 }; 489 490 union MESAPI__SUSPEND { 491 struct { 492 union MES_API_HEADER header; 493 /* false - suspend all gangs; true - specific gang */ 494 struct { 495 uint32_t suspend_all_gangs : 1; 496 uint32_t reserved : 31; 497 }; 498 /* gang_context_addr is valid only if suspend_all = false */ 499 500 uint64_t gang_context_addr; 501 502 uint64_t suspend_fence_addr; 503 uint32_t suspend_fence_value; 504 505 struct MES_API_STATUS api_status; 506 507 union { 508 uint32_t return_value; // to be removed 509 uint32_t sch_id; //keep the old return_value temporarily for compatibility 510 }; 511 uint32_t doorbell_offset; 512 uint64_t timestamp; 513 enum MES_QUEUE_TYPE legacy_uq_type; 514 enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level; 515 uint32_t gang_context_array_index; 516 }; 517 518 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 519 }; 520 521 union MESAPI__RESUME { 522 struct { 523 union MES_API_HEADER header; 524 /* false - resume all gangs; true - specified gang */ 525 struct { 526 uint32_t resume_all_gangs : 1; 527 uint32_t reserved : 31; 528 }; 529 /* valid only if resume_all_gangs = false */ 530 uint64_t gang_context_addr; 531 532 struct MES_API_STATUS api_status; 533 uint32_t doorbell_offset; 534 uint64_t timestamp; 535 uint32_t gang_context_array_index; 536 }; 537 538 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 539 }; 540 541 union MESAPI__RESET { 542 struct { 543 union MES_API_HEADER header; 544 545 struct { 546 /* Only reset the queue given by doorbell_offset (not entire gang) */ 547 uint32_t reset_queue_only : 1; 548 /* Hang detection first then reset any queues that are hung */ 549 uint32_t hang_detect_then_reset : 1; 550 /* Only do hang detection (no reset) */ 551 uint32_t hang_detect_only : 1; 552 /* Reset HP and LP kernel queues not managed by MES */ 553 uint32_t reset_legacy_gfx : 1; 554 /* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */ 555 uint32_t use_connected_queue_index : 1; 556 /* For gfx pipe 1 */ 557 uint32_t use_connected_queue_index_p1 : 1; 558 uint32_t reserved : 26; 559 }; 560 561 uint64_t gang_context_addr; 562 563 /* valid only if reset_queue_only = true */ 564 uint32_t doorbell_offset; 565 566 /* valid only if hang_detect_then_reset = true */ 567 uint64_t doorbell_offset_addr; 568 enum MES_QUEUE_TYPE queue_type; 569 570 /* valid only if reset_legacy_gfx = true */ 571 uint32_t pipe_id_lp; 572 uint32_t queue_id_lp; 573 uint32_t vmid_id_lp; 574 uint64_t mqd_mc_addr_lp; 575 uint32_t doorbell_offset_lp; 576 uint64_t wptr_addr_lp; 577 578 uint32_t pipe_id_hp; 579 uint32_t queue_id_hp; 580 uint32_t vmid_id_hp; 581 uint64_t mqd_mc_addr_hp; 582 uint32_t doorbell_offset_hp; 583 uint64_t wptr_addr_hp; 584 585 struct MES_API_STATUS api_status; 586 uint32_t active_vmids; 587 uint64_t timestamp; 588 589 uint32_t gang_context_array_index; 590 591 uint32_t connected_queue_index; 592 uint32_t connected_queue_index_p1; 593 }; 594 595 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 596 }; 597 598 union MESAPI__SET_LOGGING_BUFFER { 599 struct { 600 union MES_API_HEADER header; 601 /* There are separate log buffers for each queue type */ 602 enum MES_QUEUE_TYPE log_type; 603 /* Log buffer GPU Address */ 604 uint64_t logging_buffer_addr; 605 /* number of entries in the log buffer */ 606 uint32_t number_of_entries; 607 /* Entry index at which CPU interrupt needs to be signalled */ 608 uint32_t interrupt_entry; 609 610 struct MES_API_STATUS api_status; 611 uint64_t timestamp; 612 uint32_t vmid; 613 }; 614 615 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 616 }; 617 618 enum MES_API_QUERY_MES_OPCODE { 619 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE, 620 MES_API_QUERY_MES__CHECK_HEALTHY, 621 MES_API_QUERY_MES__MAX, 622 }; 623 624 enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 }; 625 626 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE { 627 uint64_t proc_ctx_array_size_addr; 628 uint64_t gang_ctx_array_size_addr; 629 }; 630 631 struct MES_API_QUERY_MES__HEALTHY_CHECK { 632 uint64_t healthy_addr; 633 }; 634 635 union MESAPI__QUERY_MES_STATUS { 636 struct { 637 union MES_API_HEADER header; 638 enum MES_API_QUERY_MES_OPCODE subopcode; 639 struct MES_API_STATUS api_status; 640 uint64_t timestamp; 641 union { 642 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size; 643 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check; 644 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS]; 645 }; 646 }; 647 648 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 649 }; 650 651 union MESAPI__SET_DEBUG_VMID { 652 struct { 653 union MES_API_HEADER header; 654 struct MES_API_STATUS api_status; 655 union { 656 struct { 657 uint32_t use_gds : 1; 658 uint32_t operation : 2; 659 uint32_t reserved : 29; 660 } flags; 661 uint32_t u32All; 662 }; 663 uint32_t reserved; 664 uint32_t debug_vmid; 665 uint64_t process_context_addr; 666 uint64_t page_table_base_addr; 667 uint64_t process_va_start; 668 uint64_t process_va_end; 669 uint32_t gds_base; 670 uint32_t gds_size; 671 uint32_t gws_base; 672 uint32_t gws_size; 673 uint32_t oa_mask; 674 675 uint64_t output_addr; // output addr of the acquired vmid value 676 677 uint64_t timestamp; 678 679 uint32_t process_vm_cntl; 680 enum MES_QUEUE_TYPE queue_type; 681 682 uint32_t process_context_array_index; 683 684 uint32_t alignment_mode_setting; 685 uint32_t full_sh_mem_config_data; 686 }; 687 688 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 689 }; 690 691 enum MESAPI_MISC_OPCODE { 692 MESAPI_MISC__WRITE_REG, 693 MESAPI_MISC__INV_GART, 694 MESAPI_MISC__QUERY_STATUS, 695 MESAPI_MISC__READ_REG, 696 MESAPI_MISC__WAIT_REG_MEM, 697 MESAPI_MISC__SET_SHADER_DEBUGGER, 698 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE, 699 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES, 700 MESAPI_MISC__QUERY_HUNG_ENGINE_ID, 701 MESAPI_MISC__CHANGE_CONFIG, 702 MESAPI_MISC__LAUNCH_CLEANER_SHADER, 703 MESAPI_MISC__SETUP_MES_DBGEXT, 704 705 MESAPI_MISC__MAX, 706 }; 707 708 enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20}; 709 710 /* 711 * RRMT(Register Remapping Table), allow the firmware to modify the upper 712 * address to correctly steer the register transaction to expected DIE 713 */ 714 struct RRMT_OPTION { 715 union { 716 struct { 717 uint32_t mode : 4; 718 uint32_t mid_die_id : 4; 719 uint32_t xcd_die_id : 4; 720 }; 721 uint32_t all; 722 }; 723 }; 724 725 726 struct WRITE_REG { 727 uint32_t reg_offset; 728 uint32_t reg_value; 729 struct RRMT_OPTION rrmt_opt; 730 }; 731 732 struct READ_REG { 733 uint32_t reg_offset; 734 uint64_t buffer_addr; 735 union { 736 struct { 737 uint32_t read64Bits : 1; 738 uint32_t reserved : 31; 739 } bits; 740 uint32_t all; 741 } option; 742 struct RRMT_OPTION rrmt_opt; 743 }; 744 745 struct INV_GART { 746 uint64_t inv_range_va_start; 747 uint64_t inv_range_size; 748 }; 749 750 struct QUERY_STATUS { 751 uint32_t context_id; 752 }; 753 754 enum WRM_OPERATION { 755 WRM_OPERATION__WAIT_REG_MEM, 756 WRM_OPERATION__WR_WAIT_WR_REG, 757 758 WRM_OPERATION__MAX, 759 }; 760 761 struct WAIT_REG_MEM { 762 enum WRM_OPERATION op; 763 /* only function = equal_to_the_reference_value and mem_space = register_space supported for now */ 764 uint32_t reference; 765 uint32_t mask; 766 uint32_t reg_offset1; 767 uint32_t reg_offset2; 768 struct RRMT_OPTION rrmt_opt1; /* for reg1 */ 769 struct RRMT_OPTION rrmt_opt2; /* for reg2 */ 770 }; 771 772 struct SET_SHADER_DEBUGGER { 773 uint64_t process_context_addr; 774 union { 775 struct { 776 uint32_t single_memop : 1; // SQ_DEBUG.single_memop 777 uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op 778 uint32_t reserved : 30; 779 }; 780 uint32_t u32all; 781 } flags; 782 uint32_t spi_gdbg_per_vmid_cntl; 783 uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL 784 uint32_t trap_en; 785 }; 786 787 struct SET_GANG_SUBMIT { 788 uint64_t gang_context_addr; 789 uint64_t slave_gang_context_addr; 790 uint32_t gang_context_array_index; 791 uint32_t slave_gang_context_array_index; 792 }; 793 794 enum MESAPI_MISC__CHANGE_CONFIG_OPTION { 795 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0, 796 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1, 797 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2, 798 799 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F 800 }; 801 802 struct CHANGE_CONFIG { 803 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode; 804 union { 805 struct { 806 uint32_t limit_single_process : 1; 807 uint32_t enable_hws_logging_buffer : 1; 808 uint32_t reserved : 30; 809 } bits; 810 uint32_t all; 811 } option; 812 813 struct { 814 uint32_t tdr_level; 815 uint32_t tdr_delay; 816 } tdr_config; 817 }; 818 819 union MESAPI__MISC { 820 struct { 821 union MES_API_HEADER header; 822 enum MESAPI_MISC_OPCODE opcode; 823 struct MES_API_STATUS api_status; 824 union { 825 struct WRITE_REG write_reg; 826 struct INV_GART inv_gart; 827 struct QUERY_STATUS query_status; 828 struct READ_REG read_reg; 829 struct WAIT_REG_MEM wait_reg_mem; 830 struct SET_SHADER_DEBUGGER set_shader_debugger; 831 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 832 struct CHANGE_CONFIG change_config; 833 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 834 }; 835 uint64_t timestamp; 836 uint32_t doorbell_offset; 837 uint32_t os_fence; 838 }; 839 840 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 841 }; 842 843 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 844 struct { 845 union MES_API_HEADER header; 846 uint64_t page_table_base_addr; 847 uint64_t process_context_addr; 848 struct MES_API_STATUS api_status; 849 uint64_t timestamp; 850 uint32_t process_context_array_index; 851 }; 852 853 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 854 }; 855 856 union MESAPI_AMD_LOG { 857 struct { 858 union MES_API_HEADER header; 859 uint64_t p_buffer_memory; 860 uint64_t p_buffer_size_used; 861 struct MES_API_STATUS api_status; 862 uint64_t timestamp; 863 }; 864 865 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 866 }; 867 868 enum MES_SE_MODE { 869 MES_SE_MODE_INVALID = 0, 870 MES_SE_MODE_SINGLE_SE = 1, 871 MES_SE_MODE_DUAL_SE = 2, 872 MES_SE_MODE_LOWER_POWER = 3, 873 }; 874 875 union MESAPI__SET_SE_MODE { 876 struct { 877 union MES_API_HEADER header; 878 /* the new SE mode to apply*/ 879 enum MES_SE_MODE new_se_mode; 880 /* the fence to make sure the ItCpgCtxtSync packet is completed */ 881 uint64_t cpg_ctxt_sync_fence_addr; 882 uint32_t cpg_ctxt_sync_fence_value; 883 /* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */ 884 union { 885 struct { 886 uint32_t log_seq_time : 1; 887 uint32_t reserved : 31; 888 }; 889 uint32_t uint32_all; 890 }; 891 struct MES_API_STATUS api_status; 892 }; 893 894 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 895 }; 896 897 union MESAPI__SET_GANG_SUBMIT { 898 struct { 899 union MES_API_HEADER header; 900 struct MES_API_STATUS api_status; 901 struct SET_GANG_SUBMIT set_gang_submit; 902 }; 903 904 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 905 }; 906 907 /* 908 * @inv_sel 0-select pasid as input to do the invalidation , 1-select vmid 909 * @flush_type 0-old style, 1-light weight, 2-heavyweight, 3-heavyweight2 910 * @inv_sel_id specific pasid when inv_sel is 0 and specific vmid if inv_sel is 1 911 * @hub_id 0-gc_hub, 1-mm_hub 912 */ 913 struct INV_TLBS { 914 uint8_t inv_sel; 915 uint8_t flush_type; 916 uint16_t inv_sel_id; 917 uint32_t hub_id; 918 /* If following two inv_range setting are all 0 , whole VM will be invalidated, 919 * otherwise only required range be invalidated 920 */ 921 uint64_t inv_range_va_start; 922 uint64_t inv_range_size; 923 uint64_t reserved; 924 }; 925 926 union MESAPI__INV_TLBS { 927 struct { 928 union MES_API_HEADER header; 929 struct MES_API_STATUS api_status; 930 struct INV_TLBS invalidate_tlbs; 931 }; 932 933 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 934 }; 935 936 #pragma pack(pop) 937 938 #endif 939