xref: /linux/drivers/gpu/drm/amd/include/mes_v12_api_def.h (revision 44343e8b250abb2f6bfd615493ca07a7f11f3cc2)
1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __MES_API_DEF_H__
25 #define __MES_API_DEF_H__
26 
27 #pragma pack(push, 8)
28 
29 #define MES_API_VERSION 0x14
30 
31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */
32 #define  AMDGPU_MES_LOG_BUFFER_SIZE  0xC000
33 
34 /* Driver submits one API(cmd) as a single Frame and this command size is same for all API
35  * to ease the debugging and parsing of ring buffer.
36  */
37 enum {API_FRAME_SIZE_IN_DWORDS = 64};
38 
39 /* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in,
40  * this creates another queue
41  */
42 enum {API_NUMBER_OF_COMMAND_MAX   = 32};
43 
44 enum MES_API_TYPE {
45 	MES_API_TYPE_SCHEDULER = 1,
46 	MES_API_TYPE_MAX
47 };
48 
49 enum MES_SCH_API_OPCODE {
50 	MES_SCH_API_SET_HW_RSRC			= 0,
51 	MES_SCH_API_SET_SCHEDULING_CONFIG	= 1, /* agreegated db, quantums, etc */
52 	MES_SCH_API_ADD_QUEUE			= 2,
53 	MES_SCH_API_REMOVE_QUEUE		= 3,
54 	MES_SCH_API_PERFORM_YIELD		= 4,
55 	MES_SCH_API_SET_GANG_PRIORITY_LEVEL	= 5, /* For windows GANG = Context */
56 	MES_SCH_API_SUSPEND			= 6,
57 	MES_SCH_API_RESUME			= 7,
58 	MES_SCH_API_RESET			= 8,
59 	MES_SCH_API_SET_LOG_BUFFER		= 9,
60 	MES_SCH_API_CHANGE_GANG_PRORITY		= 10,
61 	MES_SCH_API_QUERY_SCHEDULER_STATUS	= 11,
62 	MES_SCH_API_SET_DEBUG_VMID		= 13,
63 	MES_SCH_API_MISC			= 14,
64 	MES_SCH_API_UPDATE_ROOT_PAGE_TABLE	= 15,
65 	MES_SCH_API_AMD_LOG			= 16,
66 	MES_SCH_API_SET_SE_MODE			= 17,
67 	MES_SCH_API_SET_GANG_SUBMIT		= 18,
68 	MES_SCH_API_SET_HW_RSRC_1               = 19,
69 	MES_SCH_API_INV_TLBS                    = 20,
70 
71 	MES_SCH_API_MAX = 0xFF
72 };
73 
74 union MES_API_HEADER {
75 	struct {
76 		uint32_t type	  : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
77 		uint32_t opcode   : 8;
78 		uint32_t dwsize   : 8; /* including header */
79 		uint32_t reserved : 12;
80 	};
81 
82 	uint32_t u32All;
83 };
84 
85 enum MES_AMD_PRIORITY_LEVEL {
86 	AMD_PRIORITY_LEVEL_LOW		= 0,
87 	AMD_PRIORITY_LEVEL_NORMAL	= 1,
88 	AMD_PRIORITY_LEVEL_MEDIUM	= 2,
89 	AMD_PRIORITY_LEVEL_HIGH		= 3,
90 	AMD_PRIORITY_LEVEL_REALTIME	= 4,
91 
92 	AMD_PRIORITY_NUM_LEVELS
93 };
94 
95 enum MES_QUEUE_TYPE {
96 	MES_QUEUE_TYPE_GFX,
97 	MES_QUEUE_TYPE_COMPUTE,
98 	MES_QUEUE_TYPE_SDMA,
99 
100 	MES_QUEUE_TYPE_MAX,
101 	MES_QUEUE_TYPE_SCHQ = MES_QUEUE_TYPE_MAX,
102 };
103 
104 struct MES_API_STATUS {
105 	uint64_t api_completion_fence_addr;
106 	uint64_t api_completion_fence_value;
107 };
108 
109 /*
110  * MES will set api_completion_fence_value in api_completion_fence_addr
111  * when it can successflly process the API. MES will also trigger
112  * following interrupt when it finish process the API no matter success
113  * or failed.
114  *     Interrupt source id 181 (EOP) with context ID (DW 6 in the int
115  *     cookie) set to 0xb1 and context type set to 8. Driver side need
116  *     to enable TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to
117  *     catch this interrupt.
118  *     Driver side also need to set enable_mes_fence_int = 1 in
119  *     set_HW_resource package to enable this fence interrupt.
120  * when the API process failed.
121  *     lowre 32 bits set to 0.
122  *     higher 32 bits set as follows (bit shift within high 32)
123  *         bit 0  -  7    API specific error code.
124  *         bit 8  - 15    API OPCODE.
125  *         bit 16 - 23    MISC OPCODE if any
126  *         bit 24 - 30    ERROR category (API_ERROR_XXX)
127  *         bit 31         Set to 1 to indicate error status
128  *
129  */
130 enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 };
131 enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 };
132 enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 };
133 enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 };
134 
135 enum MES_ERROR_CATEGORY_CODE_12 {
136 	MES_ERROR_API                = 1,
137 	MES_ERROR_SCHEDULING         = 2,
138 	MES_ERROR_UNKNOWN            = 3,
139 };
140 
141 #define MES_ERR_CODE(api_err, opcode, misc_op, category) \
142 			((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \
143 			misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \
144 			category << MES_ERROR_CATEGORY_SHIFT_12 | \
145 			1 << MES_API_STATUS_ERROR_SHIFT_12) << 32)
146 
147 enum { MAX_COMPUTE_PIPES = 8 };
148 enum { MAX_GFX_PIPES	 = 2 };
149 enum { MAX_SDMA_PIPES	 = 2 };
150 
151 enum { MAX_COMPUTE_HQD_PER_PIPE		= 8 };
152 enum { MAX_GFX_HQD_PER_PIPE		= 8 };
153 enum { MAX_SDMA_HQD_PER_PIPE		= 10 };
154 enum { MAX_SDMA_HQD_PER_PIPE_11_0	= 8 };
155 
156 
157 enum { MAX_QUEUES_IN_A_GANG = 8 };
158 
159 enum VM_HUB_TYPE {
160 	VM_HUB_TYPE_GC = 0,
161 	VM_HUB_TYPE_MM = 1,
162 
163 	VM_HUB_TYPE_MAX,
164 };
165 
166 enum { VMID_INVALID = 0xffff };
167 
168 enum { MAX_VMID_GCHUB = 16 };
169 enum { MAX_VMID_MMHUB = 16 };
170 
171 enum SET_DEBUG_VMID_OPERATIONS {
172 	DEBUG_VMID_OP_PROGRAM	= 0,
173 	DEBUG_VMID_OP_ALLOCATE	= 1,
174 	DEBUG_VMID_OP_RELEASE	= 2,
175 	DEBUG_VMID_OP_VM_SETUP	= 3 // used to set up the debug vmid page table in the kernel queue case (mode 1)
176 };
177 
178 enum MES_MS_LOG_CONTEXT_STATE {
179 	MES_LOG_CONTEXT_STATE_IDLE		= 0,
180 	MES_LOG_CONTEXT_STATE_RUNNING		= 1,
181 	MES_LOG_CONTEXT_STATE_READY		= 2,
182 	MES_LOG_CONTEXT_STATE_READY_STANDBY	= 3,
183 	MES_LOG_CONTEXT_STATE_INVALID		= 0xF,
184 };
185 
186 enum MES_MS_LOG_OPERATION {
187 	MES_LOG_OPERATION_CONTEXT_STATE_CHANGE		= 0,
188 	MES_LOG_OPERATION_QUEUE_NEW_WORK		= 1,
189 	MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT	= 2,
190 	MES_LOG_OPERATION_QUEUE_NO_MORE_WORK		= 3,
191 	MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT	= 4,
192 	MES_LOG_OPERATION_QUEUE_INVALID			= 0xF,
193 };
194 
195 struct MES_LOG_CONTEXT_STATE_CHANGE {
196 	uint64_t			h_context;
197 	enum MES_MS_LOG_CONTEXT_STATE	new_context_state;
198 };
199 
200 struct MES_LOG_QUEUE_NEW_WORK {
201 	uint64_t	h_queue;
202 	uint64_t	reserved;
203 };
204 
205 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
206 	uint64_t	h_queue;
207 	uint64_t	h_sync_object;
208 };
209 
210 struct MES_LOG_QUEUE_NO_MORE_WORK {
211 	uint64_t	h_queue;
212 	uint64_t	reserved;
213 };
214 
215 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
216 	uint64_t	h_queue;
217 	uint64_t	h_sync_object;
218 };
219 
220 struct MES_LOG_ENTRY_HEADER {
221 	uint32_t first_free_entry_index;
222 	uint32_t wraparound_count;
223 	uint64_t number_of_entries;
224 	uint64_t reserved[2];
225 };
226 
227 struct MES_LOG_ENTRY_DATA {
228 	uint64_t gpu_time_stamp;
229 	uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
230 	uint32_t reserved_operation_type_bits;
231 	union {
232 		struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
233 		struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
234 		struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
235 		struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
236 		struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
237 		uint64_t all[2];
238 	};
239 };
240 
241 struct MES_LOG_BUFFER {
242 	struct MES_LOG_ENTRY_HEADER header;
243 	struct MES_LOG_ENTRY_DATA	entries[];
244 };
245 
246 enum MES_SWIP_TO_HWIP_DEF {
247 	MES_MAX_HWIP_SEGMENT = 8,
248 };
249 
250 union MESAPI_SET_HW_RESOURCES {
251 	struct {
252 		union MES_API_HEADER	header;
253 		uint32_t		vmid_mask_mmhub;
254 		uint32_t		vmid_mask_gfxhub;
255 		uint32_t		gds_size;
256 		uint32_t		paging_vmid;
257 		uint32_t		compute_hqd_mask[MAX_COMPUTE_PIPES];
258 		uint32_t		gfx_hqd_mask[MAX_GFX_PIPES];
259 		uint32_t		sdma_hqd_mask[MAX_SDMA_PIPES];
260 		uint32_t		aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
261 		uint64_t		g_sch_ctx_gpu_mc_ptr;
262 		uint64_t		query_status_fence_gpu_mc_ptr;
263 		uint32_t		gc_base[MES_MAX_HWIP_SEGMENT];
264 		uint32_t		mmhub_base[MES_MAX_HWIP_SEGMENT];
265 		uint32_t		osssys_base[MES_MAX_HWIP_SEGMENT];
266 		struct MES_API_STATUS	api_status;
267 		union {
268 			struct {
269 				uint32_t disable_reset : 1;
270 				uint32_t use_different_vmid_compute : 1;
271 				uint32_t disable_mes_log   : 1;
272 				uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
273 				uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
274 				uint32_t second_gfx_pipe_enabled : 1;
275 				uint32_t enable_level_process_quantum_check : 1;
276 				uint32_t legacy_sch_mode : 1;
277 				uint32_t disable_add_queue_wptr_mc_addr : 1;
278 				uint32_t enable_mes_event_int_logging : 1;
279 				uint32_t enable_reg_active_poll : 1;
280 				uint32_t use_disable_queue_in_legacy_uq_preemption : 1;
281 				uint32_t send_write_data : 1;
282 				uint32_t os_tdr_timeout_override : 1;
283 				uint32_t use_rs64mem_for_proc_gang_ctx : 1;
284 				uint32_t halt_on_misaligned_access : 1;
285 				uint32_t use_add_queue_unmap_flag_addr : 1;
286 				uint32_t enable_mes_sch_stb_log : 1;
287 				uint32_t limit_single_process : 1;
288 				uint32_t unmapped_doorbell_handling: 2;
289 				uint32_t enable_mes_fence_int: 1;
290 				uint32_t reserved : 10;
291 			};
292 			uint32_t uint32_all;
293 		};
294 	uint32_t	oversubscription_timer;
295 	uint64_t	doorbell_info;
296 	uint64_t	event_intr_history_gpu_mc_ptr;
297 	uint64_t	timestamp;
298 	uint32_t	os_tdr_timeout_in_sec;
299 	};
300 
301 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
302 };
303 
304 union MESAPI_SET_HW_RESOURCES_1 {
305 	struct {
306 		union MES_API_HEADER                header;
307 		struct MES_API_STATUS               api_status;
308 		uint64_t                            timestamp;
309 		union {
310 			struct {
311 				uint32_t enable_mes_debug_ctx : 1;
312 				uint32_t reserved : 31;
313 			};
314 			uint32_t uint32_all;
315 		};
316 		uint64_t                            mes_debug_ctx_mc_addr;
317 		uint32_t                            mes_debug_ctx_size;
318 		/* unit is 100ms */
319 		uint32_t                            mes_kiq_unmap_timeout;
320 		uint64_t                            reserved1;
321 		uint64_t                            cleaner_shader_fence_mc_addr;
322 	};
323 
324 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
325 };
326 
327 union MESAPI__ADD_QUEUE {
328 	struct {
329 		union MES_API_HEADER	header;
330 		uint32_t		process_id;
331 		uint64_t		page_table_base_addr;
332 		uint64_t		process_va_start;
333 		uint64_t		process_va_end;
334 		uint64_t		process_quantum;
335 		uint64_t		process_context_addr;
336 		uint64_t		gang_quantum;
337 		uint64_t		gang_context_addr;
338 		uint32_t		inprocess_gang_priority;
339 		enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
340 		uint32_t		doorbell_offset;
341 		uint64_t		mqd_addr;
342 		/* From MES_API_VERSION 2, mc addr is expected for wptr_addr */
343 		uint64_t		wptr_addr;
344 		uint64_t		h_context;
345 		uint64_t		h_queue;
346 		enum MES_QUEUE_TYPE	queue_type;
347 		uint32_t		gds_base;
348 		union {
349 			/* backwards compatibility with Linux, remove union once they use kfd_queue_size */
350 			uint32_t	gds_size;
351 			uint32_t	kfd_queue_size;
352 		};
353 		uint32_t		gws_base;
354 		uint32_t		gws_size;
355 		uint32_t		oa_mask;
356 		uint64_t		trap_handler_addr;
357 		uint32_t		vm_context_cntl;
358 
359 		struct {
360 			uint32_t paging	 : 1;
361 			uint32_t debug_vmid  : 4;
362 			uint32_t program_gds : 1;
363 			uint32_t is_gang_suspended : 1;
364 			uint32_t is_tmz_queue : 1;
365 			uint32_t map_kiq_utility_queue : 1;
366 			uint32_t is_kfd_process : 1;
367 			uint32_t trap_en : 1;
368 			uint32_t is_aql_queue : 1;
369 			uint32_t skip_process_ctx_clear : 1;
370 			uint32_t map_legacy_kq : 1;
371 			uint32_t exclusively_scheduled : 1;
372 			uint32_t is_long_running : 1;
373 			uint32_t is_dwm_queue : 1;
374 			uint32_t reserved	 : 15;
375 		};
376 		struct MES_API_STATUS	api_status;
377 		uint64_t		tma_addr;
378 		uint32_t		sch_id;
379 		uint64_t		timestamp;
380 		uint32_t		process_context_array_index;
381 		uint32_t		gang_context_array_index;
382 		uint32_t		pipe_id;	//used for mapping legacy kernel queue
383 		uint32_t		queue_id;
384 		uint32_t		alignment_mode_setting;
385 	};
386 
387 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
388 };
389 
390 union MESAPI__REMOVE_QUEUE {
391 	struct {
392 		union MES_API_HEADER	header;
393 		uint32_t		doorbell_offset;
394 		uint64_t		gang_context_addr;
395 
396 		struct {
397 			uint32_t reserved01		  : 1;
398 			uint32_t unmap_kiq_utility_queue  : 1;
399 			uint32_t preempt_legacy_gfx_queue : 1;
400 			uint32_t unmap_legacy_queue	  : 1;
401 			uint32_t reserved		  : 28;
402 		};
403 		struct MES_API_STATUS		api_status;
404 
405 		uint32_t			pipe_id;
406 		uint32_t			queue_id;
407 
408 		uint64_t			tf_addr;
409 		uint32_t			tf_data;
410 
411 		enum MES_QUEUE_TYPE		queue_type;
412 		uint64_t			timestamp;
413 		uint32_t			gang_context_array_index;
414 	};
415 
416 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
417 };
418 
419 union MESAPI__SET_SCHEDULING_CONFIG {
420 	struct {
421 		union MES_API_HEADER	header;
422 		/* Grace period when preempting another priority band for this priority band.
423 		 * The value for idle priority band is ignored, as it never preempts other bands.
424 		 */
425 		uint64_t		grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
426 
427 		/* Default quantum for scheduling across processes within a priority band. */
428 		uint64_t		process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
429 
430 		/* Default grace period for processes that preempt each other within a priority band.*/
431 		uint64_t		process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
432 
433 		/* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.
434 		 * Valid values are between 0 and 50, with the default being 10.
435 		 */
436 		uint32_t		normal_yield_percent;
437 
438 		struct MES_API_STATUS	api_status;
439 		uint64_t		timestamp;
440 	};
441 
442 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
443 };
444 
445 union MESAPI__PERFORM_YIELD {
446 	struct {
447 		union MES_API_HEADER	header;
448 		uint32_t		dummy;
449 		struct MES_API_STATUS	api_status;
450 		uint64_t		timestamp;
451 	};
452 
453 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
454 };
455 
456 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
457 	struct {
458 		union MES_API_HEADER		header;
459 		uint32_t			inprocess_gang_priority;
460 		enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
461 		uint64_t			gang_quantum;
462 		uint64_t			gang_context_addr;
463 		struct MES_API_STATUS		api_status;
464 		uint32_t			doorbell_offset;
465 		uint64_t			timestamp;
466 		uint32_t			gang_context_array_index;
467 		struct {
468 			uint32_t		queue_quantum_scale	: 2;
469 			uint32_t		queue_quantum_duration	: 8;
470 			uint32_t		apply_quantum_all_processes : 1;
471 			uint32_t		reserved		: 21;
472 		};
473 	};
474 
475 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
476 };
477 
478 union MESAPI__SUSPEND {
479 	struct {
480 		union MES_API_HEADER	header;
481 		/* false - suspend all gangs; true - specific gang */
482 		struct {
483 			uint32_t	suspend_all_gangs : 1;
484 			uint32_t	reserved : 31;
485 		};
486 		/* gang_context_addr is valid only if suspend_all = false */
487 
488 		uint64_t		gang_context_addr;
489 
490 		uint64_t		suspend_fence_addr;
491 		uint32_t		suspend_fence_value;
492 
493 		struct MES_API_STATUS	api_status;
494 
495 		union {
496 			uint32_t return_value; // to be removed
497 			uint32_t sch_id;       //keep the old return_value temporarily for compatibility
498 		};
499 		uint32_t		doorbell_offset;
500 		uint64_t		timestamp;
501 		enum MES_QUEUE_TYPE	legacy_uq_type;
502 		enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level;
503 		uint32_t		gang_context_array_index;
504 	};
505 
506 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
507 };
508 
509 union MESAPI__RESUME {
510 	struct {
511 		union MES_API_HEADER	header;
512 		/* false - resume all gangs; true - specified gang */
513 		struct {
514 			uint32_t	resume_all_gangs : 1;
515 			uint32_t	reserved : 31;
516 		};
517 		/* valid only if resume_all_gangs = false */
518 		uint64_t		gang_context_addr;
519 
520 		struct MES_API_STATUS	api_status;
521 		uint32_t		doorbell_offset;
522 		uint64_t		timestamp;
523 		uint32_t		gang_context_array_index;
524 	};
525 
526 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
527 };
528 
529 union MESAPI__RESET {
530 	struct {
531 		union MES_API_HEADER		header;
532 
533 		struct {
534 			/* Only reset the queue given by doorbell_offset (not entire gang) */
535 			uint32_t		reset_queue_only : 1;
536 			/* Hang detection first then reset any queues that are hung */
537 			uint32_t		hang_detect_then_reset : 1;
538 			/* Only do hang detection (no reset) */
539 			uint32_t		hang_detect_only : 1;
540 			/* Reset HP and LP kernel queues not managed by MES */
541 			uint32_t		reset_legacy_gfx : 1;
542 			/* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */
543 			uint32_t		use_connected_queue_index : 1;
544 			/* For gfx pipe 1 */
545 			uint32_t		use_connected_queue_index_p1 : 1;
546 			uint32_t		reserved : 26;
547 		};
548 
549 		uint64_t			gang_context_addr;
550 
551 		/* valid only if reset_queue_only = true */
552 		uint32_t			doorbell_offset;
553 
554 		/* valid only if hang_detect_then_reset = true */
555 		uint64_t			doorbell_offset_addr;
556 		enum MES_QUEUE_TYPE		queue_type;
557 
558 		/* valid only if reset_legacy_gfx = true */
559 		uint32_t			pipe_id_lp;
560 		uint32_t			queue_id_lp;
561 		uint32_t			vmid_id_lp;
562 		uint64_t			mqd_mc_addr_lp;
563 		uint32_t			doorbell_offset_lp;
564 		uint64_t			wptr_addr_lp;
565 
566 		uint32_t			pipe_id_hp;
567 		uint32_t			queue_id_hp;
568 		uint32_t			vmid_id_hp;
569 		uint64_t			mqd_mc_addr_hp;
570 		uint32_t			doorbell_offset_hp;
571 		uint64_t			wptr_addr_hp;
572 
573 		struct MES_API_STATUS		api_status;
574 		uint32_t			active_vmids;
575 		uint64_t			timestamp;
576 
577 		uint32_t			gang_context_array_index;
578 
579 		uint32_t			connected_queue_index;
580 		uint32_t			connected_queue_index_p1;
581 	};
582 
583 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
584 };
585 
586 union MESAPI__SET_LOGGING_BUFFER {
587 	struct {
588 		union MES_API_HEADER		header;
589 		/* There are separate log buffers for each queue type */
590 		enum MES_QUEUE_TYPE		log_type;
591 		/* Log buffer GPU Address */
592 		uint64_t			logging_buffer_addr;
593 		/* number of entries in the log buffer */
594 		uint32_t			number_of_entries;
595 		/* Entry index at which CPU interrupt needs to be signalled */
596 		uint32_t			interrupt_entry;
597 
598 		struct MES_API_STATUS		api_status;
599 		uint64_t			timestamp;
600 		uint32_t			vmid;
601 	};
602 
603 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
604 };
605 
606 enum MES_API_QUERY_MES_OPCODE {
607 	MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE,
608 	MES_API_QUERY_MES__CHECK_HEALTHY,
609 	MES_API_QUERY_MES__MAX,
610 };
611 
612 enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 };
613 
614 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE {
615 	uint64_t	proc_ctx_array_size_addr;
616 	uint64_t	gang_ctx_array_size_addr;
617 };
618 
619 struct MES_API_QUERY_MES__HEALTHY_CHECK {
620 	uint64_t	healthy_addr;
621 };
622 
623 union MESAPI__QUERY_MES_STATUS {
624 	struct {
625 		union MES_API_HEADER		header;
626 		enum MES_API_QUERY_MES_OPCODE	subopcode;
627 		struct MES_API_STATUS		api_status;
628 		uint64_t			timestamp;
629 		union {
630 			struct MES_API_QUERY_MES__CTX_ARRAY_SIZE	ctx_array_size;
631 			struct MES_API_QUERY_MES__HEALTHY_CHECK	healthy_check;
632 			uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS];
633 		};
634 	};
635 
636 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
637 };
638 
639 union MESAPI__SET_DEBUG_VMID {
640 	struct {
641 		union MES_API_HEADER	header;
642 		struct MES_API_STATUS	api_status;
643 		union {
644 			struct {
645 			uint32_t use_gds   : 1;
646 			uint32_t operation : 2;
647 			uint32_t reserved  : 29;
648 			} flags;
649 			uint32_t u32All;
650 		};
651 		uint32_t		reserved;
652 		uint32_t		debug_vmid;
653 		uint64_t		process_context_addr;
654 		uint64_t		page_table_base_addr;
655 		uint64_t		process_va_start;
656 		uint64_t		process_va_end;
657 		uint32_t		gds_base;
658 		uint32_t		gds_size;
659 		uint32_t		gws_base;
660 		uint32_t		gws_size;
661 		uint32_t		oa_mask;
662 
663 		uint64_t		output_addr; // output addr of the acquired vmid value
664 
665 		uint64_t		timestamp;
666 
667 		uint32_t		process_vm_cntl;
668 		enum MES_QUEUE_TYPE	queue_type;
669 
670 		uint32_t		process_context_array_index;
671 
672 		uint32_t		alignment_mode_setting;
673 	};
674 
675 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
676 };
677 
678 enum MESAPI_MISC_OPCODE {
679 	MESAPI_MISC__WRITE_REG,
680 	MESAPI_MISC__INV_GART,
681 	MESAPI_MISC__QUERY_STATUS,
682 	MESAPI_MISC__READ_REG,
683 	MESAPI_MISC__WAIT_REG_MEM,
684 	MESAPI_MISC__SET_SHADER_DEBUGGER,
685 	MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
686 	MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
687 	MESAPI_MISC__QUERY_HUNG_ENGINE_ID,
688 	MESAPI_MISC__CHANGE_CONFIG,
689 	MESAPI_MISC__LAUNCH_CLEANER_SHADER,
690 	MESAPI_MISC__SETUP_MES_DBGEXT,
691 
692 	MESAPI_MISC__MAX,
693 };
694 
695 enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20};
696 
697 struct WRITE_REG {
698 	uint32_t	reg_offset;
699 	uint32_t	reg_value;
700 };
701 
702 struct READ_REG {
703 	uint32_t reg_offset;
704 	uint64_t buffer_addr;
705 	union {
706 		struct {
707 			uint32_t read64Bits : 1;
708 			uint32_t reserved : 31;
709 		} bits;
710 		uint32_t all;
711 	} option;
712 };
713 
714 struct INV_GART {
715 	uint64_t	inv_range_va_start;
716 	uint64_t	inv_range_size;
717 };
718 
719 struct QUERY_STATUS {
720 	uint32_t context_id;
721 };
722 
723 enum WRM_OPERATION {
724 	WRM_OPERATION__WAIT_REG_MEM,
725 	WRM_OPERATION__WR_WAIT_WR_REG,
726 
727 	WRM_OPERATION__MAX,
728 };
729 
730 struct WAIT_REG_MEM {
731 	enum WRM_OPERATION op;
732 	/* only function = equal_to_the_reference_value and mem_space = register_space supported for now */
733 	uint32_t reference;
734 	uint32_t mask;
735 	uint32_t reg_offset1;
736 	uint32_t reg_offset2;
737 };
738 
739 struct SET_SHADER_DEBUGGER {
740 	uint64_t process_context_addr;
741 	union {
742 		struct {
743 			uint32_t single_memop : 1; // SQ_DEBUG.single_memop
744 			uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op
745 			uint32_t reserved : 30;
746 		};
747 		uint32_t u32all;
748 	} flags;
749 	uint32_t spi_gdbg_per_vmid_cntl;
750 	uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL
751 	uint32_t trap_en;
752 };
753 
754 struct SET_GANG_SUBMIT {
755 	uint64_t gang_context_addr;
756 	uint64_t slave_gang_context_addr;
757 	uint32_t gang_context_array_index;
758 	uint32_t slave_gang_context_array_index;
759 };
760 
761 enum MESAPI_MISC__CHANGE_CONFIG_OPTION {
762 	MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
763 	MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
764 	MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG    = 2,
765 
766 	MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
767 };
768 
769 struct CHANGE_CONFIG {
770 	enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
771 	union {
772 		struct  {
773 			uint32_t limit_single_process : 1;
774 			uint32_t enable_hws_logging_buffer : 1;
775 			uint32_t reserved : 30;
776 		} bits;
777 		uint32_t all;
778 	} option;
779 
780 	struct {
781 		uint32_t tdr_level;
782 		uint32_t tdr_delay;
783 	} tdr_config;
784 };
785 
786 union MESAPI__MISC {
787 	struct {
788 		union MES_API_HEADER	header;
789 		enum MESAPI_MISC_OPCODE opcode;
790 		struct MES_API_STATUS	api_status;
791 		union {
792 			struct WRITE_REG write_reg;
793 			struct INV_GART inv_gart;
794 			struct QUERY_STATUS query_status;
795 			struct READ_REG read_reg;
796 			struct WAIT_REG_MEM wait_reg_mem;
797 			struct SET_SHADER_DEBUGGER set_shader_debugger;
798 			enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
799 			struct CHANGE_CONFIG change_config;
800 			uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
801 		};
802 		uint64_t		timestamp;
803 		uint32_t		doorbell_offset;
804 		uint32_t		os_fence;
805 	};
806 
807 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
808 };
809 
810 union MESAPI__UPDATE_ROOT_PAGE_TABLE {
811 	struct {
812 		union MES_API_HEADER		header;
813 		uint64_t			page_table_base_addr;
814 		uint64_t			process_context_addr;
815 		struct MES_API_STATUS		api_status;
816 		uint64_t			timestamp;
817 		uint32_t			process_context_array_index;
818 	};
819 
820 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
821 };
822 
823 union MESAPI_AMD_LOG {
824 	struct {
825 		union MES_API_HEADER		header;
826 		uint64_t			p_buffer_memory;
827 		uint64_t			p_buffer_size_used;
828 		struct MES_API_STATUS		api_status;
829 		uint64_t			timestamp;
830 	};
831 
832 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
833 };
834 
835 enum MES_SE_MODE {
836 	MES_SE_MODE_INVALID	= 0,
837 	MES_SE_MODE_SINGLE_SE	= 1,
838 	MES_SE_MODE_DUAL_SE	= 2,
839 	MES_SE_MODE_LOWER_POWER	= 3,
840 };
841 
842 union MESAPI__SET_SE_MODE {
843 	struct {
844 		union MES_API_HEADER header;
845 		/* the new SE mode to apply*/
846 		enum MES_SE_MODE new_se_mode;
847 		/* the fence to make sure the ItCpgCtxtSync packet is completed */
848 		uint64_t cpg_ctxt_sync_fence_addr;
849 		uint32_t cpg_ctxt_sync_fence_value;
850 		/* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */
851 		union {
852 			struct {
853 				uint32_t log_seq_time : 1;
854 				uint32_t reserved : 31;
855 			};
856 			uint32_t uint32_all;
857 		};
858 		struct MES_API_STATUS api_status;
859 	};
860 
861 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
862 };
863 
864 union MESAPI__SET_GANG_SUBMIT {
865 	struct {
866 		union MES_API_HEADER	header;
867 		struct MES_API_STATUS	api_status;
868 		struct SET_GANG_SUBMIT	set_gang_submit;
869 	};
870 
871 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
872 };
873 
874 /*
875  * @inv_sel        0-select pasid as input to do the invalidation , 1-select vmid
876  * @flush_type     0-old style, 1-light weight, 2-heavyweight, 3-heavyweight2
877  * @inv_sel_id     specific pasid when inv_sel is 0 and specific vmid if inv_sel is 1
878  * @hub_id         0-gc_hub, 1-mm_hub
879  */
880 struct INV_TLBS {
881 	uint8_t     inv_sel;
882 	uint8_t     flush_type;
883 	uint16_t    inv_sel_id;
884 	uint32_t    hub_id;
885 	/* If following two inv_range setting are all 0 , whole VM will be invalidated,
886 	 * otherwise only required range be invalidated
887 	 */
888 	uint64_t    inv_range_va_start;
889 	uint64_t    inv_range_size;
890 	uint64_t    reserved;
891 };
892 
893 union MESAPI__INV_TLBS {
894 	struct {
895 		union MES_API_HEADER    header;
896 		struct MES_API_STATUS   api_status;
897 		struct INV_TLBS         invalidate_tlbs;
898 	};
899 
900 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
901 };
902 
903 #pragma pack(pop)
904 
905 #endif
906