1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 4) 28 29 #define MES_API_VERSION 1 30 31 /* Driver submits one API(cmd) as a single Frame and this command size is same 32 * for all API to ease the debugging and parsing of ring buffer. 33 */ 34 enum { API_FRAME_SIZE_IN_DWORDS = 64 }; 35 36 /* To avoid command in scheduler context to be overwritten whenenver mutilple 37 * interrupts come in, this creates another queue. 38 */ 39 enum { API_NUMBER_OF_COMMAND_MAX = 32 }; 40 41 enum MES_API_TYPE { 42 MES_API_TYPE_SCHEDULER = 1, 43 MES_API_TYPE_MAX 44 }; 45 46 enum MES_SCH_API_OPCODE { 47 MES_SCH_API_SET_HW_RSRC = 0, 48 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 49 MES_SCH_API_ADD_QUEUE = 2, 50 MES_SCH_API_REMOVE_QUEUE = 3, 51 MES_SCH_API_PERFORM_YIELD = 4, 52 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, 53 MES_SCH_API_SUSPEND = 6, 54 MES_SCH_API_RESUME = 7, 55 MES_SCH_API_RESET = 8, 56 MES_SCH_API_SET_LOG_BUFFER = 9, 57 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 58 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 59 MES_SCH_API_PROGRAM_GDS = 12, 60 MES_SCH_API_SET_DEBUG_VMID = 13, 61 MES_SCH_API_MISC = 14, 62 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 63 MES_SCH_API_AMD_LOG = 16, 64 MES_SCH_API_SET_HW_RSRC_1 = 19, 65 MES_SCH_API_MAX = 0xFF 66 }; 67 68 union MES_API_HEADER { 69 struct { 70 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 71 uint32_t opcode : 8; 72 uint32_t dwsize : 8; /* including header */ 73 uint32_t reserved : 12; 74 }; 75 76 uint32_t u32All; 77 }; 78 79 enum MES_AMD_PRIORITY_LEVEL { 80 AMD_PRIORITY_LEVEL_LOW = 0, 81 AMD_PRIORITY_LEVEL_NORMAL = 1, 82 AMD_PRIORITY_LEVEL_MEDIUM = 2, 83 AMD_PRIORITY_LEVEL_HIGH = 3, 84 AMD_PRIORITY_LEVEL_REALTIME = 4, 85 AMD_PRIORITY_NUM_LEVELS 86 }; 87 88 enum MES_QUEUE_TYPE { 89 MES_QUEUE_TYPE_GFX, 90 MES_QUEUE_TYPE_COMPUTE, 91 MES_QUEUE_TYPE_SDMA, 92 MES_QUEUE_TYPE_MAX, 93 }; 94 95 struct MES_API_STATUS { 96 uint64_t api_completion_fence_addr; 97 uint64_t api_completion_fence_value; 98 }; 99 100 enum { MAX_COMPUTE_PIPES = 8 }; 101 enum { MAX_GFX_PIPES = 2 }; 102 enum { MAX_SDMA_PIPES = 2 }; 103 104 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 105 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 106 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 107 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 108 109 enum { MAX_QUEUES_IN_A_GANG = 8 }; 110 111 enum VM_HUB_TYPE { 112 VM_HUB_TYPE_GC = 0, 113 VM_HUB_TYPE_MM = 1, 114 VM_HUB_TYPE_MAX, 115 }; 116 117 enum { VMID_INVALID = 0xffff }; 118 119 enum { MAX_VMID_GCHUB = 16 }; 120 enum { MAX_VMID_MMHUB = 16 }; 121 122 enum SET_DEBUG_VMID_OPERATIONS { 123 DEBUG_VMID_OP_PROGRAM = 0, 124 DEBUG_VMID_OP_ALLOCATE = 1, 125 DEBUG_VMID_OP_RELEASE = 2 126 }; 127 128 enum MES_LOG_OPERATION { 129 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 130 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 131 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 132 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 133 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 134 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 135 }; 136 137 enum MES_LOG_CONTEXT_STATE { 138 MES_LOG_CONTEXT_STATE_IDLE = 0, 139 MES_LOG_CONTEXT_STATE_RUNNING = 1, 140 MES_LOG_CONTEXT_STATE_READY = 2, 141 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 142 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 143 }; 144 145 struct MES_LOG_CONTEXT_STATE_CHANGE { 146 void *h_context; 147 enum MES_LOG_CONTEXT_STATE new_context_state; 148 }; 149 150 struct MES_LOG_QUEUE_NEW_WORK { 151 uint64_t h_queue; 152 uint64_t reserved; 153 }; 154 155 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 156 uint64_t h_queue; 157 uint64_t h_sync_object; 158 }; 159 160 struct MES_LOG_QUEUE_NO_MORE_WORK { 161 uint64_t h_queue; 162 uint64_t reserved; 163 }; 164 165 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 166 uint64_t h_queue; 167 uint64_t h_sync_object; 168 }; 169 170 struct MES_LOG_ENTRY_HEADER { 171 uint32_t first_free_entry_index; 172 uint32_t wraparound_count; 173 uint64_t number_of_entries; 174 uint64_t reserved[2]; 175 }; 176 177 struct MES_LOG_ENTRY_DATA { 178 uint64_t gpu_time_stamp; 179 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 180 uint32_t reserved_operation_type_bits; 181 union { 182 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 183 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 184 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 185 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 186 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 187 uint64_t all[2]; 188 }; 189 }; 190 191 struct MES_LOG_BUFFER { 192 struct MES_LOG_ENTRY_HEADER header; 193 struct MES_LOG_ENTRY_DATA entries[1]; 194 }; 195 196 enum MES_SWIP_TO_HWIP_DEF { 197 MES_MAX_HWIP_SEGMENT = 8, 198 }; 199 200 union MESAPI_SET_HW_RESOURCES { 201 struct { 202 union MES_API_HEADER header; 203 uint32_t vmid_mask_mmhub; 204 uint32_t vmid_mask_gfxhub; 205 uint32_t gds_size; 206 uint32_t paging_vmid; 207 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 208 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 209 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 210 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 211 uint64_t g_sch_ctx_gpu_mc_ptr; 212 uint64_t query_status_fence_gpu_mc_ptr; 213 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 214 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 215 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 216 struct MES_API_STATUS api_status; 217 union { 218 struct { 219 uint32_t disable_reset : 1; 220 uint32_t use_different_vmid_compute : 1; 221 uint32_t disable_mes_log : 1; 222 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 223 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 224 uint32_t second_gfx_pipe_enabled : 1; 225 uint32_t enable_level_process_quantum_check : 1; 226 uint32_t legacy_sch_mode : 1; 227 uint32_t disable_add_queue_wptr_mc_addr : 1; 228 uint32_t enable_mes_event_int_logging : 1; 229 uint32_t enable_reg_active_poll : 1; 230 uint32_t reserved : 21; 231 }; 232 uint32_t uint32_t_all; 233 }; 234 uint32_t oversubscription_timer; 235 uint64_t doorbell_info; 236 uint64_t event_intr_history_gpu_mc_ptr; 237 }; 238 239 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 240 }; 241 242 union MESAPI_SET_HW_RESOURCES_1 { 243 struct { 244 union MES_API_HEADER header; 245 struct MES_API_STATUS api_status; 246 uint64_t timestamp; 247 union { 248 struct { 249 uint32_t enable_mes_info_ctx : 1; 250 uint32_t reserved : 31; 251 }; 252 uint32_t uint32_all; 253 }; 254 uint64_t mes_info_ctx_mc_addr; 255 uint32_t mes_info_ctx_size; 256 uint32_t mes_kiq_unmap_timeout; // unit is 100ms 257 }; 258 259 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 260 }; 261 262 union MESAPI__ADD_QUEUE { 263 struct { 264 union MES_API_HEADER header; 265 uint32_t process_id; 266 uint64_t page_table_base_addr; 267 uint64_t process_va_start; 268 uint64_t process_va_end; 269 uint64_t process_quantum; 270 uint64_t process_context_addr; 271 uint64_t gang_quantum; 272 uint64_t gang_context_addr; 273 uint32_t inprocess_gang_priority; 274 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 275 uint32_t doorbell_offset; 276 uint64_t mqd_addr; 277 uint64_t wptr_addr; 278 uint64_t h_context; 279 uint64_t h_queue; 280 enum MES_QUEUE_TYPE queue_type; 281 uint32_t gds_base; 282 uint32_t gds_size; 283 uint32_t gws_base; 284 uint32_t gws_size; 285 uint32_t oa_mask; 286 uint64_t trap_handler_addr; 287 uint32_t vm_context_cntl; 288 289 struct { 290 uint32_t paging : 1; 291 uint32_t debug_vmid : 4; 292 uint32_t program_gds : 1; 293 uint32_t is_gang_suspended : 1; 294 uint32_t is_tmz_queue : 1; 295 uint32_t map_kiq_utility_queue : 1; 296 uint32_t is_kfd_process : 1; 297 uint32_t trap_en : 1; 298 uint32_t is_aql_queue : 1; 299 uint32_t skip_process_ctx_clear : 1; 300 uint32_t map_legacy_kq : 1; 301 uint32_t exclusively_scheduled : 1; 302 uint32_t reserved : 17; 303 }; 304 struct MES_API_STATUS api_status; 305 uint64_t tma_addr; 306 }; 307 308 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 309 }; 310 311 union MESAPI__REMOVE_QUEUE { 312 struct { 313 union MES_API_HEADER header; 314 uint32_t doorbell_offset; 315 uint64_t gang_context_addr; 316 317 struct { 318 uint32_t unmap_legacy_gfx_queue : 1; 319 uint32_t unmap_kiq_utility_queue : 1; 320 uint32_t preempt_legacy_gfx_queue : 1; 321 uint32_t unmap_legacy_queue : 1; 322 uint32_t reserved : 28; 323 }; 324 struct MES_API_STATUS api_status; 325 326 uint32_t pipe_id; 327 uint32_t queue_id; 328 329 uint64_t tf_addr; 330 uint32_t tf_data; 331 332 enum MES_QUEUE_TYPE queue_type; 333 }; 334 335 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 336 }; 337 338 union MESAPI__SET_SCHEDULING_CONFIG { 339 struct { 340 union MES_API_HEADER header; 341 /* Grace period when preempting another priority band for this 342 * priority band. The value for idle priority band is ignored, 343 * as it never preempts other bands. 344 */ 345 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 346 /* Default quantum for scheduling across processes within 347 * a priority band. 348 */ 349 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 350 /* Default grace period for processes that preempt each other 351 * within a priority band. 352 */ 353 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 354 /* For normal level this field specifies the target GPU 355 * percentage in situations when it's starved by the high level. 356 * Valid values are between 0 and 50, with the default being 10. 357 */ 358 uint32_t normal_yield_percent; 359 struct MES_API_STATUS api_status; 360 }; 361 362 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 363 }; 364 365 union MESAPI__PERFORM_YIELD { 366 struct { 367 union MES_API_HEADER header; 368 uint32_t dummy; 369 struct MES_API_STATUS api_status; 370 }; 371 372 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 373 }; 374 375 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 376 struct { 377 union MES_API_HEADER header; 378 uint32_t inprocess_gang_priority; 379 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 380 uint64_t gang_quantum; 381 uint64_t gang_context_addr; 382 struct MES_API_STATUS api_status; 383 }; 384 385 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 386 }; 387 388 union MESAPI__SUSPEND { 389 struct { 390 union MES_API_HEADER header; 391 /* false - suspend all gangs; true - specific gang */ 392 struct { 393 uint32_t suspend_all_gangs : 1; 394 uint32_t reserved : 31; 395 }; 396 /* gang_context_addr is valid only if suspend_all = false */ 397 uint64_t gang_context_addr; 398 399 uint64_t suspend_fence_addr; 400 uint32_t suspend_fence_value; 401 402 struct MES_API_STATUS api_status; 403 }; 404 405 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 406 }; 407 408 union MESAPI__RESUME { 409 struct { 410 union MES_API_HEADER header; 411 /* false - resume all gangs; true - specified gang */ 412 struct { 413 uint32_t resume_all_gangs : 1; 414 uint32_t reserved : 31; 415 }; 416 /* valid only if resume_all_gangs = false */ 417 uint64_t gang_context_addr; 418 419 struct MES_API_STATUS api_status; 420 }; 421 422 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 423 }; 424 425 union MESAPI__RESET { 426 struct { 427 union MES_API_HEADER header; 428 429 struct { 430 /* Only reset the queue given by doorbell_offset (not entire gang) */ 431 uint32_t reset_queue_only : 1; 432 /* Hang detection first then reset any queues that are hung */ 433 uint32_t hang_detect_then_reset : 1; 434 /* Only do hang detection (no reset) */ 435 uint32_t hang_detect_only : 1; 436 /* Rest HP and LP kernel queues not managed by MES */ 437 uint32_t reset_legacy_gfx : 1; 438 uint32_t reserved : 28; 439 }; 440 441 uint64_t gang_context_addr; 442 443 /* valid only if reset_queue_only = true */ 444 uint32_t doorbell_offset; 445 446 /* valid only if hang_detect_then_reset = true */ 447 uint64_t doorbell_offset_addr; 448 enum MES_QUEUE_TYPE queue_type; 449 450 /* valid only if reset_legacy_gfx = true */ 451 uint32_t pipe_id_lp; 452 uint32_t queue_id_lp; 453 uint32_t vmid_id_lp; 454 uint64_t mqd_mc_addr_lp; 455 uint32_t doorbell_offset_lp; 456 uint64_t wptr_addr_lp; 457 458 uint32_t pipe_id_hp; 459 uint32_t queue_id_hp; 460 uint32_t vmid_id_hp; 461 uint64_t mqd_mc_addr_hp; 462 uint32_t doorbell_offset_hp; 463 uint64_t wptr_addr_hp; 464 465 struct MES_API_STATUS api_status; 466 }; 467 468 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 469 }; 470 471 union MESAPI__SET_LOGGING_BUFFER { 472 struct { 473 union MES_API_HEADER header; 474 /* There are separate log buffers for each queue type */ 475 enum MES_QUEUE_TYPE log_type; 476 /* Log buffer GPU Address */ 477 uint64_t logging_buffer_addr; 478 /* number of entries in the log buffer */ 479 uint32_t number_of_entries; 480 /* Entry index at which CPU interrupt needs to be signalled */ 481 uint32_t interrupt_entry; 482 483 struct MES_API_STATUS api_status; 484 }; 485 486 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 487 }; 488 489 union MESAPI__QUERY_MES_STATUS { 490 struct { 491 union MES_API_HEADER header; 492 bool mes_healthy; /* 0 - not healthy, 1 - healthy */ 493 struct MES_API_STATUS api_status; 494 }; 495 496 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 497 }; 498 499 union MESAPI__PROGRAM_GDS { 500 struct { 501 union MES_API_HEADER header; 502 uint64_t process_context_addr; 503 uint32_t gds_base; 504 uint32_t gds_size; 505 uint32_t gws_base; 506 uint32_t gws_size; 507 uint32_t oa_mask; 508 struct MES_API_STATUS api_status; 509 }; 510 511 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 512 }; 513 514 union MESAPI__SET_DEBUG_VMID { 515 struct { 516 union MES_API_HEADER header; 517 struct MES_API_STATUS api_status; 518 union { 519 struct { 520 uint32_t use_gds : 1; 521 uint32_t operation : 2; 522 uint32_t reserved : 29; 523 } flags; 524 uint32_t u32All; 525 }; 526 uint32_t reserved; 527 uint32_t debug_vmid; 528 uint64_t process_context_addr; 529 uint64_t page_table_base_addr; 530 uint64_t process_va_start; 531 uint64_t process_va_end; 532 uint32_t gds_base; 533 uint32_t gds_size; 534 uint32_t gws_base; 535 uint32_t gws_size; 536 uint32_t oa_mask; 537 538 /* output addr of the acquired vmid value */ 539 uint64_t output_addr; 540 }; 541 542 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 543 }; 544 545 enum MESAPI_MISC_OPCODE { 546 MESAPI_MISC__WRITE_REG, 547 MESAPI_MISC__INV_GART, 548 MESAPI_MISC__QUERY_STATUS, 549 MESAPI_MISC__READ_REG, 550 MESAPI_MISC__WAIT_REG_MEM, 551 MESAPI_MISC__SET_SHADER_DEBUGGER, 552 MESAPI_MISC__MAX, 553 }; 554 555 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 }; 556 557 struct WRITE_REG { 558 uint32_t reg_offset; 559 uint32_t reg_value; 560 }; 561 562 struct READ_REG { 563 uint32_t reg_offset; 564 uint64_t buffer_addr; 565 }; 566 567 enum WRM_OPERATION { 568 WRM_OPERATION__WAIT_REG_MEM, 569 WRM_OPERATION__WR_WAIT_WR_REG, 570 WRM_OPERATION__MAX, 571 }; 572 573 struct WAIT_REG_MEM { 574 enum WRM_OPERATION op; 575 uint32_t reference; 576 uint32_t mask; 577 uint32_t reg_offset1; 578 uint32_t reg_offset2; 579 }; 580 581 struct INV_GART { 582 uint64_t inv_range_va_start; 583 uint64_t inv_range_size; 584 }; 585 586 struct QUERY_STATUS { 587 uint32_t context_id; 588 }; 589 590 struct SET_SHADER_DEBUGGER { 591 uint64_t process_context_addr; 592 union { 593 struct { 594 uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */ 595 uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */ 596 uint32_t reserved : 29; 597 uint32_t process_ctx_flush : 1; 598 }; 599 uint32_t u32all; 600 } flags; 601 uint32_t spi_gdbg_per_vmid_cntl; 602 uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */ 603 uint32_t trap_en; 604 }; 605 606 union MESAPI__MISC { 607 struct { 608 union MES_API_HEADER header; 609 enum MESAPI_MISC_OPCODE opcode; 610 struct MES_API_STATUS api_status; 611 612 union { 613 struct WRITE_REG write_reg; 614 struct INV_GART inv_gart; 615 struct QUERY_STATUS query_status; 616 struct READ_REG read_reg; 617 struct WAIT_REG_MEM wait_reg_mem; 618 struct SET_SHADER_DEBUGGER set_shader_debugger; 619 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 620 621 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 622 }; 623 }; 624 625 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 626 }; 627 628 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 629 struct { 630 union MES_API_HEADER header; 631 uint64_t page_table_base_addr; 632 uint64_t process_context_addr; 633 struct MES_API_STATUS api_status; 634 }; 635 636 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 637 }; 638 639 union MESAPI_AMD_LOG { 640 struct { 641 union MES_API_HEADER header; 642 uint64_t p_buffer_memory; 643 uint64_t p_buffer_size_used; 644 struct MES_API_STATUS api_status; 645 }; 646 647 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 648 }; 649 650 #pragma pack(pop) 651 #endif 652