1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 4) 28 29 #define MES_API_VERSION 1 30 31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG */ 32 #define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 33 34 /* Driver submits one API(cmd) as a single Frame and this command size is same 35 * for all API to ease the debugging and parsing of ring buffer. 36 */ 37 enum { API_FRAME_SIZE_IN_DWORDS = 64 }; 38 39 /* To avoid command in scheduler context to be overwritten whenenver mutilple 40 * interrupts come in, this creates another queue. 41 */ 42 enum { API_NUMBER_OF_COMMAND_MAX = 32 }; 43 44 enum MES_API_TYPE { 45 MES_API_TYPE_SCHEDULER = 1, 46 MES_API_TYPE_MAX 47 }; 48 49 enum MES_SCH_API_OPCODE { 50 MES_SCH_API_SET_HW_RSRC = 0, 51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 52 MES_SCH_API_ADD_QUEUE = 2, 53 MES_SCH_API_REMOVE_QUEUE = 3, 54 MES_SCH_API_PERFORM_YIELD = 4, 55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, 56 MES_SCH_API_SUSPEND = 6, 57 MES_SCH_API_RESUME = 7, 58 MES_SCH_API_RESET = 8, 59 MES_SCH_API_SET_LOG_BUFFER = 9, 60 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 62 MES_SCH_API_PROGRAM_GDS = 12, 63 MES_SCH_API_SET_DEBUG_VMID = 13, 64 MES_SCH_API_MISC = 14, 65 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 66 MES_SCH_API_AMD_LOG = 16, 67 MES_SCH_API_SET_HW_RSRC_1 = 19, 68 MES_SCH_API_MAX = 0xFF 69 }; 70 71 union MES_API_HEADER { 72 struct { 73 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 74 uint32_t opcode : 8; 75 uint32_t dwsize : 8; /* including header */ 76 uint32_t reserved : 12; 77 }; 78 79 uint32_t u32All; 80 }; 81 82 enum MES_AMD_PRIORITY_LEVEL { 83 AMD_PRIORITY_LEVEL_LOW = 0, 84 AMD_PRIORITY_LEVEL_NORMAL = 1, 85 AMD_PRIORITY_LEVEL_MEDIUM = 2, 86 AMD_PRIORITY_LEVEL_HIGH = 3, 87 AMD_PRIORITY_LEVEL_REALTIME = 4, 88 AMD_PRIORITY_NUM_LEVELS 89 }; 90 91 enum MES_QUEUE_TYPE { 92 MES_QUEUE_TYPE_GFX, 93 MES_QUEUE_TYPE_COMPUTE, 94 MES_QUEUE_TYPE_SDMA, 95 MES_QUEUE_TYPE_MAX, 96 }; 97 98 struct MES_API_STATUS { 99 uint64_t api_completion_fence_addr; 100 uint64_t api_completion_fence_value; 101 }; 102 103 enum { MAX_COMPUTE_PIPES = 8 }; 104 enum { MAX_GFX_PIPES = 2 }; 105 enum { MAX_SDMA_PIPES = 2 }; 106 107 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 108 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 109 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 110 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 111 112 enum { MAX_QUEUES_IN_A_GANG = 8 }; 113 114 enum VM_HUB_TYPE { 115 VM_HUB_TYPE_GC = 0, 116 VM_HUB_TYPE_MM = 1, 117 VM_HUB_TYPE_MAX, 118 }; 119 120 enum { VMID_INVALID = 0xffff }; 121 122 enum { MAX_VMID_GCHUB = 16 }; 123 enum { MAX_VMID_MMHUB = 16 }; 124 125 enum SET_DEBUG_VMID_OPERATIONS { 126 DEBUG_VMID_OP_PROGRAM = 0, 127 DEBUG_VMID_OP_ALLOCATE = 1, 128 DEBUG_VMID_OP_RELEASE = 2 129 }; 130 131 enum MES_LOG_OPERATION { 132 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 133 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 134 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 135 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 136 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 137 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 138 }; 139 140 enum MES_LOG_CONTEXT_STATE { 141 MES_LOG_CONTEXT_STATE_IDLE = 0, 142 MES_LOG_CONTEXT_STATE_RUNNING = 1, 143 MES_LOG_CONTEXT_STATE_READY = 2, 144 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 145 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 146 }; 147 148 struct MES_LOG_CONTEXT_STATE_CHANGE { 149 void *h_context; 150 enum MES_LOG_CONTEXT_STATE new_context_state; 151 }; 152 153 struct MES_LOG_QUEUE_NEW_WORK { 154 uint64_t h_queue; 155 uint64_t reserved; 156 }; 157 158 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 159 uint64_t h_queue; 160 uint64_t h_sync_object; 161 }; 162 163 struct MES_LOG_QUEUE_NO_MORE_WORK { 164 uint64_t h_queue; 165 uint64_t reserved; 166 }; 167 168 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 169 uint64_t h_queue; 170 uint64_t h_sync_object; 171 }; 172 173 struct MES_LOG_ENTRY_HEADER { 174 uint32_t first_free_entry_index; 175 uint32_t wraparound_count; 176 uint64_t number_of_entries; 177 uint64_t reserved[2]; 178 }; 179 180 struct MES_LOG_ENTRY_DATA { 181 uint64_t gpu_time_stamp; 182 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 183 uint32_t reserved_operation_type_bits; 184 union { 185 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 186 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 187 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 188 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 189 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 190 uint64_t all[2]; 191 }; 192 }; 193 194 struct MES_LOG_BUFFER { 195 struct MES_LOG_ENTRY_HEADER header; 196 struct MES_LOG_ENTRY_DATA entries[1]; 197 }; 198 199 enum MES_SWIP_TO_HWIP_DEF { 200 MES_MAX_HWIP_SEGMENT = 8, 201 }; 202 203 union MESAPI_SET_HW_RESOURCES { 204 struct { 205 union MES_API_HEADER header; 206 uint32_t vmid_mask_mmhub; 207 uint32_t vmid_mask_gfxhub; 208 uint32_t gds_size; 209 uint32_t paging_vmid; 210 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 211 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 212 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 213 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 214 uint64_t g_sch_ctx_gpu_mc_ptr; 215 uint64_t query_status_fence_gpu_mc_ptr; 216 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 217 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 218 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 219 struct MES_API_STATUS api_status; 220 union { 221 struct { 222 uint32_t disable_reset : 1; 223 uint32_t use_different_vmid_compute : 1; 224 uint32_t disable_mes_log : 1; 225 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 226 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 227 uint32_t second_gfx_pipe_enabled : 1; 228 uint32_t enable_level_process_quantum_check : 1; 229 uint32_t legacy_sch_mode : 1; 230 uint32_t disable_add_queue_wptr_mc_addr : 1; 231 uint32_t enable_mes_event_int_logging : 1; 232 uint32_t enable_reg_active_poll : 1; 233 uint32_t use_disable_queue_in_legacy_uq_preemption : 1; 234 uint32_t send_write_data : 1; 235 uint32_t os_tdr_timeout_override : 1; 236 uint32_t use_rs64mem_for_proc_gang_ctx : 1; 237 uint32_t use_add_queue_unmap_flag_addr : 1; 238 uint32_t enable_mes_sch_stb_log : 1; 239 uint32_t limit_single_process : 1; 240 uint32_t is_strix_tmz_wa_enabled :1; 241 uint32_t enable_lr_compute_wa : 2; 242 uint32_t enable_compute_pipe_reset : 1; 243 uint32_t reserved : 10; 244 }; 245 uint32_t uint32_t_all; 246 }; 247 uint32_t oversubscription_timer; 248 uint64_t doorbell_info; 249 uint64_t event_intr_history_gpu_mc_ptr; 250 uint64_t timestamp; 251 uint32_t os_tdr_timeout_in_sec; 252 }; 253 254 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 255 }; 256 257 union MESAPI_SET_HW_RESOURCES_1 { 258 struct { 259 union MES_API_HEADER header; 260 struct MES_API_STATUS api_status; 261 uint64_t timestamp; 262 union { 263 struct { 264 uint32_t enable_mes_info_ctx : 1; 265 uint32_t reserved : 31; 266 }; 267 uint32_t uint32_all; 268 }; 269 uint64_t mes_info_ctx_mc_addr; 270 uint32_t mes_info_ctx_size; 271 uint64_t reserved1; 272 uint64_t cleaner_shader_fence_mc_addr; 273 }; 274 275 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 276 }; 277 278 union MESAPI__ADD_QUEUE { 279 struct { 280 union MES_API_HEADER header; 281 uint32_t process_id; 282 uint64_t page_table_base_addr; 283 uint64_t process_va_start; 284 uint64_t process_va_end; 285 uint64_t process_quantum; 286 uint64_t process_context_addr; 287 uint64_t gang_quantum; 288 uint64_t gang_context_addr; 289 uint32_t inprocess_gang_priority; 290 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 291 uint32_t doorbell_offset; 292 uint64_t mqd_addr; 293 uint64_t wptr_addr; 294 uint64_t h_context; 295 uint64_t h_queue; 296 enum MES_QUEUE_TYPE queue_type; 297 uint32_t gds_base; 298 uint32_t gds_size; 299 uint32_t gws_base; 300 uint32_t gws_size; 301 uint32_t oa_mask; 302 uint64_t trap_handler_addr; 303 uint32_t vm_context_cntl; 304 305 struct { 306 uint32_t paging : 1; 307 uint32_t debug_vmid : 4; 308 uint32_t program_gds : 1; 309 uint32_t is_gang_suspended : 1; 310 uint32_t is_tmz_queue : 1; 311 uint32_t map_kiq_utility_queue : 1; 312 uint32_t is_kfd_process : 1; 313 uint32_t trap_en : 1; 314 uint32_t is_aql_queue : 1; 315 uint32_t skip_process_ctx_clear : 1; 316 uint32_t map_legacy_kq : 1; 317 uint32_t exclusively_scheduled : 1; 318 uint32_t is_long_running : 1; 319 uint32_t is_dwm_queue : 1; 320 uint32_t is_video_blit_queue : 1; 321 uint32_t reserved : 14; 322 }; 323 struct MES_API_STATUS api_status; 324 uint64_t tma_addr; 325 uint32_t sch_id; 326 uint64_t timestamp; 327 uint32_t process_context_array_index; 328 uint32_t gang_context_array_index; 329 uint32_t pipe_id; 330 uint32_t queue_id; 331 uint32_t alignment_mode_setting; 332 uint32_t full_sh_mem_config_data; 333 uint64_t unmap_flag_addr; 334 }; 335 336 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 337 }; 338 339 union MESAPI__REMOVE_QUEUE { 340 struct { 341 union MES_API_HEADER header; 342 uint32_t doorbell_offset; 343 uint64_t gang_context_addr; 344 345 struct { 346 uint32_t unmap_legacy_gfx_queue : 1; 347 uint32_t unmap_kiq_utility_queue : 1; 348 uint32_t preempt_legacy_gfx_queue : 1; 349 uint32_t unmap_legacy_queue : 1; 350 uint32_t remove_queue_after_reset : 1; 351 uint32_t reserved : 27; 352 }; 353 struct MES_API_STATUS api_status; 354 355 uint32_t pipe_id; 356 uint32_t queue_id; 357 358 uint64_t tf_addr; 359 uint32_t tf_data; 360 361 enum MES_QUEUE_TYPE queue_type; 362 uint64_t timestamp; 363 }; 364 365 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 366 }; 367 368 union MESAPI__SET_SCHEDULING_CONFIG { 369 struct { 370 union MES_API_HEADER header; 371 /* Grace period when preempting another priority band for this 372 * priority band. The value for idle priority band is ignored, 373 * as it never preempts other bands. 374 */ 375 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 376 /* Default quantum for scheduling across processes within 377 * a priority band. 378 */ 379 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 380 /* Default grace period for processes that preempt each other 381 * within a priority band. 382 */ 383 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 384 /* For normal level this field specifies the target GPU 385 * percentage in situations when it's starved by the high level. 386 * Valid values are between 0 and 50, with the default being 10. 387 */ 388 uint32_t normal_yield_percent; 389 struct MES_API_STATUS api_status; 390 }; 391 392 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 393 }; 394 395 union MESAPI__PERFORM_YIELD { 396 struct { 397 union MES_API_HEADER header; 398 uint32_t dummy; 399 struct MES_API_STATUS api_status; 400 }; 401 402 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 403 }; 404 405 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 406 struct { 407 union MES_API_HEADER header; 408 uint32_t inprocess_gang_priority; 409 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 410 uint64_t gang_quantum; 411 uint64_t gang_context_addr; 412 struct MES_API_STATUS api_status; 413 }; 414 415 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 416 }; 417 418 union MESAPI__SUSPEND { 419 struct { 420 union MES_API_HEADER header; 421 /* false - suspend all gangs; true - specific gang */ 422 struct { 423 uint32_t suspend_all_gangs : 1; 424 uint32_t reserved : 31; 425 }; 426 /* gang_context_addr is valid only if suspend_all = false */ 427 uint64_t gang_context_addr; 428 429 uint64_t suspend_fence_addr; 430 uint32_t suspend_fence_value; 431 432 struct MES_API_STATUS api_status; 433 uint32_t doorbell_offset; 434 }; 435 436 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 437 }; 438 439 union MESAPI__RESUME { 440 struct { 441 union MES_API_HEADER header; 442 /* false - resume all gangs; true - specified gang */ 443 struct { 444 uint32_t resume_all_gangs : 1; 445 uint32_t reserved : 31; 446 }; 447 /* valid only if resume_all_gangs = false */ 448 uint64_t gang_context_addr; 449 450 struct MES_API_STATUS api_status; 451 uint32_t doorbell_offset; 452 }; 453 454 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 455 }; 456 457 union MESAPI__RESET { 458 struct { 459 union MES_API_HEADER header; 460 461 struct { 462 /* Only reset the queue given by doorbell_offset (not entire gang) */ 463 uint32_t reset_queue_only : 1; 464 /* Hang detection first then reset any queues that are hung */ 465 uint32_t hang_detect_then_reset : 1; 466 /* Only do hang detection (no reset) */ 467 uint32_t hang_detect_only : 1; 468 /* Rest HP and LP kernel queues not managed by MES */ 469 uint32_t reset_legacy_gfx : 1; 470 uint32_t reserved : 28; 471 }; 472 473 uint64_t gang_context_addr; 474 475 /* valid only if reset_queue_only = true */ 476 uint32_t doorbell_offset; 477 478 /* valid only if hang_detect_then_reset = true */ 479 uint64_t doorbell_offset_addr; 480 enum MES_QUEUE_TYPE queue_type; 481 482 /* valid only if reset_legacy_gfx = true */ 483 uint32_t pipe_id_lp; 484 uint32_t queue_id_lp; 485 uint32_t vmid_id_lp; 486 uint64_t mqd_mc_addr_lp; 487 uint32_t doorbell_offset_lp; 488 uint64_t wptr_addr_lp; 489 490 uint32_t pipe_id_hp; 491 uint32_t queue_id_hp; 492 uint32_t vmid_id_hp; 493 uint64_t mqd_mc_addr_hp; 494 uint32_t doorbell_offset_hp; 495 uint64_t wptr_addr_hp; 496 497 struct MES_API_STATUS api_status; 498 }; 499 500 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 501 }; 502 503 union MESAPI__SET_LOGGING_BUFFER { 504 struct { 505 union MES_API_HEADER header; 506 /* There are separate log buffers for each queue type */ 507 enum MES_QUEUE_TYPE log_type; 508 /* Log buffer GPU Address */ 509 uint64_t logging_buffer_addr; 510 /* number of entries in the log buffer */ 511 uint32_t number_of_entries; 512 /* Entry index at which CPU interrupt needs to be signalled */ 513 uint32_t interrupt_entry; 514 515 struct MES_API_STATUS api_status; 516 }; 517 518 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 519 }; 520 521 enum MES_API_QUERY_MES_OPCODE { 522 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE, 523 MES_API_QUERY_MES__GET_CAPS = MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE, 524 MES_API_QUERY_MES__CHECK_HEALTHY, 525 MES_API_QUERY_MES__MAX, 526 }; 527 528 enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 }; 529 530 /** 531 * Obsolete 532 * to be removed once KMD stopped refering to it. 533 * use MES_API_QUERY_MES__CAPS instead 534 */ 535 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE { 536 uint64_t proc_ctx_array_size_addr; 537 uint64_t gang_ctx_array_size_addr; 538 }; 539 540 struct MES_API_QUERY_MES__HEALTHY_CHECK { 541 uint64_t healthy_addr; 542 }; 543 544 struct MES_API_QUERY_MES__CAPS { 545 uint64_t proc_ctx_array_size_addr; 546 uint64_t gang_ctx_array_size_addr; 547 uint64_t features_enablement_addr; 548 }; 549 550 union MESAPI__QUERY_MES_STATUS { 551 struct { 552 union MES_API_HEADER header; 553 enum MES_API_QUERY_MES_OPCODE subopcode; 554 struct MES_API_STATUS api_status; 555 uint64_t timestamp; 556 union { 557 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size; 558 struct MES_API_QUERY_MES__CAPS caps; 559 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check; 560 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS]; 561 }; 562 }; 563 564 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 565 }; 566 567 union MESAPI__PROGRAM_GDS { 568 struct { 569 union MES_API_HEADER header; 570 uint64_t process_context_addr; 571 uint32_t gds_base; 572 uint32_t gds_size; 573 uint32_t gws_base; 574 uint32_t gws_size; 575 uint32_t oa_mask; 576 struct MES_API_STATUS api_status; 577 }; 578 579 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 580 }; 581 582 union MESAPI__SET_DEBUG_VMID { 583 struct { 584 union MES_API_HEADER header; 585 struct MES_API_STATUS api_status; 586 union { 587 struct { 588 uint32_t use_gds : 1; 589 uint32_t operation : 2; 590 uint32_t reserved : 29; 591 } flags; 592 uint32_t u32All; 593 }; 594 uint32_t reserved; 595 uint32_t debug_vmid; 596 uint64_t process_context_addr; 597 uint64_t page_table_base_addr; 598 uint64_t process_va_start; 599 uint64_t process_va_end; 600 uint32_t gds_base; 601 uint32_t gds_size; 602 uint32_t gws_base; 603 uint32_t gws_size; 604 uint32_t oa_mask; 605 606 /* output addr of the acquired vmid value */ 607 uint64_t output_addr; 608 }; 609 610 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 611 }; 612 613 enum MESAPI_MISC_OPCODE { 614 MESAPI_MISC__WRITE_REG, 615 MESAPI_MISC__INV_GART, 616 MESAPI_MISC__QUERY_STATUS, 617 MESAPI_MISC__READ_REG, 618 MESAPI_MISC__WAIT_REG_MEM, 619 MESAPI_MISC__SET_SHADER_DEBUGGER, 620 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE, 621 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES, 622 MESAPI_MISC__CHANGE_CONFIG, 623 MESAPI_MISC__LAUNCH_CLEANER_SHADER, 624 625 MESAPI_MISC__MAX, 626 }; 627 628 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 }; 629 630 struct WRITE_REG { 631 uint32_t reg_offset; 632 uint32_t reg_value; 633 }; 634 635 struct READ_REG { 636 uint32_t reg_offset; 637 uint64_t buffer_addr; 638 }; 639 640 enum WRM_OPERATION { 641 WRM_OPERATION__WAIT_REG_MEM, 642 WRM_OPERATION__WR_WAIT_WR_REG, 643 WRM_OPERATION__MAX, 644 }; 645 646 struct WAIT_REG_MEM { 647 enum WRM_OPERATION op; 648 uint32_t reference; 649 uint32_t mask; 650 uint32_t reg_offset1; 651 uint32_t reg_offset2; 652 }; 653 654 struct INV_GART { 655 uint64_t inv_range_va_start; 656 uint64_t inv_range_size; 657 }; 658 659 struct QUERY_STATUS { 660 uint32_t context_id; 661 }; 662 663 struct SET_SHADER_DEBUGGER { 664 uint64_t process_context_addr; 665 union { 666 struct { 667 uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */ 668 uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */ 669 uint32_t reserved : 29; 670 uint32_t process_ctx_flush : 1; 671 }; 672 uint32_t u32all; 673 } flags; 674 uint32_t spi_gdbg_per_vmid_cntl; 675 uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */ 676 uint32_t trap_en; 677 }; 678 679 enum MESAPI_MISC__CHANGE_CONFIG_OPTION { 680 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0, 681 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1, 682 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2, 683 684 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F 685 }; 686 687 struct CHANGE_CONFIG { 688 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode; 689 union { 690 struct { 691 uint32_t limit_single_process : 1; 692 uint32_t enable_hws_logging_buffer : 1; 693 uint32_t reserved : 31; 694 } bits; 695 uint32_t all; 696 } option; 697 698 struct { 699 uint32_t tdr_level; 700 uint32_t tdr_delay; 701 } tdr_config; 702 }; 703 704 union MESAPI__MISC { 705 struct { 706 union MES_API_HEADER header; 707 enum MESAPI_MISC_OPCODE opcode; 708 struct MES_API_STATUS api_status; 709 710 union { 711 struct WRITE_REG write_reg; 712 struct INV_GART inv_gart; 713 struct QUERY_STATUS query_status; 714 struct READ_REG read_reg; 715 struct WAIT_REG_MEM wait_reg_mem; 716 struct SET_SHADER_DEBUGGER set_shader_debugger; 717 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 718 struct CHANGE_CONFIG change_config; 719 720 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 721 }; 722 }; 723 724 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 725 }; 726 727 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 728 struct { 729 union MES_API_HEADER header; 730 uint64_t page_table_base_addr; 731 uint64_t process_context_addr; 732 struct MES_API_STATUS api_status; 733 }; 734 735 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 736 }; 737 738 union MESAPI_AMD_LOG { 739 struct { 740 union MES_API_HEADER header; 741 uint64_t p_buffer_memory; 742 uint64_t p_buffer_size_used; 743 struct MES_API_STATUS api_status; 744 }; 745 746 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 747 }; 748 749 #pragma pack(pop) 750 #endif 751