1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 4) 28 29 #define MES_API_VERSION 1 30 31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG */ 32 #define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 33 34 /* Driver submits one API(cmd) as a single Frame and this command size is same 35 * for all API to ease the debugging and parsing of ring buffer. 36 */ 37 enum { API_FRAME_SIZE_IN_DWORDS = 64 }; 38 39 /* To avoid command in scheduler context to be overwritten whenenver mutilple 40 * interrupts come in, this creates another queue. 41 */ 42 enum { API_NUMBER_OF_COMMAND_MAX = 32 }; 43 44 enum MES_API_TYPE { 45 MES_API_TYPE_SCHEDULER = 1, 46 MES_API_TYPE_MAX 47 }; 48 49 enum MES_SCH_API_OPCODE { 50 MES_SCH_API_SET_HW_RSRC = 0, 51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 52 MES_SCH_API_ADD_QUEUE = 2, 53 MES_SCH_API_REMOVE_QUEUE = 3, 54 MES_SCH_API_PERFORM_YIELD = 4, 55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, 56 MES_SCH_API_SUSPEND = 6, 57 MES_SCH_API_RESUME = 7, 58 MES_SCH_API_RESET = 8, 59 MES_SCH_API_SET_LOG_BUFFER = 9, 60 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 62 MES_SCH_API_PROGRAM_GDS = 12, 63 MES_SCH_API_SET_DEBUG_VMID = 13, 64 MES_SCH_API_MISC = 14, 65 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 66 MES_SCH_API_AMD_LOG = 16, 67 MES_SCH_API_SET_HW_RSRC_1 = 19, 68 MES_SCH_API_MAX = 0xFF 69 }; 70 71 union MES_API_HEADER { 72 struct { 73 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 74 uint32_t opcode : 8; 75 uint32_t dwsize : 8; /* including header */ 76 uint32_t reserved : 12; 77 }; 78 79 uint32_t u32All; 80 }; 81 82 enum MES_AMD_PRIORITY_LEVEL { 83 AMD_PRIORITY_LEVEL_LOW = 0, 84 AMD_PRIORITY_LEVEL_NORMAL = 1, 85 AMD_PRIORITY_LEVEL_MEDIUM = 2, 86 AMD_PRIORITY_LEVEL_HIGH = 3, 87 AMD_PRIORITY_LEVEL_REALTIME = 4, 88 AMD_PRIORITY_NUM_LEVELS 89 }; 90 91 enum MES_QUEUE_TYPE { 92 MES_QUEUE_TYPE_GFX, 93 MES_QUEUE_TYPE_COMPUTE, 94 MES_QUEUE_TYPE_SDMA, 95 MES_QUEUE_TYPE_MAX, 96 }; 97 98 struct MES_API_STATUS { 99 uint64_t api_completion_fence_addr; 100 uint64_t api_completion_fence_value; 101 }; 102 103 enum { MAX_COMPUTE_PIPES = 8 }; 104 enum { MAX_GFX_PIPES = 2 }; 105 enum { MAX_SDMA_PIPES = 2 }; 106 107 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 108 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 109 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 110 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 111 112 enum { MAX_QUEUES_IN_A_GANG = 8 }; 113 114 enum VM_HUB_TYPE { 115 VM_HUB_TYPE_GC = 0, 116 VM_HUB_TYPE_MM = 1, 117 VM_HUB_TYPE_MAX, 118 }; 119 120 enum { VMID_INVALID = 0xffff }; 121 122 enum { MAX_VMID_GCHUB = 16 }; 123 enum { MAX_VMID_MMHUB = 16 }; 124 125 enum SET_DEBUG_VMID_OPERATIONS { 126 DEBUG_VMID_OP_PROGRAM = 0, 127 DEBUG_VMID_OP_ALLOCATE = 1, 128 DEBUG_VMID_OP_RELEASE = 2 129 }; 130 131 enum MES_LOG_OPERATION { 132 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 133 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 134 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 135 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 136 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 137 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 138 }; 139 140 enum MES_LOG_CONTEXT_STATE { 141 MES_LOG_CONTEXT_STATE_IDLE = 0, 142 MES_LOG_CONTEXT_STATE_RUNNING = 1, 143 MES_LOG_CONTEXT_STATE_READY = 2, 144 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 145 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 146 }; 147 148 struct MES_LOG_CONTEXT_STATE_CHANGE { 149 void *h_context; 150 enum MES_LOG_CONTEXT_STATE new_context_state; 151 }; 152 153 struct MES_LOG_QUEUE_NEW_WORK { 154 uint64_t h_queue; 155 uint64_t reserved; 156 }; 157 158 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 159 uint64_t h_queue; 160 uint64_t h_sync_object; 161 }; 162 163 struct MES_LOG_QUEUE_NO_MORE_WORK { 164 uint64_t h_queue; 165 uint64_t reserved; 166 }; 167 168 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 169 uint64_t h_queue; 170 uint64_t h_sync_object; 171 }; 172 173 struct MES_LOG_ENTRY_HEADER { 174 uint32_t first_free_entry_index; 175 uint32_t wraparound_count; 176 uint64_t number_of_entries; 177 uint64_t reserved[2]; 178 }; 179 180 struct MES_LOG_ENTRY_DATA { 181 uint64_t gpu_time_stamp; 182 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 183 uint32_t reserved_operation_type_bits; 184 union { 185 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 186 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 187 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 188 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 189 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 190 uint64_t all[2]; 191 }; 192 }; 193 194 struct MES_LOG_BUFFER { 195 struct MES_LOG_ENTRY_HEADER header; 196 struct MES_LOG_ENTRY_DATA entries[1]; 197 }; 198 199 enum MES_SWIP_TO_HWIP_DEF { 200 MES_MAX_HWIP_SEGMENT = 8, 201 }; 202 203 union MESAPI_SET_HW_RESOURCES { 204 struct { 205 union MES_API_HEADER header; 206 uint32_t vmid_mask_mmhub; 207 uint32_t vmid_mask_gfxhub; 208 uint32_t gds_size; 209 uint32_t paging_vmid; 210 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 211 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 212 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 213 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 214 uint64_t g_sch_ctx_gpu_mc_ptr; 215 uint64_t query_status_fence_gpu_mc_ptr; 216 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 217 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 218 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 219 struct MES_API_STATUS api_status; 220 union { 221 struct { 222 uint32_t disable_reset : 1; 223 uint32_t use_different_vmid_compute : 1; 224 uint32_t disable_mes_log : 1; 225 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 226 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 227 uint32_t second_gfx_pipe_enabled : 1; 228 uint32_t enable_level_process_quantum_check : 1; 229 uint32_t legacy_sch_mode : 1; 230 uint32_t disable_add_queue_wptr_mc_addr : 1; 231 uint32_t enable_mes_event_int_logging : 1; 232 uint32_t enable_reg_active_poll : 1; 233 uint32_t use_disable_queue_in_legacy_uq_preemption : 1; 234 uint32_t send_write_data : 1; 235 uint32_t os_tdr_timeout_override : 1; 236 uint32_t use_rs64mem_for_proc_gang_ctx : 1; 237 uint32_t use_add_queue_unmap_flag_addr : 1; 238 uint32_t enable_mes_sch_stb_log : 1; 239 uint32_t limit_single_process : 1; 240 uint32_t is_strix_tmz_wa_enabled :1; 241 uint32_t enable_lr_compute_wa : 1; 242 uint32_t reserved : 12; 243 }; 244 uint32_t uint32_t_all; 245 }; 246 uint32_t oversubscription_timer; 247 uint64_t doorbell_info; 248 uint64_t event_intr_history_gpu_mc_ptr; 249 uint64_t timestamp; 250 uint32_t os_tdr_timeout_in_sec; 251 }; 252 253 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 254 }; 255 256 union MESAPI_SET_HW_RESOURCES_1 { 257 struct { 258 union MES_API_HEADER header; 259 struct MES_API_STATUS api_status; 260 uint64_t timestamp; 261 union { 262 struct { 263 uint32_t enable_mes_info_ctx : 1; 264 uint32_t reserved : 31; 265 }; 266 uint32_t uint32_all; 267 }; 268 uint64_t mes_info_ctx_mc_addr; 269 uint32_t mes_info_ctx_size; 270 uint64_t reserved1; 271 uint64_t cleaner_shader_fence_mc_addr; 272 }; 273 274 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 275 }; 276 277 union MESAPI__ADD_QUEUE { 278 struct { 279 union MES_API_HEADER header; 280 uint32_t process_id; 281 uint64_t page_table_base_addr; 282 uint64_t process_va_start; 283 uint64_t process_va_end; 284 uint64_t process_quantum; 285 uint64_t process_context_addr; 286 uint64_t gang_quantum; 287 uint64_t gang_context_addr; 288 uint32_t inprocess_gang_priority; 289 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 290 uint32_t doorbell_offset; 291 uint64_t mqd_addr; 292 uint64_t wptr_addr; 293 uint64_t h_context; 294 uint64_t h_queue; 295 enum MES_QUEUE_TYPE queue_type; 296 uint32_t gds_base; 297 uint32_t gds_size; 298 uint32_t gws_base; 299 uint32_t gws_size; 300 uint32_t oa_mask; 301 uint64_t trap_handler_addr; 302 uint32_t vm_context_cntl; 303 304 struct { 305 uint32_t paging : 1; 306 uint32_t debug_vmid : 4; 307 uint32_t program_gds : 1; 308 uint32_t is_gang_suspended : 1; 309 uint32_t is_tmz_queue : 1; 310 uint32_t map_kiq_utility_queue : 1; 311 uint32_t is_kfd_process : 1; 312 uint32_t trap_en : 1; 313 uint32_t is_aql_queue : 1; 314 uint32_t skip_process_ctx_clear : 1; 315 uint32_t map_legacy_kq : 1; 316 uint32_t exclusively_scheduled : 1; 317 uint32_t is_long_running : 1; 318 uint32_t is_dwm_queue : 1; 319 uint32_t is_video_blit_queue : 1; 320 uint32_t reserved : 14; 321 }; 322 struct MES_API_STATUS api_status; 323 uint64_t tma_addr; 324 uint32_t sch_id; 325 uint64_t timestamp; 326 uint32_t process_context_array_index; 327 uint32_t gang_context_array_index; 328 uint32_t pipe_id; 329 uint32_t queue_id; 330 uint32_t alignment_mode_setting; 331 uint64_t unmap_flag_addr; 332 }; 333 334 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 335 }; 336 337 union MESAPI__REMOVE_QUEUE { 338 struct { 339 union MES_API_HEADER header; 340 uint32_t doorbell_offset; 341 uint64_t gang_context_addr; 342 343 struct { 344 uint32_t unmap_legacy_gfx_queue : 1; 345 uint32_t unmap_kiq_utility_queue : 1; 346 uint32_t preempt_legacy_gfx_queue : 1; 347 uint32_t unmap_legacy_queue : 1; 348 uint32_t reserved : 28; 349 }; 350 struct MES_API_STATUS api_status; 351 352 uint32_t pipe_id; 353 uint32_t queue_id; 354 355 uint64_t tf_addr; 356 uint32_t tf_data; 357 358 enum MES_QUEUE_TYPE queue_type; 359 }; 360 361 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 362 }; 363 364 union MESAPI__SET_SCHEDULING_CONFIG { 365 struct { 366 union MES_API_HEADER header; 367 /* Grace period when preempting another priority band for this 368 * priority band. The value for idle priority band is ignored, 369 * as it never preempts other bands. 370 */ 371 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 372 /* Default quantum for scheduling across processes within 373 * a priority band. 374 */ 375 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 376 /* Default grace period for processes that preempt each other 377 * within a priority band. 378 */ 379 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 380 /* For normal level this field specifies the target GPU 381 * percentage in situations when it's starved by the high level. 382 * Valid values are between 0 and 50, with the default being 10. 383 */ 384 uint32_t normal_yield_percent; 385 struct MES_API_STATUS api_status; 386 }; 387 388 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 389 }; 390 391 union MESAPI__PERFORM_YIELD { 392 struct { 393 union MES_API_HEADER header; 394 uint32_t dummy; 395 struct MES_API_STATUS api_status; 396 }; 397 398 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 399 }; 400 401 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 402 struct { 403 union MES_API_HEADER header; 404 uint32_t inprocess_gang_priority; 405 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 406 uint64_t gang_quantum; 407 uint64_t gang_context_addr; 408 struct MES_API_STATUS api_status; 409 }; 410 411 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 412 }; 413 414 union MESAPI__SUSPEND { 415 struct { 416 union MES_API_HEADER header; 417 /* false - suspend all gangs; true - specific gang */ 418 struct { 419 uint32_t suspend_all_gangs : 1; 420 uint32_t reserved : 31; 421 }; 422 /* gang_context_addr is valid only if suspend_all = false */ 423 uint64_t gang_context_addr; 424 425 uint64_t suspend_fence_addr; 426 uint32_t suspend_fence_value; 427 428 struct MES_API_STATUS api_status; 429 }; 430 431 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 432 }; 433 434 union MESAPI__RESUME { 435 struct { 436 union MES_API_HEADER header; 437 /* false - resume all gangs; true - specified gang */ 438 struct { 439 uint32_t resume_all_gangs : 1; 440 uint32_t reserved : 31; 441 }; 442 /* valid only if resume_all_gangs = false */ 443 uint64_t gang_context_addr; 444 445 struct MES_API_STATUS api_status; 446 }; 447 448 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 449 }; 450 451 union MESAPI__RESET { 452 struct { 453 union MES_API_HEADER header; 454 455 struct { 456 /* Only reset the queue given by doorbell_offset (not entire gang) */ 457 uint32_t reset_queue_only : 1; 458 /* Hang detection first then reset any queues that are hung */ 459 uint32_t hang_detect_then_reset : 1; 460 /* Only do hang detection (no reset) */ 461 uint32_t hang_detect_only : 1; 462 /* Rest HP and LP kernel queues not managed by MES */ 463 uint32_t reset_legacy_gfx : 1; 464 uint32_t reserved : 28; 465 }; 466 467 uint64_t gang_context_addr; 468 469 /* valid only if reset_queue_only = true */ 470 uint32_t doorbell_offset; 471 472 /* valid only if hang_detect_then_reset = true */ 473 uint64_t doorbell_offset_addr; 474 enum MES_QUEUE_TYPE queue_type; 475 476 /* valid only if reset_legacy_gfx = true */ 477 uint32_t pipe_id_lp; 478 uint32_t queue_id_lp; 479 uint32_t vmid_id_lp; 480 uint64_t mqd_mc_addr_lp; 481 uint32_t doorbell_offset_lp; 482 uint64_t wptr_addr_lp; 483 484 uint32_t pipe_id_hp; 485 uint32_t queue_id_hp; 486 uint32_t vmid_id_hp; 487 uint64_t mqd_mc_addr_hp; 488 uint32_t doorbell_offset_hp; 489 uint64_t wptr_addr_hp; 490 491 struct MES_API_STATUS api_status; 492 }; 493 494 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 495 }; 496 497 union MESAPI__SET_LOGGING_BUFFER { 498 struct { 499 union MES_API_HEADER header; 500 /* There are separate log buffers for each queue type */ 501 enum MES_QUEUE_TYPE log_type; 502 /* Log buffer GPU Address */ 503 uint64_t logging_buffer_addr; 504 /* number of entries in the log buffer */ 505 uint32_t number_of_entries; 506 /* Entry index at which CPU interrupt needs to be signalled */ 507 uint32_t interrupt_entry; 508 509 struct MES_API_STATUS api_status; 510 }; 511 512 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 513 }; 514 515 union MESAPI__QUERY_MES_STATUS { 516 struct { 517 union MES_API_HEADER header; 518 bool mes_healthy; /* 0 - not healthy, 1 - healthy */ 519 struct MES_API_STATUS api_status; 520 }; 521 522 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 523 }; 524 525 union MESAPI__PROGRAM_GDS { 526 struct { 527 union MES_API_HEADER header; 528 uint64_t process_context_addr; 529 uint32_t gds_base; 530 uint32_t gds_size; 531 uint32_t gws_base; 532 uint32_t gws_size; 533 uint32_t oa_mask; 534 struct MES_API_STATUS api_status; 535 }; 536 537 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 538 }; 539 540 union MESAPI__SET_DEBUG_VMID { 541 struct { 542 union MES_API_HEADER header; 543 struct MES_API_STATUS api_status; 544 union { 545 struct { 546 uint32_t use_gds : 1; 547 uint32_t operation : 2; 548 uint32_t reserved : 29; 549 } flags; 550 uint32_t u32All; 551 }; 552 uint32_t reserved; 553 uint32_t debug_vmid; 554 uint64_t process_context_addr; 555 uint64_t page_table_base_addr; 556 uint64_t process_va_start; 557 uint64_t process_va_end; 558 uint32_t gds_base; 559 uint32_t gds_size; 560 uint32_t gws_base; 561 uint32_t gws_size; 562 uint32_t oa_mask; 563 564 /* output addr of the acquired vmid value */ 565 uint64_t output_addr; 566 }; 567 568 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 569 }; 570 571 enum MESAPI_MISC_OPCODE { 572 MESAPI_MISC__WRITE_REG, 573 MESAPI_MISC__INV_GART, 574 MESAPI_MISC__QUERY_STATUS, 575 MESAPI_MISC__READ_REG, 576 MESAPI_MISC__WAIT_REG_MEM, 577 MESAPI_MISC__SET_SHADER_DEBUGGER, 578 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE, 579 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES, 580 MESAPI_MISC__CHANGE_CONFIG, 581 MESAPI_MISC__LAUNCH_CLEANER_SHADER, 582 583 MESAPI_MISC__MAX, 584 }; 585 586 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 }; 587 588 struct WRITE_REG { 589 uint32_t reg_offset; 590 uint32_t reg_value; 591 }; 592 593 struct READ_REG { 594 uint32_t reg_offset; 595 uint64_t buffer_addr; 596 }; 597 598 enum WRM_OPERATION { 599 WRM_OPERATION__WAIT_REG_MEM, 600 WRM_OPERATION__WR_WAIT_WR_REG, 601 WRM_OPERATION__MAX, 602 }; 603 604 struct WAIT_REG_MEM { 605 enum WRM_OPERATION op; 606 uint32_t reference; 607 uint32_t mask; 608 uint32_t reg_offset1; 609 uint32_t reg_offset2; 610 }; 611 612 struct INV_GART { 613 uint64_t inv_range_va_start; 614 uint64_t inv_range_size; 615 }; 616 617 struct QUERY_STATUS { 618 uint32_t context_id; 619 }; 620 621 struct SET_SHADER_DEBUGGER { 622 uint64_t process_context_addr; 623 union { 624 struct { 625 uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */ 626 uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */ 627 uint32_t reserved : 29; 628 uint32_t process_ctx_flush : 1; 629 }; 630 uint32_t u32all; 631 } flags; 632 uint32_t spi_gdbg_per_vmid_cntl; 633 uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */ 634 uint32_t trap_en; 635 }; 636 637 enum MESAPI_MISC__CHANGE_CONFIG_OPTION { 638 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0, 639 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1, 640 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2, 641 642 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F 643 }; 644 645 struct CHANGE_CONFIG { 646 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode; 647 union { 648 struct { 649 uint32_t limit_single_process : 1; 650 uint32_t enable_hws_logging_buffer : 1; 651 uint32_t reserved : 31; 652 } bits; 653 uint32_t all; 654 } option; 655 656 struct { 657 uint32_t tdr_level; 658 uint32_t tdr_delay; 659 } tdr_config; 660 }; 661 662 union MESAPI__MISC { 663 struct { 664 union MES_API_HEADER header; 665 enum MESAPI_MISC_OPCODE opcode; 666 struct MES_API_STATUS api_status; 667 668 union { 669 struct WRITE_REG write_reg; 670 struct INV_GART inv_gart; 671 struct QUERY_STATUS query_status; 672 struct READ_REG read_reg; 673 struct WAIT_REG_MEM wait_reg_mem; 674 struct SET_SHADER_DEBUGGER set_shader_debugger; 675 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 676 struct CHANGE_CONFIG change_config; 677 678 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 679 }; 680 }; 681 682 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 683 }; 684 685 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 686 struct { 687 union MES_API_HEADER header; 688 uint64_t page_table_base_addr; 689 uint64_t process_context_addr; 690 struct MES_API_STATUS api_status; 691 }; 692 693 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 694 }; 695 696 union MESAPI_AMD_LOG { 697 struct { 698 union MES_API_HEADER header; 699 uint64_t p_buffer_memory; 700 uint64_t p_buffer_size_used; 701 struct MES_API_STATUS api_status; 702 }; 703 704 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 705 }; 706 707 #pragma pack(pop) 708 #endif 709