1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_event_type { 34 SMU_EVENT_RESET_COMPLETE = 0, 35 }; 36 37 struct amd_vce_state { 38 /* vce clocks */ 39 u32 evclk; 40 u32 ecclk; 41 /* gpu clocks */ 42 u32 sclk; 43 u32 mclk; 44 u8 clk_idx; 45 u8 pstate; 46 }; 47 48 49 enum amd_dpm_forced_level { 50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 52 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 60 }; 61 62 enum amd_pm_state_type { 63 /* not used for dpm */ 64 POWER_STATE_TYPE_DEFAULT, 65 POWER_STATE_TYPE_POWERSAVE, 66 /* user selectable states */ 67 POWER_STATE_TYPE_BATTERY, 68 POWER_STATE_TYPE_BALANCED, 69 POWER_STATE_TYPE_PERFORMANCE, 70 /* internal states */ 71 POWER_STATE_TYPE_INTERNAL_UVD, 72 POWER_STATE_TYPE_INTERNAL_UVD_SD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD, 74 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 75 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 76 POWER_STATE_TYPE_INTERNAL_BOOT, 77 POWER_STATE_TYPE_INTERNAL_THERMAL, 78 POWER_STATE_TYPE_INTERNAL_ACPI, 79 POWER_STATE_TYPE_INTERNAL_ULV, 80 POWER_STATE_TYPE_INTERNAL_3DPERF, 81 }; 82 83 #define AMD_MAX_VCE_LEVELS 6 84 85 enum amd_vce_level { 86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 92 }; 93 94 enum amd_fan_ctrl_mode { 95 AMD_FAN_CTRL_NONE = 0, 96 AMD_FAN_CTRL_MANUAL = 1, 97 AMD_FAN_CTRL_AUTO = 2, 98 }; 99 100 enum pp_clock_type { 101 PP_SCLK, 102 PP_MCLK, 103 PP_PCIE, 104 PP_SOCCLK, 105 PP_FCLK, 106 PP_DCEFCLK, 107 PP_VCLK, 108 PP_VCLK1, 109 PP_DCLK, 110 PP_DCLK1, 111 OD_SCLK, 112 OD_MCLK, 113 OD_VDDC_CURVE, 114 OD_RANGE, 115 OD_VDDGFX_OFFSET, 116 OD_CCLK, 117 OD_FAN_CURVE, 118 OD_ACOUSTIC_LIMIT, 119 OD_ACOUSTIC_TARGET, 120 OD_FAN_TARGET_TEMPERATURE, 121 OD_FAN_MINIMUM_PWM, 122 }; 123 124 enum amd_pp_sensors { 125 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 126 AMDGPU_PP_SENSOR_CPU_CLK, 127 AMDGPU_PP_SENSOR_VDDNB, 128 AMDGPU_PP_SENSOR_VDDGFX, 129 AMDGPU_PP_SENSOR_UVD_VCLK, 130 AMDGPU_PP_SENSOR_UVD_DCLK, 131 AMDGPU_PP_SENSOR_VCE_ECCLK, 132 AMDGPU_PP_SENSOR_GPU_LOAD, 133 AMDGPU_PP_SENSOR_MEM_LOAD, 134 AMDGPU_PP_SENSOR_GFX_MCLK, 135 AMDGPU_PP_SENSOR_GPU_TEMP, 136 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 137 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 138 AMDGPU_PP_SENSOR_MEM_TEMP, 139 AMDGPU_PP_SENSOR_VCE_POWER, 140 AMDGPU_PP_SENSOR_UVD_POWER, 141 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 142 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 143 AMDGPU_PP_SENSOR_SS_APU_SHARE, 144 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 145 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 146 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 147 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 148 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 149 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 150 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 151 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 152 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 153 }; 154 155 enum amd_pp_task { 156 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 157 AMD_PP_TASK_ENABLE_USER_STATE, 158 AMD_PP_TASK_READJUST_POWER_STATE, 159 AMD_PP_TASK_COMPLETE_INIT, 160 AMD_PP_TASK_MAX 161 }; 162 163 enum PP_SMC_POWER_PROFILE { 164 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 165 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 166 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 167 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 168 PP_SMC_POWER_PROFILE_VR = 0x4, 169 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 170 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 171 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 172 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 173 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 174 PP_SMC_POWER_PROFILE_COUNT, 175 }; 176 177 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 178 179 180 181 enum { 182 PP_GROUP_UNKNOWN = 0, 183 PP_GROUP_GFX = 1, 184 PP_GROUP_SYS, 185 PP_GROUP_MAX 186 }; 187 188 enum PP_OD_DPM_TABLE_COMMAND { 189 PP_OD_EDIT_SCLK_VDDC_TABLE, 190 PP_OD_EDIT_MCLK_VDDC_TABLE, 191 PP_OD_EDIT_CCLK_VDDC_TABLE, 192 PP_OD_EDIT_VDDC_CURVE, 193 PP_OD_RESTORE_DEFAULT_TABLE, 194 PP_OD_COMMIT_DPM_TABLE, 195 PP_OD_EDIT_VDDGFX_OFFSET, 196 PP_OD_EDIT_FAN_CURVE, 197 PP_OD_EDIT_ACOUSTIC_LIMIT, 198 PP_OD_EDIT_ACOUSTIC_TARGET, 199 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 200 PP_OD_EDIT_FAN_MINIMUM_PWM, 201 }; 202 203 struct pp_states_info { 204 uint32_t nums; 205 uint32_t states[16]; 206 }; 207 208 enum PP_HWMON_TEMP { 209 PP_TEMP_EDGE = 0, 210 PP_TEMP_JUNCTION, 211 PP_TEMP_MEM, 212 PP_TEMP_MAX 213 }; 214 215 enum pp_mp1_state { 216 PP_MP1_STATE_NONE, 217 PP_MP1_STATE_SHUTDOWN, 218 PP_MP1_STATE_UNLOAD, 219 PP_MP1_STATE_RESET, 220 }; 221 222 enum pp_df_cstate { 223 DF_CSTATE_DISALLOW = 0, 224 DF_CSTATE_ALLOW, 225 }; 226 227 /** 228 * DOC: amdgpu_pp_power 229 * 230 * APU power is managed to system-level requirements through the PPT 231 * (package power tracking) feature. PPT is intended to limit power to the 232 * requirements of the power source and could be dynamically updated to 233 * maximize APU performance within the system power budget. 234 * 235 * Two types of power measurement can be requested, where supported, with 236 * :c:type:`enum pp_power_type <pp_power_type>`. 237 */ 238 239 /** 240 * enum pp_power_limit_level - Used to query the power limits 241 * 242 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 243 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 244 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 245 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 246 */ 247 enum pp_power_limit_level 248 { 249 PP_PWR_LIMIT_MIN = -1, 250 PP_PWR_LIMIT_CURRENT, 251 PP_PWR_LIMIT_DEFAULT, 252 PP_PWR_LIMIT_MAX, 253 }; 254 255 /** 256 * enum pp_power_type - Used to specify the type of the requested power 257 * 258 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 259 * moving average of APU power (default ~5000 ms). 260 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 261 * where supported. 262 */ 263 enum pp_power_type 264 { 265 PP_PWR_TYPE_SUSTAINED, 266 PP_PWR_TYPE_FAST, 267 }; 268 269 enum pp_xgmi_plpd_mode { 270 XGMI_PLPD_NONE = -1, 271 XGMI_PLPD_DISALLOW, 272 XGMI_PLPD_DEFAULT, 273 XGMI_PLPD_OPTIMIZED, 274 XGMI_PLPD_COUNT, 275 }; 276 277 #define PP_GROUP_MASK 0xF0000000 278 #define PP_GROUP_SHIFT 28 279 280 #define PP_BLOCK_MASK 0x0FFFFF00 281 #define PP_BLOCK_SHIFT 8 282 283 #define PP_BLOCK_GFX_CG 0x01 284 #define PP_BLOCK_GFX_MG 0x02 285 #define PP_BLOCK_GFX_3D 0x04 286 #define PP_BLOCK_GFX_RLC 0x08 287 #define PP_BLOCK_GFX_CP 0x10 288 #define PP_BLOCK_SYS_BIF 0x01 289 #define PP_BLOCK_SYS_MC 0x02 290 #define PP_BLOCK_SYS_ROM 0x04 291 #define PP_BLOCK_SYS_DRM 0x08 292 #define PP_BLOCK_SYS_HDP 0x10 293 #define PP_BLOCK_SYS_SDMA 0x20 294 295 #define PP_STATE_MASK 0x0000000F 296 #define PP_STATE_SHIFT 0 297 #define PP_STATE_SUPPORT_MASK 0x000000F0 298 #define PP_STATE_SUPPORT_SHIFT 0 299 300 #define PP_STATE_CG 0x01 301 #define PP_STATE_LS 0x02 302 #define PP_STATE_DS 0x04 303 #define PP_STATE_SD 0x08 304 #define PP_STATE_SUPPORT_CG 0x10 305 #define PP_STATE_SUPPORT_LS 0x20 306 #define PP_STATE_SUPPORT_DS 0x40 307 #define PP_STATE_SUPPORT_SD 0x80 308 309 #define PP_CG_MSG_ID(group, block, support, state) \ 310 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 311 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 312 313 #define XGMI_MODE_PSTATE_D3 0 314 #define XGMI_MODE_PSTATE_D0 1 315 316 #define NUM_HBM_INSTANCES 4 317 #define NUM_XGMI_LINKS 8 318 #define MAX_GFX_CLKS 8 319 #define MAX_CLKS 4 320 #define NUM_VCN 4 321 322 struct seq_file; 323 enum amd_pp_clock_type; 324 struct amd_pp_simple_clock_info; 325 struct amd_pp_display_configuration; 326 struct amd_pp_clock_info; 327 struct pp_display_clock_request; 328 struct pp_clock_levels_with_voltage; 329 struct pp_clock_levels_with_latency; 330 struct amd_pp_clocks; 331 struct pp_smu_wm_range_sets; 332 struct pp_smu_nv_clock_table; 333 struct dpm_clocks; 334 335 struct amd_pm_funcs { 336 /* export for dpm on ci and si */ 337 int (*pre_set_power_state)(void *handle); 338 int (*set_power_state)(void *handle); 339 void (*post_set_power_state)(void *handle); 340 void (*display_configuration_changed)(void *handle); 341 void (*print_power_state)(void *handle, void *ps); 342 bool (*vblank_too_short)(void *handle); 343 void (*enable_bapm)(void *handle, bool enable); 344 int (*check_state_equal)(void *handle, 345 void *cps, 346 void *rps, 347 bool *equal); 348 /* export for sysfs */ 349 int (*set_fan_control_mode)(void *handle, u32 mode); 350 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 351 int (*set_fan_speed_pwm)(void *handle, u32 speed); 352 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 353 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 354 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 355 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 356 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 357 int (*get_sclk_od)(void *handle); 358 int (*set_sclk_od)(void *handle, uint32_t value); 359 int (*get_mclk_od)(void *handle); 360 int (*set_mclk_od)(void *handle, uint32_t value); 361 int (*read_sensor)(void *handle, int idx, void *value, int *size); 362 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 363 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 364 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 365 enum amd_pm_state_type (*get_current_power_state)(void *handle); 366 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 367 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 368 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 369 int (*get_pp_table)(void *handle, char **table); 370 int (*set_pp_table)(void *handle, const char *buf, size_t size); 371 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 372 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 373 /* export to amdgpu */ 374 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 375 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 376 enum amd_pm_state_type *user_state); 377 int (*load_firmware)(void *handle); 378 int (*wait_for_fw_loading_complete)(void *handle); 379 int (*set_powergating_by_smu)(void *handle, 380 uint32_t block_type, bool gate); 381 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 382 int (*set_power_limit)(void *handle, uint32_t n); 383 int (*get_power_limit)(void *handle, uint32_t *limit, 384 enum pp_power_limit_level pp_limit_level, 385 enum pp_power_type power_type); 386 int (*get_power_profile_mode)(void *handle, char *buf); 387 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 388 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 389 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 390 long *input, uint32_t size); 391 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 392 int (*smu_i2c_bus_access)(void *handle, bool acquire); 393 int (*gfx_state_change_set)(void *handle, uint32_t state); 394 /* export to DC */ 395 u32 (*get_sclk)(void *handle, bool low); 396 u32 (*get_mclk)(void *handle, bool low); 397 int (*display_configuration_change)(void *handle, 398 const struct amd_pp_display_configuration *input); 399 int (*get_display_power_level)(void *handle, 400 struct amd_pp_simple_clock_info *output); 401 int (*get_current_clocks)(void *handle, 402 struct amd_pp_clock_info *clocks); 403 int (*get_clock_by_type)(void *handle, 404 enum amd_pp_clock_type type, 405 struct amd_pp_clocks *clocks); 406 int (*get_clock_by_type_with_latency)(void *handle, 407 enum amd_pp_clock_type type, 408 struct pp_clock_levels_with_latency *clocks); 409 int (*get_clock_by_type_with_voltage)(void *handle, 410 enum amd_pp_clock_type type, 411 struct pp_clock_levels_with_voltage *clocks); 412 int (*set_watermarks_for_clocks_ranges)(void *handle, 413 void *clock_ranges); 414 int (*display_clock_voltage_request)(void *handle, 415 struct pp_display_clock_request *clock); 416 int (*get_display_mode_validation_clocks)(void *handle, 417 struct amd_pp_simple_clock_info *clocks); 418 int (*notify_smu_enable_pwe)(void *handle); 419 int (*enable_mgpu_fan_boost)(void *handle); 420 int (*set_active_display_count)(void *handle, uint32_t count); 421 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 422 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 423 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 424 bool (*get_asic_baco_capability)(void *handle); 425 int (*get_asic_baco_state)(void *handle, int *state); 426 int (*set_asic_baco_state)(void *handle, int state); 427 int (*get_ppfeature_status)(void *handle, char *buf); 428 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 429 int (*asic_reset_mode_2)(void *handle); 430 int (*asic_reset_enable_gfx_features)(void *handle); 431 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 432 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 433 ssize_t (*get_gpu_metrics)(void *handle, void **table); 434 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 435 int (*set_watermarks_for_clock_ranges)(void *handle, 436 struct pp_smu_wm_range_sets *ranges); 437 int (*display_disable_memory_clock_switch)(void *handle, 438 bool disable_memory_clock_switch); 439 int (*get_max_sustainable_clocks_by_dc)(void *handle, 440 struct pp_smu_nv_clock_table *max_clocks); 441 int (*get_uclk_dpm_states)(void *handle, 442 unsigned int *clock_values_in_khz, 443 unsigned int *num_states); 444 int (*get_dpm_clock_table)(void *handle, 445 struct dpm_clocks *clock_table); 446 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 447 void (*pm_compute_clocks)(void *handle); 448 int (*notify_rlc_state)(void *handle, bool en); 449 }; 450 451 struct metrics_table_header { 452 uint16_t structure_size; 453 uint8_t format_revision; 454 uint8_t content_revision; 455 }; 456 457 /* 458 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 459 * Use gpu_metrics_v1_1 or later instead. 460 */ 461 struct gpu_metrics_v1_0 { 462 struct metrics_table_header common_header; 463 464 /* Driver attached timestamp (in ns) */ 465 uint64_t system_clock_counter; 466 467 /* Temperature */ 468 uint16_t temperature_edge; 469 uint16_t temperature_hotspot; 470 uint16_t temperature_mem; 471 uint16_t temperature_vrgfx; 472 uint16_t temperature_vrsoc; 473 uint16_t temperature_vrmem; 474 475 /* Utilization */ 476 uint16_t average_gfx_activity; 477 uint16_t average_umc_activity; // memory controller 478 uint16_t average_mm_activity; // UVD or VCN 479 480 /* Power/Energy */ 481 uint16_t average_socket_power; 482 uint32_t energy_accumulator; 483 484 /* Average clocks */ 485 uint16_t average_gfxclk_frequency; 486 uint16_t average_socclk_frequency; 487 uint16_t average_uclk_frequency; 488 uint16_t average_vclk0_frequency; 489 uint16_t average_dclk0_frequency; 490 uint16_t average_vclk1_frequency; 491 uint16_t average_dclk1_frequency; 492 493 /* Current clocks */ 494 uint16_t current_gfxclk; 495 uint16_t current_socclk; 496 uint16_t current_uclk; 497 uint16_t current_vclk0; 498 uint16_t current_dclk0; 499 uint16_t current_vclk1; 500 uint16_t current_dclk1; 501 502 /* Throttle status */ 503 uint32_t throttle_status; 504 505 /* Fans */ 506 uint16_t current_fan_speed; 507 508 /* Link width/speed */ 509 uint8_t pcie_link_width; 510 uint8_t pcie_link_speed; // in 0.1 GT/s 511 }; 512 513 struct gpu_metrics_v1_1 { 514 struct metrics_table_header common_header; 515 516 /* Temperature */ 517 uint16_t temperature_edge; 518 uint16_t temperature_hotspot; 519 uint16_t temperature_mem; 520 uint16_t temperature_vrgfx; 521 uint16_t temperature_vrsoc; 522 uint16_t temperature_vrmem; 523 524 /* Utilization */ 525 uint16_t average_gfx_activity; 526 uint16_t average_umc_activity; // memory controller 527 uint16_t average_mm_activity; // UVD or VCN 528 529 /* Power/Energy */ 530 uint16_t average_socket_power; 531 uint64_t energy_accumulator; 532 533 /* Driver attached timestamp (in ns) */ 534 uint64_t system_clock_counter; 535 536 /* Average clocks */ 537 uint16_t average_gfxclk_frequency; 538 uint16_t average_socclk_frequency; 539 uint16_t average_uclk_frequency; 540 uint16_t average_vclk0_frequency; 541 uint16_t average_dclk0_frequency; 542 uint16_t average_vclk1_frequency; 543 uint16_t average_dclk1_frequency; 544 545 /* Current clocks */ 546 uint16_t current_gfxclk; 547 uint16_t current_socclk; 548 uint16_t current_uclk; 549 uint16_t current_vclk0; 550 uint16_t current_dclk0; 551 uint16_t current_vclk1; 552 uint16_t current_dclk1; 553 554 /* Throttle status */ 555 uint32_t throttle_status; 556 557 /* Fans */ 558 uint16_t current_fan_speed; 559 560 /* Link width/speed */ 561 uint16_t pcie_link_width; 562 uint16_t pcie_link_speed; // in 0.1 GT/s 563 564 uint16_t padding; 565 566 uint32_t gfx_activity_acc; 567 uint32_t mem_activity_acc; 568 569 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 570 }; 571 572 struct gpu_metrics_v1_2 { 573 struct metrics_table_header common_header; 574 575 /* Temperature */ 576 uint16_t temperature_edge; 577 uint16_t temperature_hotspot; 578 uint16_t temperature_mem; 579 uint16_t temperature_vrgfx; 580 uint16_t temperature_vrsoc; 581 uint16_t temperature_vrmem; 582 583 /* Utilization */ 584 uint16_t average_gfx_activity; 585 uint16_t average_umc_activity; // memory controller 586 uint16_t average_mm_activity; // UVD or VCN 587 588 /* Power/Energy */ 589 uint16_t average_socket_power; 590 uint64_t energy_accumulator; 591 592 /* Driver attached timestamp (in ns) */ 593 uint64_t system_clock_counter; 594 595 /* Average clocks */ 596 uint16_t average_gfxclk_frequency; 597 uint16_t average_socclk_frequency; 598 uint16_t average_uclk_frequency; 599 uint16_t average_vclk0_frequency; 600 uint16_t average_dclk0_frequency; 601 uint16_t average_vclk1_frequency; 602 uint16_t average_dclk1_frequency; 603 604 /* Current clocks */ 605 uint16_t current_gfxclk; 606 uint16_t current_socclk; 607 uint16_t current_uclk; 608 uint16_t current_vclk0; 609 uint16_t current_dclk0; 610 uint16_t current_vclk1; 611 uint16_t current_dclk1; 612 613 /* Throttle status (ASIC dependent) */ 614 uint32_t throttle_status; 615 616 /* Fans */ 617 uint16_t current_fan_speed; 618 619 /* Link width/speed */ 620 uint16_t pcie_link_width; 621 uint16_t pcie_link_speed; // in 0.1 GT/s 622 623 uint16_t padding; 624 625 uint32_t gfx_activity_acc; 626 uint32_t mem_activity_acc; 627 628 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 629 630 /* PMFW attached timestamp (10ns resolution) */ 631 uint64_t firmware_timestamp; 632 }; 633 634 struct gpu_metrics_v1_3 { 635 struct metrics_table_header common_header; 636 637 /* Temperature */ 638 uint16_t temperature_edge; 639 uint16_t temperature_hotspot; 640 uint16_t temperature_mem; 641 uint16_t temperature_vrgfx; 642 uint16_t temperature_vrsoc; 643 uint16_t temperature_vrmem; 644 645 /* Utilization */ 646 uint16_t average_gfx_activity; 647 uint16_t average_umc_activity; // memory controller 648 uint16_t average_mm_activity; // UVD or VCN 649 650 /* Power/Energy */ 651 uint16_t average_socket_power; 652 uint64_t energy_accumulator; 653 654 /* Driver attached timestamp (in ns) */ 655 uint64_t system_clock_counter; 656 657 /* Average clocks */ 658 uint16_t average_gfxclk_frequency; 659 uint16_t average_socclk_frequency; 660 uint16_t average_uclk_frequency; 661 uint16_t average_vclk0_frequency; 662 uint16_t average_dclk0_frequency; 663 uint16_t average_vclk1_frequency; 664 uint16_t average_dclk1_frequency; 665 666 /* Current clocks */ 667 uint16_t current_gfxclk; 668 uint16_t current_socclk; 669 uint16_t current_uclk; 670 uint16_t current_vclk0; 671 uint16_t current_dclk0; 672 uint16_t current_vclk1; 673 uint16_t current_dclk1; 674 675 /* Throttle status */ 676 uint32_t throttle_status; 677 678 /* Fans */ 679 uint16_t current_fan_speed; 680 681 /* Link width/speed */ 682 uint16_t pcie_link_width; 683 uint16_t pcie_link_speed; // in 0.1 GT/s 684 685 uint16_t padding; 686 687 uint32_t gfx_activity_acc; 688 uint32_t mem_activity_acc; 689 690 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 691 692 /* PMFW attached timestamp (10ns resolution) */ 693 uint64_t firmware_timestamp; 694 695 /* Voltage (mV) */ 696 uint16_t voltage_soc; 697 uint16_t voltage_gfx; 698 uint16_t voltage_mem; 699 700 uint16_t padding1; 701 702 /* Throttle status (ASIC independent) */ 703 uint64_t indep_throttle_status; 704 }; 705 706 struct gpu_metrics_v1_4 { 707 struct metrics_table_header common_header; 708 709 /* Temperature (Celsius) */ 710 uint16_t temperature_hotspot; 711 uint16_t temperature_mem; 712 uint16_t temperature_vrsoc; 713 714 /* Power (Watts) */ 715 uint16_t curr_socket_power; 716 717 /* Utilization (%) */ 718 uint16_t average_gfx_activity; 719 uint16_t average_umc_activity; // memory controller 720 uint16_t vcn_activity[NUM_VCN]; 721 722 /* Energy (15.259uJ (2^-16) units) */ 723 uint64_t energy_accumulator; 724 725 /* Driver attached timestamp (in ns) */ 726 uint64_t system_clock_counter; 727 728 /* Throttle status */ 729 uint32_t throttle_status; 730 731 /* Clock Lock Status. Each bit corresponds to clock instance */ 732 uint32_t gfxclk_lock_status; 733 734 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 735 uint16_t pcie_link_width; 736 uint16_t pcie_link_speed; 737 738 /* XGMI bus width and bitrate (in Gbps) */ 739 uint16_t xgmi_link_width; 740 uint16_t xgmi_link_speed; 741 742 /* Utilization Accumulated (%) */ 743 uint32_t gfx_activity_acc; 744 uint32_t mem_activity_acc; 745 746 /*PCIE accumulated bandwidth (GB/sec) */ 747 uint64_t pcie_bandwidth_acc; 748 749 /*PCIE instantaneous bandwidth (GB/sec) */ 750 uint64_t pcie_bandwidth_inst; 751 752 /* PCIE L0 to recovery state transition accumulated count */ 753 uint64_t pcie_l0_to_recov_count_acc; 754 755 /* PCIE replay accumulated count */ 756 uint64_t pcie_replay_count_acc; 757 758 /* PCIE replay rollover accumulated count */ 759 uint64_t pcie_replay_rover_count_acc; 760 761 /* XGMI accumulated data transfer size(KiloBytes) */ 762 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 763 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 764 765 /* PMFW attached timestamp (10ns resolution) */ 766 uint64_t firmware_timestamp; 767 768 /* Current clocks (Mhz) */ 769 uint16_t current_gfxclk[MAX_GFX_CLKS]; 770 uint16_t current_socclk[MAX_CLKS]; 771 uint16_t current_vclk0[MAX_CLKS]; 772 uint16_t current_dclk0[MAX_CLKS]; 773 uint16_t current_uclk; 774 775 uint16_t padding; 776 }; 777 778 /* 779 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 780 * Use gpu_metrics_v2_1 or later instead. 781 */ 782 struct gpu_metrics_v2_0 { 783 struct metrics_table_header common_header; 784 785 /* Driver attached timestamp (in ns) */ 786 uint64_t system_clock_counter; 787 788 /* Temperature */ 789 uint16_t temperature_gfx; // gfx temperature on APUs 790 uint16_t temperature_soc; // soc temperature on APUs 791 uint16_t temperature_core[8]; // CPU core temperature on APUs 792 uint16_t temperature_l3[2]; 793 794 /* Utilization */ 795 uint16_t average_gfx_activity; 796 uint16_t average_mm_activity; // UVD or VCN 797 798 /* Power/Energy */ 799 uint16_t average_socket_power; // dGPU + APU power on A + A platform 800 uint16_t average_cpu_power; 801 uint16_t average_soc_power; 802 uint16_t average_gfx_power; 803 uint16_t average_core_power[8]; // CPU core power on APUs 804 805 /* Average clocks */ 806 uint16_t average_gfxclk_frequency; 807 uint16_t average_socclk_frequency; 808 uint16_t average_uclk_frequency; 809 uint16_t average_fclk_frequency; 810 uint16_t average_vclk_frequency; 811 uint16_t average_dclk_frequency; 812 813 /* Current clocks */ 814 uint16_t current_gfxclk; 815 uint16_t current_socclk; 816 uint16_t current_uclk; 817 uint16_t current_fclk; 818 uint16_t current_vclk; 819 uint16_t current_dclk; 820 uint16_t current_coreclk[8]; // CPU core clocks 821 uint16_t current_l3clk[2]; 822 823 /* Throttle status */ 824 uint32_t throttle_status; 825 826 /* Fans */ 827 uint16_t fan_pwm; 828 829 uint16_t padding; 830 }; 831 832 struct gpu_metrics_v2_1 { 833 struct metrics_table_header common_header; 834 835 /* Temperature */ 836 uint16_t temperature_gfx; // gfx temperature on APUs 837 uint16_t temperature_soc; // soc temperature on APUs 838 uint16_t temperature_core[8]; // CPU core temperature on APUs 839 uint16_t temperature_l3[2]; 840 841 /* Utilization */ 842 uint16_t average_gfx_activity; 843 uint16_t average_mm_activity; // UVD or VCN 844 845 /* Driver attached timestamp (in ns) */ 846 uint64_t system_clock_counter; 847 848 /* Power/Energy */ 849 uint16_t average_socket_power; // dGPU + APU power on A + A platform 850 uint16_t average_cpu_power; 851 uint16_t average_soc_power; 852 uint16_t average_gfx_power; 853 uint16_t average_core_power[8]; // CPU core power on APUs 854 855 /* Average clocks */ 856 uint16_t average_gfxclk_frequency; 857 uint16_t average_socclk_frequency; 858 uint16_t average_uclk_frequency; 859 uint16_t average_fclk_frequency; 860 uint16_t average_vclk_frequency; 861 uint16_t average_dclk_frequency; 862 863 /* Current clocks */ 864 uint16_t current_gfxclk; 865 uint16_t current_socclk; 866 uint16_t current_uclk; 867 uint16_t current_fclk; 868 uint16_t current_vclk; 869 uint16_t current_dclk; 870 uint16_t current_coreclk[8]; // CPU core clocks 871 uint16_t current_l3clk[2]; 872 873 /* Throttle status */ 874 uint32_t throttle_status; 875 876 /* Fans */ 877 uint16_t fan_pwm; 878 879 uint16_t padding[3]; 880 }; 881 882 struct gpu_metrics_v2_2 { 883 struct metrics_table_header common_header; 884 885 /* Temperature */ 886 uint16_t temperature_gfx; // gfx temperature on APUs 887 uint16_t temperature_soc; // soc temperature on APUs 888 uint16_t temperature_core[8]; // CPU core temperature on APUs 889 uint16_t temperature_l3[2]; 890 891 /* Utilization */ 892 uint16_t average_gfx_activity; 893 uint16_t average_mm_activity; // UVD or VCN 894 895 /* Driver attached timestamp (in ns) */ 896 uint64_t system_clock_counter; 897 898 /* Power/Energy */ 899 uint16_t average_socket_power; // dGPU + APU power on A + A platform 900 uint16_t average_cpu_power; 901 uint16_t average_soc_power; 902 uint16_t average_gfx_power; 903 uint16_t average_core_power[8]; // CPU core power on APUs 904 905 /* Average clocks */ 906 uint16_t average_gfxclk_frequency; 907 uint16_t average_socclk_frequency; 908 uint16_t average_uclk_frequency; 909 uint16_t average_fclk_frequency; 910 uint16_t average_vclk_frequency; 911 uint16_t average_dclk_frequency; 912 913 /* Current clocks */ 914 uint16_t current_gfxclk; 915 uint16_t current_socclk; 916 uint16_t current_uclk; 917 uint16_t current_fclk; 918 uint16_t current_vclk; 919 uint16_t current_dclk; 920 uint16_t current_coreclk[8]; // CPU core clocks 921 uint16_t current_l3clk[2]; 922 923 /* Throttle status (ASIC dependent) */ 924 uint32_t throttle_status; 925 926 /* Fans */ 927 uint16_t fan_pwm; 928 929 uint16_t padding[3]; 930 931 /* Throttle status (ASIC independent) */ 932 uint64_t indep_throttle_status; 933 }; 934 935 struct gpu_metrics_v2_3 { 936 struct metrics_table_header common_header; 937 938 /* Temperature */ 939 uint16_t temperature_gfx; // gfx temperature on APUs 940 uint16_t temperature_soc; // soc temperature on APUs 941 uint16_t temperature_core[8]; // CPU core temperature on APUs 942 uint16_t temperature_l3[2]; 943 944 /* Utilization */ 945 uint16_t average_gfx_activity; 946 uint16_t average_mm_activity; // UVD or VCN 947 948 /* Driver attached timestamp (in ns) */ 949 uint64_t system_clock_counter; 950 951 /* Power/Energy */ 952 uint16_t average_socket_power; // dGPU + APU power on A + A platform 953 uint16_t average_cpu_power; 954 uint16_t average_soc_power; 955 uint16_t average_gfx_power; 956 uint16_t average_core_power[8]; // CPU core power on APUs 957 958 /* Average clocks */ 959 uint16_t average_gfxclk_frequency; 960 uint16_t average_socclk_frequency; 961 uint16_t average_uclk_frequency; 962 uint16_t average_fclk_frequency; 963 uint16_t average_vclk_frequency; 964 uint16_t average_dclk_frequency; 965 966 /* Current clocks */ 967 uint16_t current_gfxclk; 968 uint16_t current_socclk; 969 uint16_t current_uclk; 970 uint16_t current_fclk; 971 uint16_t current_vclk; 972 uint16_t current_dclk; 973 uint16_t current_coreclk[8]; // CPU core clocks 974 uint16_t current_l3clk[2]; 975 976 /* Throttle status (ASIC dependent) */ 977 uint32_t throttle_status; 978 979 /* Fans */ 980 uint16_t fan_pwm; 981 982 uint16_t padding[3]; 983 984 /* Throttle status (ASIC independent) */ 985 uint64_t indep_throttle_status; 986 987 /* Average Temperature */ 988 uint16_t average_temperature_gfx; // average gfx temperature on APUs 989 uint16_t average_temperature_soc; // average soc temperature on APUs 990 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 991 uint16_t average_temperature_l3[2]; 992 }; 993 994 struct gpu_metrics_v2_4 { 995 struct metrics_table_header common_header; 996 997 /* Temperature (unit: centi-Celsius) */ 998 uint16_t temperature_gfx; 999 uint16_t temperature_soc; 1000 uint16_t temperature_core[8]; 1001 uint16_t temperature_l3[2]; 1002 1003 /* Utilization (unit: centi) */ 1004 uint16_t average_gfx_activity; 1005 uint16_t average_mm_activity; 1006 1007 /* Driver attached timestamp (in ns) */ 1008 uint64_t system_clock_counter; 1009 1010 /* Power/Energy (unit: mW) */ 1011 uint16_t average_socket_power; 1012 uint16_t average_cpu_power; 1013 uint16_t average_soc_power; 1014 uint16_t average_gfx_power; 1015 uint16_t average_core_power[8]; 1016 1017 /* Average clocks (unit: MHz) */ 1018 uint16_t average_gfxclk_frequency; 1019 uint16_t average_socclk_frequency; 1020 uint16_t average_uclk_frequency; 1021 uint16_t average_fclk_frequency; 1022 uint16_t average_vclk_frequency; 1023 uint16_t average_dclk_frequency; 1024 1025 /* Current clocks (unit: MHz) */ 1026 uint16_t current_gfxclk; 1027 uint16_t current_socclk; 1028 uint16_t current_uclk; 1029 uint16_t current_fclk; 1030 uint16_t current_vclk; 1031 uint16_t current_dclk; 1032 uint16_t current_coreclk[8]; 1033 uint16_t current_l3clk[2]; 1034 1035 /* Throttle status (ASIC dependent) */ 1036 uint32_t throttle_status; 1037 1038 /* Fans */ 1039 uint16_t fan_pwm; 1040 1041 uint16_t padding[3]; 1042 1043 /* Throttle status (ASIC independent) */ 1044 uint64_t indep_throttle_status; 1045 1046 /* Average Temperature (unit: centi-Celsius) */ 1047 uint16_t average_temperature_gfx; 1048 uint16_t average_temperature_soc; 1049 uint16_t average_temperature_core[8]; 1050 uint16_t average_temperature_l3[2]; 1051 1052 /* Power/Voltage (unit: mV) */ 1053 uint16_t average_cpu_voltage; 1054 uint16_t average_soc_voltage; 1055 uint16_t average_gfx_voltage; 1056 1057 /* Power/Current (unit: mA) */ 1058 uint16_t average_cpu_current; 1059 uint16_t average_soc_current; 1060 uint16_t average_gfx_current; 1061 }; 1062 1063 struct gpu_metrics_v3_0 { 1064 struct metrics_table_header common_header; 1065 1066 /* Temperature */ 1067 /* gfx temperature on APUs */ 1068 uint16_t temperature_gfx; 1069 /* soc temperature on APUs */ 1070 uint16_t temperature_soc; 1071 /* CPU core temperature on APUs */ 1072 uint16_t temperature_core[16]; 1073 /* skin temperature on APUs */ 1074 uint16_t temperature_skin; 1075 1076 /* Utilization */ 1077 /* time filtered GFX busy % [0-100] */ 1078 uint16_t average_gfx_activity; 1079 /* time filtered VCN busy % [0-100] */ 1080 uint16_t average_vcn_activity; 1081 /* time filtered IPU per-column busy % [0-100] */ 1082 uint16_t average_ipu_activity[8]; 1083 /* time filtered per-core C0 residency % [0-100]*/ 1084 uint16_t average_core_c0_activity[16]; 1085 /* time filtered DRAM read bandwidth [MB/sec] */ 1086 uint16_t average_dram_reads; 1087 /* time filtered DRAM write bandwidth [MB/sec] */ 1088 uint16_t average_dram_writes; 1089 1090 /* Driver attached timestamp (in ns) */ 1091 uint64_t system_clock_counter; 1092 1093 /* Power/Energy */ 1094 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1095 uint32_t average_socket_power; 1096 /* time filtered IPU power [mW] */ 1097 uint16_t average_ipu_power; 1098 /* time filtered APU power [mW] */ 1099 uint32_t average_apu_power; 1100 /* time filtered GFX power [mW] */ 1101 uint32_t average_gfx_power; 1102 /* time filtered dGPU power [mW] */ 1103 uint32_t average_dgpu_power; 1104 /* time filtered sum of core power across all cores in the socket [mW] */ 1105 uint32_t average_all_core_power; 1106 /* calculated core power [mW] */ 1107 uint16_t average_core_power[16]; 1108 /* maximum IRM defined STAPM power limit [mW] */ 1109 uint16_t stapm_power_limit; 1110 /* time filtered STAPM power limit [mW] */ 1111 uint16_t current_stapm_power_limit; 1112 1113 /* time filtered clocks [MHz] */ 1114 uint16_t average_gfxclk_frequency; 1115 uint16_t average_socclk_frequency; 1116 uint16_t average_vpeclk_frequency; 1117 uint16_t average_ipuclk_frequency; 1118 uint16_t average_fclk_frequency; 1119 uint16_t average_vclk_frequency; 1120 1121 /* Current clocks */ 1122 /* target core frequency [MHz] */ 1123 uint16_t current_coreclk[16]; 1124 /* CCLK frequency limit enforced on classic cores [MHz] */ 1125 uint16_t current_core_maxfreq; 1126 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1127 uint16_t current_gfx_maxfreq; 1128 1129 /* Metrics table alpha filter time constant [us] */ 1130 uint32_t time_filter_alphavalue; 1131 }; 1132 1133 struct amdgpu_pmmetrics_header { 1134 uint16_t structure_size; 1135 uint16_t pad; 1136 uint32_t mp1_ip_discovery_version; 1137 uint32_t pmfw_version; 1138 uint32_t pmmetrics_version; 1139 }; 1140 1141 struct amdgpu_pm_metrics { 1142 struct amdgpu_pmmetrics_header common_header; 1143 1144 uint8_t data[]; 1145 }; 1146 1147 #endif 1148