1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 extern const struct amdgpu_ip_block_version smu_v15_0_ip_block; 33 34 enum smu_temp_metric_type { 35 SMU_TEMP_METRIC_BASEBOARD, 36 SMU_TEMP_METRIC_GPUBOARD, 37 SMU_TEMP_METRIC_MAX, 38 }; 39 40 enum smu_event_type { 41 SMU_EVENT_RESET_COMPLETE = 0, 42 }; 43 44 struct amd_vce_state { 45 /* vce clocks */ 46 u32 evclk; 47 u32 ecclk; 48 /* gpu clocks */ 49 u32 sclk; 50 u32 mclk; 51 u8 clk_idx; 52 u8 pstate; 53 }; 54 55 56 enum amd_dpm_forced_level { 57 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 58 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 59 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 60 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 61 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 62 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 63 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 64 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 65 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 66 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 67 }; 68 69 enum amd_pm_state_type { 70 /* not used for dpm */ 71 POWER_STATE_TYPE_DEFAULT, 72 POWER_STATE_TYPE_POWERSAVE, 73 /* user selectable states */ 74 POWER_STATE_TYPE_BATTERY, 75 POWER_STATE_TYPE_BALANCED, 76 POWER_STATE_TYPE_PERFORMANCE, 77 /* internal states */ 78 POWER_STATE_TYPE_INTERNAL_UVD, 79 POWER_STATE_TYPE_INTERNAL_UVD_SD, 80 POWER_STATE_TYPE_INTERNAL_UVD_HD, 81 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 82 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 83 POWER_STATE_TYPE_INTERNAL_BOOT, 84 POWER_STATE_TYPE_INTERNAL_THERMAL, 85 POWER_STATE_TYPE_INTERNAL_ACPI, 86 POWER_STATE_TYPE_INTERNAL_ULV, 87 POWER_STATE_TYPE_INTERNAL_3DPERF, 88 }; 89 90 #define AMD_MAX_VCE_LEVELS 6 91 92 enum amd_vce_level { 93 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 94 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 95 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 96 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 97 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 98 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 99 }; 100 101 enum amd_fan_ctrl_mode { 102 AMD_FAN_CTRL_NONE = 0, 103 AMD_FAN_CTRL_MANUAL = 1, 104 AMD_FAN_CTRL_AUTO = 2, 105 }; 106 107 enum pp_clock_type { 108 PP_SCLK, 109 PP_MCLK, 110 PP_PCIE, 111 PP_SOCCLK, 112 PP_FCLK, 113 PP_DCEFCLK, 114 PP_VCLK, 115 PP_VCLK1, 116 PP_DCLK, 117 PP_DCLK1, 118 PP_ISPICLK, 119 PP_ISPXCLK, 120 OD_SCLK, 121 OD_MCLK, 122 OD_FCLK, 123 OD_VDDC_CURVE, 124 OD_RANGE, 125 OD_VDDGFX_OFFSET, 126 OD_CCLK, 127 OD_FAN_CURVE, 128 OD_ACOUSTIC_LIMIT, 129 OD_ACOUSTIC_TARGET, 130 OD_FAN_TARGET_TEMPERATURE, 131 OD_FAN_MINIMUM_PWM, 132 OD_FAN_ZERO_RPM_ENABLE, 133 OD_FAN_ZERO_RPM_STOP_TEMP, 134 }; 135 136 enum amd_pp_sensors { 137 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 138 AMDGPU_PP_SENSOR_CPU_CLK, 139 AMDGPU_PP_SENSOR_VDDNB, 140 AMDGPU_PP_SENSOR_VDDGFX, 141 AMDGPU_PP_SENSOR_UVD_VCLK, 142 AMDGPU_PP_SENSOR_UVD_DCLK, 143 AMDGPU_PP_SENSOR_VCE_ECCLK, 144 AMDGPU_PP_SENSOR_GPU_LOAD, 145 AMDGPU_PP_SENSOR_MEM_LOAD, 146 AMDGPU_PP_SENSOR_GFX_MCLK, 147 AMDGPU_PP_SENSOR_GPU_TEMP, 148 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 149 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 150 AMDGPU_PP_SENSOR_MEM_TEMP, 151 AMDGPU_PP_SENSOR_VCE_POWER, 152 AMDGPU_PP_SENSOR_UVD_POWER, 153 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 154 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 155 AMDGPU_PP_SENSOR_SS_APU_SHARE, 156 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 157 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 158 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 159 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 160 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 161 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 162 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 163 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 164 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 165 AMDGPU_PP_SENSOR_VCN_LOAD, 166 AMDGPU_PP_SENSOR_VDDBOARD, 167 AMDGPU_PP_SENSOR_NODEPOWERLIMIT, 168 AMDGPU_PP_SENSOR_NODEPOWER, 169 AMDGPU_PP_SENSOR_GPPTRESIDENCY, 170 AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, 171 AMDGPU_PP_SENSOR_UBB_POWER, 172 AMDGPU_PP_SENSOR_UBB_POWER_LIMIT, 173 }; 174 175 enum amd_pp_task { 176 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 177 AMD_PP_TASK_ENABLE_USER_STATE, 178 AMD_PP_TASK_READJUST_POWER_STATE, 179 AMD_PP_TASK_COMPLETE_INIT, 180 AMD_PP_TASK_MAX 181 }; 182 183 enum PP_SMC_POWER_PROFILE { 184 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 185 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 186 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 187 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 188 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 189 PP_SMC_POWER_PROFILE_VR = 0x4, 190 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 191 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 192 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 193 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 194 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 195 PP_SMC_POWER_PROFILE_COUNT, 196 }; 197 198 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 199 200 201 202 enum { 203 PP_GROUP_UNKNOWN = 0, 204 PP_GROUP_GFX = 1, 205 PP_GROUP_SYS, 206 PP_GROUP_MAX 207 }; 208 209 enum PP_OD_DPM_TABLE_COMMAND { 210 PP_OD_EDIT_SCLK_VDDC_TABLE, 211 PP_OD_EDIT_MCLK_VDDC_TABLE, 212 PP_OD_EDIT_FCLK_TABLE, 213 PP_OD_EDIT_CCLK_VDDC_TABLE, 214 PP_OD_EDIT_VDDC_CURVE, 215 PP_OD_RESTORE_DEFAULT_TABLE, 216 PP_OD_COMMIT_DPM_TABLE, 217 PP_OD_EDIT_VDDGFX_OFFSET, 218 PP_OD_EDIT_FAN_CURVE, 219 PP_OD_EDIT_ACOUSTIC_LIMIT, 220 PP_OD_EDIT_ACOUSTIC_TARGET, 221 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 222 PP_OD_EDIT_FAN_MINIMUM_PWM, 223 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 224 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 225 }; 226 227 struct pp_states_info { 228 uint32_t nums; 229 uint32_t states[16]; 230 }; 231 232 enum PP_HWMON_TEMP { 233 PP_TEMP_EDGE = 0, 234 PP_TEMP_JUNCTION, 235 PP_TEMP_MEM, 236 PP_TEMP_MAX 237 }; 238 239 enum pp_mp1_state { 240 PP_MP1_STATE_NONE, 241 PP_MP1_STATE_SHUTDOWN, 242 PP_MP1_STATE_UNLOAD, 243 PP_MP1_STATE_RESET, 244 PP_MP1_STATE_FLR, 245 }; 246 247 enum pp_df_cstate { 248 DF_CSTATE_DISALLOW = 0, 249 DF_CSTATE_ALLOW, 250 }; 251 252 /** 253 * DOC: amdgpu_pp_power 254 * 255 * APU power is managed to system-level requirements through the PPT 256 * (package power tracking) feature. PPT is intended to limit power to the 257 * requirements of the power source and could be dynamically updated to 258 * maximize APU performance within the system power budget. 259 * 260 * Two types of power measurement can be requested, where supported, with 261 * :c:type:`enum pp_power_type <pp_power_type>`. 262 */ 263 264 /** 265 * enum pp_power_limit_level - Used to query the power limits 266 * 267 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 268 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 269 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 270 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 271 */ 272 enum pp_power_limit_level { 273 PP_PWR_LIMIT_MIN = -1, 274 PP_PWR_LIMIT_CURRENT, 275 PP_PWR_LIMIT_DEFAULT, 276 PP_PWR_LIMIT_MAX, 277 }; 278 279 /** 280 * enum pp_power_type - Used to specify the type of the requested power 281 * 282 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 283 * moving average of APU power (default ~5000 ms). 284 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 285 * where supported. 286 */ 287 enum pp_power_type { 288 PP_PWR_TYPE_SUSTAINED, 289 PP_PWR_TYPE_FAST, 290 }; 291 292 enum pp_xgmi_plpd_mode { 293 XGMI_PLPD_NONE = -1, 294 XGMI_PLPD_DISALLOW, 295 XGMI_PLPD_DEFAULT, 296 XGMI_PLPD_OPTIMIZED, 297 XGMI_PLPD_COUNT, 298 }; 299 300 enum pp_pm_policy { 301 PP_PM_POLICY_NONE = -1, 302 PP_PM_POLICY_SOC_PSTATE = 0, 303 PP_PM_POLICY_XGMI_PLPD, 304 PP_PM_POLICY_NUM, 305 }; 306 307 enum pp_policy_soc_pstate { 308 SOC_PSTATE_DEFAULT = 0, 309 SOC_PSTATE_0, 310 SOC_PSTATE_1, 311 SOC_PSTATE_2, 312 SOC_PSTAT_COUNT, 313 }; 314 315 #define PP_POLICY_MAX_LEVELS 5 316 317 #define PP_GROUP_MASK 0xF0000000 318 #define PP_GROUP_SHIFT 28 319 320 #define PP_BLOCK_MASK 0x0FFFFF00 321 #define PP_BLOCK_SHIFT 8 322 323 #define PP_BLOCK_GFX_CG 0x01 324 #define PP_BLOCK_GFX_MG 0x02 325 #define PP_BLOCK_GFX_3D 0x04 326 #define PP_BLOCK_GFX_RLC 0x08 327 #define PP_BLOCK_GFX_CP 0x10 328 #define PP_BLOCK_SYS_BIF 0x01 329 #define PP_BLOCK_SYS_MC 0x02 330 #define PP_BLOCK_SYS_ROM 0x04 331 #define PP_BLOCK_SYS_DRM 0x08 332 #define PP_BLOCK_SYS_HDP 0x10 333 #define PP_BLOCK_SYS_SDMA 0x20 334 335 #define PP_STATE_MASK 0x0000000F 336 #define PP_STATE_SHIFT 0 337 #define PP_STATE_SUPPORT_MASK 0x000000F0 338 #define PP_STATE_SUPPORT_SHIFT 0 339 340 #define PP_STATE_CG 0x01 341 #define PP_STATE_LS 0x02 342 #define PP_STATE_DS 0x04 343 #define PP_STATE_SD 0x08 344 #define PP_STATE_SUPPORT_CG 0x10 345 #define PP_STATE_SUPPORT_LS 0x20 346 #define PP_STATE_SUPPORT_DS 0x40 347 #define PP_STATE_SUPPORT_SD 0x80 348 349 #define PP_CG_MSG_ID(group, block, support, state) \ 350 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 351 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 352 353 #define XGMI_MODE_PSTATE_D3 0 354 #define XGMI_MODE_PSTATE_D0 1 355 356 #define NUM_HBM_INSTANCES 4 357 #define NUM_XGMI_LINKS 8 358 #define MAX_GFX_CLKS 8 359 #define MAX_CLKS 4 360 #define NUM_VCN 4 361 #define NUM_JPEG_ENG 32 362 #define NUM_JPEG_ENG_V1 40 363 #define MAX_XCC 8 364 #define NUM_XCP 8 365 struct seq_file; 366 enum amd_pp_clock_type; 367 struct amd_pp_simple_clock_info; 368 struct amd_pp_display_configuration; 369 struct amd_pp_clock_info; 370 struct pp_display_clock_request; 371 struct pp_clock_levels_with_voltage; 372 struct pp_clock_levels_with_latency; 373 struct amd_pp_clocks; 374 struct pp_smu_wm_range_sets; 375 struct pp_smu_nv_clock_table; 376 struct dpm_clocks; 377 378 struct amdgpu_xcp_metrics { 379 /* Utilization Instantaneous (%) */ 380 uint32_t gfx_busy_inst[MAX_XCC]; 381 uint16_t jpeg_busy[NUM_JPEG_ENG]; 382 uint16_t vcn_busy[NUM_VCN]; 383 /* Utilization Accumulated (%) */ 384 uint64_t gfx_busy_acc[MAX_XCC]; 385 }; 386 387 struct amdgpu_xcp_metrics_v1_1 { 388 /* Utilization Instantaneous (%) */ 389 uint32_t gfx_busy_inst[MAX_XCC]; 390 uint16_t jpeg_busy[NUM_JPEG_ENG]; 391 uint16_t vcn_busy[NUM_VCN]; 392 /* Utilization Accumulated (%) */ 393 uint64_t gfx_busy_acc[MAX_XCC]; 394 /* Total App Clock Counter Accumulated */ 395 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 396 }; 397 398 struct amdgpu_xcp_metrics_v1_2 { 399 /* Utilization Instantaneous (%) */ 400 uint32_t gfx_busy_inst[MAX_XCC]; 401 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 402 uint16_t vcn_busy[NUM_VCN]; 403 /* Utilization Accumulated (%) */ 404 uint64_t gfx_busy_acc[MAX_XCC]; 405 /* Total App Clock Counter Accumulated */ 406 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 407 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 408 uint64_t gfx_low_utilization_acc[MAX_XCC]; 409 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 410 }; 411 412 struct amd_pm_funcs { 413 /* export for dpm on ci and si */ 414 int (*pre_set_power_state)(void *handle); 415 int (*set_power_state)(void *handle); 416 void (*post_set_power_state)(void *handle); 417 void (*display_configuration_changed)(void *handle); 418 void (*print_power_state)(void *handle, void *ps); 419 bool (*vblank_too_short)(void *handle); 420 void (*notify_ac_dc)(void *handle); 421 int (*check_state_equal)(void *handle, 422 void *cps, 423 void *rps, 424 bool *equal); 425 /* export for sysfs */ 426 int (*set_fan_control_mode)(void *handle, u32 mode); 427 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 428 int (*set_fan_speed_pwm)(void *handle, u32 speed); 429 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 430 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 431 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 432 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 433 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 434 int (*get_sclk_od)(void *handle); 435 int (*set_sclk_od)(void *handle, uint32_t value); 436 int (*get_mclk_od)(void *handle); 437 int (*set_mclk_od)(void *handle, uint32_t value); 438 int (*read_sensor)(void *handle, int idx, void *value, int *size); 439 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 440 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 441 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 442 enum amd_pm_state_type (*get_current_power_state)(void *handle); 443 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 444 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 445 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 446 int (*get_pp_table)(void *handle, char **table); 447 int (*set_pp_table)(void *handle, const char *buf, size_t size); 448 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 449 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 450 int (*pause_power_profile)(void *handle, bool pause); 451 /* export to amdgpu */ 452 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 453 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 454 enum amd_pm_state_type *user_state); 455 int (*load_firmware)(void *handle); 456 int (*wait_for_fw_loading_complete)(void *handle); 457 int (*set_powergating_by_smu)(void *handle, 458 uint32_t block_type, 459 bool gate, 460 int inst); 461 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 462 int (*set_power_limit)(void *handle, uint32_t limit_type, uint32_t n); 463 int (*get_power_limit)(void *handle, uint32_t *limit, 464 enum pp_power_limit_level pp_limit_level, 465 enum pp_power_type power_type); 466 int (*get_power_profile_mode)(void *handle, char *buf); 467 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 468 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 469 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 470 long *input, uint32_t size); 471 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 472 int (*smu_i2c_bus_access)(void *handle, bool acquire); 473 int (*gfx_state_change_set)(void *handle, uint32_t state); 474 /* export to DC */ 475 u32 (*get_sclk)(void *handle, bool low); 476 u32 (*get_mclk)(void *handle, bool low); 477 int (*display_configuration_change)(void *handle, 478 const struct amd_pp_display_configuration *input); 479 int (*get_current_clocks)(void *handle, 480 struct amd_pp_clock_info *clocks); 481 int (*get_clock_by_type)(void *handle, 482 enum amd_pp_clock_type type, 483 struct amd_pp_clocks *clocks); 484 int (*get_clock_by_type_with_latency)(void *handle, 485 enum amd_pp_clock_type type, 486 struct pp_clock_levels_with_latency *clocks); 487 int (*get_clock_by_type_with_voltage)(void *handle, 488 enum amd_pp_clock_type type, 489 struct pp_clock_levels_with_voltage *clocks); 490 int (*set_watermarks_for_clocks_ranges)(void *handle, 491 void *clock_ranges); 492 int (*display_clock_voltage_request)(void *handle, 493 struct pp_display_clock_request *clock); 494 int (*get_display_mode_validation_clocks)(void *handle, 495 struct amd_pp_simple_clock_info *clocks); 496 int (*notify_smu_enable_pwe)(void *handle); 497 int (*enable_mgpu_fan_boost)(void *handle); 498 int (*set_active_display_count)(void *handle, uint32_t count); 499 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 500 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 501 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 502 int (*get_asic_baco_capability)(void *handle); 503 int (*get_asic_baco_state)(void *handle, int *state); 504 int (*set_asic_baco_state)(void *handle, int state); 505 int (*get_ppfeature_status)(void *handle, char *buf); 506 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 507 int (*asic_reset_mode_2)(void *handle); 508 int (*asic_reset_enable_gfx_features)(void *handle); 509 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 510 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 511 ssize_t (*get_gpu_metrics)(void *handle, void **table); 512 ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table); 513 bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type); 514 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table); 515 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 516 int (*set_watermarks_for_clock_ranges)(void *handle, 517 struct pp_smu_wm_range_sets *ranges); 518 int (*display_disable_memory_clock_switch)(void *handle, 519 bool disable_memory_clock_switch); 520 int (*get_max_sustainable_clocks_by_dc)(void *handle, 521 struct pp_smu_nv_clock_table *max_clocks); 522 int (*get_uclk_dpm_states)(void *handle, 523 unsigned int *clock_values_in_khz, 524 unsigned int *num_states); 525 int (*get_dpm_clock_table)(void *handle, 526 struct dpm_clocks *clock_table); 527 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 528 void (*pm_compute_clocks)(void *handle); 529 int (*notify_rlc_state)(void *handle, bool en); 530 }; 531 532 struct metrics_table_header { 533 uint16_t structure_size; 534 uint8_t format_revision; 535 uint8_t content_revision; 536 }; 537 538 enum amdgpu_metrics_attr_id { 539 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HOTSPOT, 540 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MEM, 541 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_VRSOC, 542 AMDGPU_METRICS_ATTR_ID_CURR_SOCKET_POWER, 543 AMDGPU_METRICS_ATTR_ID_AVERAGE_GFX_ACTIVITY, 544 AMDGPU_METRICS_ATTR_ID_AVERAGE_UMC_ACTIVITY, 545 AMDGPU_METRICS_ATTR_ID_MEM_MAX_BANDWIDTH, 546 AMDGPU_METRICS_ATTR_ID_ENERGY_ACCUMULATOR, 547 AMDGPU_METRICS_ATTR_ID_SYSTEM_CLOCK_COUNTER, 548 AMDGPU_METRICS_ATTR_ID_ACCUMULATION_COUNTER, 549 AMDGPU_METRICS_ATTR_ID_PROCHOT_RESIDENCY_ACC, 550 AMDGPU_METRICS_ATTR_ID_PPT_RESIDENCY_ACC, 551 AMDGPU_METRICS_ATTR_ID_SOCKET_THM_RESIDENCY_ACC, 552 AMDGPU_METRICS_ATTR_ID_VR_THM_RESIDENCY_ACC, 553 AMDGPU_METRICS_ATTR_ID_HBM_THM_RESIDENCY_ACC, 554 AMDGPU_METRICS_ATTR_ID_GFXCLK_LOCK_STATUS, 555 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_WIDTH, 556 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_SPEED, 557 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_WIDTH, 558 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_SPEED, 559 AMDGPU_METRICS_ATTR_ID_GFX_ACTIVITY_ACC, 560 AMDGPU_METRICS_ATTR_ID_MEM_ACTIVITY_ACC, 561 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_ACC, 562 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_INST, 563 AMDGPU_METRICS_ATTR_ID_PCIE_L0_TO_RECOV_COUNT_ACC, 564 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_COUNT_ACC, 565 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_ROVER_COUNT_ACC, 566 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_SENT_COUNT_ACC, 567 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_RCVD_COUNT_ACC, 568 AMDGPU_METRICS_ATTR_ID_XGMI_READ_DATA_ACC, 569 AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_DATA_ACC, 570 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_STATUS, 571 AMDGPU_METRICS_ATTR_ID_FIRMWARE_TIMESTAMP, 572 AMDGPU_METRICS_ATTR_ID_CURRENT_GFXCLK, 573 AMDGPU_METRICS_ATTR_ID_CURRENT_SOCCLK, 574 AMDGPU_METRICS_ATTR_ID_CURRENT_VCLK0, 575 AMDGPU_METRICS_ATTR_ID_CURRENT_DCLK0, 576 AMDGPU_METRICS_ATTR_ID_CURRENT_UCLK, 577 AMDGPU_METRICS_ATTR_ID_NUM_PARTITION, 578 AMDGPU_METRICS_ATTR_ID_PCIE_LC_PERF_OTHER_END_RECOVERY, 579 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_INST, 580 AMDGPU_METRICS_ATTR_ID_JPEG_BUSY, 581 AMDGPU_METRICS_ATTR_ID_VCN_BUSY, 582 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_ACC, 583 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_PPT_ACC, 584 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC, 585 AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, 586 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, 587 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HBM, 588 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MID, 589 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_AID, 590 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_XCD, 591 AMDGPU_METRICS_ATTR_ID_LABEL_VERSION, 592 AMDGPU_METRICS_ATTR_ID_NODE_ID, 593 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_RETIMER, 594 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC, 595 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC_2, 596 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_VDD18_VR, 597 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_B_VR, 598 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_D_VR, 599 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_A, 600 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_C, 601 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X0, 602 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X1, 603 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_B, 604 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_D, 605 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_B, 606 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_D, 607 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_B, 608 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_D, 609 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_B, 610 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_D, 611 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_A, 612 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_C, 613 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_A, 614 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_C, 615 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_UCIE, 616 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAA, 617 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_A, 618 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_C, 619 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075, 620 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA, 621 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FRONT, 622 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_BACK, 623 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM7, 624 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_IBC, 625 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_UFPGA, 626 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM1, 627 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_HSC, 628 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_2_3_HSC, 629 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_HSC, 630 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_6_7_HSC, 631 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_0V72_VR, 632 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_3V3_VR, 633 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR, 634 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR, 635 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_0V9_VR, 636 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_0V9_VR, 637 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_2_3_0V9_VR, 638 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_6_7_0V9_VR, 639 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR, 640 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR, 641 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC_HSC, 642 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC, 643 AMDGPU_METRICS_ATTR_ID_MAX, 644 }; 645 646 enum amdgpu_metrics_attr_type { 647 AMDGPU_METRICS_TYPE_U8, 648 AMDGPU_METRICS_TYPE_S8, 649 AMDGPU_METRICS_TYPE_U16, 650 AMDGPU_METRICS_TYPE_S16, 651 AMDGPU_METRICS_TYPE_U32, 652 AMDGPU_METRICS_TYPE_S32, 653 AMDGPU_METRICS_TYPE_U64, 654 AMDGPU_METRICS_TYPE_S64, 655 AMDGPU_METRICS_TYPE_MAX, 656 }; 657 658 enum amdgpu_metrics_attr_unit { 659 /* None */ 660 AMDGPU_METRICS_UNIT_NONE, 661 /* MHz*/ 662 AMDGPU_METRICS_UNIT_CLOCK_1, 663 /* Degree Celsius*/ 664 AMDGPU_METRICS_UNIT_TEMP_1, 665 /* Watts*/ 666 AMDGPU_METRICS_UNIT_POWER_1, 667 /* In nanoseconds*/ 668 AMDGPU_METRICS_UNIT_TIME_1, 669 /* In 10 nanoseconds*/ 670 AMDGPU_METRICS_UNIT_TIME_2, 671 /* Speed in GT/s */ 672 AMDGPU_METRICS_UNIT_SPEED_1, 673 /* Speed in 0.1 GT/s */ 674 AMDGPU_METRICS_UNIT_SPEED_2, 675 /* Bandwidth GB/s */ 676 AMDGPU_METRICS_UNIT_BW_1, 677 /* Data in KB */ 678 AMDGPU_METRICS_UNIT_DATA_1, 679 /* Percentage */ 680 AMDGPU_METRICS_UNIT_PERCENT, 681 AMDGPU_METRICS_UNIT_MAX, 682 }; 683 684 #define AMDGPU_METRICS_ATTR_UNIT_MASK 0xFF000000 685 #define AMDGPU_METRICS_ATTR_UNIT_SHIFT 24 686 #define AMDGPU_METRICS_ATTR_TYPE_MASK 0x00F00000 687 #define AMDGPU_METRICS_ATTR_TYPE_SHIFT 20 688 #define AMDGPU_METRICS_ATTR_ID_MASK 0x000FFC00 689 #define AMDGPU_METRICS_ATTR_ID_SHIFT 10 690 #define AMDGPU_METRICS_ATTR_INST_MASK 0x000003FF 691 #define AMDGPU_METRICS_ATTR_INST_SHIFT 0 692 693 #define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \ 694 (((u64)(unit) << AMDGPU_METRICS_ATTR_UNIT_SHIFT) | \ 695 ((u64)(type) << AMDGPU_METRICS_ATTR_TYPE_SHIFT) | \ 696 ((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst)) 697 698 /* 699 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 700 * Use gpu_metrics_v1_1 or later instead. 701 */ 702 struct gpu_metrics_v1_0 { 703 struct metrics_table_header common_header; 704 705 /* Driver attached timestamp (in ns) */ 706 uint64_t system_clock_counter; 707 708 /* Temperature */ 709 uint16_t temperature_edge; 710 uint16_t temperature_hotspot; 711 uint16_t temperature_mem; 712 uint16_t temperature_vrgfx; 713 uint16_t temperature_vrsoc; 714 uint16_t temperature_vrmem; 715 716 /* Utilization */ 717 uint16_t average_gfx_activity; 718 uint16_t average_umc_activity; // memory controller 719 uint16_t average_mm_activity; // UVD or VCN 720 721 /* Power/Energy */ 722 uint16_t average_socket_power; 723 uint32_t energy_accumulator; 724 725 /* Average clocks */ 726 uint16_t average_gfxclk_frequency; 727 uint16_t average_socclk_frequency; 728 uint16_t average_uclk_frequency; 729 uint16_t average_vclk0_frequency; 730 uint16_t average_dclk0_frequency; 731 uint16_t average_vclk1_frequency; 732 uint16_t average_dclk1_frequency; 733 734 /* Current clocks */ 735 uint16_t current_gfxclk; 736 uint16_t current_socclk; 737 uint16_t current_uclk; 738 uint16_t current_vclk0; 739 uint16_t current_dclk0; 740 uint16_t current_vclk1; 741 uint16_t current_dclk1; 742 743 /* Throttle status */ 744 uint32_t throttle_status; 745 746 /* Fans */ 747 uint16_t current_fan_speed; 748 749 /* Link width/speed */ 750 uint8_t pcie_link_width; 751 uint8_t pcie_link_speed; // in 0.1 GT/s 752 }; 753 754 struct gpu_metrics_v1_1 { 755 struct metrics_table_header common_header; 756 757 /* Temperature */ 758 uint16_t temperature_edge; 759 uint16_t temperature_hotspot; 760 uint16_t temperature_mem; 761 uint16_t temperature_vrgfx; 762 uint16_t temperature_vrsoc; 763 uint16_t temperature_vrmem; 764 765 /* Utilization */ 766 uint16_t average_gfx_activity; 767 uint16_t average_umc_activity; // memory controller 768 uint16_t average_mm_activity; // UVD or VCN 769 770 /* Power/Energy */ 771 uint16_t average_socket_power; 772 uint64_t energy_accumulator; 773 774 /* Driver attached timestamp (in ns) */ 775 uint64_t system_clock_counter; 776 777 /* Average clocks */ 778 uint16_t average_gfxclk_frequency; 779 uint16_t average_socclk_frequency; 780 uint16_t average_uclk_frequency; 781 uint16_t average_vclk0_frequency; 782 uint16_t average_dclk0_frequency; 783 uint16_t average_vclk1_frequency; 784 uint16_t average_dclk1_frequency; 785 786 /* Current clocks */ 787 uint16_t current_gfxclk; 788 uint16_t current_socclk; 789 uint16_t current_uclk; 790 uint16_t current_vclk0; 791 uint16_t current_dclk0; 792 uint16_t current_vclk1; 793 uint16_t current_dclk1; 794 795 /* Throttle status */ 796 uint32_t throttle_status; 797 798 /* Fans */ 799 uint16_t current_fan_speed; 800 801 /* Link width/speed */ 802 uint16_t pcie_link_width; 803 uint16_t pcie_link_speed; // in 0.1 GT/s 804 805 uint16_t padding; 806 807 uint32_t gfx_activity_acc; 808 uint32_t mem_activity_acc; 809 810 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 811 }; 812 813 struct gpu_metrics_v1_2 { 814 struct metrics_table_header common_header; 815 816 /* Temperature */ 817 uint16_t temperature_edge; 818 uint16_t temperature_hotspot; 819 uint16_t temperature_mem; 820 uint16_t temperature_vrgfx; 821 uint16_t temperature_vrsoc; 822 uint16_t temperature_vrmem; 823 824 /* Utilization */ 825 uint16_t average_gfx_activity; 826 uint16_t average_umc_activity; // memory controller 827 uint16_t average_mm_activity; // UVD or VCN 828 829 /* Power/Energy */ 830 uint16_t average_socket_power; 831 uint64_t energy_accumulator; 832 833 /* Driver attached timestamp (in ns) */ 834 uint64_t system_clock_counter; 835 836 /* Average clocks */ 837 uint16_t average_gfxclk_frequency; 838 uint16_t average_socclk_frequency; 839 uint16_t average_uclk_frequency; 840 uint16_t average_vclk0_frequency; 841 uint16_t average_dclk0_frequency; 842 uint16_t average_vclk1_frequency; 843 uint16_t average_dclk1_frequency; 844 845 /* Current clocks */ 846 uint16_t current_gfxclk; 847 uint16_t current_socclk; 848 uint16_t current_uclk; 849 uint16_t current_vclk0; 850 uint16_t current_dclk0; 851 uint16_t current_vclk1; 852 uint16_t current_dclk1; 853 854 /* Throttle status (ASIC dependent) */ 855 uint32_t throttle_status; 856 857 /* Fans */ 858 uint16_t current_fan_speed; 859 860 /* Link width/speed */ 861 uint16_t pcie_link_width; 862 uint16_t pcie_link_speed; // in 0.1 GT/s 863 864 uint16_t padding; 865 866 uint32_t gfx_activity_acc; 867 uint32_t mem_activity_acc; 868 869 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 870 871 /* PMFW attached timestamp (10ns resolution) */ 872 uint64_t firmware_timestamp; 873 }; 874 875 struct gpu_metrics_v1_3 { 876 struct metrics_table_header common_header; 877 878 /* Temperature */ 879 uint16_t temperature_edge; 880 uint16_t temperature_hotspot; 881 uint16_t temperature_mem; 882 uint16_t temperature_vrgfx; 883 uint16_t temperature_vrsoc; 884 uint16_t temperature_vrmem; 885 886 /* Utilization */ 887 uint16_t average_gfx_activity; 888 uint16_t average_umc_activity; // memory controller 889 uint16_t average_mm_activity; // UVD or VCN 890 891 /* Power/Energy */ 892 uint16_t average_socket_power; 893 uint64_t energy_accumulator; 894 895 /* Driver attached timestamp (in ns) */ 896 uint64_t system_clock_counter; 897 898 /* Average clocks */ 899 uint16_t average_gfxclk_frequency; 900 uint16_t average_socclk_frequency; 901 uint16_t average_uclk_frequency; 902 uint16_t average_vclk0_frequency; 903 uint16_t average_dclk0_frequency; 904 uint16_t average_vclk1_frequency; 905 uint16_t average_dclk1_frequency; 906 907 /* Current clocks */ 908 uint16_t current_gfxclk; 909 uint16_t current_socclk; 910 uint16_t current_uclk; 911 uint16_t current_vclk0; 912 uint16_t current_dclk0; 913 uint16_t current_vclk1; 914 uint16_t current_dclk1; 915 916 /* Throttle status */ 917 uint32_t throttle_status; 918 919 /* Fans */ 920 uint16_t current_fan_speed; 921 922 /* Link width/speed */ 923 uint16_t pcie_link_width; 924 uint16_t pcie_link_speed; // in 0.1 GT/s 925 926 uint16_t padding; 927 928 uint32_t gfx_activity_acc; 929 uint32_t mem_activity_acc; 930 931 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 932 933 /* PMFW attached timestamp (10ns resolution) */ 934 uint64_t firmware_timestamp; 935 936 /* Voltage (mV) */ 937 uint16_t voltage_soc; 938 uint16_t voltage_gfx; 939 uint16_t voltage_mem; 940 941 uint16_t padding1; 942 943 /* Throttle status (ASIC independent) */ 944 uint64_t indep_throttle_status; 945 }; 946 947 struct gpu_metrics_v1_4 { 948 struct metrics_table_header common_header; 949 950 /* Temperature (Celsius) */ 951 uint16_t temperature_hotspot; 952 uint16_t temperature_mem; 953 uint16_t temperature_vrsoc; 954 955 /* Power (Watts) */ 956 uint16_t curr_socket_power; 957 958 /* Utilization (%) */ 959 uint16_t average_gfx_activity; 960 uint16_t average_umc_activity; // memory controller 961 uint16_t vcn_activity[NUM_VCN]; 962 963 /* Energy (15.259uJ (2^-16) units) */ 964 uint64_t energy_accumulator; 965 966 /* Driver attached timestamp (in ns) */ 967 uint64_t system_clock_counter; 968 969 /* Throttle status */ 970 uint32_t throttle_status; 971 972 /* Clock Lock Status. Each bit corresponds to clock instance */ 973 uint32_t gfxclk_lock_status; 974 975 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 976 uint16_t pcie_link_width; 977 uint16_t pcie_link_speed; 978 979 /* XGMI bus width and bitrate (in Gbps) */ 980 uint16_t xgmi_link_width; 981 uint16_t xgmi_link_speed; 982 983 /* Utilization Accumulated (%) */ 984 uint32_t gfx_activity_acc; 985 uint32_t mem_activity_acc; 986 987 /*PCIE accumulated bandwidth (GB/sec) */ 988 uint64_t pcie_bandwidth_acc; 989 990 /*PCIE instantaneous bandwidth (GB/sec) */ 991 uint64_t pcie_bandwidth_inst; 992 993 /* PCIE L0 to recovery state transition accumulated count */ 994 uint64_t pcie_l0_to_recov_count_acc; 995 996 /* PCIE replay accumulated count */ 997 uint64_t pcie_replay_count_acc; 998 999 /* PCIE replay rollover accumulated count */ 1000 uint64_t pcie_replay_rover_count_acc; 1001 1002 /* XGMI accumulated data transfer size(KiloBytes) */ 1003 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1004 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1005 1006 /* PMFW attached timestamp (10ns resolution) */ 1007 uint64_t firmware_timestamp; 1008 1009 /* Current clocks (Mhz) */ 1010 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1011 uint16_t current_socclk[MAX_CLKS]; 1012 uint16_t current_vclk0[MAX_CLKS]; 1013 uint16_t current_dclk0[MAX_CLKS]; 1014 uint16_t current_uclk; 1015 1016 uint16_t padding; 1017 }; 1018 1019 struct gpu_metrics_v1_5 { 1020 struct metrics_table_header common_header; 1021 1022 /* Temperature (Celsius) */ 1023 uint16_t temperature_hotspot; 1024 uint16_t temperature_mem; 1025 uint16_t temperature_vrsoc; 1026 1027 /* Power (Watts) */ 1028 uint16_t curr_socket_power; 1029 1030 /* Utilization (%) */ 1031 uint16_t average_gfx_activity; 1032 uint16_t average_umc_activity; // memory controller 1033 uint16_t vcn_activity[NUM_VCN]; 1034 uint16_t jpeg_activity[NUM_JPEG_ENG]; 1035 1036 /* Energy (15.259uJ (2^-16) units) */ 1037 uint64_t energy_accumulator; 1038 1039 /* Driver attached timestamp (in ns) */ 1040 uint64_t system_clock_counter; 1041 1042 /* Throttle status */ 1043 uint32_t throttle_status; 1044 1045 /* Clock Lock Status. Each bit corresponds to clock instance */ 1046 uint32_t gfxclk_lock_status; 1047 1048 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1049 uint16_t pcie_link_width; 1050 uint16_t pcie_link_speed; 1051 1052 /* XGMI bus width and bitrate (in Gbps) */ 1053 uint16_t xgmi_link_width; 1054 uint16_t xgmi_link_speed; 1055 1056 /* Utilization Accumulated (%) */ 1057 uint32_t gfx_activity_acc; 1058 uint32_t mem_activity_acc; 1059 1060 /*PCIE accumulated bandwidth (GB/sec) */ 1061 uint64_t pcie_bandwidth_acc; 1062 1063 /*PCIE instantaneous bandwidth (GB/sec) */ 1064 uint64_t pcie_bandwidth_inst; 1065 1066 /* PCIE L0 to recovery state transition accumulated count */ 1067 uint64_t pcie_l0_to_recov_count_acc; 1068 1069 /* PCIE replay accumulated count */ 1070 uint64_t pcie_replay_count_acc; 1071 1072 /* PCIE replay rollover accumulated count */ 1073 uint64_t pcie_replay_rover_count_acc; 1074 1075 /* PCIE NAK sent accumulated count */ 1076 uint32_t pcie_nak_sent_count_acc; 1077 1078 /* PCIE NAK received accumulated count */ 1079 uint32_t pcie_nak_rcvd_count_acc; 1080 1081 /* XGMI accumulated data transfer size(KiloBytes) */ 1082 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1083 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1084 1085 /* PMFW attached timestamp (10ns resolution) */ 1086 uint64_t firmware_timestamp; 1087 1088 /* Current clocks (Mhz) */ 1089 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1090 uint16_t current_socclk[MAX_CLKS]; 1091 uint16_t current_vclk0[MAX_CLKS]; 1092 uint16_t current_dclk0[MAX_CLKS]; 1093 uint16_t current_uclk; 1094 1095 uint16_t padding; 1096 }; 1097 1098 struct gpu_metrics_v1_6 { 1099 struct metrics_table_header common_header; 1100 1101 /* Temperature (Celsius) */ 1102 uint16_t temperature_hotspot; 1103 uint16_t temperature_mem; 1104 uint16_t temperature_vrsoc; 1105 1106 /* Power (Watts) */ 1107 uint16_t curr_socket_power; 1108 1109 /* Utilization (%) */ 1110 uint16_t average_gfx_activity; 1111 uint16_t average_umc_activity; // memory controller 1112 1113 /* Energy (15.259uJ (2^-16) units) */ 1114 uint64_t energy_accumulator; 1115 1116 /* Driver attached timestamp (in ns) */ 1117 uint64_t system_clock_counter; 1118 1119 /* Accumulation cycle counter */ 1120 uint32_t accumulation_counter; 1121 1122 /* Accumulated throttler residencies */ 1123 uint32_t prochot_residency_acc; 1124 uint32_t ppt_residency_acc; 1125 uint32_t socket_thm_residency_acc; 1126 uint32_t vr_thm_residency_acc; 1127 uint32_t hbm_thm_residency_acc; 1128 1129 /* Clock Lock Status. Each bit corresponds to clock instance */ 1130 uint32_t gfxclk_lock_status; 1131 1132 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1133 uint16_t pcie_link_width; 1134 uint16_t pcie_link_speed; 1135 1136 /* XGMI bus width and bitrate (in Gbps) */ 1137 uint16_t xgmi_link_width; 1138 uint16_t xgmi_link_speed; 1139 1140 /* Utilization Accumulated (%) */ 1141 uint32_t gfx_activity_acc; 1142 uint32_t mem_activity_acc; 1143 1144 /*PCIE accumulated bandwidth (GB/sec) */ 1145 uint64_t pcie_bandwidth_acc; 1146 1147 /*PCIE instantaneous bandwidth (GB/sec) */ 1148 uint64_t pcie_bandwidth_inst; 1149 1150 /* PCIE L0 to recovery state transition accumulated count */ 1151 uint64_t pcie_l0_to_recov_count_acc; 1152 1153 /* PCIE replay accumulated count */ 1154 uint64_t pcie_replay_count_acc; 1155 1156 /* PCIE replay rollover accumulated count */ 1157 uint64_t pcie_replay_rover_count_acc; 1158 1159 /* PCIE NAK sent accumulated count */ 1160 uint32_t pcie_nak_sent_count_acc; 1161 1162 /* PCIE NAK received accumulated count */ 1163 uint32_t pcie_nak_rcvd_count_acc; 1164 1165 /* XGMI accumulated data transfer size(KiloBytes) */ 1166 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1167 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1168 1169 /* PMFW attached timestamp (10ns resolution) */ 1170 uint64_t firmware_timestamp; 1171 1172 /* Current clocks (Mhz) */ 1173 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1174 uint16_t current_socclk[MAX_CLKS]; 1175 uint16_t current_vclk0[MAX_CLKS]; 1176 uint16_t current_dclk0[MAX_CLKS]; 1177 uint16_t current_uclk; 1178 1179 /* Number of current partition */ 1180 uint16_t num_partition; 1181 1182 /* XCP metrics stats */ 1183 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1184 1185 /* PCIE other end recovery counter */ 1186 uint32_t pcie_lc_perf_other_end_recovery; 1187 }; 1188 1189 struct gpu_metrics_v1_7 { 1190 struct metrics_table_header common_header; 1191 1192 /* Temperature (Celsius) */ 1193 uint16_t temperature_hotspot; 1194 uint16_t temperature_mem; 1195 uint16_t temperature_vrsoc; 1196 1197 /* Power (Watts) */ 1198 uint16_t curr_socket_power; 1199 1200 /* Utilization (%) */ 1201 uint16_t average_gfx_activity; 1202 uint16_t average_umc_activity; // memory controller 1203 1204 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1205 uint64_t mem_max_bandwidth; 1206 1207 /* Energy (15.259uJ (2^-16) units) */ 1208 uint64_t energy_accumulator; 1209 1210 /* Driver attached timestamp (in ns) */ 1211 uint64_t system_clock_counter; 1212 1213 /* Accumulation cycle counter */ 1214 uint32_t accumulation_counter; 1215 1216 /* Accumulated throttler residencies */ 1217 uint32_t prochot_residency_acc; 1218 uint32_t ppt_residency_acc; 1219 uint32_t socket_thm_residency_acc; 1220 uint32_t vr_thm_residency_acc; 1221 uint32_t hbm_thm_residency_acc; 1222 1223 /* Clock Lock Status. Each bit corresponds to clock instance */ 1224 uint32_t gfxclk_lock_status; 1225 1226 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1227 uint16_t pcie_link_width; 1228 uint16_t pcie_link_speed; 1229 1230 /* XGMI bus width and bitrate (in Gbps) */ 1231 uint16_t xgmi_link_width; 1232 uint16_t xgmi_link_speed; 1233 1234 /* Utilization Accumulated (%) */ 1235 uint32_t gfx_activity_acc; 1236 uint32_t mem_activity_acc; 1237 1238 /*PCIE accumulated bandwidth (GB/sec) */ 1239 uint64_t pcie_bandwidth_acc; 1240 1241 /*PCIE instantaneous bandwidth (GB/sec) */ 1242 uint64_t pcie_bandwidth_inst; 1243 1244 /* PCIE L0 to recovery state transition accumulated count */ 1245 uint64_t pcie_l0_to_recov_count_acc; 1246 1247 /* PCIE replay accumulated count */ 1248 uint64_t pcie_replay_count_acc; 1249 1250 /* PCIE replay rollover accumulated count */ 1251 uint64_t pcie_replay_rover_count_acc; 1252 1253 /* PCIE NAK sent accumulated count */ 1254 uint32_t pcie_nak_sent_count_acc; 1255 1256 /* PCIE NAK received accumulated count */ 1257 uint32_t pcie_nak_rcvd_count_acc; 1258 1259 /* XGMI accumulated data transfer size(KiloBytes) */ 1260 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1261 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1262 1263 /* XGMI link status(active/inactive) */ 1264 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1265 1266 uint16_t padding; 1267 1268 /* PMFW attached timestamp (10ns resolution) */ 1269 uint64_t firmware_timestamp; 1270 1271 /* Current clocks (Mhz) */ 1272 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1273 uint16_t current_socclk[MAX_CLKS]; 1274 uint16_t current_vclk0[MAX_CLKS]; 1275 uint16_t current_dclk0[MAX_CLKS]; 1276 uint16_t current_uclk; 1277 1278 /* Number of current partition */ 1279 uint16_t num_partition; 1280 1281 /* XCP metrics stats */ 1282 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1283 1284 /* PCIE other end recovery counter */ 1285 uint32_t pcie_lc_perf_other_end_recovery; 1286 }; 1287 1288 struct gpu_metrics_v1_8 { 1289 struct metrics_table_header common_header; 1290 1291 /* Temperature (Celsius) */ 1292 uint16_t temperature_hotspot; 1293 uint16_t temperature_mem; 1294 uint16_t temperature_vrsoc; 1295 1296 /* Power (Watts) */ 1297 uint16_t curr_socket_power; 1298 1299 /* Utilization (%) */ 1300 uint16_t average_gfx_activity; 1301 uint16_t average_umc_activity; // memory controller 1302 1303 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1304 uint64_t mem_max_bandwidth; 1305 1306 /* Energy (15.259uJ (2^-16) units) */ 1307 uint64_t energy_accumulator; 1308 1309 /* Driver attached timestamp (in ns) */ 1310 uint64_t system_clock_counter; 1311 1312 /* Accumulation cycle counter */ 1313 uint32_t accumulation_counter; 1314 1315 /* Accumulated throttler residencies */ 1316 uint32_t prochot_residency_acc; 1317 uint32_t ppt_residency_acc; 1318 uint32_t socket_thm_residency_acc; 1319 uint32_t vr_thm_residency_acc; 1320 uint32_t hbm_thm_residency_acc; 1321 1322 /* Clock Lock Status. Each bit corresponds to clock instance */ 1323 uint32_t gfxclk_lock_status; 1324 1325 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1326 uint16_t pcie_link_width; 1327 uint16_t pcie_link_speed; 1328 1329 /* XGMI bus width and bitrate (in Gbps) */ 1330 uint16_t xgmi_link_width; 1331 uint16_t xgmi_link_speed; 1332 1333 /* Utilization Accumulated (%) */ 1334 uint32_t gfx_activity_acc; 1335 uint32_t mem_activity_acc; 1336 1337 /*PCIE accumulated bandwidth (GB/sec) */ 1338 uint64_t pcie_bandwidth_acc; 1339 1340 /*PCIE instantaneous bandwidth (GB/sec) */ 1341 uint64_t pcie_bandwidth_inst; 1342 1343 /* PCIE L0 to recovery state transition accumulated count */ 1344 uint64_t pcie_l0_to_recov_count_acc; 1345 1346 /* PCIE replay accumulated count */ 1347 uint64_t pcie_replay_count_acc; 1348 1349 /* PCIE replay rollover accumulated count */ 1350 uint64_t pcie_replay_rover_count_acc; 1351 1352 /* PCIE NAK sent accumulated count */ 1353 uint32_t pcie_nak_sent_count_acc; 1354 1355 /* PCIE NAK received accumulated count */ 1356 uint32_t pcie_nak_rcvd_count_acc; 1357 1358 /* XGMI accumulated data transfer size(KiloBytes) */ 1359 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1360 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1361 1362 /* XGMI link status(active/inactive) */ 1363 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1364 1365 uint16_t padding; 1366 1367 /* PMFW attached timestamp (10ns resolution) */ 1368 uint64_t firmware_timestamp; 1369 1370 /* Current clocks (Mhz) */ 1371 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1372 uint16_t current_socclk[MAX_CLKS]; 1373 uint16_t current_vclk0[MAX_CLKS]; 1374 uint16_t current_dclk0[MAX_CLKS]; 1375 uint16_t current_uclk; 1376 1377 /* Number of current partition */ 1378 uint16_t num_partition; 1379 1380 /* XCP metrics stats */ 1381 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1382 1383 /* PCIE other end recovery counter */ 1384 uint32_t pcie_lc_perf_other_end_recovery; 1385 }; 1386 1387 struct gpu_metrics_attr { 1388 /* Field type encoded with AMDGPU_METRICS_ENC_ATTR */ 1389 uint64_t attr_encoding; 1390 /* Attribute value, depends on attr_encoding */ 1391 void *attr_value; 1392 }; 1393 1394 struct gpu_metrics_v1_9 { 1395 struct metrics_table_header common_header; 1396 int attr_count; 1397 struct gpu_metrics_attr metrics_attrs[]; 1398 }; 1399 1400 /* 1401 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1402 * Use gpu_metrics_v2_1 or later instead. 1403 */ 1404 struct gpu_metrics_v2_0 { 1405 struct metrics_table_header common_header; 1406 1407 /* Driver attached timestamp (in ns) */ 1408 uint64_t system_clock_counter; 1409 1410 /* Temperature */ 1411 uint16_t temperature_gfx; // gfx temperature on APUs 1412 uint16_t temperature_soc; // soc temperature on APUs 1413 uint16_t temperature_core[8]; // CPU core temperature on APUs 1414 uint16_t temperature_l3[2]; 1415 1416 /* Utilization */ 1417 uint16_t average_gfx_activity; 1418 uint16_t average_mm_activity; // UVD or VCN 1419 1420 /* Power/Energy */ 1421 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1422 uint16_t average_cpu_power; 1423 uint16_t average_soc_power; 1424 uint16_t average_gfx_power; 1425 uint16_t average_core_power[8]; // CPU core power on APUs 1426 1427 /* Average clocks */ 1428 uint16_t average_gfxclk_frequency; 1429 uint16_t average_socclk_frequency; 1430 uint16_t average_uclk_frequency; 1431 uint16_t average_fclk_frequency; 1432 uint16_t average_vclk_frequency; 1433 uint16_t average_dclk_frequency; 1434 1435 /* Current clocks */ 1436 uint16_t current_gfxclk; 1437 uint16_t current_socclk; 1438 uint16_t current_uclk; 1439 uint16_t current_fclk; 1440 uint16_t current_vclk; 1441 uint16_t current_dclk; 1442 uint16_t current_coreclk[8]; // CPU core clocks 1443 uint16_t current_l3clk[2]; 1444 1445 /* Throttle status */ 1446 uint32_t throttle_status; 1447 1448 /* Fans */ 1449 uint16_t fan_pwm; 1450 1451 uint16_t padding; 1452 }; 1453 1454 struct gpu_metrics_v2_1 { 1455 struct metrics_table_header common_header; 1456 1457 /* Temperature */ 1458 uint16_t temperature_gfx; // gfx temperature on APUs 1459 uint16_t temperature_soc; // soc temperature on APUs 1460 uint16_t temperature_core[8]; // CPU core temperature on APUs 1461 uint16_t temperature_l3[2]; 1462 1463 /* Utilization */ 1464 uint16_t average_gfx_activity; 1465 uint16_t average_mm_activity; // UVD or VCN 1466 1467 /* Driver attached timestamp (in ns) */ 1468 uint64_t system_clock_counter; 1469 1470 /* Power/Energy */ 1471 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1472 uint16_t average_cpu_power; 1473 uint16_t average_soc_power; 1474 uint16_t average_gfx_power; 1475 uint16_t average_core_power[8]; // CPU core power on APUs 1476 1477 /* Average clocks */ 1478 uint16_t average_gfxclk_frequency; 1479 uint16_t average_socclk_frequency; 1480 uint16_t average_uclk_frequency; 1481 uint16_t average_fclk_frequency; 1482 uint16_t average_vclk_frequency; 1483 uint16_t average_dclk_frequency; 1484 1485 /* Current clocks */ 1486 uint16_t current_gfxclk; 1487 uint16_t current_socclk; 1488 uint16_t current_uclk; 1489 uint16_t current_fclk; 1490 uint16_t current_vclk; 1491 uint16_t current_dclk; 1492 uint16_t current_coreclk[8]; // CPU core clocks 1493 uint16_t current_l3clk[2]; 1494 1495 /* Throttle status */ 1496 uint32_t throttle_status; 1497 1498 /* Fans */ 1499 uint16_t fan_pwm; 1500 1501 uint16_t padding[3]; 1502 }; 1503 1504 struct gpu_metrics_v2_2 { 1505 struct metrics_table_header common_header; 1506 1507 /* Temperature */ 1508 uint16_t temperature_gfx; // gfx temperature on APUs 1509 uint16_t temperature_soc; // soc temperature on APUs 1510 uint16_t temperature_core[8]; // CPU core temperature on APUs 1511 uint16_t temperature_l3[2]; 1512 1513 /* Utilization */ 1514 uint16_t average_gfx_activity; 1515 uint16_t average_mm_activity; // UVD or VCN 1516 1517 /* Driver attached timestamp (in ns) */ 1518 uint64_t system_clock_counter; 1519 1520 /* Power/Energy */ 1521 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1522 uint16_t average_cpu_power; 1523 uint16_t average_soc_power; 1524 uint16_t average_gfx_power; 1525 uint16_t average_core_power[8]; // CPU core power on APUs 1526 1527 /* Average clocks */ 1528 uint16_t average_gfxclk_frequency; 1529 uint16_t average_socclk_frequency; 1530 uint16_t average_uclk_frequency; 1531 uint16_t average_fclk_frequency; 1532 uint16_t average_vclk_frequency; 1533 uint16_t average_dclk_frequency; 1534 1535 /* Current clocks */ 1536 uint16_t current_gfxclk; 1537 uint16_t current_socclk; 1538 uint16_t current_uclk; 1539 uint16_t current_fclk; 1540 uint16_t current_vclk; 1541 uint16_t current_dclk; 1542 uint16_t current_coreclk[8]; // CPU core clocks 1543 uint16_t current_l3clk[2]; 1544 1545 /* Throttle status (ASIC dependent) */ 1546 uint32_t throttle_status; 1547 1548 /* Fans */ 1549 uint16_t fan_pwm; 1550 1551 uint16_t padding[3]; 1552 1553 /* Throttle status (ASIC independent) */ 1554 uint64_t indep_throttle_status; 1555 }; 1556 1557 struct gpu_metrics_v2_3 { 1558 struct metrics_table_header common_header; 1559 1560 /* Temperature */ 1561 uint16_t temperature_gfx; // gfx temperature on APUs 1562 uint16_t temperature_soc; // soc temperature on APUs 1563 uint16_t temperature_core[8]; // CPU core temperature on APUs 1564 uint16_t temperature_l3[2]; 1565 1566 /* Utilization */ 1567 uint16_t average_gfx_activity; 1568 uint16_t average_mm_activity; // UVD or VCN 1569 1570 /* Driver attached timestamp (in ns) */ 1571 uint64_t system_clock_counter; 1572 1573 /* Power/Energy */ 1574 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1575 uint16_t average_cpu_power; 1576 uint16_t average_soc_power; 1577 uint16_t average_gfx_power; 1578 uint16_t average_core_power[8]; // CPU core power on APUs 1579 1580 /* Average clocks */ 1581 uint16_t average_gfxclk_frequency; 1582 uint16_t average_socclk_frequency; 1583 uint16_t average_uclk_frequency; 1584 uint16_t average_fclk_frequency; 1585 uint16_t average_vclk_frequency; 1586 uint16_t average_dclk_frequency; 1587 1588 /* Current clocks */ 1589 uint16_t current_gfxclk; 1590 uint16_t current_socclk; 1591 uint16_t current_uclk; 1592 uint16_t current_fclk; 1593 uint16_t current_vclk; 1594 uint16_t current_dclk; 1595 uint16_t current_coreclk[8]; // CPU core clocks 1596 uint16_t current_l3clk[2]; 1597 1598 /* Throttle status (ASIC dependent) */ 1599 uint32_t throttle_status; 1600 1601 /* Fans */ 1602 uint16_t fan_pwm; 1603 1604 uint16_t padding[3]; 1605 1606 /* Throttle status (ASIC independent) */ 1607 uint64_t indep_throttle_status; 1608 1609 /* Average Temperature */ 1610 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1611 uint16_t average_temperature_soc; // average soc temperature on APUs 1612 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1613 uint16_t average_temperature_l3[2]; 1614 }; 1615 1616 struct gpu_metrics_v2_4 { 1617 struct metrics_table_header common_header; 1618 1619 /* Temperature (unit: centi-Celsius) */ 1620 uint16_t temperature_gfx; 1621 uint16_t temperature_soc; 1622 uint16_t temperature_core[8]; 1623 uint16_t temperature_l3[2]; 1624 1625 /* Utilization (unit: centi) */ 1626 uint16_t average_gfx_activity; 1627 uint16_t average_mm_activity; 1628 1629 /* Driver attached timestamp (in ns) */ 1630 uint64_t system_clock_counter; 1631 1632 /* Power/Energy (unit: mW) */ 1633 uint16_t average_socket_power; 1634 uint16_t average_cpu_power; 1635 uint16_t average_soc_power; 1636 uint16_t average_gfx_power; 1637 uint16_t average_core_power[8]; 1638 1639 /* Average clocks (unit: MHz) */ 1640 uint16_t average_gfxclk_frequency; 1641 uint16_t average_socclk_frequency; 1642 uint16_t average_uclk_frequency; 1643 uint16_t average_fclk_frequency; 1644 uint16_t average_vclk_frequency; 1645 uint16_t average_dclk_frequency; 1646 1647 /* Current clocks (unit: MHz) */ 1648 uint16_t current_gfxclk; 1649 uint16_t current_socclk; 1650 uint16_t current_uclk; 1651 uint16_t current_fclk; 1652 uint16_t current_vclk; 1653 uint16_t current_dclk; 1654 uint16_t current_coreclk[8]; 1655 uint16_t current_l3clk[2]; 1656 1657 /* Throttle status (ASIC dependent) */ 1658 uint32_t throttle_status; 1659 1660 /* Fans */ 1661 uint16_t fan_pwm; 1662 1663 uint16_t padding[3]; 1664 1665 /* Throttle status (ASIC independent) */ 1666 uint64_t indep_throttle_status; 1667 1668 /* Average Temperature (unit: centi-Celsius) */ 1669 uint16_t average_temperature_gfx; 1670 uint16_t average_temperature_soc; 1671 uint16_t average_temperature_core[8]; 1672 uint16_t average_temperature_l3[2]; 1673 1674 /* Power/Voltage (unit: mV) */ 1675 uint16_t average_cpu_voltage; 1676 uint16_t average_soc_voltage; 1677 uint16_t average_gfx_voltage; 1678 1679 /* Power/Current (unit: mA) */ 1680 uint16_t average_cpu_current; 1681 uint16_t average_soc_current; 1682 uint16_t average_gfx_current; 1683 }; 1684 1685 struct gpu_metrics_v3_0 { 1686 struct metrics_table_header common_header; 1687 1688 /* Temperature */ 1689 /* gfx temperature on APUs */ 1690 uint16_t temperature_gfx; 1691 /* soc temperature on APUs */ 1692 uint16_t temperature_soc; 1693 /* CPU core temperature on APUs */ 1694 uint16_t temperature_core[16]; 1695 /* skin temperature on APUs */ 1696 uint16_t temperature_skin; 1697 1698 /* Utilization */ 1699 /* time filtered GFX busy % [0-100] */ 1700 uint16_t average_gfx_activity; 1701 /* time filtered VCN busy % [0-100] */ 1702 uint16_t average_vcn_activity; 1703 /* time filtered IPU per-column busy % [0-100] */ 1704 uint16_t average_ipu_activity[8]; 1705 /* time filtered per-core C0 residency % [0-100]*/ 1706 uint16_t average_core_c0_activity[16]; 1707 /* time filtered DRAM read bandwidth [MB/sec] */ 1708 uint16_t average_dram_reads; 1709 /* time filtered DRAM write bandwidth [MB/sec] */ 1710 uint16_t average_dram_writes; 1711 /* time filtered IPU read bandwidth [MB/sec] */ 1712 uint16_t average_ipu_reads; 1713 /* time filtered IPU write bandwidth [MB/sec] */ 1714 uint16_t average_ipu_writes; 1715 1716 /* Driver attached timestamp (in ns) */ 1717 uint64_t system_clock_counter; 1718 1719 /* Power/Energy */ 1720 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1721 uint32_t average_socket_power; 1722 /* time filtered IPU power [mW] */ 1723 uint16_t average_ipu_power; 1724 /* time filtered APU power [mW] */ 1725 uint32_t average_apu_power; 1726 /* time filtered GFX power [mW] */ 1727 uint32_t average_gfx_power; 1728 /* time filtered dGPU power [mW] */ 1729 uint32_t average_dgpu_power; 1730 /* time filtered sum of core power across all cores in the socket [mW] */ 1731 uint32_t average_all_core_power; 1732 /* calculated core power [mW] */ 1733 uint16_t average_core_power[16]; 1734 /* time filtered total system power [mW] */ 1735 uint16_t average_sys_power; 1736 /* maximum IRM defined STAPM power limit [mW] */ 1737 uint16_t stapm_power_limit; 1738 /* time filtered STAPM power limit [mW] */ 1739 uint16_t current_stapm_power_limit; 1740 1741 /* time filtered clocks [MHz] */ 1742 uint16_t average_gfxclk_frequency; 1743 uint16_t average_socclk_frequency; 1744 uint16_t average_vpeclk_frequency; 1745 uint16_t average_ipuclk_frequency; 1746 uint16_t average_fclk_frequency; 1747 uint16_t average_vclk_frequency; 1748 uint16_t average_uclk_frequency; 1749 uint16_t average_mpipu_frequency; 1750 1751 /* Current clocks */ 1752 /* target core frequency [MHz] */ 1753 uint16_t current_coreclk[16]; 1754 /* CCLK frequency limit enforced on classic cores [MHz] */ 1755 uint16_t current_core_maxfreq; 1756 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1757 uint16_t current_gfx_maxfreq; 1758 1759 /* Throttle Residency (ASIC dependent) */ 1760 uint32_t throttle_residency_prochot; 1761 uint32_t throttle_residency_spl; 1762 uint32_t throttle_residency_fppt; 1763 uint32_t throttle_residency_sppt; 1764 uint32_t throttle_residency_thm_core; 1765 uint32_t throttle_residency_thm_gfx; 1766 uint32_t throttle_residency_thm_soc; 1767 1768 /* Metrics table alpha filter time constant [us] */ 1769 uint32_t time_filter_alphavalue; 1770 }; 1771 1772 struct amdgpu_pmmetrics_header { 1773 uint16_t structure_size; 1774 uint16_t pad; 1775 uint32_t mp1_ip_discovery_version; 1776 uint32_t pmfw_version; 1777 uint32_t pmmetrics_version; 1778 }; 1779 1780 struct amdgpu_pm_metrics { 1781 struct amdgpu_pmmetrics_header common_header; 1782 1783 uint8_t data[]; 1784 }; 1785 1786 enum amdgpu_vr_temp { 1787 AMDGPU_VDDCR_VDD0_TEMP, 1788 AMDGPU_VDDCR_VDD1_TEMP, 1789 AMDGPU_VDDCR_VDD2_TEMP, 1790 AMDGPU_VDDCR_VDD3_TEMP, 1791 AMDGPU_VDDCR_SOC_A_TEMP, 1792 AMDGPU_VDDCR_SOC_C_TEMP, 1793 AMDGPU_VDDCR_SOCIO_A_TEMP, 1794 AMDGPU_VDDCR_SOCIO_C_TEMP, 1795 AMDGPU_VDD_085_HBM_TEMP, 1796 AMDGPU_VDDCR_11_HBM_B_TEMP, 1797 AMDGPU_VDDCR_11_HBM_D_TEMP, 1798 AMDGPU_VDD_USR_TEMP, 1799 AMDGPU_VDDIO_11_E32_TEMP, 1800 AMDGPU_VR_MAX_TEMP_ENTRIES, 1801 }; 1802 1803 enum amdgpu_system_temp { 1804 AMDGPU_UBB_FPGA_TEMP, 1805 AMDGPU_UBB_FRONT_TEMP, 1806 AMDGPU_UBB_BACK_TEMP, 1807 AMDGPU_UBB_OAM7_TEMP, 1808 AMDGPU_UBB_IBC_TEMP, 1809 AMDGPU_UBB_UFPGA_TEMP, 1810 AMDGPU_UBB_OAM1_TEMP, 1811 AMDGPU_OAM_0_1_HSC_TEMP, 1812 AMDGPU_OAM_2_3_HSC_TEMP, 1813 AMDGPU_OAM_4_5_HSC_TEMP, 1814 AMDGPU_OAM_6_7_HSC_TEMP, 1815 AMDGPU_UBB_FPGA_0V72_VR_TEMP, 1816 AMDGPU_UBB_FPGA_3V3_VR_TEMP, 1817 AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP, 1818 AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP, 1819 AMDGPU_RETIMER_0_1_0V9_VR_TEMP, 1820 AMDGPU_RETIMER_4_5_0V9_VR_TEMP, 1821 AMDGPU_RETIMER_2_3_0V9_VR_TEMP, 1822 AMDGPU_RETIMER_6_7_0V9_VR_TEMP, 1823 AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP, 1824 AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP, 1825 AMDGPU_IBC_HSC_TEMP, 1826 AMDGPU_IBC_TEMP, 1827 AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32, 1828 }; 1829 1830 enum amdgpu_node_temp { 1831 AMDGPU_RETIMER_X_TEMP, 1832 AMDGPU_OAM_X_IBC_TEMP, 1833 AMDGPU_OAM_X_IBC_2_TEMP, 1834 AMDGPU_OAM_X_VDD18_VR_TEMP, 1835 AMDGPU_OAM_X_04_HBM_B_VR_TEMP, 1836 AMDGPU_OAM_X_04_HBM_D_VR_TEMP, 1837 AMDGPU_NODE_MAX_TEMP_ENTRIES = 12, 1838 }; 1839 1840 struct amdgpu_gpuboard_temp_metrics_v1_0 { 1841 struct metrics_table_header common_header; 1842 uint16_t label_version; 1843 uint16_t node_id; 1844 uint64_t accumulation_counter; 1845 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1846 uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES]; 1847 uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES]; 1848 }; 1849 1850 struct amdgpu_baseboard_temp_metrics_v1_0 { 1851 struct metrics_table_header common_header; 1852 uint16_t label_version; 1853 uint16_t node_id; 1854 uint64_t accumulation_counter; 1855 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1856 uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES]; 1857 }; 1858 1859 struct amdgpu_partition_metrics_v1_0 { 1860 struct metrics_table_header common_header; 1861 /* Current clocks (Mhz) */ 1862 uint16_t current_gfxclk[MAX_XCC]; 1863 uint16_t current_socclk[MAX_CLKS]; 1864 uint16_t current_vclk0[MAX_CLKS]; 1865 uint16_t current_dclk0[MAX_CLKS]; 1866 uint16_t current_uclk; 1867 uint16_t padding; 1868 1869 /* Utilization Instantaneous (%) */ 1870 uint32_t gfx_busy_inst[MAX_XCC]; 1871 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 1872 uint16_t vcn_busy[NUM_VCN]; 1873 /* Utilization Accumulated (%) */ 1874 uint64_t gfx_busy_acc[MAX_XCC]; 1875 /* Total App Clock Counter Accumulated */ 1876 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 1877 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 1878 uint64_t gfx_low_utilization_acc[MAX_XCC]; 1879 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 1880 }; 1881 1882 struct amdgpu_partition_metrics_v1_1 { 1883 struct metrics_table_header common_header; 1884 int attr_count; 1885 struct gpu_metrics_attr metrics_attrs[]; 1886 }; 1887 1888 enum amdgpu_xgmi_link_status { 1889 AMDGPU_XGMI_LINK_INACTIVE = 0, 1890 AMDGPU_XGMI_LINK_ACTIVE = 1, 1891 /* Status not available */ 1892 AMDGPU_XGMI_LINK_NA = 2, 1893 }; 1894 1895 struct amdgpu_gpuboard_temp_metrics_v1_1 { 1896 struct metrics_table_header common_header; 1897 int attr_count; 1898 struct gpu_metrics_attr metrics_attrs[]; 1899 }; 1900 1901 struct amdgpu_baseboard_temp_metrics_v1_1 { 1902 struct metrics_table_header common_header; 1903 int attr_count; 1904 struct gpu_metrics_attr metrics_attrs[]; 1905 }; 1906 1907 #endif 1908