1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_event_type { 34 SMU_EVENT_RESET_COMPLETE = 0, 35 }; 36 37 struct amd_vce_state { 38 /* vce clocks */ 39 u32 evclk; 40 u32 ecclk; 41 /* gpu clocks */ 42 u32 sclk; 43 u32 mclk; 44 u8 clk_idx; 45 u8 pstate; 46 }; 47 48 49 enum amd_dpm_forced_level { 50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 52 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 60 }; 61 62 enum amd_pm_state_type { 63 /* not used for dpm */ 64 POWER_STATE_TYPE_DEFAULT, 65 POWER_STATE_TYPE_POWERSAVE, 66 /* user selectable states */ 67 POWER_STATE_TYPE_BATTERY, 68 POWER_STATE_TYPE_BALANCED, 69 POWER_STATE_TYPE_PERFORMANCE, 70 /* internal states */ 71 POWER_STATE_TYPE_INTERNAL_UVD, 72 POWER_STATE_TYPE_INTERNAL_UVD_SD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD, 74 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 75 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 76 POWER_STATE_TYPE_INTERNAL_BOOT, 77 POWER_STATE_TYPE_INTERNAL_THERMAL, 78 POWER_STATE_TYPE_INTERNAL_ACPI, 79 POWER_STATE_TYPE_INTERNAL_ULV, 80 POWER_STATE_TYPE_INTERNAL_3DPERF, 81 }; 82 83 #define AMD_MAX_VCE_LEVELS 6 84 85 enum amd_vce_level { 86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 92 }; 93 94 enum amd_fan_ctrl_mode { 95 AMD_FAN_CTRL_NONE = 0, 96 AMD_FAN_CTRL_MANUAL = 1, 97 AMD_FAN_CTRL_AUTO = 2, 98 }; 99 100 enum pp_clock_type { 101 PP_SCLK, 102 PP_MCLK, 103 PP_PCIE, 104 PP_SOCCLK, 105 PP_FCLK, 106 PP_DCEFCLK, 107 PP_VCLK, 108 PP_VCLK1, 109 PP_DCLK, 110 PP_DCLK1, 111 OD_SCLK, 112 OD_MCLK, 113 OD_VDDC_CURVE, 114 OD_RANGE, 115 OD_VDDGFX_OFFSET, 116 OD_CCLK, 117 OD_FAN_CURVE, 118 OD_ACOUSTIC_LIMIT, 119 OD_ACOUSTIC_TARGET, 120 OD_FAN_TARGET_TEMPERATURE, 121 OD_FAN_MINIMUM_PWM, 122 OD_FAN_ZERO_RPM_ENABLE, 123 OD_FAN_ZERO_RPM_STOP_TEMP, 124 }; 125 126 enum amd_pp_sensors { 127 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 128 AMDGPU_PP_SENSOR_CPU_CLK, 129 AMDGPU_PP_SENSOR_VDDNB, 130 AMDGPU_PP_SENSOR_VDDGFX, 131 AMDGPU_PP_SENSOR_VDDBOARD, 132 AMDGPU_PP_SENSOR_UVD_VCLK, 133 AMDGPU_PP_SENSOR_UVD_DCLK, 134 AMDGPU_PP_SENSOR_VCE_ECCLK, 135 AMDGPU_PP_SENSOR_GPU_LOAD, 136 AMDGPU_PP_SENSOR_MEM_LOAD, 137 AMDGPU_PP_SENSOR_GFX_MCLK, 138 AMDGPU_PP_SENSOR_GPU_TEMP, 139 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 140 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 141 AMDGPU_PP_SENSOR_MEM_TEMP, 142 AMDGPU_PP_SENSOR_VCE_POWER, 143 AMDGPU_PP_SENSOR_UVD_POWER, 144 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 145 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 146 AMDGPU_PP_SENSOR_SS_APU_SHARE, 147 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 148 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 149 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 150 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 151 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 152 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 153 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 154 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 155 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 156 AMDGPU_PP_SENSOR_VCN_LOAD, 157 }; 158 159 enum amd_pp_task { 160 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 161 AMD_PP_TASK_ENABLE_USER_STATE, 162 AMD_PP_TASK_READJUST_POWER_STATE, 163 AMD_PP_TASK_COMPLETE_INIT, 164 AMD_PP_TASK_MAX 165 }; 166 167 enum PP_SMC_POWER_PROFILE { 168 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 169 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 170 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 171 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 172 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 173 PP_SMC_POWER_PROFILE_VR = 0x4, 174 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 175 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 176 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 177 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 178 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 179 PP_SMC_POWER_PROFILE_COUNT, 180 }; 181 182 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 183 184 185 186 enum { 187 PP_GROUP_UNKNOWN = 0, 188 PP_GROUP_GFX = 1, 189 PP_GROUP_SYS, 190 PP_GROUP_MAX 191 }; 192 193 enum PP_OD_DPM_TABLE_COMMAND { 194 PP_OD_EDIT_SCLK_VDDC_TABLE, 195 PP_OD_EDIT_MCLK_VDDC_TABLE, 196 PP_OD_EDIT_CCLK_VDDC_TABLE, 197 PP_OD_EDIT_VDDC_CURVE, 198 PP_OD_RESTORE_DEFAULT_TABLE, 199 PP_OD_COMMIT_DPM_TABLE, 200 PP_OD_EDIT_VDDGFX_OFFSET, 201 PP_OD_EDIT_FAN_CURVE, 202 PP_OD_EDIT_ACOUSTIC_LIMIT, 203 PP_OD_EDIT_ACOUSTIC_TARGET, 204 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 205 PP_OD_EDIT_FAN_MINIMUM_PWM, 206 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 207 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 208 }; 209 210 struct pp_states_info { 211 uint32_t nums; 212 uint32_t states[16]; 213 }; 214 215 enum PP_HWMON_TEMP { 216 PP_TEMP_EDGE = 0, 217 PP_TEMP_JUNCTION, 218 PP_TEMP_MEM, 219 PP_TEMP_MAX 220 }; 221 222 enum pp_mp1_state { 223 PP_MP1_STATE_NONE, 224 PP_MP1_STATE_SHUTDOWN, 225 PP_MP1_STATE_UNLOAD, 226 PP_MP1_STATE_RESET, 227 PP_MP1_STATE_FLR, 228 }; 229 230 enum pp_df_cstate { 231 DF_CSTATE_DISALLOW = 0, 232 DF_CSTATE_ALLOW, 233 }; 234 235 /** 236 * DOC: amdgpu_pp_power 237 * 238 * APU power is managed to system-level requirements through the PPT 239 * (package power tracking) feature. PPT is intended to limit power to the 240 * requirements of the power source and could be dynamically updated to 241 * maximize APU performance within the system power budget. 242 * 243 * Two types of power measurement can be requested, where supported, with 244 * :c:type:`enum pp_power_type <pp_power_type>`. 245 */ 246 247 /** 248 * enum pp_power_limit_level - Used to query the power limits 249 * 250 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 251 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 252 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 253 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 254 */ 255 enum pp_power_limit_level { 256 PP_PWR_LIMIT_MIN = -1, 257 PP_PWR_LIMIT_CURRENT, 258 PP_PWR_LIMIT_DEFAULT, 259 PP_PWR_LIMIT_MAX, 260 }; 261 262 /** 263 * enum pp_power_type - Used to specify the type of the requested power 264 * 265 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 266 * moving average of APU power (default ~5000 ms). 267 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 268 * where supported. 269 */ 270 enum pp_power_type { 271 PP_PWR_TYPE_SUSTAINED, 272 PP_PWR_TYPE_FAST, 273 }; 274 275 enum pp_xgmi_plpd_mode { 276 XGMI_PLPD_NONE = -1, 277 XGMI_PLPD_DISALLOW, 278 XGMI_PLPD_DEFAULT, 279 XGMI_PLPD_OPTIMIZED, 280 XGMI_PLPD_COUNT, 281 }; 282 283 enum pp_pm_policy { 284 PP_PM_POLICY_NONE = -1, 285 PP_PM_POLICY_SOC_PSTATE = 0, 286 PP_PM_POLICY_XGMI_PLPD, 287 PP_PM_POLICY_NUM, 288 }; 289 290 enum pp_policy_soc_pstate { 291 SOC_PSTATE_DEFAULT = 0, 292 SOC_PSTATE_0, 293 SOC_PSTATE_1, 294 SOC_PSTATE_2, 295 SOC_PSTAT_COUNT, 296 }; 297 298 #define PP_POLICY_MAX_LEVELS 5 299 300 #define PP_GROUP_MASK 0xF0000000 301 #define PP_GROUP_SHIFT 28 302 303 #define PP_BLOCK_MASK 0x0FFFFF00 304 #define PP_BLOCK_SHIFT 8 305 306 #define PP_BLOCK_GFX_CG 0x01 307 #define PP_BLOCK_GFX_MG 0x02 308 #define PP_BLOCK_GFX_3D 0x04 309 #define PP_BLOCK_GFX_RLC 0x08 310 #define PP_BLOCK_GFX_CP 0x10 311 #define PP_BLOCK_SYS_BIF 0x01 312 #define PP_BLOCK_SYS_MC 0x02 313 #define PP_BLOCK_SYS_ROM 0x04 314 #define PP_BLOCK_SYS_DRM 0x08 315 #define PP_BLOCK_SYS_HDP 0x10 316 #define PP_BLOCK_SYS_SDMA 0x20 317 318 #define PP_STATE_MASK 0x0000000F 319 #define PP_STATE_SHIFT 0 320 #define PP_STATE_SUPPORT_MASK 0x000000F0 321 #define PP_STATE_SUPPORT_SHIFT 0 322 323 #define PP_STATE_CG 0x01 324 #define PP_STATE_LS 0x02 325 #define PP_STATE_DS 0x04 326 #define PP_STATE_SD 0x08 327 #define PP_STATE_SUPPORT_CG 0x10 328 #define PP_STATE_SUPPORT_LS 0x20 329 #define PP_STATE_SUPPORT_DS 0x40 330 #define PP_STATE_SUPPORT_SD 0x80 331 332 #define PP_CG_MSG_ID(group, block, support, state) \ 333 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 334 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 335 336 #define XGMI_MODE_PSTATE_D3 0 337 #define XGMI_MODE_PSTATE_D0 1 338 339 #define NUM_HBM_INSTANCES 4 340 #define NUM_XGMI_LINKS 8 341 #define MAX_GFX_CLKS 8 342 #define MAX_CLKS 4 343 #define NUM_VCN 4 344 #define NUM_JPEG_ENG 32 345 #define NUM_JPEG_ENG_V1 40 346 #define MAX_XCC 8 347 #define NUM_XCP 8 348 struct seq_file; 349 enum amd_pp_clock_type; 350 struct amd_pp_simple_clock_info; 351 struct amd_pp_display_configuration; 352 struct amd_pp_clock_info; 353 struct pp_display_clock_request; 354 struct pp_clock_levels_with_voltage; 355 struct pp_clock_levels_with_latency; 356 struct amd_pp_clocks; 357 struct pp_smu_wm_range_sets; 358 struct pp_smu_nv_clock_table; 359 struct dpm_clocks; 360 361 struct amdgpu_xcp_metrics { 362 /* Utilization Instantaneous (%) */ 363 uint32_t gfx_busy_inst[MAX_XCC]; 364 uint16_t jpeg_busy[NUM_JPEG_ENG]; 365 uint16_t vcn_busy[NUM_VCN]; 366 /* Utilization Accumulated (%) */ 367 uint64_t gfx_busy_acc[MAX_XCC]; 368 }; 369 370 struct amdgpu_xcp_metrics_v1_1 { 371 /* Utilization Instantaneous (%) */ 372 uint32_t gfx_busy_inst[MAX_XCC]; 373 uint16_t jpeg_busy[NUM_JPEG_ENG]; 374 uint16_t vcn_busy[NUM_VCN]; 375 /* Utilization Accumulated (%) */ 376 uint64_t gfx_busy_acc[MAX_XCC]; 377 /* Total App Clock Counter Accumulated */ 378 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 379 }; 380 381 struct amdgpu_xcp_metrics_v1_2 { 382 /* Utilization Instantaneous (%) */ 383 uint32_t gfx_busy_inst[MAX_XCC]; 384 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 385 uint16_t vcn_busy[NUM_VCN]; 386 /* Utilization Accumulated (%) */ 387 uint64_t gfx_busy_acc[MAX_XCC]; 388 /* Total App Clock Counter Accumulated */ 389 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 390 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 391 uint64_t gfx_low_utilization_acc[MAX_XCC]; 392 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 393 }; 394 395 struct amd_pm_funcs { 396 /* export for dpm on ci and si */ 397 int (*pre_set_power_state)(void *handle); 398 int (*set_power_state)(void *handle); 399 void (*post_set_power_state)(void *handle); 400 void (*display_configuration_changed)(void *handle); 401 void (*print_power_state)(void *handle, void *ps); 402 bool (*vblank_too_short)(void *handle); 403 void (*enable_bapm)(void *handle, bool enable); 404 int (*check_state_equal)(void *handle, 405 void *cps, 406 void *rps, 407 bool *equal); 408 /* export for sysfs */ 409 int (*set_fan_control_mode)(void *handle, u32 mode); 410 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 411 int (*set_fan_speed_pwm)(void *handle, u32 speed); 412 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 413 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 414 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 415 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 416 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 417 int (*get_sclk_od)(void *handle); 418 int (*set_sclk_od)(void *handle, uint32_t value); 419 int (*get_mclk_od)(void *handle); 420 int (*set_mclk_od)(void *handle, uint32_t value); 421 int (*read_sensor)(void *handle, int idx, void *value, int *size); 422 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 423 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 424 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 425 enum amd_pm_state_type (*get_current_power_state)(void *handle); 426 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 427 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 428 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 429 int (*get_pp_table)(void *handle, char **table); 430 int (*set_pp_table)(void *handle, const char *buf, size_t size); 431 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 432 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 433 int (*pause_power_profile)(void *handle, bool pause); 434 /* export to amdgpu */ 435 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 436 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 437 enum amd_pm_state_type *user_state); 438 int (*load_firmware)(void *handle); 439 int (*wait_for_fw_loading_complete)(void *handle); 440 int (*set_powergating_by_smu)(void *handle, 441 uint32_t block_type, 442 bool gate, 443 int inst); 444 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 445 int (*set_power_limit)(void *handle, uint32_t n); 446 int (*get_power_limit)(void *handle, uint32_t *limit, 447 enum pp_power_limit_level pp_limit_level, 448 enum pp_power_type power_type); 449 int (*get_power_profile_mode)(void *handle, char *buf); 450 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 451 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 452 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 453 long *input, uint32_t size); 454 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 455 int (*smu_i2c_bus_access)(void *handle, bool acquire); 456 int (*gfx_state_change_set)(void *handle, uint32_t state); 457 /* export to DC */ 458 u32 (*get_sclk)(void *handle, bool low); 459 u32 (*get_mclk)(void *handle, bool low); 460 int (*display_configuration_change)(void *handle, 461 const struct amd_pp_display_configuration *input); 462 int (*get_display_power_level)(void *handle, 463 struct amd_pp_simple_clock_info *output); 464 int (*get_current_clocks)(void *handle, 465 struct amd_pp_clock_info *clocks); 466 int (*get_clock_by_type)(void *handle, 467 enum amd_pp_clock_type type, 468 struct amd_pp_clocks *clocks); 469 int (*get_clock_by_type_with_latency)(void *handle, 470 enum amd_pp_clock_type type, 471 struct pp_clock_levels_with_latency *clocks); 472 int (*get_clock_by_type_with_voltage)(void *handle, 473 enum amd_pp_clock_type type, 474 struct pp_clock_levels_with_voltage *clocks); 475 int (*set_watermarks_for_clocks_ranges)(void *handle, 476 void *clock_ranges); 477 int (*display_clock_voltage_request)(void *handle, 478 struct pp_display_clock_request *clock); 479 int (*get_display_mode_validation_clocks)(void *handle, 480 struct amd_pp_simple_clock_info *clocks); 481 int (*notify_smu_enable_pwe)(void *handle); 482 int (*enable_mgpu_fan_boost)(void *handle); 483 int (*set_active_display_count)(void *handle, uint32_t count); 484 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 485 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 486 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 487 int (*get_asic_baco_capability)(void *handle); 488 int (*get_asic_baco_state)(void *handle, int *state); 489 int (*set_asic_baco_state)(void *handle, int state); 490 int (*get_ppfeature_status)(void *handle, char *buf); 491 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 492 int (*asic_reset_mode_2)(void *handle); 493 int (*asic_reset_enable_gfx_features)(void *handle); 494 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 495 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 496 ssize_t (*get_gpu_metrics)(void *handle, void **table); 497 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 498 int (*set_watermarks_for_clock_ranges)(void *handle, 499 struct pp_smu_wm_range_sets *ranges); 500 int (*display_disable_memory_clock_switch)(void *handle, 501 bool disable_memory_clock_switch); 502 int (*get_max_sustainable_clocks_by_dc)(void *handle, 503 struct pp_smu_nv_clock_table *max_clocks); 504 int (*get_uclk_dpm_states)(void *handle, 505 unsigned int *clock_values_in_khz, 506 unsigned int *num_states); 507 int (*get_dpm_clock_table)(void *handle, 508 struct dpm_clocks *clock_table); 509 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 510 void (*pm_compute_clocks)(void *handle); 511 int (*notify_rlc_state)(void *handle, bool en); 512 }; 513 514 struct metrics_table_header { 515 uint16_t structure_size; 516 uint8_t format_revision; 517 uint8_t content_revision; 518 }; 519 520 /* 521 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 522 * Use gpu_metrics_v1_1 or later instead. 523 */ 524 struct gpu_metrics_v1_0 { 525 struct metrics_table_header common_header; 526 527 /* Driver attached timestamp (in ns) */ 528 uint64_t system_clock_counter; 529 530 /* Temperature */ 531 uint16_t temperature_edge; 532 uint16_t temperature_hotspot; 533 uint16_t temperature_mem; 534 uint16_t temperature_vrgfx; 535 uint16_t temperature_vrsoc; 536 uint16_t temperature_vrmem; 537 538 /* Utilization */ 539 uint16_t average_gfx_activity; 540 uint16_t average_umc_activity; // memory controller 541 uint16_t average_mm_activity; // UVD or VCN 542 543 /* Power/Energy */ 544 uint16_t average_socket_power; 545 uint32_t energy_accumulator; 546 547 /* Average clocks */ 548 uint16_t average_gfxclk_frequency; 549 uint16_t average_socclk_frequency; 550 uint16_t average_uclk_frequency; 551 uint16_t average_vclk0_frequency; 552 uint16_t average_dclk0_frequency; 553 uint16_t average_vclk1_frequency; 554 uint16_t average_dclk1_frequency; 555 556 /* Current clocks */ 557 uint16_t current_gfxclk; 558 uint16_t current_socclk; 559 uint16_t current_uclk; 560 uint16_t current_vclk0; 561 uint16_t current_dclk0; 562 uint16_t current_vclk1; 563 uint16_t current_dclk1; 564 565 /* Throttle status */ 566 uint32_t throttle_status; 567 568 /* Fans */ 569 uint16_t current_fan_speed; 570 571 /* Link width/speed */ 572 uint8_t pcie_link_width; 573 uint8_t pcie_link_speed; // in 0.1 GT/s 574 }; 575 576 struct gpu_metrics_v1_1 { 577 struct metrics_table_header common_header; 578 579 /* Temperature */ 580 uint16_t temperature_edge; 581 uint16_t temperature_hotspot; 582 uint16_t temperature_mem; 583 uint16_t temperature_vrgfx; 584 uint16_t temperature_vrsoc; 585 uint16_t temperature_vrmem; 586 587 /* Utilization */ 588 uint16_t average_gfx_activity; 589 uint16_t average_umc_activity; // memory controller 590 uint16_t average_mm_activity; // UVD or VCN 591 592 /* Power/Energy */ 593 uint16_t average_socket_power; 594 uint64_t energy_accumulator; 595 596 /* Driver attached timestamp (in ns) */ 597 uint64_t system_clock_counter; 598 599 /* Average clocks */ 600 uint16_t average_gfxclk_frequency; 601 uint16_t average_socclk_frequency; 602 uint16_t average_uclk_frequency; 603 uint16_t average_vclk0_frequency; 604 uint16_t average_dclk0_frequency; 605 uint16_t average_vclk1_frequency; 606 uint16_t average_dclk1_frequency; 607 608 /* Current clocks */ 609 uint16_t current_gfxclk; 610 uint16_t current_socclk; 611 uint16_t current_uclk; 612 uint16_t current_vclk0; 613 uint16_t current_dclk0; 614 uint16_t current_vclk1; 615 uint16_t current_dclk1; 616 617 /* Throttle status */ 618 uint32_t throttle_status; 619 620 /* Fans */ 621 uint16_t current_fan_speed; 622 623 /* Link width/speed */ 624 uint16_t pcie_link_width; 625 uint16_t pcie_link_speed; // in 0.1 GT/s 626 627 uint16_t padding; 628 629 uint32_t gfx_activity_acc; 630 uint32_t mem_activity_acc; 631 632 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 633 }; 634 635 struct gpu_metrics_v1_2 { 636 struct metrics_table_header common_header; 637 638 /* Temperature */ 639 uint16_t temperature_edge; 640 uint16_t temperature_hotspot; 641 uint16_t temperature_mem; 642 uint16_t temperature_vrgfx; 643 uint16_t temperature_vrsoc; 644 uint16_t temperature_vrmem; 645 646 /* Utilization */ 647 uint16_t average_gfx_activity; 648 uint16_t average_umc_activity; // memory controller 649 uint16_t average_mm_activity; // UVD or VCN 650 651 /* Power/Energy */ 652 uint16_t average_socket_power; 653 uint64_t energy_accumulator; 654 655 /* Driver attached timestamp (in ns) */ 656 uint64_t system_clock_counter; 657 658 /* Average clocks */ 659 uint16_t average_gfxclk_frequency; 660 uint16_t average_socclk_frequency; 661 uint16_t average_uclk_frequency; 662 uint16_t average_vclk0_frequency; 663 uint16_t average_dclk0_frequency; 664 uint16_t average_vclk1_frequency; 665 uint16_t average_dclk1_frequency; 666 667 /* Current clocks */ 668 uint16_t current_gfxclk; 669 uint16_t current_socclk; 670 uint16_t current_uclk; 671 uint16_t current_vclk0; 672 uint16_t current_dclk0; 673 uint16_t current_vclk1; 674 uint16_t current_dclk1; 675 676 /* Throttle status (ASIC dependent) */ 677 uint32_t throttle_status; 678 679 /* Fans */ 680 uint16_t current_fan_speed; 681 682 /* Link width/speed */ 683 uint16_t pcie_link_width; 684 uint16_t pcie_link_speed; // in 0.1 GT/s 685 686 uint16_t padding; 687 688 uint32_t gfx_activity_acc; 689 uint32_t mem_activity_acc; 690 691 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 692 693 /* PMFW attached timestamp (10ns resolution) */ 694 uint64_t firmware_timestamp; 695 }; 696 697 struct gpu_metrics_v1_3 { 698 struct metrics_table_header common_header; 699 700 /* Temperature */ 701 uint16_t temperature_edge; 702 uint16_t temperature_hotspot; 703 uint16_t temperature_mem; 704 uint16_t temperature_vrgfx; 705 uint16_t temperature_vrsoc; 706 uint16_t temperature_vrmem; 707 708 /* Utilization */ 709 uint16_t average_gfx_activity; 710 uint16_t average_umc_activity; // memory controller 711 uint16_t average_mm_activity; // UVD or VCN 712 713 /* Power/Energy */ 714 uint16_t average_socket_power; 715 uint64_t energy_accumulator; 716 717 /* Driver attached timestamp (in ns) */ 718 uint64_t system_clock_counter; 719 720 /* Average clocks */ 721 uint16_t average_gfxclk_frequency; 722 uint16_t average_socclk_frequency; 723 uint16_t average_uclk_frequency; 724 uint16_t average_vclk0_frequency; 725 uint16_t average_dclk0_frequency; 726 uint16_t average_vclk1_frequency; 727 uint16_t average_dclk1_frequency; 728 729 /* Current clocks */ 730 uint16_t current_gfxclk; 731 uint16_t current_socclk; 732 uint16_t current_uclk; 733 uint16_t current_vclk0; 734 uint16_t current_dclk0; 735 uint16_t current_vclk1; 736 uint16_t current_dclk1; 737 738 /* Throttle status */ 739 uint32_t throttle_status; 740 741 /* Fans */ 742 uint16_t current_fan_speed; 743 744 /* Link width/speed */ 745 uint16_t pcie_link_width; 746 uint16_t pcie_link_speed; // in 0.1 GT/s 747 748 uint16_t padding; 749 750 uint32_t gfx_activity_acc; 751 uint32_t mem_activity_acc; 752 753 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 754 755 /* PMFW attached timestamp (10ns resolution) */ 756 uint64_t firmware_timestamp; 757 758 /* Voltage (mV) */ 759 uint16_t voltage_soc; 760 uint16_t voltage_gfx; 761 uint16_t voltage_mem; 762 763 uint16_t padding1; 764 765 /* Throttle status (ASIC independent) */ 766 uint64_t indep_throttle_status; 767 }; 768 769 struct gpu_metrics_v1_4 { 770 struct metrics_table_header common_header; 771 772 /* Temperature (Celsius) */ 773 uint16_t temperature_hotspot; 774 uint16_t temperature_mem; 775 uint16_t temperature_vrsoc; 776 777 /* Power (Watts) */ 778 uint16_t curr_socket_power; 779 780 /* Utilization (%) */ 781 uint16_t average_gfx_activity; 782 uint16_t average_umc_activity; // memory controller 783 uint16_t vcn_activity[NUM_VCN]; 784 785 /* Energy (15.259uJ (2^-16) units) */ 786 uint64_t energy_accumulator; 787 788 /* Driver attached timestamp (in ns) */ 789 uint64_t system_clock_counter; 790 791 /* Throttle status */ 792 uint32_t throttle_status; 793 794 /* Clock Lock Status. Each bit corresponds to clock instance */ 795 uint32_t gfxclk_lock_status; 796 797 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 798 uint16_t pcie_link_width; 799 uint16_t pcie_link_speed; 800 801 /* XGMI bus width and bitrate (in Gbps) */ 802 uint16_t xgmi_link_width; 803 uint16_t xgmi_link_speed; 804 805 /* Utilization Accumulated (%) */ 806 uint32_t gfx_activity_acc; 807 uint32_t mem_activity_acc; 808 809 /*PCIE accumulated bandwidth (GB/sec) */ 810 uint64_t pcie_bandwidth_acc; 811 812 /*PCIE instantaneous bandwidth (GB/sec) */ 813 uint64_t pcie_bandwidth_inst; 814 815 /* PCIE L0 to recovery state transition accumulated count */ 816 uint64_t pcie_l0_to_recov_count_acc; 817 818 /* PCIE replay accumulated count */ 819 uint64_t pcie_replay_count_acc; 820 821 /* PCIE replay rollover accumulated count */ 822 uint64_t pcie_replay_rover_count_acc; 823 824 /* XGMI accumulated data transfer size(KiloBytes) */ 825 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 826 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 827 828 /* PMFW attached timestamp (10ns resolution) */ 829 uint64_t firmware_timestamp; 830 831 /* Current clocks (Mhz) */ 832 uint16_t current_gfxclk[MAX_GFX_CLKS]; 833 uint16_t current_socclk[MAX_CLKS]; 834 uint16_t current_vclk0[MAX_CLKS]; 835 uint16_t current_dclk0[MAX_CLKS]; 836 uint16_t current_uclk; 837 838 uint16_t padding; 839 }; 840 841 struct gpu_metrics_v1_5 { 842 struct metrics_table_header common_header; 843 844 /* Temperature (Celsius) */ 845 uint16_t temperature_hotspot; 846 uint16_t temperature_mem; 847 uint16_t temperature_vrsoc; 848 849 /* Power (Watts) */ 850 uint16_t curr_socket_power; 851 852 /* Utilization (%) */ 853 uint16_t average_gfx_activity; 854 uint16_t average_umc_activity; // memory controller 855 uint16_t vcn_activity[NUM_VCN]; 856 uint16_t jpeg_activity[NUM_JPEG_ENG]; 857 858 /* Energy (15.259uJ (2^-16) units) */ 859 uint64_t energy_accumulator; 860 861 /* Driver attached timestamp (in ns) */ 862 uint64_t system_clock_counter; 863 864 /* Throttle status */ 865 uint32_t throttle_status; 866 867 /* Clock Lock Status. Each bit corresponds to clock instance */ 868 uint32_t gfxclk_lock_status; 869 870 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 871 uint16_t pcie_link_width; 872 uint16_t pcie_link_speed; 873 874 /* XGMI bus width and bitrate (in Gbps) */ 875 uint16_t xgmi_link_width; 876 uint16_t xgmi_link_speed; 877 878 /* Utilization Accumulated (%) */ 879 uint32_t gfx_activity_acc; 880 uint32_t mem_activity_acc; 881 882 /*PCIE accumulated bandwidth (GB/sec) */ 883 uint64_t pcie_bandwidth_acc; 884 885 /*PCIE instantaneous bandwidth (GB/sec) */ 886 uint64_t pcie_bandwidth_inst; 887 888 /* PCIE L0 to recovery state transition accumulated count */ 889 uint64_t pcie_l0_to_recov_count_acc; 890 891 /* PCIE replay accumulated count */ 892 uint64_t pcie_replay_count_acc; 893 894 /* PCIE replay rollover accumulated count */ 895 uint64_t pcie_replay_rover_count_acc; 896 897 /* PCIE NAK sent accumulated count */ 898 uint32_t pcie_nak_sent_count_acc; 899 900 /* PCIE NAK received accumulated count */ 901 uint32_t pcie_nak_rcvd_count_acc; 902 903 /* XGMI accumulated data transfer size(KiloBytes) */ 904 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 905 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 906 907 /* PMFW attached timestamp (10ns resolution) */ 908 uint64_t firmware_timestamp; 909 910 /* Current clocks (Mhz) */ 911 uint16_t current_gfxclk[MAX_GFX_CLKS]; 912 uint16_t current_socclk[MAX_CLKS]; 913 uint16_t current_vclk0[MAX_CLKS]; 914 uint16_t current_dclk0[MAX_CLKS]; 915 uint16_t current_uclk; 916 917 uint16_t padding; 918 }; 919 920 struct gpu_metrics_v1_6 { 921 struct metrics_table_header common_header; 922 923 /* Temperature (Celsius) */ 924 uint16_t temperature_hotspot; 925 uint16_t temperature_mem; 926 uint16_t temperature_vrsoc; 927 928 /* Power (Watts) */ 929 uint16_t curr_socket_power; 930 931 /* Utilization (%) */ 932 uint16_t average_gfx_activity; 933 uint16_t average_umc_activity; // memory controller 934 935 /* Energy (15.259uJ (2^-16) units) */ 936 uint64_t energy_accumulator; 937 938 /* Driver attached timestamp (in ns) */ 939 uint64_t system_clock_counter; 940 941 /* Accumulation cycle counter */ 942 uint32_t accumulation_counter; 943 944 /* Accumulated throttler residencies */ 945 uint32_t prochot_residency_acc; 946 uint32_t ppt_residency_acc; 947 uint32_t socket_thm_residency_acc; 948 uint32_t vr_thm_residency_acc; 949 uint32_t hbm_thm_residency_acc; 950 951 /* Clock Lock Status. Each bit corresponds to clock instance */ 952 uint32_t gfxclk_lock_status; 953 954 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 955 uint16_t pcie_link_width; 956 uint16_t pcie_link_speed; 957 958 /* XGMI bus width and bitrate (in Gbps) */ 959 uint16_t xgmi_link_width; 960 uint16_t xgmi_link_speed; 961 962 /* Utilization Accumulated (%) */ 963 uint32_t gfx_activity_acc; 964 uint32_t mem_activity_acc; 965 966 /*PCIE accumulated bandwidth (GB/sec) */ 967 uint64_t pcie_bandwidth_acc; 968 969 /*PCIE instantaneous bandwidth (GB/sec) */ 970 uint64_t pcie_bandwidth_inst; 971 972 /* PCIE L0 to recovery state transition accumulated count */ 973 uint64_t pcie_l0_to_recov_count_acc; 974 975 /* PCIE replay accumulated count */ 976 uint64_t pcie_replay_count_acc; 977 978 /* PCIE replay rollover accumulated count */ 979 uint64_t pcie_replay_rover_count_acc; 980 981 /* PCIE NAK sent accumulated count */ 982 uint32_t pcie_nak_sent_count_acc; 983 984 /* PCIE NAK received accumulated count */ 985 uint32_t pcie_nak_rcvd_count_acc; 986 987 /* XGMI accumulated data transfer size(KiloBytes) */ 988 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 989 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 990 991 /* PMFW attached timestamp (10ns resolution) */ 992 uint64_t firmware_timestamp; 993 994 /* Current clocks (Mhz) */ 995 uint16_t current_gfxclk[MAX_GFX_CLKS]; 996 uint16_t current_socclk[MAX_CLKS]; 997 uint16_t current_vclk0[MAX_CLKS]; 998 uint16_t current_dclk0[MAX_CLKS]; 999 uint16_t current_uclk; 1000 1001 /* Number of current partition */ 1002 uint16_t num_partition; 1003 1004 /* XCP metrics stats */ 1005 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1006 1007 /* PCIE other end recovery counter */ 1008 uint32_t pcie_lc_perf_other_end_recovery; 1009 }; 1010 1011 struct gpu_metrics_v1_7 { 1012 struct metrics_table_header common_header; 1013 1014 /* Temperature (Celsius) */ 1015 uint16_t temperature_hotspot; 1016 uint16_t temperature_mem; 1017 uint16_t temperature_vrsoc; 1018 1019 /* Power (Watts) */ 1020 uint16_t curr_socket_power; 1021 1022 /* Utilization (%) */ 1023 uint16_t average_gfx_activity; 1024 uint16_t average_umc_activity; // memory controller 1025 1026 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1027 uint64_t mem_max_bandwidth; 1028 1029 /* Energy (15.259uJ (2^-16) units) */ 1030 uint64_t energy_accumulator; 1031 1032 /* Driver attached timestamp (in ns) */ 1033 uint64_t system_clock_counter; 1034 1035 /* Accumulation cycle counter */ 1036 uint32_t accumulation_counter; 1037 1038 /* Accumulated throttler residencies */ 1039 uint32_t prochot_residency_acc; 1040 uint32_t ppt_residency_acc; 1041 uint32_t socket_thm_residency_acc; 1042 uint32_t vr_thm_residency_acc; 1043 uint32_t hbm_thm_residency_acc; 1044 1045 /* Clock Lock Status. Each bit corresponds to clock instance */ 1046 uint32_t gfxclk_lock_status; 1047 1048 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1049 uint16_t pcie_link_width; 1050 uint16_t pcie_link_speed; 1051 1052 /* XGMI bus width and bitrate (in Gbps) */ 1053 uint16_t xgmi_link_width; 1054 uint16_t xgmi_link_speed; 1055 1056 /* Utilization Accumulated (%) */ 1057 uint32_t gfx_activity_acc; 1058 uint32_t mem_activity_acc; 1059 1060 /*PCIE accumulated bandwidth (GB/sec) */ 1061 uint64_t pcie_bandwidth_acc; 1062 1063 /*PCIE instantaneous bandwidth (GB/sec) */ 1064 uint64_t pcie_bandwidth_inst; 1065 1066 /* PCIE L0 to recovery state transition accumulated count */ 1067 uint64_t pcie_l0_to_recov_count_acc; 1068 1069 /* PCIE replay accumulated count */ 1070 uint64_t pcie_replay_count_acc; 1071 1072 /* PCIE replay rollover accumulated count */ 1073 uint64_t pcie_replay_rover_count_acc; 1074 1075 /* PCIE NAK sent accumulated count */ 1076 uint32_t pcie_nak_sent_count_acc; 1077 1078 /* PCIE NAK received accumulated count */ 1079 uint32_t pcie_nak_rcvd_count_acc; 1080 1081 /* XGMI accumulated data transfer size(KiloBytes) */ 1082 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1083 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1084 1085 /* XGMI link status(active/inactive) */ 1086 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1087 1088 uint16_t padding; 1089 1090 /* PMFW attached timestamp (10ns resolution) */ 1091 uint64_t firmware_timestamp; 1092 1093 /* Current clocks (Mhz) */ 1094 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1095 uint16_t current_socclk[MAX_CLKS]; 1096 uint16_t current_vclk0[MAX_CLKS]; 1097 uint16_t current_dclk0[MAX_CLKS]; 1098 uint16_t current_uclk; 1099 1100 /* Number of current partition */ 1101 uint16_t num_partition; 1102 1103 /* XCP metrics stats */ 1104 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1105 1106 /* PCIE other end recovery counter */ 1107 uint32_t pcie_lc_perf_other_end_recovery; 1108 }; 1109 1110 struct gpu_metrics_v1_8 { 1111 struct metrics_table_header common_header; 1112 1113 /* Temperature (Celsius) */ 1114 uint16_t temperature_hotspot; 1115 uint16_t temperature_mem; 1116 uint16_t temperature_vrsoc; 1117 1118 /* Power (Watts) */ 1119 uint16_t curr_socket_power; 1120 1121 /* Utilization (%) */ 1122 uint16_t average_gfx_activity; 1123 uint16_t average_umc_activity; // memory controller 1124 1125 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1126 uint64_t mem_max_bandwidth; 1127 1128 /* Energy (15.259uJ (2^-16) units) */ 1129 uint64_t energy_accumulator; 1130 1131 /* Driver attached timestamp (in ns) */ 1132 uint64_t system_clock_counter; 1133 1134 /* Accumulation cycle counter */ 1135 uint32_t accumulation_counter; 1136 1137 /* Accumulated throttler residencies */ 1138 uint32_t prochot_residency_acc; 1139 uint32_t ppt_residency_acc; 1140 uint32_t socket_thm_residency_acc; 1141 uint32_t vr_thm_residency_acc; 1142 uint32_t hbm_thm_residency_acc; 1143 1144 /* Clock Lock Status. Each bit corresponds to clock instance */ 1145 uint32_t gfxclk_lock_status; 1146 1147 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1148 uint16_t pcie_link_width; 1149 uint16_t pcie_link_speed; 1150 1151 /* XGMI bus width and bitrate (in Gbps) */ 1152 uint16_t xgmi_link_width; 1153 uint16_t xgmi_link_speed; 1154 1155 /* Utilization Accumulated (%) */ 1156 uint32_t gfx_activity_acc; 1157 uint32_t mem_activity_acc; 1158 1159 /*PCIE accumulated bandwidth (GB/sec) */ 1160 uint64_t pcie_bandwidth_acc; 1161 1162 /*PCIE instantaneous bandwidth (GB/sec) */ 1163 uint64_t pcie_bandwidth_inst; 1164 1165 /* PCIE L0 to recovery state transition accumulated count */ 1166 uint64_t pcie_l0_to_recov_count_acc; 1167 1168 /* PCIE replay accumulated count */ 1169 uint64_t pcie_replay_count_acc; 1170 1171 /* PCIE replay rollover accumulated count */ 1172 uint64_t pcie_replay_rover_count_acc; 1173 1174 /* PCIE NAK sent accumulated count */ 1175 uint32_t pcie_nak_sent_count_acc; 1176 1177 /* PCIE NAK received accumulated count */ 1178 uint32_t pcie_nak_rcvd_count_acc; 1179 1180 /* XGMI accumulated data transfer size(KiloBytes) */ 1181 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1182 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1183 1184 /* XGMI link status(active/inactive) */ 1185 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1186 1187 uint16_t padding; 1188 1189 /* PMFW attached timestamp (10ns resolution) */ 1190 uint64_t firmware_timestamp; 1191 1192 /* Current clocks (Mhz) */ 1193 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1194 uint16_t current_socclk[MAX_CLKS]; 1195 uint16_t current_vclk0[MAX_CLKS]; 1196 uint16_t current_dclk0[MAX_CLKS]; 1197 uint16_t current_uclk; 1198 1199 /* Number of current partition */ 1200 uint16_t num_partition; 1201 1202 /* XCP metrics stats */ 1203 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1204 1205 /* PCIE other end recovery counter */ 1206 uint32_t pcie_lc_perf_other_end_recovery; 1207 }; 1208 1209 /* 1210 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1211 * Use gpu_metrics_v2_1 or later instead. 1212 */ 1213 struct gpu_metrics_v2_0 { 1214 struct metrics_table_header common_header; 1215 1216 /* Driver attached timestamp (in ns) */ 1217 uint64_t system_clock_counter; 1218 1219 /* Temperature */ 1220 uint16_t temperature_gfx; // gfx temperature on APUs 1221 uint16_t temperature_soc; // soc temperature on APUs 1222 uint16_t temperature_core[8]; // CPU core temperature on APUs 1223 uint16_t temperature_l3[2]; 1224 1225 /* Utilization */ 1226 uint16_t average_gfx_activity; 1227 uint16_t average_mm_activity; // UVD or VCN 1228 1229 /* Power/Energy */ 1230 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1231 uint16_t average_cpu_power; 1232 uint16_t average_soc_power; 1233 uint16_t average_gfx_power; 1234 uint16_t average_core_power[8]; // CPU core power on APUs 1235 1236 /* Average clocks */ 1237 uint16_t average_gfxclk_frequency; 1238 uint16_t average_socclk_frequency; 1239 uint16_t average_uclk_frequency; 1240 uint16_t average_fclk_frequency; 1241 uint16_t average_vclk_frequency; 1242 uint16_t average_dclk_frequency; 1243 1244 /* Current clocks */ 1245 uint16_t current_gfxclk; 1246 uint16_t current_socclk; 1247 uint16_t current_uclk; 1248 uint16_t current_fclk; 1249 uint16_t current_vclk; 1250 uint16_t current_dclk; 1251 uint16_t current_coreclk[8]; // CPU core clocks 1252 uint16_t current_l3clk[2]; 1253 1254 /* Throttle status */ 1255 uint32_t throttle_status; 1256 1257 /* Fans */ 1258 uint16_t fan_pwm; 1259 1260 uint16_t padding; 1261 }; 1262 1263 struct gpu_metrics_v2_1 { 1264 struct metrics_table_header common_header; 1265 1266 /* Temperature */ 1267 uint16_t temperature_gfx; // gfx temperature on APUs 1268 uint16_t temperature_soc; // soc temperature on APUs 1269 uint16_t temperature_core[8]; // CPU core temperature on APUs 1270 uint16_t temperature_l3[2]; 1271 1272 /* Utilization */ 1273 uint16_t average_gfx_activity; 1274 uint16_t average_mm_activity; // UVD or VCN 1275 1276 /* Driver attached timestamp (in ns) */ 1277 uint64_t system_clock_counter; 1278 1279 /* Power/Energy */ 1280 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1281 uint16_t average_cpu_power; 1282 uint16_t average_soc_power; 1283 uint16_t average_gfx_power; 1284 uint16_t average_core_power[8]; // CPU core power on APUs 1285 1286 /* Average clocks */ 1287 uint16_t average_gfxclk_frequency; 1288 uint16_t average_socclk_frequency; 1289 uint16_t average_uclk_frequency; 1290 uint16_t average_fclk_frequency; 1291 uint16_t average_vclk_frequency; 1292 uint16_t average_dclk_frequency; 1293 1294 /* Current clocks */ 1295 uint16_t current_gfxclk; 1296 uint16_t current_socclk; 1297 uint16_t current_uclk; 1298 uint16_t current_fclk; 1299 uint16_t current_vclk; 1300 uint16_t current_dclk; 1301 uint16_t current_coreclk[8]; // CPU core clocks 1302 uint16_t current_l3clk[2]; 1303 1304 /* Throttle status */ 1305 uint32_t throttle_status; 1306 1307 /* Fans */ 1308 uint16_t fan_pwm; 1309 1310 uint16_t padding[3]; 1311 }; 1312 1313 struct gpu_metrics_v2_2 { 1314 struct metrics_table_header common_header; 1315 1316 /* Temperature */ 1317 uint16_t temperature_gfx; // gfx temperature on APUs 1318 uint16_t temperature_soc; // soc temperature on APUs 1319 uint16_t temperature_core[8]; // CPU core temperature on APUs 1320 uint16_t temperature_l3[2]; 1321 1322 /* Utilization */ 1323 uint16_t average_gfx_activity; 1324 uint16_t average_mm_activity; // UVD or VCN 1325 1326 /* Driver attached timestamp (in ns) */ 1327 uint64_t system_clock_counter; 1328 1329 /* Power/Energy */ 1330 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1331 uint16_t average_cpu_power; 1332 uint16_t average_soc_power; 1333 uint16_t average_gfx_power; 1334 uint16_t average_core_power[8]; // CPU core power on APUs 1335 1336 /* Average clocks */ 1337 uint16_t average_gfxclk_frequency; 1338 uint16_t average_socclk_frequency; 1339 uint16_t average_uclk_frequency; 1340 uint16_t average_fclk_frequency; 1341 uint16_t average_vclk_frequency; 1342 uint16_t average_dclk_frequency; 1343 1344 /* Current clocks */ 1345 uint16_t current_gfxclk; 1346 uint16_t current_socclk; 1347 uint16_t current_uclk; 1348 uint16_t current_fclk; 1349 uint16_t current_vclk; 1350 uint16_t current_dclk; 1351 uint16_t current_coreclk[8]; // CPU core clocks 1352 uint16_t current_l3clk[2]; 1353 1354 /* Throttle status (ASIC dependent) */ 1355 uint32_t throttle_status; 1356 1357 /* Fans */ 1358 uint16_t fan_pwm; 1359 1360 uint16_t padding[3]; 1361 1362 /* Throttle status (ASIC independent) */ 1363 uint64_t indep_throttle_status; 1364 }; 1365 1366 struct gpu_metrics_v2_3 { 1367 struct metrics_table_header common_header; 1368 1369 /* Temperature */ 1370 uint16_t temperature_gfx; // gfx temperature on APUs 1371 uint16_t temperature_soc; // soc temperature on APUs 1372 uint16_t temperature_core[8]; // CPU core temperature on APUs 1373 uint16_t temperature_l3[2]; 1374 1375 /* Utilization */ 1376 uint16_t average_gfx_activity; 1377 uint16_t average_mm_activity; // UVD or VCN 1378 1379 /* Driver attached timestamp (in ns) */ 1380 uint64_t system_clock_counter; 1381 1382 /* Power/Energy */ 1383 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1384 uint16_t average_cpu_power; 1385 uint16_t average_soc_power; 1386 uint16_t average_gfx_power; 1387 uint16_t average_core_power[8]; // CPU core power on APUs 1388 1389 /* Average clocks */ 1390 uint16_t average_gfxclk_frequency; 1391 uint16_t average_socclk_frequency; 1392 uint16_t average_uclk_frequency; 1393 uint16_t average_fclk_frequency; 1394 uint16_t average_vclk_frequency; 1395 uint16_t average_dclk_frequency; 1396 1397 /* Current clocks */ 1398 uint16_t current_gfxclk; 1399 uint16_t current_socclk; 1400 uint16_t current_uclk; 1401 uint16_t current_fclk; 1402 uint16_t current_vclk; 1403 uint16_t current_dclk; 1404 uint16_t current_coreclk[8]; // CPU core clocks 1405 uint16_t current_l3clk[2]; 1406 1407 /* Throttle status (ASIC dependent) */ 1408 uint32_t throttle_status; 1409 1410 /* Fans */ 1411 uint16_t fan_pwm; 1412 1413 uint16_t padding[3]; 1414 1415 /* Throttle status (ASIC independent) */ 1416 uint64_t indep_throttle_status; 1417 1418 /* Average Temperature */ 1419 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1420 uint16_t average_temperature_soc; // average soc temperature on APUs 1421 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1422 uint16_t average_temperature_l3[2]; 1423 }; 1424 1425 struct gpu_metrics_v2_4 { 1426 struct metrics_table_header common_header; 1427 1428 /* Temperature (unit: centi-Celsius) */ 1429 uint16_t temperature_gfx; 1430 uint16_t temperature_soc; 1431 uint16_t temperature_core[8]; 1432 uint16_t temperature_l3[2]; 1433 1434 /* Utilization (unit: centi) */ 1435 uint16_t average_gfx_activity; 1436 uint16_t average_mm_activity; 1437 1438 /* Driver attached timestamp (in ns) */ 1439 uint64_t system_clock_counter; 1440 1441 /* Power/Energy (unit: mW) */ 1442 uint16_t average_socket_power; 1443 uint16_t average_cpu_power; 1444 uint16_t average_soc_power; 1445 uint16_t average_gfx_power; 1446 uint16_t average_core_power[8]; 1447 1448 /* Average clocks (unit: MHz) */ 1449 uint16_t average_gfxclk_frequency; 1450 uint16_t average_socclk_frequency; 1451 uint16_t average_uclk_frequency; 1452 uint16_t average_fclk_frequency; 1453 uint16_t average_vclk_frequency; 1454 uint16_t average_dclk_frequency; 1455 1456 /* Current clocks (unit: MHz) */ 1457 uint16_t current_gfxclk; 1458 uint16_t current_socclk; 1459 uint16_t current_uclk; 1460 uint16_t current_fclk; 1461 uint16_t current_vclk; 1462 uint16_t current_dclk; 1463 uint16_t current_coreclk[8]; 1464 uint16_t current_l3clk[2]; 1465 1466 /* Throttle status (ASIC dependent) */ 1467 uint32_t throttle_status; 1468 1469 /* Fans */ 1470 uint16_t fan_pwm; 1471 1472 uint16_t padding[3]; 1473 1474 /* Throttle status (ASIC independent) */ 1475 uint64_t indep_throttle_status; 1476 1477 /* Average Temperature (unit: centi-Celsius) */ 1478 uint16_t average_temperature_gfx; 1479 uint16_t average_temperature_soc; 1480 uint16_t average_temperature_core[8]; 1481 uint16_t average_temperature_l3[2]; 1482 1483 /* Power/Voltage (unit: mV) */ 1484 uint16_t average_cpu_voltage; 1485 uint16_t average_soc_voltage; 1486 uint16_t average_gfx_voltage; 1487 1488 /* Power/Current (unit: mA) */ 1489 uint16_t average_cpu_current; 1490 uint16_t average_soc_current; 1491 uint16_t average_gfx_current; 1492 }; 1493 1494 struct gpu_metrics_v3_0 { 1495 struct metrics_table_header common_header; 1496 1497 /* Temperature */ 1498 /* gfx temperature on APUs */ 1499 uint16_t temperature_gfx; 1500 /* soc temperature on APUs */ 1501 uint16_t temperature_soc; 1502 /* CPU core temperature on APUs */ 1503 uint16_t temperature_core[16]; 1504 /* skin temperature on APUs */ 1505 uint16_t temperature_skin; 1506 1507 /* Utilization */ 1508 /* time filtered GFX busy % [0-100] */ 1509 uint16_t average_gfx_activity; 1510 /* time filtered VCN busy % [0-100] */ 1511 uint16_t average_vcn_activity; 1512 /* time filtered IPU per-column busy % [0-100] */ 1513 uint16_t average_ipu_activity[8]; 1514 /* time filtered per-core C0 residency % [0-100]*/ 1515 uint16_t average_core_c0_activity[16]; 1516 /* time filtered DRAM read bandwidth [MB/sec] */ 1517 uint16_t average_dram_reads; 1518 /* time filtered DRAM write bandwidth [MB/sec] */ 1519 uint16_t average_dram_writes; 1520 /* time filtered IPU read bandwidth [MB/sec] */ 1521 uint16_t average_ipu_reads; 1522 /* time filtered IPU write bandwidth [MB/sec] */ 1523 uint16_t average_ipu_writes; 1524 1525 /* Driver attached timestamp (in ns) */ 1526 uint64_t system_clock_counter; 1527 1528 /* Power/Energy */ 1529 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1530 uint32_t average_socket_power; 1531 /* time filtered IPU power [mW] */ 1532 uint16_t average_ipu_power; 1533 /* time filtered APU power [mW] */ 1534 uint32_t average_apu_power; 1535 /* time filtered GFX power [mW] */ 1536 uint32_t average_gfx_power; 1537 /* time filtered dGPU power [mW] */ 1538 uint32_t average_dgpu_power; 1539 /* time filtered sum of core power across all cores in the socket [mW] */ 1540 uint32_t average_all_core_power; 1541 /* calculated core power [mW] */ 1542 uint16_t average_core_power[16]; 1543 /* time filtered total system power [mW] */ 1544 uint16_t average_sys_power; 1545 /* maximum IRM defined STAPM power limit [mW] */ 1546 uint16_t stapm_power_limit; 1547 /* time filtered STAPM power limit [mW] */ 1548 uint16_t current_stapm_power_limit; 1549 1550 /* time filtered clocks [MHz] */ 1551 uint16_t average_gfxclk_frequency; 1552 uint16_t average_socclk_frequency; 1553 uint16_t average_vpeclk_frequency; 1554 uint16_t average_ipuclk_frequency; 1555 uint16_t average_fclk_frequency; 1556 uint16_t average_vclk_frequency; 1557 uint16_t average_uclk_frequency; 1558 uint16_t average_mpipu_frequency; 1559 1560 /* Current clocks */ 1561 /* target core frequency [MHz] */ 1562 uint16_t current_coreclk[16]; 1563 /* CCLK frequency limit enforced on classic cores [MHz] */ 1564 uint16_t current_core_maxfreq; 1565 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1566 uint16_t current_gfx_maxfreq; 1567 1568 /* Throttle Residency (ASIC dependent) */ 1569 uint32_t throttle_residency_prochot; 1570 uint32_t throttle_residency_spl; 1571 uint32_t throttle_residency_fppt; 1572 uint32_t throttle_residency_sppt; 1573 uint32_t throttle_residency_thm_core; 1574 uint32_t throttle_residency_thm_gfx; 1575 uint32_t throttle_residency_thm_soc; 1576 1577 /* Metrics table alpha filter time constant [us] */ 1578 uint32_t time_filter_alphavalue; 1579 }; 1580 1581 struct amdgpu_pmmetrics_header { 1582 uint16_t structure_size; 1583 uint16_t pad; 1584 uint32_t mp1_ip_discovery_version; 1585 uint32_t pmfw_version; 1586 uint32_t pmmetrics_version; 1587 }; 1588 1589 struct amdgpu_pm_metrics { 1590 struct amdgpu_pmmetrics_header common_header; 1591 1592 uint8_t data[]; 1593 }; 1594 1595 #endif 1596