1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_temp_metric_type { 34 SMU_TEMP_METRIC_BASEBOARD, 35 SMU_TEMP_METRIC_GPUBOARD, 36 SMU_TEMP_METRIC_MAX, 37 }; 38 39 enum smu_event_type { 40 SMU_EVENT_RESET_COMPLETE = 0, 41 }; 42 43 struct amd_vce_state { 44 /* vce clocks */ 45 u32 evclk; 46 u32 ecclk; 47 /* gpu clocks */ 48 u32 sclk; 49 u32 mclk; 50 u8 clk_idx; 51 u8 pstate; 52 }; 53 54 55 enum amd_dpm_forced_level { 56 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 57 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 58 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 59 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 60 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 61 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 62 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 63 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 64 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 65 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 66 }; 67 68 enum amd_pm_state_type { 69 /* not used for dpm */ 70 POWER_STATE_TYPE_DEFAULT, 71 POWER_STATE_TYPE_POWERSAVE, 72 /* user selectable states */ 73 POWER_STATE_TYPE_BATTERY, 74 POWER_STATE_TYPE_BALANCED, 75 POWER_STATE_TYPE_PERFORMANCE, 76 /* internal states */ 77 POWER_STATE_TYPE_INTERNAL_UVD, 78 POWER_STATE_TYPE_INTERNAL_UVD_SD, 79 POWER_STATE_TYPE_INTERNAL_UVD_HD, 80 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 81 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 82 POWER_STATE_TYPE_INTERNAL_BOOT, 83 POWER_STATE_TYPE_INTERNAL_THERMAL, 84 POWER_STATE_TYPE_INTERNAL_ACPI, 85 POWER_STATE_TYPE_INTERNAL_ULV, 86 POWER_STATE_TYPE_INTERNAL_3DPERF, 87 }; 88 89 #define AMD_MAX_VCE_LEVELS 6 90 91 enum amd_vce_level { 92 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 93 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 94 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 95 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 96 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 97 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 98 }; 99 100 enum amd_fan_ctrl_mode { 101 AMD_FAN_CTRL_NONE = 0, 102 AMD_FAN_CTRL_MANUAL = 1, 103 AMD_FAN_CTRL_AUTO = 2, 104 }; 105 106 enum pp_clock_type { 107 PP_SCLK, 108 PP_MCLK, 109 PP_PCIE, 110 PP_SOCCLK, 111 PP_FCLK, 112 PP_DCEFCLK, 113 PP_VCLK, 114 PP_VCLK1, 115 PP_DCLK, 116 PP_DCLK1, 117 PP_ISPICLK, 118 PP_ISPXCLK, 119 OD_SCLK, 120 OD_MCLK, 121 OD_VDDC_CURVE, 122 OD_RANGE, 123 OD_VDDGFX_OFFSET, 124 OD_CCLK, 125 OD_FAN_CURVE, 126 OD_ACOUSTIC_LIMIT, 127 OD_ACOUSTIC_TARGET, 128 OD_FAN_TARGET_TEMPERATURE, 129 OD_FAN_MINIMUM_PWM, 130 OD_FAN_ZERO_RPM_ENABLE, 131 OD_FAN_ZERO_RPM_STOP_TEMP, 132 }; 133 134 enum amd_pp_sensors { 135 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 136 AMDGPU_PP_SENSOR_CPU_CLK, 137 AMDGPU_PP_SENSOR_VDDNB, 138 AMDGPU_PP_SENSOR_VDDGFX, 139 AMDGPU_PP_SENSOR_VDDBOARD, 140 AMDGPU_PP_SENSOR_UVD_VCLK, 141 AMDGPU_PP_SENSOR_UVD_DCLK, 142 AMDGPU_PP_SENSOR_VCE_ECCLK, 143 AMDGPU_PP_SENSOR_GPU_LOAD, 144 AMDGPU_PP_SENSOR_MEM_LOAD, 145 AMDGPU_PP_SENSOR_GFX_MCLK, 146 AMDGPU_PP_SENSOR_GPU_TEMP, 147 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 148 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 149 AMDGPU_PP_SENSOR_MEM_TEMP, 150 AMDGPU_PP_SENSOR_VCE_POWER, 151 AMDGPU_PP_SENSOR_UVD_POWER, 152 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 153 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 154 AMDGPU_PP_SENSOR_SS_APU_SHARE, 155 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 156 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 157 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 158 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 159 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 160 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 161 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 162 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 163 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 164 AMDGPU_PP_SENSOR_VCN_LOAD, 165 AMDGPU_PP_SENSOR_NODEPOWERLIMIT, 166 AMDGPU_PP_SENSOR_NODEPOWER, 167 AMDGPU_PP_SENSOR_GPPTRESIDENCY, 168 AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, 169 AMDGPU_PP_SENSOR_UBB_POWER, 170 AMDGPU_PP_SENSOR_UBB_POWER_LIMIT, 171 }; 172 173 enum amd_pp_task { 174 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 175 AMD_PP_TASK_ENABLE_USER_STATE, 176 AMD_PP_TASK_READJUST_POWER_STATE, 177 AMD_PP_TASK_COMPLETE_INIT, 178 AMD_PP_TASK_MAX 179 }; 180 181 enum PP_SMC_POWER_PROFILE { 182 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 183 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 184 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 185 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 186 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 187 PP_SMC_POWER_PROFILE_VR = 0x4, 188 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 189 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 190 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 191 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 192 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 193 PP_SMC_POWER_PROFILE_COUNT, 194 }; 195 196 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 197 198 199 200 enum { 201 PP_GROUP_UNKNOWN = 0, 202 PP_GROUP_GFX = 1, 203 PP_GROUP_SYS, 204 PP_GROUP_MAX 205 }; 206 207 enum PP_OD_DPM_TABLE_COMMAND { 208 PP_OD_EDIT_SCLK_VDDC_TABLE, 209 PP_OD_EDIT_MCLK_VDDC_TABLE, 210 PP_OD_EDIT_CCLK_VDDC_TABLE, 211 PP_OD_EDIT_VDDC_CURVE, 212 PP_OD_RESTORE_DEFAULT_TABLE, 213 PP_OD_COMMIT_DPM_TABLE, 214 PP_OD_EDIT_VDDGFX_OFFSET, 215 PP_OD_EDIT_FAN_CURVE, 216 PP_OD_EDIT_ACOUSTIC_LIMIT, 217 PP_OD_EDIT_ACOUSTIC_TARGET, 218 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 219 PP_OD_EDIT_FAN_MINIMUM_PWM, 220 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 221 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 222 }; 223 224 struct pp_states_info { 225 uint32_t nums; 226 uint32_t states[16]; 227 }; 228 229 enum PP_HWMON_TEMP { 230 PP_TEMP_EDGE = 0, 231 PP_TEMP_JUNCTION, 232 PP_TEMP_MEM, 233 PP_TEMP_MAX 234 }; 235 236 enum pp_mp1_state { 237 PP_MP1_STATE_NONE, 238 PP_MP1_STATE_SHUTDOWN, 239 PP_MP1_STATE_UNLOAD, 240 PP_MP1_STATE_RESET, 241 PP_MP1_STATE_FLR, 242 }; 243 244 enum pp_df_cstate { 245 DF_CSTATE_DISALLOW = 0, 246 DF_CSTATE_ALLOW, 247 }; 248 249 /** 250 * DOC: amdgpu_pp_power 251 * 252 * APU power is managed to system-level requirements through the PPT 253 * (package power tracking) feature. PPT is intended to limit power to the 254 * requirements of the power source and could be dynamically updated to 255 * maximize APU performance within the system power budget. 256 * 257 * Two types of power measurement can be requested, where supported, with 258 * :c:type:`enum pp_power_type <pp_power_type>`. 259 */ 260 261 /** 262 * enum pp_power_limit_level - Used to query the power limits 263 * 264 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 265 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 266 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 267 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 268 */ 269 enum pp_power_limit_level { 270 PP_PWR_LIMIT_MIN = -1, 271 PP_PWR_LIMIT_CURRENT, 272 PP_PWR_LIMIT_DEFAULT, 273 PP_PWR_LIMIT_MAX, 274 }; 275 276 /** 277 * enum pp_power_type - Used to specify the type of the requested power 278 * 279 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 280 * moving average of APU power (default ~5000 ms). 281 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 282 * where supported. 283 */ 284 enum pp_power_type { 285 PP_PWR_TYPE_SUSTAINED, 286 PP_PWR_TYPE_FAST, 287 }; 288 289 enum pp_xgmi_plpd_mode { 290 XGMI_PLPD_NONE = -1, 291 XGMI_PLPD_DISALLOW, 292 XGMI_PLPD_DEFAULT, 293 XGMI_PLPD_OPTIMIZED, 294 XGMI_PLPD_COUNT, 295 }; 296 297 enum pp_pm_policy { 298 PP_PM_POLICY_NONE = -1, 299 PP_PM_POLICY_SOC_PSTATE = 0, 300 PP_PM_POLICY_XGMI_PLPD, 301 PP_PM_POLICY_NUM, 302 }; 303 304 enum pp_policy_soc_pstate { 305 SOC_PSTATE_DEFAULT = 0, 306 SOC_PSTATE_0, 307 SOC_PSTATE_1, 308 SOC_PSTATE_2, 309 SOC_PSTAT_COUNT, 310 }; 311 312 #define PP_POLICY_MAX_LEVELS 5 313 314 #define PP_GROUP_MASK 0xF0000000 315 #define PP_GROUP_SHIFT 28 316 317 #define PP_BLOCK_MASK 0x0FFFFF00 318 #define PP_BLOCK_SHIFT 8 319 320 #define PP_BLOCK_GFX_CG 0x01 321 #define PP_BLOCK_GFX_MG 0x02 322 #define PP_BLOCK_GFX_3D 0x04 323 #define PP_BLOCK_GFX_RLC 0x08 324 #define PP_BLOCK_GFX_CP 0x10 325 #define PP_BLOCK_SYS_BIF 0x01 326 #define PP_BLOCK_SYS_MC 0x02 327 #define PP_BLOCK_SYS_ROM 0x04 328 #define PP_BLOCK_SYS_DRM 0x08 329 #define PP_BLOCK_SYS_HDP 0x10 330 #define PP_BLOCK_SYS_SDMA 0x20 331 332 #define PP_STATE_MASK 0x0000000F 333 #define PP_STATE_SHIFT 0 334 #define PP_STATE_SUPPORT_MASK 0x000000F0 335 #define PP_STATE_SUPPORT_SHIFT 0 336 337 #define PP_STATE_CG 0x01 338 #define PP_STATE_LS 0x02 339 #define PP_STATE_DS 0x04 340 #define PP_STATE_SD 0x08 341 #define PP_STATE_SUPPORT_CG 0x10 342 #define PP_STATE_SUPPORT_LS 0x20 343 #define PP_STATE_SUPPORT_DS 0x40 344 #define PP_STATE_SUPPORT_SD 0x80 345 346 #define PP_CG_MSG_ID(group, block, support, state) \ 347 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 348 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 349 350 #define XGMI_MODE_PSTATE_D3 0 351 #define XGMI_MODE_PSTATE_D0 1 352 353 #define NUM_HBM_INSTANCES 4 354 #define NUM_XGMI_LINKS 8 355 #define MAX_GFX_CLKS 8 356 #define MAX_CLKS 4 357 #define NUM_VCN 4 358 #define NUM_JPEG_ENG 32 359 #define NUM_JPEG_ENG_V1 40 360 #define MAX_XCC 8 361 #define NUM_XCP 8 362 struct seq_file; 363 enum amd_pp_clock_type; 364 struct amd_pp_simple_clock_info; 365 struct amd_pp_display_configuration; 366 struct amd_pp_clock_info; 367 struct pp_display_clock_request; 368 struct pp_clock_levels_with_voltage; 369 struct pp_clock_levels_with_latency; 370 struct amd_pp_clocks; 371 struct pp_smu_wm_range_sets; 372 struct pp_smu_nv_clock_table; 373 struct dpm_clocks; 374 375 struct amdgpu_xcp_metrics { 376 /* Utilization Instantaneous (%) */ 377 uint32_t gfx_busy_inst[MAX_XCC]; 378 uint16_t jpeg_busy[NUM_JPEG_ENG]; 379 uint16_t vcn_busy[NUM_VCN]; 380 /* Utilization Accumulated (%) */ 381 uint64_t gfx_busy_acc[MAX_XCC]; 382 }; 383 384 struct amdgpu_xcp_metrics_v1_1 { 385 /* Utilization Instantaneous (%) */ 386 uint32_t gfx_busy_inst[MAX_XCC]; 387 uint16_t jpeg_busy[NUM_JPEG_ENG]; 388 uint16_t vcn_busy[NUM_VCN]; 389 /* Utilization Accumulated (%) */ 390 uint64_t gfx_busy_acc[MAX_XCC]; 391 /* Total App Clock Counter Accumulated */ 392 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 393 }; 394 395 struct amdgpu_xcp_metrics_v1_2 { 396 /* Utilization Instantaneous (%) */ 397 uint32_t gfx_busy_inst[MAX_XCC]; 398 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 399 uint16_t vcn_busy[NUM_VCN]; 400 /* Utilization Accumulated (%) */ 401 uint64_t gfx_busy_acc[MAX_XCC]; 402 /* Total App Clock Counter Accumulated */ 403 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 404 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 405 uint64_t gfx_low_utilization_acc[MAX_XCC]; 406 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 407 }; 408 409 struct amd_pm_funcs { 410 /* export for dpm on ci and si */ 411 int (*pre_set_power_state)(void *handle); 412 int (*set_power_state)(void *handle); 413 void (*post_set_power_state)(void *handle); 414 void (*display_configuration_changed)(void *handle); 415 void (*print_power_state)(void *handle, void *ps); 416 bool (*vblank_too_short)(void *handle); 417 void (*enable_bapm)(void *handle, bool enable); 418 int (*check_state_equal)(void *handle, 419 void *cps, 420 void *rps, 421 bool *equal); 422 /* export for sysfs */ 423 int (*set_fan_control_mode)(void *handle, u32 mode); 424 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 425 int (*set_fan_speed_pwm)(void *handle, u32 speed); 426 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 427 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 428 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 429 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 430 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 431 int (*get_sclk_od)(void *handle); 432 int (*set_sclk_od)(void *handle, uint32_t value); 433 int (*get_mclk_od)(void *handle); 434 int (*set_mclk_od)(void *handle, uint32_t value); 435 int (*read_sensor)(void *handle, int idx, void *value, int *size); 436 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 437 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 438 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 439 enum amd_pm_state_type (*get_current_power_state)(void *handle); 440 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 441 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 442 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 443 int (*get_pp_table)(void *handle, char **table); 444 int (*set_pp_table)(void *handle, const char *buf, size_t size); 445 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 446 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 447 int (*pause_power_profile)(void *handle, bool pause); 448 /* export to amdgpu */ 449 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 450 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 451 enum amd_pm_state_type *user_state); 452 int (*load_firmware)(void *handle); 453 int (*wait_for_fw_loading_complete)(void *handle); 454 int (*set_powergating_by_smu)(void *handle, 455 uint32_t block_type, 456 bool gate, 457 int inst); 458 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 459 int (*set_power_limit)(void *handle, uint32_t limit_type, uint32_t n); 460 int (*get_power_limit)(void *handle, uint32_t *limit, 461 enum pp_power_limit_level pp_limit_level, 462 enum pp_power_type power_type); 463 int (*get_power_profile_mode)(void *handle, char *buf); 464 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 465 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 466 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 467 long *input, uint32_t size); 468 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 469 int (*smu_i2c_bus_access)(void *handle, bool acquire); 470 int (*gfx_state_change_set)(void *handle, uint32_t state); 471 /* export to DC */ 472 u32 (*get_sclk)(void *handle, bool low); 473 u32 (*get_mclk)(void *handle, bool low); 474 int (*display_configuration_change)(void *handle, 475 const struct amd_pp_display_configuration *input); 476 int (*get_display_power_level)(void *handle, 477 struct amd_pp_simple_clock_info *output); 478 int (*get_current_clocks)(void *handle, 479 struct amd_pp_clock_info *clocks); 480 int (*get_clock_by_type)(void *handle, 481 enum amd_pp_clock_type type, 482 struct amd_pp_clocks *clocks); 483 int (*get_clock_by_type_with_latency)(void *handle, 484 enum amd_pp_clock_type type, 485 struct pp_clock_levels_with_latency *clocks); 486 int (*get_clock_by_type_with_voltage)(void *handle, 487 enum amd_pp_clock_type type, 488 struct pp_clock_levels_with_voltage *clocks); 489 int (*set_watermarks_for_clocks_ranges)(void *handle, 490 void *clock_ranges); 491 int (*display_clock_voltage_request)(void *handle, 492 struct pp_display_clock_request *clock); 493 int (*get_display_mode_validation_clocks)(void *handle, 494 struct amd_pp_simple_clock_info *clocks); 495 int (*notify_smu_enable_pwe)(void *handle); 496 int (*enable_mgpu_fan_boost)(void *handle); 497 int (*set_active_display_count)(void *handle, uint32_t count); 498 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 499 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 500 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 501 int (*get_asic_baco_capability)(void *handle); 502 int (*get_asic_baco_state)(void *handle, int *state); 503 int (*set_asic_baco_state)(void *handle, int state); 504 int (*get_ppfeature_status)(void *handle, char *buf); 505 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 506 int (*asic_reset_mode_2)(void *handle); 507 int (*asic_reset_enable_gfx_features)(void *handle); 508 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 509 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 510 ssize_t (*get_gpu_metrics)(void *handle, void **table); 511 ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table); 512 bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type); 513 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table); 514 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 515 int (*set_watermarks_for_clock_ranges)(void *handle, 516 struct pp_smu_wm_range_sets *ranges); 517 int (*display_disable_memory_clock_switch)(void *handle, 518 bool disable_memory_clock_switch); 519 int (*get_max_sustainable_clocks_by_dc)(void *handle, 520 struct pp_smu_nv_clock_table *max_clocks); 521 int (*get_uclk_dpm_states)(void *handle, 522 unsigned int *clock_values_in_khz, 523 unsigned int *num_states); 524 int (*get_dpm_clock_table)(void *handle, 525 struct dpm_clocks *clock_table); 526 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 527 void (*pm_compute_clocks)(void *handle); 528 int (*notify_rlc_state)(void *handle, bool en); 529 }; 530 531 struct metrics_table_header { 532 uint16_t structure_size; 533 uint8_t format_revision; 534 uint8_t content_revision; 535 }; 536 537 enum amdgpu_metrics_attr_id { 538 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HOTSPOT, 539 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MEM, 540 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_VRSOC, 541 AMDGPU_METRICS_ATTR_ID_CURR_SOCKET_POWER, 542 AMDGPU_METRICS_ATTR_ID_AVERAGE_GFX_ACTIVITY, 543 AMDGPU_METRICS_ATTR_ID_AVERAGE_UMC_ACTIVITY, 544 AMDGPU_METRICS_ATTR_ID_MEM_MAX_BANDWIDTH, 545 AMDGPU_METRICS_ATTR_ID_ENERGY_ACCUMULATOR, 546 AMDGPU_METRICS_ATTR_ID_SYSTEM_CLOCK_COUNTER, 547 AMDGPU_METRICS_ATTR_ID_ACCUMULATION_COUNTER, 548 AMDGPU_METRICS_ATTR_ID_PROCHOT_RESIDENCY_ACC, 549 AMDGPU_METRICS_ATTR_ID_PPT_RESIDENCY_ACC, 550 AMDGPU_METRICS_ATTR_ID_SOCKET_THM_RESIDENCY_ACC, 551 AMDGPU_METRICS_ATTR_ID_VR_THM_RESIDENCY_ACC, 552 AMDGPU_METRICS_ATTR_ID_HBM_THM_RESIDENCY_ACC, 553 AMDGPU_METRICS_ATTR_ID_GFXCLK_LOCK_STATUS, 554 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_WIDTH, 555 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_SPEED, 556 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_WIDTH, 557 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_SPEED, 558 AMDGPU_METRICS_ATTR_ID_GFX_ACTIVITY_ACC, 559 AMDGPU_METRICS_ATTR_ID_MEM_ACTIVITY_ACC, 560 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_ACC, 561 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_INST, 562 AMDGPU_METRICS_ATTR_ID_PCIE_L0_TO_RECOV_COUNT_ACC, 563 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_COUNT_ACC, 564 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_ROVER_COUNT_ACC, 565 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_SENT_COUNT_ACC, 566 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_RCVD_COUNT_ACC, 567 AMDGPU_METRICS_ATTR_ID_XGMI_READ_DATA_ACC, 568 AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_DATA_ACC, 569 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_STATUS, 570 AMDGPU_METRICS_ATTR_ID_FIRMWARE_TIMESTAMP, 571 AMDGPU_METRICS_ATTR_ID_CURRENT_GFXCLK, 572 AMDGPU_METRICS_ATTR_ID_CURRENT_SOCCLK, 573 AMDGPU_METRICS_ATTR_ID_CURRENT_VCLK0, 574 AMDGPU_METRICS_ATTR_ID_CURRENT_DCLK0, 575 AMDGPU_METRICS_ATTR_ID_CURRENT_UCLK, 576 AMDGPU_METRICS_ATTR_ID_NUM_PARTITION, 577 AMDGPU_METRICS_ATTR_ID_PCIE_LC_PERF_OTHER_END_RECOVERY, 578 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_INST, 579 AMDGPU_METRICS_ATTR_ID_JPEG_BUSY, 580 AMDGPU_METRICS_ATTR_ID_VCN_BUSY, 581 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_ACC, 582 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_PPT_ACC, 583 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC, 584 AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, 585 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, 586 AMDGPU_METRICS_ATTR_ID_MAX, 587 }; 588 589 enum amdgpu_metrics_attr_type { 590 AMDGPU_METRICS_TYPE_U8, 591 AMDGPU_METRICS_TYPE_S8, 592 AMDGPU_METRICS_TYPE_U16, 593 AMDGPU_METRICS_TYPE_S16, 594 AMDGPU_METRICS_TYPE_U32, 595 AMDGPU_METRICS_TYPE_S32, 596 AMDGPU_METRICS_TYPE_U64, 597 AMDGPU_METRICS_TYPE_S64, 598 AMDGPU_METRICS_TYPE_MAX, 599 }; 600 601 enum amdgpu_metrics_attr_unit { 602 /* None */ 603 AMDGPU_METRICS_UNIT_NONE, 604 /* MHz*/ 605 AMDGPU_METRICS_UNIT_CLOCK_1, 606 /* Degree Celsius*/ 607 AMDGPU_METRICS_UNIT_TEMP_1, 608 /* Watts*/ 609 AMDGPU_METRICS_UNIT_POWER_1, 610 /* In nanoseconds*/ 611 AMDGPU_METRICS_UNIT_TIME_1, 612 /* In 10 nanoseconds*/ 613 AMDGPU_METRICS_UNIT_TIME_2, 614 /* Speed in GT/s */ 615 AMDGPU_METRICS_UNIT_SPEED_1, 616 /* Speed in 0.1 GT/s */ 617 AMDGPU_METRICS_UNIT_SPEED_2, 618 /* Bandwidth GB/s */ 619 AMDGPU_METRICS_UNIT_BW_1, 620 /* Data in KB */ 621 AMDGPU_METRICS_UNIT_DATA_1, 622 /* Percentage */ 623 AMDGPU_METRICS_UNIT_PERCENT, 624 AMDGPU_METRICS_UNIT_MAX, 625 }; 626 627 #define AMDGPU_METRICS_ATTR_UNIT_MASK 0xFF000000 628 #define AMDGPU_METRICS_ATTR_UNIT_SHIFT 24 629 #define AMDGPU_METRICS_ATTR_TYPE_MASK 0x00F00000 630 #define AMDGPU_METRICS_ATTR_TYPE_SHIFT 20 631 #define AMDGPU_METRICS_ATTR_ID_MASK 0x000FFC00 632 #define AMDGPU_METRICS_ATTR_ID_SHIFT 10 633 #define AMDGPU_METRICS_ATTR_INST_MASK 0x000003FF 634 #define AMDGPU_METRICS_ATTR_INST_SHIFT 0 635 636 #define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \ 637 (((u64)(unit) << AMDGPU_METRICS_ATTR_UNIT_SHIFT) | \ 638 ((u64)(type) << AMDGPU_METRICS_ATTR_TYPE_SHIFT) | \ 639 ((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst)) 640 641 /* 642 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 643 * Use gpu_metrics_v1_1 or later instead. 644 */ 645 struct gpu_metrics_v1_0 { 646 struct metrics_table_header common_header; 647 648 /* Driver attached timestamp (in ns) */ 649 uint64_t system_clock_counter; 650 651 /* Temperature */ 652 uint16_t temperature_edge; 653 uint16_t temperature_hotspot; 654 uint16_t temperature_mem; 655 uint16_t temperature_vrgfx; 656 uint16_t temperature_vrsoc; 657 uint16_t temperature_vrmem; 658 659 /* Utilization */ 660 uint16_t average_gfx_activity; 661 uint16_t average_umc_activity; // memory controller 662 uint16_t average_mm_activity; // UVD or VCN 663 664 /* Power/Energy */ 665 uint16_t average_socket_power; 666 uint32_t energy_accumulator; 667 668 /* Average clocks */ 669 uint16_t average_gfxclk_frequency; 670 uint16_t average_socclk_frequency; 671 uint16_t average_uclk_frequency; 672 uint16_t average_vclk0_frequency; 673 uint16_t average_dclk0_frequency; 674 uint16_t average_vclk1_frequency; 675 uint16_t average_dclk1_frequency; 676 677 /* Current clocks */ 678 uint16_t current_gfxclk; 679 uint16_t current_socclk; 680 uint16_t current_uclk; 681 uint16_t current_vclk0; 682 uint16_t current_dclk0; 683 uint16_t current_vclk1; 684 uint16_t current_dclk1; 685 686 /* Throttle status */ 687 uint32_t throttle_status; 688 689 /* Fans */ 690 uint16_t current_fan_speed; 691 692 /* Link width/speed */ 693 uint8_t pcie_link_width; 694 uint8_t pcie_link_speed; // in 0.1 GT/s 695 }; 696 697 struct gpu_metrics_v1_1 { 698 struct metrics_table_header common_header; 699 700 /* Temperature */ 701 uint16_t temperature_edge; 702 uint16_t temperature_hotspot; 703 uint16_t temperature_mem; 704 uint16_t temperature_vrgfx; 705 uint16_t temperature_vrsoc; 706 uint16_t temperature_vrmem; 707 708 /* Utilization */ 709 uint16_t average_gfx_activity; 710 uint16_t average_umc_activity; // memory controller 711 uint16_t average_mm_activity; // UVD or VCN 712 713 /* Power/Energy */ 714 uint16_t average_socket_power; 715 uint64_t energy_accumulator; 716 717 /* Driver attached timestamp (in ns) */ 718 uint64_t system_clock_counter; 719 720 /* Average clocks */ 721 uint16_t average_gfxclk_frequency; 722 uint16_t average_socclk_frequency; 723 uint16_t average_uclk_frequency; 724 uint16_t average_vclk0_frequency; 725 uint16_t average_dclk0_frequency; 726 uint16_t average_vclk1_frequency; 727 uint16_t average_dclk1_frequency; 728 729 /* Current clocks */ 730 uint16_t current_gfxclk; 731 uint16_t current_socclk; 732 uint16_t current_uclk; 733 uint16_t current_vclk0; 734 uint16_t current_dclk0; 735 uint16_t current_vclk1; 736 uint16_t current_dclk1; 737 738 /* Throttle status */ 739 uint32_t throttle_status; 740 741 /* Fans */ 742 uint16_t current_fan_speed; 743 744 /* Link width/speed */ 745 uint16_t pcie_link_width; 746 uint16_t pcie_link_speed; // in 0.1 GT/s 747 748 uint16_t padding; 749 750 uint32_t gfx_activity_acc; 751 uint32_t mem_activity_acc; 752 753 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 754 }; 755 756 struct gpu_metrics_v1_2 { 757 struct metrics_table_header common_header; 758 759 /* Temperature */ 760 uint16_t temperature_edge; 761 uint16_t temperature_hotspot; 762 uint16_t temperature_mem; 763 uint16_t temperature_vrgfx; 764 uint16_t temperature_vrsoc; 765 uint16_t temperature_vrmem; 766 767 /* Utilization */ 768 uint16_t average_gfx_activity; 769 uint16_t average_umc_activity; // memory controller 770 uint16_t average_mm_activity; // UVD or VCN 771 772 /* Power/Energy */ 773 uint16_t average_socket_power; 774 uint64_t energy_accumulator; 775 776 /* Driver attached timestamp (in ns) */ 777 uint64_t system_clock_counter; 778 779 /* Average clocks */ 780 uint16_t average_gfxclk_frequency; 781 uint16_t average_socclk_frequency; 782 uint16_t average_uclk_frequency; 783 uint16_t average_vclk0_frequency; 784 uint16_t average_dclk0_frequency; 785 uint16_t average_vclk1_frequency; 786 uint16_t average_dclk1_frequency; 787 788 /* Current clocks */ 789 uint16_t current_gfxclk; 790 uint16_t current_socclk; 791 uint16_t current_uclk; 792 uint16_t current_vclk0; 793 uint16_t current_dclk0; 794 uint16_t current_vclk1; 795 uint16_t current_dclk1; 796 797 /* Throttle status (ASIC dependent) */ 798 uint32_t throttle_status; 799 800 /* Fans */ 801 uint16_t current_fan_speed; 802 803 /* Link width/speed */ 804 uint16_t pcie_link_width; 805 uint16_t pcie_link_speed; // in 0.1 GT/s 806 807 uint16_t padding; 808 809 uint32_t gfx_activity_acc; 810 uint32_t mem_activity_acc; 811 812 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 813 814 /* PMFW attached timestamp (10ns resolution) */ 815 uint64_t firmware_timestamp; 816 }; 817 818 struct gpu_metrics_v1_3 { 819 struct metrics_table_header common_header; 820 821 /* Temperature */ 822 uint16_t temperature_edge; 823 uint16_t temperature_hotspot; 824 uint16_t temperature_mem; 825 uint16_t temperature_vrgfx; 826 uint16_t temperature_vrsoc; 827 uint16_t temperature_vrmem; 828 829 /* Utilization */ 830 uint16_t average_gfx_activity; 831 uint16_t average_umc_activity; // memory controller 832 uint16_t average_mm_activity; // UVD or VCN 833 834 /* Power/Energy */ 835 uint16_t average_socket_power; 836 uint64_t energy_accumulator; 837 838 /* Driver attached timestamp (in ns) */ 839 uint64_t system_clock_counter; 840 841 /* Average clocks */ 842 uint16_t average_gfxclk_frequency; 843 uint16_t average_socclk_frequency; 844 uint16_t average_uclk_frequency; 845 uint16_t average_vclk0_frequency; 846 uint16_t average_dclk0_frequency; 847 uint16_t average_vclk1_frequency; 848 uint16_t average_dclk1_frequency; 849 850 /* Current clocks */ 851 uint16_t current_gfxclk; 852 uint16_t current_socclk; 853 uint16_t current_uclk; 854 uint16_t current_vclk0; 855 uint16_t current_dclk0; 856 uint16_t current_vclk1; 857 uint16_t current_dclk1; 858 859 /* Throttle status */ 860 uint32_t throttle_status; 861 862 /* Fans */ 863 uint16_t current_fan_speed; 864 865 /* Link width/speed */ 866 uint16_t pcie_link_width; 867 uint16_t pcie_link_speed; // in 0.1 GT/s 868 869 uint16_t padding; 870 871 uint32_t gfx_activity_acc; 872 uint32_t mem_activity_acc; 873 874 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 875 876 /* PMFW attached timestamp (10ns resolution) */ 877 uint64_t firmware_timestamp; 878 879 /* Voltage (mV) */ 880 uint16_t voltage_soc; 881 uint16_t voltage_gfx; 882 uint16_t voltage_mem; 883 884 uint16_t padding1; 885 886 /* Throttle status (ASIC independent) */ 887 uint64_t indep_throttle_status; 888 }; 889 890 struct gpu_metrics_v1_4 { 891 struct metrics_table_header common_header; 892 893 /* Temperature (Celsius) */ 894 uint16_t temperature_hotspot; 895 uint16_t temperature_mem; 896 uint16_t temperature_vrsoc; 897 898 /* Power (Watts) */ 899 uint16_t curr_socket_power; 900 901 /* Utilization (%) */ 902 uint16_t average_gfx_activity; 903 uint16_t average_umc_activity; // memory controller 904 uint16_t vcn_activity[NUM_VCN]; 905 906 /* Energy (15.259uJ (2^-16) units) */ 907 uint64_t energy_accumulator; 908 909 /* Driver attached timestamp (in ns) */ 910 uint64_t system_clock_counter; 911 912 /* Throttle status */ 913 uint32_t throttle_status; 914 915 /* Clock Lock Status. Each bit corresponds to clock instance */ 916 uint32_t gfxclk_lock_status; 917 918 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 919 uint16_t pcie_link_width; 920 uint16_t pcie_link_speed; 921 922 /* XGMI bus width and bitrate (in Gbps) */ 923 uint16_t xgmi_link_width; 924 uint16_t xgmi_link_speed; 925 926 /* Utilization Accumulated (%) */ 927 uint32_t gfx_activity_acc; 928 uint32_t mem_activity_acc; 929 930 /*PCIE accumulated bandwidth (GB/sec) */ 931 uint64_t pcie_bandwidth_acc; 932 933 /*PCIE instantaneous bandwidth (GB/sec) */ 934 uint64_t pcie_bandwidth_inst; 935 936 /* PCIE L0 to recovery state transition accumulated count */ 937 uint64_t pcie_l0_to_recov_count_acc; 938 939 /* PCIE replay accumulated count */ 940 uint64_t pcie_replay_count_acc; 941 942 /* PCIE replay rollover accumulated count */ 943 uint64_t pcie_replay_rover_count_acc; 944 945 /* XGMI accumulated data transfer size(KiloBytes) */ 946 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 947 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 948 949 /* PMFW attached timestamp (10ns resolution) */ 950 uint64_t firmware_timestamp; 951 952 /* Current clocks (Mhz) */ 953 uint16_t current_gfxclk[MAX_GFX_CLKS]; 954 uint16_t current_socclk[MAX_CLKS]; 955 uint16_t current_vclk0[MAX_CLKS]; 956 uint16_t current_dclk0[MAX_CLKS]; 957 uint16_t current_uclk; 958 959 uint16_t padding; 960 }; 961 962 struct gpu_metrics_v1_5 { 963 struct metrics_table_header common_header; 964 965 /* Temperature (Celsius) */ 966 uint16_t temperature_hotspot; 967 uint16_t temperature_mem; 968 uint16_t temperature_vrsoc; 969 970 /* Power (Watts) */ 971 uint16_t curr_socket_power; 972 973 /* Utilization (%) */ 974 uint16_t average_gfx_activity; 975 uint16_t average_umc_activity; // memory controller 976 uint16_t vcn_activity[NUM_VCN]; 977 uint16_t jpeg_activity[NUM_JPEG_ENG]; 978 979 /* Energy (15.259uJ (2^-16) units) */ 980 uint64_t energy_accumulator; 981 982 /* Driver attached timestamp (in ns) */ 983 uint64_t system_clock_counter; 984 985 /* Throttle status */ 986 uint32_t throttle_status; 987 988 /* Clock Lock Status. Each bit corresponds to clock instance */ 989 uint32_t gfxclk_lock_status; 990 991 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 992 uint16_t pcie_link_width; 993 uint16_t pcie_link_speed; 994 995 /* XGMI bus width and bitrate (in Gbps) */ 996 uint16_t xgmi_link_width; 997 uint16_t xgmi_link_speed; 998 999 /* Utilization Accumulated (%) */ 1000 uint32_t gfx_activity_acc; 1001 uint32_t mem_activity_acc; 1002 1003 /*PCIE accumulated bandwidth (GB/sec) */ 1004 uint64_t pcie_bandwidth_acc; 1005 1006 /*PCIE instantaneous bandwidth (GB/sec) */ 1007 uint64_t pcie_bandwidth_inst; 1008 1009 /* PCIE L0 to recovery state transition accumulated count */ 1010 uint64_t pcie_l0_to_recov_count_acc; 1011 1012 /* PCIE replay accumulated count */ 1013 uint64_t pcie_replay_count_acc; 1014 1015 /* PCIE replay rollover accumulated count */ 1016 uint64_t pcie_replay_rover_count_acc; 1017 1018 /* PCIE NAK sent accumulated count */ 1019 uint32_t pcie_nak_sent_count_acc; 1020 1021 /* PCIE NAK received accumulated count */ 1022 uint32_t pcie_nak_rcvd_count_acc; 1023 1024 /* XGMI accumulated data transfer size(KiloBytes) */ 1025 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1026 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1027 1028 /* PMFW attached timestamp (10ns resolution) */ 1029 uint64_t firmware_timestamp; 1030 1031 /* Current clocks (Mhz) */ 1032 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1033 uint16_t current_socclk[MAX_CLKS]; 1034 uint16_t current_vclk0[MAX_CLKS]; 1035 uint16_t current_dclk0[MAX_CLKS]; 1036 uint16_t current_uclk; 1037 1038 uint16_t padding; 1039 }; 1040 1041 struct gpu_metrics_v1_6 { 1042 struct metrics_table_header common_header; 1043 1044 /* Temperature (Celsius) */ 1045 uint16_t temperature_hotspot; 1046 uint16_t temperature_mem; 1047 uint16_t temperature_vrsoc; 1048 1049 /* Power (Watts) */ 1050 uint16_t curr_socket_power; 1051 1052 /* Utilization (%) */ 1053 uint16_t average_gfx_activity; 1054 uint16_t average_umc_activity; // memory controller 1055 1056 /* Energy (15.259uJ (2^-16) units) */ 1057 uint64_t energy_accumulator; 1058 1059 /* Driver attached timestamp (in ns) */ 1060 uint64_t system_clock_counter; 1061 1062 /* Accumulation cycle counter */ 1063 uint32_t accumulation_counter; 1064 1065 /* Accumulated throttler residencies */ 1066 uint32_t prochot_residency_acc; 1067 uint32_t ppt_residency_acc; 1068 uint32_t socket_thm_residency_acc; 1069 uint32_t vr_thm_residency_acc; 1070 uint32_t hbm_thm_residency_acc; 1071 1072 /* Clock Lock Status. Each bit corresponds to clock instance */ 1073 uint32_t gfxclk_lock_status; 1074 1075 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1076 uint16_t pcie_link_width; 1077 uint16_t pcie_link_speed; 1078 1079 /* XGMI bus width and bitrate (in Gbps) */ 1080 uint16_t xgmi_link_width; 1081 uint16_t xgmi_link_speed; 1082 1083 /* Utilization Accumulated (%) */ 1084 uint32_t gfx_activity_acc; 1085 uint32_t mem_activity_acc; 1086 1087 /*PCIE accumulated bandwidth (GB/sec) */ 1088 uint64_t pcie_bandwidth_acc; 1089 1090 /*PCIE instantaneous bandwidth (GB/sec) */ 1091 uint64_t pcie_bandwidth_inst; 1092 1093 /* PCIE L0 to recovery state transition accumulated count */ 1094 uint64_t pcie_l0_to_recov_count_acc; 1095 1096 /* PCIE replay accumulated count */ 1097 uint64_t pcie_replay_count_acc; 1098 1099 /* PCIE replay rollover accumulated count */ 1100 uint64_t pcie_replay_rover_count_acc; 1101 1102 /* PCIE NAK sent accumulated count */ 1103 uint32_t pcie_nak_sent_count_acc; 1104 1105 /* PCIE NAK received accumulated count */ 1106 uint32_t pcie_nak_rcvd_count_acc; 1107 1108 /* XGMI accumulated data transfer size(KiloBytes) */ 1109 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1110 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1111 1112 /* PMFW attached timestamp (10ns resolution) */ 1113 uint64_t firmware_timestamp; 1114 1115 /* Current clocks (Mhz) */ 1116 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1117 uint16_t current_socclk[MAX_CLKS]; 1118 uint16_t current_vclk0[MAX_CLKS]; 1119 uint16_t current_dclk0[MAX_CLKS]; 1120 uint16_t current_uclk; 1121 1122 /* Number of current partition */ 1123 uint16_t num_partition; 1124 1125 /* XCP metrics stats */ 1126 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1127 1128 /* PCIE other end recovery counter */ 1129 uint32_t pcie_lc_perf_other_end_recovery; 1130 }; 1131 1132 struct gpu_metrics_v1_7 { 1133 struct metrics_table_header common_header; 1134 1135 /* Temperature (Celsius) */ 1136 uint16_t temperature_hotspot; 1137 uint16_t temperature_mem; 1138 uint16_t temperature_vrsoc; 1139 1140 /* Power (Watts) */ 1141 uint16_t curr_socket_power; 1142 1143 /* Utilization (%) */ 1144 uint16_t average_gfx_activity; 1145 uint16_t average_umc_activity; // memory controller 1146 1147 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1148 uint64_t mem_max_bandwidth; 1149 1150 /* Energy (15.259uJ (2^-16) units) */ 1151 uint64_t energy_accumulator; 1152 1153 /* Driver attached timestamp (in ns) */ 1154 uint64_t system_clock_counter; 1155 1156 /* Accumulation cycle counter */ 1157 uint32_t accumulation_counter; 1158 1159 /* Accumulated throttler residencies */ 1160 uint32_t prochot_residency_acc; 1161 uint32_t ppt_residency_acc; 1162 uint32_t socket_thm_residency_acc; 1163 uint32_t vr_thm_residency_acc; 1164 uint32_t hbm_thm_residency_acc; 1165 1166 /* Clock Lock Status. Each bit corresponds to clock instance */ 1167 uint32_t gfxclk_lock_status; 1168 1169 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1170 uint16_t pcie_link_width; 1171 uint16_t pcie_link_speed; 1172 1173 /* XGMI bus width and bitrate (in Gbps) */ 1174 uint16_t xgmi_link_width; 1175 uint16_t xgmi_link_speed; 1176 1177 /* Utilization Accumulated (%) */ 1178 uint32_t gfx_activity_acc; 1179 uint32_t mem_activity_acc; 1180 1181 /*PCIE accumulated bandwidth (GB/sec) */ 1182 uint64_t pcie_bandwidth_acc; 1183 1184 /*PCIE instantaneous bandwidth (GB/sec) */ 1185 uint64_t pcie_bandwidth_inst; 1186 1187 /* PCIE L0 to recovery state transition accumulated count */ 1188 uint64_t pcie_l0_to_recov_count_acc; 1189 1190 /* PCIE replay accumulated count */ 1191 uint64_t pcie_replay_count_acc; 1192 1193 /* PCIE replay rollover accumulated count */ 1194 uint64_t pcie_replay_rover_count_acc; 1195 1196 /* PCIE NAK sent accumulated count */ 1197 uint32_t pcie_nak_sent_count_acc; 1198 1199 /* PCIE NAK received accumulated count */ 1200 uint32_t pcie_nak_rcvd_count_acc; 1201 1202 /* XGMI accumulated data transfer size(KiloBytes) */ 1203 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1204 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1205 1206 /* XGMI link status(active/inactive) */ 1207 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1208 1209 uint16_t padding; 1210 1211 /* PMFW attached timestamp (10ns resolution) */ 1212 uint64_t firmware_timestamp; 1213 1214 /* Current clocks (Mhz) */ 1215 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1216 uint16_t current_socclk[MAX_CLKS]; 1217 uint16_t current_vclk0[MAX_CLKS]; 1218 uint16_t current_dclk0[MAX_CLKS]; 1219 uint16_t current_uclk; 1220 1221 /* Number of current partition */ 1222 uint16_t num_partition; 1223 1224 /* XCP metrics stats */ 1225 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1226 1227 /* PCIE other end recovery counter */ 1228 uint32_t pcie_lc_perf_other_end_recovery; 1229 }; 1230 1231 struct gpu_metrics_v1_8 { 1232 struct metrics_table_header common_header; 1233 1234 /* Temperature (Celsius) */ 1235 uint16_t temperature_hotspot; 1236 uint16_t temperature_mem; 1237 uint16_t temperature_vrsoc; 1238 1239 /* Power (Watts) */ 1240 uint16_t curr_socket_power; 1241 1242 /* Utilization (%) */ 1243 uint16_t average_gfx_activity; 1244 uint16_t average_umc_activity; // memory controller 1245 1246 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1247 uint64_t mem_max_bandwidth; 1248 1249 /* Energy (15.259uJ (2^-16) units) */ 1250 uint64_t energy_accumulator; 1251 1252 /* Driver attached timestamp (in ns) */ 1253 uint64_t system_clock_counter; 1254 1255 /* Accumulation cycle counter */ 1256 uint32_t accumulation_counter; 1257 1258 /* Accumulated throttler residencies */ 1259 uint32_t prochot_residency_acc; 1260 uint32_t ppt_residency_acc; 1261 uint32_t socket_thm_residency_acc; 1262 uint32_t vr_thm_residency_acc; 1263 uint32_t hbm_thm_residency_acc; 1264 1265 /* Clock Lock Status. Each bit corresponds to clock instance */ 1266 uint32_t gfxclk_lock_status; 1267 1268 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1269 uint16_t pcie_link_width; 1270 uint16_t pcie_link_speed; 1271 1272 /* XGMI bus width and bitrate (in Gbps) */ 1273 uint16_t xgmi_link_width; 1274 uint16_t xgmi_link_speed; 1275 1276 /* Utilization Accumulated (%) */ 1277 uint32_t gfx_activity_acc; 1278 uint32_t mem_activity_acc; 1279 1280 /*PCIE accumulated bandwidth (GB/sec) */ 1281 uint64_t pcie_bandwidth_acc; 1282 1283 /*PCIE instantaneous bandwidth (GB/sec) */ 1284 uint64_t pcie_bandwidth_inst; 1285 1286 /* PCIE L0 to recovery state transition accumulated count */ 1287 uint64_t pcie_l0_to_recov_count_acc; 1288 1289 /* PCIE replay accumulated count */ 1290 uint64_t pcie_replay_count_acc; 1291 1292 /* PCIE replay rollover accumulated count */ 1293 uint64_t pcie_replay_rover_count_acc; 1294 1295 /* PCIE NAK sent accumulated count */ 1296 uint32_t pcie_nak_sent_count_acc; 1297 1298 /* PCIE NAK received accumulated count */ 1299 uint32_t pcie_nak_rcvd_count_acc; 1300 1301 /* XGMI accumulated data transfer size(KiloBytes) */ 1302 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1303 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1304 1305 /* XGMI link status(active/inactive) */ 1306 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1307 1308 uint16_t padding; 1309 1310 /* PMFW attached timestamp (10ns resolution) */ 1311 uint64_t firmware_timestamp; 1312 1313 /* Current clocks (Mhz) */ 1314 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1315 uint16_t current_socclk[MAX_CLKS]; 1316 uint16_t current_vclk0[MAX_CLKS]; 1317 uint16_t current_dclk0[MAX_CLKS]; 1318 uint16_t current_uclk; 1319 1320 /* Number of current partition */ 1321 uint16_t num_partition; 1322 1323 /* XCP metrics stats */ 1324 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1325 1326 /* PCIE other end recovery counter */ 1327 uint32_t pcie_lc_perf_other_end_recovery; 1328 }; 1329 1330 struct gpu_metrics_attr { 1331 /* Field type encoded with AMDGPU_METRICS_ENC_ATTR */ 1332 uint64_t attr_encoding; 1333 /* Attribute value, depends on attr_encoding */ 1334 void *attr_value; 1335 }; 1336 1337 struct gpu_metrics_v1_9 { 1338 struct metrics_table_header common_header; 1339 int attr_count; 1340 struct gpu_metrics_attr metrics_attrs[]; 1341 }; 1342 1343 /* 1344 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1345 * Use gpu_metrics_v2_1 or later instead. 1346 */ 1347 struct gpu_metrics_v2_0 { 1348 struct metrics_table_header common_header; 1349 1350 /* Driver attached timestamp (in ns) */ 1351 uint64_t system_clock_counter; 1352 1353 /* Temperature */ 1354 uint16_t temperature_gfx; // gfx temperature on APUs 1355 uint16_t temperature_soc; // soc temperature on APUs 1356 uint16_t temperature_core[8]; // CPU core temperature on APUs 1357 uint16_t temperature_l3[2]; 1358 1359 /* Utilization */ 1360 uint16_t average_gfx_activity; 1361 uint16_t average_mm_activity; // UVD or VCN 1362 1363 /* Power/Energy */ 1364 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1365 uint16_t average_cpu_power; 1366 uint16_t average_soc_power; 1367 uint16_t average_gfx_power; 1368 uint16_t average_core_power[8]; // CPU core power on APUs 1369 1370 /* Average clocks */ 1371 uint16_t average_gfxclk_frequency; 1372 uint16_t average_socclk_frequency; 1373 uint16_t average_uclk_frequency; 1374 uint16_t average_fclk_frequency; 1375 uint16_t average_vclk_frequency; 1376 uint16_t average_dclk_frequency; 1377 1378 /* Current clocks */ 1379 uint16_t current_gfxclk; 1380 uint16_t current_socclk; 1381 uint16_t current_uclk; 1382 uint16_t current_fclk; 1383 uint16_t current_vclk; 1384 uint16_t current_dclk; 1385 uint16_t current_coreclk[8]; // CPU core clocks 1386 uint16_t current_l3clk[2]; 1387 1388 /* Throttle status */ 1389 uint32_t throttle_status; 1390 1391 /* Fans */ 1392 uint16_t fan_pwm; 1393 1394 uint16_t padding; 1395 }; 1396 1397 struct gpu_metrics_v2_1 { 1398 struct metrics_table_header common_header; 1399 1400 /* Temperature */ 1401 uint16_t temperature_gfx; // gfx temperature on APUs 1402 uint16_t temperature_soc; // soc temperature on APUs 1403 uint16_t temperature_core[8]; // CPU core temperature on APUs 1404 uint16_t temperature_l3[2]; 1405 1406 /* Utilization */ 1407 uint16_t average_gfx_activity; 1408 uint16_t average_mm_activity; // UVD or VCN 1409 1410 /* Driver attached timestamp (in ns) */ 1411 uint64_t system_clock_counter; 1412 1413 /* Power/Energy */ 1414 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1415 uint16_t average_cpu_power; 1416 uint16_t average_soc_power; 1417 uint16_t average_gfx_power; 1418 uint16_t average_core_power[8]; // CPU core power on APUs 1419 1420 /* Average clocks */ 1421 uint16_t average_gfxclk_frequency; 1422 uint16_t average_socclk_frequency; 1423 uint16_t average_uclk_frequency; 1424 uint16_t average_fclk_frequency; 1425 uint16_t average_vclk_frequency; 1426 uint16_t average_dclk_frequency; 1427 1428 /* Current clocks */ 1429 uint16_t current_gfxclk; 1430 uint16_t current_socclk; 1431 uint16_t current_uclk; 1432 uint16_t current_fclk; 1433 uint16_t current_vclk; 1434 uint16_t current_dclk; 1435 uint16_t current_coreclk[8]; // CPU core clocks 1436 uint16_t current_l3clk[2]; 1437 1438 /* Throttle status */ 1439 uint32_t throttle_status; 1440 1441 /* Fans */ 1442 uint16_t fan_pwm; 1443 1444 uint16_t padding[3]; 1445 }; 1446 1447 struct gpu_metrics_v2_2 { 1448 struct metrics_table_header common_header; 1449 1450 /* Temperature */ 1451 uint16_t temperature_gfx; // gfx temperature on APUs 1452 uint16_t temperature_soc; // soc temperature on APUs 1453 uint16_t temperature_core[8]; // CPU core temperature on APUs 1454 uint16_t temperature_l3[2]; 1455 1456 /* Utilization */ 1457 uint16_t average_gfx_activity; 1458 uint16_t average_mm_activity; // UVD or VCN 1459 1460 /* Driver attached timestamp (in ns) */ 1461 uint64_t system_clock_counter; 1462 1463 /* Power/Energy */ 1464 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1465 uint16_t average_cpu_power; 1466 uint16_t average_soc_power; 1467 uint16_t average_gfx_power; 1468 uint16_t average_core_power[8]; // CPU core power on APUs 1469 1470 /* Average clocks */ 1471 uint16_t average_gfxclk_frequency; 1472 uint16_t average_socclk_frequency; 1473 uint16_t average_uclk_frequency; 1474 uint16_t average_fclk_frequency; 1475 uint16_t average_vclk_frequency; 1476 uint16_t average_dclk_frequency; 1477 1478 /* Current clocks */ 1479 uint16_t current_gfxclk; 1480 uint16_t current_socclk; 1481 uint16_t current_uclk; 1482 uint16_t current_fclk; 1483 uint16_t current_vclk; 1484 uint16_t current_dclk; 1485 uint16_t current_coreclk[8]; // CPU core clocks 1486 uint16_t current_l3clk[2]; 1487 1488 /* Throttle status (ASIC dependent) */ 1489 uint32_t throttle_status; 1490 1491 /* Fans */ 1492 uint16_t fan_pwm; 1493 1494 uint16_t padding[3]; 1495 1496 /* Throttle status (ASIC independent) */ 1497 uint64_t indep_throttle_status; 1498 }; 1499 1500 struct gpu_metrics_v2_3 { 1501 struct metrics_table_header common_header; 1502 1503 /* Temperature */ 1504 uint16_t temperature_gfx; // gfx temperature on APUs 1505 uint16_t temperature_soc; // soc temperature on APUs 1506 uint16_t temperature_core[8]; // CPU core temperature on APUs 1507 uint16_t temperature_l3[2]; 1508 1509 /* Utilization */ 1510 uint16_t average_gfx_activity; 1511 uint16_t average_mm_activity; // UVD or VCN 1512 1513 /* Driver attached timestamp (in ns) */ 1514 uint64_t system_clock_counter; 1515 1516 /* Power/Energy */ 1517 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1518 uint16_t average_cpu_power; 1519 uint16_t average_soc_power; 1520 uint16_t average_gfx_power; 1521 uint16_t average_core_power[8]; // CPU core power on APUs 1522 1523 /* Average clocks */ 1524 uint16_t average_gfxclk_frequency; 1525 uint16_t average_socclk_frequency; 1526 uint16_t average_uclk_frequency; 1527 uint16_t average_fclk_frequency; 1528 uint16_t average_vclk_frequency; 1529 uint16_t average_dclk_frequency; 1530 1531 /* Current clocks */ 1532 uint16_t current_gfxclk; 1533 uint16_t current_socclk; 1534 uint16_t current_uclk; 1535 uint16_t current_fclk; 1536 uint16_t current_vclk; 1537 uint16_t current_dclk; 1538 uint16_t current_coreclk[8]; // CPU core clocks 1539 uint16_t current_l3clk[2]; 1540 1541 /* Throttle status (ASIC dependent) */ 1542 uint32_t throttle_status; 1543 1544 /* Fans */ 1545 uint16_t fan_pwm; 1546 1547 uint16_t padding[3]; 1548 1549 /* Throttle status (ASIC independent) */ 1550 uint64_t indep_throttle_status; 1551 1552 /* Average Temperature */ 1553 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1554 uint16_t average_temperature_soc; // average soc temperature on APUs 1555 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1556 uint16_t average_temperature_l3[2]; 1557 }; 1558 1559 struct gpu_metrics_v2_4 { 1560 struct metrics_table_header common_header; 1561 1562 /* Temperature (unit: centi-Celsius) */ 1563 uint16_t temperature_gfx; 1564 uint16_t temperature_soc; 1565 uint16_t temperature_core[8]; 1566 uint16_t temperature_l3[2]; 1567 1568 /* Utilization (unit: centi) */ 1569 uint16_t average_gfx_activity; 1570 uint16_t average_mm_activity; 1571 1572 /* Driver attached timestamp (in ns) */ 1573 uint64_t system_clock_counter; 1574 1575 /* Power/Energy (unit: mW) */ 1576 uint16_t average_socket_power; 1577 uint16_t average_cpu_power; 1578 uint16_t average_soc_power; 1579 uint16_t average_gfx_power; 1580 uint16_t average_core_power[8]; 1581 1582 /* Average clocks (unit: MHz) */ 1583 uint16_t average_gfxclk_frequency; 1584 uint16_t average_socclk_frequency; 1585 uint16_t average_uclk_frequency; 1586 uint16_t average_fclk_frequency; 1587 uint16_t average_vclk_frequency; 1588 uint16_t average_dclk_frequency; 1589 1590 /* Current clocks (unit: MHz) */ 1591 uint16_t current_gfxclk; 1592 uint16_t current_socclk; 1593 uint16_t current_uclk; 1594 uint16_t current_fclk; 1595 uint16_t current_vclk; 1596 uint16_t current_dclk; 1597 uint16_t current_coreclk[8]; 1598 uint16_t current_l3clk[2]; 1599 1600 /* Throttle status (ASIC dependent) */ 1601 uint32_t throttle_status; 1602 1603 /* Fans */ 1604 uint16_t fan_pwm; 1605 1606 uint16_t padding[3]; 1607 1608 /* Throttle status (ASIC independent) */ 1609 uint64_t indep_throttle_status; 1610 1611 /* Average Temperature (unit: centi-Celsius) */ 1612 uint16_t average_temperature_gfx; 1613 uint16_t average_temperature_soc; 1614 uint16_t average_temperature_core[8]; 1615 uint16_t average_temperature_l3[2]; 1616 1617 /* Power/Voltage (unit: mV) */ 1618 uint16_t average_cpu_voltage; 1619 uint16_t average_soc_voltage; 1620 uint16_t average_gfx_voltage; 1621 1622 /* Power/Current (unit: mA) */ 1623 uint16_t average_cpu_current; 1624 uint16_t average_soc_current; 1625 uint16_t average_gfx_current; 1626 }; 1627 1628 struct gpu_metrics_v3_0 { 1629 struct metrics_table_header common_header; 1630 1631 /* Temperature */ 1632 /* gfx temperature on APUs */ 1633 uint16_t temperature_gfx; 1634 /* soc temperature on APUs */ 1635 uint16_t temperature_soc; 1636 /* CPU core temperature on APUs */ 1637 uint16_t temperature_core[16]; 1638 /* skin temperature on APUs */ 1639 uint16_t temperature_skin; 1640 1641 /* Utilization */ 1642 /* time filtered GFX busy % [0-100] */ 1643 uint16_t average_gfx_activity; 1644 /* time filtered VCN busy % [0-100] */ 1645 uint16_t average_vcn_activity; 1646 /* time filtered IPU per-column busy % [0-100] */ 1647 uint16_t average_ipu_activity[8]; 1648 /* time filtered per-core C0 residency % [0-100]*/ 1649 uint16_t average_core_c0_activity[16]; 1650 /* time filtered DRAM read bandwidth [MB/sec] */ 1651 uint16_t average_dram_reads; 1652 /* time filtered DRAM write bandwidth [MB/sec] */ 1653 uint16_t average_dram_writes; 1654 /* time filtered IPU read bandwidth [MB/sec] */ 1655 uint16_t average_ipu_reads; 1656 /* time filtered IPU write bandwidth [MB/sec] */ 1657 uint16_t average_ipu_writes; 1658 1659 /* Driver attached timestamp (in ns) */ 1660 uint64_t system_clock_counter; 1661 1662 /* Power/Energy */ 1663 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1664 uint32_t average_socket_power; 1665 /* time filtered IPU power [mW] */ 1666 uint16_t average_ipu_power; 1667 /* time filtered APU power [mW] */ 1668 uint32_t average_apu_power; 1669 /* time filtered GFX power [mW] */ 1670 uint32_t average_gfx_power; 1671 /* time filtered dGPU power [mW] */ 1672 uint32_t average_dgpu_power; 1673 /* time filtered sum of core power across all cores in the socket [mW] */ 1674 uint32_t average_all_core_power; 1675 /* calculated core power [mW] */ 1676 uint16_t average_core_power[16]; 1677 /* time filtered total system power [mW] */ 1678 uint16_t average_sys_power; 1679 /* maximum IRM defined STAPM power limit [mW] */ 1680 uint16_t stapm_power_limit; 1681 /* time filtered STAPM power limit [mW] */ 1682 uint16_t current_stapm_power_limit; 1683 1684 /* time filtered clocks [MHz] */ 1685 uint16_t average_gfxclk_frequency; 1686 uint16_t average_socclk_frequency; 1687 uint16_t average_vpeclk_frequency; 1688 uint16_t average_ipuclk_frequency; 1689 uint16_t average_fclk_frequency; 1690 uint16_t average_vclk_frequency; 1691 uint16_t average_uclk_frequency; 1692 uint16_t average_mpipu_frequency; 1693 1694 /* Current clocks */ 1695 /* target core frequency [MHz] */ 1696 uint16_t current_coreclk[16]; 1697 /* CCLK frequency limit enforced on classic cores [MHz] */ 1698 uint16_t current_core_maxfreq; 1699 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1700 uint16_t current_gfx_maxfreq; 1701 1702 /* Throttle Residency (ASIC dependent) */ 1703 uint32_t throttle_residency_prochot; 1704 uint32_t throttle_residency_spl; 1705 uint32_t throttle_residency_fppt; 1706 uint32_t throttle_residency_sppt; 1707 uint32_t throttle_residency_thm_core; 1708 uint32_t throttle_residency_thm_gfx; 1709 uint32_t throttle_residency_thm_soc; 1710 1711 /* Metrics table alpha filter time constant [us] */ 1712 uint32_t time_filter_alphavalue; 1713 }; 1714 1715 struct amdgpu_pmmetrics_header { 1716 uint16_t structure_size; 1717 uint16_t pad; 1718 uint32_t mp1_ip_discovery_version; 1719 uint32_t pmfw_version; 1720 uint32_t pmmetrics_version; 1721 }; 1722 1723 struct amdgpu_pm_metrics { 1724 struct amdgpu_pmmetrics_header common_header; 1725 1726 uint8_t data[]; 1727 }; 1728 1729 enum amdgpu_vr_temp { 1730 AMDGPU_VDDCR_VDD0_TEMP, 1731 AMDGPU_VDDCR_VDD1_TEMP, 1732 AMDGPU_VDDCR_VDD2_TEMP, 1733 AMDGPU_VDDCR_VDD3_TEMP, 1734 AMDGPU_VDDCR_SOC_A_TEMP, 1735 AMDGPU_VDDCR_SOC_C_TEMP, 1736 AMDGPU_VDDCR_SOCIO_A_TEMP, 1737 AMDGPU_VDDCR_SOCIO_C_TEMP, 1738 AMDGPU_VDD_085_HBM_TEMP, 1739 AMDGPU_VDDCR_11_HBM_B_TEMP, 1740 AMDGPU_VDDCR_11_HBM_D_TEMP, 1741 AMDGPU_VDD_USR_TEMP, 1742 AMDGPU_VDDIO_11_E32_TEMP, 1743 AMDGPU_VR_MAX_TEMP_ENTRIES, 1744 }; 1745 1746 enum amdgpu_system_temp { 1747 AMDGPU_UBB_FPGA_TEMP, 1748 AMDGPU_UBB_FRONT_TEMP, 1749 AMDGPU_UBB_BACK_TEMP, 1750 AMDGPU_UBB_OAM7_TEMP, 1751 AMDGPU_UBB_IBC_TEMP, 1752 AMDGPU_UBB_UFPGA_TEMP, 1753 AMDGPU_UBB_OAM1_TEMP, 1754 AMDGPU_OAM_0_1_HSC_TEMP, 1755 AMDGPU_OAM_2_3_HSC_TEMP, 1756 AMDGPU_OAM_4_5_HSC_TEMP, 1757 AMDGPU_OAM_6_7_HSC_TEMP, 1758 AMDGPU_UBB_FPGA_0V72_VR_TEMP, 1759 AMDGPU_UBB_FPGA_3V3_VR_TEMP, 1760 AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP, 1761 AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP, 1762 AMDGPU_RETIMER_0_1_0V9_VR_TEMP, 1763 AMDGPU_RETIMER_4_5_0V9_VR_TEMP, 1764 AMDGPU_RETIMER_2_3_0V9_VR_TEMP, 1765 AMDGPU_RETIMER_6_7_0V9_VR_TEMP, 1766 AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP, 1767 AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP, 1768 AMDGPU_IBC_HSC_TEMP, 1769 AMDGPU_IBC_TEMP, 1770 AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32, 1771 }; 1772 1773 enum amdgpu_node_temp { 1774 AMDGPU_RETIMER_X_TEMP, 1775 AMDGPU_OAM_X_IBC_TEMP, 1776 AMDGPU_OAM_X_IBC_2_TEMP, 1777 AMDGPU_OAM_X_VDD18_VR_TEMP, 1778 AMDGPU_OAM_X_04_HBM_B_VR_TEMP, 1779 AMDGPU_OAM_X_04_HBM_D_VR_TEMP, 1780 AMDGPU_NODE_MAX_TEMP_ENTRIES = 12, 1781 }; 1782 1783 struct amdgpu_gpuboard_temp_metrics_v1_0 { 1784 struct metrics_table_header common_header; 1785 uint16_t label_version; 1786 uint16_t node_id; 1787 uint64_t accumulation_counter; 1788 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1789 uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES]; 1790 uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES]; 1791 }; 1792 1793 struct amdgpu_baseboard_temp_metrics_v1_0 { 1794 struct metrics_table_header common_header; 1795 uint16_t label_version; 1796 uint16_t node_id; 1797 uint64_t accumulation_counter; 1798 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1799 uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES]; 1800 }; 1801 1802 struct amdgpu_partition_metrics_v1_0 { 1803 struct metrics_table_header common_header; 1804 /* Current clocks (Mhz) */ 1805 uint16_t current_gfxclk[MAX_XCC]; 1806 uint16_t current_socclk[MAX_CLKS]; 1807 uint16_t current_vclk0[MAX_CLKS]; 1808 uint16_t current_dclk0[MAX_CLKS]; 1809 uint16_t current_uclk; 1810 uint16_t padding; 1811 1812 /* Utilization Instantaneous (%) */ 1813 uint32_t gfx_busy_inst[MAX_XCC]; 1814 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 1815 uint16_t vcn_busy[NUM_VCN]; 1816 /* Utilization Accumulated (%) */ 1817 uint64_t gfx_busy_acc[MAX_XCC]; 1818 /* Total App Clock Counter Accumulated */ 1819 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 1820 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 1821 uint64_t gfx_low_utilization_acc[MAX_XCC]; 1822 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 1823 }; 1824 1825 struct amdgpu_partition_metrics_v1_1 { 1826 struct metrics_table_header common_header; 1827 int attr_count; 1828 struct gpu_metrics_attr metrics_attrs[]; 1829 }; 1830 1831 #endif 1832